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* simops.c (OP_10007E0): Handle SYS_times and SYS_gettimeofday.
[deliverable/binutils-gdb.git] / sim / v850 / simops.c
1 #include <signal.h>
2 #include "v850_sim.h"
3 #include "simops.h"
4 #include "sys/syscall.h"
5 #include "bfd.h"
6 #include <errno.h>
7 #include <sys/stat.h>
8 #include <sys/times.h>
9
10 enum op_types {
11 OP_UNKNOWN,
12 OP_NONE,
13 OP_TRAP,
14 OP_REG,
15 OP_REG_REG,
16 OP_REG_REG_CMP,
17 OP_REG_REG_MOVE,
18 OP_IMM_REG,
19 OP_IMM_REG_CMP,
20 OP_IMM_REG_MOVE,
21 OP_COND_BR,
22 OP_LOAD16,
23 OP_STORE16,
24 OP_LOAD32,
25 OP_STORE32,
26 OP_JUMP,
27 OP_IMM_REG_REG,
28 OP_UIMM_REG_REG,
29 OP_BIT,
30 OP_EX1,
31 OP_EX2,
32 OP_LDSR,
33 OP_STSR
34 };
35
36 #ifdef DEBUG
37 static void trace_input PARAMS ((char *name, enum op_types type, int size));
38 static void trace_output PARAMS ((enum op_types result));
39 static int init_text_p = 0;
40 static asection *text;
41 static bfd_vma text_start;
42 static bfd_vma text_end;
43 extern bfd *exec_bfd;
44
45 #ifndef SIZE_INSTRUCTION
46 #define SIZE_INSTRUCTION 6
47 #endif
48
49 #ifndef SIZE_OPERANDS
50 #define SIZE_OPERANDS 16
51 #endif
52
53 #ifndef SIZE_VALUES
54 #define SIZE_VALUES 11
55 #endif
56
57 #ifndef SIZE_LOCATION
58 #define SIZE_LOCATION 40
59 #endif
60
61 static void
62 trace_input (name, type, size)
63 char *name;
64 enum op_types type;
65 int size;
66 {
67 char buf[1024];
68 char *p;
69 uint32 values[3];
70 int num_values, i;
71 char *cond;
72 asection *s;
73 const char *filename;
74 const char *functionname;
75 unsigned int linenumber;
76
77 if ((v850_debug & DEBUG_TRACE) == 0)
78 return;
79
80 buf[0] = '\0';
81 if (!init_text_p)
82 {
83 init_text_p = 1;
84 for (s = exec_bfd->sections; s; s = s->next)
85 if (strcmp (bfd_get_section_name (exec_bfd, s), ".text") == 0)
86 {
87 text = s;
88 text_start = bfd_get_section_vma (exec_bfd, s);
89 text_end = text_start + bfd_section_size (exec_bfd, s);
90 break;
91 }
92 }
93
94 if (text && PC >= text_start && PC < text_end)
95 {
96 filename = (const char *)0;
97 functionname = (const char *)0;
98 linenumber = 0;
99 if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, PC - text_start,
100 &filename, &functionname, &linenumber))
101 {
102 p = buf;
103 if (linenumber)
104 {
105 sprintf (p, "Line %5d ", linenumber);
106 p += strlen (p);
107 }
108
109 if (functionname)
110 {
111 sprintf (p, "Func %s ", functionname);
112 p += strlen (p);
113 }
114 else if (filename)
115 {
116 char *q = (char *) strrchr (filename, '/');
117 sprintf (p, "File %s ", (q) ? q+1 : filename);
118 p += strlen (p);
119 }
120
121 if (*p == ' ')
122 *p = '\0';
123 }
124 }
125
126 (*v850_callback->printf_filtered) (v850_callback, "0x%.8x: %-*.*s %-*s",
127 (unsigned)PC,
128 SIZE_LOCATION, SIZE_LOCATION, buf,
129 SIZE_INSTRUCTION, name);
130
131 switch (type)
132 {
133 default:
134 case OP_UNKNOWN:
135 case OP_NONE:
136 strcpy (buf, "unknown");
137 break;
138
139 case OP_TRAP:
140 sprintf (buf, "%d", OP[0]);
141 break;
142
143 case OP_REG:
144 sprintf (buf, "r%d", OP[0]);
145 break;
146
147 case OP_REG_REG:
148 case OP_REG_REG_CMP:
149 case OP_REG_REG_MOVE:
150 sprintf (buf, "r%d,r%d", OP[0], OP[1]);
151 break;
152
153 case OP_IMM_REG:
154 case OP_IMM_REG_CMP:
155 case OP_IMM_REG_MOVE:
156 sprintf (buf, "%d,r%d", OP[0], OP[1]);
157 break;
158
159 case OP_COND_BR:
160 sprintf (buf, "%d", SEXT9 (OP[0]));
161 break;
162
163 case OP_LOAD16:
164 sprintf (buf, "%d[r30],r%d", OP[1] * size, OP[0]);
165 break;
166
167 case OP_STORE16:
168 sprintf (buf, "r%d,%d[r30]", OP[0], OP[1] * size);
169 break;
170
171 case OP_LOAD32:
172 sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
173 break;
174
175 case OP_STORE32:
176 sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
177 break;
178
179 case OP_JUMP:
180 sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
181 break;
182
183 case OP_IMM_REG_REG:
184 sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
185 break;
186
187 case OP_UIMM_REG_REG:
188 sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
189 break;
190
191 case OP_BIT:
192 sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
193 break;
194
195 case OP_EX1:
196 switch (OP[0] & 0xf)
197 {
198 default: cond = "?"; break;
199 case 0x0: cond = "v"; break;
200 case 0x1: cond = "c"; break;
201 case 0x2: cond = "z"; break;
202 case 0x3: cond = "nh"; break;
203 case 0x4: cond = "s"; break;
204 case 0x5: cond = "t"; break;
205 case 0x6: cond = "lt"; break;
206 case 0x7: cond = "le"; break;
207 case 0x8: cond = "nv"; break;
208 case 0x9: cond = "nc"; break;
209 case 0xa: cond = "nz"; break;
210 case 0xb: cond = "h"; break;
211 case 0xc: cond = "ns"; break;
212 case 0xd: cond = "sa"; break;
213 case 0xe: cond = "ge"; break;
214 case 0xf: cond = "gt"; break;
215 }
216
217 sprintf (buf, "%s,r%d", cond, OP[1]);
218 break;
219
220 case OP_EX2:
221 strcpy (buf, "EX2");
222 break;
223
224 case OP_LDSR:
225 case OP_STSR:
226 sprintf (buf, "r%d,s%d", OP[0], OP[1]);
227 break;
228 }
229
230 if ((v850_debug & DEBUG_VALUES) == 0)
231 {
232 (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
233 }
234 else
235 {
236 (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
237 switch (type)
238 {
239 default:
240 case OP_UNKNOWN:
241 case OP_NONE:
242 case OP_TRAP:
243 num_values = 0;
244 break;
245
246 case OP_REG:
247 case OP_REG_REG_MOVE:
248 values[0] = State.regs[OP[0]];
249 num_values = 1;
250 break;
251
252 case OP_REG_REG:
253 case OP_REG_REG_CMP:
254 values[0] = State.regs[OP[1]];
255 values[1] = State.regs[OP[0]];
256 num_values = 2;
257 break;
258
259 case OP_IMM_REG:
260 case OP_IMM_REG_CMP:
261 values[0] = SEXT5 (OP[0]);
262 values[1] = OP[1];
263 num_values = 2;
264 break;
265
266 case OP_IMM_REG_MOVE:
267 values[0] = SEXT5 (OP[0]);
268 num_values = 1;
269 break;
270
271 case OP_COND_BR:
272 values[0] = State.pc;
273 values[1] = SEXT9 (OP[0]);
274 values[2] = State.sregs[5];
275 num_values = 3;
276 break;
277
278 case OP_LOAD16:
279 values[0] = OP[1] * size;
280 values[1] = State.regs[30];
281 num_values = 2;
282 break;
283
284 case OP_STORE16:
285 values[0] = State.regs[OP[0]];
286 values[1] = OP[1] * size;
287 values[2] = State.regs[30];
288 num_values = 3;
289 break;
290
291 case OP_LOAD32:
292 values[0] = SEXT16 (OP[2]);
293 values[1] = State.regs[OP[0]];
294 num_values = 2;
295 break;
296
297 case OP_STORE32:
298 values[0] = State.regs[OP[1]];
299 values[1] = SEXT16 (OP[2]);
300 values[2] = State.regs[OP[0]];
301 num_values = 3;
302 break;
303
304 case OP_JUMP:
305 values[0] = SEXT22 (OP[0]);
306 values[1] = State.pc;
307 num_values = 2;
308 break;
309
310 case OP_IMM_REG_REG:
311 values[0] = SEXT16 (OP[0]) << size;
312 values[1] = State.regs[OP[1]];
313 num_values = 2;
314 break;
315
316 case OP_UIMM_REG_REG:
317 values[0] = (OP[0] & 0xffff) << size;
318 values[1] = State.regs[OP[1]];
319 num_values = 2;
320 break;
321
322 case OP_BIT:
323 num_values = 0;
324 break;
325
326 case OP_EX1:
327 values[0] = State.sregs[5];
328 num_values = 1;
329 break;
330
331 case OP_EX2:
332 num_values = 0;
333 break;
334
335 case OP_LDSR:
336 values[0] = State.regs[OP[0]];
337 num_values = 1;
338 break;
339
340 case OP_STSR:
341 values[0] = State.sregs[OP[1]];
342 num_values = 1;
343 }
344
345 for (i = 0; i < num_values; i++)
346 (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
347
348 while (i++ < 3)
349 (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
350 }
351 }
352
353 static void
354 trace_output (result)
355 enum op_types result;
356 {
357 if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
358 {
359 switch (result)
360 {
361 default:
362 case OP_UNKNOWN:
363 case OP_NONE:
364 case OP_TRAP:
365 case OP_REG:
366 case OP_REG_REG_CMP:
367 case OP_IMM_REG_CMP:
368 case OP_COND_BR:
369 case OP_STORE16:
370 case OP_STORE32:
371 case OP_BIT:
372 case OP_EX2:
373 break;
374
375 case OP_LOAD16:
376 case OP_STSR:
377 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
378 (unsigned long)State.regs[OP[0]]);
379 break;
380
381 case OP_REG_REG:
382 case OP_REG_REG_MOVE:
383 case OP_IMM_REG:
384 case OP_IMM_REG_MOVE:
385 case OP_LOAD32:
386 case OP_EX1:
387 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
388 (unsigned long)State.regs[OP[1]]);
389 break;
390
391 case OP_IMM_REG_REG:
392 case OP_UIMM_REG_REG:
393 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
394 (unsigned long)State.regs[OP[2]]);
395 break;
396
397 case OP_JUMP:
398 if (OP[1] != 0)
399 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
400 (unsigned long)State.regs[OP[1]]);
401 break;
402
403 case OP_LDSR:
404 (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
405 (unsigned long)State.sregs[OP[1]]);
406 break;
407 }
408
409 (*v850_callback->printf_filtered) (v850_callback, "\n");
410 }
411 }
412
413 #else
414 #define trace_input(NAME, IN1, IN2)
415 #define trace_output(RESULT)
416 #endif
417
418 \f
419 /* sld.b */
420 void
421 OP_300 ()
422 {
423 unsigned int op2;
424 int result, temp;
425
426 trace_input ("sld.b", OP_LOAD16, 1);
427 temp = OP[1];
428 temp &= 0x7f;
429 op2 = temp;
430 result = load_mem (State.regs[30] + op2, 1);
431 State.regs[OP[0]] = SEXT8 (result);
432 trace_output (OP_LOAD16);
433 }
434
435 /* sld.h */
436 void
437 OP_400 ()
438 {
439 unsigned int op2;
440 int result, temp;
441
442 trace_input ("sld.h", OP_LOAD16, 2);
443 temp = OP[1];
444 temp &= 0x7f;
445 op2 = temp << 1;
446 result = load_mem (State.regs[30] + op2, 2);
447 State.regs[OP[0]] = SEXT16 (result);
448 trace_output (OP_LOAD16);
449 }
450
451 /* sld.w */
452 void
453 OP_500 ()
454 {
455 unsigned int op2;
456 int result, temp;
457
458 trace_input ("sld.w", OP_LOAD16, 4);
459 temp = OP[1];
460 temp &= 0x7e;
461 op2 = temp << 1;
462 result = load_mem (State.regs[30] + op2, 4);
463 State.regs[OP[0]] = result;
464 trace_output (OP_LOAD16);
465 }
466
467 /* sst.b */
468 void
469 OP_380 ()
470 {
471 unsigned int op0, op1;
472 int temp;
473
474 trace_input ("sst.b", OP_STORE16, 1);
475 op0 = State.regs[OP[0]];
476 temp = OP[1];
477 temp &= 0x7f;
478 op1 = temp;
479 store_mem (State.regs[30] + op1, 1, op0);
480 trace_output (OP_STORE16);
481 }
482
483 /* sst.h */
484 void
485 OP_480 ()
486 {
487 unsigned int op0, op1;
488 int temp;
489
490 trace_input ("sst.h", OP_STORE16, 2);
491 op0 = State.regs[OP[0]];
492 temp = OP[1];
493 temp &= 0x7f;
494 op1 = temp << 1;
495 store_mem (State.regs[30] + op1, 2, op0);
496 trace_output (OP_STORE16);
497 }
498
499 /* sst.w */
500 void
501 OP_501 ()
502 {
503 unsigned int op0, op1;
504 int temp;
505
506 trace_input ("sst.w", OP_STORE16, 4);
507 op0 = State.regs[OP[0]];
508 temp = OP[1];
509 temp &= 0x7e;
510 op1 = temp << 1;
511 store_mem (State.regs[30] + op1, 4, op0);
512 trace_output (OP_STORE16);
513 }
514
515 /* ld.b */
516 void
517 OP_700 ()
518 {
519 unsigned int op0, op2;
520 int result, temp;
521
522 trace_input ("ld.b", OP_LOAD32, 1);
523 op0 = State.regs[OP[0]];
524 temp = SEXT16 (OP[2]);
525 op2 = temp;
526 result = load_mem (op0 + op2, 1);
527 State.regs[OP[1]] = SEXT8 (result);
528 trace_output (OP_LOAD32);
529 }
530
531 /* ld.h */
532 void
533 OP_720 ()
534 {
535 unsigned int op0, op2;
536 int result, temp;
537
538 trace_input ("ld.h", OP_LOAD32, 2);
539 op0 = State.regs[OP[0]];
540 temp = SEXT16 (OP[2]);
541 temp &= ~0x1;
542 op2 = temp;
543 result = load_mem (op0 + op2, 2);
544 State.regs[OP[1]] = SEXT16 (result);
545 trace_output (OP_LOAD32);
546 }
547
548 /* ld.w */
549 void
550 OP_10720 ()
551 {
552 unsigned int op0, op2;
553 int result, temp;
554
555 trace_input ("ld.w", OP_LOAD32, 4);
556 op0 = State.regs[OP[0]];
557 temp = SEXT16 (OP[2]);
558 temp &= ~0x1;
559 op2 = temp;
560 result = load_mem (op0 + op2, 4);
561 State.regs[OP[1]] = result;
562 trace_output (OP_LOAD32);
563 }
564
565 /* st.b */
566 void
567 OP_740 ()
568 {
569 unsigned int op0, op1, op2;
570 int temp;
571
572 trace_input ("st.b", OP_STORE32, 1);
573 op0 = State.regs[OP[0]];
574 op1 = State.regs[OP[1]];
575 temp = SEXT16 (OP[2]);
576 op2 = temp;
577 store_mem (op0 + op2, 1, op1);
578 trace_output (OP_STORE32);
579 }
580
581 /* st.h */
582 void
583 OP_760 ()
584 {
585 unsigned int op0, op1, op2;
586 int temp;
587
588 trace_input ("st.h", OP_STORE32, 2);
589 op0 = State.regs[OP[0]];
590 op1 = State.regs[OP[1]];
591 temp = SEXT16 (OP[2] & ~0x1);
592 op2 = temp;
593 store_mem (op0 + op2, 2, op1);
594 trace_output (OP_STORE32);
595 }
596
597 /* st.w */
598 void
599 OP_10760 ()
600 {
601 unsigned int op0, op1, op2;
602 int temp;
603
604 trace_input ("st.w", OP_STORE32, 4);
605 op0 = State.regs[OP[0]];
606 op1 = State.regs[OP[1]];
607 temp = SEXT16 (OP[2] & ~0x1);
608 op2 = temp;
609 store_mem (op0 + op2, 4, op1);
610 trace_output (OP_STORE32);
611 }
612
613 /* bv disp9 */
614 void
615 OP_580 ()
616 {
617 unsigned int psw;
618 int op0;
619
620 trace_input ("bv", OP_COND_BR, 0);
621 op0 = SEXT9 (OP[0]);
622 psw = State.sregs[5];
623
624 if ((psw & PSW_OV) != 0)
625 State.pc += op0;
626 else
627 State.pc += 2;
628 trace_output (OP_COND_BR);
629 }
630
631 /* bl disp9 */
632 void
633 OP_581 ()
634 {
635 unsigned int psw;
636 int op0;
637
638 trace_input ("bl", OP_COND_BR, 0);
639 op0 = SEXT9 (OP[0]);
640 psw = State.sregs[5];
641
642 if ((psw & PSW_CY) != 0)
643 State.pc += op0;
644 else
645 State.pc += 2;
646 trace_output (OP_COND_BR);
647 }
648
649 /* be disp9 */
650 void
651 OP_582 ()
652 {
653 unsigned int psw;
654 int op0;
655
656 trace_input ("be", OP_COND_BR, 0);
657 op0 = SEXT9 (OP[0]);
658 psw = State.sregs[5];
659
660 if ((psw & PSW_Z) != 0)
661 State.pc += op0;
662 else
663 State.pc += 2;
664 trace_output (OP_COND_BR);
665 }
666
667 /* bnh disp 9*/
668 void
669 OP_583 ()
670 {
671 unsigned int psw;
672 int op0;
673
674 trace_input ("bnh", OP_COND_BR, 0);
675 op0 = SEXT9 (OP[0]);
676 psw = State.sregs[5];
677
678 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0)
679 State.pc += op0;
680 else
681 State.pc += 2;
682 trace_output (OP_COND_BR);
683 }
684
685 /* bn disp9 */
686 void
687 OP_584 ()
688 {
689 unsigned int psw;
690 int op0;
691
692 trace_input ("bn", OP_COND_BR, 0);
693 op0 = SEXT9 (OP[0]);
694 psw = State.sregs[5];
695
696 if ((psw & PSW_S) != 0)
697 State.pc += op0;
698 else
699 State.pc += 2;
700 trace_output (OP_COND_BR);
701 }
702
703 /* br disp9 */
704 void
705 OP_585 ()
706 {
707 unsigned int psw;
708 int op0;
709
710 trace_input ("br", OP_COND_BR, 0);
711 op0 = SEXT9 (OP[0]);
712 State.pc += op0;
713 trace_output (OP_COND_BR);
714 }
715
716 /* blt disp9 */
717 void
718 OP_586 ()
719 {
720 unsigned int psw;
721 int op0;
722
723 trace_input ("blt", OP_COND_BR, 0);
724 op0 = SEXT9 (OP[0]);
725 psw = State.sregs[5];
726
727 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0)
728 State.pc += op0;
729 else
730 State.pc += 2;
731 trace_output (OP_COND_BR);
732 }
733
734 /* ble disp9 */
735 void
736 OP_587 ()
737 {
738 unsigned int psw;
739 int op0;
740
741 trace_input ("ble", OP_COND_BR, 0);
742 op0 = SEXT9 (OP[0]);
743 psw = State.sregs[5];
744
745 if ((((psw & PSW_Z) != 0)
746 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) != 0)
747 State.pc += op0;
748 else
749 State.pc += 2;
750 trace_output (OP_COND_BR);
751 }
752
753 /* bnv disp9 */
754 void
755 OP_588 ()
756 {
757 unsigned int psw;
758 int op0;
759
760 trace_input ("bnv", OP_COND_BR, 0);
761 op0 = SEXT9 (OP[0]);
762 psw = State.sregs[5];
763
764 if ((psw & PSW_OV) == 0)
765 State.pc += op0;
766 else
767 State.pc += 2;
768 trace_output (OP_COND_BR);
769 }
770
771 /* bnl disp9 */
772 void
773 OP_589 ()
774 {
775 unsigned int psw;
776 int op0;
777
778 trace_input ("bnl", OP_COND_BR, 0);
779 op0 = SEXT9 (OP[0]);
780 psw = State.sregs[5];
781
782 if ((psw & PSW_CY) == 0)
783 State.pc += op0;
784 else
785 State.pc += 2;
786 trace_output (OP_COND_BR);
787 }
788
789 /* bne disp9 */
790 void
791 OP_58A ()
792 {
793 unsigned int psw;
794 int op0;
795
796 trace_input ("bne", OP_COND_BR, 0);
797 op0 = SEXT9 (OP[0]);
798 psw = State.sregs[5];
799
800 if ((psw & PSW_Z) == 0)
801 State.pc += op0;
802 else
803 State.pc += 2;
804 trace_output (OP_COND_BR);
805 }
806
807 /* bh disp9 */
808 void
809 OP_58B ()
810 {
811 unsigned int psw;
812 int op0;
813
814 trace_input ("bh", OP_COND_BR, 0);
815 op0 = SEXT9 (OP[0]);
816 psw = State.sregs[5];
817
818 if ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0)
819 State.pc += op0;
820 else
821 State.pc += 2;
822 trace_output (OP_COND_BR);
823 }
824
825 /* bp disp9 */
826 void
827 OP_58C ()
828 {
829 unsigned int psw;
830 int op0;
831
832 trace_input ("bp", OP_COND_BR, 0);
833 op0 = SEXT9 (OP[0]);
834 psw = State.sregs[5];
835
836 if ((psw & PSW_S) == 0)
837 State.pc += op0;
838 else
839 State.pc += 2;
840 trace_output (OP_COND_BR);
841 }
842
843 /* bsa disp9 */
844 void
845 OP_58D ()
846 {
847 unsigned int psw;
848 int op0;
849
850 trace_input ("bsa", OP_COND_BR, 0);
851 op0 = SEXT9 (OP[0]);
852 psw = State.sregs[5];
853
854 if ((psw & PSW_SAT) != 0)
855 State.pc += op0;
856 else
857 State.pc += 2;
858 trace_output (OP_COND_BR);
859 }
860
861 /* bge disp9 */
862 void
863 OP_58E ()
864 {
865 unsigned int psw;
866 int op0;
867
868 trace_input ("bge", OP_COND_BR, 0);
869 op0 = SEXT9 (OP[0]);
870 psw = State.sregs[5];
871
872 if ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0)
873 State.pc += op0;
874 else
875 State.pc += 2;
876 trace_output (OP_COND_BR);
877 }
878
879 /* bgt disp9 */
880 void
881 OP_58F ()
882 {
883 unsigned int psw;
884 int op0;
885
886 trace_input ("bgt", OP_COND_BR, 0);
887 op0 = SEXT9 (OP[0]);
888 psw = State.sregs[5];
889
890 if ((((psw & PSW_Z) != 0)
891 || (((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))) == 0)
892 State.pc += op0;
893 else
894 State.pc += 2;
895 trace_output (OP_COND_BR);
896 }
897
898 /* jmp [reg1] */
899 void
900 OP_60 ()
901 {
902 /* interp.c will bump this by +2, so correct for it here. */
903 trace_input ("jmp", OP_REG, 0);
904 State.pc = State.regs[OP[0]] - 2;
905 trace_output (OP_REG);
906 }
907
908 /* jarl disp22, reg */
909 void
910 OP_780 ()
911 {
912 unsigned int op0, opc;
913 int temp;
914
915 trace_input ("jarl", OP_JUMP, 0);
916 temp = SEXT22 (OP[0]);
917 op0 = temp;
918 opc = State.pc;
919
920 State.pc += temp;
921
922 /* Gross. jarl X,r0 is really jr and doesn't save its result. */
923 if (OP[1] != 0)
924 State.regs[OP[1]] = opc + 4;
925 trace_output (OP_JUMP);
926 }
927
928 /* add reg, reg */
929 void
930 OP_1C0 ()
931 {
932 unsigned int op0, op1, result, z, s, cy, ov;
933
934 trace_input ("add", OP_REG_REG, 0);
935 /* Compute the result. */
936 op0 = State.regs[OP[0]];
937 op1 = State.regs[OP[1]];
938 result = op0 + op1;
939
940 /* Compute the condition codes. */
941 z = (result == 0);
942 s = (result & 0x80000000);
943 cy = (result < op0 || result < op1);
944 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
945 && (op0 & 0x80000000) != (result & 0x80000000));
946
947 /* Store the result and condition codes. */
948 State.regs[OP[1]] = result;
949 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
950 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
951 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
952 trace_output (OP_REG_REG);
953 }
954
955 /* add sign_extend(imm5), reg */
956 void
957 OP_240 ()
958 {
959 unsigned int op0, op1, result, z, s, cy, ov;
960 int temp;
961
962 trace_input ("add", OP_IMM_REG, 0);
963
964 /* Compute the result. */
965 temp = SEXT5 (OP[0]);
966 op0 = temp;
967 op1 = State.regs[OP[1]];
968 result = op0 + op1;
969
970 /* Compute the condition codes. */
971 z = (result == 0);
972 s = (result & 0x80000000);
973 cy = (result < op0 || result < op1);
974 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
975 && (op0 & 0x80000000) != (result & 0x80000000));
976
977 /* Store the result and condition codes. */
978 State.regs[OP[1]] = result;
979 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
980 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
981 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
982 trace_output (OP_IMM_REG);
983 }
984
985 /* addi sign_extend(imm16), reg, reg */
986 void
987 OP_600 ()
988 {
989 unsigned int op0, op1, result, z, s, cy, ov;
990 int temp;
991
992 trace_input ("addi", OP_IMM_REG_REG, 0);
993
994 /* Compute the result. */
995 temp = SEXT16 (OP[0]);
996 op0 = temp;
997 op1 = State.regs[OP[1]];
998 result = op0 + op1;
999
1000 /* Compute the condition codes. */
1001 z = (result == 0);
1002 s = (result & 0x80000000);
1003 cy = (result < op0 || result < op1);
1004 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1005 && (op0 & 0x80000000) != (result & 0x80000000));
1006
1007 /* Store the result and condition codes. */
1008 State.regs[OP[2]] = result;
1009 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1010 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1011 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1012 trace_output (OP_IMM_REG_REG);
1013 }
1014
1015 /* sub reg1, reg2 */
1016 void
1017 OP_1A0 ()
1018 {
1019 unsigned int op0, op1, result, z, s, cy, ov;
1020
1021 trace_input ("sub", OP_REG_REG, 0);
1022 /* Compute the result. */
1023 op0 = State.regs[OP[0]];
1024 op1 = State.regs[OP[1]];
1025 result = op1 - op0;
1026
1027 /* Compute the condition codes. */
1028 z = (result == 0);
1029 s = (result & 0x80000000);
1030 cy = (op1 < op0);
1031 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1032 && (op1 & 0x80000000) != (result & 0x80000000));
1033
1034 /* Store the result and condition codes. */
1035 State.regs[OP[1]] = result;
1036 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1037 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1038 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1039 trace_output (OP_REG_REG);
1040 }
1041
1042 /* subr reg1, reg2 */
1043 void
1044 OP_180 ()
1045 {
1046 unsigned int op0, op1, result, z, s, cy, ov;
1047
1048 trace_input ("subr", OP_REG_REG, 0);
1049 /* Compute the result. */
1050 op0 = State.regs[OP[0]];
1051 op1 = State.regs[OP[1]];
1052 result = op0 - op1;
1053
1054 /* Compute the condition codes. */
1055 z = (result == 0);
1056 s = (result & 0x80000000);
1057 cy = (op0 < op1);
1058 ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
1059 && (op0 & 0x80000000) != (result & 0x80000000));
1060
1061 /* Store the result and condition codes. */
1062 State.regs[OP[1]] = result;
1063 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1064 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1065 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1066 trace_output (OP_REG_REG);
1067 }
1068
1069 /* mulh reg1, reg2 */
1070 void
1071 OP_E0 ()
1072 {
1073 trace_input ("mulh", OP_REG_REG, 0);
1074 State.regs[OP[1]] = ((State.regs[OP[1]] & 0xffff)
1075 * (State.regs[OP[0]] & 0xffff));
1076 trace_output (OP_REG_REG);
1077 }
1078
1079 /* mulh sign_extend(imm5), reg2
1080
1081 Condition codes */
1082 void
1083 OP_2E0 ()
1084 {
1085 int value = SEXT5 (OP[0]);
1086
1087 trace_input ("mulh", OP_IMM_REG, 0);
1088 State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
1089 trace_output (OP_IMM_REG);
1090 }
1091
1092 /* mulhi imm16, reg1, reg2 */
1093 void
1094 OP_6E0 ()
1095 {
1096 int value = OP[0] & 0xffff;
1097
1098 trace_input ("mulhi", OP_IMM_REG_REG, 0);
1099 State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
1100 trace_output (OP_IMM_REG_REG);
1101 }
1102
1103 /* divh reg1, reg2 */
1104 void
1105 OP_40 ()
1106 {
1107 unsigned int op0, op1, result, ov, s, z;
1108 int temp;
1109
1110 trace_input ("divh", OP_REG_REG, 0);
1111
1112 /* Compute the result. */
1113 temp = SEXT16 (State.regs[OP[0]]);
1114 op0 = temp;
1115 op1 = State.regs[OP[1]];
1116
1117 if (op0 == 0xffffffff && op1 == 0x80000000)
1118 {
1119 result = 0x80000000;
1120 ov = 1;
1121 }
1122 else if (op0 != 0)
1123 {
1124 result = op1 / op0;
1125 ov = 0;
1126 }
1127 else
1128 {
1129 result = 0x0;
1130 ov = 1;
1131 }
1132
1133 /* Compute the condition codes. */
1134 z = (result == 0);
1135 s = (result & 0x80000000);
1136
1137 /* Store the result and condition codes. */
1138 State.regs[OP[1]] = result;
1139 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1140 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1141 | (ov ? PSW_OV : 0));
1142 trace_output (OP_REG_REG);
1143 }
1144
1145 /* cmp reg, reg */
1146 void
1147 OP_1E0 ()
1148 {
1149 unsigned int op0, op1, result, z, s, cy, ov;
1150
1151 trace_input ("cmp", OP_REG_REG_CMP, 0);
1152 /* Compute the result. */
1153 op0 = State.regs[OP[0]];
1154 op1 = State.regs[OP[1]];
1155 result = op1 - op0;
1156
1157 /* Compute the condition codes. */
1158 z = (result == 0);
1159 s = (result & 0x80000000);
1160 cy = (op1 < op0);
1161 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1162 && (op1 & 0x80000000) != (result & 0x80000000));
1163
1164 /* Set condition codes. */
1165 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1166 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1167 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1168 trace_output (OP_REG_REG_CMP);
1169 }
1170
1171 /* cmp sign_extend(imm5), reg */
1172 void
1173 OP_260 ()
1174 {
1175 unsigned int op0, op1, result, z, s, cy, ov;
1176 int temp;
1177
1178 /* Compute the result. */
1179 trace_input ("cmp", OP_IMM_REG_CMP, 0);
1180 temp = SEXT5 (OP[0]);
1181 op0 = temp;
1182 op1 = State.regs[OP[1]];
1183 result = op1 - op0;
1184
1185 /* Compute the condition codes. */
1186 z = (result == 0);
1187 s = (result & 0x80000000);
1188 cy = (op1 < op0);
1189 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1190 && (op1 & 0x80000000) != (result & 0x80000000));
1191
1192 /* Set condition codes. */
1193 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1194 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1195 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
1196 trace_output (OP_IMM_REG_CMP);
1197 }
1198
1199 /* setf cccc,reg2 */
1200 void
1201 OP_7E0 ()
1202 {
1203 /* Hack alert. We turn off a bit in op0 since we really only
1204 wanted 4 bits. */
1205 unsigned int op0, psw, result = 0;
1206
1207 trace_input ("setf", OP_EX1, 0);
1208 op0 = OP[0] & 0xf;
1209 psw = State.sregs[5];
1210
1211 switch (op0)
1212 {
1213 case 0x0:
1214 result = ((psw & PSW_OV) != 0);
1215 break;
1216 case 0x1:
1217 result = ((psw & PSW_CY) != 0);
1218 break;
1219 case 0x2:
1220 result = ((psw & PSW_Z) != 0);
1221 break;
1222 case 0x3:
1223 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) != 0);
1224 break;
1225 case 0x4:
1226 result = ((psw & PSW_S) != 0);
1227 break;
1228 case 0x5:
1229 result = 1;
1230 break;
1231 case 0x6:
1232 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) != 0);
1233 break;
1234 case 0x7:
1235 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
1236 || ((psw & PSW_Z) != 0)) != 0);
1237 break;
1238 case 0x8:
1239 result = ((psw & PSW_OV) == 0);
1240 break;
1241 case 0x9:
1242 result = ((psw & PSW_CY) == 0);
1243 break;
1244 case 0xa:
1245 result = ((psw & PSW_Z) == 0);
1246 break;
1247 case 0xb:
1248 result = ((((psw & PSW_CY) != 0) | ((psw & PSW_Z) != 0)) == 0);
1249 break;
1250 case 0xc:
1251 result = ((psw & PSW_S) == 0);
1252 break;
1253 case 0xd:
1254 result = ((psw & PSW_SAT) != 0);
1255 break;
1256 case 0xe:
1257 result = ((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0)) == 0);
1258 break;
1259 case 0xf:
1260 result = (((((psw & PSW_S) != 0) ^ ((psw & PSW_OV) != 0))
1261 || ((psw & PSW_Z) != 0)) == 0);
1262 break;
1263 }
1264
1265 State.regs[OP[1]] = result;
1266 trace_output (OP_EX1);
1267 }
1268
1269 /* satadd reg,reg */
1270 void
1271 OP_C0 ()
1272 {
1273 unsigned int op0, op1, result, z, s, cy, ov, sat;
1274
1275 trace_input ("satadd", OP_REG_REG, 0);
1276 /* Compute the result. */
1277 op0 = State.regs[OP[0]];
1278 op1 = State.regs[OP[1]];
1279 result = op0 + op1;
1280
1281 /* Compute the condition codes. */
1282 z = (result == 0);
1283 s = (result & 0x80000000);
1284 cy = (result < op0 || result < op1);
1285 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1286 && (op0 & 0x80000000) != (result & 0x80000000));
1287 sat = ov;
1288
1289 /* Store the result and condition codes. */
1290 State.regs[OP[1]] = result;
1291 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1292 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1293 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1294 | (sat ? PSW_SAT : 0));
1295
1296 /* Handle saturated results. */
1297 if (sat && s)
1298 State.regs[OP[1]] = 0x80000000;
1299 else if (sat)
1300 State.regs[OP[1]] = 0x7fffffff;
1301 trace_output (OP_REG_REG);
1302 }
1303
1304 /* satadd sign_extend(imm5), reg */
1305 void
1306 OP_220 ()
1307 {
1308 unsigned int op0, op1, result, z, s, cy, ov, sat;
1309
1310 int temp;
1311
1312 trace_input ("satadd", OP_IMM_REG, 0);
1313
1314 /* Compute the result. */
1315 temp = SEXT5 (OP[0]);
1316 op0 = temp;
1317 op1 = State.regs[OP[1]];
1318 result = op0 + op1;
1319
1320 /* Compute the condition codes. */
1321 z = (result == 0);
1322 s = (result & 0x80000000);
1323 cy = (result < op0 || result < op1);
1324 ov = ((op0 & 0x80000000) == (op1 & 0x80000000)
1325 && (op0 & 0x80000000) != (result & 0x80000000));
1326 sat = ov;
1327
1328 /* Store the result and condition codes. */
1329 State.regs[OP[1]] = result;
1330 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1331 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1332 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1333 | (sat ? PSW_SAT : 0));
1334
1335 /* Handle saturated results. */
1336 if (sat && s)
1337 State.regs[OP[1]] = 0x80000000;
1338 else if (sat)
1339 State.regs[OP[1]] = 0x7fffffff;
1340 trace_output (OP_IMM_REG);
1341 }
1342
1343 /* satsub reg1, reg2 */
1344 void
1345 OP_A0 ()
1346 {
1347 unsigned int op0, op1, result, z, s, cy, ov, sat;
1348
1349 trace_input ("satsub", OP_REG_REG, 0);
1350
1351 /* Compute the result. */
1352 op0 = State.regs[OP[0]];
1353 op1 = State.regs[OP[1]];
1354 result = op1 - op0;
1355
1356 /* Compute the condition codes. */
1357 z = (result == 0);
1358 s = (result & 0x80000000);
1359 cy = (op1 < op0);
1360 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1361 && (op1 & 0x80000000) != (result & 0x80000000));
1362 sat = ov;
1363
1364 /* Store the result and condition codes. */
1365 State.regs[OP[1]] = result;
1366 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1367 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1368 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1369 | (sat ? PSW_SAT : 0));
1370
1371 /* Handle saturated results. */
1372 if (sat && s)
1373 State.regs[OP[1]] = 0x80000000;
1374 else if (sat)
1375 State.regs[OP[1]] = 0x7fffffff;
1376 trace_output (OP_REG_REG);
1377 }
1378
1379 /* satsubi sign_extend(imm16), reg */
1380 void
1381 OP_660 ()
1382 {
1383 unsigned int op0, op1, result, z, s, cy, ov, sat;
1384 int temp;
1385
1386 trace_input ("satsubi", OP_IMM_REG, 0);
1387
1388 /* Compute the result. */
1389 temp = SEXT16 (OP[0]);
1390 op0 = temp;
1391 op1 = State.regs[OP[1]];
1392 result = op1 - op0;
1393
1394 /* Compute the condition codes. */
1395 z = (result == 0);
1396 s = (result & 0x80000000);
1397 cy = (op1 < op0);
1398 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1399 && (op1 & 0x80000000) != (result & 0x80000000));
1400 sat = ov;
1401
1402 /* Store the result and condition codes. */
1403 State.regs[OP[1]] = result;
1404 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1405 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1406 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1407 | (sat ? PSW_SAT : 0));
1408
1409 /* Handle saturated results. */
1410 if (sat && s)
1411 State.regs[OP[1]] = 0x80000000;
1412 else if (sat)
1413 State.regs[OP[1]] = 0x7fffffff;
1414 trace_output (OP_IMM_REG);
1415 }
1416
1417 /* satsubr reg,reg */
1418 void
1419 OP_80 ()
1420 {
1421 unsigned int op0, op1, result, z, s, cy, ov, sat;
1422
1423 trace_input ("satsubr", OP_REG_REG, 0);
1424
1425 /* Compute the result. */
1426 op0 = State.regs[OP[0]];
1427 op1 = State.regs[OP[1]];
1428 result = op0 - op1;
1429
1430 /* Compute the condition codes. */
1431 z = (result == 0);
1432 s = (result & 0x80000000);
1433 cy = (result < op0);
1434 ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
1435 && (op1 & 0x80000000) != (result & 0x80000000));
1436 sat = ov;
1437
1438 /* Store the result and condition codes. */
1439 State.regs[OP[1]] = result;
1440 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
1441 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1442 | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)
1443 | (sat ? PSW_SAT : 0));
1444
1445 /* Handle saturated results. */
1446 if (sat && s)
1447 State.regs[OP[1]] = 0x80000000;
1448 else if (sat)
1449 State.regs[OP[1]] = 0x7fffffff;
1450 trace_output (OP_REG_REG);
1451 }
1452
1453 /* tst reg,reg */
1454 void
1455 OP_160 ()
1456 {
1457 unsigned int op0, op1, result, z, s;
1458
1459 trace_input ("tst", OP_REG_REG_CMP, 0);
1460
1461 /* Compute the result. */
1462 op0 = State.regs[OP[0]];
1463 op1 = State.regs[OP[1]];
1464 result = op0 & op1;
1465
1466 /* Compute the condition codes. */
1467 z = (result == 0);
1468 s = (result & 0x80000000);
1469
1470 /* Store the condition codes. */
1471 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1472 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1473 trace_output (OP_REG_REG_CMP);
1474 }
1475
1476 /* mov reg, reg */
1477 void
1478 OP_0 ()
1479 {
1480 trace_input ("mov", OP_REG_REG_MOVE, 0);
1481 State.regs[OP[1]] = State.regs[OP[0]];
1482 trace_output (OP_REG_REG_MOVE);
1483 }
1484
1485 /* mov sign_extend(imm5), reg */
1486 void
1487 OP_200 ()
1488 {
1489 int value = SEXT5 (OP[0]);
1490
1491 trace_input ("mov", OP_IMM_REG_MOVE, 0);
1492 State.regs[OP[1]] = value;
1493 trace_output (OP_IMM_REG_MOVE);
1494 }
1495
1496 /* movea sign_extend(imm16), reg, reg */
1497
1498 void
1499 OP_620 ()
1500 {
1501 int value = SEXT16 (OP[0]);
1502
1503 trace_input ("movea", OP_IMM_REG_REG, 0);
1504 State.regs[OP[2]] = State.regs[OP[1]] + value;
1505 trace_output (OP_IMM_REG_REG);
1506 }
1507
1508 /* movhi imm16, reg, reg */
1509 void
1510 OP_640 ()
1511 {
1512 uint32 value = (OP[0] & 0xffff) << 16;
1513
1514 trace_input ("movhi", OP_UIMM_REG_REG, 16);
1515 State.regs[OP[2]] = State.regs[OP[1]] + value;
1516 trace_output (OP_UIMM_REG_REG);
1517 }
1518
1519 /* sar zero_extend(imm5),reg1 */
1520 void
1521 OP_2A0 ()
1522 {
1523 unsigned int op0, op1, result, z, s, cy;
1524
1525 trace_input ("sar", OP_IMM_REG, 0);
1526 op0 = OP[0] & 0x1f;
1527 op1 = State.regs[OP[1]];
1528 result = (signed)op1 >> op0;
1529
1530 /* Compute the condition codes. */
1531 z = (result == 0);
1532 s = (result & 0x80000000);
1533 cy = (op1 & (1 << (op0 - 1)));
1534
1535 /* Store the result and condition codes. */
1536 State.regs[OP[1]] = result;
1537 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1538 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1539 | (cy ? PSW_CY : 0));
1540 trace_output (OP_IMM_REG);
1541 }
1542
1543 /* sar reg1, reg2 */
1544 void
1545 OP_A007E0 ()
1546 {
1547 unsigned int op0, op1, result, z, s, cy;
1548
1549 trace_input ("sar", OP_REG_REG, 0);
1550 op0 = State.regs[OP[0]] & 0x1f;
1551 op1 = State.regs[OP[1]];
1552 result = (signed)op1 >> op0;
1553
1554 /* Compute the condition codes. */
1555 z = (result == 0);
1556 s = (result & 0x80000000);
1557 cy = (op1 & (1 << (op0 - 1)));
1558
1559 /* Store the result and condition codes. */
1560 State.regs[OP[1]] = result;
1561 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1562 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1563 | (cy ? PSW_CY : 0));
1564 trace_output (OP_REG_REG);
1565 }
1566
1567 /* shl zero_extend(imm5),reg1 */
1568 void
1569 OP_2C0 ()
1570 {
1571 unsigned int op0, op1, result, z, s, cy;
1572
1573 trace_input ("shl", OP_IMM_REG, 0);
1574 op0 = OP[0] & 0x1f;
1575 op1 = State.regs[OP[1]];
1576 result = op1 << op0;
1577
1578 /* Compute the condition codes. */
1579 z = (result == 0);
1580 s = (result & 0x80000000);
1581 cy = (op1 & (1 << (32 - op0)));
1582
1583 /* Store the result and condition codes. */
1584 State.regs[OP[1]] = result;
1585 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1586 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1587 | (cy ? PSW_CY : 0));
1588 trace_output (OP_IMM_REG);
1589 }
1590
1591 /* shl reg1, reg2 */
1592 void
1593 OP_C007E0 ()
1594 {
1595 unsigned int op0, op1, result, z, s, cy;
1596
1597 trace_input ("shl", OP_REG_REG, 0);
1598 op0 = State.regs[OP[0]] & 0x1f;
1599 op1 = State.regs[OP[1]];
1600 result = op1 << op0;
1601
1602 /* Compute the condition codes. */
1603 z = (result == 0);
1604 s = (result & 0x80000000);
1605 cy = (op1 & (1 << (32 - op0)));
1606
1607 /* Store the result and condition codes. */
1608 State.regs[OP[1]] = result;
1609 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1610 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1611 | (cy ? PSW_CY : 0));
1612 trace_output (OP_REG_REG);
1613 }
1614
1615 /* shr zero_extend(imm5),reg1 */
1616 void
1617 OP_280 ()
1618 {
1619 unsigned int op0, op1, result, z, s, cy;
1620
1621 trace_input ("shr", OP_IMM_REG, 0);
1622 op0 = OP[0] & 0x1f;
1623 op1 = State.regs[OP[1]];
1624 result = op1 >> op0;
1625
1626 /* Compute the condition codes. */
1627 z = (result == 0);
1628 s = (result & 0x80000000);
1629 cy = (op1 & (1 << (op0 - 1)));
1630
1631 /* Store the result and condition codes. */
1632 State.regs[OP[1]] = result;
1633 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1634 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1635 | (cy ? PSW_CY : 0));
1636 trace_output (OP_IMM_REG);
1637 }
1638
1639 /* shr reg1, reg2 */
1640 void
1641 OP_8007E0 ()
1642 {
1643 unsigned int op0, op1, result, z, s, cy;
1644
1645 trace_input ("shr", OP_REG_REG, 0);
1646 op0 = State.regs[OP[0]] & 0x1f;
1647 op1 = State.regs[OP[1]];
1648 result = op1 >> op0;
1649
1650 /* Compute the condition codes. */
1651 z = (result == 0);
1652 s = (result & 0x80000000);
1653 cy = (op1 & (1 << (op0 - 1)));
1654
1655 /* Store the result and condition codes. */
1656 State.regs[OP[1]] = result;
1657 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV | PSW_CY);
1658 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
1659 | (cy ? PSW_CY : 0));
1660 trace_output (OP_REG_REG);
1661 }
1662
1663 /* or reg, reg */
1664 void
1665 OP_100 ()
1666 {
1667 unsigned int op0, op1, result, z, s;
1668
1669 trace_input ("or", OP_REG_REG, 0);
1670
1671 /* Compute the result. */
1672 op0 = State.regs[OP[0]];
1673 op1 = State.regs[OP[1]];
1674 result = op0 | op1;
1675
1676 /* Compute the condition codes. */
1677 z = (result == 0);
1678 s = (result & 0x80000000);
1679
1680 /* Store the result and condition codes. */
1681 State.regs[OP[1]] = result;
1682 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1683 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1684 trace_output (OP_REG_REG);
1685 }
1686
1687 /* ori zero_extend(imm16), reg, reg */
1688 void
1689 OP_680 ()
1690 {
1691 unsigned int op0, op1, result, z, s;
1692
1693 trace_input ("ori", OP_UIMM_REG_REG, 0);
1694 op0 = OP[0] & 0xffff;
1695 op1 = State.regs[OP[1]];
1696 result = op0 | op1;
1697
1698 /* Compute the condition codes. */
1699 z = (result == 0);
1700 s = (result & 0x80000000);
1701
1702 /* Store the result and condition codes. */
1703 State.regs[OP[2]] = result;
1704 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1705 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1706 trace_output (OP_UIMM_REG_REG);
1707 }
1708
1709 /* and reg, reg */
1710 void
1711 OP_140 ()
1712 {
1713 unsigned int op0, op1, result, z, s;
1714
1715 trace_input ("and", OP_REG_REG, 0);
1716
1717 /* Compute the result. */
1718 op0 = State.regs[OP[0]];
1719 op1 = State.regs[OP[1]];
1720 result = op0 & op1;
1721
1722 /* Compute the condition codes. */
1723 z = (result == 0);
1724 s = (result & 0x80000000);
1725
1726 /* Store the result and condition codes. */
1727 State.regs[OP[1]] = result;
1728 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1729 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1730 trace_output (OP_REG_REG);
1731 }
1732
1733 /* andi zero_extend(imm16), reg, reg */
1734 void
1735 OP_6C0 ()
1736 {
1737 unsigned int op0, op1, result, z;
1738
1739 trace_input ("andi", OP_UIMM_REG_REG, 0);
1740 op0 = OP[0] & 0xffff;
1741 op1 = State.regs[OP[1]];
1742 result = op0 & op1;
1743
1744 /* Compute the condition codes. */
1745 z = (result == 0);
1746
1747 /* Store the result and condition codes. */
1748 State.regs[OP[2]] = result;
1749 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1750 State.sregs[5] |= (z ? PSW_Z : 0);
1751 trace_output (OP_UIMM_REG_REG);
1752 }
1753
1754 /* xor reg, reg */
1755 void
1756 OP_120 ()
1757 {
1758 unsigned int op0, op1, result, z, s;
1759
1760 trace_input ("xor", OP_REG_REG, 0);
1761
1762 /* Compute the result. */
1763 op0 = State.regs[OP[0]];
1764 op1 = State.regs[OP[1]];
1765 result = op0 ^ op1;
1766
1767 /* Compute the condition codes. */
1768 z = (result == 0);
1769 s = (result & 0x80000000);
1770
1771 /* Store the result and condition codes. */
1772 State.regs[OP[1]] = result;
1773 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1774 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1775 trace_output (OP_REG_REG);
1776 }
1777
1778 /* xori zero_extend(imm16), reg, reg */
1779 void
1780 OP_6A0 ()
1781 {
1782 unsigned int op0, op1, result, z, s;
1783
1784 trace_input ("xori", OP_UIMM_REG_REG, 0);
1785 op0 = OP[0] & 0xffff;
1786 op1 = State.regs[OP[1]];
1787 result = op0 ^ op1;
1788
1789 /* Compute the condition codes. */
1790 z = (result == 0);
1791 s = (result & 0x80000000);
1792
1793 /* Store the result and condition codes. */
1794 State.regs[OP[2]] = result;
1795 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1796 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1797 trace_output (OP_UIMM_REG_REG);
1798 }
1799
1800 /* not reg1, reg2 */
1801 void
1802 OP_20 ()
1803 {
1804 unsigned int op0, result, z, s;
1805
1806 trace_input ("not", OP_REG_REG_MOVE, 0);
1807 /* Compute the result. */
1808 op0 = State.regs[OP[0]];
1809 result = ~op0;
1810
1811 /* Compute the condition codes. */
1812 z = (result == 0);
1813 s = (result & 0x80000000);
1814
1815 /* Store the result and condition codes. */
1816 State.regs[OP[1]] = result;
1817 State.sregs[5] &= ~(PSW_Z | PSW_S | PSW_OV);
1818 State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0));
1819 trace_output (OP_REG_REG_MOVE);
1820 }
1821
1822 /* set1 */
1823 void
1824 OP_7C0 ()
1825 {
1826 unsigned int op0, op1, op2;
1827 int temp;
1828
1829 trace_input ("set1", OP_BIT, 0);
1830 op0 = State.regs[OP[0]];
1831 op1 = OP[1] & 0x7;
1832 temp = SEXT16 (OP[2]);
1833 op2 = temp;
1834 temp = load_mem (op0 + op2, 1);
1835 State.sregs[5] &= ~PSW_Z;
1836 if ((temp & (1 << op1)) == 0)
1837 State.sregs[5] |= PSW_Z;
1838 temp |= (1 << op1);
1839 store_mem (op0 + op2, 1, temp);
1840 trace_output (OP_BIT);
1841 }
1842
1843 /* not1 */
1844 void
1845 OP_47C0 ()
1846 {
1847 unsigned int op0, op1, op2;
1848 int temp;
1849
1850 trace_input ("not1", OP_BIT, 0);
1851 op0 = State.regs[OP[0]];
1852 op1 = OP[1] & 0x7;
1853 temp = SEXT16 (OP[2]);
1854 op2 = temp;
1855 temp = load_mem (op0 + op2, 1);
1856 State.sregs[5] &= ~PSW_Z;
1857 if ((temp & (1 << op1)) == 0)
1858 State.sregs[5] |= PSW_Z;
1859 temp ^= (1 << op1);
1860 store_mem (op0 + op2, 1, temp);
1861 trace_output (OP_BIT);
1862 }
1863
1864 /* clr1 */
1865 void
1866 OP_87C0 ()
1867 {
1868 unsigned int op0, op1, op2;
1869 int temp;
1870
1871 trace_input ("clr1", OP_BIT, 0);
1872 op0 = State.regs[OP[0]];
1873 op1 = OP[1] & 0x7;
1874 temp = SEXT16 (OP[2]);
1875 op2 = temp;
1876 temp = load_mem (op0 + op2, 1);
1877 State.sregs[5] &= ~PSW_Z;
1878 if ((temp & (1 << op1)) == 0)
1879 State.sregs[5] |= PSW_Z;
1880 temp &= ~(1 << op1);
1881 store_mem (op0 + op2, 1, temp);
1882 trace_output (OP_BIT);
1883 }
1884
1885 /* tst1 */
1886 void
1887 OP_C7C0 ()
1888 {
1889 unsigned int op0, op1, op2;
1890 int temp;
1891
1892 trace_input ("tst1", OP_BIT, 0);
1893 op0 = State.regs[OP[0]];
1894 op1 = OP[1] & 0x7;
1895 temp = SEXT16 (OP[2]);
1896 op2 = temp;
1897 temp = load_mem (op0 + op2, 1);
1898 State.sregs[5] &= ~PSW_Z;
1899 if ((temp & (1 << op1)) == 0)
1900 State.sregs[5] |= PSW_Z;
1901 trace_output (OP_BIT);
1902 }
1903
1904 /* breakpoint */
1905 void
1906 OP_FFFF ()
1907 {
1908 State.exception = SIGTRAP;
1909 PC -= 4;
1910 }
1911
1912 /* di */
1913 void
1914 OP_16007E0 ()
1915 {
1916 trace_input ("di", OP_NONE, 0);
1917 State.sregs[5] |= PSW_ID;
1918 trace_output (OP_NONE);
1919 }
1920
1921 /* ei */
1922 void
1923 OP_16087E0 ()
1924 {
1925 trace_input ("ei", OP_NONE, 0);
1926 State.sregs[5] &= ~PSW_ID;
1927 trace_output (OP_NONE);
1928 }
1929
1930 /* halt, not supported */
1931 void
1932 OP_12007E0 ()
1933 {
1934 trace_input ("halt", OP_NONE, 0);
1935 State.exception = SIGQUIT;
1936 trace_output (OP_NONE);
1937 }
1938
1939 /* reti, not supported */
1940 void
1941 OP_14007E0 ()
1942 {
1943 trace_input ("reti", OP_NONE, 0);
1944 trace_output (OP_NONE);
1945
1946 if ((State.sregs[5] & (PSW_NP | PSW_EP)) == PSW_NP)
1947 { /* Only NP is on */
1948 PC = State.sregs[2] - 4; /* FEPC */
1949 State.sregs[5] = State.sregs[3]; /* FEPSW */
1950 }
1951 else
1952 {
1953 PC = State.sregs[0] - 4; /* EIPC */
1954 State.sregs[5] = State.sregs[1]; /* EIPSW */
1955 }
1956 }
1957
1958 /* trap, not supportd */
1959 void
1960 OP_10007E0 ()
1961 {
1962 trace_input ("trap", OP_TRAP, 0);
1963 trace_output (OP_TRAP);
1964
1965 /* Trap 31 is used for simulating OS I/O functions */
1966
1967 if (OP[0] == 31)
1968 {
1969 int save_errno = errno;
1970 errno = 0;
1971
1972 /* Registers passed to trap 0 */
1973
1974 #define FUNC State.regs[6] /* function number, return value */
1975 #define PARM1 State.regs[7] /* optional parm 1 */
1976 #define PARM2 State.regs[8] /* optional parm 2 */
1977 #define PARM3 State.regs[9] /* optional parm 3 */
1978
1979 /* Registers set by trap 0 */
1980
1981 #define RETVAL State.regs[10] /* return value */
1982 #define RETERR State.regs[11] /* return error code */
1983
1984 /* Turn a pointer in a register into a pointer into real memory. */
1985
1986 #define MEMPTR(x) (map (x))
1987
1988 switch (FUNC)
1989 {
1990 #if !defined(__GO32__) && !defined(_WIN32)
1991 case SYS_fork:
1992 RETVAL = fork ();
1993 break;
1994 case SYS_execve:
1995 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
1996 (char **)MEMPTR (PARM3));
1997 break;
1998 case SYS_execv:
1999 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2000 break;
2001 #if 0
2002 case SYS_pipe:
2003 {
2004 reg_t buf;
2005 int host_fd[2];
2006
2007 buf = PARM1;
2008 RETVAL = pipe (host_fd);
2009 SW (buf, host_fd[0]);
2010 buf += sizeof(uint16);
2011 SW (buf, host_fd[1]);
2012 }
2013 break;
2014
2015 case SYS_wait:
2016 {
2017 int status;
2018
2019 RETVAL = wait (&status);
2020 SW (PARM1, status);
2021 }
2022 break;
2023 #endif
2024 #endif
2025
2026 case SYS_read:
2027 RETVAL = v850_callback->read (v850_callback, PARM1, MEMPTR (PARM2),
2028 PARM3);
2029 break;
2030 case SYS_write:
2031 if (PARM1 == 1)
2032 RETVAL = (int)v850_callback->write_stdout (v850_callback,
2033 MEMPTR (PARM2), PARM3);
2034 else
2035 RETVAL = (int)v850_callback->write (v850_callback, PARM1,
2036 MEMPTR (PARM2), PARM3);
2037 break;
2038 case SYS_lseek:
2039 RETVAL = v850_callback->lseek (v850_callback, PARM1, PARM2, PARM3);
2040 break;
2041 case SYS_close:
2042 RETVAL = v850_callback->close (v850_callback, PARM1);
2043 break;
2044 case SYS_open:
2045 RETVAL = v850_callback->open (v850_callback, MEMPTR (PARM1), PARM2);
2046 break;
2047 case SYS_exit:
2048 /* EXIT - caller can look in PARM1 to work out the
2049 reason */
2050 if (PARM1 == 0xdead || PARM1 == 0x1)
2051 State.exception = SIGABRT;
2052 else
2053 State.exception = SIGQUIT;
2054 break;
2055
2056 case SYS_stat: /* added at hmsi */
2057 /* stat system call */
2058 {
2059 struct stat host_stat;
2060 reg_t buf;
2061
2062 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2063
2064 buf = PARM2;
2065
2066 /* Just wild-assed guesses. */
2067 store_mem (buf, 2, host_stat.st_dev);
2068 store_mem (buf + 2, 2, host_stat.st_ino);
2069 store_mem (buf + 4, 4, host_stat.st_mode);
2070 store_mem (buf + 8, 2, host_stat.st_nlink);
2071 store_mem (buf + 10, 2, host_stat.st_uid);
2072 store_mem (buf + 12, 2, host_stat.st_gid);
2073 store_mem (buf + 14, 2, host_stat.st_rdev);
2074 store_mem (buf + 16, 4, host_stat.st_size);
2075 store_mem (buf + 20, 4, host_stat.st_atime);
2076 store_mem (buf + 28, 4, host_stat.st_mtime);
2077 store_mem (buf + 36, 4, host_stat.st_ctime);
2078 }
2079 break;
2080
2081 case SYS_chown:
2082 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2083 break;
2084 case SYS_chmod:
2085 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2086 break;
2087 case SYS_time:
2088 RETVAL = time (MEMPTR (PARM1));
2089 break;
2090 case SYS_times:
2091 {
2092 struct tms tms;
2093 RETVAL = times (&tms);
2094 store_mem (PARM1, 4, tms.tms_utime);
2095 store_mem (PARM1 + 4, 4, tms.tms_stime);
2096 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2097 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2098 break;
2099 }
2100 case SYS_gettimeofday:
2101 {
2102 struct timeval t;
2103 struct timezone tz;
2104 RETVAL = gettimeofday (&t, &tz);
2105 store_mem (PARM1, 4, t.tv_sec);
2106 store_mem (PARM1 + 4, 4, t.tv_usec);
2107 store_mem (PARM2, 4, tz.tz_minuteswest);
2108 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2109 break;
2110 }
2111 case SYS_utime:
2112 /* Cast the second argument to void *, to avoid type mismatch
2113 if a prototype is present. */
2114 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2115 break;
2116 default:
2117 abort ();
2118 }
2119 RETERR = errno;
2120 errno = save_errno;
2121 }
2122 else
2123 { /* Trap 0 -> 30 */
2124 State.sregs[0] = PC + 4; /* EIPC */
2125 State.sregs[1] = State.sregs[5]; /* EIPSW */
2126 State.sregs[4] &= 0xffff0000; /* Mask out EICC */
2127 State.sregs[4] |= 0x40 + OP[0]; /* EICC */
2128 State.sregs[5] |= PSW_EP | PSW_ID; /* Now doing exception processing */
2129 PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
2130 }
2131 }
2132
2133 /* ldsr, reg,reg */
2134 void
2135 OP_2007E0 ()
2136 {
2137 unsigned int op0;
2138
2139 trace_input ("ldsr", OP_LDSR, 0);
2140 op0 = State.regs[OP[0]];
2141 State.sregs[OP[1]] = op0;
2142 trace_output (OP_LDSR);
2143 }
2144
2145 /* stsr, not supported */
2146 void
2147 OP_4007E0 ()
2148 {
2149 unsigned int op0;
2150
2151 trace_input ("stsr", OP_STSR, 0);
2152 op0 = State.sregs[OP[1]];
2153 State.regs[OP[0]] = op0;
2154 trace_output (OP_STSR);
2155 }
GDB Binutils - Deliverables
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