sim/v850/v850.igen

   1 :option::insn-bit-size:16
   2 :option::hi-bit-nr:15
   3
   4
   5 :option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
   6 # start-sanitize-v850e
   7 :option::format-names:XI,XII,XIII
   8 # end-sanitize-v850e
   9 # start-sanitize-v850eq
  10 :option::format-names:XIV,XV
  11 # end-sanitize-v850eq
  12 :option::format-names:Z
  13
  14
  15 :model::v850:v850:
  16
  17 # start-sanitize-v850e
  18 :option::multi-sim:true
  19 :model::v850e:v850e:
  20 # end-sanitize-v850e
  21
  22 # start-sanitize-v850eq
  23 :option::multi-sim:true
  24 :model::v850eq:v850eq:
  25 # end-sanitize-v850eq
  26
  27
  28
  29 // Cache macros
  30
  31 :cache::unsigned:reg1:RRRRR:(RRRRR)
  32 :cache::unsigned:reg2:rrrrr:(rrrrr)
  33 :cache::unsigned:reg3:wwwww:(wwwww)
  34 :cache::unsigned:regID:rrrrr:(rrrrr)
  35
  36 :cache::unsigned:disp4:dddd:(dddd)
  37 # start-sanitize-v850e
  38 :cache::unsigned:disp5:dddd:(dddd << 1)
  39 # end-sanitize-v850e
  40 :cache::unsigned:disp7:ddddddd:ddddddd
  41 :cache::unsigned:disp8:ddddddd:(ddddddd << 1)
  42 :cache::unsigned:disp8:dddddd:(dddddd << 2)
  43 :cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
  44 :cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
  45 :cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
  46 :cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
  47 :cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
  48
  49 :cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
  50 :cache::unsigned:imm6:iiiiii:iiiiii
  51 :cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
  52 # start-sanitize-v850eq
  53 :cache::unsigned:imm5:iiii:(32 - (iiii << 1))
  54 # end-sanitize-v850eq
  55 :cache::unsigned:imm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  56 :cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
  57 # start-sanitize-v850e
  58 :cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
  59 :cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
  60 # end-sanitize-v850e
  61
  62 :cache::unsigned:vector:iiiii:iiiii
  63
  64 # start-sanitize-v850e
  65 :cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
  66 :cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
  67 # end-sanitize-v850e
  68
  69 :cache::unsigned:bit3:bbb:bbb
  70
  71
  72 // What do we do with an illegal instruction?
  73 :internal:::illegal
  74 {
  75   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  76                   (unsigned long) cia);
  77   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
  78 }
  79
  80
  81
  82 // Add
  83
  84 rrrrr,001110,RRRRR:I:::add
  85 "add r<reg1>, r<reg2>"
  86 {
  87   COMPAT_1 (OP_1C0 ());
  88 }
  89
  90 rrrrr,010010,iiiii:II:::add
  91 "add <imm5>,r<reg2>"
  92 {
  93   COMPAT_1 (OP_240 ());
  94 }
  95
  96
  97
  98 // ADDI
  99 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
 100 "addi <imm16>, r<reg1>, r<reg2>"
 101 {
 102   COMPAT_2 (OP_600 ());
 103 }
 104
 105
 106
 107 // AND
 108 rrrrr,001010,RRRRR:I:::and
 109 "and r<reg1>, r<reg2>"
 110 {
 111   COMPAT_1 (OP_140 ());
 112 }
 113
 114
 115
 116 // ANDI
 117 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
 118 "andi <imm16>, r<reg1>, r<reg2>"
 119 {
 120   COMPAT_2 (OP_6C0 ());
 121 }
 122
 123
 124
 125 // Bcond
 126 // ddddd,1011,ddd,cccc:III:::Bcond
 127 // "b<cond> disp9"
 128
 129 ddddd,1011,ddd,0000:III:::bv
 130 "bv <disp9>"
 131 {
 132   COMPAT_1 (OP_580 ());
 133 }
 134
 135 ddddd,1011,ddd,0001:III:::bl
 136 "bl <disp9>"
 137 {
 138   COMPAT_1 (OP_581 ());
 139 }
 140
 141 ddddd,1011,ddd,0010:III:::be
 142 "be <disp9>"
 143 {
 144   COMPAT_1 (OP_582 ());
 145 }
 146
 147 ddddd,1011,ddd,0011:III:::bnh
 148 "bnh <disp9>"
 149 {
 150   COMPAT_1 (OP_583 ());
 151 }
 152
 153 ddddd,1011,ddd,0100:III:::bn
 154 "bn <disp9>"
 155 {
 156   COMPAT_1 (OP_584 ());
 157 }
 158
 159 ddddd,1011,ddd,0101:III:::br
 160 "br <disp9>"
 161 {
 162   COMPAT_1 (OP_585 ());
 163 }
 164
 165 ddddd,1011,ddd,0110:III:::blt
 166 "blt <disp9>"
 167 {
 168   COMPAT_1 (OP_586 ());
 169 }
 170
 171 ddddd,1011,ddd,0111:III:::ble
 172 "ble <disp9>"
 173 {
 174   COMPAT_1 (OP_587 ());
 175 }
 176
 177 ddddd,1011,ddd,1000:III:::bnv
 178 "bnv <disp9>"
 179 {
 180   COMPAT_1 (OP_588 ());
 181 }
 182
 183 ddddd,1011,ddd,1001:III:::bnl
 184 "bnl <disp9>"
 185 {
 186   COMPAT_1 (OP_589 ());
 187 }
 188
 189 ddddd,1011,ddd,1010:III:::bne
 190 "bne <disp9>"
 191 {
 192   COMPAT_1 (OP_58A ());
 193 }
 194
 195 ddddd,1011,ddd,1011:III:::bh
 196 "bh <disp9>"
 197 {
 198   COMPAT_1 (OP_58B ());
 199 }
 200
 201 ddddd,1011,ddd,1100:III:::bp
 202 "bp <disp9>"
 203 {
 204   COMPAT_1 (OP_58C ());
 205 }
 206
 207 ddddd,1011,ddd,1101:III:::bsa
 208 "bsa <disp9>"
 209 {
 210   COMPAT_1 (OP_58D ());
 211 }
 212
 213 ddddd,1011,ddd,1110:III:::bge
 214 "bge <disp9>"
 215 {
 216   COMPAT_1 (OP_58E ());
 217 }
 218
 219 ddddd,1011,ddd,1111:III:::bgt
 220 "bgt <disp9>"
 221 {
 222   COMPAT_1 (OP_58F ());
 223 }
 224
 225
 226
 227 // start-sanitize-v850e
 228 // BSH
 229 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 230 *v850e
 231 // start-sanitize-v850eq
 232 *v850eq
 233 // end-sanitize-v850eq
 234 "bsh r<reg2>, r<reg3>"
 235 {
 236   COMPAT_2 (OP_34207E0 ());
 237 }
 238
 239
 240
 241 // end-sanitize-v850e
 242 // start-sanitize-v850e
 243 // BSW
 244 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 245 *v850e
 246 // start-sanitize-v850eq
 247 *v850eq
 248 // end-sanitize-v850eq
 249 "bsw r<reg2>, reg3>"
 250 {
 251   COMPAT_2 (OP_34007E0 ());
 252 }
 253
 254
 255
 256 // end-sanitize-v850e
 257 // start-sanitize-v850e
 258 // CALLT
 259 0000001000,iiiiii:II:::callt
 260 *v850e
 261 // start-sanitize-v850eq
 262 *v850eq
 263 // end-sanitize-v850eq
 264 "callt <imm6>"
 265 {
 266   COMPAT_1 (OP_200 ());
 267 }
 268
 269
 270
 271 // end-sanitize-v850e
 272 // CLR1
 273 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
 274 "clr1 <bit3>, <disp16>[r<reg1>]"
 275 {
 276   COMPAT_2 (OP_87C0 ());
 277 }
 278
 279 // start-sanitize-v850e
 280 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 281 *v850e
 282 // start-sanitize-v850eq
 283 *v850eq
 284 // end-sanitize-v850eq
 285 "clr1 r<reg2>, [r<reg1>]"
 286 {
 287   COMPAT_2 (OP_E407E0 ());
 288 }
 289
 290
 291
 292 // end-sanitize-v850e
 293 // start-sanitize-v850e
 294 // CTRET
 295 0000011111100000 + 0000000101000100:X:::ctret
 296 *v850e
 297 // start-sanitize-v850eq
 298 *v850eq
 299 // end-sanitize-v850eq
 300 "ctret"
 301 {
 302   COMPAT_2 (OP_14407E0 ());
 303 }
 304
 305
 306
 307 // end-sanitize-v850e
 308 // start-sanitize-v850e
 309 // CMOV
 310 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 311 *v850e
 312 // start-sanitize-v850eq
 313 *v850eq
 314 // end-sanitize-v850eq
 315 "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
 316 {
 317   COMPAT_2 (OP_32007E0 ());
 318 }
 319
 320 // end-sanitize-v850e
 321 // start-sanitize-v850e
 322 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
 323 *v850e
 324 // start-sanitize-v850eq
 325 *v850eq
 326 // end-sanitize-v850eq
 327 "cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
 328 {
 329   COMPAT_2 (OP_30007E0 ());
 330 }
 331
 332
 333
 334 // end-sanitize-v850e
 335 // CMP
 336 rrrrr,001111,RRRRR:I:::cmp
 337 "cmp r<reg1>, r<reg2>"
 338 {
 339   COMPAT_1 (OP_1E0 ());
 340 }
 341
 342 rrrrr,010011,iiiii:II:::cmp
 343 "cmp <imm5>, r<reg2>"
 344 {
 345   COMPAT_1 (OP_260 ());
 346 }
 347
 348
 349
 350 // DI
 351 0000011111100000 + 0000000101100000:X:::di
 352 "di"
 353 {
 354   COMPAT_2 (OP_16007E0 ());
 355 }
 356
 357
 358
 359 // start-sanitize-v850e
 360 // DISPOSE
 361 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
 362 // "dispose <imm5>, <list12>"
 363 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
 364 *v850e
 365 // start-sanitize-v850eq
 366 *v850eq
 367 // end-sanitize-v850eq
 368 "dispose <imm5>, <list12>":RRRRR == 0
 369 "dispose <imm5>, <list12>, [reg1]"
 370 {
 371   COMPAT_2 (OP_640 ());
 372 }
 373
 374
 375
 376 // end-sanitize-v850e
 377 // start-sanitize-v850e
 378 // DIV
 379 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 380 *v850e
 381 "div r<reg1>, r<reg2>, r<reg3>"
 382 {
 383   COMPAT_2 (OP_2C007E0 ());
 384 }
 385
 386
 387
 388
 389 // end-sanitize-v850e
 390 // DIVH
 391 rrrrr!0,000010,RRRRR!0:I:::divh
 392 "divh r<reg1>, r<reg2>"
 393 {
 394   COMPAT_1 (OP_40 ());
 395 }
 396
 397 // start-sanitize-v850e
 398 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
 399 *v850e
 400 "divh r<reg1>, r<reg2>, r<reg3>"
 401 {
 402   COMPAT_2 (OP_28007E0 ());
 403 }
 404
 405
 406
 407 // end-sanitize-v850e
 408 // start-sanitize-v850e
 409 // DIVHU
 410 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
 411 *v850e
 412 "divhu r<reg1>, r<reg2>, r<reg3>"
 413 {
 414   COMPAT_2 (OP_28207E0 ());
 415 }
 416
 417
 418
 419 // end-sanitize-v850e
 420 // start-sanitize-v850e
 421 // DIVU
 422 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 423 *v850e
 424 "divu r<reg1>, r<reg2>, r<reg3>"
 425 {
 426   COMPAT_2 (OP_2C207E0 ());
 427 }
 428
 429
 430
 431 // end-sanitize-v850e
 432 // EI
 433 1000011111100000 + 0000000101100000:X:::ei
 434 "ei"
 435 {
 436   COMPAT_2 (OP_16087E0 ());
 437 }
 438
 439
 440
 441 // HALT
 442 0000011111100000 + 0000000100100000:X:::halt
 443 "halt"
 444 {
 445   COMPAT_2 (OP_12007E0 ());
 446 }
 447
 448
 449
 450 // start-sanitize-v850e
 451 // HSW
 452 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 453 *v850e
 454 // start-sanitize-v850eq
 455 *v850eq
 456 // end-sanitize-v850eq
 457 "hsw r<reg2>, r<reg3>"
 458 {
 459   COMPAT_2 (OP_34407E0 ());
 460 }
 461
 462
 463
 464 // end-sanitize-v850e
 465 // JARL
 466 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 467 "jarl <disp22>, r<reg2>"
 468 {
 469   COMPAT_2 (OP_780 ());
 470 }
 471
 472
 473
 474 // JMP
 475 00000000011,RRRRR:I:::jmp
 476 "jmp [r<reg1>]"
 477 {
 478   SAVE_1;
 479   trace_input ("jmp", OP_REG, 0);
 480   nia = State.regs[ reg1 ];
 481   trace_output (OP_REG);
 482 }
 483
 484
 485
 486 // JR
 487 0000011110,dddddd + ddddddddddddddd,0:V:::jr
 488 "jr <disp22>"
 489 {
 490   COMPAT_2 (OP_780 ());
 491 }
 492
 493
 494
 495 // LD
 496 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 497 "ld.b <disp16>[r<reg1>, r<reg2>"
 498 {
 499   COMPAT_2 (OP_700 ());
 500 }
 501
 502 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 503 "ld.h <disp16>[r<reg1>], r<reg2>"
 504 {
 505   COMPAT_2 (OP_720 ());
 506 }
 507
 508 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 509 "ld.w <disp16>[r<reg1>], r<reg2>"
 510 {
 511   COMPAT_2 (OP_10720 ());
 512 }
 513
 514 // start-sanitize-v850e
 515 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 516 *v850e
 517 // start-sanitize-v850eq
 518 *v850eq
 519 // end-sanitize-v850eq
 520 "ld.bu <disp16>[r<reg1>], r<reg2>"
 521 {
 522   COMPAT_2 (OP_10780 ());
 523 }
 524
 525 // end-sanitize-v850e
 526 // start-sanitize-v850e
 527 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 528 *v850e
 529 // start-sanitize-v850eq
 530 *v850eq
 531 // end-sanitize-v850eq
 532 "ld.hu <disp16>[r<reg1>], r<reg2>"
 533 {
 534   COMPAT_2 (OP_107E0 ());
 535 }
 536
 537
 538 // end-sanitize-v850e
 539 // LDSR
 540 //rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
 541 //"ldsr r<reg2>, r<regID>"
 542 //{
 543 //  COMPAT_2 (OP_2007E0 ());
 544 //}
 545 rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
 546 "ldsr r<reg1>, r<regID>"
 547 {
 548   COMPAT_2 (OP_2007E0 ());
 549 }
 550
 551
 552
 553 // MOV
 554 rrrrr!0,000000,RRRRR:I:::mov
 555 "mov r<reg1>, r<reg2>"
 556 {
 557   COMPAT_1 (OP_0 ());
 558 }
 559
 560 rrrrr!0,010000,iiiii:II:::mov
 561 "mov <imm5>, r<reg2>"
 562 {
 563   COMPAT_1 (OP_200 ());
 564 }
 565
 566 // start-sanitize-v850e
 567 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
 568 *v850e
 569 // start-sanitize-v850eq
 570 *v850eq
 571 // end-sanitize-v850eq
 572 "mov <imm32>, r<reg1>"
 573 {
 574   COMPAT_2 (OP_620 ());
 575 }
 576
 577
 578
 579 // end-sanitize-v850e
 580 // MOVEA
 581 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
 582 "movea <imm16>, r<reg1>, r<reg2>"
 583 {
 584   COMPAT_2 (OP_620 ());
 585 }
 586
 587
 588
 589 // MOVHI
 590 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
 591 "movhi <imm16>, r<reg1>, r<reg2>"
 592 {
 593   COMPAT_2 (OP_640 ());
 594 }
 595
 596
 597
 598 // start-sanitize-v850e
 599 // MUL
 600 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
 601 *v850e
 602 // start-sanitize-v850eq
 603 *v850eq
 604 // end-sanitize-v850eq
 605 "mul r<reg1>, r<reg2>, r<reg3>"
 606 {
 607   COMPAT_2 (OP_22007E0 ());
 608 }
 609
 610 // end-sanitize-v850e
 611 // start-sanitize-v850e
 612 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
 613 *v850e
 614 // start-sanitize-v850eq
 615 *v850eq
 616 // end-sanitize-v850eq
 617 "mul <imm9>, r<reg2>, r<reg3>"
 618 {
 619   COMPAT_2 (OP_24007E0 ());
 620 }
 621
 622
 623
 624 // end-sanitize-v850e
 625 // MULH
 626 rrrrr!0,000111,RRRRR:I:::mulh
 627 "mulh r<reg1>, r<reg2>"
 628 {
 629   COMPAT_1 (OP_E0 ());
 630 }
 631
 632 rrrrr!0,010111,iiiii:II:::mulh
 633 "mulh <imm5>, r<reg2>"
 634 {
 635   COMPAT_1 (OP_2E0 ());
 636 }
 637
 638
 639
 640 // MULHI
 641 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
 642 "mulhi <imm16>, r<reg1>, r<reg2>"
 643 {
 644   COMPAT_2 (OP_6E0 ());
 645 }
 646
 647
 648
 649 // start-sanitize-v850e
 650 // MULU
 651 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
 652 *v850e
 653 // start-sanitize-v850eq
 654 *v850eq
 655 // end-sanitize-v850eq
 656 "mulu r<reg1>, r<reg2>, r<reg3>"
 657 {
 658   COMPAT_2 (OP_22207E0 ());
 659 }
 660
 661 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
 662 *v850e
 663 // start-sanitize-v850eq
 664 *v850eq
 665 // end-sanitize-v850eq
 666 "mulu <imm9>, r<reg2>, r<reg3>"
 667 {
 668   COMPAT_2 (OP_24207E0 ());
 669 }
 670
 671
 672
 673 // end-sanitize-v850e
 674 // NOP
 675 0000000000000000:I:::nop
 676 "nop"
 677 {
 678   COMPAT_1 (OP_0 ());
 679 }
 680
 681
 682
 683 // NOT
 684 rrrrr,000001,RRRRR:I:::not
 685 "not r<reg1>, r<reg2>"
 686 {
 687   COMPAT_1 (OP_20 ());
 688 }
 689
 690
 691
 692 // NOT1
 693 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
 694 "not1 <bit3>, <disp16>[r<reg1>]"
 695 {
 696   COMPAT_2 (OP_47C0 ());
 697 }
 698
 699 // start-sanitize-v850e
 700 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
 701 *v850e
 702 // start-sanitize-v850eq
 703 *v850eq
 704 // end-sanitize-v850eq
 705 "not1 r<reg2>, r<reg1>"
 706 {
 707   COMPAT_2 (OP_E207E0 ());
 708 }
 709
 710
 711
 712 // end-sanitize-v850e
 713 // OR
 714 rrrrr,001000,RRRRR:I:::or
 715 "or r<reg1>, r<reg2>"
 716 {
 717   COMPAT_1 (OP_100 ());
 718 }
 719
 720
 721
 722 // ORI
 723 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 724 "ori <imm16>, r<reg1>, r<reg2>"
 725 {
 726   COMPAT_2 (OP_680 ());
 727 }
 728
 729
 730
 731 // start-sanitize-v850e
 732 // PREPARE
 733 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
 734 *v850e
 735 // start-sanitize-v850eq
 736 *v850eq
 737 // end-sanitize-v850eq
 738 "prepare <list12>, <imm5>"
 739 {
 740   int  i;
 741   SAVE_2;
 742
 743   trace_input ("prepare", OP_PUSHPOP1, 0);
 744
 745   /* Store the registers with lower number registers being placed at
 746      higher addresses.  */
 747   for (i = 0; i < 12; i++)
 748     if ((OP[3] & (1 << type1_regs[ i ])))
 749       {
 750         SP -= 4;
 751         store_mem (SP, 4, State.regs[ 20 + i ]);
 752       }
 753
 754   SP -= (OP[3] & 0x3e) << 1;
 755
 756   trace_output (OP_PUSHPOP1);
 757 }
 758
 759
 760 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
 761 *v850e
 762 // start-sanitize-v850eq
 763 *v850eq
 764 // end-sanitize-v850eq
 765 "prepare <list12>, <imm5>, sp"
 766 {
 767   COMPAT_2 (OP_30780 ());
 768 }
 769
 770 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
 771 *v850e
 772 // start-sanitize-v850eq
 773 *v850eq
 774 // end-sanitize-v850eq
 775 "prepare <list12>, <imm5>, <uimm16>"
 776 {
 777   COMPAT_2 (OP_B0780 ());
 778 }
 779
 780 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
 781 *v850e
 782 // start-sanitize-v850eq
 783 *v850eq
 784 // end-sanitize-v850eq
 785 "prepare <list12>, <imm5>, <uimm16>"
 786 {
 787   COMPAT_2 (OP_130780 ());
 788 }
 789
 790 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
 791 *v850e
 792 // start-sanitize-v850eq
 793 *v850eq
 794 // end-sanitize-v850eq
 795 "prepare <list12>, <imm5>, <uimm32>"
 796 {
 797   COMPAT_2 (OP_1B0780 ());
 798 }
 799
 800
 801
 802 // end-sanitize-v850e
 803 // RETI
 804 0000011111100000 + 0000000101000000:X:::reti
 805 "reti"
 806 {
 807   COMPAT_2 (OP_14007E0 ());
 808 }
 809
 810
 811
 812 // SAR
 813 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
 814 "sar r<reg1>, r<reg2>"
 815 {
 816   COMPAT_2 (OP_A007E0 ());
 817 }
 818
 819 rrrrr,010101,iiiii:II:::sar
 820 "sar <imm5>, r<reg2>"
 821 {
 822   COMPAT_1 (OP_2A0 ());
 823 }
 824
 825
 826
 827 // start-sanitize-v850e
 828 // SASF
 829 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
 830 *v850e
 831 // start-sanitize-v850eq
 832 *v850eq
 833 // end-sanitize-v850eq
 834 "sasf <cccc>, r<reg2>"
 835 {
 836   COMPAT_2 (OP_20007E0 ());
 837 }
 838
 839
 840
 841
 842 // end-sanitize-v850e
 843 // SATADD
 844 rrrrr!0,000110,RRRRR:I:::satadd
 845 "satadd r<reg1>, r<reg2>"
 846 {
 847   COMPAT_1 (OP_C0 ());
 848 }
 849
 850 rrrrr!0,010001,iiiii:II:::satadd
 851 "satadd <imm5>, r<reg2>"
 852 {
 853   COMPAT_1 (OP_220 ());
 854 }
 855
 856
 857
 858 // SATSUB
 859 rrrrr!0,000101,RRRRR:I:::satsub
 860 "satsub r<reg1>, r<reg2>"
 861 {
 862   COMPAT_1 (OP_A0 ());
 863 }
 864
 865
 866
 867 // SATSUBI
 868 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
 869 "satsubi <imm16>, r<reg1>, r<reg2>"
 870 {
 871   COMPAT_2 (OP_660 ());
 872 }
 873
 874
 875
 876 // SATSUBR
 877 rrrrr!0,000100,RRRRR:I:::satsubr
 878 "satsubr r<reg1>, r<reg2>"
 879 {
 880   COMPAT_1 (OP_80 ());
 881 }
 882
 883
 884
 885 // SETF
 886 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
 887 "setf <cccc>, r<reg2>"
 888 {
 889   COMPAT_2 (OP_7E0 ());
 890 }
 891
 892
 893
 894 // SET1
 895 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
 896 "set1 <bit3>, <disp16>[r<reg1>]"
 897 {
 898   COMPAT_2 (OP_7C0 ());
 899 }
 900
 901 // start-sanitize-v850e
 902 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
 903 *v850e
 904 // start-sanitize-v850eq
 905 *v850eq
 906 // end-sanitize-v850eq
 907 "set1 r<reg2>, [r<reg1>]"
 908 {
 909   COMPAT_2 (OP_E007E0 ());
 910 }
 911
 912
 913
 914 // end-sanitize-v850e
 915 // SHL
 916 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
 917 "shl r<reg1>, r<reg2>"
 918 {
 919   COMPAT_2 (OP_C007E0 ());
 920 }
 921
 922 rrrrr,010110,iiiii:II:::shl
 923 "shl <imm5>, r<reg2>"
 924 {
 925   COMPAT_1 (OP_2C0 ());
 926 }
 927
 928
 929
 930 // SHR
 931 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
 932 "shr r<reg1>, r<reg2>"
 933 {
 934   COMPAT_2 (OP_8007E0 ());
 935 }
 936
 937 rrrrr,010100,iiiii:II:::shr
 938 "shr <imm5>, r<reg2>"
 939 {
 940   COMPAT_1 (OP_280 ());
 941 }
 942
 943
 944
 945 // SLD
 946 rrrrr,0110,ddddddd:IV:::sld.b
 947 "sld.b <disp7>[ep], r<reg2>"
 948 {
 949   COMPAT_1 (OP_300 ());
 950 }
 951
 952 rrrrr,1000,ddddddd:IV:::sld.h
 953 "sld.h <disp8>[ep], r<reg2>"
 954 {
 955   COMPAT_1 (OP_400 ());
 956 }
 957
 958 rrrrr,1010,dddddd,0:IV:::sld.w
 959 "sld.w <disp8>[ep], r<reg2>"
 960 {
 961   COMPAT_1 (OP_500 ());
 962 }
 963
 964 // start-sanitize-v850e
 965 rrrrr!0,0000110,dddd:IV:::sld.bu
 966 "sld.bu <disp4>[ep], r<reg2>"
 967 {
 968   unsigned long result;
 969
 970   SAVE_1;
 971   result = load_mem (State.regs[30] + disp4, 1);
 972
 973   /* start-sanitize-v850eq */
 974   if (PSW & PSW_US) {
 975     trace_input ("sld.b", OP_LOAD16, 1);
 976
 977     State.regs[ reg2 ] = EXTEND8 (result);
 978   } else {
 979   /* end-sanitize-v850eq */
 980   trace_input ("sld.bu", OP_LOAD16, 1);
 981   State.regs[ reg2 ] = result;
 982   /* start-sanitize-v850eq */
 983   }
 984   /* end-sanitize-v850eq */
 985   trace_output (OP_LOAD16);
 986 }
 987
 988 // end-sanitize-v850e
 989 // start-sanitize-v850e
 990 rrrrr!0,0000111,dddd:IV:::sld.hu
 991 "sld.hu <disp5>[ep], r<reg2>"
 992 {
 993   COMPAT_1 (OP_70 ());
 994 }
 995
 996 // end-sanitize-v850e
 997
 998
 999 // SST
1000 rrrrr,0111,ddddddd:IV:::sst.b
1001 "sst.b r<reg2>, <disp7>[ep]"
1002 {
1003   COMPAT_1 (OP_380 ());
1004 }
1005
1006 rrrrr,1001,ddddddd:IV:::sst.h
1007 "sst.h r<reg2>, <disp8>[ep]"
1008 {
1009   COMPAT_1 (OP_480 ());
1010 }
1011
1012 rrrrr,1010,dddddd,1:IV:::sst.w
1013 "sst.w r<reg2>, <disp8>[ep]"
1014 {
1015   COMPAT_1 (OP_501 ());
1016 }
1017
1018
1019
1020 // ST
1021 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
1022 "st.b r<reg2>, <disp16>[r<reg1>]"
1023 {
1024   COMPAT_2 (OP_740 ());
1025 }
1026
1027 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
1028 "st.h r<reg2>, <disp16>[r<reg1>]"
1029 {
1030   COMPAT_2 (OP_760 ());
1031 }
1032
1033 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1034 "st.w r<reg2>, <disp16>[r<reg1>]"
1035 {
1036   COMPAT_2 (OP_10760 ());
1037 }
1038
1039
1040
1041 // STSR
1042 //rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
1043 //"stsr r<regID>, r<reg2>"
1044 //{
1045 //  COMPAT_2 (OP_4007E0 ());
1046 //}
1047 rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
1048 "stsr r<regID>, r<reg1>"
1049 {
1050   COMPAT_2 (OP_4007E0 ());
1051 }
1052
1053
1054
1055 // SUB
1056 rrrrr,001101,RRRRR:I:::sub
1057 "sub r<reg1>, r<reg2>"
1058 {
1059   COMPAT_1 (OP_1A0 ());
1060 }
1061
1062
1063
1064 // SUBR
1065 rrrrr,001100,RRRRR:I:::subr
1066 "subr r<reg1>, r<reg2>"
1067 {
1068   COMPAT_1 (OP_180 ());
1069 }
1070
1071
1072
1073 // start-sanitize-v850e
1074 // SWITCH
1075 00000000010,RRRRR:I:::switch
1076 *v850e
1077 // start-sanitize-v850eq
1078 *v850eq
1079 // end-sanitize-v850eq
1080 "switch r<reg1>"
1081 {
1082   COMPAT_1 (OP_40 ());
1083 }
1084 // end-sanitize-v850e
1085
1086
1087
1088 // start-sanitize-v850e
1089 // SXB
1090 00000000101,RRRRR:I:::sxb
1091 *v850e
1092 // start-sanitize-v850eq
1093 *v850eq
1094 // end-sanitize-v850eq
1095 "sxb r<reg1>"
1096 {
1097   COMPAT_1 (OP_A0 ());
1098 }
1099
1100
1101
1102 // end-sanitize-v850e
1103 // start-sanitize-v850e
1104 // SXH
1105 00000000111,RRRRR:I:::sxh
1106 *v850e
1107 // start-sanitize-v850eq
1108 *v850eq
1109 // end-sanitize-v850eq
1110 "sxh r<reg1>"
1111 {
1112   COMPAT_1 (OP_E0 ());
1113 }
1114
1115
1116
1117 // end-sanitize-v850e
1118 // TRAP
1119 00000111111,iiiii + 0000000100000000:X:::trap
1120 "trap <vector>"
1121 {
1122   COMPAT_2 (OP_10007E0 ());
1123 }
1124
1125
1126
1127 // TST
1128 rrrrr,001011,RRRRR:I:::tst
1129 "tst r<reg1>, r<reg2>"
1130 {
1131   COMPAT_1 (OP_160 ());
1132 }
1133
1134
1135
1136 // TST1
1137 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1138 "tst1 <bit3>, <disp16>[r<reg1>]"
1139 {
1140   COMPAT_2 (OP_C7C0 ());
1141 }
1142
1143 // start-sanitize-v850e
1144 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1145 *v850e
1146 // start-sanitize-v850eq
1147 *v850eq
1148 // end-sanitize-v850eq
1149 "tst1 r<reg2>, [r<reg1>]"
1150 {
1151   COMPAT_2 (OP_E607E0 ());
1152 }
1153
1154
1155
1156 // end-sanitize-v850e
1157 // XOR
1158 rrrrr,001001,RRRRR:I:::xor
1159 "xor r<reg1>, r<reg2>"
1160 {
1161   COMPAT_1 (OP_120 ());
1162 }
1163
1164
1165
1166 // XORI
1167 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1168 "xori <imm16>, r<reg1>, r<reg2>"
1169 {
1170   COMPAT_2 (OP_6A0 ());
1171 }
1172
1173
1174
1175 // start-sanitize-v850e
1176 // ZXB
1177 00000000100,RRRRR:I:::zxb
1178 *v850e
1179 // start-sanitize-v850eq
1180 *v850eq
1181 // end-sanitize-v850eq
1182 "zxb r<reg1>"
1183 {
1184   SAVE_1;
1185
1186   trace_input ("zxb", OP_REG, 0);
1187
1188   State.regs[ OP[0] ] &= 0xff;
1189
1190   trace_output (OP_REG);
1191 }
1192
1193
1194
1195 // end-sanitize-v850e
1196 // start-sanitize-v850e
1197 // ZXH
1198 00000000110,RRRRR:I:::zxh
1199 *v850e
1200 // start-sanitize-v850eq
1201 *v850eq
1202 // end-sanitize-v850eq
1203 "zxh r<reg1>"
1204 {
1205   SAVE_1;
1206
1207   trace_input ("zxh", OP_REG, 0);
1208
1209   State.regs[ OP[0] ] &= 0xffff;
1210
1211   trace_output (OP_REG);
1212 }
1213
1214
1215
1216 // end-sanitize-v850e
1217 // Special - breakpoint - illegal
1218 // Hopefully, in the future, this instruction will go away
1219 1111111111111111 + 1111111111111111:Z:::breakpoint
1220 *v850
1221 {
1222   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1223 }
1224
1225 // start-sanitize-v850e
1226 // First field could be any nonzero value.
1227 11111,000010,00000:I:::break
1228 {
1229   sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1230 }
1231
1232 // end-sanitize-v850e
1233
1234
1235 // start-sanitize-v850eq
1236 // DIVHN
1237 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1238 *v850eq
1239 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1240 {
1241   signed32 quotient;
1242   signed32 remainder;
1243   signed32 divide_by;
1244   signed32 divide_this;
1245   boolean overflow = false;
1246   SAVE_2;
1247
1248   trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
1249
1250   divide_by   = EXTEND16 (State.regs[ reg1 ]);
1251   divide_this = State.regs[ reg2 ];
1252
1253   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1254
1255   State.regs[ reg2 ] = quotient;
1256   State.regs[ reg3 ] = remainder;
1257
1258   /* Set condition codes.  */
1259   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1260
1261   if (overflow)      PSW |= PSW_OV;
1262   if (quotient == 0) PSW |= PSW_Z;
1263   if (quotient <  0) PSW |= PSW_S;
1264
1265   trace_output (OP_IMM_REG_REG_REG);
1266 }
1267
1268
1269
1270 // DIVHUN
1271 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1272 *v850eq
1273 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1274 {
1275   signed32 quotient;
1276   signed32 remainder;
1277   signed32 divide_by;
1278   signed32 divide_this;
1279   boolean overflow = false;
1280   SAVE_2;
1281
1282   trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
1283
1284   divide_by   = State.regs[ reg1 ] & 0xffff;
1285   divide_this = State.regs[ reg2 ];
1286
1287   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1288
1289   State.regs[ reg2 ] = quotient;
1290   State.regs[ reg3 ] = remainder;
1291
1292   /* Set condition codes.  */
1293   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1294
1295   if (overflow)      PSW |= PSW_OV;
1296   if (quotient == 0) PSW |= PSW_Z;
1297   if (quotient & 0x80000000) PSW |= PSW_S;
1298
1299   trace_output (OP_IMM_REG_REG_REG);
1300 }
1301
1302
1303
1304 // DIVN
1305 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1306 *v850eq
1307 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1308 {
1309   signed32 quotient;
1310   signed32 remainder;
1311   signed32 divide_by;
1312   signed32 divide_this;
1313   boolean overflow = false;
1314   SAVE_2;
1315
1316   trace_input ("divn", OP_IMM_REG_REG_REG, 0);
1317
1318   divide_by   = State.regs[ reg1 ];
1319   divide_this = State.regs[ reg2 ];
1320
1321   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1322
1323   State.regs[ reg2 ] = quotient;
1324   State.regs[ reg3 ] = remainder;
1325
1326   /* Set condition codes.  */
1327   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1328
1329   if (overflow)      PSW |= PSW_OV;
1330   if (quotient == 0) PSW |= PSW_Z;
1331   if (quotient <  0) PSW |= PSW_S;
1332
1333   trace_output (OP_IMM_REG_REG_REG);
1334 }
1335
1336
1337
1338 // DIVUN
1339 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1340 *v850eq
1341 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1342 {
1343   signed32 quotient;
1344   signed32 remainder;
1345   signed32 divide_by;
1346   signed32 divide_this;
1347   boolean overflow = false;
1348   SAVE_2;
1349
1350   trace_input ("divun", OP_IMM_REG_REG_REG, 0);
1351
1352   divide_by   = State.regs[ reg1 ];
1353   divide_this = State.regs[ reg2 ];
1354
1355   divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1356
1357   State.regs[ reg2 ] = quotient;
1358   State.regs[ reg3 ] = remainder;
1359
1360   /* Set condition codes.  */
1361   PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1362
1363   if (overflow)      PSW |= PSW_OV;
1364   if (quotient == 0) PSW |= PSW_Z;
1365   if (quotient & 0x80000000) PSW |= PSW_S;
1366
1367   trace_output (OP_IMM_REG_REG_REG);
1368 }
1369
1370
1371
1372 // SDIVHN
1373 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1374 *v850eq
1375 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1376 {
1377   COMPAT_2 (OP_18007E0 ());
1378 }
1379
1380
1381
1382 // SDIVHUN
1383 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1384 *v850eq
1385 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1386 {
1387   COMPAT_2 (OP_18207E0 ());
1388 }
1389
1390
1391
1392 // SDIVN
1393 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1394 *v850eq
1395 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1396 {
1397   COMPAT_2 (OP_1C007E0 ());
1398 }
1399
1400
1401
1402 // SDIVUN
1403 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1404 *v850eq
1405 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1406 {
1407   COMPAT_2 (OP_1C207E0 ());
1408 }
1409
1410
1411
1412 // PUSHML
1413 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1414 *v850eq
1415 "pushml <list18>"
1416 {
1417   int i;
1418   SAVE_2;
1419
1420   trace_input ("pushml", OP_PUSHPOP3, 0);
1421
1422   /* Store the registers with lower number registers being placed at
1423      higher addresses.  */
1424
1425   for (i = 0; i < 15; i++)
1426     if ((OP[3] & (1 << type3_regs[ i ])))
1427       {
1428         SP -= 4;
1429         store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
1430       }
1431
1432   if (OP[3] & (1 << 3))
1433     {
1434       SP -= 4;
1435
1436       store_mem (SP & ~ 3, 4, PSW);
1437     }
1438
1439   if (OP[3] & (1 << 19))
1440     {
1441       SP -= 8;
1442
1443       if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
1444         {
1445           store_mem ((SP + 4) & ~ 3, 4, FEPC);
1446           store_mem ( SP      & ~ 3, 4, FEPSW);
1447         }
1448       else
1449         {
1450           store_mem ((SP + 4) & ~ 3, 4, EIPC);
1451           store_mem ( SP      & ~ 3, 4, EIPSW);
1452         }
1453     }
1454
1455   trace_output (OP_PUSHPOP2);
1456 }
1457
1458
1459
1460 // PUSHHML
1461 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1462 *v850eq
1463 "pushhml <list18>"
1464 {
1465   COMPAT_2 (OP_307E0 ());
1466 }
1467
1468
1469
1470 // POPML
1471 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1472 *v850eq
1473 "popml <list18>"
1474 {
1475   COMPAT_2 (OP_107F0 ());
1476 }
1477
1478
1479
1480 // POPMH
1481 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1482 *v850eq
1483 "popmh <list18>"
1484 {
1485   COMPAT_2 (OP_307F0 ());
1486 }
1487
1488
1489 // end-sanitize-v850eq