1 :option:::insn-bit-size:16
5 :option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
6 :option:::format-names:XI,XII,XIII
7 :option:::format-names:XIV,XV
8 :option:::format-names:Z
13 :option:::multi-sim:true
16 :option:::multi-sim:true
17 :model:::v850ea:v850ea:
23 :cache:::unsigned:reg1:RRRRR:(RRRRR)
24 :cache:::unsigned:reg2:rrrrr:(rrrrr)
25 :cache:::unsigned:reg3:wwwww:(wwwww)
27 :cache:::unsigned:disp4:dddd:(dddd)
28 :cache:::unsigned:disp5:dddd:(dddd << 1)
29 :cache:::unsigned:disp7:ddddddd:ddddddd
30 :cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
31 :cache:::unsigned:disp8:dddddd:(dddddd << 2)
32 :cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
33 :cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
34 :cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
35 :cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
37 :cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
38 :cache:::unsigned:imm6:iiiiii:iiiiii
39 :cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
40 :cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
41 :cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
42 :cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
43 :cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
44 :cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
46 :cache:::unsigned:vector:iiiii:iiiii
48 :cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
49 :cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
51 :cache:::unsigned:bit3:bbb:bbb
54 // What do we do with an illegal instruction?
57 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
59 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
66 rrrrr,001110,RRRRR:I:::add
67 "add r<reg1>, r<reg2>"
72 rrrrr,010010,iiiii:II:::add
81 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
82 "addi <simm16>, r<reg1>, r<reg2>"
90 rrrrr,001010,RRRRR:I:::and
91 "and r<reg1>, r<reg2>"
99 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
100 "andi <uimm16>, r<reg1>, r<reg2>"
102 COMPAT_2 (OP_6C0 ());
107 // Map condition code to a string
112 case 0xf: return "gt";
113 case 0xe: return "ge";
114 case 0x6: return "lt";
116 case 0x7: return "le";
118 case 0xb: return "h";
119 case 0x9: return "nl";
120 case 0x1: return "l";
122 case 0x3: return "nh";
124 case 0x2: return "e";
126 case 0xa: return "ne";
128 case 0x0: return "v";
129 case 0x8: return "nv";
130 case 0x4: return "n";
131 case 0xc: return "p";
132 /* case 0x1: return "c"; */
133 /* case 0x9: return "nc"; */
134 /* case 0x2: return "z"; */
135 /* case 0xa: return "nz"; */
136 case 0x5: return "r"; /* always */
137 case 0xd: return "sa";
144 ddddd,1011,ddd,cccc:III:::Bcond
148 if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
149 // Special case - treat "br *" like illegal instruction
150 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
152 cond = condition_met (cccc);
155 TRACE_BRANCH1 (cond);
162 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
165 "bsh r<reg2>, r<reg3>"
168 TRACE_ALU_INPUT1 (GR[reg2]);
170 value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
171 | MOVED32 (GR[reg2], 31, 24, 23, 16)
172 | MOVED32 (GR[reg2], 7, 0, 15, 8)
173 | MOVED32 (GR[reg2], 15, 8, 7, 0));
176 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
177 if (value == 0) PSW |= PSW_Z;
178 if (value & 0x80000000) PSW |= PSW_S;
179 if (((value & 0xff) == 0) || (value & 0x00ff) == 0) PSW |= PSW_CY;
181 TRACE_ALU_RESULT (GR[reg3]);
185 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
188 "bsw r<reg2>, r<reg3>"
190 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
192 TRACE_ALU_INPUT1 (GR[reg2]);
196 value |= (GR[reg2] << 24);
197 value |= ((GR[reg2] << 8) & 0x00ff0000);
198 value |= ((GR[reg2] >> 8) & 0x0000ff00);
201 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
203 if (value == 0) PSW |= PSW_Z;
204 if (value & 0x80000000) PSW |= PSW_S;
205 if (WORDHASNULLBYTE (value)) PSW |= PSW_CY;
207 TRACE_ALU_RESULT (GR[reg3]);
211 0000001000,iiiiii:II:::callt
220 adr = (CTBP & ~1) + (imm6 << 1);
221 off = load_mem (adr, 2) & ~1; /* Force alignment */
222 nia = (CTBP & ~1) + off;
223 TRACE_BRANCH3 (adr, CTBP, off);
228 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
229 "clr1 <bit3>, <disp16>[r<reg1>]"
231 COMPAT_2 (OP_87C0 ());
234 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
237 "clr1 r<reg2>, [r<reg1>]"
239 COMPAT_2 (OP_E407E0 ());
244 0000011111100000 + 0000000101000100:X:::ctret
250 PSW = (CTPSW & (CPU)->psw_mask);
255 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
258 "cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
260 int cond = condition_met (cccc);
261 TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
262 GR[reg3] = cond ? GR[reg1] : GR[reg2];
263 TRACE_ALU_RESULT (GR[reg3]);
266 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
269 "cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
271 int cond = condition_met (cccc);
272 TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
273 GR[reg3] = cond ? imm5 : GR[reg2];
274 TRACE_ALU_RESULT (GR[reg3]);
278 rrrrr,001111,RRRRR:I:::cmp
279 "cmp r<reg1>, r<reg2>"
281 COMPAT_1 (OP_1E0 ());
284 rrrrr,010011,iiiii:II:::cmp
285 "cmp <imm5>, r<reg2>"
287 COMPAT_1 (OP_260 ());
293 0000011111100000 + 0000000101100000:X:::di
296 COMPAT_2 (OP_16007E0 ());
302 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
303 // "dispose <imm5>, <list12>"
304 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
307 "dispose <imm5>, <list12>":RRRRR == 0
308 "dispose <imm5>, <list12>, [reg1]"
313 trace_input ("dispose", OP_PUSHPOP1, 0);
315 SP += (OP[3] & 0x3e) << 1;
317 /* Load the registers with lower number registers being retrieved
318 from higher addresses. */
320 if ((OP[3] & (1 << type1_regs[ i ])))
322 State.regs[ 20 + i ] = load_mem (SP, 4);
326 if ((OP[3] & 0x1f0000) != 0)
328 nia = State.regs[ (OP[3] >> 16) & 0x1f];
331 trace_output (OP_PUSHPOP1);
336 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
338 "div r<reg1>, r<reg2>, r<reg3>"
340 COMPAT_2 (OP_2C007E0 ());
345 rrrrr!0,000010,RRRRR!0:I:::divh
346 "divh r<reg1>, r<reg2>"
351 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
353 "divh r<reg1>, r<reg2>, r<reg3>"
355 COMPAT_2 (OP_28007E0 ());
360 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
362 "divhu r<reg1>, r<reg2>, r<reg3>"
364 COMPAT_2 (OP_28207E0 ());
369 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
371 "divu r<reg1>, r<reg2>, r<reg3>"
373 COMPAT_2 (OP_2C207E0 ());
378 1000011111100000 + 0000000101100000:X:::ei
381 COMPAT_2 (OP_16087E0 ());
387 0000011111100000 + 0000000100100000:X:::halt
390 COMPAT_2 (OP_12007E0 ());
396 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
399 "hsw r<reg2>, r<reg3>"
402 TRACE_ALU_INPUT1 (GR[reg2]);
406 value |= (GR[reg2] << 16);
410 PSW &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
412 if (value == 0) PSW |= PSW_Z;
413 if (value & 0x80000000) PSW |= PSW_S;
414 if (((value & 0xffff) == 0) || (value & 0xffff0000) == 0) PSW |= PSW_CY;
416 TRACE_ALU_RESULT (GR[reg3]);
422 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
423 "jarl <disp22>, r<reg2>"
427 TRACE_BRANCH1 (GR[reg2]);
433 00000000011,RRRRR:I:::jmp
443 0000011110,dddddd + ddddddddddddddd,0:V:::jr
453 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
454 "ld.b <disp16>[r<reg1>], r<reg2>"
456 COMPAT_2 (OP_700 ());
459 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
460 "ld.h <disp16>[r<reg1>], r<reg2>"
462 COMPAT_2 (OP_720 ());
465 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
466 "ld.w <disp16>[r<reg1>], r<reg2>"
468 COMPAT_2 (OP_10720 ());
471 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
474 "ld.bu <disp16>[r<reg1>], r<reg2>"
476 COMPAT_2 (OP_10780 ());
479 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
482 "ld.hu <disp16>[r<reg1>], r<reg2>"
484 COMPAT_2 (OP_107E0 ());
489 regID,111111,RRRRR + 0000000000100000:IX:::ldsr
490 "ldsr r<reg1>, s<regID>"
492 TRACE_ALU_INPUT1 (GR[reg1]);
494 if (&PSW == &SR[regID])
495 PSW = (GR[reg1] & (CPU)->psw_mask);
497 SR[regID] = GR[reg1];
499 TRACE_ALU_RESULT (SR[regID]);
505 rrrrr!0,000000,RRRRR:I:::mov
506 "mov r<reg1>, r<reg2>"
510 TRACE_ALU_RESULT (GR[reg2]);
514 rrrrr!0,010000,iiiii:II:::mov
515 "mov <imm5>, r<reg2>"
517 COMPAT_1 (OP_200 ());
520 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
523 "mov <imm32>, r<reg1>"
526 trace_input ("mov", OP_IMM_REG, 4);
527 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
528 trace_output (OP_IMM_REG);
534 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
535 "movea <simm16>, r<reg1>, r<reg2>"
537 TRACE_ALU_INPUT2 (GR[reg1], simm16);
538 GR[reg2] = GR[reg1] + simm16;
539 TRACE_ALU_RESULT (GR[reg2]);
545 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
546 "movhi <uimm16>, r<reg1>, r<reg2>"
548 COMPAT_2 (OP_640 ());
554 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
557 "mul r<reg1>, r<reg2>, r<reg3>"
559 COMPAT_2 (OP_22007E0 ());
562 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
565 "mul <imm9>, r<reg2>, r<reg3>"
567 COMPAT_2 (OP_24007E0 ());
572 rrrrr!0,000111,RRRRR:I:::mulh
573 "mulh r<reg1>, r<reg2>"
578 rrrrr!0,010111,iiiii:II:::mulh
579 "mulh <imm5>, r<reg2>"
581 COMPAT_1 (OP_2E0 ());
587 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
588 "mulhi <uimm16>, r<reg1>, r<reg2>"
590 COMPAT_2 (OP_6E0 ());
596 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
599 "mulu r<reg1>, r<reg2>, r<reg3>"
601 COMPAT_2 (OP_22207E0 ());
604 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
607 "mulu <imm9>, r<reg2>, r<reg3>"
609 COMPAT_2 (OP_24207E0 ());
615 0000000000000000:I:::nop
618 /* do nothing, trace nothing */
624 rrrrr,000001,RRRRR:I:::not
625 "not r<reg1>, r<reg2>"
633 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
634 "not1 <bit3>, <disp16>[r<reg1>]"
636 COMPAT_2 (OP_47C0 ());
639 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
642 "not1 r<reg2>, r<reg1>"
644 COMPAT_2 (OP_E207E0 ());
650 rrrrr,001000,RRRRR:I:::or
651 "or r<reg1>, r<reg2>"
653 COMPAT_1 (OP_100 ());
659 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
660 "ori <uimm16>, r<reg1>, r<reg2>"
662 COMPAT_2 (OP_680 ());
668 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
671 "prepare <list12>, <imm5>"
676 trace_input ("prepare", OP_PUSHPOP1, 0);
678 /* Store the registers with lower number registers being placed at
680 for (i = 0; i < 12; i++)
681 if ((OP[3] & (1 << type1_regs[ i ])))
684 store_mem (SP, 4, State.regs[ 20 + i ]);
687 SP -= (OP[3] & 0x3e) << 1;
689 trace_output (OP_PUSHPOP1);
693 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
696 "prepare <list12>, <imm5>, sp"
698 COMPAT_2 (OP_30780 ());
701 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
704 "prepare <list12>, <imm5>, <uimm16>"
706 COMPAT_2 (OP_B0780 ());
709 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
712 "prepare <list12>, <imm5>, <uimm16>"
714 COMPAT_2 (OP_130780 ());
717 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
720 "prepare <list12>, <imm5>, <uimm32>"
722 COMPAT_2 (OP_1B0780 ());
728 0000011111100000 + 0000000101000000:X:::reti
736 else if ((PSW & PSW_NP))
752 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
753 "sar r<reg1>, r<reg2>"
755 COMPAT_2 (OP_A007E0 ());
758 rrrrr,010101,iiiii:II:::sar
759 "sar <imm5>, r<reg2>"
761 COMPAT_1 (OP_2A0 ());
767 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
770 "sasf %s<cccc>, r<reg2>"
772 COMPAT_2 (OP_20007E0 ());
779 rrrrr!0,000110,RRRRR:I:::satadd
780 "satadd r<reg1>, r<reg2>"
785 rrrrr!0,010001,iiiii:II:::satadd
786 "satadd <imm5>, r<reg2>"
788 COMPAT_1 (OP_220 ());
794 rrrrr!0,000101,RRRRR:I:::satsub
795 "satsub r<reg1>, r<reg2>"
803 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
804 "satsubi <simm16>, r<reg1>, r<reg2>"
806 COMPAT_2 (OP_660 ());
812 rrrrr!0,000100,RRRRR:I:::satsubr
813 "satsubr r<reg1>, r<reg2>"
821 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
822 "setf %s<cccc>, r<reg2>"
824 COMPAT_2 (OP_7E0 ());
830 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
831 "set1 <bit3>, <disp16>[r<reg1>]"
833 COMPAT_2 (OP_7C0 ());
836 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
839 "set1 r<reg2>, [r<reg1>]"
841 COMPAT_2 (OP_E007E0 ());
847 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
848 "shl r<reg1>, r<reg2>"
850 COMPAT_2 (OP_C007E0 ());
853 rrrrr,010110,iiiii:II:::shl
854 "shl <imm5>, r<reg2>"
856 COMPAT_1 (OP_2C0 ());
862 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
863 "shr r<reg1>, r<reg2>"
865 COMPAT_2 (OP_8007E0 ());
868 rrrrr,010100,iiiii:II:::shr
869 "shr <imm5>, r<reg2>"
871 COMPAT_1 (OP_280 ());
877 rrrrr,0110,ddddddd:IV:::sld.b
878 "sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
879 "sld.b <disp7>[ep], r<reg2>"
881 unsigned32 addr = EP + disp7;
882 unsigned32 result = load_mem (addr, 1);
886 TRACE_LD_NAME ("sld.bu", addr, result);
890 result = EXTEND8 (result);
892 TRACE_LD (addr, result);
896 rrrrr,1000,ddddddd:IV:::sld.h
897 "sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
898 "sld.h <disp8>[ep], r<reg2>"
900 unsigned32 addr = EP + disp8;
901 unsigned32 result = load_mem (addr, 2);
905 TRACE_LD_NAME ("sld.hu", addr, result);
909 result = EXTEND16 (result);
911 TRACE_LD (addr, result);
915 rrrrr,1010,dddddd,0:IV:::sld.w
916 "sld.w <disp8>[ep], r<reg2>"
918 unsigned32 addr = EP + disp8;
919 unsigned32 result = load_mem (addr, 4);
921 TRACE_LD (addr, result);
924 rrrrr!0,0000110,dddd:IV:::sld.bu
927 "sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
928 "sld.bu <disp4>[ep], r<reg2>"
930 unsigned32 addr = EP + disp4;
931 unsigned32 result = load_mem (addr, 1);
934 result = EXTEND8 (result);
936 TRACE_LD_NAME ("sld.b", addr, result);
941 TRACE_LD (addr, result);
945 rrrrr!0,0000111,dddd:IV:::sld.hu
948 "sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
949 "sld.hu <disp5>[ep], r<reg2>"
951 unsigned32 addr = EP + disp5;
952 unsigned32 result = load_mem (addr, 2);
955 result = EXTEND16 (result);
957 TRACE_LD_NAME ("sld.h", addr, result);
962 TRACE_LD (addr, result);
968 rrrrr,0111,ddddddd:IV:::sst.b
969 "sst.b r<reg2>, <disp7>[ep]"
971 COMPAT_1 (OP_380 ());
974 rrrrr,1001,ddddddd:IV:::sst.h
975 "sst.h r<reg2>, <disp8>[ep]"
977 COMPAT_1 (OP_480 ());
980 rrrrr,1010,dddddd,1:IV:::sst.w
981 "sst.w r<reg2>, <disp8>[ep]"
983 COMPAT_1 (OP_501 ());
989 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
990 "st.b r<reg2>, <disp16>[r<reg1>]"
992 COMPAT_2 (OP_740 ());
995 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
996 "st.h r<reg2>, <disp16>[r<reg1>]"
998 COMPAT_2 (OP_760 ());
1001 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1002 "st.w r<reg2>, <disp16>[r<reg1>]"
1004 COMPAT_2 (OP_10760 ());
1010 rrrrr,111111,regID + 0000000001000000:IX:::stsr
1011 "stsr s<regID>, r<reg2>"
1013 TRACE_ALU_INPUT1 (SR[regID]);
1014 GR[reg2] = SR[regID];
1015 TRACE_ALU_RESULT (GR[reg2]);
1021 rrrrr,001101,RRRRR:I:::sub
1022 "sub r<reg1>, r<reg2>"
1024 COMPAT_1 (OP_1A0 ());
1030 rrrrr,001100,RRRRR:I:::subr
1031 "subr r<reg1>, r<reg2>"
1033 COMPAT_1 (OP_180 ());
1039 00000000010,RRRRR:I:::switch
1046 trace_input ("switch", OP_REG, 0);
1047 adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1048 nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1049 trace_output (OP_REG);
1054 00000000101,RRRRR:I:::sxb
1059 TRACE_ALU_INPUT1 (GR[reg1]);
1060 GR[reg1] = EXTEND8 (GR[reg1]);
1061 TRACE_ALU_RESULT (GR[reg1]);
1065 00000000111,RRRRR:I:::sxh
1070 TRACE_ALU_INPUT1 (GR[reg1]);
1071 GR[reg1] = EXTEND16 (GR[reg1]);
1072 TRACE_ALU_RESULT (GR[reg1]);
1078 00000111111,iiiii + 0000000100000000:X:::trap
1081 COMPAT_2 (OP_10007E0 ());
1087 rrrrr,001011,RRRRR:I:::tst
1088 "tst r<reg1>, r<reg2>"
1090 COMPAT_1 (OP_160 ());
1096 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1097 "tst1 <bit3>, <disp16>[r<reg1>]"
1099 COMPAT_2 (OP_C7C0 ());
1102 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1105 "tst1 r<reg2>, [r<reg1>]"
1107 COMPAT_2 (OP_E607E0 ());
1113 rrrrr,001001,RRRRR:I:::xor
1114 "xor r<reg1>, r<reg2>"
1116 COMPAT_1 (OP_120 ());
1122 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1123 "xori <uimm16>, r<reg1>, r<reg2>"
1125 COMPAT_2 (OP_6A0 ());
1131 00000000100,RRRRR:I:::zxb
1136 TRACE_ALU_INPUT1 (GR[reg1]);
1137 GR[reg1] = GR[reg1] & 0xff;
1138 TRACE_ALU_RESULT (GR[reg1]);
1142 00000000110,RRRRR:I:::zxh
1147 TRACE_ALU_INPUT1 (GR[reg1]);
1148 GR[reg1] = GR[reg1] & 0xffff;
1149 TRACE_ALU_RESULT (GR[reg1]);
1153 // Right field must be zero so that it doesn't clash with DIVH
1154 // Left field must be non-zero so that it doesn't clash with SWITCH
1155 11111,000010,00000:I:::break
1157 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1161 // New breakpoint: 0x7E0 0x7E0
1162 00000,111111,00000 + 00000,11111,100000:X:::ilgop
1164 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1168 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1170 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1175 signed32 divide_this;
1176 boolean overflow = false;
1179 trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
1181 divide_by = EXTEND16 (State.regs[ reg1 ]);
1182 divide_this = State.regs[ reg2 ];
1184 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1186 State.regs[ reg2 ] = quotient;
1187 State.regs[ reg3 ] = remainder;
1189 /* Set condition codes. */
1190 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1192 if (overflow) PSW |= PSW_OV;
1193 if (quotient == 0) PSW |= PSW_Z;
1194 if (quotient < 0) PSW |= PSW_S;
1196 trace_output (OP_IMM_REG_REG_REG);
1202 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1204 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1209 signed32 divide_this;
1210 boolean overflow = false;
1213 trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
1215 divide_by = State.regs[ reg1 ] & 0xffff;
1216 divide_this = State.regs[ reg2 ];
1218 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1220 State.regs[ reg2 ] = quotient;
1221 State.regs[ reg3 ] = remainder;
1223 /* Set condition codes. */
1224 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1226 if (overflow) PSW |= PSW_OV;
1227 if (quotient == 0) PSW |= PSW_Z;
1228 if (quotient & 0x80000000) PSW |= PSW_S;
1230 trace_output (OP_IMM_REG_REG_REG);
1236 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1238 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1243 signed32 divide_this;
1244 boolean overflow = false;
1247 trace_input ("divn", OP_IMM_REG_REG_REG, 0);
1249 divide_by = State.regs[ reg1 ];
1250 divide_this = State.regs[ reg2 ];
1252 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1254 State.regs[ reg2 ] = quotient;
1255 State.regs[ reg3 ] = remainder;
1257 /* Set condition codes. */
1258 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1260 if (overflow) PSW |= PSW_OV;
1261 if (quotient == 0) PSW |= PSW_Z;
1262 if (quotient < 0) PSW |= PSW_S;
1264 trace_output (OP_IMM_REG_REG_REG);
1270 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1272 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1277 signed32 divide_this;
1278 boolean overflow = false;
1281 trace_input ("divun", OP_IMM_REG_REG_REG, 0);
1283 divide_by = State.regs[ reg1 ];
1284 divide_this = State.regs[ reg2 ];
1286 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1288 State.regs[ reg2 ] = quotient;
1289 State.regs[ reg3 ] = remainder;
1291 /* Set condition codes. */
1292 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1294 if (overflow) PSW |= PSW_OV;
1295 if (quotient == 0) PSW |= PSW_Z;
1296 if (quotient & 0x80000000) PSW |= PSW_S;
1298 trace_output (OP_IMM_REG_REG_REG);
1304 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1306 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1308 COMPAT_2 (OP_18007E0 ());
1314 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1316 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1318 COMPAT_2 (OP_18207E0 ());
1324 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1326 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1328 COMPAT_2 (OP_1C007E0 ());
1334 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1336 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1338 COMPAT_2 (OP_1C207E0 ());
1344 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1351 trace_input ("pushml", OP_PUSHPOP3, 0);
1353 /* Store the registers with lower number registers being placed at
1354 higher addresses. */
1356 for (i = 0; i < 15; i++)
1357 if ((OP[3] & (1 << type3_regs[ i ])))
1360 store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
1363 if (OP[3] & (1 << 3))
1367 store_mem (SP & ~ 3, 4, PSW);
1370 if (OP[3] & (1 << 19))
1374 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
1376 store_mem ((SP + 4) & ~ 3, 4, FEPC);
1377 store_mem ( SP & ~ 3, 4, FEPSW);
1381 store_mem ((SP + 4) & ~ 3, 4, EIPC);
1382 store_mem ( SP & ~ 3, 4, EIPSW);
1386 trace_output (OP_PUSHPOP2);
1392 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1396 COMPAT_2 (OP_307E0 ());
1402 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1406 COMPAT_2 (OP_107F0 ());
1412 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1416 COMPAT_2 (OP_307F0 ());