1 :option::insn-bit-size:16
5 :option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
7 :option::format-names:XI,XII,XIII
9 # start-sanitize-v850eq
10 :option::format-names:XIV,XV
12 :option::format-names:Z
17 # start-sanitize-v850e
18 :option::multi-sim:true
22 # start-sanitize-v850eq
23 :option::multi-sim:true
24 :model::v850eq:v850eq:
31 :cache::unsigned:reg1:RRRRR:(RRRRR)
32 :cache::unsigned:reg2:rrrrr:(rrrrr)
33 :cache::unsigned:reg3:wwwww:(wwwww)
34 :cache::unsigned:regID:rrrrr:(rrrrr)
36 :cache::unsigned:disp4:dddd:(dddd)
37 # start-sanitize-v850e
38 :cache::unsigned:disp5:dddd:(dddd << 1)
40 :cache::unsigned:disp7:ddddddd:ddddddd
41 :cache::unsigned:disp8:ddddddd:(ddddddd << 1)
42 :cache::unsigned:disp8:dddddd:(dddddd << 2)
43 :cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
44 :cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
45 :cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
46 :cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
47 :cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
49 :cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
50 :cache::unsigned:imm6:iiiiii:iiiiii
51 :cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
52 # start-sanitize-v850eq
53 :cache::unsigned:imm5:iiii:(32 - (iiii << 1))
55 :cache::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
56 :cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
57 :cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
58 # start-sanitize-v850e
59 :cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
62 :cache::unsigned:vector:iiiii:iiiii
64 # start-sanitize-v850e
65 :cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
66 :cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
69 :cache::unsigned:bit3:bbb:bbb
72 // What do we do with an illegal instruction?
75 sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
77 sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
84 rrrrr,001110,RRRRR:I:::add
85 "add r<reg1>, r<reg2>"
90 rrrrr,010010,iiiii:II:::add
99 rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
100 "addi <simm16>, r<reg1>, r<reg2>"
102 COMPAT_2 (OP_600 ());
108 rrrrr,001010,RRRRR:I:::and
109 "and r<reg1>, r<reg2>"
111 COMPAT_1 (OP_140 ());
117 rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
118 "andi <uimm16>, r<reg1>, r<reg2>"
120 COMPAT_2 (OP_6C0 ());
126 // ddddd,1011,ddd,cccc:III:::Bcond
129 ddddd,1011,ddd,0000:III:::bv
132 COMPAT_1 (OP_580 ());
135 ddddd,1011,ddd,0001:III:::bl
138 COMPAT_1 (OP_581 ());
141 ddddd,1011,ddd,0010:III:::be
144 COMPAT_1 (OP_582 ());
147 ddddd,1011,ddd,0011:III:::bnh
150 COMPAT_1 (OP_583 ());
153 ddddd,1011,ddd,0100:III:::bn
156 COMPAT_1 (OP_584 ());
159 ddddd,1011,ddd,0101:III:::br
162 COMPAT_1 (OP_585 ());
165 ddddd,1011,ddd,0110:III:::blt
168 COMPAT_1 (OP_586 ());
171 ddddd,1011,ddd,0111:III:::ble
174 COMPAT_1 (OP_587 ());
177 ddddd,1011,ddd,1000:III:::bnv
180 COMPAT_1 (OP_588 ());
183 ddddd,1011,ddd,1001:III:::bnl
186 COMPAT_1 (OP_589 ());
189 ddddd,1011,ddd,1010:III:::bne
192 COMPAT_1 (OP_58A ());
195 ddddd,1011,ddd,1011:III:::bh
198 COMPAT_1 (OP_58B ());
201 ddddd,1011,ddd,1100:III:::bp
204 COMPAT_1 (OP_58C ());
207 ddddd,1011,ddd,1101:III:::bsa
210 COMPAT_1 (OP_58D ());
213 ddddd,1011,ddd,1110:III:::bge
216 COMPAT_1 (OP_58E ());
219 ddddd,1011,ddd,1111:III:::bgt
222 COMPAT_1 (OP_58F ());
227 // start-sanitize-v850e
229 rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
231 // start-sanitize-v850eq
233 // end-sanitize-v850eq
234 "bsh r<reg2>, r<reg3>"
236 COMPAT_2 (OP_34207E0 ());
241 // end-sanitize-v850e
242 // start-sanitize-v850e
244 rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
246 // start-sanitize-v850eq
248 // end-sanitize-v850eq
251 COMPAT_2 (OP_34007E0 ());
256 // end-sanitize-v850e
257 // start-sanitize-v850e
259 0000001000,iiiiii:II:::callt
261 // start-sanitize-v850eq
263 // end-sanitize-v850eq
268 trace_input ("callt", OP_LOAD16, 1);
271 adr = CTBP + ((OP[3] & 0x3f) << 1);
272 nia = CTBP + load_mem (adr, 1);
273 trace_output (OP_LOAD16);
278 // end-sanitize-v850e
280 10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
281 "clr1 <bit3>, <disp16>[r<reg1>]"
283 COMPAT_2 (OP_87C0 ());
286 // start-sanitize-v850e
287 rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
289 // start-sanitize-v850eq
291 // end-sanitize-v850eq
292 "clr1 r<reg2>, [r<reg1>]"
294 COMPAT_2 (OP_E407E0 ());
299 // end-sanitize-v850e
300 // start-sanitize-v850e
302 0000011111100000 + 0000000101000100:X:::ctret
304 // start-sanitize-v850eq
306 // end-sanitize-v850eq
309 COMPAT_2 (OP_14407E0 ());
314 // end-sanitize-v850e
315 // start-sanitize-v850e
317 rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
319 // start-sanitize-v850eq
321 // end-sanitize-v850eq
322 "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
324 COMPAT_2 (OP_32007E0 ());
327 // end-sanitize-v850e
328 // start-sanitize-v850e
329 rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
331 // start-sanitize-v850eq
333 // end-sanitize-v850eq
334 "cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
336 COMPAT_2 (OP_30007E0 ());
341 // end-sanitize-v850e
343 rrrrr,001111,RRRRR:I:::cmp
344 "cmp r<reg1>, r<reg2>"
346 COMPAT_1 (OP_1E0 ());
349 rrrrr,010011,iiiii:II:::cmp
350 "cmp <imm5>, r<reg2>"
352 COMPAT_1 (OP_260 ());
358 0000011111100000 + 0000000101100000:X:::di
361 COMPAT_2 (OP_16007E0 ());
366 // start-sanitize-v850e
368 // 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
369 // "dispose <imm5>, <list12>"
370 0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
372 // start-sanitize-v850eq
374 // end-sanitize-v850eq
375 "dispose <imm5>, <list12>":RRRRR == 0
376 "dispose <imm5>, <list12>, [reg1]"
381 trace_input ("dispose", OP_PUSHPOP1, 0);
383 SP += (OP[3] & 0x3e) << 1;
385 /* Load the registers with lower number registers being retrieved
386 from higher addresses. */
388 if ((OP[3] & (1 << type1_regs[ i ])))
390 State.regs[ 20 + i ] = load_mem (SP, 4);
394 if ((OP[3] & 0x1f0000) != 0)
396 nia = State.regs[ (OP[3] >> 16) & 0x1f];
399 trace_output (OP_PUSHPOP1);
404 // end-sanitize-v850e
405 // start-sanitize-v850e
407 rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
409 "div r<reg1>, r<reg2>, r<reg3>"
411 COMPAT_2 (OP_2C007E0 ());
417 // end-sanitize-v850e
419 rrrrr!0,000010,RRRRR!0:I:::divh
420 "divh r<reg1>, r<reg2>"
425 // start-sanitize-v850e
426 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
428 "divh r<reg1>, r<reg2>, r<reg3>"
430 COMPAT_2 (OP_28007E0 ());
435 // end-sanitize-v850e
436 // start-sanitize-v850e
438 rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
440 "divhu r<reg1>, r<reg2>, r<reg3>"
442 COMPAT_2 (OP_28207E0 ());
447 // end-sanitize-v850e
448 // start-sanitize-v850e
450 rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
452 "divu r<reg1>, r<reg2>, r<reg3>"
454 COMPAT_2 (OP_2C207E0 ());
459 // end-sanitize-v850e
461 1000011111100000 + 0000000101100000:X:::ei
464 COMPAT_2 (OP_16087E0 ());
470 0000011111100000 + 0000000100100000:X:::halt
473 COMPAT_2 (OP_12007E0 ());
478 // start-sanitize-v850e
480 rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
482 // start-sanitize-v850eq
484 // end-sanitize-v850eq
485 "hsw r<reg2>, r<reg3>"
487 COMPAT_2 (OP_34407E0 ());
492 // end-sanitize-v850e
494 rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
495 "jarl <disp22>, r<reg2>"
497 COMPAT_2 (OP_780 ());
503 00000000011,RRRRR:I:::jmp
507 trace_input ("jmp", OP_REG, 0);
508 nia = State.regs[ reg1 ];
509 trace_output (OP_REG);
515 0000011110,dddddd + ddddddddddddddd,0:V:::jr
518 COMPAT_2 (OP_780 ());
524 rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
525 "ld.b <disp16>[r<reg1>, r<reg2>"
527 COMPAT_2 (OP_700 ());
530 rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
531 "ld.h <disp16>[r<reg1>], r<reg2>"
533 COMPAT_2 (OP_720 ());
536 rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
537 "ld.w <disp16>[r<reg1>], r<reg2>"
539 COMPAT_2 (OP_10720 ());
542 // start-sanitize-v850e
543 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
545 // start-sanitize-v850eq
547 // end-sanitize-v850eq
548 "ld.bu <disp16>[r<reg1>], r<reg2>"
550 COMPAT_2 (OP_10780 ());
553 // end-sanitize-v850e
554 // start-sanitize-v850e
555 rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
557 // start-sanitize-v850eq
559 // end-sanitize-v850eq
560 "ld.hu <disp16>[r<reg1>], r<reg2>"
562 COMPAT_2 (OP_107E0 ());
566 // end-sanitize-v850e
568 //rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
569 //"ldsr r<reg2>, r<regID>"
571 // COMPAT_2 (OP_2007E0 ());
573 rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
574 "ldsr r<reg1>, r<regID>"
577 trace_input ("ldsr", OP_LDSR, 0);
579 if (&PSW == &State.sregs[ regID ])
580 PSW = (State.regs[ reg1 ] & (CPU)->psw_mask);
582 State.sregs[ regID ] = State.regs[ reg1 ];
584 trace_output (OP_LDSR);
590 rrrrr!0,000000,RRRRR:I:::mov
591 "mov r<reg1>, r<reg2>"
596 rrrrr!0,010000,iiiii:II:::mov
597 "mov <imm5>, r<reg2>"
599 COMPAT_1 (OP_200 ());
602 // start-sanitize-v850e
603 00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
605 // start-sanitize-v850eq
607 // end-sanitize-v850eq
608 "mov <imm32>, r<reg1>"
611 trace_input ("mov", OP_IMM_REG, 4);
612 State.regs[ OP[0] ] = load_mem (PC + 2, 4);
613 trace_output (OP_IMM_REG);
618 // end-sanitize-v850e
620 rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
621 "movea <simm16>, r<reg1>, r<reg2>"
623 TRACE_ALU_INPUT2 (GR[reg1], simm16);
624 GR[reg2] = GR[reg1] + simm16;
625 TRACE_ALU_RESULT (GR[reg2]);
631 rrrrr!0,110010,RRRRR + iiiiiiiiiiiiiiii:VI:::movhi
632 "movhi <uimm16>, r<reg1>, r<reg2>"
634 COMPAT_2 (OP_640 ());
639 // start-sanitize-v850e
641 rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
643 // start-sanitize-v850eq
645 // end-sanitize-v850eq
646 "mul r<reg1>, r<reg2>, r<reg3>"
648 COMPAT_2 (OP_22007E0 ());
651 // end-sanitize-v850e
652 // start-sanitize-v850e
653 rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
655 // start-sanitize-v850eq
657 // end-sanitize-v850eq
658 "mul <imm9>, r<reg2>, r<reg3>"
660 COMPAT_2 (OP_24007E0 ());
665 // end-sanitize-v850e
667 rrrrr!0,000111,RRRRR:I:::mulh
668 "mulh r<reg1>, r<reg2>"
673 rrrrr!0,010111,iiiii:II:::mulh
674 "mulh <imm5>, r<reg2>"
676 COMPAT_1 (OP_2E0 ());
682 rrrrr!0,110111,RRRRR + iiiiiiiiiiiiiiii:VI:::mulhi
683 "mulhi <uimm16>, r<reg1>, r<reg2>"
685 COMPAT_2 (OP_6E0 ());
690 // start-sanitize-v850e
692 rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
694 // start-sanitize-v850eq
696 // end-sanitize-v850eq
697 "mulu r<reg1>, r<reg2>, r<reg3>"
699 COMPAT_2 (OP_22207E0 ());
702 rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
704 // start-sanitize-v850eq
706 // end-sanitize-v850eq
707 "mulu <imm9>, r<reg2>, r<reg3>"
709 COMPAT_2 (OP_24207E0 ());
714 // end-sanitize-v850e
716 0000000000000000:I:::nop
725 rrrrr,000001,RRRRR:I:::not
726 "not r<reg1>, r<reg2>"
734 01,bbb,111110,RRRRR + dddddddddddddddd:VIII:::not1
735 "not1 <bit3>, <disp16>[r<reg1>]"
737 COMPAT_2 (OP_47C0 ());
740 // start-sanitize-v850e
741 rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
743 // start-sanitize-v850eq
745 // end-sanitize-v850eq
746 "not1 r<reg2>, r<reg1>"
748 COMPAT_2 (OP_E207E0 ());
753 // end-sanitize-v850e
755 rrrrr,001000,RRRRR:I:::or
756 "or r<reg1>, r<reg2>"
758 COMPAT_1 (OP_100 ());
764 rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
765 "ori <uimm16>, r<reg1>, r<reg2>"
767 COMPAT_2 (OP_680 ());
772 // start-sanitize-v850e
774 0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
776 // start-sanitize-v850eq
778 // end-sanitize-v850eq
779 "prepare <list12>, <imm5>"
784 trace_input ("prepare", OP_PUSHPOP1, 0);
786 /* Store the registers with lower number registers being placed at
788 for (i = 0; i < 12; i++)
789 if ((OP[3] & (1 << type1_regs[ i ])))
792 store_mem (SP, 4, State.regs[ 20 + i ]);
795 SP -= (OP[3] & 0x3e) << 1;
797 trace_output (OP_PUSHPOP1);
801 0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
803 // start-sanitize-v850eq
805 // end-sanitize-v850eq
806 "prepare <list12>, <imm5>, sp"
808 COMPAT_2 (OP_30780 ());
811 0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
813 // start-sanitize-v850eq
815 // end-sanitize-v850eq
816 "prepare <list12>, <imm5>, <uimm16>"
818 COMPAT_2 (OP_B0780 ());
821 0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
823 // start-sanitize-v850eq
825 // end-sanitize-v850eq
826 "prepare <list12>, <imm5>, <uimm16>"
828 COMPAT_2 (OP_130780 ());
831 0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
833 // start-sanitize-v850eq
835 // end-sanitize-v850eq
836 "prepare <list12>, <imm5>, <uimm32>"
838 COMPAT_2 (OP_1B0780 ());
843 // end-sanitize-v850e
845 0000011111100000 + 0000000101000000:X:::reti
848 COMPAT_2 (OP_14007E0 ());
854 rrrrr,111111,RRRRR + 0000000010100000:IX:::sar
855 "sar r<reg1>, r<reg2>"
857 COMPAT_2 (OP_A007E0 ());
860 rrrrr,010101,iiiii:II:::sar
861 "sar <imm5>, r<reg2>"
863 COMPAT_1 (OP_2A0 ());
868 // start-sanitize-v850e
870 rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
872 // start-sanitize-v850eq
874 // end-sanitize-v850eq
875 "sasf <cccc>, r<reg2>"
877 COMPAT_2 (OP_20007E0 ());
883 // end-sanitize-v850e
885 rrrrr!0,000110,RRRRR:I:::satadd
886 "satadd r<reg1>, r<reg2>"
891 rrrrr!0,010001,iiiii:II:::satadd
892 "satadd <imm5>, r<reg2>"
894 COMPAT_1 (OP_220 ());
900 rrrrr!0,000101,RRRRR:I:::satsub
901 "satsub r<reg1>, r<reg2>"
909 rrrrr!0,110011,RRRRR + iiiiiiiiiiiiiiii:VI:::satsubi
910 "satsubi <simm16>, r<reg1>, r<reg2>"
912 COMPAT_2 (OP_660 ());
918 rrrrr!0,000100,RRRRR:I:::satsubr
919 "satsubr r<reg1>, r<reg2>"
927 rrrrr,1111110,cccc + 0000000000000000:IX:::setf
928 "setf <cccc>, r<reg2>"
930 COMPAT_2 (OP_7E0 ());
936 00,bbb,111110,RRRRR + dddddddddddddddd:VIII:::set1
937 "set1 <bit3>, <disp16>[r<reg1>]"
939 COMPAT_2 (OP_7C0 ());
942 // start-sanitize-v850e
943 rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
945 // start-sanitize-v850eq
947 // end-sanitize-v850eq
948 "set1 r<reg2>, [r<reg1>]"
950 COMPAT_2 (OP_E007E0 ());
955 // end-sanitize-v850e
957 rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
958 "shl r<reg1>, r<reg2>"
960 COMPAT_2 (OP_C007E0 ());
963 rrrrr,010110,iiiii:II:::shl
964 "shl <imm5>, r<reg2>"
966 COMPAT_1 (OP_2C0 ());
972 rrrrr,111111,RRRRR + 0000000010000000:IX:::shr
973 "shr r<reg1>, r<reg2>"
975 COMPAT_2 (OP_8007E0 ());
978 rrrrr,010100,iiiii:II:::shr
979 "shr <imm5>, r<reg2>"
981 COMPAT_1 (OP_280 ());
987 rrrrr,0110,ddddddd:IV:::sld.b
988 "sld.b <disp7>[ep], r<reg2>"
990 COMPAT_1 (OP_300 ());
993 rrrrr,1000,ddddddd:IV:::sld.h
994 "sld.h <disp8>[ep], r<reg2>"
996 COMPAT_1 (OP_400 ());
999 rrrrr,1010,dddddd,0:IV:::sld.w
1000 "sld.w <disp8>[ep], r<reg2>"
1002 COMPAT_1 (OP_500 ());
1005 // start-sanitize-v850e
1006 rrrrr!0,0000110,dddd:IV:::sld.bu
1007 "sld.bu <disp4>[ep], r<reg2>"
1009 unsigned long result;
1012 result = load_mem (State.regs[30] + disp4, 1);
1014 /* start-sanitize-v850eq */
1016 trace_input ("sld.b", OP_LOAD16, 1);
1018 State.regs[ reg2 ] = EXTEND8 (result);
1020 /* end-sanitize-v850eq */
1021 trace_input ("sld.bu", OP_LOAD16, 1);
1022 State.regs[ reg2 ] = result;
1023 /* start-sanitize-v850eq */
1025 /* end-sanitize-v850eq */
1026 trace_output (OP_LOAD16);
1029 // end-sanitize-v850e
1030 // start-sanitize-v850e
1031 rrrrr!0,0000111,dddd:IV:::sld.hu
1032 "sld.hu <disp5>[ep], r<reg2>"
1034 COMPAT_1 (OP_70 ());
1037 // end-sanitize-v850e
1041 rrrrr,0111,ddddddd:IV:::sst.b
1042 "sst.b r<reg2>, <disp7>[ep]"
1044 COMPAT_1 (OP_380 ());
1047 rrrrr,1001,ddddddd:IV:::sst.h
1048 "sst.h r<reg2>, <disp8>[ep]"
1050 COMPAT_1 (OP_480 ());
1053 rrrrr,1010,dddddd,1:IV:::sst.w
1054 "sst.w r<reg2>, <disp8>[ep]"
1056 COMPAT_1 (OP_501 ());
1062 rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
1063 "st.b r<reg2>, <disp16>[r<reg1>]"
1065 COMPAT_2 (OP_740 ());
1068 rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
1069 "st.h r<reg2>, <disp16>[r<reg1>]"
1071 COMPAT_2 (OP_760 ());
1074 rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
1075 "st.w r<reg2>, <disp16>[r<reg1>]"
1077 COMPAT_2 (OP_10760 ());
1083 //rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
1084 //"stsr r<regID>, r<reg2>"
1086 // COMPAT_2 (OP_4007E0 ());
1088 rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
1089 "stsr r<regID>, r<reg1>"
1092 GR[reg1] = SR[regID];
1093 TRACE_ALU_RESULT (GR[reg1]);
1099 rrrrr,001101,RRRRR:I:::sub
1100 "sub r<reg1>, r<reg2>"
1102 COMPAT_1 (OP_1A0 ());
1108 rrrrr,001100,RRRRR:I:::subr
1109 "subr r<reg1>, r<reg2>"
1111 COMPAT_1 (OP_180 ());
1116 // start-sanitize-v850e
1118 00000000010,RRRRR:I:::switch
1120 // start-sanitize-v850eq
1122 // end-sanitize-v850eq
1127 trace_input ("switch", OP_REG, 0);
1128 adr = (cia + 2) + (State.regs[ reg1 ] << 1);
1129 nia = (cia + 2) + (EXTEND16 (load_mem (adr, 2)) << 1);
1130 trace_output (OP_REG);
1135 // end-sanitize-v850e
1136 // start-sanitize-v850e
1138 00000000101,RRRRR:I:::sxb
1140 // start-sanitize-v850eq
1142 // end-sanitize-v850eq
1145 TRACE_ALU_INPUT1 (GR[reg1]);
1146 GR[reg1] = EXTEND8 (GR[reg1]);
1147 TRACE_ALU_RESULT (GR[reg1]);
1152 // end-sanitize-v850e
1153 // start-sanitize-v850e
1155 00000000111,RRRRR:I:::sxh
1157 // start-sanitize-v850eq
1159 // end-sanitize-v850eq
1162 TRACE_ALU_INPUT1 (GR[reg1]);
1163 GR[reg1] = EXTEND16 (GR[reg1]);
1164 TRACE_ALU_RESULT (GR[reg1]);
1169 // end-sanitize-v850e
1171 00000111111,iiiii + 0000000100000000:X:::trap
1174 COMPAT_2 (OP_10007E0 ());
1180 rrrrr,001011,RRRRR:I:::tst
1181 "tst r<reg1>, r<reg2>"
1183 COMPAT_1 (OP_160 ());
1189 11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
1190 "tst1 <bit3>, <disp16>[r<reg1>]"
1192 COMPAT_2 (OP_C7C0 ());
1195 // start-sanitize-v850e
1196 rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
1198 // start-sanitize-v850eq
1200 // end-sanitize-v850eq
1201 "tst1 r<reg2>, [r<reg1>]"
1203 COMPAT_2 (OP_E607E0 ());
1208 // end-sanitize-v850e
1210 rrrrr,001001,RRRRR:I:::xor
1211 "xor r<reg1>, r<reg2>"
1213 COMPAT_1 (OP_120 ());
1219 rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
1220 "xori <uimm16>, r<reg1>, r<reg2>"
1222 COMPAT_2 (OP_6A0 ());
1227 // start-sanitize-v850e
1229 00000000100,RRRRR:I:::zxb
1231 // start-sanitize-v850eq
1233 // end-sanitize-v850eq
1236 TRACE_ALU_INPUT1 (GR[reg1]);
1237 GR[reg1] = GR[reg1] & 0xff;
1238 TRACE_ALU_RESULT (GR[reg1]);
1243 // end-sanitize-v850e
1244 // start-sanitize-v850e
1246 00000000110,RRRRR:I:::zxh
1248 // start-sanitize-v850eq
1250 // end-sanitize-v850eq
1253 TRACE_ALU_INPUT1 (GR[reg1]);
1254 GR[reg1] = GR[reg1] & 0xffff;
1255 TRACE_ALU_RESULT (GR[reg1]);
1260 // end-sanitize-v850e
1261 // Special - breakpoint - illegal
1262 // Hopefully, in the future, this instruction will go away
1263 1111111111111111 + 1111111111111111:Z:::breakpoint
1266 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1269 // start-sanitize-v850e
1270 // First field could be any nonzero value.
1271 11111,000010,00000:I:::break
1273 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
1276 // end-sanitize-v850e
1279 // start-sanitize-v850eq
1281 rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
1283 "divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1288 signed32 divide_this;
1289 boolean overflow = false;
1292 trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
1294 divide_by = EXTEND16 (State.regs[ reg1 ]);
1295 divide_this = State.regs[ reg2 ];
1297 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1299 State.regs[ reg2 ] = quotient;
1300 State.regs[ reg3 ] = remainder;
1302 /* Set condition codes. */
1303 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1305 if (overflow) PSW |= PSW_OV;
1306 if (quotient == 0) PSW |= PSW_Z;
1307 if (quotient < 0) PSW |= PSW_S;
1309 trace_output (OP_IMM_REG_REG_REG);
1315 rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
1317 "divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1322 signed32 divide_this;
1323 boolean overflow = false;
1326 trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
1328 divide_by = State.regs[ reg1 ] & 0xffff;
1329 divide_this = State.regs[ reg2 ];
1331 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1333 State.regs[ reg2 ] = quotient;
1334 State.regs[ reg3 ] = remainder;
1336 /* Set condition codes. */
1337 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1339 if (overflow) PSW |= PSW_OV;
1340 if (quotient == 0) PSW |= PSW_Z;
1341 if (quotient & 0x80000000) PSW |= PSW_S;
1343 trace_output (OP_IMM_REG_REG_REG);
1349 rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
1351 "divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1356 signed32 divide_this;
1357 boolean overflow = false;
1360 trace_input ("divn", OP_IMM_REG_REG_REG, 0);
1362 divide_by = State.regs[ reg1 ];
1363 divide_this = State.regs[ reg2 ];
1365 divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1367 State.regs[ reg2 ] = quotient;
1368 State.regs[ reg3 ] = remainder;
1370 /* Set condition codes. */
1371 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1373 if (overflow) PSW |= PSW_OV;
1374 if (quotient == 0) PSW |= PSW_Z;
1375 if (quotient < 0) PSW |= PSW_S;
1377 trace_output (OP_IMM_REG_REG_REG);
1383 rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
1385 "divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1390 signed32 divide_this;
1391 boolean overflow = false;
1394 trace_input ("divun", OP_IMM_REG_REG_REG, 0);
1396 divide_by = State.regs[ reg1 ];
1397 divide_this = State.regs[ reg2 ];
1399 divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
1401 State.regs[ reg2 ] = quotient;
1402 State.regs[ reg3 ] = remainder;
1404 /* Set condition codes. */
1405 PSW &= ~(PSW_Z | PSW_S | PSW_OV);
1407 if (overflow) PSW |= PSW_OV;
1408 if (quotient == 0) PSW |= PSW_Z;
1409 if (quotient & 0x80000000) PSW |= PSW_S;
1411 trace_output (OP_IMM_REG_REG_REG);
1417 rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
1419 "sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1421 COMPAT_2 (OP_18007E0 ());
1427 rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
1429 "sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1431 COMPAT_2 (OP_18207E0 ());
1437 rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
1439 "sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
1441 COMPAT_2 (OP_1C007E0 ());
1447 rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
1449 "sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
1451 COMPAT_2 (OP_1C207E0 ());
1457 000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
1464 trace_input ("pushml", OP_PUSHPOP3, 0);
1466 /* Store the registers with lower number registers being placed at
1467 higher addresses. */
1469 for (i = 0; i < 15; i++)
1470 if ((OP[3] & (1 << type3_regs[ i ])))
1473 store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
1476 if (OP[3] & (1 << 3))
1480 store_mem (SP & ~ 3, 4, PSW);
1483 if (OP[3] & (1 << 19))
1487 if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
1489 store_mem ((SP + 4) & ~ 3, 4, FEPC);
1490 store_mem ( SP & ~ 3, 4, FEPSW);
1494 store_mem ((SP + 4) & ~ 3, 4, EIPC);
1495 store_mem ( SP & ~ 3, 4, EIPSW);
1499 trace_output (OP_PUSHPOP2);
1505 000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
1509 COMPAT_2 (OP_307E0 ());
1515 000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
1519 COMPAT_2 (OP_107F0 ());
1525 000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
1529 COMPAT_2 (OP_307F0 ());
1533 // end-sanitize-v850eq