2 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
5 * Author: Nicolas Pitre
6 * Created: Dec 02, 2004
7 * Copyright: MontaVista Software Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
20 #include <sound/ac97_codec.h>
21 #include <sound/pxa2xx-lib.h>
24 #include <mach/hardware.h>
25 #include <mach/regs-ac97.h>
26 #include <mach/pxa2xx-gpio.h>
27 #include <mach/audio.h>
29 static DEFINE_MUTEX(car_mutex
);
30 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq
);
31 static volatile long gsr_bits
;
32 static struct clk
*ac97_clk
;
33 static struct clk
*ac97conf_clk
;
34 static int reset_gpio
;
39 * o Slot 12 read from modem space will hang controller.
40 * o CDONE, SDONE interrupt fails after any slot 12 IO.
42 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
43 * 1 jiffy timeout if interrupt never comes).
49 RESETGPIO_NORMAL_ALTFUNC
53 * set_resetgpio_mode - computes and sets the AC97_RESET gpio mode on PXA
54 * @mode: chosen action
56 * As the PXA27x CPUs suffer from a AC97 bug, a manual control of the reset line
57 * must be done to insure proper work of AC97 reset line. This function
58 * computes the correct gpio_mode for further use by reset functions, and
59 * applied the change through pxa_gpio_mode.
61 static void set_resetgpio_mode(int resetgpio_action
)
66 switch (resetgpio_action
) {
67 case RESETGPIO_NORMAL_ALTFUNC
:
68 if (reset_gpio
== 113)
69 mode
= 113 | GPIO_OUT
| GPIO_DFLT_LOW
;
71 mode
= 95 | GPIO_ALT_FN_1_OUT
;
73 case RESETGPIO_FORCE_LOW
:
74 mode
= reset_gpio
| GPIO_OUT
| GPIO_DFLT_LOW
;
76 case RESETGPIO_FORCE_HIGH
:
77 mode
= reset_gpio
| GPIO_OUT
| GPIO_DFLT_HIGH
;
85 unsigned short pxa2xx_ac97_read(struct snd_ac97
*ac97
, unsigned short reg
)
87 unsigned short val
= -1;
88 volatile u32
*reg_addr
;
90 mutex_lock(&car_mutex
);
92 /* set up primary or secondary codec space */
93 if (cpu_is_pxa25x() && reg
== AC97_GPIO_STATUS
)
94 reg_addr
= ac97
->num
? &SMC_REG_BASE
: &PMC_REG_BASE
;
96 reg_addr
= ac97
->num
? &SAC_REG_BASE
: &PAC_REG_BASE
;
97 reg_addr
+= (reg
>> 1);
99 /* start read access across the ac97 link */
100 GSR
= GSR_CDONE
| GSR_SDONE
;
103 if (reg
== AC97_GPIO_STATUS
)
105 if (wait_event_timeout(gsr_wq
, (GSR
| gsr_bits
) & GSR_SDONE
, 1) <= 0 &&
106 !((GSR
| gsr_bits
) & GSR_SDONE
)) {
107 printk(KERN_ERR
"%s: read error (ac97_reg=%d GSR=%#lx)\n",
108 __func__
, reg
, GSR
| gsr_bits
);
114 GSR
= GSR_CDONE
| GSR_SDONE
;
117 /* but we've just started another cycle... */
118 wait_event_timeout(gsr_wq
, (GSR
| gsr_bits
) & GSR_SDONE
, 1);
120 out
: mutex_unlock(&car_mutex
);
123 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read
);
125 void pxa2xx_ac97_write(struct snd_ac97
*ac97
, unsigned short reg
,
128 volatile u32
*reg_addr
;
130 mutex_lock(&car_mutex
);
132 /* set up primary or secondary codec space */
133 if (cpu_is_pxa25x() && reg
== AC97_GPIO_STATUS
)
134 reg_addr
= ac97
->num
? &SMC_REG_BASE
: &PMC_REG_BASE
;
136 reg_addr
= ac97
->num
? &SAC_REG_BASE
: &PAC_REG_BASE
;
137 reg_addr
+= (reg
>> 1);
139 GSR
= GSR_CDONE
| GSR_SDONE
;
142 if (wait_event_timeout(gsr_wq
, (GSR
| gsr_bits
) & GSR_CDONE
, 1) <= 0 &&
143 !((GSR
| gsr_bits
) & GSR_CDONE
))
144 printk(KERN_ERR
"%s: write error (ac97_reg=%d GSR=%#lx)\n",
145 __func__
, reg
, GSR
| gsr_bits
);
147 mutex_unlock(&car_mutex
);
149 EXPORT_SYMBOL_GPL(pxa2xx_ac97_write
);
152 static inline void pxa_ac97_warm_pxa25x(void)
156 GCR
|= GCR_WARM_RST
| GCR_PRIRDY_IEN
| GCR_SECRDY_IEN
;
157 wait_event_timeout(gsr_wq
, gsr_bits
& (GSR_PCR
| GSR_SCR
), 1);
160 static inline void pxa_ac97_cold_pxa25x(void)
162 GCR
&= GCR_COLD_RST
; /* clear everything but nCRST */
163 GCR
&= ~GCR_COLD_RST
; /* then assert nCRST */
168 GCR
|= GCR_CDONE_IE
|GCR_SDONE_IE
;
169 wait_event_timeout(gsr_wq
, gsr_bits
& (GSR_PCR
| GSR_SCR
), 1);
174 static inline void pxa_ac97_warm_pxa27x(void)
178 /* warm reset broken on Bulverde,
179 so manually keep AC97 reset high */
180 set_resetgpio_mode(RESETGPIO_FORCE_HIGH
);
183 set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC
);
187 static inline void pxa_ac97_cold_pxa27x(void)
189 GCR
&= GCR_COLD_RST
; /* clear everything but nCRST */
190 GCR
&= ~GCR_COLD_RST
; /* then assert nCRST */
194 /* PXA27x Developers Manual section 13.5.2.2.1 */
195 clk_enable(ac97conf_clk
);
197 clk_disable(ac97conf_clk
);
204 static inline void pxa_ac97_warm_pxa3xx(void)
210 /* Can't use interrupts */
212 while (!((GSR
| gsr_bits
) & (GSR_PCR
| GSR_SCR
)) && timeout
--)
216 static inline void pxa_ac97_cold_pxa3xx(void)
220 /* Hold CLKBPB for 100us */
226 GCR
&= GCR_COLD_RST
; /* clear everything but nCRST */
227 GCR
&= ~GCR_COLD_RST
; /* then assert nCRST */
231 /* Can't use interrupts on PXA3xx */
232 GCR
&= ~(GCR_PRIRDY_IEN
|GCR_SECRDY_IEN
);
234 GCR
= GCR_WARM_RST
| GCR_COLD_RST
;
235 while (!(GSR
& (GSR_PCR
| GSR_SCR
)) && timeout
--)
240 bool pxa2xx_ac97_try_warm_reset(struct snd_ac97
*ac97
)
244 pxa_ac97_warm_pxa25x();
249 pxa_ac97_warm_pxa27x();
254 pxa_ac97_warm_pxa3xx();
259 if (!((GSR
| gsr_bits
) & (GSR_PCR
| GSR_SCR
))) {
260 printk(KERN_INFO
"%s: warm reset timeout (GSR=%#lx)\n",
268 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset
);
270 bool pxa2xx_ac97_try_cold_reset(struct snd_ac97
*ac97
)
274 pxa_ac97_cold_pxa25x();
279 pxa_ac97_cold_pxa27x();
284 pxa_ac97_cold_pxa3xx();
289 if (!((GSR
| gsr_bits
) & (GSR_PCR
| GSR_SCR
))) {
290 printk(KERN_INFO
"%s: cold reset timeout (GSR=%#lx)\n",
298 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset
);
301 void pxa2xx_ac97_finish_reset(struct snd_ac97
*ac97
)
303 GCR
&= ~(GCR_PRIRDY_IEN
|GCR_SECRDY_IEN
);
304 GCR
|= GCR_SDONE_IE
|GCR_CDONE_IE
;
306 EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset
);
308 static irqreturn_t
pxa2xx_ac97_irq(int irq
, void *dev_id
)
318 /* Although we don't use those we still need to clear them
319 since they tend to spuriously trigger when MMC is used
320 (hardware bug? go figure)... */
321 if (cpu_is_pxa27x()) {
334 int pxa2xx_ac97_hw_suspend(void)
336 GCR
|= GCR_ACLINK_OFF
;
337 clk_disable(ac97_clk
);
340 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend
);
342 int pxa2xx_ac97_hw_resume(void)
344 if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
345 pxa_gpio_mode(GPIO31_SYNC_AC97_MD
);
346 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD
);
347 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD
);
348 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD
);
350 if (cpu_is_pxa27x()) {
351 /* Use GPIO 113 or 95 as AC97 Reset on Bulverde */
352 set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC
);
354 clk_enable(ac97_clk
);
357 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume
);
360 int __devinit
pxa2xx_ac97_hw_probe(struct platform_device
*dev
)
363 struct pxa2xx_ac97_platform_data
*pdata
= dev
->dev
.platform_data
;
366 switch (pdata
->reset_gpio
) {
369 reset_gpio
= pdata
->reset_gpio
;
377 dev_err(dev
, "Invalid reset GPIO %d\n",
385 if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
386 pxa_gpio_mode(GPIO31_SYNC_AC97_MD
);
387 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD
);
388 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD
);
389 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD
);
392 if (cpu_is_pxa27x()) {
393 /* Use GPIO 113 as AC97 Reset on Bulverde */
394 set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC
);
395 ac97conf_clk
= clk_get(&dev
->dev
, "AC97CONFCLK");
396 if (IS_ERR(ac97conf_clk
)) {
397 ret
= PTR_ERR(ac97conf_clk
);
403 ac97_clk
= clk_get(&dev
->dev
, "AC97CLK");
404 if (IS_ERR(ac97_clk
)) {
405 ret
= PTR_ERR(ac97_clk
);
410 ret
= clk_enable(ac97_clk
);
414 ret
= request_irq(IRQ_AC97
, pxa2xx_ac97_irq
, IRQF_DISABLED
, "AC97", NULL
);
421 GCR
|= GCR_ACLINK_OFF
;
427 clk_put(ac97conf_clk
);
433 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe
);
435 void pxa2xx_ac97_hw_remove(struct platform_device
*dev
)
437 GCR
|= GCR_ACLINK_OFF
;
438 free_irq(IRQ_AC97
, NULL
);
440 clk_put(ac97conf_clk
);
443 clk_disable(ac97_clk
);
447 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove
);
449 MODULE_AUTHOR("Nicolas Pitre");
450 MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
451 MODULE_LICENSE("GPL");