2 * TC Applied Technologies Digital Interface Communications Engine driver
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 * Licensed under the terms of the GNU General Public License, version 2.
10 MODULE_DESCRIPTION("DICE driver");
11 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
12 MODULE_LICENSE("GPL v2");
14 const unsigned int snd_dice_rates
[SND_DICE_RATES_COUNT
] = {
27 static unsigned int rate_to_index(unsigned int rate
)
31 for (i
= 0; i
< ARRAY_SIZE(snd_dice_rates
); ++i
)
32 if (snd_dice_rates
[i
] == rate
)
38 static unsigned int rate_index_to_mode(unsigned int rate_index
)
40 return ((int)rate_index
- 1) / 2;
43 static void dice_lock_changed(struct snd_dice
*dice
)
45 dice
->dev_lock_changed
= true;
46 wake_up(&dice
->hwdep_wait
);
49 static int dice_try_lock(struct snd_dice
*dice
)
53 spin_lock_irq(&dice
->lock
);
55 if (dice
->dev_lock_count
< 0) {
60 if (dice
->dev_lock_count
++ == 0)
61 dice_lock_changed(dice
);
65 spin_unlock_irq(&dice
->lock
);
70 static void dice_unlock(struct snd_dice
*dice
)
72 spin_lock_irq(&dice
->lock
);
74 if (WARN_ON(dice
->dev_lock_count
<= 0))
77 if (--dice
->dev_lock_count
== 0)
78 dice_lock_changed(dice
);
81 spin_unlock_irq(&dice
->lock
);
84 static int dice_rate_constraint(struct snd_pcm_hw_params
*params
,
85 struct snd_pcm_hw_rule
*rule
)
87 struct snd_dice
*dice
= rule
->private;
88 const struct snd_interval
*channels
=
89 hw_param_interval_c(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
90 struct snd_interval
*rate
=
91 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_RATE
);
92 struct snd_interval allowed_rates
= {
93 .min
= UINT_MAX
, .max
= 0, .integer
= 1
97 for (i
= 0; i
< ARRAY_SIZE(snd_dice_rates
); ++i
) {
98 mode
= rate_index_to_mode(i
);
99 if ((dice
->clock_caps
& (1 << i
)) &&
100 snd_interval_test(channels
, dice
->rx_channels
[mode
])) {
101 allowed_rates
.min
= min(allowed_rates
.min
,
103 allowed_rates
.max
= max(allowed_rates
.max
,
108 return snd_interval_refine(rate
, &allowed_rates
);
111 static int dice_channels_constraint(struct snd_pcm_hw_params
*params
,
112 struct snd_pcm_hw_rule
*rule
)
114 struct snd_dice
*dice
= rule
->private;
115 const struct snd_interval
*rate
=
116 hw_param_interval_c(params
, SNDRV_PCM_HW_PARAM_RATE
);
117 struct snd_interval
*channels
=
118 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
119 struct snd_interval allowed_channels
= {
120 .min
= UINT_MAX
, .max
= 0, .integer
= 1
122 unsigned int i
, mode
;
124 for (i
= 0; i
< ARRAY_SIZE(snd_dice_rates
); ++i
)
125 if ((dice
->clock_caps
& (1 << i
)) &&
126 snd_interval_test(rate
, snd_dice_rates
[i
])) {
127 mode
= rate_index_to_mode(i
);
128 allowed_channels
.min
= min(allowed_channels
.min
,
129 dice
->rx_channels
[mode
]);
130 allowed_channels
.max
= max(allowed_channels
.max
,
131 dice
->rx_channels
[mode
]);
134 return snd_interval_refine(channels
, &allowed_channels
);
137 static int dice_open(struct snd_pcm_substream
*substream
)
139 static const struct snd_pcm_hardware hardware
= {
140 .info
= SNDRV_PCM_INFO_MMAP
|
141 SNDRV_PCM_INFO_MMAP_VALID
|
142 SNDRV_PCM_INFO_BATCH
|
143 SNDRV_PCM_INFO_INTERLEAVED
|
144 SNDRV_PCM_INFO_BLOCK_TRANSFER
,
145 .formats
= AMDTP_OUT_PCM_FORMAT_BITS
,
146 .channels_min
= UINT_MAX
,
148 .buffer_bytes_max
= 16 * 1024 * 1024,
149 .period_bytes_min
= 1,
150 .period_bytes_max
= UINT_MAX
,
152 .periods_max
= UINT_MAX
,
154 struct snd_dice
*dice
= substream
->private_data
;
155 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
159 err
= dice_try_lock(dice
);
163 runtime
->hw
= hardware
;
165 for (i
= 0; i
< ARRAY_SIZE(snd_dice_rates
); ++i
)
166 if (dice
->clock_caps
& (1 << i
))
168 snd_pcm_rate_to_rate_bit(snd_dice_rates
[i
]);
169 snd_pcm_limit_hw_rates(runtime
);
171 for (i
= 0; i
< 3; ++i
)
172 if (dice
->rx_channels
[i
]) {
173 runtime
->hw
.channels_min
= min(runtime
->hw
.channels_min
,
174 dice
->rx_channels
[i
]);
175 runtime
->hw
.channels_max
= max(runtime
->hw
.channels_max
,
176 dice
->rx_channels
[i
]);
179 err
= snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
180 dice_rate_constraint
, dice
,
181 SNDRV_PCM_HW_PARAM_CHANNELS
, -1);
184 err
= snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
,
185 dice_channels_constraint
, dice
,
186 SNDRV_PCM_HW_PARAM_RATE
, -1);
190 err
= amdtp_stream_add_pcm_hw_constraints(&dice
->rx_stream
, runtime
);
202 static int dice_close(struct snd_pcm_substream
*substream
)
204 struct snd_dice
*dice
= substream
->private_data
;
211 static int dice_stream_start_packets(struct snd_dice
*dice
)
215 if (amdtp_stream_running(&dice
->rx_stream
))
218 err
= amdtp_stream_start(&dice
->rx_stream
, dice
->rx_resources
.channel
,
219 fw_parent_device(dice
->unit
)->max_speed
);
223 err
= snd_dice_transaction_set_enable(dice
);
225 amdtp_stream_stop(&dice
->rx_stream
);
232 static int dice_stream_start(struct snd_dice
*dice
)
237 if (!dice
->rx_resources
.allocated
) {
238 err
= fw_iso_resources_allocate(&dice
->rx_resources
,
239 amdtp_stream_get_max_payload(&dice
->rx_stream
),
240 fw_parent_device(dice
->unit
)->max_speed
);
244 channel
= cpu_to_be32(dice
->rx_resources
.channel
);
245 err
= snd_dice_transaction_write_tx(dice
, TX_ISOCHRONOUS
,
251 err
= dice_stream_start_packets(dice
);
258 channel
= cpu_to_be32((u32
)-1);
259 snd_dice_transaction_write_rx(dice
, RX_ISOCHRONOUS
, &channel
, 4);
261 fw_iso_resources_free(&dice
->rx_resources
);
266 static void dice_stream_stop_packets(struct snd_dice
*dice
)
268 if (amdtp_stream_running(&dice
->rx_stream
)) {
269 snd_dice_transaction_clear_enable(dice
);
270 amdtp_stream_stop(&dice
->rx_stream
);
274 static void dice_stream_stop(struct snd_dice
*dice
)
278 dice_stream_stop_packets(dice
);
280 if (!dice
->rx_resources
.allocated
)
283 channel
= cpu_to_be32((u32
)-1);
284 snd_dice_transaction_write_rx(dice
, RX_ISOCHRONOUS
, &channel
, 4);
286 fw_iso_resources_free(&dice
->rx_resources
);
289 static int dice_hw_params(struct snd_pcm_substream
*substream
,
290 struct snd_pcm_hw_params
*hw_params
)
292 struct snd_dice
*dice
= substream
->private_data
;
293 unsigned int rate_index
, mode
, rate
, channels
, i
;
296 mutex_lock(&dice
->mutex
);
297 dice_stream_stop(dice
);
298 mutex_unlock(&dice
->mutex
);
300 err
= snd_pcm_lib_alloc_vmalloc_buffer(substream
,
301 params_buffer_bytes(hw_params
));
305 rate
= params_rate(hw_params
);
306 err
= snd_dice_transaction_set_rate(dice
, rate
);
311 * At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in
312 * one data block of AMDTP packet. Thus sampling transfer frequency is
313 * a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are
314 * transferred on AMDTP packets at 96 kHz. Two successive samples of a
315 * channel are stored consecutively in the packet. This quirk is called
317 * For this quirk, blocking mode is required and PCM buffer size should
318 * be aligned to SYT_INTERVAL.
320 channels
= params_channels(hw_params
);
321 rate_index
= rate_to_index(rate
);
322 if (rate_index
> 4) {
323 if (channels
> AMDTP_MAX_CHANNELS_FOR_PCM
/ 2) {
330 dice
->rx_stream
.double_pcm_frames
= true;
332 dice
->rx_stream
.double_pcm_frames
= false;
335 mode
= rate_index_to_mode(rate_index
);
336 amdtp_stream_set_parameters(&dice
->rx_stream
, rate
, channels
,
337 dice
->rx_midi_ports
[mode
]);
338 if (rate_index
> 4) {
341 for (i
= 0; i
< channels
; i
++) {
342 dice
->rx_stream
.pcm_positions
[i
] = i
* 2;
343 dice
->rx_stream
.pcm_positions
[i
+ channels
] = i
* 2 + 1;
347 amdtp_stream_set_pcm_format(&dice
->rx_stream
,
348 params_format(hw_params
));
353 static int dice_hw_free(struct snd_pcm_substream
*substream
)
355 struct snd_dice
*dice
= substream
->private_data
;
357 mutex_lock(&dice
->mutex
);
358 dice_stream_stop(dice
);
359 mutex_unlock(&dice
->mutex
);
361 return snd_pcm_lib_free_vmalloc_buffer(substream
);
364 static int dice_prepare(struct snd_pcm_substream
*substream
)
366 struct snd_dice
*dice
= substream
->private_data
;
369 mutex_lock(&dice
->mutex
);
371 if (amdtp_streaming_error(&dice
->rx_stream
))
372 dice_stream_stop_packets(dice
);
374 err
= dice_stream_start(dice
);
376 mutex_unlock(&dice
->mutex
);
380 mutex_unlock(&dice
->mutex
);
382 amdtp_stream_pcm_prepare(&dice
->rx_stream
);
387 static int dice_trigger(struct snd_pcm_substream
*substream
, int cmd
)
389 struct snd_dice
*dice
= substream
->private_data
;
390 struct snd_pcm_substream
*pcm
;
393 case SNDRV_PCM_TRIGGER_START
:
396 case SNDRV_PCM_TRIGGER_STOP
:
402 amdtp_stream_pcm_trigger(&dice
->rx_stream
, pcm
);
407 static snd_pcm_uframes_t
dice_pointer(struct snd_pcm_substream
*substream
)
409 struct snd_dice
*dice
= substream
->private_data
;
411 return amdtp_stream_pcm_pointer(&dice
->rx_stream
);
414 static int dice_create_pcm(struct snd_dice
*dice
)
416 static struct snd_pcm_ops ops
= {
419 .ioctl
= snd_pcm_lib_ioctl
,
420 .hw_params
= dice_hw_params
,
421 .hw_free
= dice_hw_free
,
422 .prepare
= dice_prepare
,
423 .trigger
= dice_trigger
,
424 .pointer
= dice_pointer
,
425 .page
= snd_pcm_lib_get_vmalloc_page
,
426 .mmap
= snd_pcm_lib_mmap_vmalloc
,
431 err
= snd_pcm_new(dice
->card
, "DICE", 0, 1, 0, &pcm
);
434 pcm
->private_data
= dice
;
435 strcpy(pcm
->name
, dice
->card
->shortname
);
436 pcm
->streams
[SNDRV_PCM_STREAM_PLAYBACK
].substream
->ops
= &ops
;
441 static long dice_hwdep_read(struct snd_hwdep
*hwdep
, char __user
*buf
,
442 long count
, loff_t
*offset
)
444 struct snd_dice
*dice
= hwdep
->private_data
;
446 union snd_firewire_event event
;
448 spin_lock_irq(&dice
->lock
);
450 while (!dice
->dev_lock_changed
&& dice
->notification_bits
== 0) {
451 prepare_to_wait(&dice
->hwdep_wait
, &wait
, TASK_INTERRUPTIBLE
);
452 spin_unlock_irq(&dice
->lock
);
454 finish_wait(&dice
->hwdep_wait
, &wait
);
455 if (signal_pending(current
))
457 spin_lock_irq(&dice
->lock
);
460 memset(&event
, 0, sizeof(event
));
461 if (dice
->dev_lock_changed
) {
462 event
.lock_status
.type
= SNDRV_FIREWIRE_EVENT_LOCK_STATUS
;
463 event
.lock_status
.status
= dice
->dev_lock_count
> 0;
464 dice
->dev_lock_changed
= false;
466 count
= min_t(long, count
, sizeof(event
.lock_status
));
468 event
.dice_notification
.type
=
469 SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION
;
470 event
.dice_notification
.notification
= dice
->notification_bits
;
471 dice
->notification_bits
= 0;
473 count
= min_t(long, count
, sizeof(event
.dice_notification
));
476 spin_unlock_irq(&dice
->lock
);
478 if (copy_to_user(buf
, &event
, count
))
484 static unsigned int dice_hwdep_poll(struct snd_hwdep
*hwdep
, struct file
*file
,
487 struct snd_dice
*dice
= hwdep
->private_data
;
490 poll_wait(file
, &dice
->hwdep_wait
, wait
);
492 spin_lock_irq(&dice
->lock
);
493 if (dice
->dev_lock_changed
|| dice
->notification_bits
!= 0)
494 events
= POLLIN
| POLLRDNORM
;
497 spin_unlock_irq(&dice
->lock
);
502 static int dice_hwdep_get_info(struct snd_dice
*dice
, void __user
*arg
)
504 struct fw_device
*dev
= fw_parent_device(dice
->unit
);
505 struct snd_firewire_get_info info
;
507 memset(&info
, 0, sizeof(info
));
508 info
.type
= SNDRV_FIREWIRE_TYPE_DICE
;
509 info
.card
= dev
->card
->index
;
510 *(__be32
*)&info
.guid
[0] = cpu_to_be32(dev
->config_rom
[3]);
511 *(__be32
*)&info
.guid
[4] = cpu_to_be32(dev
->config_rom
[4]);
512 strlcpy(info
.device_name
, dev_name(&dev
->device
),
513 sizeof(info
.device_name
));
515 if (copy_to_user(arg
, &info
, sizeof(info
)))
521 static int dice_hwdep_lock(struct snd_dice
*dice
)
525 spin_lock_irq(&dice
->lock
);
527 if (dice
->dev_lock_count
== 0) {
528 dice
->dev_lock_count
= -1;
534 spin_unlock_irq(&dice
->lock
);
539 static int dice_hwdep_unlock(struct snd_dice
*dice
)
543 spin_lock_irq(&dice
->lock
);
545 if (dice
->dev_lock_count
== -1) {
546 dice
->dev_lock_count
= 0;
552 spin_unlock_irq(&dice
->lock
);
557 static int dice_hwdep_release(struct snd_hwdep
*hwdep
, struct file
*file
)
559 struct snd_dice
*dice
= hwdep
->private_data
;
561 spin_lock_irq(&dice
->lock
);
562 if (dice
->dev_lock_count
== -1)
563 dice
->dev_lock_count
= 0;
564 spin_unlock_irq(&dice
->lock
);
569 static int dice_hwdep_ioctl(struct snd_hwdep
*hwdep
, struct file
*file
,
570 unsigned int cmd
, unsigned long arg
)
572 struct snd_dice
*dice
= hwdep
->private_data
;
575 case SNDRV_FIREWIRE_IOCTL_GET_INFO
:
576 return dice_hwdep_get_info(dice
, (void __user
*)arg
);
577 case SNDRV_FIREWIRE_IOCTL_LOCK
:
578 return dice_hwdep_lock(dice
);
579 case SNDRV_FIREWIRE_IOCTL_UNLOCK
:
580 return dice_hwdep_unlock(dice
);
587 static int dice_hwdep_compat_ioctl(struct snd_hwdep
*hwdep
, struct file
*file
,
588 unsigned int cmd
, unsigned long arg
)
590 return dice_hwdep_ioctl(hwdep
, file
, cmd
,
591 (unsigned long)compat_ptr(arg
));
594 #define dice_hwdep_compat_ioctl NULL
597 static int dice_create_hwdep(struct snd_dice
*dice
)
599 static const struct snd_hwdep_ops ops
= {
600 .read
= dice_hwdep_read
,
601 .release
= dice_hwdep_release
,
602 .poll
= dice_hwdep_poll
,
603 .ioctl
= dice_hwdep_ioctl
,
604 .ioctl_compat
= dice_hwdep_compat_ioctl
,
606 struct snd_hwdep
*hwdep
;
609 err
= snd_hwdep_new(dice
->card
, "DICE", 0, &hwdep
);
612 strcpy(hwdep
->name
, "DICE");
613 hwdep
->iface
= SNDRV_HWDEP_IFACE_FW_DICE
;
615 hwdep
->private_data
= dice
;
616 hwdep
->exclusive
= true;
621 static int dice_proc_read_mem(struct snd_dice
*dice
, void *buffer
,
622 unsigned int offset_q
, unsigned int quadlets
)
627 err
= snd_fw_transaction(dice
->unit
, TCODE_READ_BLOCK_REQUEST
,
628 DICE_PRIVATE_SPACE
+ 4 * offset_q
,
629 buffer
, 4 * quadlets
, 0);
633 for (i
= 0; i
< quadlets
; ++i
)
634 be32_to_cpus(&((u32
*)buffer
)[i
]);
639 static const char *str_from_array(const char *const strs
[], unsigned int count
,
648 static void dice_proc_fixup_string(char *s
, unsigned int size
)
652 for (i
= 0; i
< size
; i
+= 4)
653 cpu_to_le32s((u32
*)(s
+ i
));
655 for (i
= 0; i
< size
- 2; ++i
) {
658 if (s
[i
] == '\\' && s
[i
+ 1] == '\\') {
666 static void dice_proc_read(struct snd_info_entry
*entry
,
667 struct snd_info_buffer
*buffer
)
669 static const char *const section_names
[5] = {
670 "global", "tx", "rx", "ext_sync", "unused2"
672 static const char *const clock_sources
[] = {
673 "aes1", "aes2", "aes3", "aes4", "aes", "adat", "tdif",
674 "wc", "arx1", "arx2", "arx3", "arx4", "internal"
676 static const char *const rates
[] = {
677 "32000", "44100", "48000", "88200", "96000", "176400", "192000",
678 "any low", "any mid", "any high", "none"
680 struct snd_dice
*dice
= entry
->private_data
;
681 u32 sections
[ARRAY_SIZE(section_names
) * 2];
688 u32 owner_hi
, owner_lo
;
690 char nick_name
[NICK_NAME_SIZE
];
698 char clock_source_names
[CLOCK_SOURCE_NAMES_SIZE
];
705 char names
[TX_NAMES_SIZE
];
714 char names
[RX_NAMES_SIZE
];
725 unsigned int quadlets
, stream
, i
;
727 if (dice_proc_read_mem(dice
, sections
, 0, ARRAY_SIZE(sections
)) < 0)
729 snd_iprintf(buffer
, "sections:\n");
730 for (i
= 0; i
< ARRAY_SIZE(section_names
); ++i
)
731 snd_iprintf(buffer
, " %s: offset %u, size %u\n",
733 sections
[i
* 2], sections
[i
* 2 + 1]);
735 quadlets
= min_t(u32
, sections
[1], sizeof(buf
.global
) / 4);
736 if (dice_proc_read_mem(dice
, &buf
.global
, sections
[0], quadlets
) < 0)
738 snd_iprintf(buffer
, "global:\n");
739 snd_iprintf(buffer
, " owner: %04x:%04x%08x\n",
740 buf
.global
.owner_hi
>> 16,
741 buf
.global
.owner_hi
& 0xffff, buf
.global
.owner_lo
);
742 snd_iprintf(buffer
, " notification: %08x\n", buf
.global
.notification
);
743 dice_proc_fixup_string(buf
.global
.nick_name
, NICK_NAME_SIZE
);
744 snd_iprintf(buffer
, " nick name: %s\n", buf
.global
.nick_name
);
745 snd_iprintf(buffer
, " clock select: %s %s\n",
746 str_from_array(clock_sources
, ARRAY_SIZE(clock_sources
),
747 buf
.global
.clock_select
& CLOCK_SOURCE_MASK
),
748 str_from_array(rates
, ARRAY_SIZE(rates
),
749 (buf
.global
.clock_select
& CLOCK_RATE_MASK
)
750 >> CLOCK_RATE_SHIFT
));
751 snd_iprintf(buffer
, " enable: %u\n", buf
.global
.enable
);
752 snd_iprintf(buffer
, " status: %slocked %s\n",
753 buf
.global
.status
& STATUS_SOURCE_LOCKED
? "" : "un",
754 str_from_array(rates
, ARRAY_SIZE(rates
),
756 STATUS_NOMINAL_RATE_MASK
)
757 >> CLOCK_RATE_SHIFT
));
758 snd_iprintf(buffer
, " ext status: %08x\n", buf
.global
.extended_status
);
759 snd_iprintf(buffer
, " sample rate: %u\n", buf
.global
.sample_rate
);
760 snd_iprintf(buffer
, " version: %u.%u.%u.%u\n",
761 (buf
.global
.version
>> 24) & 0xff,
762 (buf
.global
.version
>> 16) & 0xff,
763 (buf
.global
.version
>> 8) & 0xff,
764 (buf
.global
.version
>> 0) & 0xff);
765 if (quadlets
>= 90) {
766 snd_iprintf(buffer
, " clock caps:");
767 for (i
= 0; i
<= 6; ++i
)
768 if (buf
.global
.clock_caps
& (1 << i
))
769 snd_iprintf(buffer
, " %s", rates
[i
]);
770 for (i
= 0; i
<= 12; ++i
)
771 if (buf
.global
.clock_caps
& (1 << (16 + i
)))
772 snd_iprintf(buffer
, " %s", clock_sources
[i
]);
773 snd_iprintf(buffer
, "\n");
774 dice_proc_fixup_string(buf
.global
.clock_source_names
,
775 CLOCK_SOURCE_NAMES_SIZE
);
776 snd_iprintf(buffer
, " clock source names: %s\n",
777 buf
.global
.clock_source_names
);
780 if (dice_proc_read_mem(dice
, &tx_rx_header
, sections
[2], 2) < 0)
782 quadlets
= min_t(u32
, tx_rx_header
.size
, sizeof(buf
.tx
) / 4);
783 for (stream
= 0; stream
< tx_rx_header
.number
; ++stream
) {
784 if (dice_proc_read_mem(dice
, &buf
.tx
, sections
[2] + 2 +
785 stream
* tx_rx_header
.size
,
788 snd_iprintf(buffer
, "tx %u:\n", stream
);
789 snd_iprintf(buffer
, " iso channel: %d\n", (int)buf
.tx
.iso
);
790 snd_iprintf(buffer
, " audio channels: %u\n",
791 buf
.tx
.number_audio
);
792 snd_iprintf(buffer
, " midi ports: %u\n", buf
.tx
.number_midi
);
793 snd_iprintf(buffer
, " speed: S%u\n", 100u << buf
.tx
.speed
);
794 if (quadlets
>= 68) {
795 dice_proc_fixup_string(buf
.tx
.names
, TX_NAMES_SIZE
);
796 snd_iprintf(buffer
, " names: %s\n", buf
.tx
.names
);
798 if (quadlets
>= 70) {
799 snd_iprintf(buffer
, " ac3 caps: %08x\n",
801 snd_iprintf(buffer
, " ac3 enable: %08x\n",
806 if (dice_proc_read_mem(dice
, &tx_rx_header
, sections
[4], 2) < 0)
808 quadlets
= min_t(u32
, tx_rx_header
.size
, sizeof(buf
.rx
) / 4);
809 for (stream
= 0; stream
< tx_rx_header
.number
; ++stream
) {
810 if (dice_proc_read_mem(dice
, &buf
.rx
, sections
[4] + 2 +
811 stream
* tx_rx_header
.size
,
814 snd_iprintf(buffer
, "rx %u:\n", stream
);
815 snd_iprintf(buffer
, " iso channel: %d\n", (int)buf
.rx
.iso
);
816 snd_iprintf(buffer
, " sequence start: %u\n", buf
.rx
.seq_start
);
817 snd_iprintf(buffer
, " audio channels: %u\n",
818 buf
.rx
.number_audio
);
819 snd_iprintf(buffer
, " midi ports: %u\n", buf
.rx
.number_midi
);
820 if (quadlets
>= 68) {
821 dice_proc_fixup_string(buf
.rx
.names
, RX_NAMES_SIZE
);
822 snd_iprintf(buffer
, " names: %s\n", buf
.rx
.names
);
824 if (quadlets
>= 70) {
825 snd_iprintf(buffer
, " ac3 caps: %08x\n",
827 snd_iprintf(buffer
, " ac3 enable: %08x\n",
832 quadlets
= min_t(u32
, sections
[7], sizeof(buf
.ext_sync
) / 4);
834 if (dice_proc_read_mem(dice
, &buf
.ext_sync
,
837 snd_iprintf(buffer
, "ext status:\n");
838 snd_iprintf(buffer
, " clock source: %s\n",
839 str_from_array(clock_sources
,
840 ARRAY_SIZE(clock_sources
),
841 buf
.ext_sync
.clock_source
));
842 snd_iprintf(buffer
, " locked: %u\n", buf
.ext_sync
.locked
);
843 snd_iprintf(buffer
, " rate: %s\n",
844 str_from_array(rates
, ARRAY_SIZE(rates
),
846 snd_iprintf(buffer
, " adat user data: ");
847 if (buf
.ext_sync
.adat_user_data
& ADAT_USER_DATA_NO_DATA
)
848 snd_iprintf(buffer
, "-\n");
850 snd_iprintf(buffer
, "%x\n",
851 buf
.ext_sync
.adat_user_data
);
855 static void dice_create_proc(struct snd_dice
*dice
)
857 struct snd_info_entry
*entry
;
859 if (!snd_card_proc_new(dice
->card
, "dice", &entry
))
860 snd_info_set_text_ops(entry
, dice
, dice_proc_read
);
863 #define OUI_WEISS 0x001c6a
865 #define DICE_CATEGORY_ID 0x04
866 #define WEISS_CATEGORY_ID 0x00
868 static int dice_interface_check(struct fw_unit
*unit
)
870 static const int min_values
[10] = {
877 struct fw_device
*device
= fw_parent_device(unit
);
878 struct fw_csr_iterator it
;
879 int key
, val
, vendor
= -1, model
= -1, err
;
880 unsigned int category
, i
;
881 __be32
*pointers
, value
;
885 pointers
= kmalloc_array(ARRAY_SIZE(min_values
), sizeof(__be32
),
887 if (pointers
== NULL
)
891 * Check that GUID and unit directory are constructed according to DICE
892 * rules, i.e., that the specifier ID is the GUID's OUI, and that the
893 * GUID chip ID consists of the 8-bit category ID, the 10-bit product
894 * ID, and a 22-bit serial number.
896 fw_csr_iterator_init(&it
, unit
->directory
);
897 while (fw_csr_iterator_next(&it
, &key
, &val
)) {
899 case CSR_SPECIFIER_ID
:
907 if (vendor
== OUI_WEISS
)
908 category
= WEISS_CATEGORY_ID
;
910 category
= DICE_CATEGORY_ID
;
911 if (device
->config_rom
[3] != ((vendor
<< 8) | category
) ||
912 device
->config_rom
[4] >> 22 != model
) {
918 * Check that the sub address spaces exist and are located inside the
919 * private address space. The minimum values are chosen so that all
920 * minimally required registers are included.
922 err
= snd_fw_transaction(unit
, TCODE_READ_BLOCK_REQUEST
,
923 DICE_PRIVATE_SPACE
, pointers
,
924 sizeof(__be32
) * ARRAY_SIZE(min_values
), 0);
929 for (i
= 0; i
< ARRAY_SIZE(min_values
); ++i
) {
930 value
= be32_to_cpu(pointers
[i
]);
931 if (value
< min_values
[i
] || value
>= 0x40000) {
937 /* We support playback only. Let capture devices be handled by FFADO. */
938 err
= snd_fw_transaction(unit
, TCODE_READ_BLOCK_REQUEST
,
940 be32_to_cpu(pointers
[2]) * 4,
941 tx_data
, sizeof(tx_data
), 0);
942 if (err
< 0 || (tx_data
[0] && tx_data
[3])) {
948 * Check that the implemented DICE driver specification major version
951 err
= snd_fw_transaction(unit
, TCODE_READ_QUADLET_REQUEST
,
953 be32_to_cpu(pointers
[0]) * 4 + GLOBAL_VERSION
,
959 if ((version
& cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
960 dev_err(&unit
->device
,
961 "unknown DICE version: 0x%08x\n", be32_to_cpu(version
));
969 static int highest_supported_mode_rate(struct snd_dice
*dice
, unsigned int mode
)
973 for (i
= ARRAY_SIZE(snd_dice_rates
) - 1; i
>= 0; --i
)
974 if ((dice
->clock_caps
& (1 << i
)) &&
975 rate_index_to_mode(i
) == mode
)
981 static int dice_read_mode_params(struct snd_dice
*dice
, unsigned int mode
)
986 rate_index
= highest_supported_mode_rate(dice
, mode
);
987 if (rate_index
< 0) {
988 dice
->rx_channels
[mode
] = 0;
989 dice
->rx_midi_ports
[mode
] = 0;
993 err
= snd_dice_transaction_set_rate(dice
, snd_dice_rates
[rate_index
]);
997 err
= snd_dice_transaction_read_rx(dice
, RX_NUMBER_AUDIO
,
998 values
, sizeof(values
));
1002 dice
->rx_channels
[mode
] = be32_to_cpu(values
[0]);
1003 dice
->rx_midi_ports
[mode
] = be32_to_cpu(values
[1]);
1008 static int dice_read_params(struct snd_dice
*dice
)
1013 /* some very old firmwares don't tell about their clock support */
1014 if (dice
->clock_caps
> 0) {
1015 err
= snd_dice_transaction_read_global(dice
,
1016 GLOBAL_CLOCK_CAPABILITIES
,
1020 dice
->clock_caps
= be32_to_cpu(value
);
1022 /* this should be supported by any device */
1023 dice
->clock_caps
= CLOCK_CAP_RATE_44100
|
1024 CLOCK_CAP_RATE_48000
|
1025 CLOCK_CAP_SOURCE_ARX1
|
1026 CLOCK_CAP_SOURCE_INTERNAL
;
1029 for (mode
= 2; mode
>= 0; --mode
) {
1030 err
= dice_read_mode_params(dice
, mode
);
1038 static void dice_card_strings(struct snd_dice
*dice
)
1040 struct snd_card
*card
= dice
->card
;
1041 struct fw_device
*dev
= fw_parent_device(dice
->unit
);
1042 char vendor
[32], model
[32];
1046 strcpy(card
->driver
, "DICE");
1048 strcpy(card
->shortname
, "DICE");
1049 BUILD_BUG_ON(NICK_NAME_SIZE
< sizeof(card
->shortname
));
1050 err
= snd_dice_transaction_read_global(dice
, GLOBAL_NICK_NAME
,
1052 sizeof(card
->shortname
));
1054 /* DICE strings are returned in "always-wrong" endianness */
1055 BUILD_BUG_ON(sizeof(card
->shortname
) % 4 != 0);
1056 for (i
= 0; i
< sizeof(card
->shortname
); i
+= 4)
1057 swab32s((u32
*)&card
->shortname
[i
]);
1058 card
->shortname
[sizeof(card
->shortname
) - 1] = '\0';
1061 strcpy(vendor
, "?");
1062 fw_csr_string(dev
->config_rom
+ 5, CSR_VENDOR
, vendor
, sizeof(vendor
));
1064 fw_csr_string(dice
->unit
->directory
, CSR_MODEL
, model
, sizeof(model
));
1065 snprintf(card
->longname
, sizeof(card
->longname
),
1066 "%s %s (serial %u) at %s, S%d",
1067 vendor
, model
, dev
->config_rom
[4] & 0x3fffff,
1068 dev_name(&dice
->unit
->device
), 100 << dev
->max_speed
);
1070 strcpy(card
->mixername
, "DICE");
1073 static void dice_card_free(struct snd_card
*card
)
1075 struct snd_dice
*dice
= card
->private_data
;
1077 snd_dice_transaction_destroy(dice
);
1078 mutex_destroy(&dice
->mutex
);
1081 static int dice_probe(struct fw_unit
*unit
, const struct ieee1394_device_id
*id
)
1083 struct snd_card
*card
;
1084 struct snd_dice
*dice
;
1087 err
= dice_interface_check(unit
);
1091 err
= snd_card_new(&unit
->device
, -1, NULL
, THIS_MODULE
,
1092 sizeof(*dice
), &card
);
1096 dice
= card
->private_data
;
1099 card
->private_free
= dice_card_free
;
1101 spin_lock_init(&dice
->lock
);
1102 mutex_init(&dice
->mutex
);
1103 init_completion(&dice
->clock_accepted
);
1104 init_waitqueue_head(&dice
->hwdep_wait
);
1106 err
= snd_dice_transaction_init(dice
);
1110 err
= dice_read_params(dice
);
1114 dice_card_strings(dice
);
1116 err
= snd_dice_transaction_set_clock_source(dice
, CLOCK_SOURCE_ARX1
);
1120 err
= dice_create_pcm(dice
);
1124 err
= dice_create_hwdep(dice
);
1128 dice_create_proc(dice
);
1130 err
= fw_iso_resources_init(&dice
->rx_resources
, unit
);
1133 dice
->rx_resources
.channels_mask
= 0x00000000ffffffffuLL
;
1135 err
= amdtp_stream_init(&dice
->rx_stream
, unit
, AMDTP_OUT_STREAM
,
1138 fw_iso_resources_destroy(&dice
->rx_resources
);
1142 err
= snd_card_register(card
);
1144 amdtp_stream_destroy(&dice
->rx_stream
);
1145 fw_iso_resources_destroy(&dice
->rx_resources
);
1149 dev_set_drvdata(&unit
->device
, dice
);
1153 snd_card_free(card
);
1157 static void dice_remove(struct fw_unit
*unit
)
1159 struct snd_dice
*dice
= dev_get_drvdata(&unit
->device
);
1161 amdtp_stream_pcm_abort(&dice
->rx_stream
);
1163 snd_card_disconnect(dice
->card
);
1165 mutex_lock(&dice
->mutex
);
1167 dice_stream_stop(dice
);
1169 mutex_unlock(&dice
->mutex
);
1171 snd_card_free_when_closed(dice
->card
);
1174 static void dice_bus_reset(struct fw_unit
*unit
)
1176 struct snd_dice
*dice
= dev_get_drvdata(&unit
->device
);
1178 /* The handler address register becomes initialized. */
1179 snd_dice_transaction_reinit(dice
);
1182 * On a bus reset, the DICE firmware disables streaming and then goes
1183 * off contemplating its own navel for hundreds of milliseconds before
1184 * it can react to any of our attempts to reenable streaming. This
1185 * means that we lose synchronization anyway, so we force our streams
1186 * to stop so that the application can restart them in an orderly
1189 amdtp_stream_pcm_abort(&dice
->rx_stream
);
1191 mutex_lock(&dice
->mutex
);
1193 dice
->global_enabled
= false;
1195 dice_stream_stop_packets(dice
);
1196 fw_iso_resources_update(&dice
->rx_resources
);
1198 mutex_unlock(&dice
->mutex
);
1201 #define DICE_INTERFACE 0x000001
1203 static const struct ieee1394_device_id dice_id_table
[] = {
1205 .match_flags
= IEEE1394_MATCH_VERSION
,
1206 .version
= DICE_INTERFACE
,
1210 MODULE_DEVICE_TABLE(ieee1394
, dice_id_table
);
1212 static struct fw_driver dice_driver
= {
1214 .owner
= THIS_MODULE
,
1215 .name
= KBUILD_MODNAME
,
1216 .bus
= &fw_bus_type
,
1218 .probe
= dice_probe
,
1219 .update
= dice_bus_reset
,
1220 .remove
= dice_remove
,
1221 .id_table
= dice_id_table
,
1224 static int __init
alsa_dice_init(void)
1226 return driver_register(&dice_driver
.driver
);
1229 static void __exit
alsa_dice_exit(void)
1231 driver_unregister(&dice_driver
.driver
);
1234 module_init(alsa_dice_init
);
1235 module_exit(alsa_dice_exit
);