dd62316ea8b3d003a00c39dbaf51957efe228195
[deliverable/linux.git] / sound / firewire / dice / dice.c
1 /*
2 * TC Applied Technologies Digital Interface Communications Engine driver
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 * Licensed under the terms of the GNU General Public License, version 2.
6 */
7
8 #include "dice.h"
9
10 MODULE_DESCRIPTION("DICE driver");
11 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
12 MODULE_LICENSE("GPL v2");
13
14 const unsigned int snd_dice_rates[SND_DICE_RATES_COUNT] = {
15 /* mode 0 */
16 [0] = 32000,
17 [1] = 44100,
18 [2] = 48000,
19 /* mode 1 */
20 [3] = 88200,
21 [4] = 96000,
22 /* mode 2 */
23 [5] = 176400,
24 [6] = 192000,
25 };
26
27 static unsigned int rate_to_index(unsigned int rate)
28 {
29 unsigned int i;
30
31 for (i = 0; i < ARRAY_SIZE(snd_dice_rates); ++i)
32 if (snd_dice_rates[i] == rate)
33 return i;
34
35 return 0;
36 }
37
38 static unsigned int rate_index_to_mode(unsigned int rate_index)
39 {
40 return ((int)rate_index - 1) / 2;
41 }
42
43 static void dice_lock_changed(struct snd_dice *dice)
44 {
45 dice->dev_lock_changed = true;
46 wake_up(&dice->hwdep_wait);
47 }
48
49 static int dice_try_lock(struct snd_dice *dice)
50 {
51 int err;
52
53 spin_lock_irq(&dice->lock);
54
55 if (dice->dev_lock_count < 0) {
56 err = -EBUSY;
57 goto out;
58 }
59
60 if (dice->dev_lock_count++ == 0)
61 dice_lock_changed(dice);
62 err = 0;
63
64 out:
65 spin_unlock_irq(&dice->lock);
66
67 return err;
68 }
69
70 static void dice_unlock(struct snd_dice *dice)
71 {
72 spin_lock_irq(&dice->lock);
73
74 if (WARN_ON(dice->dev_lock_count <= 0))
75 goto out;
76
77 if (--dice->dev_lock_count == 0)
78 dice_lock_changed(dice);
79
80 out:
81 spin_unlock_irq(&dice->lock);
82 }
83
84 static int dice_rate_constraint(struct snd_pcm_hw_params *params,
85 struct snd_pcm_hw_rule *rule)
86 {
87 struct snd_dice *dice = rule->private;
88 const struct snd_interval *channels =
89 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_CHANNELS);
90 struct snd_interval *rate =
91 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
92 struct snd_interval allowed_rates = {
93 .min = UINT_MAX, .max = 0, .integer = 1
94 };
95 unsigned int i, mode;
96
97 for (i = 0; i < ARRAY_SIZE(snd_dice_rates); ++i) {
98 mode = rate_index_to_mode(i);
99 if ((dice->clock_caps & (1 << i)) &&
100 snd_interval_test(channels, dice->rx_channels[mode])) {
101 allowed_rates.min = min(allowed_rates.min,
102 snd_dice_rates[i]);
103 allowed_rates.max = max(allowed_rates.max,
104 snd_dice_rates[i]);
105 }
106 }
107
108 return snd_interval_refine(rate, &allowed_rates);
109 }
110
111 static int dice_channels_constraint(struct snd_pcm_hw_params *params,
112 struct snd_pcm_hw_rule *rule)
113 {
114 struct snd_dice *dice = rule->private;
115 const struct snd_interval *rate =
116 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE);
117 struct snd_interval *channels =
118 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
119 struct snd_interval allowed_channels = {
120 .min = UINT_MAX, .max = 0, .integer = 1
121 };
122 unsigned int i, mode;
123
124 for (i = 0; i < ARRAY_SIZE(snd_dice_rates); ++i)
125 if ((dice->clock_caps & (1 << i)) &&
126 snd_interval_test(rate, snd_dice_rates[i])) {
127 mode = rate_index_to_mode(i);
128 allowed_channels.min = min(allowed_channels.min,
129 dice->rx_channels[mode]);
130 allowed_channels.max = max(allowed_channels.max,
131 dice->rx_channels[mode]);
132 }
133
134 return snd_interval_refine(channels, &allowed_channels);
135 }
136
137 static int dice_open(struct snd_pcm_substream *substream)
138 {
139 static const struct snd_pcm_hardware hardware = {
140 .info = SNDRV_PCM_INFO_MMAP |
141 SNDRV_PCM_INFO_MMAP_VALID |
142 SNDRV_PCM_INFO_BATCH |
143 SNDRV_PCM_INFO_INTERLEAVED |
144 SNDRV_PCM_INFO_BLOCK_TRANSFER,
145 .formats = AMDTP_OUT_PCM_FORMAT_BITS,
146 .channels_min = UINT_MAX,
147 .channels_max = 0,
148 .buffer_bytes_max = 16 * 1024 * 1024,
149 .period_bytes_min = 1,
150 .period_bytes_max = UINT_MAX,
151 .periods_min = 1,
152 .periods_max = UINT_MAX,
153 };
154 struct snd_dice *dice = substream->private_data;
155 struct snd_pcm_runtime *runtime = substream->runtime;
156 unsigned int i;
157 int err;
158
159 err = dice_try_lock(dice);
160 if (err < 0)
161 goto error;
162
163 runtime->hw = hardware;
164
165 for (i = 0; i < ARRAY_SIZE(snd_dice_rates); ++i)
166 if (dice->clock_caps & (1 << i))
167 runtime->hw.rates |=
168 snd_pcm_rate_to_rate_bit(snd_dice_rates[i]);
169 snd_pcm_limit_hw_rates(runtime);
170
171 for (i = 0; i < 3; ++i)
172 if (dice->rx_channels[i]) {
173 runtime->hw.channels_min = min(runtime->hw.channels_min,
174 dice->rx_channels[i]);
175 runtime->hw.channels_max = max(runtime->hw.channels_max,
176 dice->rx_channels[i]);
177 }
178
179 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
180 dice_rate_constraint, dice,
181 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
182 if (err < 0)
183 goto err_lock;
184 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
185 dice_channels_constraint, dice,
186 SNDRV_PCM_HW_PARAM_RATE, -1);
187 if (err < 0)
188 goto err_lock;
189
190 err = amdtp_stream_add_pcm_hw_constraints(&dice->rx_stream, runtime);
191 if (err < 0)
192 goto err_lock;
193
194 return 0;
195
196 err_lock:
197 dice_unlock(dice);
198 error:
199 return err;
200 }
201
202 static int dice_close(struct snd_pcm_substream *substream)
203 {
204 struct snd_dice *dice = substream->private_data;
205
206 dice_unlock(dice);
207
208 return 0;
209 }
210
211 static int dice_stream_start_packets(struct snd_dice *dice)
212 {
213 int err;
214
215 if (amdtp_stream_running(&dice->rx_stream))
216 return 0;
217
218 err = amdtp_stream_start(&dice->rx_stream, dice->rx_resources.channel,
219 fw_parent_device(dice->unit)->max_speed);
220 if (err < 0)
221 return err;
222
223 err = snd_dice_transaction_set_enable(dice);
224 if (err < 0) {
225 amdtp_stream_stop(&dice->rx_stream);
226 return err;
227 }
228
229 return 0;
230 }
231
232 static int dice_stream_start(struct snd_dice *dice)
233 {
234 __be32 channel;
235 int err;
236
237 if (!dice->rx_resources.allocated) {
238 err = fw_iso_resources_allocate(&dice->rx_resources,
239 amdtp_stream_get_max_payload(&dice->rx_stream),
240 fw_parent_device(dice->unit)->max_speed);
241 if (err < 0)
242 goto error;
243
244 channel = cpu_to_be32(dice->rx_resources.channel);
245 err = snd_dice_transaction_write_tx(dice, TX_ISOCHRONOUS,
246 &channel, 4);
247 if (err < 0)
248 goto err_resources;
249 }
250
251 err = dice_stream_start_packets(dice);
252 if (err < 0)
253 goto err_rx_channel;
254
255 return 0;
256
257 err_rx_channel:
258 channel = cpu_to_be32((u32)-1);
259 snd_dice_transaction_write_rx(dice, RX_ISOCHRONOUS, &channel, 4);
260 err_resources:
261 fw_iso_resources_free(&dice->rx_resources);
262 error:
263 return err;
264 }
265
266 static void dice_stream_stop_packets(struct snd_dice *dice)
267 {
268 if (amdtp_stream_running(&dice->rx_stream)) {
269 snd_dice_transaction_clear_enable(dice);
270 amdtp_stream_stop(&dice->rx_stream);
271 }
272 }
273
274 static void dice_stream_stop(struct snd_dice *dice)
275 {
276 __be32 channel;
277
278 dice_stream_stop_packets(dice);
279
280 if (!dice->rx_resources.allocated)
281 return;
282
283 channel = cpu_to_be32((u32)-1);
284 snd_dice_transaction_write_rx(dice, RX_ISOCHRONOUS, &channel, 4);
285
286 fw_iso_resources_free(&dice->rx_resources);
287 }
288
289 static int dice_hw_params(struct snd_pcm_substream *substream,
290 struct snd_pcm_hw_params *hw_params)
291 {
292 struct snd_dice *dice = substream->private_data;
293 unsigned int rate_index, mode, rate, channels, i;
294 int err;
295
296 mutex_lock(&dice->mutex);
297 dice_stream_stop(dice);
298 mutex_unlock(&dice->mutex);
299
300 err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
301 params_buffer_bytes(hw_params));
302 if (err < 0)
303 return err;
304
305 rate = params_rate(hw_params);
306 err = snd_dice_transaction_set_rate(dice, rate);
307 if (err < 0)
308 return err;
309
310 /*
311 * At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in
312 * one data block of AMDTP packet. Thus sampling transfer frequency is
313 * a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are
314 * transferred on AMDTP packets at 96 kHz. Two successive samples of a
315 * channel are stored consecutively in the packet. This quirk is called
316 * as 'Dual Wire'.
317 * For this quirk, blocking mode is required and PCM buffer size should
318 * be aligned to SYT_INTERVAL.
319 */
320 channels = params_channels(hw_params);
321 rate_index = rate_to_index(rate);
322 if (rate_index > 4) {
323 if (channels > AMDTP_MAX_CHANNELS_FOR_PCM / 2) {
324 err = -ENOSYS;
325 return err;
326 }
327
328 rate /= 2;
329 channels *= 2;
330 dice->rx_stream.double_pcm_frames = true;
331 } else {
332 dice->rx_stream.double_pcm_frames = false;
333 }
334
335 mode = rate_index_to_mode(rate_index);
336 amdtp_stream_set_parameters(&dice->rx_stream, rate, channels,
337 dice->rx_midi_ports[mode]);
338 if (rate_index > 4) {
339 channels /= 2;
340
341 for (i = 0; i < channels; i++) {
342 dice->rx_stream.pcm_positions[i] = i * 2;
343 dice->rx_stream.pcm_positions[i + channels] = i * 2 + 1;
344 }
345 }
346
347 amdtp_stream_set_pcm_format(&dice->rx_stream,
348 params_format(hw_params));
349
350 return 0;
351 }
352
353 static int dice_hw_free(struct snd_pcm_substream *substream)
354 {
355 struct snd_dice *dice = substream->private_data;
356
357 mutex_lock(&dice->mutex);
358 dice_stream_stop(dice);
359 mutex_unlock(&dice->mutex);
360
361 return snd_pcm_lib_free_vmalloc_buffer(substream);
362 }
363
364 static int dice_prepare(struct snd_pcm_substream *substream)
365 {
366 struct snd_dice *dice = substream->private_data;
367 int err;
368
369 mutex_lock(&dice->mutex);
370
371 if (amdtp_streaming_error(&dice->rx_stream))
372 dice_stream_stop_packets(dice);
373
374 err = dice_stream_start(dice);
375 if (err < 0) {
376 mutex_unlock(&dice->mutex);
377 return err;
378 }
379
380 mutex_unlock(&dice->mutex);
381
382 amdtp_stream_pcm_prepare(&dice->rx_stream);
383
384 return 0;
385 }
386
387 static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
388 {
389 struct snd_dice *dice = substream->private_data;
390 struct snd_pcm_substream *pcm;
391
392 switch (cmd) {
393 case SNDRV_PCM_TRIGGER_START:
394 pcm = substream;
395 break;
396 case SNDRV_PCM_TRIGGER_STOP:
397 pcm = NULL;
398 break;
399 default:
400 return -EINVAL;
401 }
402 amdtp_stream_pcm_trigger(&dice->rx_stream, pcm);
403
404 return 0;
405 }
406
407 static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
408 {
409 struct snd_dice *dice = substream->private_data;
410
411 return amdtp_stream_pcm_pointer(&dice->rx_stream);
412 }
413
414 static int dice_create_pcm(struct snd_dice *dice)
415 {
416 static struct snd_pcm_ops ops = {
417 .open = dice_open,
418 .close = dice_close,
419 .ioctl = snd_pcm_lib_ioctl,
420 .hw_params = dice_hw_params,
421 .hw_free = dice_hw_free,
422 .prepare = dice_prepare,
423 .trigger = dice_trigger,
424 .pointer = dice_pointer,
425 .page = snd_pcm_lib_get_vmalloc_page,
426 .mmap = snd_pcm_lib_mmap_vmalloc,
427 };
428 struct snd_pcm *pcm;
429 int err;
430
431 err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
432 if (err < 0)
433 return err;
434 pcm->private_data = dice;
435 strcpy(pcm->name, dice->card->shortname);
436 pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->ops = &ops;
437
438 return 0;
439 }
440
441 static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
442 long count, loff_t *offset)
443 {
444 struct snd_dice *dice = hwdep->private_data;
445 DEFINE_WAIT(wait);
446 union snd_firewire_event event;
447
448 spin_lock_irq(&dice->lock);
449
450 while (!dice->dev_lock_changed && dice->notification_bits == 0) {
451 prepare_to_wait(&dice->hwdep_wait, &wait, TASK_INTERRUPTIBLE);
452 spin_unlock_irq(&dice->lock);
453 schedule();
454 finish_wait(&dice->hwdep_wait, &wait);
455 if (signal_pending(current))
456 return -ERESTARTSYS;
457 spin_lock_irq(&dice->lock);
458 }
459
460 memset(&event, 0, sizeof(event));
461 if (dice->dev_lock_changed) {
462 event.lock_status.type = SNDRV_FIREWIRE_EVENT_LOCK_STATUS;
463 event.lock_status.status = dice->dev_lock_count > 0;
464 dice->dev_lock_changed = false;
465
466 count = min_t(long, count, sizeof(event.lock_status));
467 } else {
468 event.dice_notification.type =
469 SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION;
470 event.dice_notification.notification = dice->notification_bits;
471 dice->notification_bits = 0;
472
473 count = min_t(long, count, sizeof(event.dice_notification));
474 }
475
476 spin_unlock_irq(&dice->lock);
477
478 if (copy_to_user(buf, &event, count))
479 return -EFAULT;
480
481 return count;
482 }
483
484 static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
485 poll_table *wait)
486 {
487 struct snd_dice *dice = hwdep->private_data;
488 unsigned int events;
489
490 poll_wait(file, &dice->hwdep_wait, wait);
491
492 spin_lock_irq(&dice->lock);
493 if (dice->dev_lock_changed || dice->notification_bits != 0)
494 events = POLLIN | POLLRDNORM;
495 else
496 events = 0;
497 spin_unlock_irq(&dice->lock);
498
499 return events;
500 }
501
502 static int dice_hwdep_get_info(struct snd_dice *dice, void __user *arg)
503 {
504 struct fw_device *dev = fw_parent_device(dice->unit);
505 struct snd_firewire_get_info info;
506
507 memset(&info, 0, sizeof(info));
508 info.type = SNDRV_FIREWIRE_TYPE_DICE;
509 info.card = dev->card->index;
510 *(__be32 *)&info.guid[0] = cpu_to_be32(dev->config_rom[3]);
511 *(__be32 *)&info.guid[4] = cpu_to_be32(dev->config_rom[4]);
512 strlcpy(info.device_name, dev_name(&dev->device),
513 sizeof(info.device_name));
514
515 if (copy_to_user(arg, &info, sizeof(info)))
516 return -EFAULT;
517
518 return 0;
519 }
520
521 static int dice_hwdep_lock(struct snd_dice *dice)
522 {
523 int err;
524
525 spin_lock_irq(&dice->lock);
526
527 if (dice->dev_lock_count == 0) {
528 dice->dev_lock_count = -1;
529 err = 0;
530 } else {
531 err = -EBUSY;
532 }
533
534 spin_unlock_irq(&dice->lock);
535
536 return err;
537 }
538
539 static int dice_hwdep_unlock(struct snd_dice *dice)
540 {
541 int err;
542
543 spin_lock_irq(&dice->lock);
544
545 if (dice->dev_lock_count == -1) {
546 dice->dev_lock_count = 0;
547 err = 0;
548 } else {
549 err = -EBADFD;
550 }
551
552 spin_unlock_irq(&dice->lock);
553
554 return err;
555 }
556
557 static int dice_hwdep_release(struct snd_hwdep *hwdep, struct file *file)
558 {
559 struct snd_dice *dice = hwdep->private_data;
560
561 spin_lock_irq(&dice->lock);
562 if (dice->dev_lock_count == -1)
563 dice->dev_lock_count = 0;
564 spin_unlock_irq(&dice->lock);
565
566 return 0;
567 }
568
569 static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
570 unsigned int cmd, unsigned long arg)
571 {
572 struct snd_dice *dice = hwdep->private_data;
573
574 switch (cmd) {
575 case SNDRV_FIREWIRE_IOCTL_GET_INFO:
576 return dice_hwdep_get_info(dice, (void __user *)arg);
577 case SNDRV_FIREWIRE_IOCTL_LOCK:
578 return dice_hwdep_lock(dice);
579 case SNDRV_FIREWIRE_IOCTL_UNLOCK:
580 return dice_hwdep_unlock(dice);
581 default:
582 return -ENOIOCTLCMD;
583 }
584 }
585
586 #ifdef CONFIG_COMPAT
587 static int dice_hwdep_compat_ioctl(struct snd_hwdep *hwdep, struct file *file,
588 unsigned int cmd, unsigned long arg)
589 {
590 return dice_hwdep_ioctl(hwdep, file, cmd,
591 (unsigned long)compat_ptr(arg));
592 }
593 #else
594 #define dice_hwdep_compat_ioctl NULL
595 #endif
596
597 static int dice_create_hwdep(struct snd_dice *dice)
598 {
599 static const struct snd_hwdep_ops ops = {
600 .read = dice_hwdep_read,
601 .release = dice_hwdep_release,
602 .poll = dice_hwdep_poll,
603 .ioctl = dice_hwdep_ioctl,
604 .ioctl_compat = dice_hwdep_compat_ioctl,
605 };
606 struct snd_hwdep *hwdep;
607 int err;
608
609 err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
610 if (err < 0)
611 return err;
612 strcpy(hwdep->name, "DICE");
613 hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
614 hwdep->ops = ops;
615 hwdep->private_data = dice;
616 hwdep->exclusive = true;
617
618 return 0;
619 }
620
621 static int dice_proc_read_mem(struct snd_dice *dice, void *buffer,
622 unsigned int offset_q, unsigned int quadlets)
623 {
624 unsigned int i;
625 int err;
626
627 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
628 DICE_PRIVATE_SPACE + 4 * offset_q,
629 buffer, 4 * quadlets, 0);
630 if (err < 0)
631 return err;
632
633 for (i = 0; i < quadlets; ++i)
634 be32_to_cpus(&((u32 *)buffer)[i]);
635
636 return 0;
637 }
638
639 static const char *str_from_array(const char *const strs[], unsigned int count,
640 unsigned int i)
641 {
642 if (i < count)
643 return strs[i];
644
645 return "(unknown)";
646 }
647
648 static void dice_proc_fixup_string(char *s, unsigned int size)
649 {
650 unsigned int i;
651
652 for (i = 0; i < size; i += 4)
653 cpu_to_le32s((u32 *)(s + i));
654
655 for (i = 0; i < size - 2; ++i) {
656 if (s[i] == '\0')
657 return;
658 if (s[i] == '\\' && s[i + 1] == '\\') {
659 s[i + 2] = '\0';
660 return;
661 }
662 }
663 s[size - 1] = '\0';
664 }
665
666 static void dice_proc_read(struct snd_info_entry *entry,
667 struct snd_info_buffer *buffer)
668 {
669 static const char *const section_names[5] = {
670 "global", "tx", "rx", "ext_sync", "unused2"
671 };
672 static const char *const clock_sources[] = {
673 "aes1", "aes2", "aes3", "aes4", "aes", "adat", "tdif",
674 "wc", "arx1", "arx2", "arx3", "arx4", "internal"
675 };
676 static const char *const rates[] = {
677 "32000", "44100", "48000", "88200", "96000", "176400", "192000",
678 "any low", "any mid", "any high", "none"
679 };
680 struct snd_dice *dice = entry->private_data;
681 u32 sections[ARRAY_SIZE(section_names) * 2];
682 struct {
683 u32 number;
684 u32 size;
685 } tx_rx_header;
686 union {
687 struct {
688 u32 owner_hi, owner_lo;
689 u32 notification;
690 char nick_name[NICK_NAME_SIZE];
691 u32 clock_select;
692 u32 enable;
693 u32 status;
694 u32 extended_status;
695 u32 sample_rate;
696 u32 version;
697 u32 clock_caps;
698 char clock_source_names[CLOCK_SOURCE_NAMES_SIZE];
699 } global;
700 struct {
701 u32 iso;
702 u32 number_audio;
703 u32 number_midi;
704 u32 speed;
705 char names[TX_NAMES_SIZE];
706 u32 ac3_caps;
707 u32 ac3_enable;
708 } tx;
709 struct {
710 u32 iso;
711 u32 seq_start;
712 u32 number_audio;
713 u32 number_midi;
714 char names[RX_NAMES_SIZE];
715 u32 ac3_caps;
716 u32 ac3_enable;
717 } rx;
718 struct {
719 u32 clock_source;
720 u32 locked;
721 u32 rate;
722 u32 adat_user_data;
723 } ext_sync;
724 } buf;
725 unsigned int quadlets, stream, i;
726
727 if (dice_proc_read_mem(dice, sections, 0, ARRAY_SIZE(sections)) < 0)
728 return;
729 snd_iprintf(buffer, "sections:\n");
730 for (i = 0; i < ARRAY_SIZE(section_names); ++i)
731 snd_iprintf(buffer, " %s: offset %u, size %u\n",
732 section_names[i],
733 sections[i * 2], sections[i * 2 + 1]);
734
735 quadlets = min_t(u32, sections[1], sizeof(buf.global) / 4);
736 if (dice_proc_read_mem(dice, &buf.global, sections[0], quadlets) < 0)
737 return;
738 snd_iprintf(buffer, "global:\n");
739 snd_iprintf(buffer, " owner: %04x:%04x%08x\n",
740 buf.global.owner_hi >> 16,
741 buf.global.owner_hi & 0xffff, buf.global.owner_lo);
742 snd_iprintf(buffer, " notification: %08x\n", buf.global.notification);
743 dice_proc_fixup_string(buf.global.nick_name, NICK_NAME_SIZE);
744 snd_iprintf(buffer, " nick name: %s\n", buf.global.nick_name);
745 snd_iprintf(buffer, " clock select: %s %s\n",
746 str_from_array(clock_sources, ARRAY_SIZE(clock_sources),
747 buf.global.clock_select & CLOCK_SOURCE_MASK),
748 str_from_array(rates, ARRAY_SIZE(rates),
749 (buf.global.clock_select & CLOCK_RATE_MASK)
750 >> CLOCK_RATE_SHIFT));
751 snd_iprintf(buffer, " enable: %u\n", buf.global.enable);
752 snd_iprintf(buffer, " status: %slocked %s\n",
753 buf.global.status & STATUS_SOURCE_LOCKED ? "" : "un",
754 str_from_array(rates, ARRAY_SIZE(rates),
755 (buf.global.status &
756 STATUS_NOMINAL_RATE_MASK)
757 >> CLOCK_RATE_SHIFT));
758 snd_iprintf(buffer, " ext status: %08x\n", buf.global.extended_status);
759 snd_iprintf(buffer, " sample rate: %u\n", buf.global.sample_rate);
760 snd_iprintf(buffer, " version: %u.%u.%u.%u\n",
761 (buf.global.version >> 24) & 0xff,
762 (buf.global.version >> 16) & 0xff,
763 (buf.global.version >> 8) & 0xff,
764 (buf.global.version >> 0) & 0xff);
765 if (quadlets >= 90) {
766 snd_iprintf(buffer, " clock caps:");
767 for (i = 0; i <= 6; ++i)
768 if (buf.global.clock_caps & (1 << i))
769 snd_iprintf(buffer, " %s", rates[i]);
770 for (i = 0; i <= 12; ++i)
771 if (buf.global.clock_caps & (1 << (16 + i)))
772 snd_iprintf(buffer, " %s", clock_sources[i]);
773 snd_iprintf(buffer, "\n");
774 dice_proc_fixup_string(buf.global.clock_source_names,
775 CLOCK_SOURCE_NAMES_SIZE);
776 snd_iprintf(buffer, " clock source names: %s\n",
777 buf.global.clock_source_names);
778 }
779
780 if (dice_proc_read_mem(dice, &tx_rx_header, sections[2], 2) < 0)
781 return;
782 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.tx) / 4);
783 for (stream = 0; stream < tx_rx_header.number; ++stream) {
784 if (dice_proc_read_mem(dice, &buf.tx, sections[2] + 2 +
785 stream * tx_rx_header.size,
786 quadlets) < 0)
787 break;
788 snd_iprintf(buffer, "tx %u:\n", stream);
789 snd_iprintf(buffer, " iso channel: %d\n", (int)buf.tx.iso);
790 snd_iprintf(buffer, " audio channels: %u\n",
791 buf.tx.number_audio);
792 snd_iprintf(buffer, " midi ports: %u\n", buf.tx.number_midi);
793 snd_iprintf(buffer, " speed: S%u\n", 100u << buf.tx.speed);
794 if (quadlets >= 68) {
795 dice_proc_fixup_string(buf.tx.names, TX_NAMES_SIZE);
796 snd_iprintf(buffer, " names: %s\n", buf.tx.names);
797 }
798 if (quadlets >= 70) {
799 snd_iprintf(buffer, " ac3 caps: %08x\n",
800 buf.tx.ac3_caps);
801 snd_iprintf(buffer, " ac3 enable: %08x\n",
802 buf.tx.ac3_enable);
803 }
804 }
805
806 if (dice_proc_read_mem(dice, &tx_rx_header, sections[4], 2) < 0)
807 return;
808 quadlets = min_t(u32, tx_rx_header.size, sizeof(buf.rx) / 4);
809 for (stream = 0; stream < tx_rx_header.number; ++stream) {
810 if (dice_proc_read_mem(dice, &buf.rx, sections[4] + 2 +
811 stream * tx_rx_header.size,
812 quadlets) < 0)
813 break;
814 snd_iprintf(buffer, "rx %u:\n", stream);
815 snd_iprintf(buffer, " iso channel: %d\n", (int)buf.rx.iso);
816 snd_iprintf(buffer, " sequence start: %u\n", buf.rx.seq_start);
817 snd_iprintf(buffer, " audio channels: %u\n",
818 buf.rx.number_audio);
819 snd_iprintf(buffer, " midi ports: %u\n", buf.rx.number_midi);
820 if (quadlets >= 68) {
821 dice_proc_fixup_string(buf.rx.names, RX_NAMES_SIZE);
822 snd_iprintf(buffer, " names: %s\n", buf.rx.names);
823 }
824 if (quadlets >= 70) {
825 snd_iprintf(buffer, " ac3 caps: %08x\n",
826 buf.rx.ac3_caps);
827 snd_iprintf(buffer, " ac3 enable: %08x\n",
828 buf.rx.ac3_enable);
829 }
830 }
831
832 quadlets = min_t(u32, sections[7], sizeof(buf.ext_sync) / 4);
833 if (quadlets >= 4) {
834 if (dice_proc_read_mem(dice, &buf.ext_sync,
835 sections[6], 4) < 0)
836 return;
837 snd_iprintf(buffer, "ext status:\n");
838 snd_iprintf(buffer, " clock source: %s\n",
839 str_from_array(clock_sources,
840 ARRAY_SIZE(clock_sources),
841 buf.ext_sync.clock_source));
842 snd_iprintf(buffer, " locked: %u\n", buf.ext_sync.locked);
843 snd_iprintf(buffer, " rate: %s\n",
844 str_from_array(rates, ARRAY_SIZE(rates),
845 buf.ext_sync.rate));
846 snd_iprintf(buffer, " adat user data: ");
847 if (buf.ext_sync.adat_user_data & ADAT_USER_DATA_NO_DATA)
848 snd_iprintf(buffer, "-\n");
849 else
850 snd_iprintf(buffer, "%x\n",
851 buf.ext_sync.adat_user_data);
852 }
853 }
854
855 static void dice_create_proc(struct snd_dice *dice)
856 {
857 struct snd_info_entry *entry;
858
859 if (!snd_card_proc_new(dice->card, "dice", &entry))
860 snd_info_set_text_ops(entry, dice, dice_proc_read);
861 }
862
863 #define OUI_WEISS 0x001c6a
864
865 #define DICE_CATEGORY_ID 0x04
866 #define WEISS_CATEGORY_ID 0x00
867
868 static int dice_interface_check(struct fw_unit *unit)
869 {
870 static const int min_values[10] = {
871 10, 0x64 / 4,
872 10, 0x18 / 4,
873 10, 0x18 / 4,
874 0, 0,
875 0, 0,
876 };
877 struct fw_device *device = fw_parent_device(unit);
878 struct fw_csr_iterator it;
879 int key, val, vendor = -1, model = -1, err;
880 unsigned int category, i;
881 __be32 *pointers, value;
882 __be32 tx_data[4];
883 __be32 version;
884
885 pointers = kmalloc_array(ARRAY_SIZE(min_values), sizeof(__be32),
886 GFP_KERNEL);
887 if (pointers == NULL)
888 return -ENOMEM;
889
890 /*
891 * Check that GUID and unit directory are constructed according to DICE
892 * rules, i.e., that the specifier ID is the GUID's OUI, and that the
893 * GUID chip ID consists of the 8-bit category ID, the 10-bit product
894 * ID, and a 22-bit serial number.
895 */
896 fw_csr_iterator_init(&it, unit->directory);
897 while (fw_csr_iterator_next(&it, &key, &val)) {
898 switch (key) {
899 case CSR_SPECIFIER_ID:
900 vendor = val;
901 break;
902 case CSR_MODEL:
903 model = val;
904 break;
905 }
906 }
907 if (vendor == OUI_WEISS)
908 category = WEISS_CATEGORY_ID;
909 else
910 category = DICE_CATEGORY_ID;
911 if (device->config_rom[3] != ((vendor << 8) | category) ||
912 device->config_rom[4] >> 22 != model) {
913 err = -ENODEV;
914 goto end;
915 }
916
917 /*
918 * Check that the sub address spaces exist and are located inside the
919 * private address space. The minimum values are chosen so that all
920 * minimally required registers are included.
921 */
922 err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
923 DICE_PRIVATE_SPACE, pointers,
924 sizeof(__be32) * ARRAY_SIZE(min_values), 0);
925 if (err < 0) {
926 err = -ENODEV;
927 goto end;
928 }
929 for (i = 0; i < ARRAY_SIZE(min_values); ++i) {
930 value = be32_to_cpu(pointers[i]);
931 if (value < min_values[i] || value >= 0x40000) {
932 err = -ENODEV;
933 goto end;
934 }
935 }
936
937 /* We support playback only. Let capture devices be handled by FFADO. */
938 err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
939 DICE_PRIVATE_SPACE +
940 be32_to_cpu(pointers[2]) * 4,
941 tx_data, sizeof(tx_data), 0);
942 if (err < 0 || (tx_data[0] && tx_data[3])) {
943 err = -ENODEV;
944 goto end;
945 }
946
947 /*
948 * Check that the implemented DICE driver specification major version
949 * number matches.
950 */
951 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
952 DICE_PRIVATE_SPACE +
953 be32_to_cpu(pointers[0]) * 4 + GLOBAL_VERSION,
954 &version, 4, 0);
955 if (err < 0) {
956 err = -ENODEV;
957 goto end;
958 }
959 if ((version & cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
960 dev_err(&unit->device,
961 "unknown DICE version: 0x%08x\n", be32_to_cpu(version));
962 err = -ENODEV;
963 goto end;
964 }
965 end:
966 return err;
967 }
968
969 static int highest_supported_mode_rate(struct snd_dice *dice, unsigned int mode)
970 {
971 int i;
972
973 for (i = ARRAY_SIZE(snd_dice_rates) - 1; i >= 0; --i)
974 if ((dice->clock_caps & (1 << i)) &&
975 rate_index_to_mode(i) == mode)
976 return i;
977
978 return -1;
979 }
980
981 static int dice_read_mode_params(struct snd_dice *dice, unsigned int mode)
982 {
983 __be32 values[2];
984 int rate_index, err;
985
986 rate_index = highest_supported_mode_rate(dice, mode);
987 if (rate_index < 0) {
988 dice->rx_channels[mode] = 0;
989 dice->rx_midi_ports[mode] = 0;
990 return 0;
991 }
992
993 err = snd_dice_transaction_set_rate(dice, snd_dice_rates[rate_index]);
994 if (err < 0)
995 return err;
996
997 err = snd_dice_transaction_read_rx(dice, RX_NUMBER_AUDIO,
998 values, sizeof(values));
999 if (err < 0)
1000 return err;
1001
1002 dice->rx_channels[mode] = be32_to_cpu(values[0]);
1003 dice->rx_midi_ports[mode] = be32_to_cpu(values[1]);
1004
1005 return 0;
1006 }
1007
1008 static int dice_read_params(struct snd_dice *dice)
1009 {
1010 __be32 value;
1011 int mode, err;
1012
1013 /* some very old firmwares don't tell about their clock support */
1014 if (dice->clock_caps > 0) {
1015 err = snd_dice_transaction_read_global(dice,
1016 GLOBAL_CLOCK_CAPABILITIES,
1017 &value, 4);
1018 if (err < 0)
1019 return err;
1020 dice->clock_caps = be32_to_cpu(value);
1021 } else {
1022 /* this should be supported by any device */
1023 dice->clock_caps = CLOCK_CAP_RATE_44100 |
1024 CLOCK_CAP_RATE_48000 |
1025 CLOCK_CAP_SOURCE_ARX1 |
1026 CLOCK_CAP_SOURCE_INTERNAL;
1027 }
1028
1029 for (mode = 2; mode >= 0; --mode) {
1030 err = dice_read_mode_params(dice, mode);
1031 if (err < 0)
1032 return err;
1033 }
1034
1035 return 0;
1036 }
1037
1038 static void dice_card_strings(struct snd_dice *dice)
1039 {
1040 struct snd_card *card = dice->card;
1041 struct fw_device *dev = fw_parent_device(dice->unit);
1042 char vendor[32], model[32];
1043 unsigned int i;
1044 int err;
1045
1046 strcpy(card->driver, "DICE");
1047
1048 strcpy(card->shortname, "DICE");
1049 BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
1050 err = snd_dice_transaction_read_global(dice, GLOBAL_NICK_NAME,
1051 card->shortname,
1052 sizeof(card->shortname));
1053 if (err >= 0) {
1054 /* DICE strings are returned in "always-wrong" endianness */
1055 BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
1056 for (i = 0; i < sizeof(card->shortname); i += 4)
1057 swab32s((u32 *)&card->shortname[i]);
1058 card->shortname[sizeof(card->shortname) - 1] = '\0';
1059 }
1060
1061 strcpy(vendor, "?");
1062 fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
1063 strcpy(model, "?");
1064 fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
1065 snprintf(card->longname, sizeof(card->longname),
1066 "%s %s (serial %u) at %s, S%d",
1067 vendor, model, dev->config_rom[4] & 0x3fffff,
1068 dev_name(&dice->unit->device), 100 << dev->max_speed);
1069
1070 strcpy(card->mixername, "DICE");
1071 }
1072
1073 static void dice_card_free(struct snd_card *card)
1074 {
1075 struct snd_dice *dice = card->private_data;
1076
1077 snd_dice_transaction_destroy(dice);
1078 mutex_destroy(&dice->mutex);
1079 }
1080
1081 static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
1082 {
1083 struct snd_card *card;
1084 struct snd_dice *dice;
1085 int err;
1086
1087 err = dice_interface_check(unit);
1088 if (err < 0)
1089 goto end;
1090
1091 err = snd_card_new(&unit->device, -1, NULL, THIS_MODULE,
1092 sizeof(*dice), &card);
1093 if (err < 0)
1094 goto end;
1095
1096 dice = card->private_data;
1097 dice->card = card;
1098 dice->unit = unit;
1099 card->private_free = dice_card_free;
1100
1101 spin_lock_init(&dice->lock);
1102 mutex_init(&dice->mutex);
1103 init_completion(&dice->clock_accepted);
1104 init_waitqueue_head(&dice->hwdep_wait);
1105
1106 err = snd_dice_transaction_init(dice);
1107 if (err < 0)
1108 goto error;
1109
1110 err = dice_read_params(dice);
1111 if (err < 0)
1112 goto error;
1113
1114 dice_card_strings(dice);
1115
1116 err = snd_dice_transaction_set_clock_source(dice, CLOCK_SOURCE_ARX1);
1117 if (err < 0)
1118 goto error;
1119
1120 err = dice_create_pcm(dice);
1121 if (err < 0)
1122 goto error;
1123
1124 err = dice_create_hwdep(dice);
1125 if (err < 0)
1126 goto error;
1127
1128 dice_create_proc(dice);
1129
1130 err = fw_iso_resources_init(&dice->rx_resources, unit);
1131 if (err < 0)
1132 goto error;
1133 dice->rx_resources.channels_mask = 0x00000000ffffffffuLL;
1134
1135 err = amdtp_stream_init(&dice->rx_stream, unit, AMDTP_OUT_STREAM,
1136 CIP_BLOCKING);
1137 if (err < 0) {
1138 fw_iso_resources_destroy(&dice->rx_resources);
1139 goto error;
1140 }
1141
1142 err = snd_card_register(card);
1143 if (err < 0) {
1144 amdtp_stream_destroy(&dice->rx_stream);
1145 fw_iso_resources_destroy(&dice->rx_resources);
1146 goto error;
1147 }
1148
1149 dev_set_drvdata(&unit->device, dice);
1150 end:
1151 return err;
1152 error:
1153 snd_card_free(card);
1154 return err;
1155 }
1156
1157 static void dice_remove(struct fw_unit *unit)
1158 {
1159 struct snd_dice *dice = dev_get_drvdata(&unit->device);
1160
1161 amdtp_stream_pcm_abort(&dice->rx_stream);
1162
1163 snd_card_disconnect(dice->card);
1164
1165 mutex_lock(&dice->mutex);
1166
1167 dice_stream_stop(dice);
1168
1169 mutex_unlock(&dice->mutex);
1170
1171 snd_card_free_when_closed(dice->card);
1172 }
1173
1174 static void dice_bus_reset(struct fw_unit *unit)
1175 {
1176 struct snd_dice *dice = dev_get_drvdata(&unit->device);
1177
1178 /* The handler address register becomes initialized. */
1179 snd_dice_transaction_reinit(dice);
1180
1181 /*
1182 * On a bus reset, the DICE firmware disables streaming and then goes
1183 * off contemplating its own navel for hundreds of milliseconds before
1184 * it can react to any of our attempts to reenable streaming. This
1185 * means that we lose synchronization anyway, so we force our streams
1186 * to stop so that the application can restart them in an orderly
1187 * manner.
1188 */
1189 amdtp_stream_pcm_abort(&dice->rx_stream);
1190
1191 mutex_lock(&dice->mutex);
1192
1193 dice->global_enabled = false;
1194
1195 dice_stream_stop_packets(dice);
1196 fw_iso_resources_update(&dice->rx_resources);
1197
1198 mutex_unlock(&dice->mutex);
1199 }
1200
1201 #define DICE_INTERFACE 0x000001
1202
1203 static const struct ieee1394_device_id dice_id_table[] = {
1204 {
1205 .match_flags = IEEE1394_MATCH_VERSION,
1206 .version = DICE_INTERFACE,
1207 },
1208 { }
1209 };
1210 MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
1211
1212 static struct fw_driver dice_driver = {
1213 .driver = {
1214 .owner = THIS_MODULE,
1215 .name = KBUILD_MODNAME,
1216 .bus = &fw_bus_type,
1217 },
1218 .probe = dice_probe,
1219 .update = dice_bus_reset,
1220 .remove = dice_remove,
1221 .id_table = dice_id_table,
1222 };
1223
1224 static int __init alsa_dice_init(void)
1225 {
1226 return driver_register(&dice_driver.driver);
1227 }
1228
1229 static void __exit alsa_dice_exit(void)
1230 {
1231 driver_unregister(&dice_driver.driver);
1232 }
1233
1234 module_init(alsa_dice_init);
1235 module_exit(alsa_dice_exit);
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