2 * TC Applied Technologies Digital Interface Communications Engine driver
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 * Licensed under the terms of the GNU General Public License, version 2.
10 MODULE_DESCRIPTION("DICE driver");
11 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
12 MODULE_LICENSE("GPL v2");
14 static int dice_rate_constraint(struct snd_pcm_hw_params
*params
,
15 struct snd_pcm_hw_rule
*rule
)
17 struct snd_dice
*dice
= rule
->private;
19 const struct snd_interval
*c
=
20 hw_param_interval_c(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
21 struct snd_interval
*r
=
22 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_RATE
);
23 struct snd_interval rates
= {
24 .min
= UINT_MAX
, .max
= 0, .integer
= 1
26 unsigned int i
, rate
, mode
, *pcm_channels
= dice
->rx_channels
;
28 for (i
= 0; i
< ARRAY_SIZE(snd_dice_rates
); ++i
) {
29 rate
= snd_dice_rates
[i
];
30 if (snd_dice_stream_get_rate_mode(dice
, rate
, &mode
) < 0)
33 if (!snd_interval_test(c
, pcm_channels
[mode
]))
36 rates
.min
= min(rates
.min
, rate
);
37 rates
.max
= max(rates
.max
, rate
);
40 return snd_interval_refine(r
, &rates
);
43 static int dice_channels_constraint(struct snd_pcm_hw_params
*params
,
44 struct snd_pcm_hw_rule
*rule
)
46 struct snd_dice
*dice
= rule
->private;
48 const struct snd_interval
*r
=
49 hw_param_interval_c(params
, SNDRV_PCM_HW_PARAM_RATE
);
50 struct snd_interval
*c
=
51 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
52 struct snd_interval channels
= {
53 .min
= UINT_MAX
, .max
= 0, .integer
= 1
55 unsigned int i
, rate
, mode
, *pcm_channels
= dice
->rx_channels
;
57 for (i
= 0; i
< ARRAY_SIZE(snd_dice_rates
); ++i
) {
58 rate
= snd_dice_rates
[i
];
59 if (snd_dice_stream_get_rate_mode(dice
, rate
, &mode
) < 0)
62 if (!snd_interval_test(r
, rate
))
65 channels
.min
= min(channels
.min
, pcm_channels
[mode
]);
66 channels
.max
= max(channels
.max
, pcm_channels
[mode
]);
69 return snd_interval_refine(c
, &channels
);
72 static int dice_open(struct snd_pcm_substream
*substream
)
74 static const struct snd_pcm_hardware hardware
= {
75 .info
= SNDRV_PCM_INFO_MMAP
|
76 SNDRV_PCM_INFO_MMAP_VALID
|
77 SNDRV_PCM_INFO_BATCH
|
78 SNDRV_PCM_INFO_INTERLEAVED
|
79 SNDRV_PCM_INFO_BLOCK_TRANSFER
,
80 .formats
= AMDTP_OUT_PCM_FORMAT_BITS
,
81 .channels_min
= UINT_MAX
,
83 .buffer_bytes_max
= 16 * 1024 * 1024,
84 .period_bytes_min
= 1,
85 .period_bytes_max
= UINT_MAX
,
87 .periods_max
= UINT_MAX
,
89 struct snd_dice
*dice
= substream
->private_data
;
90 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
94 err
= snd_dice_stream_lock_try(dice
);
98 runtime
->hw
= hardware
;
100 for (i
= 0; i
< ARRAY_SIZE(snd_dice_rates
); ++i
)
101 if (dice
->clock_caps
& (1 << i
))
103 snd_pcm_rate_to_rate_bit(snd_dice_rates
[i
]);
104 snd_pcm_limit_hw_rates(runtime
);
106 for (i
= 0; i
< 3; ++i
)
107 if (dice
->rx_channels
[i
]) {
108 runtime
->hw
.channels_min
= min(runtime
->hw
.channels_min
,
109 dice
->rx_channels
[i
]);
110 runtime
->hw
.channels_max
= max(runtime
->hw
.channels_max
,
111 dice
->rx_channels
[i
]);
114 err
= snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
115 dice_rate_constraint
, dice
,
116 SNDRV_PCM_HW_PARAM_CHANNELS
, -1);
119 err
= snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
,
120 dice_channels_constraint
, dice
,
121 SNDRV_PCM_HW_PARAM_RATE
, -1);
125 err
= amdtp_stream_add_pcm_hw_constraints(&dice
->rx_stream
, runtime
);
132 snd_dice_stream_lock_release(dice
);
137 static int dice_close(struct snd_pcm_substream
*substream
)
139 struct snd_dice
*dice
= substream
->private_data
;
141 snd_dice_stream_lock_release(dice
);
146 static int dice_hw_params(struct snd_pcm_substream
*substream
,
147 struct snd_pcm_hw_params
*hw_params
)
149 struct snd_dice
*dice
= substream
->private_data
;
150 unsigned int mode
, rate
, channels
, i
;
153 mutex_lock(&dice
->mutex
);
154 snd_dice_stream_stop(dice
);
155 mutex_unlock(&dice
->mutex
);
157 err
= snd_pcm_lib_alloc_vmalloc_buffer(substream
,
158 params_buffer_bytes(hw_params
));
162 rate
= params_rate(hw_params
);
163 err
= snd_dice_transaction_set_rate(dice
, rate
);
167 err
= snd_dice_stream_get_rate_mode(dice
, rate
, &mode
);
172 * At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in
173 * one data block of AMDTP packet. Thus sampling transfer frequency is
174 * a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are
175 * transferred on AMDTP packets at 96 kHz. Two successive samples of a
176 * channel are stored consecutively in the packet. This quirk is called
178 * For this quirk, blocking mode is required and PCM buffer size should
179 * be aligned to SYT_INTERVAL.
181 channels
= params_channels(hw_params
);
183 if (channels
> AMDTP_MAX_CHANNELS_FOR_PCM
/ 2) {
190 dice
->rx_stream
.double_pcm_frames
= true;
192 dice
->rx_stream
.double_pcm_frames
= false;
195 amdtp_stream_set_parameters(&dice
->rx_stream
, rate
, channels
,
196 dice
->rx_midi_ports
[mode
]);
200 for (i
= 0; i
< channels
; i
++) {
201 dice
->rx_stream
.pcm_positions
[i
] = i
* 2;
202 dice
->rx_stream
.pcm_positions
[i
+ channels
] = i
* 2 + 1;
206 amdtp_stream_set_pcm_format(&dice
->rx_stream
,
207 params_format(hw_params
));
212 static int dice_hw_free(struct snd_pcm_substream
*substream
)
214 struct snd_dice
*dice
= substream
->private_data
;
216 mutex_lock(&dice
->mutex
);
217 snd_dice_stream_stop(dice
);
218 mutex_unlock(&dice
->mutex
);
220 return snd_pcm_lib_free_vmalloc_buffer(substream
);
223 static int dice_prepare(struct snd_pcm_substream
*substream
)
225 struct snd_dice
*dice
= substream
->private_data
;
228 mutex_lock(&dice
->mutex
);
230 if (amdtp_streaming_error(&dice
->rx_stream
))
231 snd_dice_stream_stop_packets(dice
);
233 err
= snd_dice_stream_start(dice
);
235 mutex_unlock(&dice
->mutex
);
239 mutex_unlock(&dice
->mutex
);
241 amdtp_stream_pcm_prepare(&dice
->rx_stream
);
246 static int dice_trigger(struct snd_pcm_substream
*substream
, int cmd
)
248 struct snd_dice
*dice
= substream
->private_data
;
249 struct snd_pcm_substream
*pcm
;
252 case SNDRV_PCM_TRIGGER_START
:
255 case SNDRV_PCM_TRIGGER_STOP
:
261 amdtp_stream_pcm_trigger(&dice
->rx_stream
, pcm
);
266 static snd_pcm_uframes_t
dice_pointer(struct snd_pcm_substream
*substream
)
268 struct snd_dice
*dice
= substream
->private_data
;
270 return amdtp_stream_pcm_pointer(&dice
->rx_stream
);
273 static int dice_create_pcm(struct snd_dice
*dice
)
275 static struct snd_pcm_ops ops
= {
278 .ioctl
= snd_pcm_lib_ioctl
,
279 .hw_params
= dice_hw_params
,
280 .hw_free
= dice_hw_free
,
281 .prepare
= dice_prepare
,
282 .trigger
= dice_trigger
,
283 .pointer
= dice_pointer
,
284 .page
= snd_pcm_lib_get_vmalloc_page
,
285 .mmap
= snd_pcm_lib_mmap_vmalloc
,
290 err
= snd_pcm_new(dice
->card
, "DICE", 0, 1, 0, &pcm
);
293 pcm
->private_data
= dice
;
294 strcpy(pcm
->name
, dice
->card
->shortname
);
295 pcm
->streams
[SNDRV_PCM_STREAM_PLAYBACK
].substream
->ops
= &ops
;
300 static long dice_hwdep_read(struct snd_hwdep
*hwdep
, char __user
*buf
,
301 long count
, loff_t
*offset
)
303 struct snd_dice
*dice
= hwdep
->private_data
;
305 union snd_firewire_event event
;
307 spin_lock_irq(&dice
->lock
);
309 while (!dice
->dev_lock_changed
&& dice
->notification_bits
== 0) {
310 prepare_to_wait(&dice
->hwdep_wait
, &wait
, TASK_INTERRUPTIBLE
);
311 spin_unlock_irq(&dice
->lock
);
313 finish_wait(&dice
->hwdep_wait
, &wait
);
314 if (signal_pending(current
))
316 spin_lock_irq(&dice
->lock
);
319 memset(&event
, 0, sizeof(event
));
320 if (dice
->dev_lock_changed
) {
321 event
.lock_status
.type
= SNDRV_FIREWIRE_EVENT_LOCK_STATUS
;
322 event
.lock_status
.status
= dice
->dev_lock_count
> 0;
323 dice
->dev_lock_changed
= false;
325 count
= min_t(long, count
, sizeof(event
.lock_status
));
327 event
.dice_notification
.type
=
328 SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION
;
329 event
.dice_notification
.notification
= dice
->notification_bits
;
330 dice
->notification_bits
= 0;
332 count
= min_t(long, count
, sizeof(event
.dice_notification
));
335 spin_unlock_irq(&dice
->lock
);
337 if (copy_to_user(buf
, &event
, count
))
343 static unsigned int dice_hwdep_poll(struct snd_hwdep
*hwdep
, struct file
*file
,
346 struct snd_dice
*dice
= hwdep
->private_data
;
349 poll_wait(file
, &dice
->hwdep_wait
, wait
);
351 spin_lock_irq(&dice
->lock
);
352 if (dice
->dev_lock_changed
|| dice
->notification_bits
!= 0)
353 events
= POLLIN
| POLLRDNORM
;
356 spin_unlock_irq(&dice
->lock
);
361 static int dice_hwdep_get_info(struct snd_dice
*dice
, void __user
*arg
)
363 struct fw_device
*dev
= fw_parent_device(dice
->unit
);
364 struct snd_firewire_get_info info
;
366 memset(&info
, 0, sizeof(info
));
367 info
.type
= SNDRV_FIREWIRE_TYPE_DICE
;
368 info
.card
= dev
->card
->index
;
369 *(__be32
*)&info
.guid
[0] = cpu_to_be32(dev
->config_rom
[3]);
370 *(__be32
*)&info
.guid
[4] = cpu_to_be32(dev
->config_rom
[4]);
371 strlcpy(info
.device_name
, dev_name(&dev
->device
),
372 sizeof(info
.device_name
));
374 if (copy_to_user(arg
, &info
, sizeof(info
)))
380 static int dice_hwdep_lock(struct snd_dice
*dice
)
384 spin_lock_irq(&dice
->lock
);
386 if (dice
->dev_lock_count
== 0) {
387 dice
->dev_lock_count
= -1;
393 spin_unlock_irq(&dice
->lock
);
398 static int dice_hwdep_unlock(struct snd_dice
*dice
)
402 spin_lock_irq(&dice
->lock
);
404 if (dice
->dev_lock_count
== -1) {
405 dice
->dev_lock_count
= 0;
411 spin_unlock_irq(&dice
->lock
);
416 static int dice_hwdep_release(struct snd_hwdep
*hwdep
, struct file
*file
)
418 struct snd_dice
*dice
= hwdep
->private_data
;
420 spin_lock_irq(&dice
->lock
);
421 if (dice
->dev_lock_count
== -1)
422 dice
->dev_lock_count
= 0;
423 spin_unlock_irq(&dice
->lock
);
428 static int dice_hwdep_ioctl(struct snd_hwdep
*hwdep
, struct file
*file
,
429 unsigned int cmd
, unsigned long arg
)
431 struct snd_dice
*dice
= hwdep
->private_data
;
434 case SNDRV_FIREWIRE_IOCTL_GET_INFO
:
435 return dice_hwdep_get_info(dice
, (void __user
*)arg
);
436 case SNDRV_FIREWIRE_IOCTL_LOCK
:
437 return dice_hwdep_lock(dice
);
438 case SNDRV_FIREWIRE_IOCTL_UNLOCK
:
439 return dice_hwdep_unlock(dice
);
446 static int dice_hwdep_compat_ioctl(struct snd_hwdep
*hwdep
, struct file
*file
,
447 unsigned int cmd
, unsigned long arg
)
449 return dice_hwdep_ioctl(hwdep
, file
, cmd
,
450 (unsigned long)compat_ptr(arg
));
453 #define dice_hwdep_compat_ioctl NULL
456 static int dice_create_hwdep(struct snd_dice
*dice
)
458 static const struct snd_hwdep_ops ops
= {
459 .read
= dice_hwdep_read
,
460 .release
= dice_hwdep_release
,
461 .poll
= dice_hwdep_poll
,
462 .ioctl
= dice_hwdep_ioctl
,
463 .ioctl_compat
= dice_hwdep_compat_ioctl
,
465 struct snd_hwdep
*hwdep
;
468 err
= snd_hwdep_new(dice
->card
, "DICE", 0, &hwdep
);
471 strcpy(hwdep
->name
, "DICE");
472 hwdep
->iface
= SNDRV_HWDEP_IFACE_FW_DICE
;
474 hwdep
->private_data
= dice
;
475 hwdep
->exclusive
= true;
480 static int dice_proc_read_mem(struct snd_dice
*dice
, void *buffer
,
481 unsigned int offset_q
, unsigned int quadlets
)
486 err
= snd_fw_transaction(dice
->unit
, TCODE_READ_BLOCK_REQUEST
,
487 DICE_PRIVATE_SPACE
+ 4 * offset_q
,
488 buffer
, 4 * quadlets
, 0);
492 for (i
= 0; i
< quadlets
; ++i
)
493 be32_to_cpus(&((u32
*)buffer
)[i
]);
498 static const char *str_from_array(const char *const strs
[], unsigned int count
,
507 static void dice_proc_fixup_string(char *s
, unsigned int size
)
511 for (i
= 0; i
< size
; i
+= 4)
512 cpu_to_le32s((u32
*)(s
+ i
));
514 for (i
= 0; i
< size
- 2; ++i
) {
517 if (s
[i
] == '\\' && s
[i
+ 1] == '\\') {
525 static void dice_proc_read(struct snd_info_entry
*entry
,
526 struct snd_info_buffer
*buffer
)
528 static const char *const section_names
[5] = {
529 "global", "tx", "rx", "ext_sync", "unused2"
531 static const char *const clock_sources
[] = {
532 "aes1", "aes2", "aes3", "aes4", "aes", "adat", "tdif",
533 "wc", "arx1", "arx2", "arx3", "arx4", "internal"
535 static const char *const rates
[] = {
536 "32000", "44100", "48000", "88200", "96000", "176400", "192000",
537 "any low", "any mid", "any high", "none"
539 struct snd_dice
*dice
= entry
->private_data
;
540 u32 sections
[ARRAY_SIZE(section_names
) * 2];
547 u32 owner_hi
, owner_lo
;
549 char nick_name
[NICK_NAME_SIZE
];
557 char clock_source_names
[CLOCK_SOURCE_NAMES_SIZE
];
564 char names
[TX_NAMES_SIZE
];
573 char names
[RX_NAMES_SIZE
];
584 unsigned int quadlets
, stream
, i
;
586 if (dice_proc_read_mem(dice
, sections
, 0, ARRAY_SIZE(sections
)) < 0)
588 snd_iprintf(buffer
, "sections:\n");
589 for (i
= 0; i
< ARRAY_SIZE(section_names
); ++i
)
590 snd_iprintf(buffer
, " %s: offset %u, size %u\n",
592 sections
[i
* 2], sections
[i
* 2 + 1]);
594 quadlets
= min_t(u32
, sections
[1], sizeof(buf
.global
) / 4);
595 if (dice_proc_read_mem(dice
, &buf
.global
, sections
[0], quadlets
) < 0)
597 snd_iprintf(buffer
, "global:\n");
598 snd_iprintf(buffer
, " owner: %04x:%04x%08x\n",
599 buf
.global
.owner_hi
>> 16,
600 buf
.global
.owner_hi
& 0xffff, buf
.global
.owner_lo
);
601 snd_iprintf(buffer
, " notification: %08x\n", buf
.global
.notification
);
602 dice_proc_fixup_string(buf
.global
.nick_name
, NICK_NAME_SIZE
);
603 snd_iprintf(buffer
, " nick name: %s\n", buf
.global
.nick_name
);
604 snd_iprintf(buffer
, " clock select: %s %s\n",
605 str_from_array(clock_sources
, ARRAY_SIZE(clock_sources
),
606 buf
.global
.clock_select
& CLOCK_SOURCE_MASK
),
607 str_from_array(rates
, ARRAY_SIZE(rates
),
608 (buf
.global
.clock_select
& CLOCK_RATE_MASK
)
609 >> CLOCK_RATE_SHIFT
));
610 snd_iprintf(buffer
, " enable: %u\n", buf
.global
.enable
);
611 snd_iprintf(buffer
, " status: %slocked %s\n",
612 buf
.global
.status
& STATUS_SOURCE_LOCKED
? "" : "un",
613 str_from_array(rates
, ARRAY_SIZE(rates
),
615 STATUS_NOMINAL_RATE_MASK
)
616 >> CLOCK_RATE_SHIFT
));
617 snd_iprintf(buffer
, " ext status: %08x\n", buf
.global
.extended_status
);
618 snd_iprintf(buffer
, " sample rate: %u\n", buf
.global
.sample_rate
);
619 snd_iprintf(buffer
, " version: %u.%u.%u.%u\n",
620 (buf
.global
.version
>> 24) & 0xff,
621 (buf
.global
.version
>> 16) & 0xff,
622 (buf
.global
.version
>> 8) & 0xff,
623 (buf
.global
.version
>> 0) & 0xff);
624 if (quadlets
>= 90) {
625 snd_iprintf(buffer
, " clock caps:");
626 for (i
= 0; i
<= 6; ++i
)
627 if (buf
.global
.clock_caps
& (1 << i
))
628 snd_iprintf(buffer
, " %s", rates
[i
]);
629 for (i
= 0; i
<= 12; ++i
)
630 if (buf
.global
.clock_caps
& (1 << (16 + i
)))
631 snd_iprintf(buffer
, " %s", clock_sources
[i
]);
632 snd_iprintf(buffer
, "\n");
633 dice_proc_fixup_string(buf
.global
.clock_source_names
,
634 CLOCK_SOURCE_NAMES_SIZE
);
635 snd_iprintf(buffer
, " clock source names: %s\n",
636 buf
.global
.clock_source_names
);
639 if (dice_proc_read_mem(dice
, &tx_rx_header
, sections
[2], 2) < 0)
641 quadlets
= min_t(u32
, tx_rx_header
.size
, sizeof(buf
.tx
) / 4);
642 for (stream
= 0; stream
< tx_rx_header
.number
; ++stream
) {
643 if (dice_proc_read_mem(dice
, &buf
.tx
, sections
[2] + 2 +
644 stream
* tx_rx_header
.size
,
647 snd_iprintf(buffer
, "tx %u:\n", stream
);
648 snd_iprintf(buffer
, " iso channel: %d\n", (int)buf
.tx
.iso
);
649 snd_iprintf(buffer
, " audio channels: %u\n",
650 buf
.tx
.number_audio
);
651 snd_iprintf(buffer
, " midi ports: %u\n", buf
.tx
.number_midi
);
652 snd_iprintf(buffer
, " speed: S%u\n", 100u << buf
.tx
.speed
);
653 if (quadlets
>= 68) {
654 dice_proc_fixup_string(buf
.tx
.names
, TX_NAMES_SIZE
);
655 snd_iprintf(buffer
, " names: %s\n", buf
.tx
.names
);
657 if (quadlets
>= 70) {
658 snd_iprintf(buffer
, " ac3 caps: %08x\n",
660 snd_iprintf(buffer
, " ac3 enable: %08x\n",
665 if (dice_proc_read_mem(dice
, &tx_rx_header
, sections
[4], 2) < 0)
667 quadlets
= min_t(u32
, tx_rx_header
.size
, sizeof(buf
.rx
) / 4);
668 for (stream
= 0; stream
< tx_rx_header
.number
; ++stream
) {
669 if (dice_proc_read_mem(dice
, &buf
.rx
, sections
[4] + 2 +
670 stream
* tx_rx_header
.size
,
673 snd_iprintf(buffer
, "rx %u:\n", stream
);
674 snd_iprintf(buffer
, " iso channel: %d\n", (int)buf
.rx
.iso
);
675 snd_iprintf(buffer
, " sequence start: %u\n", buf
.rx
.seq_start
);
676 snd_iprintf(buffer
, " audio channels: %u\n",
677 buf
.rx
.number_audio
);
678 snd_iprintf(buffer
, " midi ports: %u\n", buf
.rx
.number_midi
);
679 if (quadlets
>= 68) {
680 dice_proc_fixup_string(buf
.rx
.names
, RX_NAMES_SIZE
);
681 snd_iprintf(buffer
, " names: %s\n", buf
.rx
.names
);
683 if (quadlets
>= 70) {
684 snd_iprintf(buffer
, " ac3 caps: %08x\n",
686 snd_iprintf(buffer
, " ac3 enable: %08x\n",
691 quadlets
= min_t(u32
, sections
[7], sizeof(buf
.ext_sync
) / 4);
693 if (dice_proc_read_mem(dice
, &buf
.ext_sync
,
696 snd_iprintf(buffer
, "ext status:\n");
697 snd_iprintf(buffer
, " clock source: %s\n",
698 str_from_array(clock_sources
,
699 ARRAY_SIZE(clock_sources
),
700 buf
.ext_sync
.clock_source
));
701 snd_iprintf(buffer
, " locked: %u\n", buf
.ext_sync
.locked
);
702 snd_iprintf(buffer
, " rate: %s\n",
703 str_from_array(rates
, ARRAY_SIZE(rates
),
705 snd_iprintf(buffer
, " adat user data: ");
706 if (buf
.ext_sync
.adat_user_data
& ADAT_USER_DATA_NO_DATA
)
707 snd_iprintf(buffer
, "-\n");
709 snd_iprintf(buffer
, "%x\n",
710 buf
.ext_sync
.adat_user_data
);
714 static void dice_create_proc(struct snd_dice
*dice
)
716 struct snd_info_entry
*entry
;
718 if (!snd_card_proc_new(dice
->card
, "dice", &entry
))
719 snd_info_set_text_ops(entry
, dice
, dice_proc_read
);
722 #define OUI_WEISS 0x001c6a
724 #define DICE_CATEGORY_ID 0x04
725 #define WEISS_CATEGORY_ID 0x00
727 static int dice_interface_check(struct fw_unit
*unit
)
729 static const int min_values
[10] = {
736 struct fw_device
*device
= fw_parent_device(unit
);
737 struct fw_csr_iterator it
;
738 int key
, val
, vendor
= -1, model
= -1, err
;
739 unsigned int category
, i
;
740 __be32
*pointers
, value
;
744 pointers
= kmalloc_array(ARRAY_SIZE(min_values
), sizeof(__be32
),
746 if (pointers
== NULL
)
750 * Check that GUID and unit directory are constructed according to DICE
751 * rules, i.e., that the specifier ID is the GUID's OUI, and that the
752 * GUID chip ID consists of the 8-bit category ID, the 10-bit product
753 * ID, and a 22-bit serial number.
755 fw_csr_iterator_init(&it
, unit
->directory
);
756 while (fw_csr_iterator_next(&it
, &key
, &val
)) {
758 case CSR_SPECIFIER_ID
:
766 if (vendor
== OUI_WEISS
)
767 category
= WEISS_CATEGORY_ID
;
769 category
= DICE_CATEGORY_ID
;
770 if (device
->config_rom
[3] != ((vendor
<< 8) | category
) ||
771 device
->config_rom
[4] >> 22 != model
) {
777 * Check that the sub address spaces exist and are located inside the
778 * private address space. The minimum values are chosen so that all
779 * minimally required registers are included.
781 err
= snd_fw_transaction(unit
, TCODE_READ_BLOCK_REQUEST
,
782 DICE_PRIVATE_SPACE
, pointers
,
783 sizeof(__be32
) * ARRAY_SIZE(min_values
), 0);
788 for (i
= 0; i
< ARRAY_SIZE(min_values
); ++i
) {
789 value
= be32_to_cpu(pointers
[i
]);
790 if (value
< min_values
[i
] || value
>= 0x40000) {
796 /* We support playback only. Let capture devices be handled by FFADO. */
797 err
= snd_fw_transaction(unit
, TCODE_READ_BLOCK_REQUEST
,
799 be32_to_cpu(pointers
[2]) * 4,
800 tx_data
, sizeof(tx_data
), 0);
801 if (err
< 0 || (tx_data
[0] && tx_data
[3])) {
807 * Check that the implemented DICE driver specification major version
810 err
= snd_fw_transaction(unit
, TCODE_READ_QUADLET_REQUEST
,
812 be32_to_cpu(pointers
[0]) * 4 + GLOBAL_VERSION
,
818 if ((version
& cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
819 dev_err(&unit
->device
,
820 "unknown DICE version: 0x%08x\n", be32_to_cpu(version
));
828 static int highest_supported_mode_rate(struct snd_dice
*dice
,
829 unsigned int mode
, unsigned int *rate
)
833 for (i
= ARRAY_SIZE(snd_dice_rates
); i
> 0; i
--) {
834 *rate
= snd_dice_rates
[i
- 1];
835 if (snd_dice_stream_get_rate_mode(dice
, *rate
, &m
) < 0)
846 static int dice_read_mode_params(struct snd_dice
*dice
, unsigned int mode
)
852 if (highest_supported_mode_rate(dice
, mode
, &rate
) < 0) {
853 dice
->rx_channels
[mode
] = 0;
854 dice
->rx_midi_ports
[mode
] = 0;
858 err
= snd_dice_transaction_set_rate(dice
, rate
);
862 err
= snd_dice_transaction_read_rx(dice
, RX_NUMBER_AUDIO
,
863 values
, sizeof(values
));
867 dice
->rx_channels
[mode
] = be32_to_cpu(values
[0]);
868 dice
->rx_midi_ports
[mode
] = be32_to_cpu(values
[1]);
873 static int dice_read_params(struct snd_dice
*dice
)
878 /* some very old firmwares don't tell about their clock support */
879 if (dice
->clock_caps
> 0) {
880 err
= snd_dice_transaction_read_global(dice
,
881 GLOBAL_CLOCK_CAPABILITIES
,
885 dice
->clock_caps
= be32_to_cpu(value
);
887 /* this should be supported by any device */
888 dice
->clock_caps
= CLOCK_CAP_RATE_44100
|
889 CLOCK_CAP_RATE_48000
|
890 CLOCK_CAP_SOURCE_ARX1
|
891 CLOCK_CAP_SOURCE_INTERNAL
;
894 for (mode
= 2; mode
>= 0; --mode
) {
895 err
= dice_read_mode_params(dice
, mode
);
903 static void dice_card_strings(struct snd_dice
*dice
)
905 struct snd_card
*card
= dice
->card
;
906 struct fw_device
*dev
= fw_parent_device(dice
->unit
);
907 char vendor
[32], model
[32];
911 strcpy(card
->driver
, "DICE");
913 strcpy(card
->shortname
, "DICE");
914 BUILD_BUG_ON(NICK_NAME_SIZE
< sizeof(card
->shortname
));
915 err
= snd_dice_transaction_read_global(dice
, GLOBAL_NICK_NAME
,
917 sizeof(card
->shortname
));
919 /* DICE strings are returned in "always-wrong" endianness */
920 BUILD_BUG_ON(sizeof(card
->shortname
) % 4 != 0);
921 for (i
= 0; i
< sizeof(card
->shortname
); i
+= 4)
922 swab32s((u32
*)&card
->shortname
[i
]);
923 card
->shortname
[sizeof(card
->shortname
) - 1] = '\0';
927 fw_csr_string(dev
->config_rom
+ 5, CSR_VENDOR
, vendor
, sizeof(vendor
));
929 fw_csr_string(dice
->unit
->directory
, CSR_MODEL
, model
, sizeof(model
));
930 snprintf(card
->longname
, sizeof(card
->longname
),
931 "%s %s (serial %u) at %s, S%d",
932 vendor
, model
, dev
->config_rom
[4] & 0x3fffff,
933 dev_name(&dice
->unit
->device
), 100 << dev
->max_speed
);
935 strcpy(card
->mixername
, "DICE");
938 static void dice_card_free(struct snd_card
*card
)
940 struct snd_dice
*dice
= card
->private_data
;
942 snd_dice_transaction_destroy(dice
);
943 mutex_destroy(&dice
->mutex
);
946 static int dice_probe(struct fw_unit
*unit
, const struct ieee1394_device_id
*id
)
948 struct snd_card
*card
;
949 struct snd_dice
*dice
;
952 err
= dice_interface_check(unit
);
956 err
= snd_card_new(&unit
->device
, -1, NULL
, THIS_MODULE
,
957 sizeof(*dice
), &card
);
961 dice
= card
->private_data
;
964 card
->private_free
= dice_card_free
;
966 spin_lock_init(&dice
->lock
);
967 mutex_init(&dice
->mutex
);
968 init_completion(&dice
->clock_accepted
);
969 init_waitqueue_head(&dice
->hwdep_wait
);
971 err
= snd_dice_transaction_init(dice
);
975 err
= dice_read_params(dice
);
979 dice_card_strings(dice
);
981 err
= dice_create_pcm(dice
);
985 err
= dice_create_hwdep(dice
);
989 dice_create_proc(dice
);
991 err
= snd_dice_stream_init(dice
);
995 err
= snd_card_register(card
);
997 snd_dice_stream_destroy(dice
);
1001 dev_set_drvdata(&unit
->device
, dice
);
1005 snd_card_free(card
);
1009 static void dice_remove(struct fw_unit
*unit
)
1011 struct snd_dice
*dice
= dev_get_drvdata(&unit
->device
);
1013 snd_card_disconnect(dice
->card
);
1015 mutex_lock(&dice
->mutex
);
1017 snd_dice_stream_destroy(dice
);
1019 mutex_unlock(&dice
->mutex
);
1021 snd_card_free_when_closed(dice
->card
);
1024 static void dice_bus_reset(struct fw_unit
*unit
)
1026 struct snd_dice
*dice
= dev_get_drvdata(&unit
->device
);
1028 /* The handler address register becomes initialized. */
1029 snd_dice_transaction_reinit(dice
);
1031 mutex_lock(&dice
->mutex
);
1032 snd_dice_stream_update(dice
);
1033 mutex_unlock(&dice
->mutex
);
1036 #define DICE_INTERFACE 0x000001
1038 static const struct ieee1394_device_id dice_id_table
[] = {
1040 .match_flags
= IEEE1394_MATCH_VERSION
,
1041 .version
= DICE_INTERFACE
,
1045 MODULE_DEVICE_TABLE(ieee1394
, dice_id_table
);
1047 static struct fw_driver dice_driver
= {
1049 .owner
= THIS_MODULE
,
1050 .name
= KBUILD_MODNAME
,
1051 .bus
= &fw_bus_type
,
1053 .probe
= dice_probe
,
1054 .update
= dice_bus_reset
,
1055 .remove
= dice_remove
,
1056 .id_table
= dice_id_table
,
1059 static int __init
alsa_dice_init(void)
1061 return driver_register(&dice_driver
.driver
);
1064 static void __exit
alsa_dice_exit(void)
1066 driver_unregister(&dice_driver
.driver
);
1069 module_init(alsa_dice_init
);
1070 module_exit(alsa_dice_exit
);