2 * HD-audio stream operations
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/export.h>
8 #include <linux/clocksource.h>
9 #include <sound/core.h>
10 #include <sound/pcm.h>
11 #include <sound/hdaudio.h>
12 #include <sound/hda_register.h>
16 * snd_hdac_stream_init - initialize each stream (aka device)
17 * @bus: HD-audio core bus
18 * @azx_dev: HD-audio core stream object to initialize
19 * @idx: stream index number
20 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
21 * @tag: the tag id to assign
23 * Assign the starting bdl address to each stream (device) and initialize.
25 void snd_hdac_stream_init(struct hdac_bus
*bus
, struct hdac_stream
*azx_dev
,
26 int idx
, int direction
, int tag
)
29 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
30 azx_dev
->sd_addr
= bus
->remap_addr
+ (0x20 * idx
+ 0x80);
31 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
32 azx_dev
->sd_int_sta_mask
= 1 << idx
;
34 azx_dev
->direction
= direction
;
35 azx_dev
->stream_tag
= tag
;
36 snd_hdac_dsp_lock_init(azx_dev
);
37 list_add_tail(&azx_dev
->list
, &bus
->stream_list
);
39 EXPORT_SYMBOL_GPL(snd_hdac_stream_init
);
42 * snd_hdac_stream_start - start a stream
43 * @azx_dev: HD-audio core stream to start
44 * @fresh_start: false = wallclock timestamp relative to period wallclock
46 * Start a stream, set start_wallclk and set the running flag.
48 void snd_hdac_stream_start(struct hdac_stream
*azx_dev
, bool fresh_start
)
50 struct hdac_bus
*bus
= azx_dev
->bus
;
52 trace_snd_hdac_stream_start(bus
, azx_dev
);
54 azx_dev
->start_wallclk
= snd_hdac_chip_readl(bus
, WALLCLK
);
56 azx_dev
->start_wallclk
-= azx_dev
->period_wallclk
;
59 snd_hdac_chip_updatel(bus
, INTCTL
, 0, 1 << azx_dev
->index
);
60 /* set DMA start and interrupt mask */
61 snd_hdac_stream_updateb(azx_dev
, SD_CTL
,
62 0, SD_CTL_DMA_START
| SD_INT_MASK
);
63 azx_dev
->running
= true;
65 EXPORT_SYMBOL_GPL(snd_hdac_stream_start
);
68 * snd_hdac_stream_clear - stop a stream DMA
69 * @azx_dev: HD-audio core stream to stop
71 void snd_hdac_stream_clear(struct hdac_stream
*azx_dev
)
73 snd_hdac_stream_updateb(azx_dev
, SD_CTL
,
74 SD_CTL_DMA_START
| SD_INT_MASK
, 0);
75 snd_hdac_stream_writeb(azx_dev
, SD_STS
, SD_INT_MASK
); /* to be sure */
76 azx_dev
->running
= false;
78 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear
);
81 * snd_hdac_stream_stop - stop a stream
82 * @azx_dev: HD-audio core stream to stop
84 * Stop a stream DMA and disable stream interrupt
86 void snd_hdac_stream_stop(struct hdac_stream
*azx_dev
)
88 trace_snd_hdac_stream_stop(azx_dev
->bus
, azx_dev
);
90 snd_hdac_stream_clear(azx_dev
);
92 snd_hdac_chip_updatel(azx_dev
->bus
, INTCTL
, 1 << azx_dev
->index
, 0);
94 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop
);
97 * snd_hdac_stream_reset - reset a stream
98 * @azx_dev: HD-audio core stream to reset
100 void snd_hdac_stream_reset(struct hdac_stream
*azx_dev
)
105 snd_hdac_stream_clear(azx_dev
);
107 snd_hdac_stream_updateb(azx_dev
, SD_CTL
, 0, SD_CTL_STREAM_RESET
);
111 val
= snd_hdac_stream_readb(azx_dev
, SD_CTL
) &
116 val
&= ~SD_CTL_STREAM_RESET
;
117 snd_hdac_stream_writeb(azx_dev
, SD_CTL
, val
);
121 /* waiting for hardware to report that the stream is out of reset */
123 val
= snd_hdac_stream_readb(azx_dev
, SD_CTL
) &
129 /* reset first position - may not be synced with hw at this time */
131 *azx_dev
->posbuf
= 0;
133 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset
);
136 * snd_hdac_stream_setup - set up the SD for streaming
137 * @azx_dev: HD-audio core stream to set up
139 int snd_hdac_stream_setup(struct hdac_stream
*azx_dev
)
141 struct hdac_bus
*bus
= azx_dev
->bus
;
142 struct snd_pcm_runtime
*runtime
;
145 if (azx_dev
->substream
)
146 runtime
= azx_dev
->substream
->runtime
;
149 /* make sure the run bit is zero for SD */
150 snd_hdac_stream_clear(azx_dev
);
151 /* program the stream_tag */
152 val
= snd_hdac_stream_readl(azx_dev
, SD_CTL
);
153 val
= (val
& ~SD_CTL_STREAM_TAG_MASK
) |
154 (azx_dev
->stream_tag
<< SD_CTL_STREAM_TAG_SHIFT
);
156 val
|= SD_CTL_TRAFFIC_PRIO
;
157 snd_hdac_stream_writel(azx_dev
, SD_CTL
, val
);
159 /* program the length of samples in cyclic buffer */
160 snd_hdac_stream_writel(azx_dev
, SD_CBL
, azx_dev
->bufsize
);
162 /* program the stream format */
163 /* this value needs to be the same as the one programmed */
164 snd_hdac_stream_writew(azx_dev
, SD_FORMAT
, azx_dev
->format_val
);
166 /* program the stream LVI (last valid index) of the BDL */
167 snd_hdac_stream_writew(azx_dev
, SD_LVI
, azx_dev
->frags
- 1);
169 /* program the BDL address */
170 /* lower BDL address */
171 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, (u32
)azx_dev
->bdl
.addr
);
172 /* upper BDL address */
173 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
,
174 upper_32_bits(azx_dev
->bdl
.addr
));
176 /* enable the position buffer */
177 if (bus
->use_posbuf
&& bus
->posbuf
.addr
) {
178 if (!(snd_hdac_chip_readl(bus
, DPLBASE
) & AZX_DPLBASE_ENABLE
))
179 snd_hdac_chip_writel(bus
, DPLBASE
,
180 (u32
)bus
->posbuf
.addr
| AZX_DPLBASE_ENABLE
);
183 /* set the interrupt enable bits in the descriptor control register */
184 snd_hdac_stream_updatel(azx_dev
, SD_CTL
, 0, SD_INT_MASK
);
186 if (azx_dev
->direction
== SNDRV_PCM_STREAM_PLAYBACK
)
188 snd_hdac_stream_readw(azx_dev
, SD_FIFOSIZE
) + 1;
190 azx_dev
->fifo_size
= 0;
192 /* when LPIB delay correction gives a small negative value,
193 * we ignore it; currently set the threshold statically to
196 if (runtime
&& runtime
->period_size
> 64)
197 azx_dev
->delay_negative_threshold
=
198 -frames_to_bytes(runtime
, 64);
200 azx_dev
->delay_negative_threshold
= 0;
202 /* wallclk has 24Mhz clock source */
204 azx_dev
->period_wallclk
= (((runtime
->period_size
* 24000) /
205 runtime
->rate
) * 1000);
209 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup
);
212 * snd_hdac_stream_cleanup - cleanup a stream
213 * @azx_dev: HD-audio core stream to clean up
215 void snd_hdac_stream_cleanup(struct hdac_stream
*azx_dev
)
217 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, 0);
218 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
, 0);
219 snd_hdac_stream_writel(azx_dev
, SD_CTL
, 0);
220 azx_dev
->bufsize
= 0;
221 azx_dev
->period_bytes
= 0;
222 azx_dev
->format_val
= 0;
224 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup
);
227 * snd_hdac_stream_assign - assign a stream for the PCM
228 * @bus: HD-audio core bus
229 * @substream: PCM substream to assign
231 * Look for an unused stream for the given PCM substream, assign it
232 * and return the stream object. If no stream is free, returns NULL.
233 * The function tries to keep using the same stream object when it's used
234 * beforehand. Also, when bus->reverse_assign flag is set, the last free
235 * or matching entry is returned. This is needed for some strange codecs.
237 struct hdac_stream
*snd_hdac_stream_assign(struct hdac_bus
*bus
,
238 struct snd_pcm_substream
*substream
)
240 struct hdac_stream
*azx_dev
;
241 struct hdac_stream
*res
= NULL
;
243 /* make a non-zero unique key for the substream */
244 int key
= (substream
->pcm
->device
<< 16) | (substream
->number
<< 2) |
245 (substream
->stream
+ 1);
247 list_for_each_entry(azx_dev
, &bus
->stream_list
, list
) {
248 if (azx_dev
->direction
!= substream
->stream
)
252 if (azx_dev
->assigned_key
== key
) {
256 if (!res
|| bus
->reverse_assign
)
260 spin_lock_irq(&bus
->reg_lock
);
263 res
->assigned_key
= key
;
264 res
->substream
= substream
;
265 spin_unlock_irq(&bus
->reg_lock
);
269 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign
);
272 * snd_hdac_stream_release - release the assigned stream
273 * @azx_dev: HD-audio core stream to release
275 * Release the stream that has been assigned by snd_hdac_stream_assign().
277 void snd_hdac_stream_release(struct hdac_stream
*azx_dev
)
279 struct hdac_bus
*bus
= azx_dev
->bus
;
281 spin_lock_irq(&bus
->reg_lock
);
283 azx_dev
->running
= 0;
284 azx_dev
->substream
= NULL
;
285 spin_unlock_irq(&bus
->reg_lock
);
287 EXPORT_SYMBOL_GPL(snd_hdac_stream_release
);
292 static int setup_bdle(struct hdac_bus
*bus
,
293 struct snd_dma_buffer
*dmab
,
294 struct hdac_stream
*azx_dev
, __le32
**bdlp
,
295 int ofs
, int size
, int with_ioc
)
303 if (azx_dev
->frags
>= AZX_MAX_BDL_ENTRIES
)
306 addr
= snd_sgbuf_get_addr(dmab
, ofs
);
307 /* program the address field of the BDL entry */
308 bdl
[0] = cpu_to_le32((u32
)addr
);
309 bdl
[1] = cpu_to_le32(upper_32_bits(addr
));
310 /* program the size field of the BDL entry */
311 chunk
= snd_sgbuf_get_chunk_size(dmab
, ofs
, size
);
312 /* one BDLE cannot cross 4K boundary on CTHDA chips */
313 if (bus
->align_bdle_4k
) {
314 u32 remain
= 0x1000 - (ofs
& 0xfff);
319 bdl
[2] = cpu_to_le32(chunk
);
320 /* program the IOC to enable interrupt
321 * only when the whole fragment is processed
324 bdl
[3] = (size
|| !with_ioc
) ? 0 : cpu_to_le32(0x01);
334 * snd_hdac_stream_setup_periods - set up BDL entries
335 * @azx_dev: HD-audio core stream to set up
337 * Set up the buffer descriptor table of the given stream based on the
338 * period and buffer sizes of the assigned PCM substream.
340 int snd_hdac_stream_setup_periods(struct hdac_stream
*azx_dev
)
342 struct hdac_bus
*bus
= azx_dev
->bus
;
343 struct snd_pcm_substream
*substream
= azx_dev
->substream
;
344 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
346 int i
, ofs
, periods
, period_bytes
;
347 int pos_adj
, pos_align
;
349 /* reset BDL address */
350 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, 0);
351 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
, 0);
353 period_bytes
= azx_dev
->period_bytes
;
354 periods
= azx_dev
->bufsize
/ period_bytes
;
356 /* program the initial BDL entries */
357 bdl
= (__le32
*)azx_dev
->bdl
.area
;
361 pos_adj
= bus
->bdl_pos_adj
;
362 if (!azx_dev
->no_period_wakeup
&& pos_adj
> 0) {
364 pos_adj
= (pos_adj
* runtime
->rate
+ 47999) / 48000;
368 pos_adj
= ((pos_adj
+ pos_align
- 1) / pos_align
) *
370 pos_adj
= frames_to_bytes(runtime
, pos_adj
);
371 if (pos_adj
>= period_bytes
) {
372 dev_warn(bus
->dev
, "Too big adjustment %d\n",
376 ofs
= setup_bdle(bus
, snd_pcm_get_dma_buf(substream
),
378 &bdl
, ofs
, pos_adj
, true);
385 for (i
= 0; i
< periods
; i
++) {
386 if (i
== periods
- 1 && pos_adj
)
387 ofs
= setup_bdle(bus
, snd_pcm_get_dma_buf(substream
),
389 period_bytes
- pos_adj
, 0);
391 ofs
= setup_bdle(bus
, snd_pcm_get_dma_buf(substream
),
394 !azx_dev
->no_period_wakeup
);
401 dev_err(bus
->dev
, "Too many BDL entries: buffer=%d, period=%d\n",
402 azx_dev
->bufsize
, period_bytes
);
405 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods
);
407 /* snd_hdac_stream_set_params - set stream parameters
408 * @azx_dev: HD-audio core stream for which parameters are to be set
409 * @format_val: format value parameter
411 * Setup the HD-audio core stream parameters from substream of the stream
412 * and passed format value
414 int snd_hdac_stream_set_params(struct hdac_stream
*azx_dev
,
415 unsigned int format_val
)
418 unsigned int bufsize
, period_bytes
;
419 struct snd_pcm_substream
*substream
= azx_dev
->substream
;
420 struct snd_pcm_runtime
*runtime
;
425 runtime
= substream
->runtime
;
426 bufsize
= snd_pcm_lib_buffer_bytes(substream
);
427 period_bytes
= snd_pcm_lib_period_bytes(substream
);
429 if (bufsize
!= azx_dev
->bufsize
||
430 period_bytes
!= azx_dev
->period_bytes
||
431 format_val
!= azx_dev
->format_val
||
432 runtime
->no_period_wakeup
!= azx_dev
->no_period_wakeup
) {
433 azx_dev
->bufsize
= bufsize
;
434 azx_dev
->period_bytes
= period_bytes
;
435 azx_dev
->format_val
= format_val
;
436 azx_dev
->no_period_wakeup
= runtime
->no_period_wakeup
;
437 err
= snd_hdac_stream_setup_periods(azx_dev
);
443 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params
);
445 static cycle_t
azx_cc_read(const struct cyclecounter
*cc
)
447 struct hdac_stream
*azx_dev
= container_of(cc
, struct hdac_stream
, cc
);
449 return snd_hdac_chip_readl(azx_dev
->bus
, WALLCLK
);
452 static void azx_timecounter_init(struct hdac_stream
*azx_dev
,
453 bool force
, cycle_t last
)
455 struct timecounter
*tc
= &azx_dev
->tc
;
456 struct cyclecounter
*cc
= &azx_dev
->cc
;
459 cc
->read
= azx_cc_read
;
460 cc
->mask
= CLOCKSOURCE_MASK(32);
463 * Converting from 24 MHz to ns means applying a 125/3 factor.
464 * To avoid any saturation issues in intermediate operations,
465 * the 125 factor is applied first. The division is applied
466 * last after reading the timecounter value.
467 * Applying the 1/3 factor as part of the multiplication
468 * requires at least 20 bits for a decent precision, however
469 * overflows occur after about 4 hours or less, not a option.
472 cc
->mult
= 125; /* saturation after 195 years */
475 nsec
= 0; /* audio time is elapsed time since trigger */
476 timecounter_init(tc
, cc
, nsec
);
479 * force timecounter to use predefined value,
480 * used for synchronized starts
482 tc
->cycle_last
= last
;
487 * snd_hdac_stream_timecounter_init - initialize time counter
488 * @azx_dev: HD-audio core stream (master stream)
489 * @streams: bit flags of streams to set up
491 * Initializes the time counter of streams marked by the bit flags (each
492 * bit corresponds to the stream index).
493 * The trigger timestamp of PCM substream assigned to the given stream is
494 * updated accordingly, too.
496 void snd_hdac_stream_timecounter_init(struct hdac_stream
*azx_dev
,
497 unsigned int streams
)
499 struct hdac_bus
*bus
= azx_dev
->bus
;
500 struct snd_pcm_runtime
*runtime
= azx_dev
->substream
->runtime
;
501 struct hdac_stream
*s
;
503 cycle_t cycle_last
= 0;
506 list_for_each_entry(s
, &bus
->stream_list
, list
) {
507 if (streams
& (1 << i
)) {
508 azx_timecounter_init(s
, inited
, cycle_last
);
511 cycle_last
= s
->tc
.cycle_last
;
517 snd_pcm_gettime(runtime
, &runtime
->trigger_tstamp
);
518 runtime
->trigger_tstamp_latched
= true;
520 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init
);
523 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
524 * @azx_dev: HD-audio core stream (master stream)
525 * @streams: bit flags of streams to sync
527 void snd_hdac_stream_sync_trigger(struct hdac_stream
*azx_dev
, bool set
,
528 unsigned int streams
, unsigned int reg
)
530 struct hdac_bus
*bus
= azx_dev
->bus
;
535 val
= _snd_hdac_chip_read(l
, bus
, reg
);
540 _snd_hdac_chip_write(l
, bus
, reg
, val
);
542 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger
);
545 * snd_hdac_stream_sync - sync with start/strop trigger operation
546 * @azx_dev: HD-audio core stream (master stream)
547 * @start: true = start, false = stop
548 * @streams: bit flags of streams to sync
550 * For @start = true, wait until all FIFOs get ready.
551 * For @start = false, wait until all RUN bits are cleared.
553 void snd_hdac_stream_sync(struct hdac_stream
*azx_dev
, bool start
,
554 unsigned int streams
)
556 struct hdac_bus
*bus
= azx_dev
->bus
;
557 int i
, nwait
, timeout
;
558 struct hdac_stream
*s
;
560 for (timeout
= 5000; timeout
; timeout
--) {
563 list_for_each_entry(s
, &bus
->stream_list
, list
) {
564 if (streams
& (1 << i
)) {
566 /* check FIFO gets ready */
567 if (!(snd_hdac_stream_readb(s
, SD_STS
) &
571 /* check RUN bit is cleared */
572 if (snd_hdac_stream_readb(s
, SD_CTL
) &
584 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync
);
586 #ifdef CONFIG_SND_HDA_DSP_LOADER
588 * snd_hdac_dsp_prepare - prepare for DSP loading
589 * @azx_dev: HD-audio core stream used for DSP loading
590 * @format: HD-audio stream format
591 * @byte_size: data chunk byte size
592 * @bufp: allocated buffer
594 * Allocate the buffer for the given size and set up the given stream for
595 * DSP loading. Returns the stream tag (>= 0), or a negative error code.
597 int snd_hdac_dsp_prepare(struct hdac_stream
*azx_dev
, unsigned int format
,
598 unsigned int byte_size
, struct snd_dma_buffer
*bufp
)
600 struct hdac_bus
*bus
= azx_dev
->bus
;
604 snd_hdac_dsp_lock(azx_dev
);
605 spin_lock_irq(&bus
->reg_lock
);
606 if (azx_dev
->running
|| azx_dev
->locked
) {
607 spin_unlock_irq(&bus
->reg_lock
);
611 azx_dev
->locked
= true;
612 spin_unlock_irq(&bus
->reg_lock
);
614 err
= bus
->io_ops
->dma_alloc_pages(bus
, SNDRV_DMA_TYPE_DEV_SG
,
619 azx_dev
->substream
= NULL
;
620 azx_dev
->bufsize
= byte_size
;
621 azx_dev
->period_bytes
= byte_size
;
622 azx_dev
->format_val
= format
;
624 snd_hdac_stream_reset(azx_dev
);
626 /* reset BDL address */
627 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, 0);
628 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
, 0);
631 bdl
= (u32
*)azx_dev
->bdl
.area
;
632 err
= setup_bdle(bus
, bufp
, azx_dev
, &bdl
, 0, byte_size
, 0);
636 snd_hdac_stream_setup(azx_dev
);
637 snd_hdac_dsp_unlock(azx_dev
);
638 return azx_dev
->stream_tag
;
641 bus
->io_ops
->dma_free_pages(bus
, bufp
);
643 spin_lock_irq(&bus
->reg_lock
);
644 azx_dev
->locked
= false;
645 spin_unlock_irq(&bus
->reg_lock
);
647 snd_hdac_dsp_unlock(azx_dev
);
650 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare
);
653 * snd_hdac_dsp_trigger - start / stop DSP loading
654 * @azx_dev: HD-audio core stream used for DSP loading
655 * @start: trigger start or stop
657 void snd_hdac_dsp_trigger(struct hdac_stream
*azx_dev
, bool start
)
660 snd_hdac_stream_start(azx_dev
, true);
662 snd_hdac_stream_stop(azx_dev
);
664 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger
);
667 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
668 * @azx_dev: HD-audio core stream used for DSP loading
669 * @dmab: buffer used by DSP loading
671 void snd_hdac_dsp_cleanup(struct hdac_stream
*azx_dev
,
672 struct snd_dma_buffer
*dmab
)
674 struct hdac_bus
*bus
= azx_dev
->bus
;
676 if (!dmab
->area
|| !azx_dev
->locked
)
679 snd_hdac_dsp_lock(azx_dev
);
680 /* reset BDL address */
681 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, 0);
682 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
, 0);
683 snd_hdac_stream_writel(azx_dev
, SD_CTL
, 0);
684 azx_dev
->bufsize
= 0;
685 azx_dev
->period_bytes
= 0;
686 azx_dev
->format_val
= 0;
688 bus
->io_ops
->dma_free_pages(bus
, dmab
);
691 spin_lock_irq(&bus
->reg_lock
);
692 azx_dev
->locked
= false;
693 spin_unlock_irq(&bus
->reg_lock
);
694 snd_hdac_dsp_unlock(azx_dev
);
696 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup
);
697 #endif /* CONFIG_SND_HDA_DSP_LOADER */