2 * HD-audio stream operations
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/export.h>
8 #include <sound/core.h>
10 #include <sound/hdaudio.h>
11 #include <sound/hda_register.h>
14 * snd_hdac_stream_init - initialize each stream (aka device)
15 * @bus: HD-audio core bus
16 * @azx_dev: HD-audio core stream object to initialize
17 * @idx: stream index number
18 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
19 * @tag: the tag id to assign
21 * Assign the starting bdl address to each stream (device) and initialize.
23 void snd_hdac_stream_init(struct hdac_bus
*bus
, struct hdac_stream
*azx_dev
,
24 int idx
, int direction
, int tag
)
27 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
28 azx_dev
->sd_addr
= bus
->remap_addr
+ (0x20 * idx
+ 0x80);
29 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
30 azx_dev
->sd_int_sta_mask
= 1 << idx
;
32 azx_dev
->direction
= direction
;
33 azx_dev
->stream_tag
= tag
;
34 snd_hdac_dsp_lock_init(azx_dev
);
35 list_add_tail(&azx_dev
->list
, &bus
->stream_list
);
37 EXPORT_SYMBOL_GPL(snd_hdac_stream_init
);
40 * snd_hdac_stream_start - start a stream
41 * @azx_dev: HD-audio core stream to start
42 * @fresh_start: false = wallclock timestamp relative to period wallclock
44 * Start a stream, set start_wallclk and set the running flag.
46 void snd_hdac_stream_start(struct hdac_stream
*azx_dev
, bool fresh_start
)
48 struct hdac_bus
*bus
= azx_dev
->bus
;
50 azx_dev
->start_wallclk
= snd_hdac_chip_readl(bus
, WALLCLK
);
52 azx_dev
->start_wallclk
-= azx_dev
->period_wallclk
;
55 snd_hdac_chip_updatel(bus
, INTCTL
, 0, 1 << azx_dev
->index
);
56 /* set DMA start and interrupt mask */
57 snd_hdac_stream_updateb(azx_dev
, SD_CTL
,
58 0, SD_CTL_DMA_START
| SD_INT_MASK
);
59 azx_dev
->running
= true;
61 EXPORT_SYMBOL_GPL(snd_hdac_stream_start
);
64 * snd_hdac_stream_clear - stop a stream DMA
65 * @azx_dev: HD-audio core stream to stop
67 void snd_hdac_stream_clear(struct hdac_stream
*azx_dev
)
69 snd_hdac_stream_updateb(azx_dev
, SD_CTL
,
70 SD_CTL_DMA_START
| SD_INT_MASK
, 0);
71 snd_hdac_stream_writeb(azx_dev
, SD_STS
, SD_INT_MASK
); /* to be sure */
72 azx_dev
->running
= false;
74 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear
);
77 * snd_hdac_stream_stop - stop a stream
78 * @azx_dev: HD-audio core stream to stop
80 * Stop a stream DMA and disable stream interrupt
82 void snd_hdac_stream_stop(struct hdac_stream
*azx_dev
)
84 snd_hdac_stream_clear(azx_dev
);
86 snd_hdac_chip_updatel(azx_dev
->bus
, INTCTL
, 1 << azx_dev
->index
, 0);
88 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop
);
91 * snd_hdac_stream_reset - reset a stream
92 * @azx_dev: HD-audio core stream to reset
94 void snd_hdac_stream_reset(struct hdac_stream
*azx_dev
)
99 snd_hdac_stream_clear(azx_dev
);
101 snd_hdac_stream_updateb(azx_dev
, SD_CTL
, 0, SD_CTL_STREAM_RESET
);
105 val
= snd_hdac_stream_readb(azx_dev
, SD_CTL
) &
110 val
&= ~SD_CTL_STREAM_RESET
;
111 snd_hdac_stream_writeb(azx_dev
, SD_CTL
, val
);
115 /* waiting for hardware to report that the stream is out of reset */
117 val
= snd_hdac_stream_readb(azx_dev
, SD_CTL
) &
123 /* reset first position - may not be synced with hw at this time */
125 *azx_dev
->posbuf
= 0;
127 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset
);
130 * snd_hdac_stream_setup - set up the SD for streaming
131 * @azx_dev: HD-audio core stream to set up
133 int snd_hdac_stream_setup(struct hdac_stream
*azx_dev
)
135 struct hdac_bus
*bus
= azx_dev
->bus
;
136 struct snd_pcm_runtime
*runtime
= azx_dev
->substream
->runtime
;
139 /* make sure the run bit is zero for SD */
140 snd_hdac_stream_clear(azx_dev
);
141 /* program the stream_tag */
142 val
= snd_hdac_stream_readl(azx_dev
, SD_CTL
);
143 val
= (val
& ~SD_CTL_STREAM_TAG_MASK
) |
144 (azx_dev
->stream_tag
<< SD_CTL_STREAM_TAG_SHIFT
);
146 val
|= SD_CTL_TRAFFIC_PRIO
;
147 snd_hdac_stream_writel(azx_dev
, SD_CTL
, val
);
149 /* program the length of samples in cyclic buffer */
150 snd_hdac_stream_writel(azx_dev
, SD_CBL
, azx_dev
->bufsize
);
152 /* program the stream format */
153 /* this value needs to be the same as the one programmed */
154 snd_hdac_stream_writew(azx_dev
, SD_FORMAT
, azx_dev
->format_val
);
156 /* program the stream LVI (last valid index) of the BDL */
157 snd_hdac_stream_writew(azx_dev
, SD_LVI
, azx_dev
->frags
- 1);
159 /* program the BDL address */
160 /* lower BDL address */
161 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, (u32
)azx_dev
->bdl
.addr
);
162 /* upper BDL address */
163 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
,
164 upper_32_bits(azx_dev
->bdl
.addr
));
166 /* enable the position buffer */
167 if (bus
->use_posbuf
&& bus
->posbuf
.addr
) {
168 if (!(snd_hdac_chip_readl(bus
, DPLBASE
) & AZX_DPLBASE_ENABLE
))
169 snd_hdac_chip_writel(bus
, DPLBASE
,
170 (u32
)bus
->posbuf
.addr
| AZX_DPLBASE_ENABLE
);
173 /* set the interrupt enable bits in the descriptor control register */
174 snd_hdac_stream_updatel(azx_dev
, SD_CTL
, 0, SD_INT_MASK
);
176 if (azx_dev
->direction
== SNDRV_PCM_STREAM_PLAYBACK
)
178 snd_hdac_stream_readw(azx_dev
, SD_FIFOSIZE
) + 1;
180 azx_dev
->fifo_size
= 0;
182 /* when LPIB delay correction gives a small negative value,
183 * we ignore it; currently set the threshold statically to
186 if (runtime
->period_size
> 64)
187 azx_dev
->delay_negative_threshold
=
188 -frames_to_bytes(runtime
, 64);
190 azx_dev
->delay_negative_threshold
= 0;
192 /* wallclk has 24Mhz clock source */
193 azx_dev
->period_wallclk
= (((runtime
->period_size
* 24000) /
194 runtime
->rate
) * 1000);
198 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup
);
201 * snd_hdac_stream_cleanup - cleanup a stream
202 * @azx_dev: HD-audio core stream to clean up
204 void snd_hdac_stream_cleanup(struct hdac_stream
*azx_dev
)
206 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, 0);
207 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
, 0);
208 snd_hdac_stream_writel(azx_dev
, SD_CTL
, 0);
209 azx_dev
->bufsize
= 0;
210 azx_dev
->period_bytes
= 0;
211 azx_dev
->format_val
= 0;
213 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup
);
216 * snd_hdac_stream_assign - assign a stream for the PCM
217 * @bus: HD-audio core bus
218 * @substream: PCM substream to assign
220 * Look for an unused stream for the given PCM substream, assign it
221 * and return the stream object. If no stream is free, returns NULL.
222 * The function tries to keep using the same stream object when it's used
223 * beforehand. Also, when bus->reverse_assign flag is set, the last free
224 * or matching entry is returned. This is needed for some strange codecs.
226 struct hdac_stream
*snd_hdac_stream_assign(struct hdac_bus
*bus
,
227 struct snd_pcm_substream
*substream
)
229 struct hdac_stream
*azx_dev
;
230 struct hdac_stream
*res
= NULL
;
232 /* make a non-zero unique key for the substream */
233 int key
= (substream
->pcm
->device
<< 16) | (substream
->number
<< 2) |
234 (substream
->stream
+ 1);
236 list_for_each_entry(azx_dev
, &bus
->stream_list
, list
) {
237 if (azx_dev
->direction
!= substream
->stream
)
241 if (azx_dev
->assigned_key
== key
) {
245 if (!res
|| bus
->reverse_assign
)
249 spin_lock_irq(&bus
->reg_lock
);
252 res
->assigned_key
= key
;
253 res
->substream
= substream
;
254 spin_unlock_irq(&bus
->reg_lock
);
258 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign
);
261 * snd_hdac_stream_release - release the assigned stream
262 * @azx_dev: HD-audio core stream to release
264 * Release the stream that has been assigned by snd_hdac_stream_assign().
266 void snd_hdac_stream_release(struct hdac_stream
*azx_dev
)
268 struct hdac_bus
*bus
= azx_dev
->bus
;
270 spin_lock_irq(&bus
->reg_lock
);
272 azx_dev
->running
= 0;
273 azx_dev
->substream
= NULL
;
274 spin_unlock_irq(&bus
->reg_lock
);
276 EXPORT_SYMBOL_GPL(snd_hdac_stream_release
);
281 static int setup_bdle(struct hdac_bus
*bus
,
282 struct snd_dma_buffer
*dmab
,
283 struct hdac_stream
*azx_dev
, __le32
**bdlp
,
284 int ofs
, int size
, int with_ioc
)
292 if (azx_dev
->frags
>= AZX_MAX_BDL_ENTRIES
)
295 addr
= snd_sgbuf_get_addr(dmab
, ofs
);
296 /* program the address field of the BDL entry */
297 bdl
[0] = cpu_to_le32((u32
)addr
);
298 bdl
[1] = cpu_to_le32(upper_32_bits(addr
));
299 /* program the size field of the BDL entry */
300 chunk
= snd_sgbuf_get_chunk_size(dmab
, ofs
, size
);
301 /* one BDLE cannot cross 4K boundary on CTHDA chips */
302 if (bus
->align_bdle_4k
) {
303 u32 remain
= 0x1000 - (ofs
& 0xfff);
308 bdl
[2] = cpu_to_le32(chunk
);
309 /* program the IOC to enable interrupt
310 * only when the whole fragment is processed
313 bdl
[3] = (size
|| !with_ioc
) ? 0 : cpu_to_le32(0x01);
323 * snd_hdac_stream_setup_periods - set up BDL entries
324 * @azx_dev: HD-audio core stream to set up
326 * Set up the buffer descriptor table of the given stream based on the
327 * period and buffer sizes of the assigned PCM substream.
329 int snd_hdac_stream_setup_periods(struct hdac_stream
*azx_dev
)
331 struct hdac_bus
*bus
= azx_dev
->bus
;
332 struct snd_pcm_substream
*substream
= azx_dev
->substream
;
333 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
335 int i
, ofs
, periods
, period_bytes
;
336 int pos_adj
, pos_align
;
338 /* reset BDL address */
339 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, 0);
340 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
, 0);
342 period_bytes
= azx_dev
->period_bytes
;
343 periods
= azx_dev
->bufsize
/ period_bytes
;
345 /* program the initial BDL entries */
346 bdl
= (__le32
*)azx_dev
->bdl
.area
;
350 pos_adj
= bus
->bdl_pos_adj
;
351 if (!azx_dev
->no_period_wakeup
&& pos_adj
> 0) {
353 pos_adj
= (pos_adj
* runtime
->rate
+ 47999) / 48000;
357 pos_adj
= ((pos_adj
+ pos_align
- 1) / pos_align
) *
359 pos_adj
= frames_to_bytes(runtime
, pos_adj
);
360 if (pos_adj
>= period_bytes
) {
361 dev_warn(bus
->dev
, "Too big adjustment %d\n",
365 ofs
= setup_bdle(bus
, snd_pcm_get_dma_buf(substream
),
367 &bdl
, ofs
, pos_adj
, true);
374 for (i
= 0; i
< periods
; i
++) {
375 if (i
== periods
- 1 && pos_adj
)
376 ofs
= setup_bdle(bus
, snd_pcm_get_dma_buf(substream
),
378 period_bytes
- pos_adj
, 0);
380 ofs
= setup_bdle(bus
, snd_pcm_get_dma_buf(substream
),
383 !azx_dev
->no_period_wakeup
);
390 dev_err(bus
->dev
, "Too many BDL entries: buffer=%d, period=%d\n",
391 azx_dev
->bufsize
, period_bytes
);
394 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods
);
396 static cycle_t
azx_cc_read(const struct cyclecounter
*cc
)
398 struct hdac_stream
*azx_dev
= container_of(cc
, struct hdac_stream
, cc
);
400 return snd_hdac_chip_readl(azx_dev
->bus
, WALLCLK
);
403 static void azx_timecounter_init(struct hdac_stream
*azx_dev
,
404 bool force
, cycle_t last
)
406 struct timecounter
*tc
= &azx_dev
->tc
;
407 struct cyclecounter
*cc
= &azx_dev
->cc
;
410 cc
->read
= azx_cc_read
;
411 cc
->mask
= CLOCKSOURCE_MASK(32);
414 * Converting from 24 MHz to ns means applying a 125/3 factor.
415 * To avoid any saturation issues in intermediate operations,
416 * the 125 factor is applied first. The division is applied
417 * last after reading the timecounter value.
418 * Applying the 1/3 factor as part of the multiplication
419 * requires at least 20 bits for a decent precision, however
420 * overflows occur after about 4 hours or less, not a option.
423 cc
->mult
= 125; /* saturation after 195 years */
426 nsec
= 0; /* audio time is elapsed time since trigger */
427 timecounter_init(tc
, cc
, nsec
);
430 * force timecounter to use predefined value,
431 * used for synchronized starts
433 tc
->cycle_last
= last
;
438 * snd_hdac_stream_timecounter_init - initialize time counter
439 * @azx_dev: HD-audio core stream (master stream)
440 * @streams: bit flags of streams to set up
442 * Initializes the time counter of streams marked by the bit flags (each
443 * bit corresponds to the stream index).
444 * The trigger timestamp of PCM substream assigned to the given stream is
445 * updated accordingly, too.
447 void snd_hdac_stream_timecounter_init(struct hdac_stream
*azx_dev
,
448 unsigned int streams
)
450 struct hdac_bus
*bus
= azx_dev
->bus
;
451 struct snd_pcm_runtime
*runtime
= azx_dev
->substream
->runtime
;
452 struct hdac_stream
*s
;
454 cycle_t cycle_last
= 0;
457 list_for_each_entry(s
, &bus
->stream_list
, list
) {
458 if (streams
& (1 << i
)) {
459 azx_timecounter_init(s
, inited
, cycle_last
);
462 cycle_last
= s
->tc
.cycle_last
;
468 snd_pcm_gettime(runtime
, &runtime
->trigger_tstamp
);
469 runtime
->trigger_tstamp_latched
= true;
471 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init
);
474 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
475 * @azx_dev: HD-audio core stream (master stream)
476 * @streams: bit flags of streams to sync
478 void snd_hdac_stream_sync_trigger(struct hdac_stream
*azx_dev
, bool set
,
479 unsigned int streams
, unsigned int reg
)
481 struct hdac_bus
*bus
= azx_dev
->bus
;
486 val
= _snd_hdac_chip_read(l
, bus
, reg
);
491 _snd_hdac_chip_write(l
, bus
, reg
, val
);
493 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger
);
496 * snd_hdac_stream_sync - sync with start/strop trigger operation
497 * @azx_dev: HD-audio core stream (master stream)
498 * @start: true = start, false = stop
499 * @streams: bit flags of streams to sync
501 * For @start = true, wait until all FIFOs get ready.
502 * For @start = false, wait until all RUN bits are cleared.
504 void snd_hdac_stream_sync(struct hdac_stream
*azx_dev
, bool start
,
505 unsigned int streams
)
507 struct hdac_bus
*bus
= azx_dev
->bus
;
508 int i
, nwait
, timeout
;
509 struct hdac_stream
*s
;
511 for (timeout
= 5000; timeout
; timeout
--) {
514 list_for_each_entry(s
, &bus
->stream_list
, list
) {
515 if (streams
& (1 << i
)) {
517 /* check FIFO gets ready */
518 if (!(snd_hdac_stream_readb(s
, SD_STS
) &
522 /* check RUN bit is cleared */
523 if (snd_hdac_stream_readb(s
, SD_CTL
) &
535 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync
);
537 #ifdef CONFIG_SND_HDA_DSP_LOADER
539 * snd_hdac_dsp_prepare - prepare for DSP loading
540 * @azx_dev: HD-audio core stream used for DSP loading
541 * @format: HD-audio stream format
542 * @byte_size: data chunk byte size
543 * @bufp: allocated buffer
545 * Allocate the buffer for the given size and set up the given stream for
546 * DSP loading. Returns the stream tag (>= 0), or a negative error code.
548 int snd_hdac_dsp_prepare(struct hdac_stream
*azx_dev
, unsigned int format
,
549 unsigned int byte_size
, struct snd_dma_buffer
*bufp
)
551 struct hdac_bus
*bus
= azx_dev
->bus
;
555 snd_hdac_dsp_lock(azx_dev
);
556 spin_lock_irq(&bus
->reg_lock
);
557 if (azx_dev
->running
|| azx_dev
->locked
) {
558 spin_unlock_irq(&bus
->reg_lock
);
562 azx_dev
->locked
= true;
563 spin_unlock_irq(&bus
->reg_lock
);
565 err
= bus
->io_ops
->dma_alloc_pages(bus
, SNDRV_DMA_TYPE_DEV_SG
,
570 azx_dev
->bufsize
= byte_size
;
571 azx_dev
->period_bytes
= byte_size
;
572 azx_dev
->format_val
= format
;
574 snd_hdac_stream_reset(azx_dev
);
576 /* reset BDL address */
577 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, 0);
578 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
, 0);
581 bdl
= (u32
*)azx_dev
->bdl
.area
;
582 err
= setup_bdle(bus
, bufp
, azx_dev
, &bdl
, 0, byte_size
, 0);
586 snd_hdac_stream_setup(azx_dev
);
587 snd_hdac_dsp_unlock(azx_dev
);
588 return azx_dev
->stream_tag
;
591 bus
->io_ops
->dma_free_pages(bus
, bufp
);
593 spin_lock_irq(&bus
->reg_lock
);
594 azx_dev
->locked
= false;
595 spin_unlock_irq(&bus
->reg_lock
);
597 snd_hdac_dsp_unlock(azx_dev
);
600 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare
);
603 * snd_hdac_dsp_trigger - start / stop DSP loading
604 * @azx_dev: HD-audio core stream used for DSP loading
605 * @start: trigger start or stop
607 void snd_hdac_dsp_trigger(struct hdac_stream
*azx_dev
, bool start
)
610 snd_hdac_stream_start(azx_dev
, true);
612 snd_hdac_stream_stop(azx_dev
);
614 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger
);
617 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
618 * @azx_dev: HD-audio core stream used for DSP loading
619 * @dmab: buffer used by DSP loading
621 void snd_hdac_dsp_cleanup(struct hdac_stream
*azx_dev
,
622 struct snd_dma_buffer
*dmab
)
624 struct hdac_bus
*bus
= azx_dev
->bus
;
626 if (!dmab
->area
|| !azx_dev
->locked
)
629 snd_hdac_dsp_lock(azx_dev
);
630 /* reset BDL address */
631 snd_hdac_stream_writel(azx_dev
, SD_BDLPL
, 0);
632 snd_hdac_stream_writel(azx_dev
, SD_BDLPU
, 0);
633 snd_hdac_stream_writel(azx_dev
, SD_CTL
, 0);
634 azx_dev
->bufsize
= 0;
635 azx_dev
->period_bytes
= 0;
636 azx_dev
->format_val
= 0;
638 bus
->io_ops
->dma_free_pages(bus
, dmab
);
641 spin_lock_irq(&bus
->reg_lock
);
642 azx_dev
->locked
= false;
643 spin_unlock_irq(&bus
->reg_lock
);
644 snd_hdac_dsp_unlock(azx_dev
);
646 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup
);
647 #endif /* CONFIG_SND_HDA_DSP_LOADER */