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Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik...
[deliverable/linux.git] / sound / oss / es1371.c
1 /*****************************************************************************/
2
3 /*
4 * es1371.c -- Creative Ensoniq ES1371.
5 *
6 * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Special thanks to Ensoniq
23 *
24 * Supported devices:
25 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
26 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
27 * /dev/dsp1 additional DAC, like /dev/dsp, but outputs to mixer "SYNTH" setting
28 * /dev/midi simple MIDI UART interface, no ioctl
29 *
30 * NOTE: the card does not have any FM/Wavetable synthesizer, it is supposed
31 * to be done in software. That is what /dev/dac is for. By now (Q2 1998)
32 * there are several MIDI to PCM (WAV) packages, one of them is timidity.
33 *
34 * Revision history
35 * 04.06.1998 0.1 Initial release
36 * Mixer stuff should be overhauled; especially optional AC97 mixer bits
37 * should be detected. This results in strange behaviour of some mixer
38 * settings, like master volume and mic.
39 * 08.06.1998 0.2 First release using Alan Cox' soundcore instead of miscdevice
40 * 03.08.1998 0.3 Do not include modversions.h
41 * Now mixer behaviour can basically be selected between
42 * "OSS documented" and "OSS actual" behaviour
43 * 31.08.1998 0.4 Fix realplayer problems - dac.count issues
44 * 27.10.1998 0.5 Fix joystick support
45 * -- Oliver Neukum (c188@org.chemie.uni-muenchen.de)
46 * 10.12.1998 0.6 Fix drain_dac trying to wait on not yet initialized DMA
47 * 23.12.1998 0.7 Fix a few f_file & FMODE_ bugs
48 * Don't wake up app until there are fragsize bytes to read/write
49 * 06.01.1999 0.8 remove the silly SA_INTERRUPT flag.
50 * hopefully killed the egcs section type conflict
51 * 12.03.1999 0.9 cinfo.blocks should be reset after GETxPTR ioctl.
52 * reported by Johan Maes <joma@telindus.be>
53 * 22.03.1999 0.10 return EAGAIN instead of EBUSY when O_NONBLOCK
54 * read/write cannot be executed
55 * 07.04.1999 0.11 implemented the following ioctl's: SOUND_PCM_READ_RATE,
56 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
57 * Alpha fixes reported by Peter Jones <pjones@redhat.com>
58 * Another Alpha fix (wait_src_ready in init routine)
59 * reported by "Ivan N. Kokshaysky" <ink@jurassic.park.msu.ru>
60 * Note: joystick address handling might still be wrong on archs
61 * other than i386
62 * 15.06.1999 0.12 Fix bad allocation bug.
63 * Thanks to Deti Fliegl <fliegl@in.tum.de>
64 * 28.06.1999 0.13 Add pci_set_master
65 * 03.08.1999 0.14 adapt to Linus' new __setup/__initcall
66 * added kernel command line option "es1371=joystickaddr"
67 * removed CONFIG_SOUND_ES1371_JOYPORT_BOOT kludge
68 * 10.08.1999 0.15 (Re)added S/PDIF module option for cards revision >= 4.
69 * Initial version by Dave Platt <dplatt@snulbug.mtview.ca.us>.
70 * module_init/__setup fixes
71 * 08.16.1999 0.16 Joe Cotellese <joec@ensoniq.com>
72 * Added detection for ES1371 revision ID so that we can
73 * detect the ES1373 and later parts.
74 * added AC97 #defines for readability
75 * added a /proc file system for dumping hardware state
76 * updated SRC and CODEC w/r functions to accommodate bugs
77 * in some versions of the ES137x chips.
78 * 31.08.1999 0.17 add spin_lock_init
79 * replaced current->state = x with set_current_state(x)
80 * 03.09.1999 0.18 change read semantics for MIDI to match
81 * OSS more closely; remove possible wakeup race
82 * 21.10.1999 0.19 Round sampling rates, requested by
83 * Kasamatsu Kenichi <t29w0267@ip.media.kyoto-u.ac.jp>
84 * 27.10.1999 0.20 Added SigmaTel 3D enhancement string
85 * Codec ID printing changes
86 * 28.10.1999 0.21 More waitqueue races fixed
87 * Joe Cotellese <joec@ensoniq.com>
88 * Changed PCI detection routine so we can more easily
89 * detect ES137x chip and derivatives.
90 * 05.01.2000 0.22 Should now work with rev7 boards; patch by
91 * Eric Lemar, elemar@cs.washington.edu
92 * 08.01.2000 0.23 Prevent some ioctl's from returning bad count values on underrun/overrun;
93 * Tim Janik's BSE (Bedevilled Sound Engine) found this
94 * 07.02.2000 0.24 Use pci_alloc_consistent and pci_register_driver
95 * 07.02.2000 0.25 Use ac97_codec
96 * 01.03.2000 0.26 SPDIF patch by Mikael Bouillot <mikael.bouillot@bigfoot.com>
97 * Use pci_module_init
98 * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
99 * 12.12.2000 0.28 More dma buffer initializations, patch from
100 * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
101 * 05.01.2001 0.29 Hopefully updates will not be required anymore when Creative bumps
102 * the CT5880 revision.
103 * suggested by Stephan Müller <smueller@chronox.de>
104 * 31.01.2001 0.30 Register/Unregister gameport
105 * Fix SETTRIGGER non OSS API conformity
106 * 14.07.2001 0.31 Add list of laptops needing amplifier control
107 * 03.01.2003 0.32 open_mode fixes from Georg Acher <acher@in.tum.de>
108 */
109
110 /*****************************************************************************/
111
112 #include <linux/interrupt.h>
113 #include <linux/module.h>
114 #include <linux/string.h>
115 #include <linux/ioport.h>
116 #include <linux/sched.h>
117 #include <linux/delay.h>
118 #include <linux/sound.h>
119 #include <linux/slab.h>
120 #include <linux/soundcard.h>
121 #include <linux/pci.h>
122 #include <linux/init.h>
123 #include <linux/poll.h>
124 #include <linux/bitops.h>
125 #include <linux/proc_fs.h>
126 #include <linux/spinlock.h>
127 #include <linux/smp_lock.h>
128 #include <linux/ac97_codec.h>
129 #include <linux/gameport.h>
130 #include <linux/wait.h>
131 #include <linux/dma-mapping.h>
132 #include <linux/mutex.h>
133 #include <linux/mm.h>
134
135 #include <asm/io.h>
136 #include <asm/page.h>
137 #include <asm/uaccess.h>
138
139 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
140 #define SUPPORT_JOYSTICK
141 #endif
142
143 /* --------------------------------------------------------------------- */
144
145 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
146 #define ES1371_DEBUG
147 #define DBG(x) {}
148 /*#define DBG(x) {x}*/
149
150 /* --------------------------------------------------------------------- */
151
152 #ifndef PCI_VENDOR_ID_ENSONIQ
153 #define PCI_VENDOR_ID_ENSONIQ 0x1274
154 #endif
155
156 #ifndef PCI_VENDOR_ID_ECTIVA
157 #define PCI_VENDOR_ID_ECTIVA 0x1102
158 #endif
159
160 #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
161 #define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
162 #endif
163
164 #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
165 #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
166 #endif
167
168 #ifndef PCI_DEVICE_ID_ECTIVA_EV1938
169 #define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
170 #endif
171
172 /* ES1371 chip ID */
173 /* This is a little confusing because all ES1371 compatible chips have the
174 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
175 This is only significant if you want to enable features on the later parts.
176 Yes, I know it's stupid and why didn't we use the sub IDs?
177 */
178 #define ES1371REV_ES1373_A 0x04
179 #define ES1371REV_ES1373_B 0x06
180 #define ES1371REV_CT5880_A 0x07
181 #define CT5880REV_CT5880_C 0x02
182 #define CT5880REV_CT5880_D 0x03
183 #define ES1371REV_ES1371_B 0x09
184 #define EV1938REV_EV1938_A 0x00
185 #define ES1371REV_ES1373_8 0x08
186
187 #define ES1371_MAGIC ((PCI_VENDOR_ID_ENSONIQ<<16)|PCI_DEVICE_ID_ENSONIQ_ES1371)
188
189 #define ES1371_EXTENT 0x40
190 #define JOY_EXTENT 8
191
192 #define ES1371_REG_CONTROL 0x00
193 #define ES1371_REG_STATUS 0x04 /* on the 5880 it is control/status */
194 #define ES1371_REG_UART_DATA 0x08
195 #define ES1371_REG_UART_STATUS 0x09
196 #define ES1371_REG_UART_CONTROL 0x09
197 #define ES1371_REG_UART_TEST 0x0a
198 #define ES1371_REG_MEMPAGE 0x0c
199 #define ES1371_REG_SRCONV 0x10
200 #define ES1371_REG_CODEC 0x14
201 #define ES1371_REG_LEGACY 0x18
202 #define ES1371_REG_SERIAL_CONTROL 0x20
203 #define ES1371_REG_DAC1_SCOUNT 0x24
204 #define ES1371_REG_DAC2_SCOUNT 0x28
205 #define ES1371_REG_ADC_SCOUNT 0x2c
206
207 #define ES1371_REG_DAC1_FRAMEADR 0xc30
208 #define ES1371_REG_DAC1_FRAMECNT 0xc34
209 #define ES1371_REG_DAC2_FRAMEADR 0xc38
210 #define ES1371_REG_DAC2_FRAMECNT 0xc3c
211 #define ES1371_REG_ADC_FRAMEADR 0xd30
212 #define ES1371_REG_ADC_FRAMECNT 0xd34
213
214 #define ES1371_FMT_U8_MONO 0
215 #define ES1371_FMT_U8_STEREO 1
216 #define ES1371_FMT_S16_MONO 2
217 #define ES1371_FMT_S16_STEREO 3
218 #define ES1371_FMT_STEREO 1
219 #define ES1371_FMT_S16 2
220 #define ES1371_FMT_MASK 3
221
222 static const unsigned sample_size[] = { 1, 2, 2, 4 };
223 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
224
225 #define CTRL_RECEN_B 0x08000000 /* 1 = don't mix analog in to digital out */
226 #define CTRL_SPDIFEN_B 0x04000000
227 #define CTRL_JOY_SHIFT 24
228 #define CTRL_JOY_MASK 3
229 #define CTRL_JOY_200 0x00000000 /* joystick base address */
230 #define CTRL_JOY_208 0x01000000
231 #define CTRL_JOY_210 0x02000000
232 #define CTRL_JOY_218 0x03000000
233 #define CTRL_GPIO_IN0 0x00100000 /* general purpose inputs/outputs */
234 #define CTRL_GPIO_IN1 0x00200000
235 #define CTRL_GPIO_IN2 0x00400000
236 #define CTRL_GPIO_IN3 0x00800000
237 #define CTRL_GPIO_OUT0 0x00010000
238 #define CTRL_GPIO_OUT1 0x00020000
239 #define CTRL_GPIO_OUT2 0x00040000
240 #define CTRL_GPIO_OUT3 0x00080000
241 #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
242 #define CTRL_SYNCRES 0x00004000 /* AC97 warm reset */
243 #define CTRL_ADCSTOP 0x00002000 /* stop ADC transfers */
244 #define CTRL_PWR_INTRM 0x00001000 /* 1 = power level ints enabled */
245 #define CTRL_M_CB 0x00000800 /* recording source: 0 = ADC, 1 = MPEG */
246 #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
247 #define CTRL_PDLEV0 0x00000000 /* power down level */
248 #define CTRL_PDLEV1 0x00000100
249 #define CTRL_PDLEV2 0x00000200
250 #define CTRL_PDLEV3 0x00000300
251 #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
252 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
253 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
254 #define CTRL_ADC_EN 0x00000010 /* enable ADC */
255 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
256 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port */
257 #define CTRL_XTALCLKDIS 0x00000002 /* 1 = disable crystal clock input */
258 #define CTRL_PCICLKDIS 0x00000001 /* 1 = disable PCI clock distribution */
259
260
261 #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
262 #define CSTAT_5880_AC97_RST 0x20000000 /* CT5880 Reset bit */
263 #define STAT_EN_SPDIF 0x00040000 /* enable S/PDIF circuitry */
264 #define STAT_TS_SPDIF 0x00020000 /* test S/PDIF circuitry */
265 #define STAT_TESTMODE 0x00010000 /* test ASIC */
266 #define STAT_SYNC_ERR 0x00000100 /* 1 = codec sync error */
267 #define STAT_VC 0x000000c0 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
268 #define STAT_SH_VC 6
269 #define STAT_MPWR 0x00000020 /* power level interrupt */
270 #define STAT_MCCB 0x00000010 /* CCB int pending */
271 #define STAT_UART 0x00000008 /* UART int pending */
272 #define STAT_DAC1 0x00000004 /* DAC1 int pending */
273 #define STAT_DAC2 0x00000002 /* DAC2 int pending */
274 #define STAT_ADC 0x00000001 /* ADC int pending */
275
276 #define USTAT_RXINT 0x80 /* UART rx int pending */
277 #define USTAT_TXINT 0x04 /* UART tx int pending */
278 #define USTAT_TXRDY 0x02 /* UART tx ready */
279 #define USTAT_RXRDY 0x01 /* UART rx ready */
280
281 #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
282 #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
283 #define UCTRL_ENA_TXINT 0x20 /* enable TX int */
284 #define UCTRL_CNTRL 0x03 /* control field */
285 #define UCTRL_CNTRL_SWR 0x03 /* software reset command */
286
287 /* sample rate converter */
288 #define SRC_OKSTATE 1
289
290 #define SRC_RAMADDR_MASK 0xfe000000
291 #define SRC_RAMADDR_SHIFT 25
292 #define SRC_DAC1FREEZE (1UL << 21)
293 #define SRC_DAC2FREEZE (1UL << 20)
294 #define SRC_ADCFREEZE (1UL << 19)
295
296
297 #define SRC_WE 0x01000000 /* read/write control for SRC RAM */
298 #define SRC_BUSY 0x00800000 /* SRC busy */
299 #define SRC_DIS 0x00400000 /* 1 = disable SRC */
300 #define SRC_DDAC1 0x00200000 /* 1 = disable accum update for DAC1 */
301 #define SRC_DDAC2 0x00100000 /* 1 = disable accum update for DAC2 */
302 #define SRC_DADC 0x00080000 /* 1 = disable accum update for ADC2 */
303 #define SRC_CTLMASK 0x00780000
304 #define SRC_RAMDATA_MASK 0x0000ffff
305 #define SRC_RAMDATA_SHIFT 0
306
307 #define SRCREG_ADC 0x78
308 #define SRCREG_DAC1 0x70
309 #define SRCREG_DAC2 0x74
310 #define SRCREG_VOL_ADC 0x6c
311 #define SRCREG_VOL_DAC1 0x7c
312 #define SRCREG_VOL_DAC2 0x7e
313
314 #define SRCREG_TRUNC_N 0x00
315 #define SRCREG_INT_REGS 0x01
316 #define SRCREG_ACCUM_FRAC 0x02
317 #define SRCREG_VFREQ_FRAC 0x03
318
319 #define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
320 #define CODEC_PIADD_MASK 0x007f0000
321 #define CODEC_PIADD_SHIFT 16
322 #define CODEC_PIDAT_MASK 0x0000ffff
323 #define CODEC_PIDAT_SHIFT 0
324
325 #define CODEC_RDY 0x80000000 /* AC97 read data valid */
326 #define CODEC_WIP 0x40000000 /* AC97 write in progress */
327 #define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
328 #define CODEC_POADD_MASK 0x007f0000
329 #define CODEC_POADD_SHIFT 16
330 #define CODEC_PODAT_MASK 0x0000ffff
331 #define CODEC_PODAT_SHIFT 0
332
333
334 #define LEGACY_JFAST 0x80000000 /* fast joystick timing */
335 #define LEGACY_FIRQ 0x01000000 /* force IRQ */
336
337 #define SCTRL_DACTEST 0x00400000 /* 1 = DAC test, test vector generation purposes */
338 #define SCTRL_P2ENDINC 0x00380000 /* */
339 #define SCTRL_SH_P2ENDINC 19
340 #define SCTRL_P2STINC 0x00070000 /* */
341 #define SCTRL_SH_P2STINC 16
342 #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
343 #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
344 #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
345 #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
346 #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
347 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
348 #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
349 #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
350 #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
351 #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
352 #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
353 #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
354 #define SCTRL_R1FMT 0x00000030 /* format mask */
355 #define SCTRL_SH_R1FMT 4
356 #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
357 #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
358 #define SCTRL_P2FMT 0x0000000c /* format mask */
359 #define SCTRL_SH_P2FMT 2
360 #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
361 #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
362 #define SCTRL_P1FMT 0x00000003 /* format mask */
363 #define SCTRL_SH_P1FMT 0
364
365
366 /* misc stuff */
367 #define POLL_COUNT 0x1000
368 #define FMODE_DAC 4 /* slight misuse of mode_t */
369
370 /* MIDI buffer sizes */
371
372 #define MIDIINBUF 256
373 #define MIDIOUTBUF 256
374
375 #define FMODE_MIDI_SHIFT 3
376 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
377 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
378
379 #define ES1371_MODULE_NAME "es1371"
380 #define PFX ES1371_MODULE_NAME ": "
381
382 /* --------------------------------------------------------------------- */
383
384 struct es1371_state {
385 /* magic */
386 unsigned int magic;
387
388 /* list of es1371 devices */
389 struct list_head devs;
390
391 /* the corresponding pci_dev structure */
392 struct pci_dev *dev;
393
394 /* soundcore stuff */
395 int dev_audio;
396 int dev_dac;
397 int dev_midi;
398
399 /* hardware resources */
400 unsigned long io; /* long for SPARC */
401 unsigned int irq;
402
403 /* PCI ID's */
404 u16 vendor;
405 u16 device;
406 u8 rev; /* the chip revision */
407
408 /* options */
409 int spdif_volume; /* S/PDIF output is enabled if != -1 */
410
411 #ifdef ES1371_DEBUG
412 /* debug /proc entry */
413 struct proc_dir_entry *ps;
414 #endif /* ES1371_DEBUG */
415
416 struct ac97_codec *codec;
417
418 /* wave stuff */
419 unsigned ctrl;
420 unsigned sctrl;
421 unsigned dac1rate, dac2rate, adcrate;
422
423 spinlock_t lock;
424 struct mutex open_mutex;
425 mode_t open_mode;
426 wait_queue_head_t open_wait;
427
428 struct dmabuf {
429 void *rawbuf;
430 dma_addr_t dmaaddr;
431 unsigned buforder;
432 unsigned numfrag;
433 unsigned fragshift;
434 unsigned hwptr, swptr;
435 unsigned total_bytes;
436 int count;
437 unsigned error; /* over/underrun */
438 wait_queue_head_t wait;
439 /* redundant, but makes calculations easier */
440 unsigned fragsize;
441 unsigned dmasize;
442 unsigned fragsamples;
443 /* OSS stuff */
444 unsigned mapped:1;
445 unsigned ready:1;
446 unsigned endcleared:1;
447 unsigned enabled:1;
448 unsigned ossfragshift;
449 int ossmaxfrags;
450 unsigned subdivision;
451 } dma_dac1, dma_dac2, dma_adc;
452
453 /* midi stuff */
454 struct {
455 unsigned ird, iwr, icnt;
456 unsigned ord, owr, ocnt;
457 wait_queue_head_t iwait;
458 wait_queue_head_t owait;
459 unsigned char ibuf[MIDIINBUF];
460 unsigned char obuf[MIDIOUTBUF];
461 } midi;
462
463 #ifdef SUPPORT_JOYSTICK
464 struct gameport *gameport;
465 #endif
466
467 struct mutex sem;
468 };
469
470 /* --------------------------------------------------------------------- */
471
472 static LIST_HEAD(devs);
473
474 /* --------------------------------------------------------------------- */
475
476 static inline unsigned ld2(unsigned int x)
477 {
478 unsigned r = 0;
479
480 if (x >= 0x10000) {
481 x >>= 16;
482 r += 16;
483 }
484 if (x >= 0x100) {
485 x >>= 8;
486 r += 8;
487 }
488 if (x >= 0x10) {
489 x >>= 4;
490 r += 4;
491 }
492 if (x >= 4) {
493 x >>= 2;
494 r += 2;
495 }
496 if (x >= 2)
497 r++;
498 return r;
499 }
500
501 /* --------------------------------------------------------------------- */
502
503 static unsigned wait_src_ready(struct es1371_state *s)
504 {
505 unsigned int t, r;
506
507 for (t = 0; t < POLL_COUNT; t++) {
508 if (!((r = inl(s->io + ES1371_REG_SRCONV)) & SRC_BUSY))
509 return r;
510 udelay(1);
511 }
512 printk(KERN_DEBUG PFX "sample rate converter timeout r = 0x%08x\n", r);
513 return r;
514 }
515
516 static unsigned src_read(struct es1371_state *s, unsigned reg)
517 {
518 unsigned int temp,i,orig;
519
520 /* wait for ready */
521 temp = wait_src_ready (s);
522
523 /* we can only access the SRC at certain times, make sure
524 we're allowed to before we read */
525
526 orig = temp;
527 /* expose the SRC state bits */
528 outl ( (temp & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT) | 0x10000UL,
529 s->io + ES1371_REG_SRCONV);
530
531 /* now, wait for busy and the correct time to read */
532 temp = wait_src_ready (s);
533
534 if ( (temp & 0x00870000UL ) != ( SRC_OKSTATE << 16 )){
535 /* wait for the right state */
536 for (i=0; i<POLL_COUNT; i++){
537 temp = inl (s->io + ES1371_REG_SRCONV);
538 if ( (temp & 0x00870000UL ) == ( SRC_OKSTATE << 16 ))
539 break;
540 }
541 }
542
543 /* hide the state bits */
544 outl ((orig & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT), s->io + ES1371_REG_SRCONV);
545 return temp;
546
547
548 }
549
550 static void src_write(struct es1371_state *s, unsigned reg, unsigned data)
551 {
552
553 unsigned int r;
554
555 r = wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC);
556 r |= (reg << SRC_RAMADDR_SHIFT) & SRC_RAMADDR_MASK;
557 r |= (data << SRC_RAMDATA_SHIFT) & SRC_RAMDATA_MASK;
558 outl(r | SRC_WE, s->io + ES1371_REG_SRCONV);
559
560 }
561
562 /* --------------------------------------------------------------------- */
563
564 /* most of the following here is black magic */
565 static void set_adc_rate(struct es1371_state *s, unsigned rate)
566 {
567 unsigned long flags;
568 unsigned int n, truncm, freq;
569
570 if (rate > 48000)
571 rate = 48000;
572 if (rate < 4000)
573 rate = 4000;
574 n = rate / 3000;
575 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
576 n--;
577 truncm = (21 * n - 1) | 1;
578 freq = ((48000UL << 15) / rate) * n;
579 s->adcrate = (48000UL << 15) / (freq / n);
580 spin_lock_irqsave(&s->lock, flags);
581 if (rate >= 24000) {
582 if (truncm > 239)
583 truncm = 239;
584 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
585 (((239 - truncm) >> 1) << 9) | (n << 4));
586 } else {
587 if (truncm > 119)
588 truncm = 119;
589 src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
590 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
591 }
592 src_write(s, SRCREG_ADC+SRCREG_INT_REGS,
593 (src_read(s, SRCREG_ADC+SRCREG_INT_REGS) & 0x00ff) |
594 ((freq >> 5) & 0xfc00));
595 src_write(s, SRCREG_ADC+SRCREG_VFREQ_FRAC, freq & 0x7fff);
596 src_write(s, SRCREG_VOL_ADC, n << 8);
597 src_write(s, SRCREG_VOL_ADC+1, n << 8);
598 spin_unlock_irqrestore(&s->lock, flags);
599 }
600
601
602 static void set_dac1_rate(struct es1371_state *s, unsigned rate)
603 {
604 unsigned long flags;
605 unsigned int freq, r;
606
607 if (rate > 48000)
608 rate = 48000;
609 if (rate < 4000)
610 rate = 4000;
611 freq = ((rate << 15) + 1500) / 3000;
612 s->dac1rate = (freq * 3000 + 16384) >> 15;
613 spin_lock_irqsave(&s->lock, flags);
614 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC)) | SRC_DDAC1;
615 outl(r, s->io + ES1371_REG_SRCONV);
616 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS,
617 (src_read(s, SRCREG_DAC1+SRCREG_INT_REGS) & 0x00ff) |
618 ((freq >> 5) & 0xfc00));
619 src_write(s, SRCREG_DAC1+SRCREG_VFREQ_FRAC, freq & 0x7fff);
620 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC));
621 outl(r, s->io + ES1371_REG_SRCONV);
622 spin_unlock_irqrestore(&s->lock, flags);
623 }
624
625 static void set_dac2_rate(struct es1371_state *s, unsigned rate)
626 {
627 unsigned long flags;
628 unsigned int freq, r;
629
630 if (rate > 48000)
631 rate = 48000;
632 if (rate < 4000)
633 rate = 4000;
634 freq = ((rate << 15) + 1500) / 3000;
635 s->dac2rate = (freq * 3000 + 16384) >> 15;
636 spin_lock_irqsave(&s->lock, flags);
637 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC)) | SRC_DDAC2;
638 outl(r, s->io + ES1371_REG_SRCONV);
639 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS,
640 (src_read(s, SRCREG_DAC2+SRCREG_INT_REGS) & 0x00ff) |
641 ((freq >> 5) & 0xfc00));
642 src_write(s, SRCREG_DAC2+SRCREG_VFREQ_FRAC, freq & 0x7fff);
643 r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC));
644 outl(r, s->io + ES1371_REG_SRCONV);
645 spin_unlock_irqrestore(&s->lock, flags);
646 }
647
648 /* --------------------------------------------------------------------- */
649
650 static void __devinit src_init(struct es1371_state *s)
651 {
652 unsigned int i;
653
654 /* before we enable or disable the SRC we need
655 to wait for it to become ready */
656 wait_src_ready(s);
657
658 outl(SRC_DIS, s->io + ES1371_REG_SRCONV);
659
660 for (i = 0; i < 0x80; i++)
661 src_write(s, i, 0);
662
663 src_write(s, SRCREG_DAC1+SRCREG_TRUNC_N, 16 << 4);
664 src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 16 << 10);
665 src_write(s, SRCREG_DAC2+SRCREG_TRUNC_N, 16 << 4);
666 src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 16 << 10);
667 src_write(s, SRCREG_VOL_ADC, 1 << 12);
668 src_write(s, SRCREG_VOL_ADC+1, 1 << 12);
669 src_write(s, SRCREG_VOL_DAC1, 1 << 12);
670 src_write(s, SRCREG_VOL_DAC1+1, 1 << 12);
671 src_write(s, SRCREG_VOL_DAC2, 1 << 12);
672 src_write(s, SRCREG_VOL_DAC2+1, 1 << 12);
673 set_adc_rate(s, 22050);
674 set_dac1_rate(s, 22050);
675 set_dac2_rate(s, 22050);
676
677 /* WARNING:
678 * enabling the sample rate converter without properly programming
679 * its parameters causes the chip to lock up (the SRC busy bit will
680 * be stuck high, and I've found no way to rectify this other than
681 * power cycle)
682 */
683 wait_src_ready(s);
684 outl(0, s->io+ES1371_REG_SRCONV);
685 }
686
687 /* --------------------------------------------------------------------- */
688
689 static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
690 {
691 struct es1371_state *s = (struct es1371_state *)codec->private_data;
692 unsigned long flags;
693 unsigned t, x;
694
695 spin_lock_irqsave(&s->lock, flags);
696 for (t = 0; t < POLL_COUNT; t++)
697 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
698 break;
699
700 /* save the current state for later */
701 x = wait_src_ready(s);
702
703 /* enable SRC state data in SRC mux */
704 outl((x & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC)) | 0x00010000,
705 s->io+ES1371_REG_SRCONV);
706
707 /* wait for not busy (state 0) first to avoid
708 transition states */
709 for (t=0; t<POLL_COUNT; t++){
710 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
711 break;
712 udelay(1);
713 }
714
715 /* wait for a SAFE time to write addr/data and then do it, dammit */
716 for (t=0; t<POLL_COUNT; t++){
717 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
718 break;
719 udelay(1);
720 }
721
722 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) |
723 ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), s->io+ES1371_REG_CODEC);
724
725 /* restore SRC reg */
726 wait_src_ready(s);
727 outl(x, s->io+ES1371_REG_SRCONV);
728 spin_unlock_irqrestore(&s->lock, flags);
729 }
730
731 static u16 rdcodec(struct ac97_codec *codec, u8 addr)
732 {
733 struct es1371_state *s = (struct es1371_state *)codec->private_data;
734 unsigned long flags;
735 unsigned t, x;
736
737 spin_lock_irqsave(&s->lock, flags);
738
739 /* wait for WIP to go away */
740 for (t = 0; t < 0x1000; t++)
741 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
742 break;
743
744 /* save the current state for later */
745 x = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC));
746
747 /* enable SRC state data in SRC mux */
748 outl( x | 0x00010000,
749 s->io+ES1371_REG_SRCONV);
750
751 /* wait for not busy (state 0) first to avoid
752 transition states */
753 for (t=0; t<POLL_COUNT; t++){
754 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
755 break;
756 udelay(1);
757 }
758
759 /* wait for a SAFE time to write addr/data and then do it, dammit */
760 for (t=0; t<POLL_COUNT; t++){
761 if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
762 break;
763 udelay(1);
764 }
765
766 outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD, s->io+ES1371_REG_CODEC);
767 /* restore SRC reg */
768 wait_src_ready(s);
769 outl(x, s->io+ES1371_REG_SRCONV);
770
771 /* wait for WIP again */
772 for (t = 0; t < 0x1000; t++)
773 if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
774 break;
775
776 /* now wait for the stinkin' data (RDY) */
777 for (t = 0; t < POLL_COUNT; t++)
778 if ((x = inl(s->io+ES1371_REG_CODEC)) & CODEC_RDY)
779 break;
780
781 spin_unlock_irqrestore(&s->lock, flags);
782 return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT);
783 }
784
785 /* --------------------------------------------------------------------- */
786
787 static inline void stop_adc(struct es1371_state *s)
788 {
789 unsigned long flags;
790
791 spin_lock_irqsave(&s->lock, flags);
792 s->ctrl &= ~CTRL_ADC_EN;
793 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
794 spin_unlock_irqrestore(&s->lock, flags);
795 }
796
797 static inline void stop_dac1(struct es1371_state *s)
798 {
799 unsigned long flags;
800
801 spin_lock_irqsave(&s->lock, flags);
802 s->ctrl &= ~CTRL_DAC1_EN;
803 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
804 spin_unlock_irqrestore(&s->lock, flags);
805 }
806
807 static inline void stop_dac2(struct es1371_state *s)
808 {
809 unsigned long flags;
810
811 spin_lock_irqsave(&s->lock, flags);
812 s->ctrl &= ~CTRL_DAC2_EN;
813 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
814 spin_unlock_irqrestore(&s->lock, flags);
815 }
816
817 static void start_dac1(struct es1371_state *s)
818 {
819 unsigned long flags;
820 unsigned fragremain, fshift;
821
822 spin_lock_irqsave(&s->lock, flags);
823 if (!(s->ctrl & CTRL_DAC1_EN) && (s->dma_dac1.mapped || s->dma_dac1.count > 0)
824 && s->dma_dac1.ready) {
825 s->ctrl |= CTRL_DAC1_EN;
826 s->sctrl = (s->sctrl & ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD)) | SCTRL_P1INTEN;
827 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
828 fragremain = ((- s->dma_dac1.hwptr) & (s->dma_dac1.fragsize-1));
829 fshift = sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
830 if (fragremain < 2*fshift)
831 fragremain = s->dma_dac1.fragsize;
832 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
833 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
834 outl((s->dma_dac1.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
835 }
836 spin_unlock_irqrestore(&s->lock, flags);
837 }
838
839 static void start_dac2(struct es1371_state *s)
840 {
841 unsigned long flags;
842 unsigned fragremain, fshift;
843
844 spin_lock_irqsave(&s->lock, flags);
845 if (!(s->ctrl & CTRL_DAC2_EN) && (s->dma_dac2.mapped || s->dma_dac2.count > 0)
846 && s->dma_dac2.ready) {
847 s->ctrl |= CTRL_DAC2_EN;
848 s->sctrl = (s->sctrl & ~(SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN |
849 SCTRL_P2ENDINC | SCTRL_P2STINC)) | SCTRL_P2INTEN |
850 (((s->sctrl & SCTRL_P2FMT) ? 2 : 1) << SCTRL_SH_P2ENDINC) |
851 (0 << SCTRL_SH_P2STINC);
852 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
853 fragremain = ((- s->dma_dac2.hwptr) & (s->dma_dac2.fragsize-1));
854 fshift = sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
855 if (fragremain < 2*fshift)
856 fragremain = s->dma_dac2.fragsize;
857 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
858 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
859 outl((s->dma_dac2.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
860 }
861 spin_unlock_irqrestore(&s->lock, flags);
862 }
863
864 static void start_adc(struct es1371_state *s)
865 {
866 unsigned long flags;
867 unsigned fragremain, fshift;
868
869 spin_lock_irqsave(&s->lock, flags);
870 if (!(s->ctrl & CTRL_ADC_EN) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
871 && s->dma_adc.ready) {
872 s->ctrl |= CTRL_ADC_EN;
873 s->sctrl = (s->sctrl & ~SCTRL_R1LOOPSEL) | SCTRL_R1INTEN;
874 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
875 fragremain = ((- s->dma_adc.hwptr) & (s->dma_adc.fragsize-1));
876 fshift = sample_shift[(s->sctrl & SCTRL_R1FMT) >> SCTRL_SH_R1FMT];
877 if (fragremain < 2*fshift)
878 fragremain = s->dma_adc.fragsize;
879 outl((fragremain >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
880 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
881 outl((s->dma_adc.fragsize >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
882 }
883 spin_unlock_irqrestore(&s->lock, flags);
884 }
885
886 /* --------------------------------------------------------------------- */
887
888 #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
889 #define DMABUF_MINORDER 1
890
891
892 static inline void dealloc_dmabuf(struct es1371_state *s, struct dmabuf *db)
893 {
894 struct page *page, *pend;
895
896 if (db->rawbuf) {
897 /* undo marking the pages as reserved */
898 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
899 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
900 ClearPageReserved(page);
901 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
902 }
903 db->rawbuf = NULL;
904 db->mapped = db->ready = 0;
905 }
906
907 static int prog_dmabuf(struct es1371_state *s, struct dmabuf *db, unsigned rate, unsigned fmt, unsigned reg)
908 {
909 int order;
910 unsigned bytepersec;
911 unsigned bufs;
912 struct page *page, *pend;
913
914 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
915 if (!db->rawbuf) {
916 db->ready = db->mapped = 0;
917 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
918 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
919 break;
920 if (!db->rawbuf)
921 return -ENOMEM;
922 db->buforder = order;
923 /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
924 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
925 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
926 SetPageReserved(page);
927 }
928 fmt &= ES1371_FMT_MASK;
929 bytepersec = rate << sample_shift[fmt];
930 bufs = PAGE_SIZE << db->buforder;
931 if (db->ossfragshift) {
932 if ((1000 << db->ossfragshift) < bytepersec)
933 db->fragshift = ld2(bytepersec/1000);
934 else
935 db->fragshift = db->ossfragshift;
936 } else {
937 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
938 if (db->fragshift < 3)
939 db->fragshift = 3;
940 }
941 db->numfrag = bufs >> db->fragshift;
942 while (db->numfrag < 4 && db->fragshift > 3) {
943 db->fragshift--;
944 db->numfrag = bufs >> db->fragshift;
945 }
946 db->fragsize = 1 << db->fragshift;
947 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
948 db->numfrag = db->ossmaxfrags;
949 db->fragsamples = db->fragsize >> sample_shift[fmt];
950 db->dmasize = db->numfrag << db->fragshift;
951 memset(db->rawbuf, (fmt & ES1371_FMT_S16) ? 0 : 0x80, db->dmasize);
952 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
953 outl(db->dmaaddr, s->io+(reg & 0xff));
954 outl((db->dmasize >> 2)-1, s->io+((reg + 4) & 0xff));
955 db->enabled = 1;
956 db->ready = 1;
957 return 0;
958 }
959
960 static inline int prog_dmabuf_adc(struct es1371_state *s)
961 {
962 stop_adc(s);
963 return prog_dmabuf(s, &s->dma_adc, s->adcrate, (s->sctrl >> SCTRL_SH_R1FMT) & ES1371_FMT_MASK,
964 ES1371_REG_ADC_FRAMEADR);
965 }
966
967 static inline int prog_dmabuf_dac2(struct es1371_state *s)
968 {
969 stop_dac2(s);
970 return prog_dmabuf(s, &s->dma_dac2, s->dac2rate, (s->sctrl >> SCTRL_SH_P2FMT) & ES1371_FMT_MASK,
971 ES1371_REG_DAC2_FRAMEADR);
972 }
973
974 static inline int prog_dmabuf_dac1(struct es1371_state *s)
975 {
976 stop_dac1(s);
977 return prog_dmabuf(s, &s->dma_dac1, s->dac1rate, (s->sctrl >> SCTRL_SH_P1FMT) & ES1371_FMT_MASK,
978 ES1371_REG_DAC1_FRAMEADR);
979 }
980
981 static inline unsigned get_hwptr(struct es1371_state *s, struct dmabuf *db, unsigned reg)
982 {
983 unsigned hwptr, diff;
984
985 outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
986 hwptr = (inl(s->io+(reg & 0xff)) >> 14) & 0x3fffc;
987 diff = (db->dmasize + hwptr - db->hwptr) % db->dmasize;
988 db->hwptr = hwptr;
989 return diff;
990 }
991
992 static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
993 {
994 if (bptr + len > bsize) {
995 unsigned x = bsize - bptr;
996 memset(((char *)buf) + bptr, c, x);
997 bptr = 0;
998 len -= x;
999 }
1000 memset(((char *)buf) + bptr, c, len);
1001 }
1002
1003 /* call with spinlock held! */
1004 static void es1371_update_ptr(struct es1371_state *s)
1005 {
1006 int diff;
1007
1008 /* update ADC pointer */
1009 if (s->ctrl & CTRL_ADC_EN) {
1010 diff = get_hwptr(s, &s->dma_adc, ES1371_REG_ADC_FRAMECNT);
1011 s->dma_adc.total_bytes += diff;
1012 s->dma_adc.count += diff;
1013 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1014 wake_up(&s->dma_adc.wait);
1015 if (!s->dma_adc.mapped) {
1016 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1017 s->ctrl &= ~CTRL_ADC_EN;
1018 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1019 s->dma_adc.error++;
1020 }
1021 }
1022 }
1023 /* update DAC1 pointer */
1024 if (s->ctrl & CTRL_DAC1_EN) {
1025 diff = get_hwptr(s, &s->dma_dac1, ES1371_REG_DAC1_FRAMECNT);
1026 s->dma_dac1.total_bytes += diff;
1027 if (s->dma_dac1.mapped) {
1028 s->dma_dac1.count += diff;
1029 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
1030 wake_up(&s->dma_dac1.wait);
1031 } else {
1032 s->dma_dac1.count -= diff;
1033 if (s->dma_dac1.count <= 0) {
1034 s->ctrl &= ~CTRL_DAC1_EN;
1035 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1036 s->dma_dac1.error++;
1037 } else if (s->dma_dac1.count <= (signed)s->dma_dac1.fragsize && !s->dma_dac1.endcleared) {
1038 clear_advance(s->dma_dac1.rawbuf, s->dma_dac1.dmasize, s->dma_dac1.swptr,
1039 s->dma_dac1.fragsize, (s->sctrl & SCTRL_P1SEB) ? 0 : 0x80);
1040 s->dma_dac1.endcleared = 1;
1041 }
1042 if (s->dma_dac1.count + (signed)s->dma_dac1.fragsize <= (signed)s->dma_dac1.dmasize)
1043 wake_up(&s->dma_dac1.wait);
1044 }
1045 }
1046 /* update DAC2 pointer */
1047 if (s->ctrl & CTRL_DAC2_EN) {
1048 diff = get_hwptr(s, &s->dma_dac2, ES1371_REG_DAC2_FRAMECNT);
1049 s->dma_dac2.total_bytes += diff;
1050 if (s->dma_dac2.mapped) {
1051 s->dma_dac2.count += diff;
1052 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1053 wake_up(&s->dma_dac2.wait);
1054 } else {
1055 s->dma_dac2.count -= diff;
1056 if (s->dma_dac2.count <= 0) {
1057 s->ctrl &= ~CTRL_DAC2_EN;
1058 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
1059 s->dma_dac2.error++;
1060 } else if (s->dma_dac2.count <= (signed)s->dma_dac2.fragsize && !s->dma_dac2.endcleared) {
1061 clear_advance(s->dma_dac2.rawbuf, s->dma_dac2.dmasize, s->dma_dac2.swptr,
1062 s->dma_dac2.fragsize, (s->sctrl & SCTRL_P2SEB) ? 0 : 0x80);
1063 s->dma_dac2.endcleared = 1;
1064 }
1065 if (s->dma_dac2.count + (signed)s->dma_dac2.fragsize <= (signed)s->dma_dac2.dmasize)
1066 wake_up(&s->dma_dac2.wait);
1067 }
1068 }
1069 }
1070
1071 /* hold spinlock for the following! */
1072 static void es1371_handle_midi(struct es1371_state *s)
1073 {
1074 unsigned char ch;
1075 int wake;
1076
1077 if (!(s->ctrl & CTRL_UART_EN))
1078 return;
1079 wake = 0;
1080 while (inb(s->io+ES1371_REG_UART_STATUS) & USTAT_RXRDY) {
1081 ch = inb(s->io+ES1371_REG_UART_DATA);
1082 if (s->midi.icnt < MIDIINBUF) {
1083 s->midi.ibuf[s->midi.iwr] = ch;
1084 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
1085 s->midi.icnt++;
1086 }
1087 wake = 1;
1088 }
1089 if (wake)
1090 wake_up(&s->midi.iwait);
1091 wake = 0;
1092 while ((inb(s->io+ES1371_REG_UART_STATUS) & USTAT_TXRDY) && s->midi.ocnt > 0) {
1093 outb(s->midi.obuf[s->midi.ord], s->io+ES1371_REG_UART_DATA);
1094 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
1095 s->midi.ocnt--;
1096 if (s->midi.ocnt < MIDIOUTBUF-16)
1097 wake = 1;
1098 }
1099 if (wake)
1100 wake_up(&s->midi.owait);
1101 outb((s->midi.ocnt > 0) ? UCTRL_RXINTEN | UCTRL_ENA_TXINT : UCTRL_RXINTEN, s->io+ES1371_REG_UART_CONTROL);
1102 }
1103
1104 static irqreturn_t es1371_interrupt(int irq, void *dev_id)
1105 {
1106 struct es1371_state *s = dev_id;
1107 unsigned int intsrc, sctl;
1108
1109 /* fastpath out, to ease interrupt sharing */
1110 intsrc = inl(s->io+ES1371_REG_STATUS);
1111 if (!(intsrc & 0x80000000))
1112 return IRQ_NONE;
1113 spin_lock(&s->lock);
1114 /* clear audio interrupts first */
1115 sctl = s->sctrl;
1116 if (intsrc & STAT_ADC)
1117 sctl &= ~SCTRL_R1INTEN;
1118 if (intsrc & STAT_DAC1)
1119 sctl &= ~SCTRL_P1INTEN;
1120 if (intsrc & STAT_DAC2)
1121 sctl &= ~SCTRL_P2INTEN;
1122 outl(sctl, s->io+ES1371_REG_SERIAL_CONTROL);
1123 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1124 es1371_update_ptr(s);
1125 es1371_handle_midi(s);
1126 spin_unlock(&s->lock);
1127 return IRQ_HANDLED;
1128 }
1129
1130 /* --------------------------------------------------------------------- */
1131
1132 static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value\n";
1133
1134 #define VALIDATE_STATE(s) \
1135 ({ \
1136 if (!(s) || (s)->magic != ES1371_MAGIC) { \
1137 printk(invalid_magic); \
1138 return -ENXIO; \
1139 } \
1140 })
1141
1142 /* --------------------------------------------------------------------- */
1143
1144 /* Conversion table for S/PDIF PCM volume emulation through the SRC */
1145 /* dB-linear table of DAC vol values; -0dB to -46.5dB with mute */
1146 static const unsigned short DACVolTable[101] =
1147 {
1148 0x1000, 0x0f2a, 0x0e60, 0x0da0, 0x0cea, 0x0c3e, 0x0b9a, 0x0aff,
1149 0x0a6d, 0x09e1, 0x095e, 0x08e1, 0x086a, 0x07fa, 0x078f, 0x072a,
1150 0x06cb, 0x0670, 0x061a, 0x05c9, 0x057b, 0x0532, 0x04ed, 0x04ab,
1151 0x046d, 0x0432, 0x03fa, 0x03c5, 0x0392, 0x0363, 0x0335, 0x030b,
1152 0x02e2, 0x02bc, 0x0297, 0x0275, 0x0254, 0x0235, 0x0217, 0x01fb,
1153 0x01e1, 0x01c8, 0x01b0, 0x0199, 0x0184, 0x0170, 0x015d, 0x014b,
1154 0x0139, 0x0129, 0x0119, 0x010b, 0x00fd, 0x00f0, 0x00e3, 0x00d7,
1155 0x00cc, 0x00c1, 0x00b7, 0x00ae, 0x00a5, 0x009c, 0x0094, 0x008c,
1156 0x0085, 0x007e, 0x0077, 0x0071, 0x006b, 0x0066, 0x0060, 0x005b,
1157 0x0057, 0x0052, 0x004e, 0x004a, 0x0046, 0x0042, 0x003f, 0x003c,
1158 0x0038, 0x0036, 0x0033, 0x0030, 0x002e, 0x002b, 0x0029, 0x0027,
1159 0x0025, 0x0023, 0x0021, 0x001f, 0x001e, 0x001c, 0x001b, 0x0019,
1160 0x0018, 0x0017, 0x0016, 0x0014, 0x0000
1161 };
1162
1163 /*
1164 * when we are in S/PDIF mode, we want to disable any analog output so
1165 * we filter the mixer ioctls
1166 */
1167 static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd, unsigned long arg)
1168 {
1169 struct es1371_state *s = (struct es1371_state *)codec->private_data;
1170 int val;
1171 unsigned long flags;
1172 unsigned int left, right;
1173
1174 VALIDATE_STATE(s);
1175 /* filter mixer ioctls to catch PCM and MASTER volume when in S/PDIF mode */
1176 if (s->spdif_volume == -1)
1177 return codec->mixer_ioctl(codec, cmd, arg);
1178 switch (cmd) {
1179 case SOUND_MIXER_WRITE_VOLUME:
1180 return 0;
1181
1182 case SOUND_MIXER_WRITE_PCM: /* use SRC for PCM volume */
1183 if (get_user(val, (int __user *)arg))
1184 return -EFAULT;
1185 right = ((val >> 8) & 0xff);
1186 left = (val & 0xff);
1187 if (right > 100)
1188 right = 100;
1189 if (left > 100)
1190 left = 100;
1191 s->spdif_volume = (right << 8) | left;
1192 spin_lock_irqsave(&s->lock, flags);
1193 src_write(s, SRCREG_VOL_DAC2, DACVolTable[100 - left]);
1194 src_write(s, SRCREG_VOL_DAC2+1, DACVolTable[100 - right]);
1195 spin_unlock_irqrestore(&s->lock, flags);
1196 return 0;
1197
1198 case SOUND_MIXER_READ_PCM:
1199 return put_user(s->spdif_volume, (int __user *)arg);
1200 }
1201 return codec->mixer_ioctl(codec, cmd, arg);
1202 }
1203
1204 /* --------------------------------------------------------------------- */
1205
1206 /*
1207 * AC97 Mixer Register to Connections mapping of the Concert 97 board
1208 *
1209 * AC97_MASTER_VOL_STEREO Line Out
1210 * AC97_MASTER_VOL_MONO TAD Output
1211 * AC97_PCBEEP_VOL none
1212 * AC97_PHONE_VOL TAD Input (mono)
1213 * AC97_MIC_VOL MIC Input (mono)
1214 * AC97_LINEIN_VOL Line Input (stereo)
1215 * AC97_CD_VOL CD Input (stereo)
1216 * AC97_VIDEO_VOL none
1217 * AC97_AUX_VOL Aux Input (stereo)
1218 * AC97_PCMOUT_VOL Wave Output (stereo)
1219 */
1220
1221 static int es1371_open_mixdev(struct inode *inode, struct file *file)
1222 {
1223 int minor = iminor(inode);
1224 struct list_head *list;
1225 struct es1371_state *s;
1226
1227 for (list = devs.next; ; list = list->next) {
1228 if (list == &devs)
1229 return -ENODEV;
1230 s = list_entry(list, struct es1371_state, devs);
1231 if (s->codec->dev_mixer == minor)
1232 break;
1233 }
1234 VALIDATE_STATE(s);
1235 file->private_data = s;
1236 return nonseekable_open(inode, file);
1237 }
1238
1239 static int es1371_release_mixdev(struct inode *inode, struct file *file)
1240 {
1241 struct es1371_state *s = (struct es1371_state *)file->private_data;
1242
1243 VALIDATE_STATE(s);
1244 return 0;
1245 }
1246
1247 static int es1371_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1248 {
1249 struct es1371_state *s = (struct es1371_state *)file->private_data;
1250 struct ac97_codec *codec = s->codec;
1251
1252 return mixdev_ioctl(codec, cmd, arg);
1253 }
1254
1255 static /*const*/ struct file_operations es1371_mixer_fops = {
1256 .owner = THIS_MODULE,
1257 .llseek = no_llseek,
1258 .ioctl = es1371_ioctl_mixdev,
1259 .open = es1371_open_mixdev,
1260 .release = es1371_release_mixdev,
1261 };
1262
1263 /* --------------------------------------------------------------------- */
1264
1265 static int drain_dac1(struct es1371_state *s, int nonblock)
1266 {
1267 DECLARE_WAITQUEUE(wait, current);
1268 unsigned long flags;
1269 int count, tmo;
1270
1271 if (s->dma_dac1.mapped || !s->dma_dac1.ready)
1272 return 0;
1273 add_wait_queue(&s->dma_dac1.wait, &wait);
1274 for (;;) {
1275 __set_current_state(TASK_INTERRUPTIBLE);
1276 spin_lock_irqsave(&s->lock, flags);
1277 count = s->dma_dac1.count;
1278 spin_unlock_irqrestore(&s->lock, flags);
1279 if (count <= 0)
1280 break;
1281 if (signal_pending(current))
1282 break;
1283 if (nonblock) {
1284 remove_wait_queue(&s->dma_dac1.wait, &wait);
1285 set_current_state(TASK_RUNNING);
1286 return -EBUSY;
1287 }
1288 tmo = 3 * HZ * (count + s->dma_dac1.fragsize) / 2 / s->dac1rate;
1289 tmo >>= sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
1290 if (!schedule_timeout(tmo + 1))
1291 DBG(printk(KERN_DEBUG PFX "dac1 dma timed out??\n");)
1292 }
1293 remove_wait_queue(&s->dma_dac1.wait, &wait);
1294 set_current_state(TASK_RUNNING);
1295 if (signal_pending(current))
1296 return -ERESTARTSYS;
1297 return 0;
1298 }
1299
1300 static int drain_dac2(struct es1371_state *s, int nonblock)
1301 {
1302 DECLARE_WAITQUEUE(wait, current);
1303 unsigned long flags;
1304 int count, tmo;
1305
1306 if (s->dma_dac2.mapped || !s->dma_dac2.ready)
1307 return 0;
1308 add_wait_queue(&s->dma_dac2.wait, &wait);
1309 for (;;) {
1310 __set_current_state(TASK_UNINTERRUPTIBLE);
1311 spin_lock_irqsave(&s->lock, flags);
1312 count = s->dma_dac2.count;
1313 spin_unlock_irqrestore(&s->lock, flags);
1314 if (count <= 0)
1315 break;
1316 if (signal_pending(current))
1317 break;
1318 if (nonblock) {
1319 remove_wait_queue(&s->dma_dac2.wait, &wait);
1320 set_current_state(TASK_RUNNING);
1321 return -EBUSY;
1322 }
1323 tmo = 3 * HZ * (count + s->dma_dac2.fragsize) / 2 / s->dac2rate;
1324 tmo >>= sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
1325 if (!schedule_timeout(tmo + 1))
1326 DBG(printk(KERN_DEBUG PFX "dac2 dma timed out??\n");)
1327 }
1328 remove_wait_queue(&s->dma_dac2.wait, &wait);
1329 set_current_state(TASK_RUNNING);
1330 if (signal_pending(current))
1331 return -ERESTARTSYS;
1332 return 0;
1333 }
1334
1335 /* --------------------------------------------------------------------- */
1336
1337 static ssize_t es1371_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1338 {
1339 struct es1371_state *s = (struct es1371_state *)file->private_data;
1340 DECLARE_WAITQUEUE(wait, current);
1341 ssize_t ret = 0;
1342 unsigned long flags;
1343 unsigned swptr;
1344 int cnt;
1345
1346 VALIDATE_STATE(s);
1347 if (s->dma_adc.mapped)
1348 return -ENXIO;
1349 if (!access_ok(VERIFY_WRITE, buffer, count))
1350 return -EFAULT;
1351 mutex_lock(&s->sem);
1352 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1353 goto out2;
1354
1355 add_wait_queue(&s->dma_adc.wait, &wait);
1356 while (count > 0) {
1357 spin_lock_irqsave(&s->lock, flags);
1358 swptr = s->dma_adc.swptr;
1359 cnt = s->dma_adc.dmasize-swptr;
1360 if (s->dma_adc.count < cnt)
1361 cnt = s->dma_adc.count;
1362 if (cnt <= 0)
1363 __set_current_state(TASK_INTERRUPTIBLE);
1364 spin_unlock_irqrestore(&s->lock, flags);
1365 if (cnt > count)
1366 cnt = count;
1367 if (cnt <= 0) {
1368 if (s->dma_adc.enabled)
1369 start_adc(s);
1370 if (file->f_flags & O_NONBLOCK) {
1371 if (!ret)
1372 ret = -EAGAIN;
1373 goto out;
1374 }
1375 mutex_unlock(&s->sem);
1376 schedule();
1377 if (signal_pending(current)) {
1378 if (!ret)
1379 ret = -ERESTARTSYS;
1380 goto out2;
1381 }
1382 mutex_lock(&s->sem);
1383 if (s->dma_adc.mapped)
1384 {
1385 ret = -ENXIO;
1386 goto out;
1387 }
1388 continue;
1389 }
1390 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1391 if (!ret)
1392 ret = -EFAULT;
1393 goto out;
1394 }
1395 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1396 spin_lock_irqsave(&s->lock, flags);
1397 s->dma_adc.swptr = swptr;
1398 s->dma_adc.count -= cnt;
1399 spin_unlock_irqrestore(&s->lock, flags);
1400 count -= cnt;
1401 buffer += cnt;
1402 ret += cnt;
1403 if (s->dma_adc.enabled)
1404 start_adc(s);
1405 }
1406 out:
1407 mutex_unlock(&s->sem);
1408 out2:
1409 remove_wait_queue(&s->dma_adc.wait, &wait);
1410 set_current_state(TASK_RUNNING);
1411 return ret;
1412 }
1413
1414 static ssize_t es1371_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1415 {
1416 struct es1371_state *s = (struct es1371_state *)file->private_data;
1417 DECLARE_WAITQUEUE(wait, current);
1418 ssize_t ret;
1419 unsigned long flags;
1420 unsigned swptr;
1421 int cnt;
1422
1423 VALIDATE_STATE(s);
1424 if (s->dma_dac2.mapped)
1425 return -ENXIO;
1426 if (!access_ok(VERIFY_READ, buffer, count))
1427 return -EFAULT;
1428 mutex_lock(&s->sem);
1429 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1430 goto out3;
1431 ret = 0;
1432 add_wait_queue(&s->dma_dac2.wait, &wait);
1433 while (count > 0) {
1434 spin_lock_irqsave(&s->lock, flags);
1435 if (s->dma_dac2.count < 0) {
1436 s->dma_dac2.count = 0;
1437 s->dma_dac2.swptr = s->dma_dac2.hwptr;
1438 }
1439 swptr = s->dma_dac2.swptr;
1440 cnt = s->dma_dac2.dmasize-swptr;
1441 if (s->dma_dac2.count + cnt > s->dma_dac2.dmasize)
1442 cnt = s->dma_dac2.dmasize - s->dma_dac2.count;
1443 if (cnt <= 0)
1444 __set_current_state(TASK_INTERRUPTIBLE);
1445 spin_unlock_irqrestore(&s->lock, flags);
1446 if (cnt > count)
1447 cnt = count;
1448 if (cnt <= 0) {
1449 if (s->dma_dac2.enabled)
1450 start_dac2(s);
1451 if (file->f_flags & O_NONBLOCK) {
1452 if (!ret)
1453 ret = -EAGAIN;
1454 goto out;
1455 }
1456 mutex_unlock(&s->sem);
1457 schedule();
1458 if (signal_pending(current)) {
1459 if (!ret)
1460 ret = -ERESTARTSYS;
1461 goto out2;
1462 }
1463 mutex_lock(&s->sem);
1464 if (s->dma_dac2.mapped)
1465 {
1466 ret = -ENXIO;
1467 goto out;
1468 }
1469 continue;
1470 }
1471 if (copy_from_user(s->dma_dac2.rawbuf + swptr, buffer, cnt)) {
1472 if (!ret)
1473 ret = -EFAULT;
1474 goto out;
1475 }
1476 swptr = (swptr + cnt) % s->dma_dac2.dmasize;
1477 spin_lock_irqsave(&s->lock, flags);
1478 s->dma_dac2.swptr = swptr;
1479 s->dma_dac2.count += cnt;
1480 s->dma_dac2.endcleared = 0;
1481 spin_unlock_irqrestore(&s->lock, flags);
1482 count -= cnt;
1483 buffer += cnt;
1484 ret += cnt;
1485 if (s->dma_dac2.enabled)
1486 start_dac2(s);
1487 }
1488 out:
1489 mutex_unlock(&s->sem);
1490 out2:
1491 remove_wait_queue(&s->dma_dac2.wait, &wait);
1492 out3:
1493 set_current_state(TASK_RUNNING);
1494 return ret;
1495 }
1496
1497 /* No kernel lock - we have our own spinlock */
1498 static unsigned int es1371_poll(struct file *file, struct poll_table_struct *wait)
1499 {
1500 struct es1371_state *s = (struct es1371_state *)file->private_data;
1501 unsigned long flags;
1502 unsigned int mask = 0;
1503
1504 VALIDATE_STATE(s);
1505 if (file->f_mode & FMODE_WRITE) {
1506 if (!s->dma_dac2.ready && prog_dmabuf_dac2(s))
1507 return 0;
1508 poll_wait(file, &s->dma_dac2.wait, wait);
1509 }
1510 if (file->f_mode & FMODE_READ) {
1511 if (!s->dma_adc.ready && prog_dmabuf_adc(s))
1512 return 0;
1513 poll_wait(file, &s->dma_adc.wait, wait);
1514 }
1515 spin_lock_irqsave(&s->lock, flags);
1516 es1371_update_ptr(s);
1517 if (file->f_mode & FMODE_READ) {
1518 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1519 mask |= POLLIN | POLLRDNORM;
1520 }
1521 if (file->f_mode & FMODE_WRITE) {
1522 if (s->dma_dac2.mapped) {
1523 if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
1524 mask |= POLLOUT | POLLWRNORM;
1525 } else {
1526 if ((signed)s->dma_dac2.dmasize >= s->dma_dac2.count + (signed)s->dma_dac2.fragsize)
1527 mask |= POLLOUT | POLLWRNORM;
1528 }
1529 }
1530 spin_unlock_irqrestore(&s->lock, flags);
1531 return mask;
1532 }
1533
1534 static int es1371_mmap(struct file *file, struct vm_area_struct *vma)
1535 {
1536 struct es1371_state *s = (struct es1371_state *)file->private_data;
1537 struct dmabuf *db;
1538 int ret = 0;
1539 unsigned long size;
1540
1541 VALIDATE_STATE(s);
1542 lock_kernel();
1543 mutex_lock(&s->sem);
1544
1545 if (vma->vm_flags & VM_WRITE) {
1546 if ((ret = prog_dmabuf_dac2(s)) != 0) {
1547 goto out;
1548 }
1549 db = &s->dma_dac2;
1550 } else if (vma->vm_flags & VM_READ) {
1551 if ((ret = prog_dmabuf_adc(s)) != 0) {
1552 goto out;
1553 }
1554 db = &s->dma_adc;
1555 } else {
1556 ret = -EINVAL;
1557 goto out;
1558 }
1559 if (vma->vm_pgoff != 0) {
1560 ret = -EINVAL;
1561 goto out;
1562 }
1563 size = vma->vm_end - vma->vm_start;
1564 if (size > (PAGE_SIZE << db->buforder)) {
1565 ret = -EINVAL;
1566 goto out;
1567 }
1568 if (remap_pfn_range(vma, vma->vm_start,
1569 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
1570 size, vma->vm_page_prot)) {
1571 ret = -EAGAIN;
1572 goto out;
1573 }
1574 db->mapped = 1;
1575 out:
1576 mutex_unlock(&s->sem);
1577 unlock_kernel();
1578 return ret;
1579 }
1580
1581 static int es1371_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1582 {
1583 struct es1371_state *s = (struct es1371_state *)file->private_data;
1584 unsigned long flags;
1585 audio_buf_info abinfo;
1586 count_info cinfo;
1587 int count;
1588 int val, mapped, ret;
1589 void __user *argp = (void __user *)arg;
1590 int __user *p = argp;
1591
1592 VALIDATE_STATE(s);
1593 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac2.mapped) ||
1594 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1595 switch (cmd) {
1596 case OSS_GETVERSION:
1597 return put_user(SOUND_VERSION, p);
1598
1599 case SNDCTL_DSP_SYNC:
1600 if (file->f_mode & FMODE_WRITE)
1601 return drain_dac2(s, 0/*file->f_flags & O_NONBLOCK*/);
1602 return 0;
1603
1604 case SNDCTL_DSP_SETDUPLEX:
1605 return 0;
1606
1607 case SNDCTL_DSP_GETCAPS:
1608 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
1609
1610 case SNDCTL_DSP_RESET:
1611 if (file->f_mode & FMODE_WRITE) {
1612 stop_dac2(s);
1613 synchronize_irq(s->irq);
1614 s->dma_dac2.swptr = s->dma_dac2.hwptr = s->dma_dac2.count = s->dma_dac2.total_bytes = 0;
1615 }
1616 if (file->f_mode & FMODE_READ) {
1617 stop_adc(s);
1618 synchronize_irq(s->irq);
1619 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1620 }
1621 return 0;
1622
1623 case SNDCTL_DSP_SPEED:
1624 if (get_user(val, p))
1625 return -EFAULT;
1626 if (val >= 0) {
1627 if (file->f_mode & FMODE_READ) {
1628 stop_adc(s);
1629 s->dma_adc.ready = 0;
1630 set_adc_rate(s, val);
1631 }
1632 if (file->f_mode & FMODE_WRITE) {
1633 stop_dac2(s);
1634 s->dma_dac2.ready = 0;
1635 set_dac2_rate(s, val);
1636 }
1637 }
1638 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p);
1639
1640 case SNDCTL_DSP_STEREO:
1641 if (get_user(val, p))
1642 return -EFAULT;
1643 if (file->f_mode & FMODE_READ) {
1644 stop_adc(s);
1645 s->dma_adc.ready = 0;
1646 spin_lock_irqsave(&s->lock, flags);
1647 if (val)
1648 s->sctrl |= SCTRL_R1SMB;
1649 else
1650 s->sctrl &= ~SCTRL_R1SMB;
1651 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1652 spin_unlock_irqrestore(&s->lock, flags);
1653 }
1654 if (file->f_mode & FMODE_WRITE) {
1655 stop_dac2(s);
1656 s->dma_dac2.ready = 0;
1657 spin_lock_irqsave(&s->lock, flags);
1658 if (val)
1659 s->sctrl |= SCTRL_P2SMB;
1660 else
1661 s->sctrl &= ~SCTRL_P2SMB;
1662 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1663 spin_unlock_irqrestore(&s->lock, flags);
1664 }
1665 return 0;
1666
1667 case SNDCTL_DSP_CHANNELS:
1668 if (get_user(val, p))
1669 return -EFAULT;
1670 if (val != 0) {
1671 if (file->f_mode & FMODE_READ) {
1672 stop_adc(s);
1673 s->dma_adc.ready = 0;
1674 spin_lock_irqsave(&s->lock, flags);
1675 if (val >= 2)
1676 s->sctrl |= SCTRL_R1SMB;
1677 else
1678 s->sctrl &= ~SCTRL_R1SMB;
1679 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1680 spin_unlock_irqrestore(&s->lock, flags);
1681 }
1682 if (file->f_mode & FMODE_WRITE) {
1683 stop_dac2(s);
1684 s->dma_dac2.ready = 0;
1685 spin_lock_irqsave(&s->lock, flags);
1686 if (val >= 2)
1687 s->sctrl |= SCTRL_P2SMB;
1688 else
1689 s->sctrl &= ~SCTRL_P2SMB;
1690 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1691 spin_unlock_irqrestore(&s->lock, flags);
1692 }
1693 }
1694 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p);
1695
1696 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1697 return put_user(AFMT_S16_LE|AFMT_U8, p);
1698
1699 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1700 if (get_user(val, p))
1701 return -EFAULT;
1702 if (val != AFMT_QUERY) {
1703 if (file->f_mode & FMODE_READ) {
1704 stop_adc(s);
1705 s->dma_adc.ready = 0;
1706 spin_lock_irqsave(&s->lock, flags);
1707 if (val == AFMT_S16_LE)
1708 s->sctrl |= SCTRL_R1SEB;
1709 else
1710 s->sctrl &= ~SCTRL_R1SEB;
1711 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1712 spin_unlock_irqrestore(&s->lock, flags);
1713 }
1714 if (file->f_mode & FMODE_WRITE) {
1715 stop_dac2(s);
1716 s->dma_dac2.ready = 0;
1717 spin_lock_irqsave(&s->lock, flags);
1718 if (val == AFMT_S16_LE)
1719 s->sctrl |= SCTRL_P2SEB;
1720 else
1721 s->sctrl &= ~SCTRL_P2SEB;
1722 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1723 spin_unlock_irqrestore(&s->lock, flags);
1724 }
1725 }
1726 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ?
1727 AFMT_S16_LE : AFMT_U8, p);
1728
1729 case SNDCTL_DSP_POST:
1730 return 0;
1731
1732 case SNDCTL_DSP_GETTRIGGER:
1733 val = 0;
1734 if (file->f_mode & FMODE_READ && s->ctrl & CTRL_ADC_EN)
1735 val |= PCM_ENABLE_INPUT;
1736 if (file->f_mode & FMODE_WRITE && s->ctrl & CTRL_DAC2_EN)
1737 val |= PCM_ENABLE_OUTPUT;
1738 return put_user(val, p);
1739
1740 case SNDCTL_DSP_SETTRIGGER:
1741 if (get_user(val, p))
1742 return -EFAULT;
1743 if (file->f_mode & FMODE_READ) {
1744 if (val & PCM_ENABLE_INPUT) {
1745 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1746 return ret;
1747 s->dma_adc.enabled = 1;
1748 start_adc(s);
1749 } else {
1750 s->dma_adc.enabled = 0;
1751 stop_adc(s);
1752 }
1753 }
1754 if (file->f_mode & FMODE_WRITE) {
1755 if (val & PCM_ENABLE_OUTPUT) {
1756 if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
1757 return ret;
1758 s->dma_dac2.enabled = 1;
1759 start_dac2(s);
1760 } else {
1761 s->dma_dac2.enabled = 0;
1762 stop_dac2(s);
1763 }
1764 }
1765 return 0;
1766
1767 case SNDCTL_DSP_GETOSPACE:
1768 if (!(file->f_mode & FMODE_WRITE))
1769 return -EINVAL;
1770 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1771 return val;
1772 spin_lock_irqsave(&s->lock, flags);
1773 es1371_update_ptr(s);
1774 abinfo.fragsize = s->dma_dac2.fragsize;
1775 count = s->dma_dac2.count;
1776 if (count < 0)
1777 count = 0;
1778 abinfo.bytes = s->dma_dac2.dmasize - count;
1779 abinfo.fragstotal = s->dma_dac2.numfrag;
1780 abinfo.fragments = abinfo.bytes >> s->dma_dac2.fragshift;
1781 spin_unlock_irqrestore(&s->lock, flags);
1782 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1783
1784 case SNDCTL_DSP_GETISPACE:
1785 if (!(file->f_mode & FMODE_READ))
1786 return -EINVAL;
1787 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1788 return val;
1789 spin_lock_irqsave(&s->lock, flags);
1790 es1371_update_ptr(s);
1791 abinfo.fragsize = s->dma_adc.fragsize;
1792 count = s->dma_adc.count;
1793 if (count < 0)
1794 count = 0;
1795 abinfo.bytes = count;
1796 abinfo.fragstotal = s->dma_adc.numfrag;
1797 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1798 spin_unlock_irqrestore(&s->lock, flags);
1799 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1800
1801 case SNDCTL_DSP_NONBLOCK:
1802 file->f_flags |= O_NONBLOCK;
1803 return 0;
1804
1805 case SNDCTL_DSP_GETODELAY:
1806 if (!(file->f_mode & FMODE_WRITE))
1807 return -EINVAL;
1808 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1809 return val;
1810 spin_lock_irqsave(&s->lock, flags);
1811 es1371_update_ptr(s);
1812 count = s->dma_dac2.count;
1813 spin_unlock_irqrestore(&s->lock, flags);
1814 if (count < 0)
1815 count = 0;
1816 return put_user(count, p);
1817
1818 case SNDCTL_DSP_GETIPTR:
1819 if (!(file->f_mode & FMODE_READ))
1820 return -EINVAL;
1821 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
1822 return val;
1823 spin_lock_irqsave(&s->lock, flags);
1824 es1371_update_ptr(s);
1825 cinfo.bytes = s->dma_adc.total_bytes;
1826 count = s->dma_adc.count;
1827 if (count < 0)
1828 count = 0;
1829 cinfo.blocks = count >> s->dma_adc.fragshift;
1830 cinfo.ptr = s->dma_adc.hwptr;
1831 if (s->dma_adc.mapped)
1832 s->dma_adc.count &= s->dma_adc.fragsize-1;
1833 spin_unlock_irqrestore(&s->lock, flags);
1834 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1835 return -EFAULT;
1836 return 0;
1837
1838 case SNDCTL_DSP_GETOPTR:
1839 if (!(file->f_mode & FMODE_WRITE))
1840 return -EINVAL;
1841 if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
1842 return val;
1843 spin_lock_irqsave(&s->lock, flags);
1844 es1371_update_ptr(s);
1845 cinfo.bytes = s->dma_dac2.total_bytes;
1846 count = s->dma_dac2.count;
1847 if (count < 0)
1848 count = 0;
1849 cinfo.blocks = count >> s->dma_dac2.fragshift;
1850 cinfo.ptr = s->dma_dac2.hwptr;
1851 if (s->dma_dac2.mapped)
1852 s->dma_dac2.count &= s->dma_dac2.fragsize-1;
1853 spin_unlock_irqrestore(&s->lock, flags);
1854 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1855 return -EFAULT;
1856 return 0;
1857
1858 case SNDCTL_DSP_GETBLKSIZE:
1859 if (file->f_mode & FMODE_WRITE) {
1860 if ((val = prog_dmabuf_dac2(s)))
1861 return val;
1862 return put_user(s->dma_dac2.fragsize, p);
1863 }
1864 if ((val = prog_dmabuf_adc(s)))
1865 return val;
1866 return put_user(s->dma_adc.fragsize, p);
1867
1868 case SNDCTL_DSP_SETFRAGMENT:
1869 if (get_user(val, p))
1870 return -EFAULT;
1871 if (file->f_mode & FMODE_READ) {
1872 s->dma_adc.ossfragshift = val & 0xffff;
1873 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1874 if (s->dma_adc.ossfragshift < 4)
1875 s->dma_adc.ossfragshift = 4;
1876 if (s->dma_adc.ossfragshift > 15)
1877 s->dma_adc.ossfragshift = 15;
1878 if (s->dma_adc.ossmaxfrags < 4)
1879 s->dma_adc.ossmaxfrags = 4;
1880 }
1881 if (file->f_mode & FMODE_WRITE) {
1882 s->dma_dac2.ossfragshift = val & 0xffff;
1883 s->dma_dac2.ossmaxfrags = (val >> 16) & 0xffff;
1884 if (s->dma_dac2.ossfragshift < 4)
1885 s->dma_dac2.ossfragshift = 4;
1886 if (s->dma_dac2.ossfragshift > 15)
1887 s->dma_dac2.ossfragshift = 15;
1888 if (s->dma_dac2.ossmaxfrags < 4)
1889 s->dma_dac2.ossmaxfrags = 4;
1890 }
1891 return 0;
1892
1893 case SNDCTL_DSP_SUBDIVIDE:
1894 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1895 (file->f_mode & FMODE_WRITE && s->dma_dac2.subdivision))
1896 return -EINVAL;
1897 if (get_user(val, p))
1898 return -EFAULT;
1899 if (val != 1 && val != 2 && val != 4)
1900 return -EINVAL;
1901 if (file->f_mode & FMODE_READ)
1902 s->dma_adc.subdivision = val;
1903 if (file->f_mode & FMODE_WRITE)
1904 s->dma_dac2.subdivision = val;
1905 return 0;
1906
1907 case SOUND_PCM_READ_RATE:
1908 return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p);
1909
1910 case SOUND_PCM_READ_CHANNELS:
1911 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p);
1912
1913 case SOUND_PCM_READ_BITS:
1914 return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ? 16 : 8, p);
1915
1916 case SOUND_PCM_WRITE_FILTER:
1917 case SNDCTL_DSP_SETSYNCRO:
1918 case SOUND_PCM_READ_FILTER:
1919 return -EINVAL;
1920
1921 }
1922 return mixdev_ioctl(s->codec, cmd, arg);
1923 }
1924
1925 static int es1371_open(struct inode *inode, struct file *file)
1926 {
1927 int minor = iminor(inode);
1928 DECLARE_WAITQUEUE(wait, current);
1929 unsigned long flags;
1930 struct list_head *list;
1931 struct es1371_state *s;
1932
1933 for (list = devs.next; ; list = list->next) {
1934 if (list == &devs)
1935 return -ENODEV;
1936 s = list_entry(list, struct es1371_state, devs);
1937 if (!((s->dev_audio ^ minor) & ~0xf))
1938 break;
1939 }
1940 VALIDATE_STATE(s);
1941 file->private_data = s;
1942 /* wait for device to become free */
1943 mutex_lock(&s->open_mutex);
1944 while (s->open_mode & file->f_mode) {
1945 if (file->f_flags & O_NONBLOCK) {
1946 mutex_unlock(&s->open_mutex);
1947 return -EBUSY;
1948 }
1949 add_wait_queue(&s->open_wait, &wait);
1950 __set_current_state(TASK_INTERRUPTIBLE);
1951 mutex_unlock(&s->open_mutex);
1952 schedule();
1953 remove_wait_queue(&s->open_wait, &wait);
1954 set_current_state(TASK_RUNNING);
1955 if (signal_pending(current))
1956 return -ERESTARTSYS;
1957 mutex_lock(&s->open_mutex);
1958 }
1959 if (file->f_mode & FMODE_READ) {
1960 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1961 s->dma_adc.enabled = 1;
1962 set_adc_rate(s, 8000);
1963 }
1964 if (file->f_mode & FMODE_WRITE) {
1965 s->dma_dac2.ossfragshift = s->dma_dac2.ossmaxfrags = s->dma_dac2.subdivision = 0;
1966 s->dma_dac2.enabled = 1;
1967 set_dac2_rate(s, 8000);
1968 }
1969 spin_lock_irqsave(&s->lock, flags);
1970 if (file->f_mode & FMODE_READ) {
1971 s->sctrl &= ~SCTRL_R1FMT;
1972 if ((minor & 0xf) == SND_DEV_DSP16)
1973 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_R1FMT;
1974 else
1975 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_R1FMT;
1976 }
1977 if (file->f_mode & FMODE_WRITE) {
1978 s->sctrl &= ~SCTRL_P2FMT;
1979 if ((minor & 0xf) == SND_DEV_DSP16)
1980 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P2FMT;
1981 else
1982 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P2FMT;
1983 }
1984 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
1985 spin_unlock_irqrestore(&s->lock, flags);
1986 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1987 mutex_unlock(&s->open_mutex);
1988 mutex_init(&s->sem);
1989 return nonseekable_open(inode, file);
1990 }
1991
1992 static int es1371_release(struct inode *inode, struct file *file)
1993 {
1994 struct es1371_state *s = (struct es1371_state *)file->private_data;
1995
1996 VALIDATE_STATE(s);
1997 lock_kernel();
1998 if (file->f_mode & FMODE_WRITE)
1999 drain_dac2(s, file->f_flags & O_NONBLOCK);
2000 mutex_lock(&s->open_mutex);
2001 if (file->f_mode & FMODE_WRITE) {
2002 stop_dac2(s);
2003 dealloc_dmabuf(s, &s->dma_dac2);
2004 }
2005 if (file->f_mode & FMODE_READ) {
2006 stop_adc(s);
2007 dealloc_dmabuf(s, &s->dma_adc);
2008 }
2009 s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
2010 mutex_unlock(&s->open_mutex);
2011 wake_up(&s->open_wait);
2012 unlock_kernel();
2013 return 0;
2014 }
2015
2016 static /*const*/ struct file_operations es1371_audio_fops = {
2017 .owner = THIS_MODULE,
2018 .llseek = no_llseek,
2019 .read = es1371_read,
2020 .write = es1371_write,
2021 .poll = es1371_poll,
2022 .ioctl = es1371_ioctl,
2023 .mmap = es1371_mmap,
2024 .open = es1371_open,
2025 .release = es1371_release,
2026 };
2027
2028 /* --------------------------------------------------------------------- */
2029
2030 static ssize_t es1371_write_dac(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
2031 {
2032 struct es1371_state *s = (struct es1371_state *)file->private_data;
2033 DECLARE_WAITQUEUE(wait, current);
2034 ssize_t ret = 0;
2035 unsigned long flags;
2036 unsigned swptr;
2037 int cnt;
2038
2039 VALIDATE_STATE(s);
2040 if (s->dma_dac1.mapped)
2041 return -ENXIO;
2042 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2043 return ret;
2044 if (!access_ok(VERIFY_READ, buffer, count))
2045 return -EFAULT;
2046 add_wait_queue(&s->dma_dac1.wait, &wait);
2047 while (count > 0) {
2048 spin_lock_irqsave(&s->lock, flags);
2049 if (s->dma_dac1.count < 0) {
2050 s->dma_dac1.count = 0;
2051 s->dma_dac1.swptr = s->dma_dac1.hwptr;
2052 }
2053 swptr = s->dma_dac1.swptr;
2054 cnt = s->dma_dac1.dmasize-swptr;
2055 if (s->dma_dac1.count + cnt > s->dma_dac1.dmasize)
2056 cnt = s->dma_dac1.dmasize - s->dma_dac1.count;
2057 if (cnt <= 0)
2058 __set_current_state(TASK_INTERRUPTIBLE);
2059 spin_unlock_irqrestore(&s->lock, flags);
2060 if (cnt > count)
2061 cnt = count;
2062 if (cnt <= 0) {
2063 if (s->dma_dac1.enabled)
2064 start_dac1(s);
2065 if (file->f_flags & O_NONBLOCK) {
2066 if (!ret)
2067 ret = -EAGAIN;
2068 break;
2069 }
2070 schedule();
2071 if (signal_pending(current)) {
2072 if (!ret)
2073 ret = -ERESTARTSYS;
2074 break;
2075 }
2076 continue;
2077 }
2078 if (copy_from_user(s->dma_dac1.rawbuf + swptr, buffer, cnt)) {
2079 if (!ret)
2080 ret = -EFAULT;
2081 break;
2082 }
2083 swptr = (swptr + cnt) % s->dma_dac1.dmasize;
2084 spin_lock_irqsave(&s->lock, flags);
2085 s->dma_dac1.swptr = swptr;
2086 s->dma_dac1.count += cnt;
2087 s->dma_dac1.endcleared = 0;
2088 spin_unlock_irqrestore(&s->lock, flags);
2089 count -= cnt;
2090 buffer += cnt;
2091 ret += cnt;
2092 if (s->dma_dac1.enabled)
2093 start_dac1(s);
2094 }
2095 remove_wait_queue(&s->dma_dac1.wait, &wait);
2096 set_current_state(TASK_RUNNING);
2097 return ret;
2098 }
2099
2100 /* No kernel lock - we have our own spinlock */
2101 static unsigned int es1371_poll_dac(struct file *file, struct poll_table_struct *wait)
2102 {
2103 struct es1371_state *s = (struct es1371_state *)file->private_data;
2104 unsigned long flags;
2105 unsigned int mask = 0;
2106
2107 VALIDATE_STATE(s);
2108 if (!s->dma_dac1.ready && prog_dmabuf_dac1(s))
2109 return 0;
2110 poll_wait(file, &s->dma_dac1.wait, wait);
2111 spin_lock_irqsave(&s->lock, flags);
2112 es1371_update_ptr(s);
2113 if (s->dma_dac1.mapped) {
2114 if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
2115 mask |= POLLOUT | POLLWRNORM;
2116 } else {
2117 if ((signed)s->dma_dac1.dmasize >= s->dma_dac1.count + (signed)s->dma_dac1.fragsize)
2118 mask |= POLLOUT | POLLWRNORM;
2119 }
2120 spin_unlock_irqrestore(&s->lock, flags);
2121 return mask;
2122 }
2123
2124 static int es1371_mmap_dac(struct file *file, struct vm_area_struct *vma)
2125 {
2126 struct es1371_state *s = (struct es1371_state *)file->private_data;
2127 int ret;
2128 unsigned long size;
2129
2130 VALIDATE_STATE(s);
2131 if (!(vma->vm_flags & VM_WRITE))
2132 return -EINVAL;
2133 lock_kernel();
2134 if ((ret = prog_dmabuf_dac1(s)) != 0)
2135 goto out;
2136 ret = -EINVAL;
2137 if (vma->vm_pgoff != 0)
2138 goto out;
2139 size = vma->vm_end - vma->vm_start;
2140 if (size > (PAGE_SIZE << s->dma_dac1.buforder))
2141 goto out;
2142 ret = -EAGAIN;
2143 if (remap_pfn_range(vma, vma->vm_start,
2144 virt_to_phys(s->dma_dac1.rawbuf) >> PAGE_SHIFT,
2145 size, vma->vm_page_prot))
2146 goto out;
2147 s->dma_dac1.mapped = 1;
2148 ret = 0;
2149 out:
2150 unlock_kernel();
2151 return ret;
2152 }
2153
2154 static int es1371_ioctl_dac(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2155 {
2156 struct es1371_state *s = (struct es1371_state *)file->private_data;
2157 unsigned long flags;
2158 audio_buf_info abinfo;
2159 count_info cinfo;
2160 int count;
2161 int val, ret;
2162 int __user *p = (int __user *)arg;
2163
2164 VALIDATE_STATE(s);
2165 switch (cmd) {
2166 case OSS_GETVERSION:
2167 return put_user(SOUND_VERSION, p);
2168
2169 case SNDCTL_DSP_SYNC:
2170 return drain_dac1(s, 0/*file->f_flags & O_NONBLOCK*/);
2171
2172 case SNDCTL_DSP_SETDUPLEX:
2173 return -EINVAL;
2174
2175 case SNDCTL_DSP_GETCAPS:
2176 return put_user(DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
2177
2178 case SNDCTL_DSP_RESET:
2179 stop_dac1(s);
2180 synchronize_irq(s->irq);
2181 s->dma_dac1.swptr = s->dma_dac1.hwptr = s->dma_dac1.count = s->dma_dac1.total_bytes = 0;
2182 return 0;
2183
2184 case SNDCTL_DSP_SPEED:
2185 if (get_user(val, p))
2186 return -EFAULT;
2187 if (val >= 0) {
2188 stop_dac1(s);
2189 s->dma_dac1.ready = 0;
2190 set_dac1_rate(s, val);
2191 }
2192 return put_user(s->dac1rate, p);
2193
2194 case SNDCTL_DSP_STEREO:
2195 if (get_user(val, p))
2196 return -EFAULT;
2197 stop_dac1(s);
2198 s->dma_dac1.ready = 0;
2199 spin_lock_irqsave(&s->lock, flags);
2200 if (val)
2201 s->sctrl |= SCTRL_P1SMB;
2202 else
2203 s->sctrl &= ~SCTRL_P1SMB;
2204 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2205 spin_unlock_irqrestore(&s->lock, flags);
2206 return 0;
2207
2208 case SNDCTL_DSP_CHANNELS:
2209 if (get_user(val, p))
2210 return -EFAULT;
2211 if (val != 0) {
2212 stop_dac1(s);
2213 s->dma_dac1.ready = 0;
2214 spin_lock_irqsave(&s->lock, flags);
2215 if (val >= 2)
2216 s->sctrl |= SCTRL_P1SMB;
2217 else
2218 s->sctrl &= ~SCTRL_P1SMB;
2219 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2220 spin_unlock_irqrestore(&s->lock, flags);
2221 }
2222 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p);
2223
2224 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2225 return put_user(AFMT_S16_LE|AFMT_U8, p);
2226
2227 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2228 if (get_user(val, p))
2229 return -EFAULT;
2230 if (val != AFMT_QUERY) {
2231 stop_dac1(s);
2232 s->dma_dac1.ready = 0;
2233 spin_lock_irqsave(&s->lock, flags);
2234 if (val == AFMT_S16_LE)
2235 s->sctrl |= SCTRL_P1SEB;
2236 else
2237 s->sctrl &= ~SCTRL_P1SEB;
2238 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2239 spin_unlock_irqrestore(&s->lock, flags);
2240 }
2241 return put_user((s->sctrl & SCTRL_P1SEB) ? AFMT_S16_LE : AFMT_U8, p);
2242
2243 case SNDCTL_DSP_POST:
2244 return 0;
2245
2246 case SNDCTL_DSP_GETTRIGGER:
2247 return put_user((s->ctrl & CTRL_DAC1_EN) ? PCM_ENABLE_OUTPUT : 0, p);
2248
2249 case SNDCTL_DSP_SETTRIGGER:
2250 if (get_user(val, p))
2251 return -EFAULT;
2252 if (val & PCM_ENABLE_OUTPUT) {
2253 if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
2254 return ret;
2255 s->dma_dac1.enabled = 1;
2256 start_dac1(s);
2257 } else {
2258 s->dma_dac1.enabled = 0;
2259 stop_dac1(s);
2260 }
2261 return 0;
2262
2263 case SNDCTL_DSP_GETOSPACE:
2264 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2265 return val;
2266 spin_lock_irqsave(&s->lock, flags);
2267 es1371_update_ptr(s);
2268 abinfo.fragsize = s->dma_dac1.fragsize;
2269 count = s->dma_dac1.count;
2270 if (count < 0)
2271 count = 0;
2272 abinfo.bytes = s->dma_dac1.dmasize - count;
2273 abinfo.fragstotal = s->dma_dac1.numfrag;
2274 abinfo.fragments = abinfo.bytes >> s->dma_dac1.fragshift;
2275 spin_unlock_irqrestore(&s->lock, flags);
2276 return copy_to_user((void __user *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2277
2278 case SNDCTL_DSP_NONBLOCK:
2279 file->f_flags |= O_NONBLOCK;
2280 return 0;
2281
2282 case SNDCTL_DSP_GETODELAY:
2283 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2284 return val;
2285 spin_lock_irqsave(&s->lock, flags);
2286 es1371_update_ptr(s);
2287 count = s->dma_dac1.count;
2288 spin_unlock_irqrestore(&s->lock, flags);
2289 if (count < 0)
2290 count = 0;
2291 return put_user(count, p);
2292
2293 case SNDCTL_DSP_GETOPTR:
2294 if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
2295 return val;
2296 spin_lock_irqsave(&s->lock, flags);
2297 es1371_update_ptr(s);
2298 cinfo.bytes = s->dma_dac1.total_bytes;
2299 count = s->dma_dac1.count;
2300 if (count < 0)
2301 count = 0;
2302 cinfo.blocks = count >> s->dma_dac1.fragshift;
2303 cinfo.ptr = s->dma_dac1.hwptr;
2304 if (s->dma_dac1.mapped)
2305 s->dma_dac1.count &= s->dma_dac1.fragsize-1;
2306 spin_unlock_irqrestore(&s->lock, flags);
2307 if (copy_to_user((void __user *)arg, &cinfo, sizeof(cinfo)))
2308 return -EFAULT;
2309 return 0;
2310
2311 case SNDCTL_DSP_GETBLKSIZE:
2312 if ((val = prog_dmabuf_dac1(s)))
2313 return val;
2314 return put_user(s->dma_dac1.fragsize, p);
2315
2316 case SNDCTL_DSP_SETFRAGMENT:
2317 if (get_user(val, p))
2318 return -EFAULT;
2319 s->dma_dac1.ossfragshift = val & 0xffff;
2320 s->dma_dac1.ossmaxfrags = (val >> 16) & 0xffff;
2321 if (s->dma_dac1.ossfragshift < 4)
2322 s->dma_dac1.ossfragshift = 4;
2323 if (s->dma_dac1.ossfragshift > 15)
2324 s->dma_dac1.ossfragshift = 15;
2325 if (s->dma_dac1.ossmaxfrags < 4)
2326 s->dma_dac1.ossmaxfrags = 4;
2327 return 0;
2328
2329 case SNDCTL_DSP_SUBDIVIDE:
2330 if (s->dma_dac1.subdivision)
2331 return -EINVAL;
2332 if (get_user(val, p))
2333 return -EFAULT;
2334 if (val != 1 && val != 2 && val != 4)
2335 return -EINVAL;
2336 s->dma_dac1.subdivision = val;
2337 return 0;
2338
2339 case SOUND_PCM_READ_RATE:
2340 return put_user(s->dac1rate, p);
2341
2342 case SOUND_PCM_READ_CHANNELS:
2343 return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p);
2344
2345 case SOUND_PCM_READ_BITS:
2346 return put_user((s->sctrl & SCTRL_P1SEB) ? 16 : 8, p);
2347
2348 case SOUND_PCM_WRITE_FILTER:
2349 case SNDCTL_DSP_SETSYNCRO:
2350 case SOUND_PCM_READ_FILTER:
2351 return -EINVAL;
2352
2353 }
2354 return mixdev_ioctl(s->codec, cmd, arg);
2355 }
2356
2357 static int es1371_open_dac(struct inode *inode, struct file *file)
2358 {
2359 int minor = iminor(inode);
2360 DECLARE_WAITQUEUE(wait, current);
2361 unsigned long flags;
2362 struct list_head *list;
2363 struct es1371_state *s;
2364
2365 for (list = devs.next; ; list = list->next) {
2366 if (list == &devs)
2367 return -ENODEV;
2368 s = list_entry(list, struct es1371_state, devs);
2369 if (!((s->dev_dac ^ minor) & ~0xf))
2370 break;
2371 }
2372 VALIDATE_STATE(s);
2373 /* we allow opening with O_RDWR, most programs do it although they will only write */
2374 #if 0
2375 if (file->f_mode & FMODE_READ)
2376 return -EPERM;
2377 #endif
2378 if (!(file->f_mode & FMODE_WRITE))
2379 return -EINVAL;
2380 file->private_data = s;
2381 /* wait for device to become free */
2382 mutex_lock(&s->open_mutex);
2383 while (s->open_mode & FMODE_DAC) {
2384 if (file->f_flags & O_NONBLOCK) {
2385 mutex_unlock(&s->open_mutex);
2386 return -EBUSY;
2387 }
2388 add_wait_queue(&s->open_wait, &wait);
2389 __set_current_state(TASK_INTERRUPTIBLE);
2390 mutex_unlock(&s->open_mutex);
2391 schedule();
2392 remove_wait_queue(&s->open_wait, &wait);
2393 set_current_state(TASK_RUNNING);
2394 if (signal_pending(current))
2395 return -ERESTARTSYS;
2396 mutex_lock(&s->open_mutex);
2397 }
2398 s->dma_dac1.ossfragshift = s->dma_dac1.ossmaxfrags = s->dma_dac1.subdivision = 0;
2399 s->dma_dac1.enabled = 1;
2400 set_dac1_rate(s, 8000);
2401 spin_lock_irqsave(&s->lock, flags);
2402 s->sctrl &= ~SCTRL_P1FMT;
2403 if ((minor & 0xf) == SND_DEV_DSP16)
2404 s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P1FMT;
2405 else
2406 s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P1FMT;
2407 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2408 spin_unlock_irqrestore(&s->lock, flags);
2409 s->open_mode |= FMODE_DAC;
2410 mutex_unlock(&s->open_mutex);
2411 return nonseekable_open(inode, file);
2412 }
2413
2414 static int es1371_release_dac(struct inode *inode, struct file *file)
2415 {
2416 struct es1371_state *s = (struct es1371_state *)file->private_data;
2417
2418 VALIDATE_STATE(s);
2419 lock_kernel();
2420 drain_dac1(s, file->f_flags & O_NONBLOCK);
2421 mutex_lock(&s->open_mutex);
2422 stop_dac1(s);
2423 dealloc_dmabuf(s, &s->dma_dac1);
2424 s->open_mode &= ~FMODE_DAC;
2425 mutex_unlock(&s->open_mutex);
2426 wake_up(&s->open_wait);
2427 unlock_kernel();
2428 return 0;
2429 }
2430
2431 static /*const*/ struct file_operations es1371_dac_fops = {
2432 .owner = THIS_MODULE,
2433 .llseek = no_llseek,
2434 .write = es1371_write_dac,
2435 .poll = es1371_poll_dac,
2436 .ioctl = es1371_ioctl_dac,
2437 .mmap = es1371_mmap_dac,
2438 .open = es1371_open_dac,
2439 .release = es1371_release_dac,
2440 };
2441
2442 /* --------------------------------------------------------------------- */
2443
2444 static ssize_t es1371_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
2445 {
2446 struct es1371_state *s = (struct es1371_state *)file->private_data;
2447 DECLARE_WAITQUEUE(wait, current);
2448 ssize_t ret;
2449 unsigned long flags;
2450 unsigned ptr;
2451 int cnt;
2452
2453 VALIDATE_STATE(s);
2454 if (!access_ok(VERIFY_WRITE, buffer, count))
2455 return -EFAULT;
2456 if (count == 0)
2457 return 0;
2458 ret = 0;
2459 add_wait_queue(&s->midi.iwait, &wait);
2460 while (count > 0) {
2461 spin_lock_irqsave(&s->lock, flags);
2462 ptr = s->midi.ird;
2463 cnt = MIDIINBUF - ptr;
2464 if (s->midi.icnt < cnt)
2465 cnt = s->midi.icnt;
2466 if (cnt <= 0)
2467 __set_current_state(TASK_INTERRUPTIBLE);
2468 spin_unlock_irqrestore(&s->lock, flags);
2469 if (cnt > count)
2470 cnt = count;
2471 if (cnt <= 0) {
2472 if (file->f_flags & O_NONBLOCK) {
2473 if (!ret)
2474 ret = -EAGAIN;
2475 break;
2476 }
2477 schedule();
2478 if (signal_pending(current)) {
2479 if (!ret)
2480 ret = -ERESTARTSYS;
2481 break;
2482 }
2483 continue;
2484 }
2485 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
2486 if (!ret)
2487 ret = -EFAULT;
2488 break;
2489 }
2490 ptr = (ptr + cnt) % MIDIINBUF;
2491 spin_lock_irqsave(&s->lock, flags);
2492 s->midi.ird = ptr;
2493 s->midi.icnt -= cnt;
2494 spin_unlock_irqrestore(&s->lock, flags);
2495 count -= cnt;
2496 buffer += cnt;
2497 ret += cnt;
2498 break;
2499 }
2500 __set_current_state(TASK_RUNNING);
2501 remove_wait_queue(&s->midi.iwait, &wait);
2502 return ret;
2503 }
2504
2505 static ssize_t es1371_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
2506 {
2507 struct es1371_state *s = (struct es1371_state *)file->private_data;
2508 DECLARE_WAITQUEUE(wait, current);
2509 ssize_t ret;
2510 unsigned long flags;
2511 unsigned ptr;
2512 int cnt;
2513
2514 VALIDATE_STATE(s);
2515 if (!access_ok(VERIFY_READ, buffer, count))
2516 return -EFAULT;
2517 if (count == 0)
2518 return 0;
2519 ret = 0;
2520 add_wait_queue(&s->midi.owait, &wait);
2521 while (count > 0) {
2522 spin_lock_irqsave(&s->lock, flags);
2523 ptr = s->midi.owr;
2524 cnt = MIDIOUTBUF - ptr;
2525 if (s->midi.ocnt + cnt > MIDIOUTBUF)
2526 cnt = MIDIOUTBUF - s->midi.ocnt;
2527 if (cnt <= 0) {
2528 __set_current_state(TASK_INTERRUPTIBLE);
2529 es1371_handle_midi(s);
2530 }
2531 spin_unlock_irqrestore(&s->lock, flags);
2532 if (cnt > count)
2533 cnt = count;
2534 if (cnt <= 0) {
2535 if (file->f_flags & O_NONBLOCK) {
2536 if (!ret)
2537 ret = -EAGAIN;
2538 break;
2539 }
2540 schedule();
2541 if (signal_pending(current)) {
2542 if (!ret)
2543 ret = -ERESTARTSYS;
2544 break;
2545 }
2546 continue;
2547 }
2548 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
2549 if (!ret)
2550 ret = -EFAULT;
2551 break;
2552 }
2553 ptr = (ptr + cnt) % MIDIOUTBUF;
2554 spin_lock_irqsave(&s->lock, flags);
2555 s->midi.owr = ptr;
2556 s->midi.ocnt += cnt;
2557 spin_unlock_irqrestore(&s->lock, flags);
2558 count -= cnt;
2559 buffer += cnt;
2560 ret += cnt;
2561 spin_lock_irqsave(&s->lock, flags);
2562 es1371_handle_midi(s);
2563 spin_unlock_irqrestore(&s->lock, flags);
2564 }
2565 __set_current_state(TASK_RUNNING);
2566 remove_wait_queue(&s->midi.owait, &wait);
2567 return ret;
2568 }
2569
2570 /* No kernel lock - we have our own spinlock */
2571 static unsigned int es1371_midi_poll(struct file *file, struct poll_table_struct *wait)
2572 {
2573 struct es1371_state *s = (struct es1371_state *)file->private_data;
2574 unsigned long flags;
2575 unsigned int mask = 0;
2576
2577 VALIDATE_STATE(s);
2578 if (file->f_mode & FMODE_WRITE)
2579 poll_wait(file, &s->midi.owait, wait);
2580 if (file->f_mode & FMODE_READ)
2581 poll_wait(file, &s->midi.iwait, wait);
2582 spin_lock_irqsave(&s->lock, flags);
2583 if (file->f_mode & FMODE_READ) {
2584 if (s->midi.icnt > 0)
2585 mask |= POLLIN | POLLRDNORM;
2586 }
2587 if (file->f_mode & FMODE_WRITE) {
2588 if (s->midi.ocnt < MIDIOUTBUF)
2589 mask |= POLLOUT | POLLWRNORM;
2590 }
2591 spin_unlock_irqrestore(&s->lock, flags);
2592 return mask;
2593 }
2594
2595 static int es1371_midi_open(struct inode *inode, struct file *file)
2596 {
2597 int minor = iminor(inode);
2598 DECLARE_WAITQUEUE(wait, current);
2599 unsigned long flags;
2600 struct list_head *list;
2601 struct es1371_state *s;
2602
2603 for (list = devs.next; ; list = list->next) {
2604 if (list == &devs)
2605 return -ENODEV;
2606 s = list_entry(list, struct es1371_state, devs);
2607 if (s->dev_midi == minor)
2608 break;
2609 }
2610 VALIDATE_STATE(s);
2611 file->private_data = s;
2612 /* wait for device to become free */
2613 mutex_lock(&s->open_mutex);
2614 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
2615 if (file->f_flags & O_NONBLOCK) {
2616 mutex_unlock(&s->open_mutex);
2617 return -EBUSY;
2618 }
2619 add_wait_queue(&s->open_wait, &wait);
2620 __set_current_state(TASK_INTERRUPTIBLE);
2621 mutex_unlock(&s->open_mutex);
2622 schedule();
2623 remove_wait_queue(&s->open_wait, &wait);
2624 set_current_state(TASK_RUNNING);
2625 if (signal_pending(current))
2626 return -ERESTARTSYS;
2627 mutex_lock(&s->open_mutex);
2628 }
2629 spin_lock_irqsave(&s->lock, flags);
2630 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2631 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2632 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2633 outb(UCTRL_CNTRL_SWR, s->io+ES1371_REG_UART_CONTROL);
2634 outb(0, s->io+ES1371_REG_UART_CONTROL);
2635 outb(0, s->io+ES1371_REG_UART_TEST);
2636 }
2637 if (file->f_mode & FMODE_READ) {
2638 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2639 }
2640 if (file->f_mode & FMODE_WRITE) {
2641 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2642 }
2643 s->ctrl |= CTRL_UART_EN;
2644 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2645 es1371_handle_midi(s);
2646 spin_unlock_irqrestore(&s->lock, flags);
2647 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
2648 mutex_unlock(&s->open_mutex);
2649 return nonseekable_open(inode, file);
2650 }
2651
2652 static int es1371_midi_release(struct inode *inode, struct file *file)
2653 {
2654 struct es1371_state *s = (struct es1371_state *)file->private_data;
2655 DECLARE_WAITQUEUE(wait, current);
2656 unsigned long flags;
2657 unsigned count, tmo;
2658
2659 VALIDATE_STATE(s);
2660 lock_kernel();
2661 if (file->f_mode & FMODE_WRITE) {
2662 add_wait_queue(&s->midi.owait, &wait);
2663 for (;;) {
2664 __set_current_state(TASK_INTERRUPTIBLE);
2665 spin_lock_irqsave(&s->lock, flags);
2666 count = s->midi.ocnt;
2667 spin_unlock_irqrestore(&s->lock, flags);
2668 if (count <= 0)
2669 break;
2670 if (signal_pending(current))
2671 break;
2672 if (file->f_flags & O_NONBLOCK)
2673 break;
2674 tmo = (count * HZ) / 3100;
2675 if (!schedule_timeout(tmo ? : 1) && tmo)
2676 printk(KERN_DEBUG PFX "midi timed out??\n");
2677 }
2678 remove_wait_queue(&s->midi.owait, &wait);
2679 set_current_state(TASK_RUNNING);
2680 }
2681 mutex_lock(&s->open_mutex);
2682 s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE));
2683 spin_lock_irqsave(&s->lock, flags);
2684 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2685 s->ctrl &= ~CTRL_UART_EN;
2686 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2687 }
2688 spin_unlock_irqrestore(&s->lock, flags);
2689 mutex_unlock(&s->open_mutex);
2690 wake_up(&s->open_wait);
2691 unlock_kernel();
2692 return 0;
2693 }
2694
2695 static /*const*/ struct file_operations es1371_midi_fops = {
2696 .owner = THIS_MODULE,
2697 .llseek = no_llseek,
2698 .read = es1371_midi_read,
2699 .write = es1371_midi_write,
2700 .poll = es1371_midi_poll,
2701 .open = es1371_midi_open,
2702 .release = es1371_midi_release,
2703 };
2704
2705 /* --------------------------------------------------------------------- */
2706
2707 /*
2708 * for debugging purposes, we'll create a proc device that dumps the
2709 * CODEC chipstate
2710 */
2711
2712 #ifdef ES1371_DEBUG
2713 static int proc_es1371_dump (char *buf, char **start, off_t fpos, int length, int *eof, void *data)
2714 {
2715 struct es1371_state *s;
2716 int cnt, len = 0;
2717
2718 if (list_empty(&devs))
2719 return 0;
2720 s = list_entry(devs.next, struct es1371_state, devs);
2721 /* print out header */
2722 len += sprintf(buf + len, "\t\tCreative ES137x Debug Dump-o-matic\n");
2723
2724 /* print out CODEC state */
2725 len += sprintf (buf + len, "AC97 CODEC state\n");
2726 for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
2727 len+= sprintf (buf + len, "reg:0x%02x val:0x%04x\n", cnt, rdcodec(s->codec, cnt));
2728
2729 if (fpos >=len){
2730 *start = buf;
2731 *eof =1;
2732 return 0;
2733 }
2734 *start = buf + fpos;
2735 if ((len -= fpos) > length)
2736 return length;
2737 *eof =1;
2738 return len;
2739
2740 }
2741 #endif /* ES1371_DEBUG */
2742
2743 /* --------------------------------------------------------------------- */
2744
2745 /* maximum number of devices; only used for command line params */
2746 #define NR_DEVICE 5
2747
2748 static int spdif[NR_DEVICE];
2749 static int nomix[NR_DEVICE];
2750 static int amplifier[NR_DEVICE];
2751
2752 static unsigned int devindex;
2753
2754 module_param_array(spdif, bool, NULL, 0);
2755 MODULE_PARM_DESC(spdif, "if 1 the output is in S/PDIF digital mode");
2756 module_param_array(nomix, bool, NULL, 0);
2757 MODULE_PARM_DESC(nomix, "if 1 no analog audio is mixed to the digital output");
2758 module_param_array(amplifier, bool, NULL, 0);
2759 MODULE_PARM_DESC(amplifier, "Set to 1 if the machine needs the amp control enabling (many laptops)");
2760
2761 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2762 MODULE_DESCRIPTION("ES1371 AudioPCI97 Driver");
2763 MODULE_LICENSE("GPL");
2764
2765
2766 /* --------------------------------------------------------------------- */
2767
2768 static struct initvol {
2769 int mixch;
2770 int vol;
2771 } initvol[] __devinitdata = {
2772 { SOUND_MIXER_WRITE_LINE, 0x4040 },
2773 { SOUND_MIXER_WRITE_CD, 0x4040 },
2774 { MIXER_WRITE(SOUND_MIXER_VIDEO), 0x4040 },
2775 { SOUND_MIXER_WRITE_LINE1, 0x4040 },
2776 { SOUND_MIXER_WRITE_PCM, 0x4040 },
2777 { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
2778 { MIXER_WRITE(SOUND_MIXER_PHONEOUT), 0x4040 },
2779 { SOUND_MIXER_WRITE_OGAIN, 0x4040 },
2780 { MIXER_WRITE(SOUND_MIXER_PHONEIN), 0x4040 },
2781 { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
2782 { SOUND_MIXER_WRITE_MIC, 0x4040 },
2783 { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
2784 { SOUND_MIXER_WRITE_IGAIN, 0x4040 }
2785 };
2786
2787 static struct
2788 {
2789 short svid, sdid;
2790 } amplifier_needed[] =
2791 {
2792 { 0x107B, 0x2150 }, /* Gateway Solo 2150 */
2793 { 0x13BD, 0x100C }, /* Mebius PC-MJ100V */
2794 { 0x1102, 0x5938 }, /* Targa Xtender 300 */
2795 { 0x1102, 0x8938 }, /* IPC notebook */
2796 { PCI_ANY_ID, PCI_ANY_ID }
2797 };
2798
2799 #ifdef SUPPORT_JOYSTICK
2800
2801 static int __devinit es1371_register_gameport(struct es1371_state *s)
2802 {
2803 struct gameport *gp;
2804 int gpio;
2805
2806 for (gpio = 0x218; gpio >= 0x200; gpio -= 0x08)
2807 if (request_region(gpio, JOY_EXTENT, "es1371"))
2808 break;
2809
2810 if (gpio < 0x200) {
2811 printk(KERN_ERR PFX "no free joystick address found\n");
2812 return -EBUSY;
2813 }
2814
2815 s->gameport = gp = gameport_allocate_port();
2816 if (!gp) {
2817 printk(KERN_ERR PFX "can not allocate memory for gameport\n");
2818 release_region(gpio, JOY_EXTENT);
2819 return -ENOMEM;
2820 }
2821
2822 gameport_set_name(gp, "ESS1371 Gameport");
2823 gameport_set_phys(gp, "isa%04x/gameport0", gpio);
2824 gp->dev.parent = &s->dev->dev;
2825 gp->io = gpio;
2826
2827 s->ctrl |= CTRL_JYSTK_EN | (((gpio >> 3) & CTRL_JOY_MASK) << CTRL_JOY_SHIFT);
2828 outl(s->ctrl, s->io + ES1371_REG_CONTROL);
2829
2830 gameport_register_port(gp);
2831
2832 return 0;
2833 }
2834
2835 static inline void es1371_unregister_gameport(struct es1371_state *s)
2836 {
2837 if (s->gameport) {
2838 int gpio = s->gameport->io;
2839 gameport_unregister_port(s->gameport);
2840 release_region(gpio, JOY_EXTENT);
2841
2842 }
2843 }
2844
2845 #else
2846 static inline int es1371_register_gameport(struct es1371_state *s) { return -ENOSYS; }
2847 static inline void es1371_unregister_gameport(struct es1371_state *s) { }
2848 #endif /* SUPPORT_JOYSTICK */
2849
2850
2851 static int __devinit es1371_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
2852 {
2853 struct es1371_state *s;
2854 mm_segment_t fs;
2855 int i, val, res = -1;
2856 int idx;
2857 unsigned long tmo;
2858 signed long tmo2;
2859 unsigned int cssr;
2860
2861 if ((res=pci_enable_device(pcidev)))
2862 return res;
2863
2864 if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO))
2865 return -ENODEV;
2866 if (pcidev->irq == 0)
2867 return -ENODEV;
2868 i = pci_set_dma_mask(pcidev, DMA_32BIT_MASK);
2869 if (i) {
2870 printk(KERN_WARNING "es1371: architecture does not support 32bit PCI busmaster DMA\n");
2871 return i;
2872 }
2873 if (!(s = kmalloc(sizeof(struct es1371_state), GFP_KERNEL))) {
2874 printk(KERN_WARNING PFX "out of memory\n");
2875 return -ENOMEM;
2876 }
2877 memset(s, 0, sizeof(struct es1371_state));
2878
2879 s->codec = ac97_alloc_codec();
2880 if(s->codec == NULL)
2881 goto err_codec;
2882
2883 init_waitqueue_head(&s->dma_adc.wait);
2884 init_waitqueue_head(&s->dma_dac1.wait);
2885 init_waitqueue_head(&s->dma_dac2.wait);
2886 init_waitqueue_head(&s->open_wait);
2887 init_waitqueue_head(&s->midi.iwait);
2888 init_waitqueue_head(&s->midi.owait);
2889 mutex_init(&s->open_mutex);
2890 spin_lock_init(&s->lock);
2891 s->magic = ES1371_MAGIC;
2892 s->dev = pcidev;
2893 s->io = pci_resource_start(pcidev, 0);
2894 s->irq = pcidev->irq;
2895 s->vendor = pcidev->vendor;
2896 s->device = pcidev->device;
2897 pci_read_config_byte(pcidev, PCI_REVISION_ID, &s->rev);
2898 s->codec->private_data = s;
2899 s->codec->id = 0;
2900 s->codec->codec_read = rdcodec;
2901 s->codec->codec_write = wrcodec;
2902 printk(KERN_INFO PFX "found chip, vendor id 0x%04x device id 0x%04x revision 0x%02x\n",
2903 s->vendor, s->device, s->rev);
2904 if (!request_region(s->io, ES1371_EXTENT, "es1371")) {
2905 printk(KERN_ERR PFX "io ports %#lx-%#lx in use\n", s->io, s->io+ES1371_EXTENT-1);
2906 res = -EBUSY;
2907 goto err_region;
2908 }
2909 if ((res=request_irq(s->irq, es1371_interrupt, IRQF_SHARED, "es1371",s))) {
2910 printk(KERN_ERR PFX "irq %u in use\n", s->irq);
2911 goto err_irq;
2912 }
2913 printk(KERN_INFO PFX "found es1371 rev %d at io %#lx irq %u\n",
2914 s->rev, s->io, s->irq);
2915 /* register devices */
2916 if ((res=(s->dev_audio = register_sound_dsp(&es1371_audio_fops,-1)))<0)
2917 goto err_dev1;
2918 if ((res=(s->codec->dev_mixer = register_sound_mixer(&es1371_mixer_fops, -1))) < 0)
2919 goto err_dev2;
2920 if ((res=(s->dev_dac = register_sound_dsp(&es1371_dac_fops, -1))) < 0)
2921 goto err_dev3;
2922 if ((res=(s->dev_midi = register_sound_midi(&es1371_midi_fops, -1)))<0 )
2923 goto err_dev4;
2924 #ifdef ES1371_DEBUG
2925 /* initialize the debug proc device */
2926 s->ps = create_proc_read_entry("es1371",0,NULL,proc_es1371_dump,NULL);
2927 #endif /* ES1371_DEBUG */
2928
2929 /* initialize codec registers */
2930 s->ctrl = 0;
2931
2932 /* Check amplifier requirements */
2933
2934 if (amplifier[devindex])
2935 s->ctrl |= CTRL_GPIO_OUT0;
2936 else for(idx = 0; amplifier_needed[idx].svid != PCI_ANY_ID; idx++)
2937 {
2938 if(pcidev->subsystem_vendor == amplifier_needed[idx].svid &&
2939 pcidev->subsystem_device == amplifier_needed[idx].sdid)
2940 {
2941 s->ctrl |= CTRL_GPIO_OUT0; /* turn internal amplifier on */
2942 printk(KERN_INFO PFX "Enabling internal amplifier.\n");
2943 }
2944 }
2945
2946 s->sctrl = 0;
2947 cssr = 0;
2948 s->spdif_volume = -1;
2949 /* check to see if s/pdif mode is being requested */
2950 if (spdif[devindex]) {
2951 if (s->rev >= 4) {
2952 printk(KERN_INFO PFX "enabling S/PDIF output\n");
2953 s->spdif_volume = 0;
2954 cssr |= STAT_EN_SPDIF;
2955 s->ctrl |= CTRL_SPDIFEN_B;
2956 if (nomix[devindex]) /* don't mix analog inputs to s/pdif output */
2957 s->ctrl |= CTRL_RECEN_B;
2958 } else {
2959 printk(KERN_ERR PFX "revision %d does not support S/PDIF\n", s->rev);
2960 }
2961 }
2962 /* initialize the chips */
2963 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2964 outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
2965 outl(LEGACY_JFAST, s->io+ES1371_REG_LEGACY);
2966 pci_set_master(pcidev); /* enable bus mastering */
2967 /* if we are a 5880 turn on the AC97 */
2968 if (s->vendor == PCI_VENDOR_ID_ENSONIQ &&
2969 ((s->device == PCI_DEVICE_ID_ENSONIQ_CT5880 && s->rev >= CT5880REV_CT5880_C) ||
2970 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_CT5880_A) ||
2971 (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_ES1373_8))) {
2972 cssr |= CSTAT_5880_AC97_RST;
2973 outl(cssr, s->io+ES1371_REG_STATUS);
2974 /* need to delay around 20ms(bleech) to give
2975 some CODECs enough time to wakeup */
2976 tmo = jiffies + (HZ / 50) + 1;
2977 for (;;) {
2978 tmo2 = tmo - jiffies;
2979 if (tmo2 <= 0)
2980 break;
2981 schedule_timeout(tmo2);
2982 }
2983 }
2984 /* AC97 warm reset to start the bitclk */
2985 outl(s->ctrl | CTRL_SYNCRES, s->io+ES1371_REG_CONTROL);
2986 udelay(2);
2987 outl(s->ctrl, s->io+ES1371_REG_CONTROL);
2988 /* init the sample rate converter */
2989 src_init(s);
2990 /* codec init */
2991 if (!ac97_probe_codec(s->codec)) {
2992 res = -ENODEV;
2993 goto err_gp;
2994 }
2995 /* set default values */
2996
2997 fs = get_fs();
2998 set_fs(KERNEL_DS);
2999 val = SOUND_MASK_LINE;
3000 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
3001 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
3002 val = initvol[i].vol;
3003 mixdev_ioctl(s->codec, initvol[i].mixch, (unsigned long)&val);
3004 }
3005 /* mute master and PCM when in S/PDIF mode */
3006 if (s->spdif_volume != -1) {
3007 val = 0x0000;
3008 s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_VOLUME, (unsigned long)&val);
3009 s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_PCM, (unsigned long)&val);
3010 }
3011 set_fs(fs);
3012 /* turn on S/PDIF output driver if requested */
3013 outl(cssr, s->io+ES1371_REG_STATUS);
3014
3015 es1371_register_gameport(s);
3016
3017 /* store it in the driver field */
3018 pci_set_drvdata(pcidev, s);
3019 /* put it into driver list */
3020 list_add_tail(&s->devs, &devs);
3021 /* increment devindex */
3022 if (devindex < NR_DEVICE-1)
3023 devindex++;
3024 return 0;
3025
3026 err_gp:
3027 #ifdef ES1371_DEBUG
3028 if (s->ps)
3029 remove_proc_entry("es1371", NULL);
3030 #endif
3031 unregister_sound_midi(s->dev_midi);
3032 err_dev4:
3033 unregister_sound_dsp(s->dev_dac);
3034 err_dev3:
3035 unregister_sound_mixer(s->codec->dev_mixer);
3036 err_dev2:
3037 unregister_sound_dsp(s->dev_audio);
3038 err_dev1:
3039 printk(KERN_ERR PFX "cannot register misc device\n");
3040 free_irq(s->irq, s);
3041 err_irq:
3042 release_region(s->io, ES1371_EXTENT);
3043 err_region:
3044 err_codec:
3045 ac97_release_codec(s->codec);
3046 kfree(s);
3047 return res;
3048 }
3049
3050 static void __devexit es1371_remove(struct pci_dev *dev)
3051 {
3052 struct es1371_state *s = pci_get_drvdata(dev);
3053
3054 if (!s)
3055 return;
3056 list_del(&s->devs);
3057 #ifdef ES1371_DEBUG
3058 if (s->ps)
3059 remove_proc_entry("es1371", NULL);
3060 #endif /* ES1371_DEBUG */
3061 outl(0, s->io+ES1371_REG_CONTROL); /* switch everything off */
3062 outl(0, s->io+ES1371_REG_SERIAL_CONTROL); /* clear serial interrupts */
3063 synchronize_irq(s->irq);
3064 free_irq(s->irq, s);
3065 es1371_unregister_gameport(s);
3066 release_region(s->io, ES1371_EXTENT);
3067 unregister_sound_dsp(s->dev_audio);
3068 unregister_sound_mixer(s->codec->dev_mixer);
3069 unregister_sound_dsp(s->dev_dac);
3070 unregister_sound_midi(s->dev_midi);
3071 ac97_release_codec(s->codec);
3072 kfree(s);
3073 pci_set_drvdata(dev, NULL);
3074 }
3075
3076 static struct pci_device_id id_table[] = {
3077 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3078 { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3079 { PCI_VENDOR_ID_ECTIVA, PCI_DEVICE_ID_ECTIVA_EV1938, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
3080 { 0, }
3081 };
3082
3083 MODULE_DEVICE_TABLE(pci, id_table);
3084
3085 static struct pci_driver es1371_driver = {
3086 .name = "es1371",
3087 .id_table = id_table,
3088 .probe = es1371_probe,
3089 .remove = __devexit_p(es1371_remove),
3090 };
3091
3092 static int __init init_es1371(void)
3093 {
3094 printk(KERN_INFO PFX "version v0.32 time " __TIME__ " " __DATE__ "\n");
3095 return pci_register_driver(&es1371_driver);
3096 }
3097
3098 static void __exit cleanup_es1371(void)
3099 {
3100 printk(KERN_INFO PFX "unloading\n");
3101 pci_unregister_driver(&es1371_driver);
3102 }
3103
3104 module_init(init_es1371);
3105 module_exit(cleanup_es1371);
3106
3107 /* --------------------------------------------------------------------- */
3108
3109 #ifndef MODULE
3110
3111 /* format is: es1371=[spdif,[nomix,[amplifier]]] */
3112
3113 static int __init es1371_setup(char *str)
3114 {
3115 static unsigned __initdata nr_dev = 0;
3116
3117 if (nr_dev >= NR_DEVICE)
3118 return 0;
3119
3120 (void)
3121 ((get_option(&str, &spdif[nr_dev]) == 2)
3122 && (get_option(&str, &nomix[nr_dev]) == 2)
3123 && (get_option(&str, &amplifier[nr_dev])));
3124
3125 nr_dev++;
3126 return 1;
3127 }
3128
3129 __setup("es1371=", es1371_setup);
3130
3131 #endif /* MODULE */
Linux kernel - Deliverables
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