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[PATCH] OSS: Use ARRAY_SIZE macro when appropriate (2)
[deliverable/linux.git] / sound / oss / swarm_cs4297a.c
1 /*******************************************************************************
2 *
3 * "swarm_cs4297a.c" -- Cirrus Logic-Crystal CS4297a linux audio driver.
4 *
5 * Copyright (C) 2001 Broadcom Corporation.
6 * Copyright (C) 2000,2001 Cirrus Logic Corp.
7 * -- adapted from drivers by Thomas Sailer,
8 * -- but don't bug him; Problems should go to:
9 * -- tom woller (twoller@crystal.cirrus.com) or
10 * (audio@crystal.cirrus.com).
11 * -- adapted from cs4281 PCI driver for cs4297a on
12 * BCM1250 Synchronous Serial interface
13 * (Kip Walker, Broadcom Corp.)
14 * Copyright (C) 2004 Maciej W. Rozycki
15 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 * Module command line parameters:
32 * none
33 *
34 * Supported devices:
35 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
36 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
37 * /dev/midi simple MIDI UART interface, no ioctl
38 *
39 * Modification History
40 * 08/20/00 trw - silence and no stopping DAC until release
41 * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
42 * 09/18/00 trw - added 16bit only record with conversion
43 * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
44 * capture/playback rates)
45 * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
46 * libOSSm.so)
47 * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
48 * 11/03/00 trw - fixed interrupt loss/stutter, added debug.
49 * 11/10/00 bkz - added __devinit to cs4297a_hw_init()
50 * 11/10/00 trw - fixed SMP and capture spinlock hang.
51 * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
52 * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
53 * 12/08/00 trw - added PM support.
54 * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
55 * (RH/Dell base), 2.2.18, 2.2.12. cleaned up code mods by ident.
56 * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
57 * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
58 * defaultorder-100 as power of 2 for the buffer size. example:
59 * 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
60 *
61 *******************************************************************************/
62
63 #include <linux/list.h>
64 #include <linux/module.h>
65 #include <linux/string.h>
66 #include <linux/ioport.h>
67 #include <linux/sched.h>
68 #include <linux/delay.h>
69 #include <linux/sound.h>
70 #include <linux/slab.h>
71 #include <linux/soundcard.h>
72 #include <linux/ac97_codec.h>
73 #include <linux/pci.h>
74 #include <linux/bitops.h>
75 #include <linux/interrupt.h>
76 #include <linux/init.h>
77 #include <linux/poll.h>
78 #include <linux/smp_lock.h>
79 #include <linux/mutex.h>
80 #include <linux/kernel.h>
81
82 #include <asm/byteorder.h>
83 #include <asm/dma.h>
84 #include <asm/io.h>
85 #include <asm/uaccess.h>
86
87 #include <asm/sibyte/sb1250_regs.h>
88 #include <asm/sibyte/sb1250_int.h>
89 #include <asm/sibyte/sb1250_dma.h>
90 #include <asm/sibyte/sb1250_scd.h>
91 #include <asm/sibyte/sb1250_syncser.h>
92 #include <asm/sibyte/sb1250_mac.h>
93 #include <asm/sibyte/sb1250.h>
94
95 struct cs4297a_state;
96
97 static void stop_dac(struct cs4297a_state *s);
98 static void stop_adc(struct cs4297a_state *s);
99 static void start_dac(struct cs4297a_state *s);
100 static void start_adc(struct cs4297a_state *s);
101 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
102
103 // ---------------------------------------------------------------------
104
105 #define CS4297a_MAGIC 0xf00beef1
106
107 // buffer order determines the size of the dma buffer for the driver.
108 // under Linux, a smaller buffer allows more responsiveness from many of the
109 // applications (e.g. games). A larger buffer allows some of the apps (esound)
110 // to not underrun the dma buffer as easily. As default, use 32k (order=3)
111 // rather than 64k as some of the games work more responsively.
112 // log base 2( buff sz = 32k).
113
114 //static unsigned long defaultorder = 3;
115 //MODULE_PARM(defaultorder, "i");
116
117 //
118 // Turn on/off debugging compilation by commenting out "#define CSDEBUG"
119 //
120 #define CSDEBUG 0
121 #if CSDEBUG
122 #define CSDEBUG_INTERFACE 1
123 #else
124 #undef CSDEBUG_INTERFACE
125 #endif
126 //
127 // cs_debugmask areas
128 //
129 #define CS_INIT 0x00000001 // initialization and probe functions
130 #define CS_ERROR 0x00000002 // tmp debugging bit placeholder
131 #define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other)
132 #define CS_FUNCTION 0x00000008 // enter/leave functions
133 #define CS_WAVE_WRITE 0x00000010 // write information for wave
134 #define CS_WAVE_READ 0x00000020 // read information for wave
135 #define CS_AC97 0x00000040 // AC97 register access
136 #define CS_DESCR 0x00000080 // descriptor management
137 #define CS_OPEN 0x00000400 // all open functions in the driver
138 #define CS_RELEASE 0x00000800 // all release functions in the driver
139 #define CS_PARMS 0x00001000 // functional and operational parameters
140 #define CS_IOCTL 0x00002000 // ioctl (non-mixer)
141 #define CS_TMP 0x10000000 // tmp debug mask bit
142
143 //
144 // CSDEBUG is usual mode is set to 1, then use the
145 // cs_debuglevel and cs_debugmask to turn on or off debugging.
146 // Debug level of 1 has been defined to be kernel errors and info
147 // that should be printed on any released driver.
148 //
149 #if CSDEBUG
150 #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
151 #else
152 #define CS_DBGOUT(mask,level,x)
153 #endif
154
155 #if CSDEBUG
156 static unsigned long cs_debuglevel = 4; // levels range from 1-9
157 static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/;
158 module_param(cs_debuglevel, int, 0);
159 module_param(cs_debugmask, int, 0);
160 #endif
161 #define CS_TRUE 1
162 #define CS_FALSE 0
163
164 #define CS_TYPE_ADC 0
165 #define CS_TYPE_DAC 1
166
167 #define SER_BASE (A_SER_BASE_1 + KSEG1)
168 #define SS_CSR(t) (SER_BASE+t)
169 #define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8))
170 #define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8))
171
172 #define FRAME_BYTES 32
173 #define FRAME_SAMPLE_BYTES 4
174
175 /* Should this be variable? */
176 #define SAMPLE_BUF_SIZE (16*1024)
177 #define SAMPLE_FRAME_COUNT (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES)
178 /* The driver can explode/shrink the frames to/from a smaller sample
179 buffer */
180 #define DMA_BLOAT_FACTOR 1
181 #define DMA_DESCR (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR)
182 #define DMA_BUF_SIZE (DMA_DESCR * FRAME_BYTES)
183
184 /* Use the maxmium count (255 == 5.1 ms between interrupts) */
185 #define DMA_INT_CNT ((1 << S_DMA_INT_PKTCNT) - 1)
186
187 /* Figure this out: how many TX DMAs ahead to schedule a reg access */
188 #define REG_LATENCY 150
189
190 #define FRAME_TX_US 20
191
192 #define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz)
193
194 static const char invalid_magic[] =
195 KERN_CRIT "cs4297a: invalid magic value\n";
196
197 #define VALIDATE_STATE(s) \
198 ({ \
199 if (!(s) || (s)->magic != CS4297a_MAGIC) { \
200 printk(invalid_magic); \
201 return -ENXIO; \
202 } \
203 })
204
205 struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs };
206
207 typedef struct serdma_descr_s {
208 u64 descr_a;
209 u64 descr_b;
210 } serdma_descr_t;
211
212 typedef unsigned long paddr_t;
213
214 typedef struct serdma_s {
215 unsigned ringsz;
216 serdma_descr_t *descrtab;
217 serdma_descr_t *descrtab_end;
218 paddr_t descrtab_phys;
219
220 serdma_descr_t *descr_add;
221 serdma_descr_t *descr_rem;
222
223 u64 *dma_buf; // buffer for DMA contents (frames)
224 paddr_t dma_buf_phys;
225 u16 *sample_buf; // tmp buffer for sample conversions
226 u16 *sb_swptr;
227 u16 *sb_hwptr;
228 u16 *sb_end;
229
230 dma_addr_t dmaaddr;
231 // unsigned buforder; // Log base 2 of 'dma_buf' size in bytes..
232 unsigned numfrag; // # of 'fragments' in the buffer.
233 unsigned fragshift; // Log base 2 of fragment size.
234 unsigned hwptr, swptr;
235 unsigned total_bytes; // # bytes process since open.
236 unsigned blocks; // last returned blocks value GETOPTR
237 unsigned wakeup; // interrupt occurred on block
238 int count;
239 unsigned underrun; // underrun flag
240 unsigned error; // over/underrun
241 wait_queue_head_t wait;
242 wait_queue_head_t reg_wait;
243 // redundant, but makes calculations easier
244 unsigned fragsize; // 2**fragshift..
245 unsigned sbufsz; // 2**buforder.
246 unsigned fragsamples;
247 // OSS stuff
248 unsigned mapped:1; // Buffer mapped in cs4297a_mmap()?
249 unsigned ready:1; // prog_dmabuf_dac()/adc() successful?
250 unsigned endcleared:1;
251 unsigned type:1; // adc or dac buffer (CS_TYPE_XXX)
252 unsigned ossfragshift;
253 int ossmaxfrags;
254 unsigned subdivision;
255 } serdma_t;
256
257 struct cs4297a_state {
258 // magic
259 unsigned int magic;
260
261 struct list_head list;
262
263 // soundcore stuff
264 int dev_audio;
265 int dev_mixer;
266
267 // hardware resources
268 unsigned int irq;
269
270 struct {
271 unsigned int rx_ovrrn; /* FIFO */
272 unsigned int rx_overflow; /* staging buffer */
273 unsigned int tx_underrun;
274 unsigned int rx_bad;
275 unsigned int rx_good;
276 } stats;
277
278 // mixer registers
279 struct {
280 unsigned short vol[10];
281 unsigned int recsrc;
282 unsigned int modcnt;
283 unsigned short micpreamp;
284 } mix;
285
286 // wave stuff
287 struct properties {
288 unsigned fmt;
289 unsigned fmt_original; // original requested format
290 unsigned channels;
291 unsigned rate;
292 } prop_dac, prop_adc;
293 unsigned conversion:1; // conversion from 16 to 8 bit in progress
294 unsigned ena;
295 spinlock_t lock;
296 struct mutex open_mutex;
297 struct mutex open_sem_adc;
298 struct mutex open_sem_dac;
299 mode_t open_mode;
300 wait_queue_head_t open_wait;
301 wait_queue_head_t open_wait_adc;
302 wait_queue_head_t open_wait_dac;
303
304 dma_addr_t dmaaddr_sample_buf;
305 unsigned buforder_sample_buf; // Log base 2 of 'dma_buf' size in bytes..
306
307 serdma_t dma_dac, dma_adc;
308
309 volatile u16 read_value;
310 volatile u16 read_reg;
311 volatile u64 reg_request;
312 };
313
314 #if 1
315 #define prog_codec(a,b)
316 #define dealloc_dmabuf(a,b);
317 #endif
318
319 static int prog_dmabuf_adc(struct cs4297a_state *s)
320 {
321 s->dma_adc.ready = 1;
322 return 0;
323 }
324
325
326 static int prog_dmabuf_dac(struct cs4297a_state *s)
327 {
328 s->dma_dac.ready = 1;
329 return 0;
330 }
331
332 static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
333 unsigned len, unsigned char c)
334 {
335 if (bptr + len > bsize) {
336 unsigned x = bsize - bptr;
337 memset(((char *) buf) + bptr, c, x);
338 bptr = 0;
339 len -= x;
340 }
341 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
342 "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n",
343 (unsigned)c, (unsigned)((char *) buf) + bptr, len));
344 memset(((char *) buf) + bptr, c, len);
345 }
346
347 #if CSDEBUG
348
349 // DEBUG ROUTINES
350
351 #define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int)
352 #define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int)
353 #define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int)
354 #define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int)
355
356 static void cs_printioctl(unsigned int x)
357 {
358 unsigned int i;
359 unsigned char vidx;
360 // Index of mixtable1[] member is Device ID
361 // and must be <= SOUND_MIXER_NRDEVICES.
362 // Value of array member is index into s->mix.vol[]
363 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
364 [SOUND_MIXER_PCM] = 1, // voice
365 [SOUND_MIXER_LINE1] = 2, // AUX
366 [SOUND_MIXER_CD] = 3, // CD
367 [SOUND_MIXER_LINE] = 4, // Line
368 [SOUND_MIXER_SYNTH] = 5, // FM
369 [SOUND_MIXER_MIC] = 6, // Mic
370 [SOUND_MIXER_SPEAKER] = 7, // Speaker
371 [SOUND_MIXER_RECLEV] = 8, // Recording level
372 [SOUND_MIXER_VOLUME] = 9 // Master Volume
373 };
374
375 switch (x) {
376 case SOUND_MIXER_CS_GETDBGMASK:
377 CS_DBGOUT(CS_IOCTL, 4,
378 printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
379 break;
380 case SOUND_MIXER_CS_GETDBGLEVEL:
381 CS_DBGOUT(CS_IOCTL, 4,
382 printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
383 break;
384 case SOUND_MIXER_CS_SETDBGMASK:
385 CS_DBGOUT(CS_IOCTL, 4,
386 printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
387 break;
388 case SOUND_MIXER_CS_SETDBGLEVEL:
389 CS_DBGOUT(CS_IOCTL, 4,
390 printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
391 break;
392 case OSS_GETVERSION:
393 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
394 break;
395 case SNDCTL_DSP_SYNC:
396 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
397 break;
398 case SNDCTL_DSP_SETDUPLEX:
399 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
400 break;
401 case SNDCTL_DSP_GETCAPS:
402 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
403 break;
404 case SNDCTL_DSP_RESET:
405 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
406 break;
407 case SNDCTL_DSP_SPEED:
408 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
409 break;
410 case SNDCTL_DSP_STEREO:
411 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
412 break;
413 case SNDCTL_DSP_CHANNELS:
414 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
415 break;
416 case SNDCTL_DSP_GETFMTS:
417 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
418 break;
419 case SNDCTL_DSP_SETFMT:
420 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
421 break;
422 case SNDCTL_DSP_POST:
423 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
424 break;
425 case SNDCTL_DSP_GETTRIGGER:
426 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
427 break;
428 case SNDCTL_DSP_SETTRIGGER:
429 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
430 break;
431 case SNDCTL_DSP_GETOSPACE:
432 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
433 break;
434 case SNDCTL_DSP_GETISPACE:
435 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
436 break;
437 case SNDCTL_DSP_NONBLOCK:
438 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
439 break;
440 case SNDCTL_DSP_GETODELAY:
441 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
442 break;
443 case SNDCTL_DSP_GETIPTR:
444 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
445 break;
446 case SNDCTL_DSP_GETOPTR:
447 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
448 break;
449 case SNDCTL_DSP_GETBLKSIZE:
450 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
451 break;
452 case SNDCTL_DSP_SETFRAGMENT:
453 CS_DBGOUT(CS_IOCTL, 4,
454 printk("SNDCTL_DSP_SETFRAGMENT:\n"));
455 break;
456 case SNDCTL_DSP_SUBDIVIDE:
457 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
458 break;
459 case SOUND_PCM_READ_RATE:
460 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
461 break;
462 case SOUND_PCM_READ_CHANNELS:
463 CS_DBGOUT(CS_IOCTL, 4,
464 printk("SOUND_PCM_READ_CHANNELS:\n"));
465 break;
466 case SOUND_PCM_READ_BITS:
467 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
468 break;
469 case SOUND_PCM_WRITE_FILTER:
470 CS_DBGOUT(CS_IOCTL, 4,
471 printk("SOUND_PCM_WRITE_FILTER:\n"));
472 break;
473 case SNDCTL_DSP_SETSYNCRO:
474 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
475 break;
476 case SOUND_PCM_READ_FILTER:
477 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
478 break;
479 case SOUND_MIXER_PRIVATE1:
480 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
481 break;
482 case SOUND_MIXER_PRIVATE2:
483 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
484 break;
485 case SOUND_MIXER_PRIVATE3:
486 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
487 break;
488 case SOUND_MIXER_PRIVATE4:
489 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
490 break;
491 case SOUND_MIXER_PRIVATE5:
492 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
493 break;
494 case SOUND_MIXER_INFO:
495 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
496 break;
497 case SOUND_OLD_MIXER_INFO:
498 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
499 break;
500
501 default:
502 switch (_IOC_NR(x)) {
503 case SOUND_MIXER_VOLUME:
504 CS_DBGOUT(CS_IOCTL, 4,
505 printk("SOUND_MIXER_VOLUME:\n"));
506 break;
507 case SOUND_MIXER_SPEAKER:
508 CS_DBGOUT(CS_IOCTL, 4,
509 printk("SOUND_MIXER_SPEAKER:\n"));
510 break;
511 case SOUND_MIXER_RECLEV:
512 CS_DBGOUT(CS_IOCTL, 4,
513 printk("SOUND_MIXER_RECLEV:\n"));
514 break;
515 case SOUND_MIXER_MIC:
516 CS_DBGOUT(CS_IOCTL, 4,
517 printk("SOUND_MIXER_MIC:\n"));
518 break;
519 case SOUND_MIXER_SYNTH:
520 CS_DBGOUT(CS_IOCTL, 4,
521 printk("SOUND_MIXER_SYNTH:\n"));
522 break;
523 case SOUND_MIXER_RECSRC:
524 CS_DBGOUT(CS_IOCTL, 4,
525 printk("SOUND_MIXER_RECSRC:\n"));
526 break;
527 case SOUND_MIXER_DEVMASK:
528 CS_DBGOUT(CS_IOCTL, 4,
529 printk("SOUND_MIXER_DEVMASK:\n"));
530 break;
531 case SOUND_MIXER_RECMASK:
532 CS_DBGOUT(CS_IOCTL, 4,
533 printk("SOUND_MIXER_RECMASK:\n"));
534 break;
535 case SOUND_MIXER_STEREODEVS:
536 CS_DBGOUT(CS_IOCTL, 4,
537 printk("SOUND_MIXER_STEREODEVS:\n"));
538 break;
539 case SOUND_MIXER_CAPS:
540 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
541 break;
542 default:
543 i = _IOC_NR(x);
544 if (i >= SOUND_MIXER_NRDEVICES
545 || !(vidx = mixtable1[i])) {
546 CS_DBGOUT(CS_IOCTL, 4, printk
547 ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
548 x, i));
549 } else {
550 CS_DBGOUT(CS_IOCTL, 4, printk
551 ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
552 x, i));
553 }
554 break;
555 }
556 }
557 }
558 #endif
559
560
561 static int ser_init(struct cs4297a_state *s)
562 {
563 int i;
564
565 CS_DBGOUT(CS_INIT, 2,
566 printk(KERN_INFO "cs4297a: Setting up serial parameters\n"));
567
568 __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
569
570 __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
571 __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ));
572 __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ));
573
574 __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH));
575 __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH));
576 __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH));
577
578 /* This looks good from experimentation */
579 __raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT |
580 M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE),
581 SS_CSR(R_SER_LINE_MODE));
582
583 /* This looks good from experimentation */
584 __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
585 SS_TXTBL(0));
586 __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
587 SS_TXTBL(1));
588 __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
589 SS_TXTBL(2));
590 __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE |
591 M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3));
592
593 __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
594 SS_RXTBL(0));
595 __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
596 SS_RXTBL(1));
597 __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
598 SS_RXTBL(2));
599 __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE |
600 M_SYNCSER_SEQ_LAST, SS_RXTBL(3));
601
602 for (i=4; i<16; i++) {
603 /* Just in case... */
604 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i));
605 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i));
606 }
607
608 return 0;
609 }
610
611 static int init_serdma(serdma_t *dma)
612 {
613 CS_DBGOUT(CS_INIT, 2,
614 printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n",
615 DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE));
616
617 /* Descriptors */
618 dma->ringsz = DMA_DESCR;
619 dma->descrtab = kmalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL);
620 if (!dma->descrtab) {
621 printk(KERN_ERR "cs4297a: kmalloc descrtab failed\n");
622 return -1;
623 }
624 memset(dma->descrtab, 0, dma->ringsz * sizeof(serdma_descr_t));
625 dma->descrtab_end = dma->descrtab + dma->ringsz;
626 /* XXX bloddy mess, use proper DMA API here ... */
627 dma->descrtab_phys = CPHYSADDR((long)dma->descrtab);
628 dma->descr_add = dma->descr_rem = dma->descrtab;
629
630 /* Frame buffer area */
631 dma->dma_buf = kmalloc(DMA_BUF_SIZE, GFP_KERNEL);
632 if (!dma->dma_buf) {
633 printk(KERN_ERR "cs4297a: kmalloc dma_buf failed\n");
634 kfree(dma->descrtab);
635 return -1;
636 }
637 memset(dma->dma_buf, 0, DMA_BUF_SIZE);
638 dma->dma_buf_phys = CPHYSADDR((long)dma->dma_buf);
639
640 /* Samples buffer area */
641 dma->sbufsz = SAMPLE_BUF_SIZE;
642 dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL);
643 if (!dma->sample_buf) {
644 printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n");
645 kfree(dma->descrtab);
646 kfree(dma->dma_buf);
647 return -1;
648 }
649 dma->sb_swptr = dma->sb_hwptr = dma->sample_buf;
650 dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz);
651 dma->fragsize = dma->sbufsz >> 1;
652
653 CS_DBGOUT(CS_INIT, 4,
654 printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n",
655 (int)dma->descrtab, (int)dma->dma_buf,
656 (int)dma->sample_buf));
657
658 return 0;
659 }
660
661 static int dma_init(struct cs4297a_state *s)
662 {
663 int i;
664
665 CS_DBGOUT(CS_INIT, 2,
666 printk(KERN_INFO "cs4297a: Setting up DMA\n"));
667
668 if (init_serdma(&s->dma_adc) ||
669 init_serdma(&s->dma_dac))
670 return -1;
671
672 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
673 __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
674 panic("DMA state corrupted?!");
675 }
676
677 /* Initialize now - the descr/buffer pairings will never
678 change... */
679 for (i=0; i<DMA_DESCR; i++) {
680 s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) |
681 (s->dma_dac.dma_buf_phys + i*FRAME_BYTES);
682 s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES);
683 s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) |
684 (s->dma_adc.dma_buf_phys + i*FRAME_BYTES);
685 s->dma_adc.descrtab[i].descr_b = 0;
686 }
687
688 __raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) |
689 V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN),
690 SS_CSR(R_SER_DMA_CONFIG0_RX));
691 __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
692 __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
693
694 __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
695 __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
696 __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
697
698 /* Prep the receive DMA descriptor ring */
699 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
700
701 __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
702
703 __raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT),
704 SS_CSR(R_SER_INT_MASK));
705
706 /* Enable the rx/tx; let the codec warm up to the sync and
707 start sending good frames before the receive FIFO is
708 enabled */
709 __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
710 udelay(1000);
711 __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
712
713 /* XXXKW is this magic? (the "1" part) */
714 while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
715 ;
716
717 CS_DBGOUT(CS_INIT, 4,
718 printk(KERN_INFO "cs4297a: status: %08x\n",
719 (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
720
721 return 0;
722 }
723
724 static int serdma_reg_access(struct cs4297a_state *s, u64 data)
725 {
726 serdma_t *d = &s->dma_dac;
727 u64 *data_p;
728 unsigned swptr;
729 unsigned long flags;
730 serdma_descr_t *descr;
731
732 if (s->reg_request) {
733 printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n");
734 return -1;
735 }
736
737 if (s->ena & FMODE_WRITE) {
738 /* Since a writer has the DSP open, we have to mux the
739 request in */
740 s->reg_request = data;
741 interruptible_sleep_on(&s->dma_dac.reg_wait);
742 /* XXXKW how can I deal with the starvation case where
743 the opener isn't writing? */
744 } else {
745 /* Be safe when changing ring pointers */
746 spin_lock_irqsave(&s->lock, flags);
747 if (d->hwptr != d->swptr) {
748 printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n",
749 d->hwptr, d->swptr);
750 spin_unlock_irqrestore(&s->lock, flags);
751 return -1;
752 }
753 swptr = d->swptr;
754 d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz;
755 spin_unlock_irqrestore(&s->lock, flags);
756
757 descr = &d->descrtab[swptr];
758 data_p = &d->dma_buf[swptr * 4];
759 *data_p = cpu_to_be64(data);
760 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
761 CS_DBGOUT(CS_DESCR, 4,
762 printk(KERN_INFO "cs4297a: add_tx %p (%x -> %x)\n",
763 data_p, swptr, d->hwptr));
764 }
765
766 CS_DBGOUT(CS_FUNCTION, 6,
767 printk(KERN_INFO "cs4297a: serdma_reg_access()-\n"));
768
769 return 0;
770 }
771
772 //****************************************************************************
773 // "cs4297a_read_ac97" -- Reads an AC97 register
774 //****************************************************************************
775 static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset,
776 u32 * value)
777 {
778 CS_DBGOUT(CS_AC97, 1,
779 printk(KERN_INFO "cs4297a: read reg %2x\n", offset));
780 if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40)))
781 return -1;
782
783 interruptible_sleep_on(&s->dma_adc.reg_wait);
784 *value = s->read_value;
785 CS_DBGOUT(CS_AC97, 2,
786 printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value));
787
788 return 0;
789 }
790
791
792 //****************************************************************************
793 // "cs4297a_write_ac97()"-- writes an AC97 register
794 //****************************************************************************
795 static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset,
796 u32 value)
797 {
798 CS_DBGOUT(CS_AC97, 1,
799 printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value));
800 return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12)));
801 }
802
803 static void stop_dac(struct cs4297a_state *s)
804 {
805 unsigned long flags;
806
807 CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n"));
808 spin_lock_irqsave(&s->lock, flags);
809 s->ena &= ~FMODE_WRITE;
810 #if 0
811 /* XXXKW what do I really want here? My theory for now is
812 that I just flip the "ena" bit, and the interrupt handler
813 will stop processing the xmit channel */
814 __raw_writeq((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0,
815 SS_CSR(R_SER_DMA_ENABLE));
816 #endif
817
818 spin_unlock_irqrestore(&s->lock, flags);
819 }
820
821
822 static void start_dac(struct cs4297a_state *s)
823 {
824 unsigned long flags;
825
826 CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n"));
827 spin_lock_irqsave(&s->lock, flags);
828 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
829 (s->dma_dac.count > 0
830 && s->dma_dac.ready))) {
831 s->ena |= FMODE_WRITE;
832 /* XXXKW what do I really want here? My theory for
833 now is that I just flip the "ena" bit, and the
834 interrupt handler will start processing the xmit
835 channel */
836
837 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
838 "cs4297a: start_dac(): start dma\n"));
839
840 }
841 spin_unlock_irqrestore(&s->lock, flags);
842 CS_DBGOUT(CS_FUNCTION, 3,
843 printk(KERN_INFO "cs4297a: start_dac()-\n"));
844 }
845
846
847 static void stop_adc(struct cs4297a_state *s)
848 {
849 unsigned long flags;
850
851 CS_DBGOUT(CS_FUNCTION, 3,
852 printk(KERN_INFO "cs4297a: stop_adc()+\n"));
853
854 spin_lock_irqsave(&s->lock, flags);
855 s->ena &= ~FMODE_READ;
856
857 if (s->conversion == 1) {
858 s->conversion = 0;
859 s->prop_adc.fmt = s->prop_adc.fmt_original;
860 }
861 /* Nothing to do really, I need to keep the DMA going
862 XXXKW when do I get here, and is there more I should do? */
863 spin_unlock_irqrestore(&s->lock, flags);
864 CS_DBGOUT(CS_FUNCTION, 3,
865 printk(KERN_INFO "cs4297a: stop_adc()-\n"));
866 }
867
868
869 static void start_adc(struct cs4297a_state *s)
870 {
871 unsigned long flags;
872
873 CS_DBGOUT(CS_FUNCTION, 2,
874 printk(KERN_INFO "cs4297a: start_adc()+\n"));
875
876 if (!(s->ena & FMODE_READ) &&
877 (s->dma_adc.mapped || s->dma_adc.count <=
878 (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize))
879 && s->dma_adc.ready) {
880 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
881 //
882 // now only use 16 bit capture, due to truncation issue
883 // in the chip, noticable distortion occurs.
884 // allocate buffer and then convert from 16 bit to
885 // 8 bit for the user buffer.
886 //
887 s->prop_adc.fmt_original = s->prop_adc.fmt;
888 if (s->prop_adc.fmt & AFMT_S8) {
889 s->prop_adc.fmt &= ~AFMT_S8;
890 s->prop_adc.fmt |= AFMT_S16_LE;
891 }
892 if (s->prop_adc.fmt & AFMT_U8) {
893 s->prop_adc.fmt &= ~AFMT_U8;
894 s->prop_adc.fmt |= AFMT_U16_LE;
895 }
896 //
897 // prog_dmabuf_adc performs a stop_adc() but that is
898 // ok since we really haven't started the DMA yet.
899 //
900 prog_codec(s, CS_TYPE_ADC);
901
902 prog_dmabuf_adc(s);
903 s->conversion = 1;
904 }
905 spin_lock_irqsave(&s->lock, flags);
906 s->ena |= FMODE_READ;
907 /* Nothing to do really, I am probably already
908 DMAing... XXXKW when do I get here, and is there
909 more I should do? */
910 spin_unlock_irqrestore(&s->lock, flags);
911
912 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
913 "cs4297a: start_adc(): start adc\n"));
914 }
915 CS_DBGOUT(CS_FUNCTION, 2,
916 printk(KERN_INFO "cs4297a: start_adc()-\n"));
917
918 }
919
920
921 // call with spinlock held!
922 static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag)
923 {
924 int good_diff, diff, diff2;
925 u64 *data_p, data;
926 u32 *s_ptr;
927 unsigned hwptr;
928 u32 status;
929 serdma_t *d;
930 serdma_descr_t *descr;
931
932 // update ADC pointer
933 status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0;
934
935 if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) {
936 d = &s->dma_adc;
937 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
938 d->descrtab_phys) / sizeof(serdma_descr_t));
939
940 if (s->ena & FMODE_READ) {
941 CS_DBGOUT(CS_FUNCTION, 2,
942 printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n",
943 d->swptr, d->hwptr, hwptr, intflag));
944 /* Number of DMA buffers available for software: */
945 diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
946 d->hwptr = hwptr;
947 good_diff = 0;
948 s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]);
949 descr = &d->descrtab[d->swptr];
950 while (diff2--) {
951 u64 data = be64_to_cpu(*(u64 *)s_ptr);
952 u64 descr_a;
953 u16 left, right;
954 descr_a = descr->descr_a;
955 descr->descr_a &= ~M_DMA_SERRX_SOP;
956 if ((descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)s_ptr)) {
957 printk(KERN_ERR "cs4297a: RX Bad address (read)\n");
958 }
959 if (((data & 0x9800000000000000) != 0x9800000000000000) ||
960 (!(descr_a & M_DMA_SERRX_SOP)) ||
961 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
962 s->stats.rx_bad++;
963 printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n");
964 continue;
965 }
966 s->stats.rx_good++;
967 if ((data >> 61) == 7) {
968 s->read_value = (data >> 12) & 0xffff;
969 s->read_reg = (data >> 40) & 0x7f;
970 wake_up(&d->reg_wait);
971 }
972 if (d->count && (d->sb_hwptr == d->sb_swptr)) {
973 s->stats.rx_overflow++;
974 printk(KERN_DEBUG "cs4297a: RX overflow\n");
975 continue;
976 }
977 good_diff++;
978 left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) |
979 ((be32_to_cpu(s_ptr[2]) >> 24) & 0xff);
980 right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff;
981 *d->sb_hwptr++ = cpu_to_be16(left);
982 *d->sb_hwptr++ = cpu_to_be16(right);
983 if (d->sb_hwptr == d->sb_end)
984 d->sb_hwptr = d->sample_buf;
985 descr++;
986 if (descr == d->descrtab_end) {
987 descr = d->descrtab;
988 s_ptr = (u32 *)s->dma_adc.dma_buf;
989 } else {
990 s_ptr += 8;
991 }
992 }
993 d->total_bytes += good_diff * FRAME_SAMPLE_BYTES;
994 d->count += good_diff * FRAME_SAMPLE_BYTES;
995 if (d->count > d->sbufsz) {
996 printk(KERN_ERR "cs4297a: bogus receive overflow!!\n");
997 }
998 d->swptr = (d->swptr + diff) % d->ringsz;
999 __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1000 if (d->mapped) {
1001 if (d->count >= (signed) d->fragsize)
1002 wake_up(&d->wait);
1003 } else {
1004 if (d->count > 0) {
1005 CS_DBGOUT(CS_WAVE_READ, 4,
1006 printk(KERN_INFO
1007 "cs4297a: update count -> %d\n", d->count));
1008 wake_up(&d->wait);
1009 }
1010 }
1011 } else {
1012 /* Receive is going even if no one is
1013 listening (for register accesses and to
1014 avoid FIFO overrun) */
1015 diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz;
1016 if (!diff) {
1017 printk(KERN_ERR "cs4297a: RX full or empty?\n");
1018 }
1019
1020 descr = &d->descrtab[d->swptr];
1021 data_p = &d->dma_buf[d->swptr*4];
1022
1023 /* Force this to happen at least once; I got
1024 here because of an interrupt, so there must
1025 be a buffer to process. */
1026 do {
1027 data = be64_to_cpu(*data_p);
1028 if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)data_p)) {
1029 printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr,
1030 (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR),
1031 (long)CPHYSADDR((long)data_p));
1032 }
1033 if (!(data & (1LL << 63)) ||
1034 !(descr->descr_a & M_DMA_SERRX_SOP) ||
1035 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
1036 s->stats.rx_bad++;
1037 printk(KERN_DEBUG "cs4297a: RX Bad attributes\n");
1038 } else {
1039 s->stats.rx_good++;
1040 if ((data >> 61) == 7) {
1041 s->read_value = (data >> 12) & 0xffff;
1042 s->read_reg = (data >> 40) & 0x7f;
1043 wake_up(&d->reg_wait);
1044 }
1045 }
1046 descr->descr_a &= ~M_DMA_SERRX_SOP;
1047 descr++;
1048 d->swptr++;
1049 data_p += 4;
1050 if (descr == d->descrtab_end) {
1051 descr = d->descrtab;
1052 d->swptr = 0;
1053 data_p = d->dma_buf;
1054 }
1055 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1056 } while (--diff);
1057 d->hwptr = hwptr;
1058
1059 CS_DBGOUT(CS_DESCR, 6,
1060 printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr));
1061 }
1062
1063 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1064 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1065 (unsigned)s, d->hwptr,
1066 d->total_bytes, d->count));
1067 }
1068
1069 /* XXXKW worry about s->reg_request -- there is a starvation
1070 case if s->ena has FMODE_WRITE on, but the client isn't
1071 doing writes */
1072
1073 // update DAC pointer
1074 //
1075 // check for end of buffer, means that we are going to wait for another interrupt
1076 // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1077 //
1078 if (s->ena & FMODE_WRITE) {
1079 serdma_t *d = &s->dma_dac;
1080 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1081 d->descrtab_phys) / sizeof(serdma_descr_t));
1082 diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
1083 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1084 "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n",
1085 d->hwptr, hwptr, d->swptr, diff, d->count));
1086 d->hwptr = hwptr;
1087 /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */
1088 d->total_bytes += diff * FRAME_SAMPLE_BYTES;
1089 if (d->mapped) {
1090 d->count += diff * FRAME_SAMPLE_BYTES;
1091 if (d->count >= d->fragsize) {
1092 d->wakeup = 1;
1093 wake_up(&d->wait);
1094 if (d->count > d->sbufsz)
1095 d->count &= d->sbufsz - 1;
1096 }
1097 } else {
1098 d->count -= diff * FRAME_SAMPLE_BYTES;
1099 if (d->count <= 0) {
1100 //
1101 // fill with silence, and do not shut down the DAC.
1102 // Continue to play silence until the _release.
1103 //
1104 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
1105 "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n",
1106 (unsigned)(s->prop_dac.fmt &
1107 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1108 (unsigned)d->dma_buf,
1109 d->ringsz));
1110 memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES);
1111 if (d->count < 0) {
1112 d->underrun = 1;
1113 s->stats.tx_underrun++;
1114 d->count = 0;
1115 CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
1116 "cs4297a: cs4297a_update_ptr(): underrun\n"));
1117 }
1118 } else if (d->count <=
1119 (signed) d->fragsize
1120 && !d->endcleared) {
1121 /* XXXKW what is this for? */
1122 clear_advance(d->dma_buf,
1123 d->sbufsz,
1124 d->swptr,
1125 d->fragsize,
1126 0);
1127 d->endcleared = 1;
1128 }
1129 if ( (d->count <= (signed) d->sbufsz/2) || intflag)
1130 {
1131 CS_DBGOUT(CS_WAVE_WRITE, 4,
1132 printk(KERN_INFO
1133 "cs4297a: update count -> %d\n", d->count));
1134 wake_up(&d->wait);
1135 }
1136 }
1137 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1138 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1139 (unsigned) s, d->hwptr,
1140 d->total_bytes, d->count));
1141 }
1142 }
1143
1144 static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd,
1145 unsigned long arg)
1146 {
1147 // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
1148 // Value of array member is recording source Device ID Mask.
1149 static const unsigned int mixer_src[8] = {
1150 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
1151 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
1152 };
1153
1154 // Index of mixtable1[] member is Device ID
1155 // and must be <= SOUND_MIXER_NRDEVICES.
1156 // Value of array member is index into s->mix.vol[]
1157 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
1158 [SOUND_MIXER_PCM] = 1, // voice
1159 [SOUND_MIXER_LINE1] = 2, // AUX
1160 [SOUND_MIXER_CD] = 3, // CD
1161 [SOUND_MIXER_LINE] = 4, // Line
1162 [SOUND_MIXER_SYNTH] = 5, // FM
1163 [SOUND_MIXER_MIC] = 6, // Mic
1164 [SOUND_MIXER_SPEAKER] = 7, // Speaker
1165 [SOUND_MIXER_RECLEV] = 8, // Recording level
1166 [SOUND_MIXER_VOLUME] = 9 // Master Volume
1167 };
1168
1169 static const unsigned mixreg[] = {
1170 AC97_PCMOUT_VOL,
1171 AC97_AUX_VOL,
1172 AC97_CD_VOL,
1173 AC97_LINEIN_VOL
1174 };
1175 unsigned char l, r, rl, rr, vidx;
1176 unsigned char attentbl[11] =
1177 { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
1178 unsigned temp1;
1179 int i, val;
1180
1181 VALIDATE_STATE(s);
1182 CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
1183 "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
1184 (unsigned) s, cmd));
1185 #if CSDEBUG
1186 cs_printioctl(cmd);
1187 #endif
1188 #if CSDEBUG_INTERFACE
1189
1190 if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
1191 (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
1192 (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
1193 (cmd == SOUND_MIXER_CS_SETDBGLEVEL))
1194 {
1195 switch (cmd) {
1196
1197 case SOUND_MIXER_CS_GETDBGMASK:
1198 return put_user(cs_debugmask,
1199 (unsigned long *) arg);
1200
1201 case SOUND_MIXER_CS_GETDBGLEVEL:
1202 return put_user(cs_debuglevel,
1203 (unsigned long *) arg);
1204
1205 case SOUND_MIXER_CS_SETDBGMASK:
1206 if (get_user(val, (unsigned long *) arg))
1207 return -EFAULT;
1208 cs_debugmask = val;
1209 return 0;
1210
1211 case SOUND_MIXER_CS_SETDBGLEVEL:
1212 if (get_user(val, (unsigned long *) arg))
1213 return -EFAULT;
1214 cs_debuglevel = val;
1215 return 0;
1216 default:
1217 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
1218 "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n"));
1219 return 0;
1220 }
1221 }
1222 #endif
1223
1224 if (cmd == SOUND_MIXER_PRIVATE1) {
1225 return -EINVAL;
1226 }
1227 if (cmd == SOUND_MIXER_PRIVATE2) {
1228 // enable/disable/query spatializer
1229 if (get_user(val, (int *) arg))
1230 return -EFAULT;
1231 if (val != -1) {
1232 temp1 = (val & 0x3f) >> 2;
1233 cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1);
1234 cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE,
1235 &temp1);
1236 cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE,
1237 temp1 | 0x2000);
1238 }
1239 cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1);
1240 return put_user((temp1 << 2) | 3, (int *) arg);
1241 }
1242 if (cmd == SOUND_MIXER_INFO) {
1243 mixer_info info;
1244 memset(&info, 0, sizeof(info));
1245 strlcpy(info.id, "CS4297a", sizeof(info.id));
1246 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1247 info.modify_counter = s->mix.modcnt;
1248 if (copy_to_user((void *) arg, &info, sizeof(info)))
1249 return -EFAULT;
1250 return 0;
1251 }
1252 if (cmd == SOUND_OLD_MIXER_INFO) {
1253 _old_mixer_info info;
1254 memset(&info, 0, sizeof(info));
1255 strlcpy(info.id, "CS4297a", sizeof(info.id));
1256 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
1257 if (copy_to_user((void *) arg, &info, sizeof(info)))
1258 return -EFAULT;
1259 return 0;
1260 }
1261 if (cmd == OSS_GETVERSION)
1262 return put_user(SOUND_VERSION, (int *) arg);
1263
1264 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1265 return -EINVAL;
1266
1267 // If ioctl has only the SIOC_READ bit(bit 31)
1268 // on, process the only-read commands.
1269 if (_SIOC_DIR(cmd) == _SIOC_READ) {
1270 switch (_IOC_NR(cmd)) {
1271 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
1272 cs4297a_read_ac97(s, AC97_RECORD_SELECT,
1273 &temp1);
1274 return put_user(mixer_src[temp1 & 7], (int *) arg);
1275
1276 case SOUND_MIXER_DEVMASK: // Arg contains a bit for each supported device
1277 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1278 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1279 (int *) arg);
1280
1281 case SOUND_MIXER_RECMASK: // Arg contains a bit for each supported recording source
1282 return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME,
1283 (int *) arg);
1284
1285 case SOUND_MIXER_STEREODEVS: // Mixer channels supporting stereo
1286 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1287 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1288 (int *) arg);
1289
1290 case SOUND_MIXER_CAPS:
1291 return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
1292
1293 default:
1294 i = _IOC_NR(cmd);
1295 if (i >= SOUND_MIXER_NRDEVICES
1296 || !(vidx = mixtable1[i]))
1297 return -EINVAL;
1298 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1299 }
1300 }
1301 // If ioctl doesn't have both the SIOC_READ and
1302 // the SIOC_WRITE bit set, return invalid.
1303 if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
1304 return -EINVAL;
1305
1306 // Increment the count of volume writes.
1307 s->mix.modcnt++;
1308
1309 // Isolate the command; it must be a write.
1310 switch (_IOC_NR(cmd)) {
1311
1312 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
1313 if (get_user(val, (int *) arg))
1314 return -EFAULT;
1315 i = hweight32(val); // i = # bits on in val.
1316 if (i != 1) // One & only 1 bit must be on.
1317 return 0;
1318 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
1319 if (val == mixer_src[i]) {
1320 temp1 = (i << 8) | i;
1321 cs4297a_write_ac97(s,
1322 AC97_RECORD_SELECT,
1323 temp1);
1324 return 0;
1325 }
1326 }
1327 return 0;
1328
1329 case SOUND_MIXER_VOLUME:
1330 if (get_user(val, (int *) arg))
1331 return -EFAULT;
1332 l = val & 0xff;
1333 if (l > 100)
1334 l = 100; // Max soundcard.h vol is 100.
1335 if (l < 6) {
1336 rl = 63;
1337 l = 0;
1338 } else
1339 rl = attentbl[(10 * l) / 100]; // Convert 0-100 vol to 63-0 atten.
1340
1341 r = (val >> 8) & 0xff;
1342 if (r > 100)
1343 r = 100; // Max right volume is 100, too
1344 if (r < 6) {
1345 rr = 63;
1346 r = 0;
1347 } else
1348 rr = attentbl[(10 * r) / 100]; // Convert volume to attenuation.
1349
1350 if ((rl > 60) && (rr > 60)) // If both l & r are 'low',
1351 temp1 = 0x8000; // turn on the mute bit.
1352 else
1353 temp1 = 0;
1354
1355 temp1 |= (rl << 8) | rr;
1356
1357 cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1);
1358 cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1);
1359
1360 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1361 s->mix.vol[8] = ((unsigned int) r << 8) | l;
1362 #else
1363 s->mix.vol[8] = val;
1364 #endif
1365 return put_user(s->mix.vol[8], (int *) arg);
1366
1367 case SOUND_MIXER_SPEAKER:
1368 if (get_user(val, (int *) arg))
1369 return -EFAULT;
1370 l = val & 0xff;
1371 if (l > 100)
1372 l = 100;
1373 if (l < 3) {
1374 rl = 0;
1375 l = 0;
1376 } else {
1377 rl = (l * 2 - 5) / 13; // Convert 0-100 range to 0-15.
1378 l = (rl * 13 + 5) / 2;
1379 }
1380
1381 if (rl < 3) {
1382 temp1 = 0x8000;
1383 rl = 0;
1384 } else
1385 temp1 = 0;
1386 rl = 15 - rl; // Convert volume to attenuation.
1387 temp1 |= rl << 1;
1388 cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1);
1389
1390 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1391 s->mix.vol[6] = l << 8;
1392 #else
1393 s->mix.vol[6] = val;
1394 #endif
1395 return put_user(s->mix.vol[6], (int *) arg);
1396
1397 case SOUND_MIXER_RECLEV:
1398 if (get_user(val, (int *) arg))
1399 return -EFAULT;
1400 l = val & 0xff;
1401 if (l > 100)
1402 l = 100;
1403 r = (val >> 8) & 0xff;
1404 if (r > 100)
1405 r = 100;
1406 rl = (l * 2 - 5) / 13; // Convert 0-100 scale to 0-15.
1407 rr = (r * 2 - 5) / 13;
1408 if (rl < 3 && rr < 3)
1409 temp1 = 0x8000;
1410 else
1411 temp1 = 0;
1412
1413 temp1 = temp1 | (rl << 8) | rr;
1414 cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1);
1415
1416 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1417 s->mix.vol[7] = ((unsigned int) r << 8) | l;
1418 #else
1419 s->mix.vol[7] = val;
1420 #endif
1421 return put_user(s->mix.vol[7], (int *) arg);
1422
1423 case SOUND_MIXER_MIC:
1424 if (get_user(val, (int *) arg))
1425 return -EFAULT;
1426 l = val & 0xff;
1427 if (l > 100)
1428 l = 100;
1429 if (l < 1) {
1430 l = 0;
1431 rl = 0;
1432 } else {
1433 rl = ((unsigned) l * 5 - 4) / 16; // Convert 0-100 range to 0-31.
1434 l = (rl * 16 + 4) / 5;
1435 }
1436 cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1);
1437 temp1 &= 0x40; // Isolate 20db gain bit.
1438 if (rl < 3) {
1439 temp1 |= 0x8000;
1440 rl = 0;
1441 }
1442 rl = 31 - rl; // Convert volume to attenuation.
1443 temp1 |= rl;
1444 cs4297a_write_ac97(s, AC97_MIC_VOL, temp1);
1445
1446 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1447 s->mix.vol[5] = val << 8;
1448 #else
1449 s->mix.vol[5] = val;
1450 #endif
1451 return put_user(s->mix.vol[5], (int *) arg);
1452
1453
1454 case SOUND_MIXER_SYNTH:
1455 if (get_user(val, (int *) arg))
1456 return -EFAULT;
1457 l = val & 0xff;
1458 if (l > 100)
1459 l = 100;
1460 if (get_user(val, (int *) arg))
1461 return -EFAULT;
1462 r = (val >> 8) & 0xff;
1463 if (r > 100)
1464 r = 100;
1465 rl = (l * 2 - 11) / 3; // Convert 0-100 range to 0-63.
1466 rr = (r * 2 - 11) / 3;
1467 if (rl < 3) // If l is low, turn on
1468 temp1 = 0x0080; // the mute bit.
1469 else
1470 temp1 = 0;
1471
1472 rl = 63 - rl; // Convert vol to attenuation.
1473 // writel(temp1 | rl, s->pBA0 + FMLVC);
1474 if (rr < 3) // If rr is low, turn on
1475 temp1 = 0x0080; // the mute bit.
1476 else
1477 temp1 = 0;
1478 rr = 63 - rr; // Convert vol to attenuation.
1479 // writel(temp1 | rr, s->pBA0 + FMRVC);
1480
1481 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1482 s->mix.vol[4] = (r << 8) | l;
1483 #else
1484 s->mix.vol[4] = val;
1485 #endif
1486 return put_user(s->mix.vol[4], (int *) arg);
1487
1488
1489 default:
1490 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1491 "cs4297a: mixer_ioctl(): default\n"));
1492
1493 i = _IOC_NR(cmd);
1494 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
1495 return -EINVAL;
1496 if (get_user(val, (int *) arg))
1497 return -EFAULT;
1498 l = val & 0xff;
1499 if (l > 100)
1500 l = 100;
1501 if (l < 1) {
1502 l = 0;
1503 rl = 31;
1504 } else
1505 rl = (attentbl[(l * 10) / 100]) >> 1;
1506
1507 r = (val >> 8) & 0xff;
1508 if (r > 100)
1509 r = 100;
1510 if (r < 1) {
1511 r = 0;
1512 rr = 31;
1513 } else
1514 rr = (attentbl[(r * 10) / 100]) >> 1;
1515 if ((rl > 30) && (rr > 30))
1516 temp1 = 0x8000;
1517 else
1518 temp1 = 0;
1519 temp1 = temp1 | (rl << 8) | rr;
1520 cs4297a_write_ac97(s, mixreg[vidx - 1], temp1);
1521
1522 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1523 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
1524 #else
1525 s->mix.vol[vidx - 1] = val;
1526 #endif
1527 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1528 }
1529 }
1530
1531
1532 // ---------------------------------------------------------------------
1533
1534 static int cs4297a_open_mixdev(struct inode *inode, struct file *file)
1535 {
1536 int minor = iminor(inode);
1537 struct cs4297a_state *s=NULL;
1538 struct list_head *entry;
1539
1540 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1541 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n"));
1542
1543 list_for_each(entry, &cs4297a_devs)
1544 {
1545 s = list_entry(entry, struct cs4297a_state, list);
1546 if(s->dev_mixer == minor)
1547 break;
1548 }
1549 if (!s)
1550 {
1551 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
1552 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n"));
1553 return -ENODEV;
1554 }
1555 VALIDATE_STATE(s);
1556 file->private_data = s;
1557
1558 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1559 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n"));
1560
1561 return nonseekable_open(inode, file);
1562 }
1563
1564
1565 static int cs4297a_release_mixdev(struct inode *inode, struct file *file)
1566 {
1567 struct cs4297a_state *s =
1568 (struct cs4297a_state *) file->private_data;
1569
1570 VALIDATE_STATE(s);
1571 return 0;
1572 }
1573
1574
1575 static int cs4297a_ioctl_mixdev(struct inode *inode, struct file *file,
1576 unsigned int cmd, unsigned long arg)
1577 {
1578 return mixer_ioctl((struct cs4297a_state *) file->private_data, cmd,
1579 arg);
1580 }
1581
1582
1583 // ******************************************************************************************
1584 // Mixer file operations struct.
1585 // ******************************************************************************************
1586 static /*const */ struct file_operations cs4297a_mixer_fops = {
1587 .owner = THIS_MODULE,
1588 .llseek = no_llseek,
1589 .ioctl = cs4297a_ioctl_mixdev,
1590 .open = cs4297a_open_mixdev,
1591 .release = cs4297a_release_mixdev,
1592 };
1593
1594 // ---------------------------------------------------------------------
1595
1596
1597 static int drain_adc(struct cs4297a_state *s, int nonblock)
1598 {
1599 /* This routine serves no purpose currently - any samples
1600 sitting in the receive queue will just be processed by the
1601 background consumer. This would be different if DMA
1602 actually stopped when there were no clients. */
1603 return 0;
1604 }
1605
1606 static int drain_dac(struct cs4297a_state *s, int nonblock)
1607 {
1608 DECLARE_WAITQUEUE(wait, current);
1609 unsigned long flags;
1610 unsigned hwptr;
1611 unsigned tmo;
1612 int count;
1613
1614 if (s->dma_dac.mapped)
1615 return 0;
1616 if (nonblock)
1617 return -EBUSY;
1618 add_wait_queue(&s->dma_dac.wait, &wait);
1619 while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ||
1620 (s->dma_dac.count > 0)) {
1621 if (!signal_pending(current)) {
1622 set_current_state(TASK_INTERRUPTIBLE);
1623 /* XXXKW is this calculation working? */
1624 tmo = ((count * FRAME_TX_US) * HZ) / 1000000;
1625 schedule_timeout(tmo + 1);
1626 } else {
1627 /* XXXKW do I care if there is a signal pending? */
1628 }
1629 }
1630 spin_lock_irqsave(&s->lock, flags);
1631 /* Reset the bookkeeping */
1632 hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1633 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
1634 s->dma_dac.hwptr = s->dma_dac.swptr = hwptr;
1635 spin_unlock_irqrestore(&s->lock, flags);
1636 remove_wait_queue(&s->dma_dac.wait, &wait);
1637 current->state = TASK_RUNNING;
1638 return 0;
1639 }
1640
1641
1642 // ---------------------------------------------------------------------
1643
1644 static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count,
1645 loff_t * ppos)
1646 {
1647 struct cs4297a_state *s =
1648 (struct cs4297a_state *) file->private_data;
1649 ssize_t ret;
1650 unsigned long flags;
1651 int cnt, count_fr, cnt_by;
1652 unsigned copied = 0;
1653
1654 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1655 printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count));
1656
1657 VALIDATE_STATE(s);
1658 if (s->dma_adc.mapped)
1659 return -ENXIO;
1660 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1661 return ret;
1662 if (!access_ok(VERIFY_WRITE, buffer, count))
1663 return -EFAULT;
1664 ret = 0;
1665 //
1666 // "count" is the amount of bytes to read (from app), is decremented each loop
1667 // by the amount of bytes that have been returned to the user buffer.
1668 // "cnt" is the running total of each read from the buffer (changes each loop)
1669 // "buffer" points to the app's buffer
1670 // "ret" keeps a running total of the amount of bytes that have been copied
1671 // to the user buffer.
1672 // "copied" is the total bytes copied into the user buffer for each loop.
1673 //
1674 while (count > 0) {
1675 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1676 "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
1677 count, s->dma_adc.count,
1678 s->dma_adc.swptr, s->dma_adc.hwptr));
1679 spin_lock_irqsave(&s->lock, flags);
1680
1681 /* cnt will be the number of available samples (16-bit
1682 stereo); it starts out as the maxmimum consequetive
1683 samples */
1684 cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2;
1685 count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES;
1686
1687 // dma_adc.count is the current total bytes that have not been read.
1688 // if the amount of unread bytes from the current sw pointer to the
1689 // end of the buffer is greater than the current total bytes that
1690 // have not been read, then set the "cnt" (unread bytes) to the
1691 // amount of unread bytes.
1692
1693 if (count_fr < cnt)
1694 cnt = count_fr;
1695 cnt_by = cnt * FRAME_SAMPLE_BYTES;
1696 spin_unlock_irqrestore(&s->lock, flags);
1697 //
1698 // if we are converting from 8/16 then we need to copy
1699 // twice the number of 16 bit bytes then 8 bit bytes.
1700 //
1701 if (s->conversion) {
1702 if (cnt_by > (count * 2)) {
1703 cnt = (count * 2) / FRAME_SAMPLE_BYTES;
1704 cnt_by = count * 2;
1705 }
1706 } else {
1707 if (cnt_by > count) {
1708 cnt = count / FRAME_SAMPLE_BYTES;
1709 cnt_by = count;
1710 }
1711 }
1712 //
1713 // "cnt" NOW is the smaller of the amount that will be read,
1714 // and the amount that is requested in this read (or partial).
1715 // if there are no bytes in the buffer to read, then start the
1716 // ADC and wait for the interrupt handler to wake us up.
1717 //
1718 if (cnt <= 0) {
1719
1720 // start up the dma engine and then continue back to the top of
1721 // the loop when wake up occurs.
1722 start_adc(s);
1723 if (file->f_flags & O_NONBLOCK)
1724 return ret ? ret : -EAGAIN;
1725 interruptible_sleep_on(&s->dma_adc.wait);
1726 if (signal_pending(current))
1727 return ret ? ret : -ERESTARTSYS;
1728 continue;
1729 }
1730 // there are bytes in the buffer to read.
1731 // copy from the hw buffer over to the user buffer.
1732 // user buffer is designated by "buffer"
1733 // virtual address to copy from is dma_buf+swptr
1734 // the "cnt" is the number of bytes to read.
1735
1736 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
1737 "_read() copy_to cnt=%d count=%d ", cnt_by, count));
1738 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1739 " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n",
1740 s->dma_adc.sbufsz, s->dma_adc.count,
1741 (unsigned) buffer, ret));
1742
1743 if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by))
1744 return ret ? ret : -EFAULT;
1745 copied = cnt_by;
1746
1747 /* Return the descriptors */
1748 spin_lock_irqsave(&s->lock, flags);
1749 CS_DBGOUT(CS_FUNCTION, 2,
1750 printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr));
1751 s->dma_adc.count -= cnt_by;
1752 s->dma_adc.sb_swptr += cnt * 2;
1753 if (s->dma_adc.sb_swptr == s->dma_adc.sb_end)
1754 s->dma_adc.sb_swptr = s->dma_adc.sample_buf;
1755 spin_unlock_irqrestore(&s->lock, flags);
1756 count -= copied;
1757 buffer += copied;
1758 ret += copied;
1759 start_adc(s);
1760 }
1761 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1762 printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret));
1763 return ret;
1764 }
1765
1766
1767 static ssize_t cs4297a_write(struct file *file, const char *buffer,
1768 size_t count, loff_t * ppos)
1769 {
1770 struct cs4297a_state *s =
1771 (struct cs4297a_state *) file->private_data;
1772 ssize_t ret;
1773 unsigned long flags;
1774 unsigned swptr, hwptr;
1775 int cnt;
1776
1777 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1778 printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n",
1779 count));
1780 VALIDATE_STATE(s);
1781
1782 if (s->dma_dac.mapped)
1783 return -ENXIO;
1784 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1785 return ret;
1786 if (!access_ok(VERIFY_READ, buffer, count))
1787 return -EFAULT;
1788 ret = 0;
1789 while (count > 0) {
1790 serdma_t *d = &s->dma_dac;
1791 int copy_cnt;
1792 u32 *s_tmpl;
1793 u32 *t_tmpl;
1794 u32 left, right;
1795 int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE);
1796
1797 /* XXXXXX this is broken for BLOAT_FACTOR */
1798 spin_lock_irqsave(&s->lock, flags);
1799 if (d->count < 0) {
1800 d->count = 0;
1801 d->swptr = d->hwptr;
1802 }
1803 if (d->underrun) {
1804 d->underrun = 0;
1805 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1806 d->descrtab_phys) / sizeof(serdma_descr_t));
1807 d->swptr = d->hwptr = hwptr;
1808 }
1809 swptr = d->swptr;
1810 cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES);
1811 /* Will this write fill up the buffer? */
1812 if (d->count + cnt > d->sbufsz)
1813 cnt = d->sbufsz - d->count;
1814 spin_unlock_irqrestore(&s->lock, flags);
1815 if (cnt > count)
1816 cnt = count;
1817 if (cnt <= 0) {
1818 start_dac(s);
1819 if (file->f_flags & O_NONBLOCK)
1820 return ret ? ret : -EAGAIN;
1821 interruptible_sleep_on(&d->wait);
1822 if (signal_pending(current))
1823 return ret ? ret : -ERESTARTSYS;
1824 continue;
1825 }
1826 if (copy_from_user(d->sample_buf, buffer, cnt))
1827 return ret ? ret : -EFAULT;
1828
1829 copy_cnt = cnt;
1830 s_tmpl = (u32 *)d->sample_buf;
1831 t_tmpl = (u32 *)(d->dma_buf + (swptr * 4));
1832
1833 /* XXXKW assuming 16-bit stereo! */
1834 do {
1835 u32 tmp;
1836
1837 t_tmpl[0] = cpu_to_be32(0x98000000);
1838
1839 tmp = be32_to_cpu(s_tmpl[0]);
1840 left = tmp & 0xffff;
1841 right = tmp >> 16;
1842 if (swap) {
1843 left = swab16(left);
1844 right = swab16(right);
1845 }
1846 t_tmpl[1] = cpu_to_be32(left >> 8);
1847 t_tmpl[2] = cpu_to_be32(((left & 0xff) << 24) |
1848 (right << 4));
1849
1850 s_tmpl++;
1851 t_tmpl += 8;
1852 copy_cnt -= 4;
1853 } while (copy_cnt);
1854
1855 /* Mux in any pending read/write accesses */
1856 if (s->reg_request) {
1857 *(u64 *)(d->dma_buf + (swptr * 4)) |=
1858 cpu_to_be64(s->reg_request);
1859 s->reg_request = 0;
1860 wake_up(&s->dma_dac.reg_wait);
1861 }
1862
1863 CS_DBGOUT(CS_WAVE_WRITE, 4,
1864 printk(KERN_INFO
1865 "cs4297a: copy in %d to swptr %x\n", cnt, swptr));
1866
1867 swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz;
1868 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
1869 spin_lock_irqsave(&s->lock, flags);
1870 d->swptr = swptr;
1871 d->count += cnt;
1872 d->endcleared = 0;
1873 spin_unlock_irqrestore(&s->lock, flags);
1874 count -= cnt;
1875 buffer += cnt;
1876 ret += cnt;
1877 start_dac(s);
1878 }
1879 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1880 printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret));
1881 return ret;
1882 }
1883
1884
1885 static unsigned int cs4297a_poll(struct file *file,
1886 struct poll_table_struct *wait)
1887 {
1888 struct cs4297a_state *s =
1889 (struct cs4297a_state *) file->private_data;
1890 unsigned long flags;
1891 unsigned int mask = 0;
1892
1893 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1894 printk(KERN_INFO "cs4297a: cs4297a_poll()+\n"));
1895 VALIDATE_STATE(s);
1896 if (file->f_mode & FMODE_WRITE) {
1897 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1898 printk(KERN_INFO
1899 "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n"));
1900 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
1901 return 0;
1902 poll_wait(file, &s->dma_dac.wait, wait);
1903 }
1904 if (file->f_mode & FMODE_READ) {
1905 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1906 printk(KERN_INFO
1907 "cs4297a: cs4297a_poll() wait on FMODE_READ\n"));
1908 if(!s->dma_dac.ready && prog_dmabuf_adc(s))
1909 return 0;
1910 poll_wait(file, &s->dma_adc.wait, wait);
1911 }
1912 spin_lock_irqsave(&s->lock, flags);
1913 cs4297a_update_ptr(s,CS_FALSE);
1914 if (file->f_mode & FMODE_WRITE) {
1915 if (s->dma_dac.mapped) {
1916 if (s->dma_dac.count >=
1917 (signed) s->dma_dac.fragsize) {
1918 if (s->dma_dac.wakeup)
1919 mask |= POLLOUT | POLLWRNORM;
1920 else
1921 mask = 0;
1922 s->dma_dac.wakeup = 0;
1923 }
1924 } else {
1925 if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count)
1926 mask |= POLLOUT | POLLWRNORM;
1927 }
1928 } else if (file->f_mode & FMODE_READ) {
1929 if (s->dma_adc.mapped) {
1930 if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
1931 mask |= POLLIN | POLLRDNORM;
1932 } else {
1933 if (s->dma_adc.count > 0)
1934 mask |= POLLIN | POLLRDNORM;
1935 }
1936 }
1937 spin_unlock_irqrestore(&s->lock, flags);
1938 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1939 printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n",
1940 mask));
1941 return mask;
1942 }
1943
1944
1945 static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma)
1946 {
1947 /* XXXKW currently no mmap support */
1948 return -EINVAL;
1949 return 0;
1950 }
1951
1952
1953 static int cs4297a_ioctl(struct inode *inode, struct file *file,
1954 unsigned int cmd, unsigned long arg)
1955 {
1956 struct cs4297a_state *s =
1957 (struct cs4297a_state *) file->private_data;
1958 unsigned long flags;
1959 audio_buf_info abinfo;
1960 count_info cinfo;
1961 int val, mapped, ret;
1962
1963 CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO
1964 "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n",
1965 (unsigned) file, cmd));
1966 #if CSDEBUG
1967 cs_printioctl(cmd);
1968 #endif
1969 VALIDATE_STATE(s);
1970 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1971 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1972 switch (cmd) {
1973 case OSS_GETVERSION:
1974 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
1975 "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n",
1976 SOUND_VERSION));
1977 return put_user(SOUND_VERSION, (int *) arg);
1978
1979 case SNDCTL_DSP_SYNC:
1980 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1981 "cs4297a: cs4297a_ioctl(): DSP_SYNC\n"));
1982 if (file->f_mode & FMODE_WRITE)
1983 return drain_dac(s,
1984 0 /*file->f_flags & O_NONBLOCK */
1985 );
1986 return 0;
1987
1988 case SNDCTL_DSP_SETDUPLEX:
1989 return 0;
1990
1991 case SNDCTL_DSP_GETCAPS:
1992 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1993 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
1994 (int *) arg);
1995
1996 case SNDCTL_DSP_RESET:
1997 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1998 "cs4297a: cs4297a_ioctl(): DSP_RESET\n"));
1999 if (file->f_mode & FMODE_WRITE) {
2000 stop_dac(s);
2001 synchronize_irq(s->irq);
2002 s->dma_dac.count = s->dma_dac.total_bytes =
2003 s->dma_dac.blocks = s->dma_dac.wakeup = 0;
2004 s->dma_dac.swptr = s->dma_dac.hwptr =
2005 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
2006 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
2007 }
2008 if (file->f_mode & FMODE_READ) {
2009 stop_adc(s);
2010 synchronize_irq(s->irq);
2011 s->dma_adc.count = s->dma_adc.total_bytes =
2012 s->dma_adc.blocks = s->dma_dac.wakeup = 0;
2013 s->dma_adc.swptr = s->dma_adc.hwptr =
2014 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2015 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2016 }
2017 return 0;
2018
2019 case SNDCTL_DSP_SPEED:
2020 if (get_user(val, (int *) arg))
2021 return -EFAULT;
2022 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2023 "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val));
2024 val = 48000;
2025 return put_user(val, (int *) arg);
2026
2027 case SNDCTL_DSP_STEREO:
2028 if (get_user(val, (int *) arg))
2029 return -EFAULT;
2030 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2031 "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val));
2032 if (file->f_mode & FMODE_READ) {
2033 stop_adc(s);
2034 s->dma_adc.ready = 0;
2035 s->prop_adc.channels = val ? 2 : 1;
2036 }
2037 if (file->f_mode & FMODE_WRITE) {
2038 stop_dac(s);
2039 s->dma_dac.ready = 0;
2040 s->prop_dac.channels = val ? 2 : 1;
2041 }
2042 return 0;
2043
2044 case SNDCTL_DSP_CHANNELS:
2045 if (get_user(val, (int *) arg))
2046 return -EFAULT;
2047 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2048 "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n",
2049 val));
2050 if (val != 0) {
2051 if (file->f_mode & FMODE_READ) {
2052 stop_adc(s);
2053 s->dma_adc.ready = 0;
2054 if (val >= 2)
2055 s->prop_adc.channels = 2;
2056 else
2057 s->prop_adc.channels = 1;
2058 }
2059 if (file->f_mode & FMODE_WRITE) {
2060 stop_dac(s);
2061 s->dma_dac.ready = 0;
2062 if (val >= 2)
2063 s->prop_dac.channels = 2;
2064 else
2065 s->prop_dac.channels = 1;
2066 }
2067 }
2068
2069 if (file->f_mode & FMODE_WRITE)
2070 val = s->prop_dac.channels;
2071 else if (file->f_mode & FMODE_READ)
2072 val = s->prop_adc.channels;
2073
2074 return put_user(val, (int *) arg);
2075
2076 case SNDCTL_DSP_GETFMTS: // Returns a mask
2077 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2078 "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n",
2079 AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2080 AFMT_U8));
2081 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2082 AFMT_U8, (int *) arg);
2083
2084 case SNDCTL_DSP_SETFMT:
2085 if (get_user(val, (int *) arg))
2086 return -EFAULT;
2087 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2088 "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n",
2089 val));
2090 if (val != AFMT_QUERY) {
2091 if (file->f_mode & FMODE_READ) {
2092 stop_adc(s);
2093 s->dma_adc.ready = 0;
2094 if (val != AFMT_S16_LE
2095 && val != AFMT_U16_LE && val != AFMT_S8
2096 && val != AFMT_U8)
2097 val = AFMT_U8;
2098 s->prop_adc.fmt = val;
2099 s->prop_adc.fmt_original = s->prop_adc.fmt;
2100 }
2101 if (file->f_mode & FMODE_WRITE) {
2102 stop_dac(s);
2103 s->dma_dac.ready = 0;
2104 if (val != AFMT_S16_LE
2105 && val != AFMT_U16_LE && val != AFMT_S8
2106 && val != AFMT_U8)
2107 val = AFMT_U8;
2108 s->prop_dac.fmt = val;
2109 s->prop_dac.fmt_original = s->prop_dac.fmt;
2110 }
2111 } else {
2112 if (file->f_mode & FMODE_WRITE)
2113 val = s->prop_dac.fmt_original;
2114 else if (file->f_mode & FMODE_READ)
2115 val = s->prop_adc.fmt_original;
2116 }
2117 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2118 "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n",
2119 val));
2120 return put_user(val, (int *) arg);
2121
2122 case SNDCTL_DSP_POST:
2123 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2124 "cs4297a: cs4297a_ioctl(): DSP_POST\n"));
2125 return 0;
2126
2127 case SNDCTL_DSP_GETTRIGGER:
2128 val = 0;
2129 if (file->f_mode & s->ena & FMODE_READ)
2130 val |= PCM_ENABLE_INPUT;
2131 if (file->f_mode & s->ena & FMODE_WRITE)
2132 val |= PCM_ENABLE_OUTPUT;
2133 return put_user(val, (int *) arg);
2134
2135 case SNDCTL_DSP_SETTRIGGER:
2136 if (get_user(val, (int *) arg))
2137 return -EFAULT;
2138 if (file->f_mode & FMODE_READ) {
2139 if (val & PCM_ENABLE_INPUT) {
2140 if (!s->dma_adc.ready
2141 && (ret = prog_dmabuf_adc(s)))
2142 return ret;
2143 start_adc(s);
2144 } else
2145 stop_adc(s);
2146 }
2147 if (file->f_mode & FMODE_WRITE) {
2148 if (val & PCM_ENABLE_OUTPUT) {
2149 if (!s->dma_dac.ready
2150 && (ret = prog_dmabuf_dac(s)))
2151 return ret;
2152 start_dac(s);
2153 } else
2154 stop_dac(s);
2155 }
2156 return 0;
2157
2158 case SNDCTL_DSP_GETOSPACE:
2159 if (!(file->f_mode & FMODE_WRITE))
2160 return -EINVAL;
2161 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
2162 return val;
2163 spin_lock_irqsave(&s->lock, flags);
2164 cs4297a_update_ptr(s,CS_FALSE);
2165 abinfo.fragsize = s->dma_dac.fragsize;
2166 if (s->dma_dac.mapped)
2167 abinfo.bytes = s->dma_dac.sbufsz;
2168 else
2169 abinfo.bytes =
2170 s->dma_dac.sbufsz - s->dma_dac.count;
2171 abinfo.fragstotal = s->dma_dac.numfrag;
2172 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2173 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
2174 "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
2175 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
2176 abinfo.fragments));
2177 spin_unlock_irqrestore(&s->lock, flags);
2178 return copy_to_user((void *) arg, &abinfo,
2179 sizeof(abinfo)) ? -EFAULT : 0;
2180
2181 case SNDCTL_DSP_GETISPACE:
2182 if (!(file->f_mode & FMODE_READ))
2183 return -EINVAL;
2184 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
2185 return val;
2186 spin_lock_irqsave(&s->lock, flags);
2187 cs4297a_update_ptr(s,CS_FALSE);
2188 if (s->conversion) {
2189 abinfo.fragsize = s->dma_adc.fragsize / 2;
2190 abinfo.bytes = s->dma_adc.count / 2;
2191 abinfo.fragstotal = s->dma_adc.numfrag;
2192 abinfo.fragments =
2193 abinfo.bytes >> (s->dma_adc.fragshift - 1);
2194 } else {
2195 abinfo.fragsize = s->dma_adc.fragsize;
2196 abinfo.bytes = s->dma_adc.count;
2197 abinfo.fragstotal = s->dma_adc.numfrag;
2198 abinfo.fragments =
2199 abinfo.bytes >> s->dma_adc.fragshift;
2200 }
2201 spin_unlock_irqrestore(&s->lock, flags);
2202 return copy_to_user((void *) arg, &abinfo,
2203 sizeof(abinfo)) ? -EFAULT : 0;
2204
2205 case SNDCTL_DSP_NONBLOCK:
2206 file->f_flags |= O_NONBLOCK;
2207 return 0;
2208
2209 case SNDCTL_DSP_GETODELAY:
2210 if (!(file->f_mode & FMODE_WRITE))
2211 return -EINVAL;
2212 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2213 return 0;
2214 spin_lock_irqsave(&s->lock, flags);
2215 cs4297a_update_ptr(s,CS_FALSE);
2216 val = s->dma_dac.count;
2217 spin_unlock_irqrestore(&s->lock, flags);
2218 return put_user(val, (int *) arg);
2219
2220 case SNDCTL_DSP_GETIPTR:
2221 if (!(file->f_mode & FMODE_READ))
2222 return -EINVAL;
2223 if(!s->dma_adc.ready && prog_dmabuf_adc(s))
2224 return 0;
2225 spin_lock_irqsave(&s->lock, flags);
2226 cs4297a_update_ptr(s,CS_FALSE);
2227 cinfo.bytes = s->dma_adc.total_bytes;
2228 if (s->dma_adc.mapped) {
2229 cinfo.blocks =
2230 (cinfo.bytes >> s->dma_adc.fragshift) -
2231 s->dma_adc.blocks;
2232 s->dma_adc.blocks =
2233 cinfo.bytes >> s->dma_adc.fragshift;
2234 } else {
2235 if (s->conversion) {
2236 cinfo.blocks =
2237 s->dma_adc.count /
2238 2 >> (s->dma_adc.fragshift - 1);
2239 } else
2240 cinfo.blocks =
2241 s->dma_adc.count >> s->dma_adc.
2242 fragshift;
2243 }
2244 if (s->conversion)
2245 cinfo.ptr = s->dma_adc.hwptr / 2;
2246 else
2247 cinfo.ptr = s->dma_adc.hwptr;
2248 if (s->dma_adc.mapped)
2249 s->dma_adc.count &= s->dma_adc.fragsize - 1;
2250 spin_unlock_irqrestore(&s->lock, flags);
2251 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2252
2253 case SNDCTL_DSP_GETOPTR:
2254 if (!(file->f_mode & FMODE_WRITE))
2255 return -EINVAL;
2256 if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2257 return 0;
2258 spin_lock_irqsave(&s->lock, flags);
2259 cs4297a_update_ptr(s,CS_FALSE);
2260 cinfo.bytes = s->dma_dac.total_bytes;
2261 if (s->dma_dac.mapped) {
2262 cinfo.blocks =
2263 (cinfo.bytes >> s->dma_dac.fragshift) -
2264 s->dma_dac.blocks;
2265 s->dma_dac.blocks =
2266 cinfo.bytes >> s->dma_dac.fragshift;
2267 } else {
2268 cinfo.blocks =
2269 s->dma_dac.count >> s->dma_dac.fragshift;
2270 }
2271 cinfo.ptr = s->dma_dac.hwptr;
2272 if (s->dma_dac.mapped)
2273 s->dma_dac.count &= s->dma_dac.fragsize - 1;
2274 spin_unlock_irqrestore(&s->lock, flags);
2275 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
2276
2277 case SNDCTL_DSP_GETBLKSIZE:
2278 if (file->f_mode & FMODE_WRITE) {
2279 if ((val = prog_dmabuf_dac(s)))
2280 return val;
2281 return put_user(s->dma_dac.fragsize, (int *) arg);
2282 }
2283 if ((val = prog_dmabuf_adc(s)))
2284 return val;
2285 if (s->conversion)
2286 return put_user(s->dma_adc.fragsize / 2,
2287 (int *) arg);
2288 else
2289 return put_user(s->dma_adc.fragsize, (int *) arg);
2290
2291 case SNDCTL_DSP_SETFRAGMENT:
2292 if (get_user(val, (int *) arg))
2293 return -EFAULT;
2294 return 0; // Say OK, but do nothing.
2295
2296 case SNDCTL_DSP_SUBDIVIDE:
2297 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
2298 || (file->f_mode & FMODE_WRITE
2299 && s->dma_dac.subdivision)) return -EINVAL;
2300 if (get_user(val, (int *) arg))
2301 return -EFAULT;
2302 if (val != 1 && val != 2 && val != 4)
2303 return -EINVAL;
2304 if (file->f_mode & FMODE_READ)
2305 s->dma_adc.subdivision = val;
2306 else if (file->f_mode & FMODE_WRITE)
2307 s->dma_dac.subdivision = val;
2308 return 0;
2309
2310 case SOUND_PCM_READ_RATE:
2311 if (file->f_mode & FMODE_READ)
2312 return put_user(s->prop_adc.rate, (int *) arg);
2313 else if (file->f_mode & FMODE_WRITE)
2314 return put_user(s->prop_dac.rate, (int *) arg);
2315
2316 case SOUND_PCM_READ_CHANNELS:
2317 if (file->f_mode & FMODE_READ)
2318 return put_user(s->prop_adc.channels, (int *) arg);
2319 else if (file->f_mode & FMODE_WRITE)
2320 return put_user(s->prop_dac.channels, (int *) arg);
2321
2322 case SOUND_PCM_READ_BITS:
2323 if (file->f_mode & FMODE_READ)
2324 return
2325 put_user(
2326 (s->prop_adc.
2327 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2328 (int *) arg);
2329 else if (file->f_mode & FMODE_WRITE)
2330 return
2331 put_user(
2332 (s->prop_dac.
2333 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2334 (int *) arg);
2335
2336 case SOUND_PCM_WRITE_FILTER:
2337 case SNDCTL_DSP_SETSYNCRO:
2338 case SOUND_PCM_READ_FILTER:
2339 return -EINVAL;
2340 }
2341 return mixer_ioctl(s, cmd, arg);
2342 }
2343
2344
2345 static int cs4297a_release(struct inode *inode, struct file *file)
2346 {
2347 struct cs4297a_state *s =
2348 (struct cs4297a_state *) file->private_data;
2349
2350 CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
2351 "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2352 (unsigned) inode, (unsigned) file, file->f_mode));
2353 VALIDATE_STATE(s);
2354
2355 if (file->f_mode & FMODE_WRITE) {
2356 drain_dac(s, file->f_flags & O_NONBLOCK);
2357 mutex_lock(&s->open_sem_dac);
2358 stop_dac(s);
2359 dealloc_dmabuf(s, &s->dma_dac);
2360 s->open_mode &= ~FMODE_WRITE;
2361 mutex_unlock(&s->open_sem_dac);
2362 wake_up(&s->open_wait_dac);
2363 }
2364 if (file->f_mode & FMODE_READ) {
2365 drain_adc(s, file->f_flags & O_NONBLOCK);
2366 mutex_lock(&s->open_sem_adc);
2367 stop_adc(s);
2368 dealloc_dmabuf(s, &s->dma_adc);
2369 s->open_mode &= ~FMODE_READ;
2370 mutex_unlock(&s->open_sem_adc);
2371 wake_up(&s->open_wait_adc);
2372 }
2373 return 0;
2374 }
2375
2376 static int cs4297a_open(struct inode *inode, struct file *file)
2377 {
2378 int minor = iminor(inode);
2379 struct cs4297a_state *s=NULL;
2380 struct list_head *entry;
2381
2382 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2383 "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2384 (unsigned) inode, (unsigned) file, file->f_mode));
2385 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2386 "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG))));
2387
2388 list_for_each(entry, &cs4297a_devs)
2389 {
2390 s = list_entry(entry, struct cs4297a_state, list);
2391
2392 if (!((s->dev_audio ^ minor) & ~0xf))
2393 break;
2394 }
2395 if (entry == &cs4297a_devs)
2396 return -ENODEV;
2397 if (!s) {
2398 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2399 "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n"));
2400 return -ENODEV;
2401 }
2402 VALIDATE_STATE(s);
2403 file->private_data = s;
2404
2405 // wait for device to become free
2406 if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
2407 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
2408 "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n"));
2409 return -ENODEV;
2410 }
2411 if (file->f_mode & FMODE_WRITE) {
2412 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) {
2413 printk(KERN_ERR "cs4297a: TX pipe needs to drain\n");
2414 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)))
2415 ;
2416 }
2417
2418 mutex_lock(&s->open_sem_dac);
2419 while (s->open_mode & FMODE_WRITE) {
2420 if (file->f_flags & O_NONBLOCK) {
2421 mutex_unlock(&s->open_sem_dac);
2422 return -EBUSY;
2423 }
2424 mutex_unlock(&s->open_sem_dac);
2425 interruptible_sleep_on(&s->open_wait_dac);
2426
2427 if (signal_pending(current)) {
2428 printk("open - sig pending\n");
2429 return -ERESTARTSYS;
2430 }
2431 mutex_lock(&s->open_sem_dac);
2432 }
2433 }
2434 if (file->f_mode & FMODE_READ) {
2435 mutex_lock(&s->open_sem_adc);
2436 while (s->open_mode & FMODE_READ) {
2437 if (file->f_flags & O_NONBLOCK) {
2438 mutex_unlock(&s->open_sem_adc);
2439 return -EBUSY;
2440 }
2441 mutex_unlock(&s->open_sem_adc);
2442 interruptible_sleep_on(&s->open_wait_adc);
2443
2444 if (signal_pending(current)) {
2445 printk("open - sig pending\n");
2446 return -ERESTARTSYS;
2447 }
2448 mutex_lock(&s->open_sem_adc);
2449 }
2450 }
2451 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2452 if (file->f_mode & FMODE_READ) {
2453 s->prop_adc.fmt = AFMT_S16_BE;
2454 s->prop_adc.fmt_original = s->prop_adc.fmt;
2455 s->prop_adc.channels = 2;
2456 s->prop_adc.rate = 48000;
2457 s->conversion = 0;
2458 s->ena &= ~FMODE_READ;
2459 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
2460 s->dma_adc.subdivision = 0;
2461 mutex_unlock(&s->open_sem_adc);
2462
2463 if (prog_dmabuf_adc(s)) {
2464 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2465 "cs4297a: adc Program dmabufs failed.\n"));
2466 cs4297a_release(inode, file);
2467 return -ENOMEM;
2468 }
2469 }
2470 if (file->f_mode & FMODE_WRITE) {
2471 s->prop_dac.fmt = AFMT_S16_BE;
2472 s->prop_dac.fmt_original = s->prop_dac.fmt;
2473 s->prop_dac.channels = 2;
2474 s->prop_dac.rate = 48000;
2475 s->conversion = 0;
2476 s->ena &= ~FMODE_WRITE;
2477 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
2478 s->dma_dac.subdivision = 0;
2479 mutex_unlock(&s->open_sem_dac);
2480
2481 if (prog_dmabuf_dac(s)) {
2482 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2483 "cs4297a: dac Program dmabufs failed.\n"));
2484 cs4297a_release(inode, file);
2485 return -ENOMEM;
2486 }
2487 }
2488 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
2489 printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n"));
2490 return nonseekable_open(inode, file);
2491 }
2492
2493
2494 // ******************************************************************************************
2495 // Wave (audio) file operations struct.
2496 // ******************************************************************************************
2497 static /*const */ struct file_operations cs4297a_audio_fops = {
2498 .owner = THIS_MODULE,
2499 .llseek = no_llseek,
2500 .read = cs4297a_read,
2501 .write = cs4297a_write,
2502 .poll = cs4297a_poll,
2503 .ioctl = cs4297a_ioctl,
2504 .mmap = cs4297a_mmap,
2505 .open = cs4297a_open,
2506 .release = cs4297a_release,
2507 };
2508
2509 static void cs4297a_interrupt(int irq, void *dev_id)
2510 {
2511 struct cs4297a_state *s = (struct cs4297a_state *) dev_id;
2512 u32 status;
2513
2514 status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG));
2515
2516 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2517 "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status));
2518
2519 #if 0
2520 /* XXXKW what check *should* be done here? */
2521 if (!(status & (M_SYNCSER_RX_EOP_COUNT | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_SYNC_ERR))) {
2522 status = __raw_readq(SS_CSR(R_SER_STATUS));
2523 printk(KERN_ERR "cs4297a: unexpected interrupt (status %08x)\n", status);
2524 return;
2525 }
2526 #endif
2527
2528 if (status & M_SYNCSER_RX_SYNC_ERR) {
2529 status = __raw_readq(SS_CSR(R_SER_STATUS));
2530 printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status);
2531 return;
2532 }
2533
2534 if (status & M_SYNCSER_RX_OVERRUN) {
2535 int newptr, i;
2536 s->stats.rx_ovrrn++;
2537 printk(KERN_ERR "cs4297a: receive FIFO overrun\n");
2538
2539 /* Fix things up: get the receive descriptor pool
2540 clean and give them back to the hardware */
2541 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX)))
2542 ;
2543 newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2544 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2545 for (i=0; i<DMA_DESCR; i++) {
2546 s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP;
2547 }
2548 s->dma_adc.swptr = s->dma_adc.hwptr = newptr;
2549 s->dma_adc.count = 0;
2550 s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf;
2551 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
2552 }
2553
2554 spin_lock(&s->lock);
2555 cs4297a_update_ptr(s,CS_TRUE);
2556 spin_unlock(&s->lock);
2557
2558 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2559 "cs4297a: cs4297a_interrupt()-\n"));
2560 }
2561
2562 #if 0
2563 static struct initvol {
2564 int mixch;
2565 int vol;
2566 } initvol[] __initdata = {
2567
2568 {SOUND_MIXER_WRITE_VOLUME, 0x4040},
2569 {SOUND_MIXER_WRITE_PCM, 0x4040},
2570 {SOUND_MIXER_WRITE_SYNTH, 0x4040},
2571 {SOUND_MIXER_WRITE_CD, 0x4040},
2572 {SOUND_MIXER_WRITE_LINE, 0x4040},
2573 {SOUND_MIXER_WRITE_LINE1, 0x4040},
2574 {SOUND_MIXER_WRITE_RECLEV, 0x0000},
2575 {SOUND_MIXER_WRITE_SPEAKER, 0x4040},
2576 {SOUND_MIXER_WRITE_MIC, 0x0000}
2577 };
2578 #endif
2579
2580 static int __init cs4297a_init(void)
2581 {
2582 struct cs4297a_state *s;
2583 u32 pwr, id;
2584 mm_segment_t fs;
2585 int rval;
2586 #ifndef CONFIG_BCM_CS4297A_CSWARM
2587 u64 cfg;
2588 int mdio_val;
2589 #endif
2590
2591 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
2592 "cs4297a: cs4297a_init_module()+ \n"));
2593
2594 #ifndef CONFIG_BCM_CS4297A_CSWARM
2595 mdio_val = __raw_readq(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) &
2596 (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT);
2597
2598 /* Check syscfg for synchronous serial on port 1 */
2599 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2600 if (!(cfg & M_SYS_SER1_ENABLE)) {
2601 __raw_writeq(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG);
2602 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
2603 if (!(cfg & M_SYS_SER1_ENABLE)) {
2604 printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n");
2605 return -1;
2606 }
2607
2608 printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n");
2609
2610 /* Force the codec (on SWARM) to reset by clearing
2611 GENO, preserving MDIO (no effect on CSWARM) */
2612 __raw_writeq(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2613 udelay(10);
2614 }
2615
2616 /* Now set GENO */
2617 __raw_writeq(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2618 /* Give the codec some time to finish resetting (start the bit clock) */
2619 udelay(100);
2620 #endif
2621
2622 if (!(s = kmalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) {
2623 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
2624 "cs4297a: probe() no memory for state struct.\n"));
2625 return -1;
2626 }
2627 memset(s, 0, sizeof(struct cs4297a_state));
2628 s->magic = CS4297a_MAGIC;
2629 init_waitqueue_head(&s->dma_adc.wait);
2630 init_waitqueue_head(&s->dma_dac.wait);
2631 init_waitqueue_head(&s->dma_adc.reg_wait);
2632 init_waitqueue_head(&s->dma_dac.reg_wait);
2633 init_waitqueue_head(&s->open_wait);
2634 init_waitqueue_head(&s->open_wait_adc);
2635 init_waitqueue_head(&s->open_wait_dac);
2636 mutex_init(&s->open_sem_adc);
2637 mutex_init(&s->open_sem_dac);
2638 spin_lock_init(&s->lock);
2639
2640 s->irq = K_INT_SER_1;
2641
2642 if (request_irq
2643 (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) {
2644 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
2645 printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq));
2646 goto err_irq;
2647 }
2648 if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) <
2649 0) {
2650 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2651 "cs4297a: probe() register_sound_dsp() failed.\n"));
2652 goto err_dev1;
2653 }
2654 if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) <
2655 0) {
2656 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2657 "cs4297a: probe() register_sound_mixer() failed.\n"));
2658 goto err_dev2;
2659 }
2660
2661 if (ser_init(s) || dma_init(s)) {
2662 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2663 "cs4297a: ser_init failed.\n"));
2664 goto err_dev3;
2665 }
2666
2667 do {
2668 udelay(4000);
2669 rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr);
2670 } while (!rval && (pwr != 0xf));
2671
2672 if (!rval) {
2673 char *sb1250_duart_present;
2674
2675 fs = get_fs();
2676 set_fs(KERNEL_DS);
2677 #if 0
2678 val = SOUND_MASK_LINE;
2679 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
2680 for (i = 0; i < ARRAY_SIZE(initvol); i++) {
2681 val = initvol[i].vol;
2682 mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
2683 }
2684 // cs4297a_write_ac97(s, 0x18, 0x0808);
2685 #else
2686 // cs4297a_write_ac97(s, 0x5e, 0x180);
2687 cs4297a_write_ac97(s, 0x02, 0x0808);
2688 cs4297a_write_ac97(s, 0x18, 0x0808);
2689 #endif
2690 set_fs(fs);
2691
2692 list_add(&s->list, &cs4297a_devs);
2693
2694 cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id);
2695
2696 sb1250_duart_present = symbol_get(sb1250_duart_present);
2697 if (sb1250_duart_present)
2698 sb1250_duart_present[1] = 0;
2699
2700 printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id);
2701
2702 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2703 printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n"));
2704
2705 return 0;
2706 }
2707
2708 err_dev3:
2709 unregister_sound_mixer(s->dev_mixer);
2710 err_dev2:
2711 unregister_sound_dsp(s->dev_audio);
2712 err_dev1:
2713 free_irq(s->irq, s);
2714 err_irq:
2715 kfree(s);
2716
2717 printk(KERN_INFO "cs4297a: initialization failed\n");
2718
2719 return -1;
2720 }
2721
2722 static void __exit cs4297a_cleanup(void)
2723 {
2724 /*
2725 XXXKW
2726 disable_irq, free_irq
2727 drain DMA queue
2728 disable DMA
2729 disable TX/RX
2730 free memory
2731 */
2732 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2733 printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n"));
2734 }
2735
2736 // ---------------------------------------------------------------------
2737
2738 MODULE_AUTHOR("Kip Walker, Broadcom Corp.");
2739 MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board");
2740
2741 // ---------------------------------------------------------------------
2742
2743 module_init(cs4297a_init);
2744 module_exit(cs4297a_cleanup);
Linux kernel - Deliverables
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