1 /******************************************************************************
3 AudioScience HPI driver
4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of version 2 of the GNU General Public License as
8 published by the Free Software Foundation;
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 Hardware Programming Interface (HPI) for AudioScience ASI6200 series adapters.
20 These PCI bus adapters are based on the TI C6711 DSP.
23 void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
26 HIDE_PCI_ASSERTS to show the PCI asserts
27 PROFILE_DSP2 get profile data from DSP2 if present (instead of DSP 1)
29 (C) Copyright AudioScience Inc. 1998-2003
30 *******************************************************************************/
31 #define SOURCEFILE_NAME "hpi6000.c"
33 #include "hpi_internal.h"
34 #include "hpimsginit.h"
40 #define HPI_HIF_BASE (0x00000200) /* start of C67xx internal RAM */
41 #define HPI_HIF_ADDR(member) \
42 (HPI_HIF_BASE + offsetof(struct hpi_hif_6000, member))
43 #define HPI_HIF_ERROR_MASK 0x4000
45 /* HPI6000 specific error codes */
47 #define HPI6000_ERROR_BASE 900
48 #define HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT 901
49 #define HPI6000_ERROR_MSG_RESP_SEND_MSG_ACK 902
50 #define HPI6000_ERROR_MSG_RESP_GET_RESP_ACK 903
51 #define HPI6000_ERROR_MSG_GET_ADR 904
52 #define HPI6000_ERROR_RESP_GET_ADR 905
53 #define HPI6000_ERROR_MSG_RESP_BLOCKWRITE32 906
54 #define HPI6000_ERROR_MSG_RESP_BLOCKREAD32 907
55 #define HPI6000_ERROR_MSG_INVALID_DSP_INDEX 908
56 #define HPI6000_ERROR_CONTROL_CACHE_PARAMS 909
58 #define HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT 911
59 #define HPI6000_ERROR_SEND_DATA_ACK 912
60 #define HPI6000_ERROR_SEND_DATA_ADR 913
61 #define HPI6000_ERROR_SEND_DATA_TIMEOUT 914
62 #define HPI6000_ERROR_SEND_DATA_CMD 915
63 #define HPI6000_ERROR_SEND_DATA_WRITE 916
64 #define HPI6000_ERROR_SEND_DATA_IDLECMD 917
65 #define HPI6000_ERROR_SEND_DATA_VERIFY 918
67 #define HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT 921
68 #define HPI6000_ERROR_GET_DATA_ACK 922
69 #define HPI6000_ERROR_GET_DATA_CMD 923
70 #define HPI6000_ERROR_GET_DATA_READ 924
71 #define HPI6000_ERROR_GET_DATA_IDLECMD 925
73 #define HPI6000_ERROR_CONTROL_CACHE_ADDRLEN 951
74 #define HPI6000_ERROR_CONTROL_CACHE_READ 952
75 #define HPI6000_ERROR_CONTROL_CACHE_FLUSH 953
77 #define HPI6000_ERROR_MSG_RESP_GETRESPCMD 961
78 #define HPI6000_ERROR_MSG_RESP_IDLECMD 962
79 #define HPI6000_ERROR_MSG_RESP_BLOCKVERIFY32 963
81 /* adapter init errors */
82 #define HPI6000_ERROR_UNHANDLED_SUBSYS_ID 930
84 /* can't access PCI2040 */
85 #define HPI6000_ERROR_INIT_PCI2040 931
86 /* can't access DSP HPI i/f */
87 #define HPI6000_ERROR_INIT_DSPHPI 932
88 /* can't access internal DSP memory */
89 #define HPI6000_ERROR_INIT_DSPINTMEM 933
90 /* can't access SDRAM - test#1 */
91 #define HPI6000_ERROR_INIT_SDRAM1 934
92 /* can't access SDRAM - test#2 */
93 #define HPI6000_ERROR_INIT_SDRAM2 935
95 #define HPI6000_ERROR_INIT_VERIFY 938
97 #define HPI6000_ERROR_INIT_NOACK 939
99 #define HPI6000_ERROR_INIT_PLDTEST1 941
100 #define HPI6000_ERROR_INIT_PLDTEST2 942
104 #define HIDE_PCI_ASSERTS
107 /* for PCI2040 i/f chip */
108 /* HPI CSR registers */
109 /* word offsets from CSR base */
110 /* use when io addresses defined as u32 * */
112 #define INTERRUPT_EVENT_SET 0
113 #define INTERRUPT_EVENT_CLEAR 1
114 #define INTERRUPT_MASK_SET 2
115 #define INTERRUPT_MASK_CLEAR 3
116 #define HPI_ERROR_REPORT 4
118 #define HPI_DATA_WIDTH 6
121 /* HPI registers, spaced 8K bytes = 2K words apart */
122 #define DSP_SPACING 0x800
124 #define CONTROL 0x0000
125 #define ADDRESS 0x0200
126 #define DATA_AUTOINC 0x0400
129 #define TIMEOUT 500000
132 __iomem u32
*prHPI_control
;
133 __iomem u32
*prHPI_address
;
134 __iomem u32
*prHPI_data
;
135 __iomem u32
*prHPI_data_auto_inc
;
136 char c_dsp_rev
; /*A, B */
137 u32 control_cache_address_on_dsp
;
138 u32 control_cache_length_on_dsp
;
139 struct hpi_adapter_obj
*pa_parent_adapter
;
143 __iomem u32
*dw2040_HPICSR
;
144 __iomem u32
*dw2040_HPIDSP
;
147 struct dsp_obj ado
[MAX_DSPS
];
149 u32 message_buffer_address_on_dsp
;
150 u32 response_buffer_address_on_dsp
;
151 u32 pCI2040HPI_error_count
;
153 struct hpi_control_cache_single control_cache
[HPI_NMIXER_CONTROLS
];
154 struct hpi_control_cache
*p_cache
;
157 static u16
hpi6000_dsp_block_write32(struct hpi_adapter_obj
*pao
,
158 u16 dsp_index
, u32 hpi_address
, u32
*source
, u32 count
);
159 static u16
hpi6000_dsp_block_read32(struct hpi_adapter_obj
*pao
,
160 u16 dsp_index
, u32 hpi_address
, u32
*dest
, u32 count
);
162 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj
*pao
,
163 u32
*pos_error_code
);
164 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj
*pao
,
169 static short hpi6000_update_control_cache(struct hpi_adapter_obj
*pao
,
170 struct hpi_message
*phm
);
171 static short hpi6000_message_response_sequence(struct hpi_adapter_obj
*pao
,
172 u16 dsp_index
, struct hpi_message
*phm
, struct hpi_response
*phr
);
174 static void hw_message(struct hpi_adapter_obj
*pao
, struct hpi_message
*phm
,
175 struct hpi_response
*phr
);
177 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj
*pao
, u16 dsp_index
,
180 static short hpi6000_send_host_command(struct hpi_adapter_obj
*pao
,
181 u16 dsp_index
, u32 host_cmd
);
183 static void hpi6000_send_dsp_interrupt(struct dsp_obj
*pdo
);
185 static short hpi6000_send_data(struct hpi_adapter_obj
*pao
, u16 dsp_index
,
186 struct hpi_message
*phm
, struct hpi_response
*phr
);
188 static short hpi6000_get_data(struct hpi_adapter_obj
*pao
, u16 dsp_index
,
189 struct hpi_message
*phm
, struct hpi_response
*phr
);
191 static void hpi_write_word(struct dsp_obj
*pdo
, u32 address
, u32 data
);
193 static u32
hpi_read_word(struct dsp_obj
*pdo
, u32 address
);
195 static void hpi_write_block(struct dsp_obj
*pdo
, u32 address
, u32
*pdata
,
198 static void hpi_read_block(struct dsp_obj
*pdo
, u32 address
, u32
*pdata
,
201 static void subsys_create_adapter(struct hpi_message
*phm
,
202 struct hpi_response
*phr
);
204 static void subsys_delete_adapter(struct hpi_message
*phm
,
205 struct hpi_response
*phr
);
207 static void adapter_get_asserts(struct hpi_adapter_obj
*pao
,
208 struct hpi_message
*phm
, struct hpi_response
*phr
);
210 static short create_adapter_obj(struct hpi_adapter_obj
*pao
,
211 u32
*pos_error_code
);
215 static u16 gw_pci_read_asserts
; /* used to count PCI2040 errors */
216 static u16 gw_pci_write_asserts
; /* used to count PCI2040 errors */
218 static void subsys_message(struct hpi_message
*phm
, struct hpi_response
*phr
)
221 switch (phm
->function
) {
222 case HPI_SUBSYS_OPEN
:
223 case HPI_SUBSYS_CLOSE
:
224 case HPI_SUBSYS_GET_INFO
:
225 case HPI_SUBSYS_DRIVER_UNLOAD
:
226 case HPI_SUBSYS_DRIVER_LOAD
:
227 case HPI_SUBSYS_FIND_ADAPTERS
:
228 /* messages that should not get here */
229 phr
->error
= HPI_ERROR_UNIMPLEMENTED
;
231 case HPI_SUBSYS_CREATE_ADAPTER
:
232 subsys_create_adapter(phm
, phr
);
234 case HPI_SUBSYS_DELETE_ADAPTER
:
235 subsys_delete_adapter(phm
, phr
);
238 phr
->error
= HPI_ERROR_INVALID_FUNC
;
243 static void control_message(struct hpi_adapter_obj
*pao
,
244 struct hpi_message
*phm
, struct hpi_response
*phr
)
247 switch (phm
->function
) {
248 case HPI_CONTROL_GET_STATE
:
249 if (pao
->has_control_cache
) {
251 err
= hpi6000_update_control_cache(pao
, phm
);
258 if (hpi_check_control_cache(((struct hpi_hw_obj
*)
259 pao
->priv
)->p_cache
, phm
,
263 hw_message(pao
, phm
, phr
);
265 case HPI_CONTROL_GET_INFO
:
266 hw_message(pao
, phm
, phr
);
268 case HPI_CONTROL_SET_STATE
:
269 hw_message(pao
, phm
, phr
);
270 hpi_sync_control_cache(((struct hpi_hw_obj
*)pao
->priv
)->
274 phr
->error
= HPI_ERROR_INVALID_FUNC
;
279 static void adapter_message(struct hpi_adapter_obj
*pao
,
280 struct hpi_message
*phm
, struct hpi_response
*phr
)
282 switch (phm
->function
) {
283 case HPI_ADAPTER_GET_INFO
:
284 hw_message(pao
, phm
, phr
);
286 case HPI_ADAPTER_GET_ASSERT
:
287 adapter_get_asserts(pao
, phm
, phr
);
289 case HPI_ADAPTER_OPEN
:
290 case HPI_ADAPTER_CLOSE
:
291 case HPI_ADAPTER_TEST_ASSERT
:
292 case HPI_ADAPTER_SELFTEST
:
293 case HPI_ADAPTER_GET_MODE
:
294 case HPI_ADAPTER_SET_MODE
:
295 case HPI_ADAPTER_FIND_OBJECT
:
296 case HPI_ADAPTER_GET_PROPERTY
:
297 case HPI_ADAPTER_SET_PROPERTY
:
298 case HPI_ADAPTER_ENUM_PROPERTY
:
299 hw_message(pao
, phm
, phr
);
302 phr
->error
= HPI_ERROR_INVALID_FUNC
;
307 static void outstream_message(struct hpi_adapter_obj
*pao
,
308 struct hpi_message
*phm
, struct hpi_response
*phr
)
310 switch (phm
->function
) {
311 case HPI_OSTREAM_HOSTBUFFER_ALLOC
:
312 case HPI_OSTREAM_HOSTBUFFER_FREE
:
313 /* Don't let these messages go to the HW function because
314 * they're called without allocating the spinlock.
315 * For the HPI6000 adapters the HW would return
316 * HPI_ERROR_INVALID_FUNC anyway.
318 phr
->error
= HPI_ERROR_INVALID_FUNC
;
321 hw_message(pao
, phm
, phr
);
326 static void instream_message(struct hpi_adapter_obj
*pao
,
327 struct hpi_message
*phm
, struct hpi_response
*phr
)
330 switch (phm
->function
) {
331 case HPI_ISTREAM_HOSTBUFFER_ALLOC
:
332 case HPI_ISTREAM_HOSTBUFFER_FREE
:
333 /* Don't let these messages go to the HW function because
334 * they're called without allocating the spinlock.
335 * For the HPI6000 adapters the HW would return
336 * HPI_ERROR_INVALID_FUNC anyway.
338 phr
->error
= HPI_ERROR_INVALID_FUNC
;
341 hw_message(pao
, phm
, phr
);
346 /************************************************************************/
348 * Entry point from HPIMAN
349 * All calls to the HPI start here
351 void HPI_6000(struct hpi_message
*phm
, struct hpi_response
*phr
)
353 struct hpi_adapter_obj
*pao
= NULL
;
355 /* subsytem messages get executed by every HPI. */
356 /* All other messages are ignored unless the adapter index matches */
357 /* an adapter in the HPI */
358 HPI_DEBUG_LOG(DEBUG
, "O %d,F %x\n", phm
->object
, phm
->function
);
360 /* if Dsp has crashed then do not communicate with it any more */
361 if (phm
->object
!= HPI_OBJ_SUBSYSTEM
) {
362 pao
= hpi_find_adapter(phm
->adapter_index
);
365 " %d,%d refused, for another HPI?\n",
366 phm
->object
, phm
->function
);
370 if (pao
->dsp_crashed
>= 10) {
371 hpi_init_response(phr
, phm
->object
, phm
->function
,
372 HPI_ERROR_DSP_HARDWARE
);
373 HPI_DEBUG_LOG(DEBUG
, " %d,%d dsp crashed.\n",
374 phm
->object
, phm
->function
);
378 /* Init default response including the size field */
379 if (phm
->function
!= HPI_SUBSYS_CREATE_ADAPTER
)
380 hpi_init_response(phr
, phm
->object
, phm
->function
,
381 HPI_ERROR_PROCESSING_MESSAGE
);
384 case HPI_TYPE_MESSAGE
:
385 switch (phm
->object
) {
386 case HPI_OBJ_SUBSYSTEM
:
387 subsys_message(phm
, phr
);
390 case HPI_OBJ_ADAPTER
:
392 sizeof(struct hpi_response_header
) +
393 sizeof(struct hpi_adapter_res
);
394 adapter_message(pao
, phm
, phr
);
397 case HPI_OBJ_CONTROL
:
398 control_message(pao
, phm
, phr
);
401 case HPI_OBJ_OSTREAM
:
402 outstream_message(pao
, phm
, phr
);
405 case HPI_OBJ_ISTREAM
:
406 instream_message(pao
, phm
, phr
);
410 hw_message(pao
, phm
, phr
);
416 phr
->error
= HPI_ERROR_INVALID_TYPE
;
421 /************************************************************************/
424 /* create an adapter object and initialise it based on resource information
425 * passed in in the message
426 * NOTE - you cannot use this function AND the FindAdapters function at the
427 * same time, the application must use only one of them to get the adapters
429 static void subsys_create_adapter(struct hpi_message
*phm
,
430 struct hpi_response
*phr
)
432 /* create temp adapter obj, because we don't know what index yet */
433 struct hpi_adapter_obj ao
;
434 struct hpi_adapter_obj
*pao
;
439 HPI_DEBUG_LOG(VERBOSE
, "subsys_create_adapter\n");
441 memset(&ao
, 0, sizeof(ao
));
443 /* this HPI only creates adapters for TI/PCI2040 based devices */
444 if (phm
->u
.s
.resource
.bus_type
!= HPI_BUS_PCI
)
446 if (phm
->u
.s
.resource
.r
.pci
->vendor_id
!= HPI_PCI_VENDOR_ID_TI
)
448 if (phm
->u
.s
.resource
.r
.pci
->device_id
!= HPI_PCI_DEV_ID_PCI2040
)
451 ao
.priv
= kmalloc(sizeof(struct hpi_hw_obj
), GFP_KERNEL
);
453 HPI_DEBUG_LOG(ERROR
, "cant get mem for adapter object\n");
454 phr
->error
= HPI_ERROR_MEMORY_ALLOC
;
458 memset(ao
.priv
, 0, sizeof(struct hpi_hw_obj
));
459 /* create the adapter object based on the resource information */
460 /*? memcpy(&ao.Pci,&phm->u.s.Resource.r.Pci,sizeof(ao.Pci)); */
461 ao
.pci
= *phm
->u
.s
.resource
.r
.pci
;
463 error
= create_adapter_obj(&ao
, &os_error_code
);
465 error
= hpi_add_adapter(&ao
);
467 phr
->u
.s
.data
= os_error_code
;
472 /* need to update paParentAdapter */
473 pao
= hpi_find_adapter(ao
.index
);
475 /* We just added this adapter, why can't we find it!? */
476 HPI_DEBUG_LOG(ERROR
, "lost adapter after boot\n");
481 for (dsp_index
= 0; dsp_index
< MAX_DSPS
; dsp_index
++) {
482 struct hpi_hw_obj
*phw
= (struct hpi_hw_obj
*)pao
->priv
;
483 phw
->ado
[dsp_index
].pa_parent_adapter
= pao
;
486 phr
->u
.s
.aw_adapter_list
[ao
.index
] = ao
.adapter_type
;
487 phr
->u
.s
.adapter_index
= ao
.index
;
488 phr
->u
.s
.num_adapters
++;
492 static void subsys_delete_adapter(struct hpi_message
*phm
,
493 struct hpi_response
*phr
)
495 struct hpi_adapter_obj
*pao
= NULL
;
496 struct hpi_hw_obj
*phw
;
498 pao
= hpi_find_adapter(phm
->adapter_index
);
502 phw
= (struct hpi_hw_obj
*)pao
->priv
;
504 if (pao
->has_control_cache
)
505 hpi_free_control_cache(phw
->p_cache
);
507 hpi_delete_adapter(pao
);
513 /* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */
514 static short create_adapter_obj(struct hpi_adapter_obj
*pao
,
517 short boot_error
= 0;
519 u32 control_cache_size
= 0;
520 u32 control_cache_count
= 0;
521 struct hpi_hw_obj
*phw
= (struct hpi_hw_obj
*)pao
->priv
;
523 /* init error reporting */
524 pao
->dsp_crashed
= 0;
526 /* The PCI2040 has the following address map */
527 /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */
528 /* BAR1 - 32K = HPI registers on DSP */
529 phw
->dw2040_HPICSR
= pao
->pci
.ap_mem_base
[0];
530 phw
->dw2040_HPIDSP
= pao
->pci
.ap_mem_base
[1];
531 HPI_DEBUG_LOG(VERBOSE
, "csr %p, dsp %p\n", phw
->dw2040_HPICSR
,
534 /* set addresses for the possible DSP HPI interfaces */
535 for (dsp_index
= 0; dsp_index
< MAX_DSPS
; dsp_index
++) {
536 phw
->ado
[dsp_index
].prHPI_control
=
537 phw
->dw2040_HPIDSP
+ (CONTROL
+
538 DSP_SPACING
* dsp_index
);
540 phw
->ado
[dsp_index
].prHPI_address
=
541 phw
->dw2040_HPIDSP
+ (ADDRESS
+
542 DSP_SPACING
* dsp_index
);
543 phw
->ado
[dsp_index
].prHPI_data
=
544 phw
->dw2040_HPIDSP
+ (DATA
+ DSP_SPACING
* dsp_index
);
546 phw
->ado
[dsp_index
].prHPI_data_auto_inc
=
547 phw
->dw2040_HPIDSP
+ (DATA_AUTOINC
+
548 DSP_SPACING
* dsp_index
);
550 HPI_DEBUG_LOG(VERBOSE
, "ctl %p, adr %p, dat %p, dat++ %p\n",
551 phw
->ado
[dsp_index
].prHPI_control
,
552 phw
->ado
[dsp_index
].prHPI_address
,
553 phw
->ado
[dsp_index
].prHPI_data
,
554 phw
->ado
[dsp_index
].prHPI_data_auto_inc
);
556 phw
->ado
[dsp_index
].pa_parent_adapter
= pao
;
559 phw
->pCI2040HPI_error_count
= 0;
560 pao
->has_control_cache
= 0;
562 /* Set the default number of DSPs on this card */
563 /* This is (conditionally) adjusted after bootloading */
564 /* of the first DSP in the bootload section. */
567 boot_error
= hpi6000_adapter_boot_load_dsp(pao
, pos_error_code
);
571 HPI_DEBUG_LOG(INFO
, "bootload DSP OK\n");
573 phw
->message_buffer_address_on_dsp
= 0L;
574 phw
->response_buffer_address_on_dsp
= 0L;
576 /* get info about the adapter by asking the adapter */
577 /* send a HPI_ADAPTER_GET_INFO message */
579 struct hpi_message hM
;
580 struct hpi_response hR0
; /* response from DSP 0 */
581 struct hpi_response hR1
; /* response from DSP 1 */
584 HPI_DEBUG_LOG(VERBOSE
, "send ADAPTER_GET_INFO\n");
585 memset(&hM
, 0, sizeof(hM
));
586 hM
.type
= HPI_TYPE_MESSAGE
;
587 hM
.size
= sizeof(struct hpi_message
);
588 hM
.object
= HPI_OBJ_ADAPTER
;
589 hM
.function
= HPI_ADAPTER_GET_INFO
;
590 hM
.adapter_index
= 0;
591 memset(&hR0
, 0, sizeof(hR0
));
592 memset(&hR1
, 0, sizeof(hR1
));
593 hR0
.size
= sizeof(hR0
);
594 hR1
.size
= sizeof(hR1
);
596 error
= hpi6000_message_response_sequence(pao
, 0, &hM
, &hR0
);
598 HPI_DEBUG_LOG(DEBUG
, "message error %d\n", hR0
.error
);
601 if (phw
->num_dsp
== 2) {
602 error
= hpi6000_message_response_sequence(pao
, 1, &hM
,
607 pao
->adapter_type
= hR0
.u
.a
.adapter_type
;
608 pao
->index
= hR0
.u
.a
.adapter_index
;
611 memset(&phw
->control_cache
[0], 0,
612 sizeof(struct hpi_control_cache_single
) *
613 HPI_NMIXER_CONTROLS
);
614 /* Read the control cache length to figure out if it is turned on */
616 hpi_read_word(&phw
->ado
[0],
617 HPI_HIF_ADDR(control_cache_size_in_bytes
));
618 if (control_cache_size
) {
619 control_cache_count
=
620 hpi_read_word(&phw
->ado
[0],
621 HPI_HIF_ADDR(control_cache_count
));
622 pao
->has_control_cache
= 1;
625 hpi_alloc_control_cache(control_cache_count
,
626 control_cache_size
, (struct hpi_control_cache_info
*)
627 &phw
->control_cache
[0]
630 pao
->has_control_cache
= 0;
632 HPI_DEBUG_LOG(DEBUG
, "get adapter info ASI%04X index %d\n",
633 pao
->adapter_type
, pao
->index
);
634 pao
->open
= 0; /* upon creation the adapter is closed */
638 /************************************************************************/
641 static void adapter_get_asserts(struct hpi_adapter_obj
*pao
,
642 struct hpi_message
*phm
, struct hpi_response
*phr
)
644 #ifndef HIDE_PCI_ASSERTS
645 /* if we have PCI2040 asserts then collect them */
646 if ((gw_pci_read_asserts
> 0) || (gw_pci_write_asserts
> 0)) {
647 phr
->u
.a
.serial_number
=
648 gw_pci_read_asserts
* 100 + gw_pci_write_asserts
;
649 phr
->u
.a
.adapter_index
= 1; /* assert count */
650 phr
->u
.a
.adapter_type
= -1; /* "dsp index" */
651 strcpy(phr
->u
.a
.sz_adapter_assert
, "PCI2040 error");
652 gw_pci_read_asserts
= 0;
653 gw_pci_write_asserts
= 0;
657 hw_message(pao
, phm
, phr
); /*get DSP asserts */
662 /************************************************************************/
665 static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj
*pao
,
668 struct hpi_hw_obj
*phw
= (struct hpi_hw_obj
*)pao
->priv
;
675 u32 test_addr
= 0x80000000;
676 u32 test_data
= 0x00000001;
677 u32 dw2040_reset
= 0;
680 u32 adapter_info
= 0;
683 struct dsp_code dsp_code
;
684 u16 boot_load_family
= 0;
686 /* NOTE don't use wAdapterType in this routine. It is not setup yet */
688 switch (pao
->pci
.subsys_device_id
) {
690 case 0x5110: /* ASI5100 revB or higher with C6711D */
693 boot_load_family
= HPI_ADAPTER_FAMILY_ASI(0x6200);
696 boot_load_family
= HPI_ADAPTER_FAMILY_ASI(0x8800);
699 return HPI6000_ERROR_UNHANDLED_SUBSYS_ID
;
702 /* reset all DSPs, indicate two DSPs are present
703 * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode
706 dw2040_reset
= 0x0003000F;
707 iowrite32(dw2040_reset
, phw
->dw2040_HPICSR
+ HPI_RESET
);
709 /* read back register to make sure PCI2040 chip is functioning
710 * note that bits 4..15 are read-only and so should always return zero,
711 * even though we wrote 1 to them
713 for (i
= 0; i
< 1000; i
++)
714 delay
= ioread32(phw
->dw2040_HPICSR
+ HPI_RESET
);
715 if (delay
!= dw2040_reset
) {
716 HPI_DEBUG_LOG(ERROR
, "INIT_PCI2040 %x %x\n", dw2040_reset
,
718 return HPI6000_ERROR_INIT_PCI2040
;
721 /* Indicate that DSP#0,1 is a C6X */
722 iowrite32(0x00000003, phw
->dw2040_HPICSR
+ HPI_DATA_WIDTH
);
723 /* set Bit30 and 29 - which will prevent Target aborts from being
724 * issued upon HPI or GP error
726 iowrite32(0x60000000, phw
->dw2040_HPICSR
+ INTERRUPT_MASK_SET
);
728 /* isolate DSP HAD8 line from PCI2040 so that
729 * Little endian can be set by pullup
731 dw2040_reset
= dw2040_reset
& (~(endian
<< 3));
732 iowrite32(dw2040_reset
, phw
->dw2040_HPICSR
+ HPI_RESET
);
734 phw
->ado
[0].c_dsp_rev
= 'B'; /* revB */
735 phw
->ado
[1].c_dsp_rev
= 'B'; /* revB */
737 /*Take both DSPs out of reset, setting HAD8 to the correct Endian */
738 dw2040_reset
= dw2040_reset
& (~0x00000001); /* start DSP 0 */
739 iowrite32(dw2040_reset
, phw
->dw2040_HPICSR
+ HPI_RESET
);
740 dw2040_reset
= dw2040_reset
& (~0x00000002); /* start DSP 1 */
741 iowrite32(dw2040_reset
, phw
->dw2040_HPICSR
+ HPI_RESET
);
743 /* set HAD8 back to PCI2040, now that DSP set to little endian mode */
744 dw2040_reset
= dw2040_reset
& (~0x00000008);
745 iowrite32(dw2040_reset
, phw
->dw2040_HPICSR
+ HPI_RESET
);
746 /*delay to allow DSP to get going */
747 for (i
= 0; i
< 100; i
++)
748 delay
= ioread32(phw
->dw2040_HPICSR
+ HPI_RESET
);
750 /* loop through all DSPs, downloading DSP code */
751 for (dsp_index
= 0; dsp_index
< phw
->num_dsp
; dsp_index
++) {
752 struct dsp_obj
*pdo
= &phw
->ado
[dsp_index
];
754 /* configure DSP so that we download code into the SRAM */
755 /* set control reg for little endian, HWOB=1 */
756 iowrite32(0x00010001, pdo
->prHPI_control
);
758 /* test access to the HPI address register (HPIA) */
759 test_data
= 0x00000001;
760 for (j
= 0; j
< 32; j
++) {
761 iowrite32(test_data
, pdo
->prHPI_address
);
762 data
= ioread32(pdo
->prHPI_address
);
763 if (data
!= test_data
) {
764 HPI_DEBUG_LOG(ERROR
, "INIT_DSPHPI %x %x %x\n",
765 test_data
, data
, dsp_index
);
766 return HPI6000_ERROR_INIT_DSPHPI
;
768 test_data
= test_data
<< 1;
771 /* if C6713 the setup PLL to generate 225MHz from 25MHz.
772 * Since the PLLDIV1 read is sometimes wrong, even on a C6713,
773 * we're going to do this unconditionally
775 /* PLLDIV1 should have a value of 8000 after reset */
777 if (HpiReadWord(pdo,0x01B7C118) == 0x8000)
780 /* C6713 datasheet says we cannot program PLL from HPI,
781 * and indeed if we try to set the PLL multiply from the
782 * HPI, the PLL does not seem to lock,
783 * so we enable the PLL and use the default of x 7
786 hpi_write_word(pdo
, 0x01B7C100, 0x0000);
787 for (i
= 0; i
< 100; i
++)
788 delay
= ioread32(phw
->dw2040_HPICSR
+
791 /* ** use default of PLL x7 ** */
792 /* EMIF = 225/3=75MHz */
793 hpi_write_word(pdo
, 0x01B7C120, 0x8002);
795 hpi_write_word(pdo
, 0x01B7C11C, 0x8001);
797 hpi_write_word(pdo
, 0x01B7C118, 0x8000);
799 for (i
= 0; i
< 2000; i
++)
800 delay
= ioread32(phw
->dw2040_HPICSR
+
802 /* PLL not bypassed */
803 hpi_write_word(pdo
, 0x01B7C100, 0x0001);
805 for (i
= 0; i
< 2000; i
++)
806 delay
= ioread32(phw
->dw2040_HPICSR
+
810 /* test r/w to internal DSP memory
811 * C6711 has L2 cache mapped to 0x0 when reset
813 * revB - because of bug 3.0.1 last HPI read
814 * (before HPI address issued) must be non-autoinc
816 /* test each bit in the 32bit word */
817 for (i
= 0; i
< 100; i
++) {
818 test_addr
= 0x00000000;
819 test_data
= 0x00000001;
820 for (j
= 0; j
< 32; j
++) {
821 hpi_write_word(pdo
, test_addr
+ i
, test_data
);
822 data
= hpi_read_word(pdo
, test_addr
+ i
);
823 if (data
!= test_data
) {
825 "DSP mem %x %x %x %x\n",
826 test_addr
+ i
, test_data
,
829 return HPI6000_ERROR_INIT_DSPINTMEM
;
831 test_data
= test_data
<< 1;
835 /* memory map of ASI6200
836 00000000-0000FFFF 16Kx32 internal program
837 01800000-019FFFFF Internal peripheral
838 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz
839 90000000-9000FFFF CE1 Async peripherals:
847 3 CLK2EN = 1 CLKOUT2 enabled
848 4 CLK1EN = 0 CLKOUT1 disabled
849 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT
851 7 NOHOLD = 1 external HOLD disabled
852 8 HOLDA = 0 HOLDA output is low
853 9 HOLD = 0 HOLD input is low
854 10 ARDY = 1 ARDY input is high
855 11 BUSREQ = 0 BUSREQ output is low
858 hpi_write_word(pdo
, 0x01800000, 0x34A8);
860 /* EMIF CE0 setup - 2Mx32 Sync DRAM
867 7..4 MTYPE 0011 Sync DRAM 32bits
871 hpi_write_word(pdo
, 0x01800008, 0x00000030);
873 /* EMIF SDRAM Extension
883 6-5 TWR = 2-1 = 01b (tWR = 10ns)
884 4 TRRD = 0b = 2 ECLK (tRRD = 14ns)
885 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK)
886 1 CAS latency = 3 ECLK
887 (for Micron 2M32-7 operating at 100Mhz)
890 /* need to use this else DSP code crashes */
891 hpi_write_word(pdo
, 0x01800020, 0x001BDF29);
893 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
896 29..28 SDRSZ 00 11 row address pins
897 27..26 SDCSZ 01 8 column address pins
898 25 RFEN 1 refersh enabled
905 /* need to use this else DSP code crashes */
906 hpi_write_word(pdo
, 0x01800018, 0x47117000);
908 /* EMIF SDRAM Refresh Timing */
909 hpi_write_word(pdo
, 0x0180001C, 0x00000410);
911 /*MIF CE1 setup - Async peripherals
912 @100MHz bus speed, each cycle is 10ns,
914 27..22 Wr strobe = 3 30ns
918 13..8 Rd strobe = 3 30ns
919 7..4 MTYPE 0010 Async 32bits
925 (1L << 28) | (3L << 22) | (1L << 20) | (1L <<
926 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L;
927 hpi_write_word(pdo
, 0x01800004, cE1
);
930 /* delay a little to allow SDRAM and DSP to "get going" */
932 for (i
= 0; i
< 1000; i
++)
933 delay
= ioread32(phw
->dw2040_HPICSR
+ HPI_RESET
);
935 /* test access to SDRAM */
937 test_addr
= 0x80000000;
938 test_data
= 0x00000001;
939 /* test each bit in the 32bit word */
940 for (j
= 0; j
< 32; j
++) {
941 hpi_write_word(pdo
, test_addr
, test_data
);
942 data
= hpi_read_word(pdo
, test_addr
);
943 if (data
!= test_data
) {
945 "DSP dram %x %x %x %x\n",
946 test_addr
, test_data
, data
,
949 return HPI6000_ERROR_INIT_SDRAM1
;
951 test_data
= test_data
<< 1;
953 /* test every Nth address in the DRAM */
954 #define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */
955 #define DRAM_INC 1024
956 test_addr
= 0x80000000;
958 for (i
= 0; i
< DRAM_SIZE_WORDS
; i
= i
+ DRAM_INC
) {
959 hpi_write_word(pdo
, test_addr
+ i
, test_data
);
962 test_addr
= 0x80000000;
964 for (i
= 0; i
< DRAM_SIZE_WORDS
; i
= i
+ DRAM_INC
) {
965 data
= hpi_read_word(pdo
, test_addr
+ i
);
966 if (data
!= test_data
) {
968 "DSP dram %x %x %x %x\n",
969 test_addr
+ i
, test_data
,
971 return HPI6000_ERROR_INIT_SDRAM2
;
978 /* write the DSP code down into the DSPs memory */
979 /*HpiDspCode_Open(nBootLoadFamily,&DspCode,pdwOsErrorCode); */
980 dsp_code
.ps_dev
= pao
->pci
.p_os_data
;
982 error
= hpi_dsp_code_open(boot_load_family
, &dsp_code
,
994 error
= hpi_dsp_code_read_word(&dsp_code
, &length
);
997 if (length
== 0xFFFFFFFF)
998 break; /* end of code */
1000 error
= hpi_dsp_code_read_word(&dsp_code
, &address
);
1003 error
= hpi_dsp_code_read_word(&dsp_code
, &type
);
1006 error
= hpi_dsp_code_read_block(length
, &dsp_code
,
1010 error
= hpi6000_dsp_block_write32(pao
, (u16
)dsp_index
,
1011 address
, pcode
, length
);
1017 hpi_dsp_code_close(&dsp_code
);
1020 /* verify that code was written correctly */
1021 /* this time through, assume no errors in DSP code file/array */
1022 hpi_dsp_code_rewind(&dsp_code
);
1029 hpi_dsp_code_read_word(&dsp_code
, &length
);
1030 if (length
== 0xFFFFFFFF)
1031 break; /* end of code */
1033 hpi_dsp_code_read_word(&dsp_code
, &address
);
1034 hpi_dsp_code_read_word(&dsp_code
, &type
);
1035 hpi_dsp_code_read_block(length
, &dsp_code
, &pcode
);
1037 for (i
= 0; i
< length
; i
++) {
1038 data
= hpi_read_word(pdo
, address
);
1039 if (data
!= *pcode
) {
1040 error
= HPI6000_ERROR_INIT_VERIFY
;
1041 HPI_DEBUG_LOG(ERROR
,
1042 "DSP verify %x %x %x %x\n",
1043 address
, *pcode
, data
,
1053 hpi_dsp_code_close(&dsp_code
);
1057 /* zero out the hostmailbox */
1059 u32 address
= HPI_HIF_ADDR(host_cmd
);
1060 for (i
= 0; i
< 4; i
++) {
1061 hpi_write_word(pdo
, address
, 0);
1065 /* write the DSP number into the hostmailbox */
1066 /* structure before starting the DSP */
1067 hpi_write_word(pdo
, HPI_HIF_ADDR(dsp_number
), dsp_index
);
1069 /* write the DSP adapter Info into the */
1070 /* hostmailbox before starting the DSP */
1072 hpi_write_word(pdo
, HPI_HIF_ADDR(adapter_info
),
1075 /* step 3. Start code by sending interrupt */
1076 iowrite32(0x00030003, pdo
->prHPI_control
);
1077 for (i
= 0; i
< 10000; i
++)
1078 delay
= ioread32(phw
->dw2040_HPICSR
+ HPI_RESET
);
1080 /* wait for a non-zero value in hostcmd -
1081 * indicating initialization is complete
1083 * Init could take a while if DSP checks SDRAM memory
1084 * Was 200000. Increased to 2000000 for ASI8801 so we
1085 * don't get 938 errors.
1090 read
= hpi_read_word(pdo
,
1091 HPI_HIF_ADDR(host_cmd
));
1093 && hpi6000_check_PCI2040_error_flag(pao
,
1098 /* The following is a workaround for bug #94:
1099 * Bluescreen on install and subsequent boots on a
1100 * DELL PowerEdge 600SC PC with 1.8GHz P4 and
1101 * ServerWorks chipset. Without this delay the system
1102 * locks up with a bluescreen (NOT GPF or pagefault).
1105 hpios_delay_micro_seconds(1000);
1108 return HPI6000_ERROR_INIT_NOACK
;
1110 /* read the DSP adapter Info from the */
1111 /* hostmailbox structure after starting the DSP */
1112 if (dsp_index
== 0) {
1113 /*u32 dwTestData=0; */
1118 HPI_HIF_ADDR(adapter_info
));
1119 if (HPI_ADAPTER_FAMILY_ASI
1120 (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER
1122 HPI_ADAPTER_FAMILY_ASI(0x6200))
1123 /* all 6200 cards have this many DSPs */
1126 /* test that the PLD is programmed */
1127 /* and we can read/write 24bits */
1128 #define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */
1130 switch (boot_load_family
) {
1131 case HPI_ADAPTER_FAMILY_ASI(0x6200):
1132 /* ASI6100/6200 has 24bit path to FPGA */
1134 /* ASI5100 uses AX6 code, */
1135 /* but has no PLD r/w register to test */
1136 if (HPI_ADAPTER_FAMILY_ASI(pao
->pci
.
1137 subsys_device_id
) ==
1138 HPI_ADAPTER_FAMILY_ASI(0x5100))
1141 case HPI_ADAPTER_FAMILY_ASI(0x8800):
1142 /* ASI8800 has 16bit path to FPGA */
1146 test_data
= 0xAAAAAA00L
& mask
;
1147 /* write to 24 bit Debug register (D31-D8) */
1148 hpi_write_word(pdo
, PLD_BASE_ADDRESS
+ 4L, test_data
);
1149 read
= hpi_read_word(pdo
,
1150 PLD_BASE_ADDRESS
+ 4L) & mask
;
1151 if (read
!= test_data
) {
1152 HPI_DEBUG_LOG(ERROR
, "PLD %x %x\n", test_data
,
1154 return HPI6000_ERROR_INIT_PLDTEST1
;
1156 test_data
= 0x55555500L
& mask
;
1157 hpi_write_word(pdo
, PLD_BASE_ADDRESS
+ 4L, test_data
);
1158 read
= hpi_read_word(pdo
,
1159 PLD_BASE_ADDRESS
+ 4L) & mask
;
1160 if (read
!= test_data
) {
1161 HPI_DEBUG_LOG(ERROR
, "PLD %x %x\n", test_data
,
1163 return HPI6000_ERROR_INIT_PLDTEST2
;
1170 #define PCI_TIMEOUT 100
1172 static int hpi_set_address(struct dsp_obj
*pdo
, u32 address
)
1174 u32 timeout
= PCI_TIMEOUT
;
1177 iowrite32(address
, pdo
->prHPI_address
);
1178 } while (hpi6000_check_PCI2040_error_flag(pdo
->pa_parent_adapter
,
1188 /* write one word to the HPI port */
1189 static void hpi_write_word(struct dsp_obj
*pdo
, u32 address
, u32 data
)
1191 if (hpi_set_address(pdo
, address
))
1193 iowrite32(data
, pdo
->prHPI_data
);
1196 /* read one word from the HPI port */
1197 static u32
hpi_read_word(struct dsp_obj
*pdo
, u32 address
)
1201 if (hpi_set_address(pdo
, address
))
1202 return 0; /*? no way to return error */
1204 /* take care of errata in revB DSP (2.0.1) */
1205 data
= ioread32(pdo
->prHPI_data
);
1209 /* write a block of 32bit words to the DSP HPI port using auto-inc mode */
1210 static void hpi_write_block(struct dsp_obj
*pdo
, u32 address
, u32
*pdata
,
1213 u16 length16
= length
- 1;
1218 if (hpi_set_address(pdo
, address
))
1221 iowrite32_rep(pdo
->prHPI_data_auto_inc
, pdata
, length16
);
1223 /* take care of errata in revB DSP (2.0.1) */
1224 /* must end with non auto-inc */
1225 iowrite32(*(pdata
+ length
- 1), pdo
->prHPI_data
);
1228 /** read a block of 32bit words from the DSP HPI port using auto-inc mode
1230 static void hpi_read_block(struct dsp_obj
*pdo
, u32 address
, u32
*pdata
,
1233 u16 length16
= length
- 1;
1238 if (hpi_set_address(pdo
, address
))
1241 ioread32_rep(pdo
->prHPI_data_auto_inc
, pdata
, length16
);
1243 /* take care of errata in revB DSP (2.0.1) */
1244 /* must end with non auto-inc */
1245 *(pdata
+ length
- 1) = ioread32(pdo
->prHPI_data
);
1248 static u16
hpi6000_dsp_block_write32(struct hpi_adapter_obj
*pao
,
1249 u16 dsp_index
, u32 hpi_address
, u32
*source
, u32 count
)
1251 struct dsp_obj
*pdo
=
1252 &(*(struct hpi_hw_obj
*)pao
->priv
).ado
[dsp_index
];
1253 u32 time_out
= PCI_TIMEOUT
;
1254 int c6711_burst_size
= 128;
1255 u32 local_hpi_address
= hpi_address
;
1256 int local_count
= count
;
1258 u32
*pdata
= source
;
1260 while (local_count
) {
1261 if (local_count
> c6711_burst_size
)
1262 xfer_size
= c6711_burst_size
;
1264 xfer_size
= local_count
;
1266 time_out
= PCI_TIMEOUT
;
1268 hpi_write_block(pdo
, local_hpi_address
, pdata
,
1270 } while (hpi6000_check_PCI2040_error_flag(pao
, H6WRITE
)
1276 local_hpi_address
+= sizeof(u32
) * xfer_size
;
1277 local_count
-= xfer_size
;
1286 static u16
hpi6000_dsp_block_read32(struct hpi_adapter_obj
*pao
,
1287 u16 dsp_index
, u32 hpi_address
, u32
*dest
, u32 count
)
1289 struct dsp_obj
*pdo
=
1290 &(*(struct hpi_hw_obj
*)pao
->priv
).ado
[dsp_index
];
1291 u32 time_out
= PCI_TIMEOUT
;
1292 int c6711_burst_size
= 16;
1293 u32 local_hpi_address
= hpi_address
;
1294 int local_count
= count
;
1299 while (local_count
) {
1300 if (local_count
> c6711_burst_size
)
1301 xfer_size
= c6711_burst_size
;
1303 xfer_size
= local_count
;
1305 time_out
= PCI_TIMEOUT
;
1307 hpi_read_block(pdo
, local_hpi_address
, pdata
,
1309 } while (hpi6000_check_PCI2040_error_flag(pao
, H6READ
)
1315 local_hpi_address
+= sizeof(u32
) * xfer_size
;
1316 local_count
-= xfer_size
;
1326 static short hpi6000_message_response_sequence(struct hpi_adapter_obj
*pao
,
1327 u16 dsp_index
, struct hpi_message
*phm
, struct hpi_response
*phr
)
1329 struct hpi_hw_obj
*phw
= (struct hpi_hw_obj
*)pao
->priv
;
1330 struct dsp_obj
*pdo
= &phw
->ado
[dsp_index
];
1338 /* does the DSP we are referencing exist? */
1339 if (dsp_index
>= phw
->num_dsp
)
1340 return HPI6000_ERROR_MSG_INVALID_DSP_INDEX
;
1342 ack
= hpi6000_wait_dsp_ack(pao
, dsp_index
, HPI_HIF_IDLE
);
1343 if (ack
& HPI_HIF_ERROR_MASK
) {
1345 return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT
;
1347 pao
->dsp_crashed
= 0;
1349 /* send the message */
1351 /* get the address and size */
1352 if (phw
->message_buffer_address_on_dsp
== 0) {
1357 HPI_HIF_ADDR(message_buffer_address
));
1358 phw
->message_buffer_address_on_dsp
= address
;
1359 } while (hpi6000_check_PCI2040_error_flag(pao
, H6READ
)
1362 return HPI6000_ERROR_MSG_GET_ADR
;
1364 address
= phw
->message_buffer_address_on_dsp
;
1366 /* dwLength = sizeof(struct hpi_message); */
1370 p_data
= (u32
*)phm
;
1371 if (hpi6000_dsp_block_write32(pao
, dsp_index
, address
, p_data
,
1373 return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32
;
1375 if (hpi6000_send_host_command(pao
, dsp_index
, HPI_HIF_GET_RESP
))
1376 return HPI6000_ERROR_MSG_RESP_GETRESPCMD
;
1377 hpi6000_send_dsp_interrupt(pdo
);
1379 ack
= hpi6000_wait_dsp_ack(pao
, dsp_index
, HPI_HIF_GET_RESP
);
1380 if (ack
& HPI_HIF_ERROR_MASK
)
1381 return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK
;
1383 /* get the address and size */
1384 if (phw
->response_buffer_address_on_dsp
== 0) {
1389 HPI_HIF_ADDR(response_buffer_address
));
1390 } while (hpi6000_check_PCI2040_error_flag(pao
, H6READ
)
1392 phw
->response_buffer_address_on_dsp
= address
;
1395 return HPI6000_ERROR_RESP_GET_ADR
;
1397 address
= phw
->response_buffer_address_on_dsp
;
1399 /* read the length of the response back from the DSP */
1402 length
= hpi_read_word(pdo
, HPI_HIF_ADDR(length
));
1403 } while (hpi6000_check_PCI2040_error_flag(pao
, H6READ
) && --timeout
);
1405 length
= sizeof(struct hpi_response
);
1408 p_data
= (u32
*)phr
;
1409 if (hpi6000_dsp_block_read32(pao
, dsp_index
, address
, p_data
,
1411 return HPI6000_ERROR_MSG_RESP_BLOCKREAD32
;
1413 /* set i/f back to idle */
1414 if (hpi6000_send_host_command(pao
, dsp_index
, HPI_HIF_IDLE
))
1415 return HPI6000_ERROR_MSG_RESP_IDLECMD
;
1416 hpi6000_send_dsp_interrupt(pdo
);
1418 error
= hpi_validate_response(phm
, phr
);
1422 /* have to set up the below defines to match stuff in the MAP file */
1424 #define MSG_ADDRESS (HPI_HIF_BASE+0x18)
1425 #define MSG_LENGTH 11
1426 #define RESP_ADDRESS (HPI_HIF_BASE+0x44)
1427 #define RESP_LENGTH 16
1428 #define QUEUE_START (HPI_HIF_BASE+0x88)
1429 #define QUEUE_SIZE 0x8000
1431 static short hpi6000_send_data_check_adr(u32 address
, u32 length_in_dwords
)
1433 /*#define CHECKING // comment this line in to enable checking */
1435 if (address
< (u32
)MSG_ADDRESS
)
1437 if (address
> (u32
)(QUEUE_START
+ QUEUE_SIZE
))
1439 if ((address
+ (length_in_dwords
<< 2)) >
1440 (u32
)(QUEUE_START
+ QUEUE_SIZE
))
1444 (void)length_in_dwords
;
1449 static short hpi6000_send_data(struct hpi_adapter_obj
*pao
, u16 dsp_index
,
1450 struct hpi_message
*phm
, struct hpi_response
*phr
)
1452 struct dsp_obj
*pdo
=
1453 &(*(struct hpi_hw_obj
*)pao
->priv
).ado
[dsp_index
];
1456 u32 length
, address
;
1457 u32
*p_data
= (u32
*)phm
->u
.d
.u
.data
.pb_data
;
1462 /* round dwDataSize down to nearest 4 bytes */
1463 while ((data_sent
< (phm
->u
.d
.u
.data
.data_size
& ~3L))
1465 ack
= hpi6000_wait_dsp_ack(pao
, dsp_index
, HPI_HIF_IDLE
);
1466 if (ack
& HPI_HIF_ERROR_MASK
)
1467 return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT
;
1469 if (hpi6000_send_host_command(pao
, dsp_index
,
1471 return HPI6000_ERROR_SEND_DATA_CMD
;
1473 hpi6000_send_dsp_interrupt(pdo
);
1475 ack
= hpi6000_wait_dsp_ack(pao
, dsp_index
, HPI_HIF_SEND_DATA
);
1477 if (ack
& HPI_HIF_ERROR_MASK
)
1478 return HPI6000_ERROR_SEND_DATA_ACK
;
1481 /* get the address and size */
1482 address
= hpi_read_word(pdo
, HPI_HIF_ADDR(address
));
1483 /* DSP returns number of DWORDS */
1484 length
= hpi_read_word(pdo
, HPI_HIF_ADDR(length
));
1485 } while (hpi6000_check_PCI2040_error_flag(pao
, H6READ
));
1487 if (!hpi6000_send_data_check_adr(address
, length
))
1488 return HPI6000_ERROR_SEND_DATA_ADR
;
1490 /* send the data. break data into 512 DWORD blocks (2K bytes)
1491 * and send using block write. 2Kbytes is the max as this is the
1492 * memory window given to the HPI data register by the PCI2040
1501 if (hpi6000_dsp_block_write32(pao
, dsp_index
,
1502 address
, p_data
, blk_len
))
1503 return HPI6000_ERROR_SEND_DATA_WRITE
;
1504 address
+= blk_len
* 4;
1510 if (hpi6000_send_host_command(pao
, dsp_index
, HPI_HIF_IDLE
))
1511 return HPI6000_ERROR_SEND_DATA_IDLECMD
;
1513 hpi6000_send_dsp_interrupt(pdo
);
1515 data_sent
+= length
* 4;
1518 return HPI6000_ERROR_SEND_DATA_TIMEOUT
;
1522 static short hpi6000_get_data(struct hpi_adapter_obj
*pao
, u16 dsp_index
,
1523 struct hpi_message
*phm
, struct hpi_response
*phr
)
1525 struct dsp_obj
*pdo
=
1526 &(*(struct hpi_hw_obj
*)pao
->priv
).ado
[dsp_index
];
1529 u32 length
, address
;
1530 u32
*p_data
= (u32
*)phm
->u
.d
.u
.data
.pb_data
;
1532 (void)phr
; /* this parameter not used! */
1534 /* round dwDataSize down to nearest 4 bytes */
1535 while (data_got
< (phm
->u
.d
.u
.data
.data_size
& ~3L)) {
1536 ack
= hpi6000_wait_dsp_ack(pao
, dsp_index
, HPI_HIF_IDLE
);
1537 if (ack
& HPI_HIF_ERROR_MASK
)
1538 return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT
;
1540 if (hpi6000_send_host_command(pao
, dsp_index
,
1542 return HPI6000_ERROR_GET_DATA_CMD
;
1543 hpi6000_send_dsp_interrupt(pdo
);
1545 ack
= hpi6000_wait_dsp_ack(pao
, dsp_index
, HPI_HIF_GET_DATA
);
1547 if (ack
& HPI_HIF_ERROR_MASK
)
1548 return HPI6000_ERROR_GET_DATA_ACK
;
1550 /* get the address and size */
1552 address
= hpi_read_word(pdo
, HPI_HIF_ADDR(address
));
1553 length
= hpi_read_word(pdo
, HPI_HIF_ADDR(length
));
1554 } while (hpi6000_check_PCI2040_error_flag(pao
, H6READ
));
1563 if (hpi6000_dsp_block_read32(pao
, dsp_index
,
1564 address
, p_data
, blk_len
))
1565 return HPI6000_ERROR_GET_DATA_READ
;
1566 address
+= blk_len
* 4;
1572 if (hpi6000_send_host_command(pao
, dsp_index
, HPI_HIF_IDLE
))
1573 return HPI6000_ERROR_GET_DATA_IDLECMD
;
1574 hpi6000_send_dsp_interrupt(pdo
);
1576 data_got
+= length
* 4;
1581 static void hpi6000_send_dsp_interrupt(struct dsp_obj
*pdo
)
1583 iowrite32(0x00030003, pdo
->prHPI_control
); /* DSPINT */
1586 static short hpi6000_send_host_command(struct hpi_adapter_obj
*pao
,
1587 u16 dsp_index
, u32 host_cmd
)
1589 struct dsp_obj
*pdo
=
1590 &(*(struct hpi_hw_obj
*)pao
->priv
).ado
[dsp_index
];
1591 u32 timeout
= TIMEOUT
;
1595 hpi_write_word(pdo
, HPI_HIF_ADDR(host_cmd
), host_cmd
);
1596 /* flush the FIFO */
1597 hpi_set_address(pdo
, HPI_HIF_ADDR(host_cmd
));
1598 } while (hpi6000_check_PCI2040_error_flag(pao
, H6WRITE
) && --timeout
);
1600 /* reset the interrupt bit */
1601 iowrite32(0x00040004, pdo
->prHPI_control
);
1609 /* if the PCI2040 has recorded an HPI timeout, reset the error and return 1 */
1610 static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj
*pao
,
1615 struct hpi_hw_obj
*phw
= (struct hpi_hw_obj
*)pao
->priv
;
1617 /* read the error bits from the PCI2040 */
1618 hPI_error
= ioread32(phw
->dw2040_HPICSR
+ HPI_ERROR_REPORT
);
1620 /* reset the error flag */
1621 iowrite32(0L, phw
->dw2040_HPICSR
+ HPI_ERROR_REPORT
);
1622 phw
->pCI2040HPI_error_count
++;
1623 if (read_or_write
== 1)
1624 gw_pci_read_asserts
++; /************* inc global */
1626 gw_pci_write_asserts
++;
1632 static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj
*pao
, u16 dsp_index
,
1635 struct dsp_obj
*pdo
=
1636 &(*(struct hpi_hw_obj
*)pao
->priv
).ado
[dsp_index
];
1641 /* wait for host interrupt to signal ack is ready */
1644 hPIC
= ioread32(pdo
->prHPI_control
);
1645 if (hPIC
& 0x04) /* 0x04 = HINT from DSP */
1649 return HPI_HIF_ERROR_MASK
;
1651 /* wait for dwAckValue */
1654 /* read the ack mailbox */
1655 ack
= hpi_read_word(pdo
, HPI_HIF_ADDR(dsp_ack
));
1656 if (ack
== ack_value
)
1658 if ((ack
& HPI_HIF_ERROR_MASK
)
1659 && !hpi6000_check_PCI2040_error_flag(pao
, H6READ
))
1661 /*for (i=0;i<1000;i++) */
1664 if (ack
& HPI_HIF_ERROR_MASK
)
1665 /* indicates bad read from DSP -
1666 typically 0xffffff is read for some reason */
1667 ack
= HPI_HIF_ERROR_MASK
;
1670 ack
= HPI_HIF_ERROR_MASK
;
1674 static short hpi6000_update_control_cache(struct hpi_adapter_obj
*pao
,
1675 struct hpi_message
*phm
)
1677 const u16 dsp_index
= 0;
1678 struct hpi_hw_obj
*phw
= (struct hpi_hw_obj
*)pao
->priv
;
1679 struct dsp_obj
*pdo
= &phw
->ado
[dsp_index
];
1681 u32 cache_dirty_flag
;
1684 hpios_dsplock_lock(pao
);
1689 hpi_read_word((struct dsp_obj
*)pdo
,
1690 HPI_HIF_ADDR(control_cache_is_dirty
));
1691 } while (hpi6000_check_PCI2040_error_flag(pao
, H6READ
) && --timeout
);
1693 err
= HPI6000_ERROR_CONTROL_CACHE_PARAMS
;
1697 if (cache_dirty_flag
) {
1698 /* read the cached controls */
1703 if (pdo
->control_cache_address_on_dsp
== 0) {
1706 hpi_read_word((struct dsp_obj
*)pdo
,
1707 HPI_HIF_ADDR(control_cache_address
));
1709 length
= hpi_read_word((struct dsp_obj
*)pdo
,
1711 (control_cache_size_in_bytes
));
1712 } while (hpi6000_check_PCI2040_error_flag(pao
, H6READ
)
1715 err
= HPI6000_ERROR_CONTROL_CACHE_ADDRLEN
;
1718 pdo
->control_cache_address_on_dsp
= address
;
1719 pdo
->control_cache_length_on_dsp
= length
;
1721 address
= pdo
->control_cache_address_on_dsp
;
1722 length
= pdo
->control_cache_length_on_dsp
;
1725 if (hpi6000_dsp_block_read32(pao
, dsp_index
, address
,
1726 (u32
*)&phw
->control_cache
[0],
1727 length
/ sizeof(u32
))) {
1728 err
= HPI6000_ERROR_CONTROL_CACHE_READ
;
1732 hpi_write_word((struct dsp_obj
*)pdo
,
1733 HPI_HIF_ADDR(control_cache_is_dirty
), 0);
1734 /* flush the FIFO */
1735 hpi_set_address(pdo
, HPI_HIF_ADDR(host_cmd
));
1736 } while (hpi6000_check_PCI2040_error_flag(pao
, H6WRITE
)
1739 err
= HPI6000_ERROR_CONTROL_CACHE_FLUSH
;
1747 hpios_dsplock_unlock(pao
);
1751 /** Get dsp index for multi DSP adapters only */
1752 static u16
get_dsp_index(struct hpi_adapter_obj
*pao
, struct hpi_message
*phm
)
1755 switch (phm
->object
) {
1756 case HPI_OBJ_ISTREAM
:
1757 if (phm
->obj_index
< 2)
1760 case HPI_OBJ_PROFILE
:
1761 ret
= phm
->obj_index
;
1769 /** Complete transaction with DSP
1771 Send message, get response, send or get stream data if any.
1773 static void hw_message(struct hpi_adapter_obj
*pao
, struct hpi_message
*phm
,
1774 struct hpi_response
*phr
)
1778 u16 num_dsp
= ((struct hpi_hw_obj
*)pao
->priv
)->num_dsp
;
1779 hpios_dsplock_lock(pao
);
1784 dsp_index
= get_dsp_index(pao
, phm
);
1786 /* is this checked on the DSP anyway? */
1787 if ((phm
->function
== HPI_ISTREAM_GROUP_ADD
)
1788 || (phm
->function
== HPI_OSTREAM_GROUP_ADD
)) {
1789 struct hpi_message hm
;
1791 hm
.obj_index
= phm
->u
.d
.u
.stream
.stream_index
;
1792 hm
.object
= phm
->u
.d
.u
.stream
.object_type
;
1793 add_index
= get_dsp_index(pao
, &hm
);
1794 if (add_index
!= dsp_index
) {
1795 phr
->error
= HPI_ERROR_NO_INTERDSP_GROUPS
;
1800 error
= hpi6000_message_response_sequence(pao
, dsp_index
, phm
, phr
);
1802 /* maybe an error response */
1804 /* something failed in the HPI/DSP interface */
1806 /* just the header of the response is valid */
1807 phr
->size
= sizeof(struct hpi_response_header
);
1811 if (phr
->error
!= 0) /* something failed in the DSP */
1814 switch (phm
->function
) {
1815 case HPI_OSTREAM_WRITE
:
1816 case HPI_ISTREAM_ANC_WRITE
:
1817 error
= hpi6000_send_data(pao
, dsp_index
, phm
, phr
);
1819 case HPI_ISTREAM_READ
:
1820 case HPI_OSTREAM_ANC_READ
:
1821 error
= hpi6000_get_data(pao
, dsp_index
, phm
, phr
);
1823 case HPI_ADAPTER_GET_ASSERT
:
1824 phr
->u
.a
.adapter_index
= 0; /* dsp 0 default */
1826 if (!phr
->u
.a
.adapter_type
) {
1827 /* no assert from dsp 0, check dsp 1 */
1828 error
= hpi6000_message_response_sequence(pao
,
1830 phr
->u
.a
.adapter_index
= 1;
1839 hpios_dsplock_unlock(pao
);