1 /******************************************************************************
3 AudioScience HPI driver
4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of version 2 of the GNU General Public License as
8 published by the Free Software Foundation;
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 Hardware Programming Interface (HPI) for AudioScience
20 ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters.
21 These PCI and PCIe bus adapters are based on a
22 TMS320C6205 PCI bus mastering DSP,
23 and (except ASI50xx) TI TMS320C6xxx floating point DSP
26 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
28 (C) Copyright AudioScience Inc. 1998-2010
29 *******************************************************************************/
30 #define SOURCEFILE_NAME "hpi6205.c"
32 #include "hpi_internal.h"
33 #include "hpimsginit.h"
39 /*****************************************************************************/
40 /* HPI6205 specific error codes */
41 #define HPI6205_ERROR_BASE 1000
42 /*#define HPI6205_ERROR_MEM_ALLOC 1001 */
43 #define HPI6205_ERROR_6205_NO_IRQ 1002
44 #define HPI6205_ERROR_6205_INIT_FAILED 1003
45 /*#define HPI6205_ERROR_MISSING_DSPCODE 1004 */
46 #define HPI6205_ERROR_UNKNOWN_PCI_DEVICE 1005
47 #define HPI6205_ERROR_6205_REG 1006
48 #define HPI6205_ERROR_6205_DSPPAGE 1007
49 #define HPI6205_ERROR_BAD_DSPINDEX 1008
50 #define HPI6205_ERROR_C6713_HPIC 1009
51 #define HPI6205_ERROR_C6713_HPIA 1010
52 #define HPI6205_ERROR_C6713_PLL 1011
53 #define HPI6205_ERROR_DSP_INTMEM 1012
54 #define HPI6205_ERROR_DSP_EXTMEM 1013
55 #define HPI6205_ERROR_DSP_PLD 1014
56 #define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015
57 #define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016
58 #define HPI6205_ERROR_6205_EEPROM 1017
59 #define HPI6205_ERROR_DSP_EMIF 1018
61 #define hpi6205_error(dsp_index, err) (err)
62 /*****************************************************************************/
63 /* for C6205 PCI i/f */
64 /* Host Status Register (HSR) bitfields */
65 #define C6205_HSR_INTSRC 0x01
66 #define C6205_HSR_INTAVAL 0x02
67 #define C6205_HSR_INTAM 0x04
68 #define C6205_HSR_CFGERR 0x08
69 #define C6205_HSR_EEREAD 0x10
70 /* Host-to-DSP Control Register (HDCR) bitfields */
71 #define C6205_HDCR_WARMRESET 0x01
72 #define C6205_HDCR_DSPINT 0x02
73 #define C6205_HDCR_PCIBOOT 0x04
74 /* DSP Page Register (DSPP) bitfields, */
75 /* defines 4 Mbyte page that BAR0 points to */
76 #define C6205_DSPP_MAP1 0x400
78 /* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP.
79 * BAR1 maps to non-prefetchable 8 Mbyte memory block
80 * of DSP memory mapped registers (starting at 0x01800000).
81 * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this
82 * needs to be added to the BAR1 base address set in the PCI config reg
84 #define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L)
85 #define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET)
86 #define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4)
87 #define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8)
89 /* used to control LED (revA) and reset C6713 (revB) */
90 #define C6205_BAR0_TIMER1_CTL (0x01980000L)
92 /* For first 6713 in CE1 space, using DA17,16,2 */
93 #define HPICL_ADDR 0x01400000L
94 #define HPICH_ADDR 0x01400004L
95 #define HPIAL_ADDR 0x01410000L
96 #define HPIAH_ADDR 0x01410004L
97 #define HPIDIL_ADDR 0x01420000L
98 #define HPIDIH_ADDR 0x01420004L
99 #define HPIDL_ADDR 0x01430000L
100 #define HPIDH_ADDR 0x01430004L
102 #define C6713_EMIF_GCTL 0x01800000
103 #define C6713_EMIF_CE1 0x01800004
104 #define C6713_EMIF_CE0 0x01800008
105 #define C6713_EMIF_CE2 0x01800010
106 #define C6713_EMIF_CE3 0x01800014
107 #define C6713_EMIF_SDRAMCTL 0x01800018
108 #define C6713_EMIF_SDRAMTIMING 0x0180001C
109 #define C6713_EMIF_SDRAMEXT 0x01800020
119 struct consistent_dma_area h_locked_mem
;
120 struct bus_master_interface
*p_interface_buffer
;
122 u16 flag_outstream_just_reset
[HPI_MAX_STREAMS
];
123 /* a non-NULL handle means there is an HPI allocated buffer */
124 struct consistent_dma_area instream_host_buffers
[HPI_MAX_STREAMS
];
125 struct consistent_dma_area outstream_host_buffers
[HPI_MAX_STREAMS
];
126 /* non-zero size means a buffer exists, may be external */
127 u32 instream_host_buffer_size
[HPI_MAX_STREAMS
];
128 u32 outstream_host_buffer_size
[HPI_MAX_STREAMS
];
130 struct consistent_dma_area h_control_cache
;
131 struct consistent_dma_area h_async_event_buffer
;
132 /* struct hpi_control_cache_single *pControlCache; */
133 struct hpi_async_event
*p_async_event_buffer
;
134 struct hpi_control_cache
*p_cache
;
137 /*****************************************************************************/
138 /* local prototypes */
140 #define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write)
142 static int wait_dsp_ack(struct hpi_hw_obj
*phw
, int state
, int timeout_us
);
144 static void send_dsp_command(struct hpi_hw_obj
*phw
, int cmd
);
146 static u16
adapter_boot_load_dsp(struct hpi_adapter_obj
*pao
,
147 u32
*pos_error_code
);
149 static u16
message_response_sequence(struct hpi_adapter_obj
*pao
,
150 struct hpi_message
*phm
, struct hpi_response
*phr
);
152 static void hw_message(struct hpi_adapter_obj
*pao
, struct hpi_message
*phm
,
153 struct hpi_response
*phr
);
155 #define HPI6205_TIMEOUT 1000000
157 static void subsys_create_adapter(struct hpi_message
*phm
,
158 struct hpi_response
*phr
);
159 static void subsys_delete_adapter(struct hpi_message
*phm
,
160 struct hpi_response
*phr
);
162 static u16
create_adapter_obj(struct hpi_adapter_obj
*pao
,
163 u32
*pos_error_code
);
165 static void delete_adapter_obj(struct hpi_adapter_obj
*pao
);
167 static void outstream_host_buffer_allocate(struct hpi_adapter_obj
*pao
,
168 struct hpi_message
*phm
, struct hpi_response
*phr
);
170 static void outstream_host_buffer_get_info(struct hpi_adapter_obj
*pao
,
171 struct hpi_message
*phm
, struct hpi_response
*phr
);
173 static void outstream_host_buffer_free(struct hpi_adapter_obj
*pao
,
174 struct hpi_message
*phm
, struct hpi_response
*phr
);
175 static void outstream_write(struct hpi_adapter_obj
*pao
,
176 struct hpi_message
*phm
, struct hpi_response
*phr
);
178 static void outstream_get_info(struct hpi_adapter_obj
*pao
,
179 struct hpi_message
*phm
, struct hpi_response
*phr
);
181 static void outstream_start(struct hpi_adapter_obj
*pao
,
182 struct hpi_message
*phm
, struct hpi_response
*phr
);
184 static void outstream_open(struct hpi_adapter_obj
*pao
,
185 struct hpi_message
*phm
, struct hpi_response
*phr
);
187 static void outstream_reset(struct hpi_adapter_obj
*pao
,
188 struct hpi_message
*phm
, struct hpi_response
*phr
);
190 static void instream_host_buffer_allocate(struct hpi_adapter_obj
*pao
,
191 struct hpi_message
*phm
, struct hpi_response
*phr
);
193 static void instream_host_buffer_get_info(struct hpi_adapter_obj
*pao
,
194 struct hpi_message
*phm
, struct hpi_response
*phr
);
196 static void instream_host_buffer_free(struct hpi_adapter_obj
*pao
,
197 struct hpi_message
*phm
, struct hpi_response
*phr
);
199 static void instream_read(struct hpi_adapter_obj
*pao
,
200 struct hpi_message
*phm
, struct hpi_response
*phr
);
202 static void instream_get_info(struct hpi_adapter_obj
*pao
,
203 struct hpi_message
*phm
, struct hpi_response
*phr
);
205 static void instream_start(struct hpi_adapter_obj
*pao
,
206 struct hpi_message
*phm
, struct hpi_response
*phr
);
208 static u32
boot_loader_read_mem32(struct hpi_adapter_obj
*pao
, int dsp_index
,
211 static u16
boot_loader_write_mem32(struct hpi_adapter_obj
*pao
, int dsp_index
,
212 u32 address
, u32 data
);
214 static u16
boot_loader_config_emif(struct hpi_adapter_obj
*pao
,
217 static u16
boot_loader_test_memory(struct hpi_adapter_obj
*pao
, int dsp_index
,
218 u32 address
, u32 length
);
220 static u16
boot_loader_test_internal_memory(struct hpi_adapter_obj
*pao
,
223 static u16
boot_loader_test_external_memory(struct hpi_adapter_obj
*pao
,
226 static u16
boot_loader_test_pld(struct hpi_adapter_obj
*pao
, int dsp_index
);
228 /*****************************************************************************/
230 static void subsys_message(struct hpi_message
*phm
, struct hpi_response
*phr
)
233 switch (phm
->function
) {
234 case HPI_SUBSYS_OPEN
:
235 case HPI_SUBSYS_CLOSE
:
236 case HPI_SUBSYS_GET_INFO
:
237 case HPI_SUBSYS_DRIVER_UNLOAD
:
238 case HPI_SUBSYS_DRIVER_LOAD
:
239 case HPI_SUBSYS_FIND_ADAPTERS
:
240 /* messages that should not get here */
241 phr
->error
= HPI_ERROR_UNIMPLEMENTED
;
243 case HPI_SUBSYS_CREATE_ADAPTER
:
244 subsys_create_adapter(phm
, phr
);
246 case HPI_SUBSYS_DELETE_ADAPTER
:
247 subsys_delete_adapter(phm
, phr
);
250 phr
->error
= HPI_ERROR_INVALID_FUNC
;
255 static void control_message(struct hpi_adapter_obj
*pao
,
256 struct hpi_message
*phm
, struct hpi_response
*phr
)
259 struct hpi_hw_obj
*phw
= pao
->priv
;
261 switch (phm
->function
) {
262 case HPI_CONTROL_GET_STATE
:
263 if (pao
->has_control_cache
) {
264 rmb(); /* make sure we see updates DM_aed from DSP */
265 if (hpi_check_control_cache(phw
->p_cache
, phm
, phr
))
268 hw_message(pao
, phm
, phr
);
270 case HPI_CONTROL_GET_INFO
:
271 hw_message(pao
, phm
, phr
);
273 case HPI_CONTROL_SET_STATE
:
274 hw_message(pao
, phm
, phr
);
275 if (pao
->has_control_cache
)
276 hpi_sync_control_cache(phw
->p_cache
, phm
, phr
);
279 phr
->error
= HPI_ERROR_INVALID_FUNC
;
284 static void adapter_message(struct hpi_adapter_obj
*pao
,
285 struct hpi_message
*phm
, struct hpi_response
*phr
)
287 switch (phm
->function
) {
289 hw_message(pao
, phm
, phr
);
294 static void outstream_message(struct hpi_adapter_obj
*pao
,
295 struct hpi_message
*phm
, struct hpi_response
*phr
)
298 if (phm
->obj_index
>= HPI_MAX_STREAMS
) {
299 phr
->error
= HPI_ERROR_INVALID_STREAM
;
300 HPI_DEBUG_LOG(WARNING
,
301 "message referencing invalid stream %d "
302 "on adapter index %d\n", phm
->obj_index
,
307 switch (phm
->function
) {
308 case HPI_OSTREAM_WRITE
:
309 outstream_write(pao
, phm
, phr
);
311 case HPI_OSTREAM_GET_INFO
:
312 outstream_get_info(pao
, phm
, phr
);
314 case HPI_OSTREAM_HOSTBUFFER_ALLOC
:
315 outstream_host_buffer_allocate(pao
, phm
, phr
);
317 case HPI_OSTREAM_HOSTBUFFER_GET_INFO
:
318 outstream_host_buffer_get_info(pao
, phm
, phr
);
320 case HPI_OSTREAM_HOSTBUFFER_FREE
:
321 outstream_host_buffer_free(pao
, phm
, phr
);
323 case HPI_OSTREAM_START
:
324 outstream_start(pao
, phm
, phr
);
326 case HPI_OSTREAM_OPEN
:
327 outstream_open(pao
, phm
, phr
);
329 case HPI_OSTREAM_RESET
:
330 outstream_reset(pao
, phm
, phr
);
333 hw_message(pao
, phm
, phr
);
338 static void instream_message(struct hpi_adapter_obj
*pao
,
339 struct hpi_message
*phm
, struct hpi_response
*phr
)
342 if (phm
->obj_index
>= HPI_MAX_STREAMS
) {
343 phr
->error
= HPI_ERROR_INVALID_STREAM
;
344 HPI_DEBUG_LOG(WARNING
,
345 "message referencing invalid stream %d "
346 "on adapter index %d\n", phm
->obj_index
,
351 switch (phm
->function
) {
352 case HPI_ISTREAM_READ
:
353 instream_read(pao
, phm
, phr
);
355 case HPI_ISTREAM_GET_INFO
:
356 instream_get_info(pao
, phm
, phr
);
358 case HPI_ISTREAM_HOSTBUFFER_ALLOC
:
359 instream_host_buffer_allocate(pao
, phm
, phr
);
361 case HPI_ISTREAM_HOSTBUFFER_GET_INFO
:
362 instream_host_buffer_get_info(pao
, phm
, phr
);
364 case HPI_ISTREAM_HOSTBUFFER_FREE
:
365 instream_host_buffer_free(pao
, phm
, phr
);
367 case HPI_ISTREAM_START
:
368 instream_start(pao
, phm
, phr
);
371 hw_message(pao
, phm
, phr
);
376 /*****************************************************************************/
377 /** Entry point to this HPI backend
378 * All calls to the HPI start here
380 void HPI_6205(struct hpi_message
*phm
, struct hpi_response
*phr
)
382 struct hpi_adapter_obj
*pao
= NULL
;
384 /* subsytem messages are processed by every HPI.
385 * All other messages are ignored unless the adapter index matches
386 * an adapter in the HPI
388 HPI_DEBUG_LOG(DEBUG
, "HPI obj=%d, func=%d\n", phm
->object
,
391 /* if Dsp has crashed then do not communicate with it any more */
392 if (phm
->object
!= HPI_OBJ_SUBSYSTEM
) {
393 pao
= hpi_find_adapter(phm
->adapter_index
);
396 " %d,%d refused, for another HPI?\n",
397 phm
->object
, phm
->function
);
401 if ((pao
->dsp_crashed
>= 10)
402 && (phm
->function
!= HPI_ADAPTER_DEBUG_READ
)) {
403 /* allow last resort debug read even after crash */
404 hpi_init_response(phr
, phm
->object
, phm
->function
,
405 HPI_ERROR_DSP_HARDWARE
);
406 HPI_DEBUG_LOG(WARNING
, " %d,%d dsp crashed.\n",
407 phm
->object
, phm
->function
);
412 /* Init default response */
413 if (phm
->function
!= HPI_SUBSYS_CREATE_ADAPTER
)
414 hpi_init_response(phr
, phm
->object
, phm
->function
,
415 HPI_ERROR_PROCESSING_MESSAGE
);
417 HPI_DEBUG_LOG(VERBOSE
, "start of switch\n");
419 case HPI_TYPE_MESSAGE
:
420 switch (phm
->object
) {
421 case HPI_OBJ_SUBSYSTEM
:
422 subsys_message(phm
, phr
);
425 case HPI_OBJ_ADAPTER
:
427 sizeof(struct hpi_response_header
) +
428 sizeof(struct hpi_adapter_res
);
429 adapter_message(pao
, phm
, phr
);
432 case HPI_OBJ_CONTROLEX
:
433 case HPI_OBJ_CONTROL
:
434 control_message(pao
, phm
, phr
);
437 case HPI_OBJ_OSTREAM
:
438 outstream_message(pao
, phm
, phr
);
441 case HPI_OBJ_ISTREAM
:
442 instream_message(pao
, phm
, phr
);
446 hw_message(pao
, phm
, phr
);
452 phr
->error
= HPI_ERROR_INVALID_TYPE
;
457 /*****************************************************************************/
460 /** Create an adapter object and initialise it based on resource information
461 * passed in in the message
462 * *** NOTE - you cannot use this function AND the FindAdapters function at the
463 * same time, the application must use only one of them to get the adapters ***
465 static void subsys_create_adapter(struct hpi_message
*phm
,
466 struct hpi_response
*phr
)
468 /* create temp adapter obj, because we don't know what index yet */
469 struct hpi_adapter_obj ao
;
473 HPI_DEBUG_LOG(DEBUG
, " subsys_create_adapter\n");
475 memset(&ao
, 0, sizeof(ao
));
477 /* this HPI only creates adapters for TI/PCI devices */
478 if (phm
->u
.s
.resource
.bus_type
!= HPI_BUS_PCI
)
480 if (phm
->u
.s
.resource
.r
.pci
->vendor_id
!= HPI_PCI_VENDOR_ID_TI
)
482 if (phm
->u
.s
.resource
.r
.pci
->device_id
!= HPI_PCI_DEV_ID_DSP6205
)
485 ao
.priv
= kmalloc(sizeof(struct hpi_hw_obj
), GFP_KERNEL
);
487 HPI_DEBUG_LOG(ERROR
, "cant get mem for adapter object\n");
488 phr
->error
= HPI_ERROR_MEMORY_ALLOC
;
491 memset(ao
.priv
, 0, sizeof(struct hpi_hw_obj
));
493 ao
.pci
= *phm
->u
.s
.resource
.r
.pci
;
494 err
= create_adapter_obj(&ao
, &os_error_code
);
496 err
= hpi_add_adapter(&ao
);
498 phr
->u
.s
.data
= os_error_code
;
499 delete_adapter_obj(&ao
);
504 phr
->u
.s
.aw_adapter_list
[ao
.index
] = ao
.adapter_type
;
505 phr
->u
.s
.adapter_index
= ao
.index
;
506 phr
->u
.s
.num_adapters
++;
510 /** delete an adapter - required by WDM driver */
511 static void subsys_delete_adapter(struct hpi_message
*phm
,
512 struct hpi_response
*phr
)
514 struct hpi_adapter_obj
*pao
;
515 struct hpi_hw_obj
*phw
;
517 pao
= hpi_find_adapter(phm
->adapter_index
);
519 phr
->error
= HPI_ERROR_INVALID_OBJ_INDEX
;
522 phw
= (struct hpi_hw_obj
*)pao
->priv
;
523 /* reset adapter h/w */
525 boot_loader_write_mem32(pao
, 0, C6205_BAR0_TIMER1_CTL
, 0);
527 iowrite32(C6205_HDCR_WARMRESET
, phw
->prHDCR
);
529 delete_adapter_obj(pao
);
533 /** Create adapter object
534 allocate buffers, bootload DSPs, initialise control cache
536 static u16
create_adapter_obj(struct hpi_adapter_obj
*pao
,
539 struct hpi_hw_obj
*phw
= pao
->priv
;
540 struct bus_master_interface
*interface
;
542 #ifndef HPI6205_NO_HSR_POLL
543 u32 time_out
= HPI6205_TIMEOUT
;
549 /* init error reporting */
550 pao
->dsp_crashed
= 0;
552 for (i
= 0; i
< HPI_MAX_STREAMS
; i
++)
553 phw
->flag_outstream_just_reset
[i
] = 1;
555 /* The C6205 memory area 1 is 8Mbyte window into DSP registers */
557 pao
->pci
.ap_mem_base
[1] +
558 C6205_BAR1_HSR
/ sizeof(*pao
->pci
.ap_mem_base
[1]);
560 pao
->pci
.ap_mem_base
[1] +
561 C6205_BAR1_HDCR
/ sizeof(*pao
->pci
.ap_mem_base
[1]);
563 pao
->pci
.ap_mem_base
[1] +
564 C6205_BAR1_DSPP
/ sizeof(*pao
->pci
.ap_mem_base
[1]);
566 pao
->has_control_cache
= 0;
568 if (hpios_locked_mem_alloc(&phw
->h_locked_mem
,
569 sizeof(struct bus_master_interface
),
571 phw
->p_interface_buffer
= NULL
;
572 else if (hpios_locked_mem_get_virt_addr(&phw
->h_locked_mem
,
573 (void *)&phw
->p_interface_buffer
))
574 phw
->p_interface_buffer
= NULL
;
576 HPI_DEBUG_LOG(DEBUG
, "interface buffer address %p\n",
577 phw
->p_interface_buffer
);
579 if (phw
->p_interface_buffer
) {
580 memset((void *)phw
->p_interface_buffer
, 0,
581 sizeof(struct bus_master_interface
));
582 phw
->p_interface_buffer
->dsp_ack
= H620_HIF_UNKNOWN
;
585 err
= adapter_boot_load_dsp(pao
, pos_error_code
);
587 /* no need to clean up as SubSysCreateAdapter */
588 /* calls DeleteAdapter on error. */
591 HPI_DEBUG_LOG(INFO
, "load DSP code OK\n");
593 /* allow boot load even if mem alloc wont work */
594 if (!phw
->p_interface_buffer
)
595 return hpi6205_error(0, HPI_ERROR_MEMORY_ALLOC
);
597 interface
= phw
->p_interface_buffer
;
599 #ifndef HPI6205_NO_HSR_POLL
600 /* wait for first interrupt indicating the DSP init is done */
601 time_out
= HPI6205_TIMEOUT
* 10;
603 while (((temp1
& C6205_HSR_INTSRC
) == 0) && --time_out
)
604 temp1
= ioread32(phw
->prHSR
);
606 if (temp1
& C6205_HSR_INTSRC
)
608 "interrupt confirming DSP code running OK\n");
611 "timed out waiting for interrupt "
612 "confirming DSP code running\n");
613 return hpi6205_error(0, HPI6205_ERROR_6205_NO_IRQ
);
616 /* reset the interrupt */
617 iowrite32(C6205_HSR_INTSRC
, phw
->prHSR
);
620 /* make sure the DSP has started ok */
621 if (!wait_dsp_ack(phw
, H620_HIF_RESET
, HPI6205_TIMEOUT
* 10)) {
622 HPI_DEBUG_LOG(ERROR
, "timed out waiting reset state \n");
623 return hpi6205_error(0, HPI6205_ERROR_6205_INIT_FAILED
);
625 /* Note that *pao, *phw are zeroed after allocation,
626 * so pointers and flags are NULL by default.
627 * Allocate bus mastering control cache buffer and tell the DSP about it
629 if (interface
->control_cache
.number_of_controls
) {
630 void *p_control_cache_virtual
;
632 err
= hpios_locked_mem_alloc(&phw
->h_control_cache
,
633 interface
->control_cache
.size_in_bytes
,
636 err
= hpios_locked_mem_get_virt_addr(&phw
->
637 h_control_cache
, &p_control_cache_virtual
);
639 memset(p_control_cache_virtual
, 0,
640 interface
->control_cache
.size_in_bytes
);
643 hpi_alloc_control_cache(interface
->
644 control_cache
.number_of_controls
,
645 interface
->control_cache
.size_in_bytes
,
646 (struct hpi_control_cache_info
*)
647 p_control_cache_virtual
);
650 err
= hpios_locked_mem_get_phys_addr(&phw
->
651 h_control_cache
, &phys_addr
);
652 interface
->control_cache
.physical_address32
=
657 pao
->has_control_cache
= 1;
659 if (hpios_locked_mem_valid(&phw
->h_control_cache
))
660 hpios_locked_mem_free(&phw
->h_control_cache
);
661 pao
->has_control_cache
= 0;
664 /* allocate bus mastering async buffer and tell the DSP about it */
665 if (interface
->async_buffer
.b
.size
) {
666 err
= hpios_locked_mem_alloc(&phw
->h_async_event_buffer
,
667 interface
->async_buffer
.b
.size
*
668 sizeof(struct hpi_async_event
), pao
->pci
.p_os_data
);
670 err
= hpios_locked_mem_get_virt_addr
671 (&phw
->h_async_event_buffer
, (void *)
672 &phw
->p_async_event_buffer
);
674 memset((void *)phw
->p_async_event_buffer
, 0,
675 interface
->async_buffer
.b
.size
*
676 sizeof(struct hpi_async_event
));
678 err
= hpios_locked_mem_get_phys_addr
679 (&phw
->h_async_event_buffer
, &phys_addr
);
680 interface
->async_buffer
.physical_address32
=
684 if (hpios_locked_mem_valid(&phw
->
685 h_async_event_buffer
)) {
686 hpios_locked_mem_free
687 (&phw
->h_async_event_buffer
);
688 phw
->p_async_event_buffer
= NULL
;
692 send_dsp_command(phw
, H620_HIF_IDLE
);
695 struct hpi_message hM
;
696 struct hpi_response hR
;
699 HPI_DEBUG_LOG(VERBOSE
, "init ADAPTER_GET_INFO\n");
700 memset(&hM
, 0, sizeof(hM
));
701 hM
.type
= HPI_TYPE_MESSAGE
;
702 hM
.size
= sizeof(hM
);
703 hM
.object
= HPI_OBJ_ADAPTER
;
704 hM
.function
= HPI_ADAPTER_GET_INFO
;
705 hM
.adapter_index
= 0;
706 memset(&hR
, 0, sizeof(hR
));
707 hR
.size
= sizeof(hR
);
709 err
= message_response_sequence(pao
, &hM
, &hR
);
711 HPI_DEBUG_LOG(ERROR
, "message transport error %d\n",
718 pao
->adapter_type
= hR
.u
.a
.adapter_type
;
719 pao
->index
= hR
.u
.a
.adapter_index
;
721 max_streams
= hR
.u
.a
.num_outstreams
+ hR
.u
.a
.num_instreams
;
723 hpios_locked_mem_prepare((max_streams
* 6) / 10, max_streams
,
724 65536, pao
->pci
.p_os_data
);
726 HPI_DEBUG_LOG(VERBOSE
,
727 "got adapter info type %x index %d serial %d\n",
728 hR
.u
.a
.adapter_type
, hR
.u
.a
.adapter_index
,
729 hR
.u
.a
.serial_number
);
732 pao
->open
= 0; /* upon creation the adapter is closed */
734 HPI_DEBUG_LOG(INFO
, "bootload DSP OK\n");
738 /** Free memory areas allocated by adapter
739 * this routine is called from SubSysDeleteAdapter,
740 * and SubSysCreateAdapter if duplicate index
742 static void delete_adapter_obj(struct hpi_adapter_obj
*pao
)
744 struct hpi_hw_obj
*phw
;
749 if (hpios_locked_mem_valid(&phw
->h_async_event_buffer
)) {
750 hpios_locked_mem_free(&phw
->h_async_event_buffer
);
751 phw
->p_async_event_buffer
= NULL
;
754 if (hpios_locked_mem_valid(&phw
->h_control_cache
)) {
755 hpios_locked_mem_free(&phw
->h_control_cache
);
756 hpi_free_control_cache(phw
->p_cache
);
759 if (hpios_locked_mem_valid(&phw
->h_locked_mem
)) {
760 hpios_locked_mem_free(&phw
->h_locked_mem
);
761 phw
->p_interface_buffer
= NULL
;
764 for (i
= 0; i
< HPI_MAX_STREAMS
; i
++)
765 if (hpios_locked_mem_valid(&phw
->instream_host_buffers
[i
])) {
766 hpios_locked_mem_free(&phw
->instream_host_buffers
[i
]);
767 /*?phw->InStreamHostBuffers[i] = NULL; */
768 phw
->instream_host_buffer_size
[i
] = 0;
771 for (i
= 0; i
< HPI_MAX_STREAMS
; i
++)
772 if (hpios_locked_mem_valid(&phw
->outstream_host_buffers
[i
])) {
773 hpios_locked_mem_free(&phw
->outstream_host_buffers
775 phw
->outstream_host_buffer_size
[i
] = 0;
778 hpios_locked_mem_unprepare(pao
->pci
.p_os_data
);
780 hpi_delete_adapter(pao
);
784 /*****************************************************************************/
785 /* OutStream Host buffer functions */
787 /** Allocate or attach buffer for busmastering
789 static void outstream_host_buffer_allocate(struct hpi_adapter_obj
*pao
,
790 struct hpi_message
*phm
, struct hpi_response
*phr
)
793 u32 command
= phm
->u
.d
.u
.buffer
.command
;
794 struct hpi_hw_obj
*phw
= pao
->priv
;
795 struct bus_master_interface
*interface
= phw
->p_interface_buffer
;
797 hpi_init_response(phr
, phm
->object
, phm
->function
, 0);
799 if (command
== HPI_BUFFER_CMD_EXTERNAL
800 || command
== HPI_BUFFER_CMD_INTERNAL_ALLOC
) {
801 /* ALLOC phase, allocate a buffer with power of 2 size,
802 get its bus address for PCI bus mastering
804 phm
->u
.d
.u
.buffer
.buffer_size
=
805 roundup_pow_of_two(phm
->u
.d
.u
.buffer
.buffer_size
);
806 /* return old size and allocated size,
807 so caller can detect change */
808 phr
->u
.d
.u
.stream_info
.data_available
=
809 phw
->outstream_host_buffer_size
[phm
->obj_index
];
810 phr
->u
.d
.u
.stream_info
.buffer_size
=
811 phm
->u
.d
.u
.buffer
.buffer_size
;
813 if (phw
->outstream_host_buffer_size
[phm
->obj_index
] ==
814 phm
->u
.d
.u
.buffer
.buffer_size
) {
815 /* Same size, no action required */
819 if (hpios_locked_mem_valid(&phw
->outstream_host_buffers
[phm
->
821 hpios_locked_mem_free(&phw
->outstream_host_buffers
824 err
= hpios_locked_mem_alloc(&phw
->outstream_host_buffers
825 [phm
->obj_index
], phm
->u
.d
.u
.buffer
.buffer_size
,
829 phr
->error
= HPI_ERROR_INVALID_DATASIZE
;
830 phw
->outstream_host_buffer_size
[phm
->obj_index
] = 0;
834 err
= hpios_locked_mem_get_phys_addr
835 (&phw
->outstream_host_buffers
[phm
->obj_index
],
836 &phm
->u
.d
.u
.buffer
.pci_address
);
837 /* get the phys addr into msg for single call alloc caller
838 * needs to do this for split alloc (or use the same message)
839 * return the phy address for split alloc in the respose too
841 phr
->u
.d
.u
.stream_info
.auxiliary_data_available
=
842 phm
->u
.d
.u
.buffer
.pci_address
;
845 hpios_locked_mem_free(&phw
->outstream_host_buffers
847 phw
->outstream_host_buffer_size
[phm
->obj_index
] = 0;
848 phr
->error
= HPI_ERROR_MEMORY_ALLOC
;
853 if (command
== HPI_BUFFER_CMD_EXTERNAL
854 || command
== HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER
) {
855 /* GRANT phase. Set up the BBM status, tell the DSP about
856 the buffer so it can start using BBM.
858 struct hpi_hostbuffer_status
*status
;
860 if (phm
->u
.d
.u
.buffer
.buffer_size
& (phm
->u
.d
.u
.buffer
.
863 "buffer size must be 2^N not %d\n",
864 phm
->u
.d
.u
.buffer
.buffer_size
);
865 phr
->error
= HPI_ERROR_INVALID_DATASIZE
;
868 phw
->outstream_host_buffer_size
[phm
->obj_index
] =
869 phm
->u
.d
.u
.buffer
.buffer_size
;
870 status
= &interface
->outstream_host_buffer_status
[phm
->
872 status
->samples_processed
= 0;
873 status
->stream_state
= HPI_STATE_STOPPED
;
874 status
->dSP_index
= 0;
875 status
->host_index
= status
->dSP_index
;
876 status
->size_in_bytes
= phm
->u
.d
.u
.buffer
.buffer_size
;
878 hw_message(pao
, phm
, phr
);
881 && hpios_locked_mem_valid(&phw
->
882 outstream_host_buffers
[phm
->obj_index
])) {
883 hpios_locked_mem_free(&phw
->outstream_host_buffers
885 phw
->outstream_host_buffer_size
[phm
->obj_index
] = 0;
890 static void outstream_host_buffer_get_info(struct hpi_adapter_obj
*pao
,
891 struct hpi_message
*phm
, struct hpi_response
*phr
)
893 struct hpi_hw_obj
*phw
= pao
->priv
;
894 struct bus_master_interface
*interface
= phw
->p_interface_buffer
;
895 struct hpi_hostbuffer_status
*status
;
898 if (hpios_locked_mem_valid(&phw
->outstream_host_buffers
[phm
->
900 if (hpios_locked_mem_get_virt_addr(&phw
->
901 outstream_host_buffers
[phm
->obj_index
],
902 (void *)&p_bbm_data
)) {
903 phr
->error
= HPI_ERROR_INVALID_OPERATION
;
906 status
= &interface
->outstream_host_buffer_status
[phm
->
908 hpi_init_response(phr
, HPI_OBJ_OSTREAM
,
909 HPI_OSTREAM_HOSTBUFFER_GET_INFO
, 0);
910 phr
->u
.d
.u
.hostbuffer_info
.p_buffer
= p_bbm_data
;
911 phr
->u
.d
.u
.hostbuffer_info
.p_status
= status
;
913 hpi_init_response(phr
, HPI_OBJ_OSTREAM
,
914 HPI_OSTREAM_HOSTBUFFER_GET_INFO
,
915 HPI_ERROR_INVALID_OPERATION
);
919 static void outstream_host_buffer_free(struct hpi_adapter_obj
*pao
,
920 struct hpi_message
*phm
, struct hpi_response
*phr
)
922 struct hpi_hw_obj
*phw
= pao
->priv
;
923 u32 command
= phm
->u
.d
.u
.buffer
.command
;
925 if (phw
->outstream_host_buffer_size
[phm
->obj_index
]) {
926 if (command
== HPI_BUFFER_CMD_EXTERNAL
927 || command
== HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER
) {
928 phw
->outstream_host_buffer_size
[phm
->obj_index
] = 0;
929 hw_message(pao
, phm
, phr
);
930 /* Tell adapter to stop using the host buffer. */
932 if (command
== HPI_BUFFER_CMD_EXTERNAL
933 || command
== HPI_BUFFER_CMD_INTERNAL_FREE
)
934 hpios_locked_mem_free(&phw
->outstream_host_buffers
937 /* Should HPI_ERROR_INVALID_OPERATION be returned
938 if no host buffer is allocated? */
940 hpi_init_response(phr
, HPI_OBJ_OSTREAM
,
941 HPI_OSTREAM_HOSTBUFFER_FREE
, 0);
945 static long outstream_get_space_available(struct hpi_hostbuffer_status
948 return status
->size_in_bytes
- ((long)(status
->host_index
) -
949 (long)(status
->dSP_index
));
952 static void outstream_write(struct hpi_adapter_obj
*pao
,
953 struct hpi_message
*phm
, struct hpi_response
*phr
)
955 struct hpi_hw_obj
*phw
= pao
->priv
;
956 struct bus_master_interface
*interface
= phw
->p_interface_buffer
;
957 struct hpi_hostbuffer_status
*status
;
958 long space_available
;
960 if (!phw
->outstream_host_buffer_size
[phm
->obj_index
]) {
961 /* there is no BBM buffer, write via message */
962 hw_message(pao
, phm
, phr
);
966 hpi_init_response(phr
, phm
->object
, phm
->function
, 0);
967 status
= &interface
->outstream_host_buffer_status
[phm
->obj_index
];
969 if (phw
->flag_outstream_just_reset
[phm
->obj_index
]) {
970 /* Format can only change after reset. Must tell DSP. */
971 u16 function
= phm
->function
;
972 phw
->flag_outstream_just_reset
[phm
->obj_index
] = 0;
973 phm
->function
= HPI_OSTREAM_SET_FORMAT
;
974 hw_message(pao
, phm
, phr
); /* send the format to the DSP */
975 phm
->function
= function
;
980 if (phw
->flag_outstream_just_reset
[phm
->obj_index
]) {
981 /* First OutStremWrite() call following reset will write data to the
982 adapter's buffers, reducing delay before stream can start
984 int partial_write
= 0;
985 unsigned int original_size
= 0;
987 /* Send the first buffer to the DSP the old way. */
988 /* Limit size of first transfer - */
989 /* expect that this will not usually be triggered. */
990 if (phm
->u
.d
.u
.data
.data_size
> HPI6205_SIZEOF_DATA
) {
992 original_size
= phm
->u
.d
.u
.data
.data_size
;
993 phm
->u
.d
.u
.data
.data_size
= HPI6205_SIZEOF_DATA
;
996 phm
->function
= HPI_OSTREAM_WRITE
;
997 hw_message(pao
, phm
, phr
);
998 /* update status information that the DSP would typically
999 * update (and will update next time the DSP
1000 * buffer update task reads data from the host BBM buffer)
1002 status
->auxiliary_data_available
= phm
->u
.d
.u
.data
.data_size
;
1003 status
->host_index
+= phm
->u
.d
.u
.data
.data_size
;
1004 status
->dSP_index
+= phm
->u
.d
.u
.data
.data_size
;
1006 /* if we did a full write, we can return from here. */
1010 /* tweak buffer parameters and let the rest of the */
1011 /* buffer land in internal BBM buffer */
1012 phm
->u
.d
.u
.data
.data_size
=
1013 original_size
- HPI6205_SIZEOF_DATA
;
1014 phm
->u
.d
.u
.data
.pb_data
+= HPI6205_SIZEOF_DATA
;
1018 space_available
= outstream_get_space_available(status
);
1019 if (space_available
< (long)phm
->u
.d
.u
.data
.data_size
) {
1020 phr
->error
= HPI_ERROR_INVALID_DATASIZE
;
1024 /* HostBuffers is used to indicate host buffer is internally allocated.
1025 otherwise, assumed external, data written externally */
1026 if (phm
->u
.d
.u
.data
.pb_data
1027 && hpios_locked_mem_valid(&phw
->outstream_host_buffers
[phm
->
1031 u8
*p_app_data
= (u8
*)phm
->u
.d
.u
.data
.pb_data
;
1033 if (hpios_locked_mem_get_virt_addr(&phw
->
1034 outstream_host_buffers
[phm
->obj_index
],
1035 (void *)&p_bbm_data
)) {
1036 phr
->error
= HPI_ERROR_INVALID_OPERATION
;
1041 or enough to fit from current to end of BBM buffer */
1043 min(phm
->u
.d
.u
.data
.data_size
,
1044 status
->size_in_bytes
-
1045 (status
->host_index
& (status
->size_in_bytes
- 1)));
1048 (status
->host_index
& (status
->size_in_bytes
- 1)),
1049 p_app_data
, l_first_write
);
1050 /* remaining data if any */
1051 memcpy(p_bbm_data
, p_app_data
+ l_first_write
,
1052 phm
->u
.d
.u
.data
.data_size
- l_first_write
);
1054 status
->host_index
+= phm
->u
.d
.u
.data
.data_size
;
1057 static void outstream_get_info(struct hpi_adapter_obj
*pao
,
1058 struct hpi_message
*phm
, struct hpi_response
*phr
)
1060 struct hpi_hw_obj
*phw
= pao
->priv
;
1061 struct bus_master_interface
*interface
= phw
->p_interface_buffer
;
1062 struct hpi_hostbuffer_status
*status
;
1064 if (!phw
->outstream_host_buffer_size
[phm
->obj_index
]) {
1065 hw_message(pao
, phm
, phr
);
1069 hpi_init_response(phr
, phm
->object
, phm
->function
, 0);
1071 status
= &interface
->outstream_host_buffer_status
[phm
->obj_index
];
1073 phr
->u
.d
.u
.stream_info
.state
= (u16
)status
->stream_state
;
1074 phr
->u
.d
.u
.stream_info
.samples_transferred
=
1075 status
->samples_processed
;
1076 phr
->u
.d
.u
.stream_info
.buffer_size
= status
->size_in_bytes
;
1077 phr
->u
.d
.u
.stream_info
.data_available
=
1078 status
->size_in_bytes
- outstream_get_space_available(status
);
1079 phr
->u
.d
.u
.stream_info
.auxiliary_data_available
=
1080 status
->auxiliary_data_available
;
1083 static void outstream_start(struct hpi_adapter_obj
*pao
,
1084 struct hpi_message
*phm
, struct hpi_response
*phr
)
1086 hw_message(pao
, phm
, phr
);
1089 static void outstream_reset(struct hpi_adapter_obj
*pao
,
1090 struct hpi_message
*phm
, struct hpi_response
*phr
)
1092 struct hpi_hw_obj
*phw
= pao
->priv
;
1093 phw
->flag_outstream_just_reset
[phm
->obj_index
] = 1;
1094 hw_message(pao
, phm
, phr
);
1097 static void outstream_open(struct hpi_adapter_obj
*pao
,
1098 struct hpi_message
*phm
, struct hpi_response
*phr
)
1100 outstream_reset(pao
, phm
, phr
);
1103 /*****************************************************************************/
1104 /* InStream Host buffer functions */
1106 static void instream_host_buffer_allocate(struct hpi_adapter_obj
*pao
,
1107 struct hpi_message
*phm
, struct hpi_response
*phr
)
1110 u32 command
= phm
->u
.d
.u
.buffer
.command
;
1111 struct hpi_hw_obj
*phw
= pao
->priv
;
1112 struct bus_master_interface
*interface
= phw
->p_interface_buffer
;
1114 hpi_init_response(phr
, phm
->object
, phm
->function
, 0);
1116 if (command
== HPI_BUFFER_CMD_EXTERNAL
1117 || command
== HPI_BUFFER_CMD_INTERNAL_ALLOC
) {
1119 phm
->u
.d
.u
.buffer
.buffer_size
=
1120 roundup_pow_of_two(phm
->u
.d
.u
.buffer
.buffer_size
);
1121 phr
->u
.d
.u
.stream_info
.data_available
=
1122 phw
->instream_host_buffer_size
[phm
->obj_index
];
1123 phr
->u
.d
.u
.stream_info
.buffer_size
=
1124 phm
->u
.d
.u
.buffer
.buffer_size
;
1126 if (phw
->instream_host_buffer_size
[phm
->obj_index
] ==
1127 phm
->u
.d
.u
.buffer
.buffer_size
) {
1128 /* Same size, no action required */
1132 if (hpios_locked_mem_valid(&phw
->instream_host_buffers
[phm
->
1134 hpios_locked_mem_free(&phw
->instream_host_buffers
1137 err
= hpios_locked_mem_alloc(&phw
->instream_host_buffers
[phm
->
1138 obj_index
], phm
->u
.d
.u
.buffer
.buffer_size
,
1139 pao
->pci
.p_os_data
);
1142 phr
->error
= HPI_ERROR_INVALID_DATASIZE
;
1143 phw
->instream_host_buffer_size
[phm
->obj_index
] = 0;
1147 err
= hpios_locked_mem_get_phys_addr
1148 (&phw
->instream_host_buffers
[phm
->obj_index
],
1149 &phm
->u
.d
.u
.buffer
.pci_address
);
1150 /* get the phys addr into msg for single call alloc. Caller
1151 needs to do this for split alloc so return the phy address */
1152 phr
->u
.d
.u
.stream_info
.auxiliary_data_available
=
1153 phm
->u
.d
.u
.buffer
.pci_address
;
1155 hpios_locked_mem_free(&phw
->instream_host_buffers
1157 phw
->instream_host_buffer_size
[phm
->obj_index
] = 0;
1158 phr
->error
= HPI_ERROR_MEMORY_ALLOC
;
1163 if (command
== HPI_BUFFER_CMD_EXTERNAL
1164 || command
== HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER
) {
1165 struct hpi_hostbuffer_status
*status
;
1167 if (phm
->u
.d
.u
.buffer
.buffer_size
& (phm
->u
.d
.u
.buffer
.
1169 HPI_DEBUG_LOG(ERROR
,
1170 "buffer size must be 2^N not %d\n",
1171 phm
->u
.d
.u
.buffer
.buffer_size
);
1172 phr
->error
= HPI_ERROR_INVALID_DATASIZE
;
1176 phw
->instream_host_buffer_size
[phm
->obj_index
] =
1177 phm
->u
.d
.u
.buffer
.buffer_size
;
1178 status
= &interface
->instream_host_buffer_status
[phm
->
1180 status
->samples_processed
= 0;
1181 status
->stream_state
= HPI_STATE_STOPPED
;
1182 status
->dSP_index
= 0;
1183 status
->host_index
= status
->dSP_index
;
1184 status
->size_in_bytes
= phm
->u
.d
.u
.buffer
.buffer_size
;
1186 hw_message(pao
, phm
, phr
);
1188 && hpios_locked_mem_valid(&phw
->
1189 instream_host_buffers
[phm
->obj_index
])) {
1190 hpios_locked_mem_free(&phw
->instream_host_buffers
1192 phw
->instream_host_buffer_size
[phm
->obj_index
] = 0;
1197 static void instream_host_buffer_get_info(struct hpi_adapter_obj
*pao
,
1198 struct hpi_message
*phm
, struct hpi_response
*phr
)
1200 struct hpi_hw_obj
*phw
= pao
->priv
;
1201 struct bus_master_interface
*interface
= phw
->p_interface_buffer
;
1202 struct hpi_hostbuffer_status
*status
;
1205 if (hpios_locked_mem_valid(&phw
->instream_host_buffers
[phm
->
1207 if (hpios_locked_mem_get_virt_addr(&phw
->
1208 instream_host_buffers
[phm
->obj_index
],
1209 (void *)&p_bbm_data
)) {
1210 phr
->error
= HPI_ERROR_INVALID_OPERATION
;
1213 status
= &interface
->instream_host_buffer_status
[phm
->
1215 hpi_init_response(phr
, HPI_OBJ_ISTREAM
,
1216 HPI_ISTREAM_HOSTBUFFER_GET_INFO
, 0);
1217 phr
->u
.d
.u
.hostbuffer_info
.p_buffer
= p_bbm_data
;
1218 phr
->u
.d
.u
.hostbuffer_info
.p_status
= status
;
1220 hpi_init_response(phr
, HPI_OBJ_ISTREAM
,
1221 HPI_ISTREAM_HOSTBUFFER_GET_INFO
,
1222 HPI_ERROR_INVALID_OPERATION
);
1226 static void instream_host_buffer_free(struct hpi_adapter_obj
*pao
,
1227 struct hpi_message
*phm
, struct hpi_response
*phr
)
1229 struct hpi_hw_obj
*phw
= pao
->priv
;
1230 u32 command
= phm
->u
.d
.u
.buffer
.command
;
1232 if (phw
->instream_host_buffer_size
[phm
->obj_index
]) {
1233 if (command
== HPI_BUFFER_CMD_EXTERNAL
1234 || command
== HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER
) {
1235 phw
->instream_host_buffer_size
[phm
->obj_index
] = 0;
1236 hw_message(pao
, phm
, phr
);
1239 if (command
== HPI_BUFFER_CMD_EXTERNAL
1240 || command
== HPI_BUFFER_CMD_INTERNAL_FREE
)
1241 hpios_locked_mem_free(&phw
->instream_host_buffers
1245 /* Should HPI_ERROR_INVALID_OPERATION be returned
1246 if no host buffer is allocated? */
1247 hpi_init_response(phr
, HPI_OBJ_ISTREAM
,
1248 HPI_ISTREAM_HOSTBUFFER_FREE
, 0);
1254 static void instream_start(struct hpi_adapter_obj
*pao
,
1255 struct hpi_message
*phm
, struct hpi_response
*phr
)
1257 hw_message(pao
, phm
, phr
);
1260 static long instream_get_bytes_available(struct hpi_hostbuffer_status
*status
)
1262 return (long)(status
->dSP_index
) - (long)(status
->host_index
);
1265 static void instream_read(struct hpi_adapter_obj
*pao
,
1266 struct hpi_message
*phm
, struct hpi_response
*phr
)
1268 struct hpi_hw_obj
*phw
= pao
->priv
;
1269 struct bus_master_interface
*interface
= phw
->p_interface_buffer
;
1270 struct hpi_hostbuffer_status
*status
;
1271 long data_available
;
1274 u8
*p_app_data
= (u8
*)phm
->u
.d
.u
.data
.pb_data
;
1276 if (!phw
->instream_host_buffer_size
[phm
->obj_index
]) {
1277 hw_message(pao
, phm
, phr
);
1280 hpi_init_response(phr
, phm
->object
, phm
->function
, 0);
1282 status
= &interface
->instream_host_buffer_status
[phm
->obj_index
];
1283 data_available
= instream_get_bytes_available(status
);
1284 if (data_available
< (long)phm
->u
.d
.u
.data
.data_size
) {
1285 phr
->error
= HPI_ERROR_INVALID_DATASIZE
;
1289 if (hpios_locked_mem_valid(&phw
->instream_host_buffers
[phm
->
1291 if (hpios_locked_mem_get_virt_addr(&phw
->
1292 instream_host_buffers
[phm
->obj_index
],
1293 (void *)&p_bbm_data
)) {
1294 phr
->error
= HPI_ERROR_INVALID_OPERATION
;
1299 or enough to fit from current to end of BBM buffer */
1301 min(phm
->u
.d
.u
.data
.data_size
,
1302 status
->size_in_bytes
-
1303 (status
->host_index
& (status
->size_in_bytes
- 1)));
1307 (status
->host_index
& (status
->size_in_bytes
- 1)),
1309 /* remaining data if any */
1310 memcpy(p_app_data
+ l_first_read
, p_bbm_data
,
1311 phm
->u
.d
.u
.data
.data_size
- l_first_read
);
1313 status
->host_index
+= phm
->u
.d
.u
.data
.data_size
;
1316 static void instream_get_info(struct hpi_adapter_obj
*pao
,
1317 struct hpi_message
*phm
, struct hpi_response
*phr
)
1319 struct hpi_hw_obj
*phw
= pao
->priv
;
1320 struct bus_master_interface
*interface
= phw
->p_interface_buffer
;
1321 struct hpi_hostbuffer_status
*status
;
1322 if (!phw
->instream_host_buffer_size
[phm
->obj_index
]) {
1323 hw_message(pao
, phm
, phr
);
1327 status
= &interface
->instream_host_buffer_status
[phm
->obj_index
];
1329 hpi_init_response(phr
, phm
->object
, phm
->function
, 0);
1331 phr
->u
.d
.u
.stream_info
.state
= (u16
)status
->stream_state
;
1332 phr
->u
.d
.u
.stream_info
.samples_transferred
=
1333 status
->samples_processed
;
1334 phr
->u
.d
.u
.stream_info
.buffer_size
= status
->size_in_bytes
;
1335 phr
->u
.d
.u
.stream_info
.data_available
=
1336 instream_get_bytes_available(status
);
1337 phr
->u
.d
.u
.stream_info
.auxiliary_data_available
=
1338 status
->auxiliary_data_available
;
1341 /*****************************************************************************/
1343 #define HPI6205_MAX_FILES_TO_LOAD 2
1345 static u16
adapter_boot_load_dsp(struct hpi_adapter_obj
*pao
,
1346 u32
*pos_error_code
)
1348 struct hpi_hw_obj
*phw
= pao
->priv
;
1349 struct dsp_code dsp_code
;
1350 u16 boot_code_id
[HPI6205_MAX_FILES_TO_LOAD
];
1351 u16 firmware_id
= pao
->pci
.subsys_device_id
;
1356 boot_code_id
[0] = HPI_ADAPTER_ASI(0x6205);
1358 /* special cases where firmware_id != subsys ID */
1359 switch (firmware_id
) {
1360 case HPI_ADAPTER_FAMILY_ASI(0x5000):
1361 boot_code_id
[0] = firmware_id
;
1364 case HPI_ADAPTER_FAMILY_ASI(0x5300):
1365 case HPI_ADAPTER_FAMILY_ASI(0x5400):
1366 case HPI_ADAPTER_FAMILY_ASI(0x6300):
1367 firmware_id
= HPI_ADAPTER_FAMILY_ASI(0x6400);
1369 case HPI_ADAPTER_FAMILY_ASI(0x5600):
1370 case HPI_ADAPTER_FAMILY_ASI(0x6500):
1371 firmware_id
= HPI_ADAPTER_FAMILY_ASI(0x6600);
1374 boot_code_id
[1] = firmware_id
;
1376 /* reset DSP by writing a 1 to the WARMRESET bit */
1377 temp
= C6205_HDCR_WARMRESET
;
1378 iowrite32(temp
, phw
->prHDCR
);
1379 hpios_delay_micro_seconds(1000);
1381 /* check that PCI i/f was configured by EEPROM */
1382 temp
= ioread32(phw
->prHSR
);
1383 if ((temp
& (C6205_HSR_CFGERR
| C6205_HSR_EEREAD
)) !=
1385 return hpi6205_error(0, HPI6205_ERROR_6205_EEPROM
);
1387 /* disable PINTA interrupt */
1388 iowrite32(temp
, phw
->prHSR
);
1390 /* check control register reports PCI boot mode */
1391 temp
= ioread32(phw
->prHDCR
);
1392 if (!(temp
& C6205_HDCR_PCIBOOT
))
1393 return hpi6205_error(0, HPI6205_ERROR_6205_REG
);
1395 /* try writing a couple of numbers to the DSP page register */
1396 /* and reading them back. */
1398 iowrite32(temp
, phw
->prDSPP
);
1399 if ((temp
| C6205_DSPP_MAP1
) != ioread32(phw
->prDSPP
))
1400 return hpi6205_error(0, HPI6205_ERROR_6205_DSPPAGE
);
1402 iowrite32(temp
, phw
->prDSPP
);
1403 if ((temp
| C6205_DSPP_MAP1
) != ioread32(phw
->prDSPP
))
1404 return hpi6205_error(0, HPI6205_ERROR_6205_DSPPAGE
);
1406 iowrite32(temp
, phw
->prDSPP
);
1407 if ((temp
| C6205_DSPP_MAP1
) != ioread32(phw
->prDSPP
))
1408 return hpi6205_error(0, HPI6205_ERROR_6205_DSPPAGE
);
1409 /* reset DSP page to the correct number */
1411 iowrite32(temp
, phw
->prDSPP
);
1412 if ((temp
| C6205_DSPP_MAP1
) != ioread32(phw
->prDSPP
))
1413 return hpi6205_error(0, HPI6205_ERROR_6205_DSPPAGE
);
1416 /* release 6713 from reset before 6205 is bootloaded.
1417 This ensures that the EMIF is inactive,
1418 and the 6713 HPI gets the correct bootmode etc
1420 if (boot_code_id
[1] != 0) {
1421 /* DSP 1 is a C6713 */
1422 /* CLKX0 <- '1' release the C6205 bootmode pulldowns */
1423 boot_loader_write_mem32(pao
, 0, (0x018C0024L
), 0x00002202);
1424 hpios_delay_micro_seconds(100);
1425 /* Reset the 6713 #1 - revB */
1426 boot_loader_write_mem32(pao
, 0, C6205_BAR0_TIMER1_CTL
, 0);
1428 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1429 boot_loader_read_mem32(pao
, 0, 0);
1431 hpios_delay_micro_seconds(100);
1432 /* Release C6713 from reset - revB */
1433 boot_loader_write_mem32(pao
, 0, C6205_BAR0_TIMER1_CTL
, 4);
1434 hpios_delay_micro_seconds(100);
1437 for (dsp
= 0; dsp
< HPI6205_MAX_FILES_TO_LOAD
; dsp
++) {
1438 /* is there a DSP to load? */
1439 if (boot_code_id
[dsp
] == 0)
1442 err
= boot_loader_config_emif(pao
, dsp
);
1446 err
= boot_loader_test_internal_memory(pao
, dsp
);
1450 err
= boot_loader_test_external_memory(pao
, dsp
);
1454 err
= boot_loader_test_pld(pao
, dsp
);
1458 /* write the DSP code down into the DSPs memory */
1459 dsp_code
.ps_dev
= pao
->pci
.p_os_data
;
1460 err
= hpi_dsp_code_open(boot_code_id
[dsp
], &dsp_code
,
1471 err
= hpi_dsp_code_read_word(&dsp_code
, &length
);
1474 if (length
== 0xFFFFFFFF)
1475 break; /* end of code */
1477 err
= hpi_dsp_code_read_word(&dsp_code
, &address
);
1480 err
= hpi_dsp_code_read_word(&dsp_code
, &type
);
1483 err
= hpi_dsp_code_read_block(length
, &dsp_code
,
1487 for (i
= 0; i
< (int)length
; i
++) {
1488 err
= boot_loader_write_mem32(pao
, dsp
,
1492 /* dummy read every 4 words */
1493 /* for 6205 advisory 1.4.4 */
1495 boot_loader_read_mem32(pao
, dsp
,
1503 hpi_dsp_code_close(&dsp_code
);
1508 hpi_dsp_code_rewind(&dsp_code
);
1516 hpi_dsp_code_read_word(&dsp_code
, &length
);
1517 if (length
== 0xFFFFFFFF)
1518 break; /* end of code */
1520 hpi_dsp_code_read_word(&dsp_code
, &address
);
1521 hpi_dsp_code_read_word(&dsp_code
, &type
);
1522 hpi_dsp_code_read_block(length
, &dsp_code
, &pcode
);
1524 for (i
= 0; i
< (int)length
; i
++) {
1525 data
= boot_loader_read_mem32(pao
, dsp
,
1527 if (data
!= *pcode
) {
1537 hpi_dsp_code_close(&dsp_code
);
1542 /* After bootloading all DSPs, start DSP0 running
1543 * The DSP0 code will handle starting and synchronizing with its slaves
1545 if (phw
->p_interface_buffer
) {
1546 /* we need to tell the card the physical PCI address */
1547 u32 physicalPC_iaddress
;
1548 struct bus_master_interface
*interface
=
1549 phw
->p_interface_buffer
;
1550 u32 host_mailbox_address_on_dsp
;
1551 u32 physicalPC_iaddress_verify
= 0;
1553 /* set ack so we know when DSP is ready to go */
1554 /* (dwDspAck will be changed to HIF_RESET) */
1555 interface
->dsp_ack
= H620_HIF_UNKNOWN
;
1556 wmb(); /* ensure ack is written before dsp writes back */
1558 err
= hpios_locked_mem_get_phys_addr(&phw
->h_locked_mem
,
1559 &physicalPC_iaddress
);
1561 /* locate the host mailbox on the DSP. */
1562 host_mailbox_address_on_dsp
= 0x80000000;
1563 while ((physicalPC_iaddress
!= physicalPC_iaddress_verify
)
1565 err
= boot_loader_write_mem32(pao
, 0,
1566 host_mailbox_address_on_dsp
,
1567 physicalPC_iaddress
);
1568 physicalPC_iaddress_verify
=
1569 boot_loader_read_mem32(pao
, 0,
1570 host_mailbox_address_on_dsp
);
1573 HPI_DEBUG_LOG(DEBUG
, "starting DS_ps running\n");
1574 /* enable interrupts */
1575 temp
= ioread32(phw
->prHSR
);
1576 temp
&= ~(u32
)C6205_HSR_INTAM
;
1577 iowrite32(temp
, phw
->prHSR
);
1579 /* start code running... */
1580 temp
= ioread32(phw
->prHDCR
);
1581 temp
|= (u32
)C6205_HDCR_DSPINT
;
1582 iowrite32(temp
, phw
->prHDCR
);
1584 /* give the DSP 10ms to start up */
1585 hpios_delay_micro_seconds(10000);
1590 /*****************************************************************************/
1591 /* Bootloader utility functions */
1593 static u32
boot_loader_read_mem32(struct hpi_adapter_obj
*pao
, int dsp_index
,
1596 struct hpi_hw_obj
*phw
= pao
->priv
;
1598 __iomem u32
*p_data
;
1600 if (dsp_index
== 0) {
1601 /* DSP 0 is always C6205 */
1602 if ((address
>= 0x01800000) & (address
< 0x02000000)) {
1603 /* BAR1 register access */
1604 p_data
= pao
->pci
.ap_mem_base
[1] +
1605 (address
& 0x007fffff) /
1606 sizeof(*pao
->pci
.ap_mem_base
[1]);
1607 /* HPI_DEBUG_LOG(WARNING,
1608 "BAR1 access %08x\n", dwAddress); */
1610 u32 dw4M_page
= address
>> 22L;
1611 if (dw4M_page
!= phw
->dsp_page
) {
1612 phw
->dsp_page
= dw4M_page
;
1614 iowrite32(phw
->dsp_page
, phw
->prDSPP
);
1617 address
&= 0x3fffff; /* address within 4M page */
1618 /* BAR0 memory access */
1619 p_data
= pao
->pci
.ap_mem_base
[0] +
1620 address
/ sizeof(u32
);
1622 data
= ioread32(p_data
);
1623 } else if (dsp_index
== 1) {
1624 /* DSP 1 is a C6713 */
1626 boot_loader_write_mem32(pao
, 0, HPIAL_ADDR
, address
);
1627 boot_loader_write_mem32(pao
, 0, HPIAH_ADDR
, address
>> 16);
1628 lsb
= boot_loader_read_mem32(pao
, 0, HPIDL_ADDR
);
1629 data
= boot_loader_read_mem32(pao
, 0, HPIDH_ADDR
);
1630 data
= (data
<< 16) | (lsb
& 0xFFFF);
1635 static u16
boot_loader_write_mem32(struct hpi_adapter_obj
*pao
, int dsp_index
,
1636 u32 address
, u32 data
)
1638 struct hpi_hw_obj
*phw
= pao
->priv
;
1640 __iomem u32
*p_data
;
1641 /* u32 dwVerifyData=0; */
1643 if (dsp_index
== 0) {
1644 /* DSP 0 is always C6205 */
1645 if ((address
>= 0x01800000) & (address
< 0x02000000)) {
1646 /* BAR1 - DSP register access using */
1647 /* Non-prefetchable PCI access */
1648 p_data
= pao
->pci
.ap_mem_base
[1] +
1649 (address
& 0x007fffff) /
1650 sizeof(*pao
->pci
.ap_mem_base
[1]);
1652 /* BAR0 access - all of DSP memory using */
1653 /* pre-fetchable PCI access */
1654 u32 dw4M_page
= address
>> 22L;
1655 if (dw4M_page
!= phw
->dsp_page
) {
1656 phw
->dsp_page
= dw4M_page
;
1658 iowrite32(phw
->dsp_page
, phw
->prDSPP
);
1661 address
&= 0x3fffff; /* address within 4M page */
1662 p_data
= pao
->pci
.ap_mem_base
[0] +
1663 address
/ sizeof(u32
);
1665 iowrite32(data
, p_data
);
1666 } else if (dsp_index
== 1) {
1667 /* DSP 1 is a C6713 */
1668 boot_loader_write_mem32(pao
, 0, HPIAL_ADDR
, address
);
1669 boot_loader_write_mem32(pao
, 0, HPIAH_ADDR
, address
>> 16);
1671 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1672 boot_loader_read_mem32(pao
, 0, 0);
1674 boot_loader_write_mem32(pao
, 0, HPIDL_ADDR
, data
);
1675 boot_loader_write_mem32(pao
, 0, HPIDH_ADDR
, data
>> 16);
1677 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1678 boot_loader_read_mem32(pao
, 0, 0);
1680 err
= hpi6205_error(dsp_index
, HPI6205_ERROR_BAD_DSPINDEX
);
1684 static u16
boot_loader_config_emif(struct hpi_adapter_obj
*pao
, int dsp_index
)
1688 if (dsp_index
== 0) {
1691 /* DSP 0 is always C6205 */
1694 /* memory map of C6205 */
1695 /* 00000000-0000FFFF 16Kx32 internal program */
1696 /* 00400000-00BFFFFF CE0 2Mx32 SDRAM running @ 100MHz */
1700 /* Global EMIF control */
1701 boot_loader_write_mem32(pao
, dsp_index
, 0x01800000, 0x3779);
1710 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */
1711 setting
= 0x00000030;
1712 boot_loader_write_mem32(pao
, dsp_index
, 0x01800008, setting
);
1713 if (setting
!= boot_loader_read_mem32(pao
, dsp_index
,
1715 return hpi6205_error(dsp_index
,
1716 HPI6205_ERROR_DSP_EMIF
);
1718 /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */
1719 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1720 /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */
1721 /* WST should be 71, but 63 is max possible */
1723 (1L << WS_OFS
) | (63L << WST_OFS
) | (1L << WH_OFS
) |
1724 (1L << RS_OFS
) | (63L << RST_OFS
) | (1L << RH_OFS
) |
1726 boot_loader_write_mem32(pao
, dsp_index
, 0x01800004, setting
);
1727 if (setting
!= boot_loader_read_mem32(pao
, dsp_index
,
1729 return hpi6205_error(dsp_index
,
1730 HPI6205_ERROR_DSP_EMIF
);
1732 /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */
1733 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1734 /* plenty of wait states */
1736 (1L << WS_OFS
) | (28L << WST_OFS
) | (1L << WH_OFS
) |
1737 (1L << RS_OFS
) | (63L << RST_OFS
) | (1L << RH_OFS
) |
1739 boot_loader_write_mem32(pao
, dsp_index
, 0x01800010, setting
);
1740 if (setting
!= boot_loader_read_mem32(pao
, dsp_index
,
1742 return hpi6205_error(dsp_index
,
1743 HPI6205_ERROR_DSP_EMIF
);
1745 /* EMIF CE3 setup - 32 bit async. */
1746 /* This is the PLD on the ASI5000 cards only */
1748 (1L << WS_OFS
) | (10L << WST_OFS
) | (1L << WH_OFS
) |
1749 (1L << RS_OFS
) | (10L << RST_OFS
) | (1L << RH_OFS
) |
1751 boot_loader_write_mem32(pao
, dsp_index
, 0x01800014, setting
);
1752 if (setting
!= boot_loader_read_mem32(pao
, dsp_index
,
1754 return hpi6205_error(dsp_index
,
1755 HPI6205_ERROR_DSP_EMIF
);
1757 /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */
1758 /* need to use this else DSP code crashes? */
1759 boot_loader_write_mem32(pao
, dsp_index
, 0x01800018,
1762 /* EMIF SDRAM Refresh Timing */
1763 /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */
1764 boot_loader_write_mem32(pao
, dsp_index
, 0x0180001C,
1767 } else if (dsp_index
== 1) {
1768 /* test access to the C6713s HPI registers */
1769 u32 write_data
= 0, read_data
= 0, i
= 0;
1771 /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */
1773 boot_loader_write_mem32(pao
, 0, HPICL_ADDR
, write_data
);
1774 boot_loader_write_mem32(pao
, 0, HPICH_ADDR
, write_data
);
1775 /* C67 HPI is on lower 16bits of 32bit EMIF */
1777 0xFFF7 & boot_loader_read_mem32(pao
, 0, HPICL_ADDR
);
1778 if (write_data
!= read_data
) {
1779 err
= hpi6205_error(dsp_index
,
1780 HPI6205_ERROR_C6713_HPIC
);
1781 HPI_DEBUG_LOG(ERROR
, "HPICL %x %x\n", write_data
,
1786 /* HPIA - walking ones test */
1788 for (i
= 0; i
< 32; i
++) {
1789 boot_loader_write_mem32(pao
, 0, HPIAL_ADDR
,
1791 boot_loader_write_mem32(pao
, 0, HPIAH_ADDR
,
1792 (write_data
>> 16));
1794 0xFFFF & boot_loader_read_mem32(pao
, 0,
1797 read_data
| ((0xFFFF &
1798 boot_loader_read_mem32(pao
, 0,
1801 if (read_data
!= write_data
) {
1802 err
= hpi6205_error(dsp_index
,
1803 HPI6205_ERROR_C6713_HPIA
);
1804 HPI_DEBUG_LOG(ERROR
, "HPIA %x %x\n",
1805 write_data
, read_data
);
1808 write_data
= write_data
<< 1;
1812 * ** C6713 datasheet says we cannot program PLL from HPI,
1813 * and indeed if we try to set the PLL multiply from the HPI,
1814 * the PLL does not seem to lock, so we enable the PLL and
1815 * use the default multiply of x 7, which for a 27MHz clock
1816 * gives a DSP speed of 189MHz
1819 boot_loader_write_mem32(pao
, dsp_index
, 0x01B7C100, 0x0000);
1820 hpios_delay_micro_seconds(1000);
1821 /* EMIF = 189/3=63MHz */
1822 boot_loader_write_mem32(pao
, dsp_index
, 0x01B7C120, 0x8002);
1824 boot_loader_write_mem32(pao
, dsp_index
, 0x01B7C11C, 0x8001);
1826 boot_loader_write_mem32(pao
, dsp_index
, 0x01B7C118, 0x8000);
1827 hpios_delay_micro_seconds(1000);
1828 /* ** SGT test to take GPO3 high when we start the PLL */
1829 /* and low when the delay is completed */
1830 /* FSX0 <- '1' (GPO3) */
1831 boot_loader_write_mem32(pao
, 0, (0x018C0024L
), 0x00002A0A);
1832 /* PLL not bypassed */
1833 boot_loader_write_mem32(pao
, dsp_index
, 0x01B7C100, 0x0001);
1834 hpios_delay_micro_seconds(1000);
1835 /* FSX0 <- '0' (GPO3) */
1836 boot_loader_write_mem32(pao
, 0, (0x018C0024L
), 0x00002A02);
1838 /* 6205 EMIF CE1 resetup - 32 bit async. */
1839 /* Now 6713 #1 is running at 189MHz can reduce waitstates */
1840 boot_loader_write_mem32(pao
, 0, 0x01800004, /* CE1 */
1841 (1L << WS_OFS
) | (8L << WST_OFS
) | (1L << WH_OFS
) |
1842 (1L << RS_OFS
) | (12L << RST_OFS
) | (1L << RH_OFS
) |
1845 hpios_delay_micro_seconds(1000);
1847 /* check that we can read one of the PLL registers */
1848 /* PLL should not be bypassed! */
1849 if ((boot_loader_read_mem32(pao
, dsp_index
, 0x01B7C100) & 0xF)
1851 err
= hpi6205_error(dsp_index
,
1852 HPI6205_ERROR_C6713_PLL
);
1855 /* setup C67x EMIF (note this is the only use of
1856 BAR1 via BootLoader_WriteMem32) */
1857 boot_loader_write_mem32(pao
, dsp_index
, C6713_EMIF_GCTL
,
1859 boot_loader_write_mem32(pao
, dsp_index
, C6713_EMIF_CE0
,
1861 boot_loader_write_mem32(pao
, dsp_index
, C6713_EMIF_SDRAMEXT
,
1863 boot_loader_write_mem32(pao
, dsp_index
, C6713_EMIF_SDRAMCTL
,
1865 boot_loader_write_mem32(pao
, dsp_index
,
1866 C6713_EMIF_SDRAMTIMING
, 0x00000410);
1868 hpios_delay_micro_seconds(1000);
1869 } else if (dsp_index
== 2) {
1870 /* DSP 2 is a C6713 */
1873 err
= hpi6205_error(dsp_index
, HPI6205_ERROR_BAD_DSPINDEX
);
1877 static u16
boot_loader_test_memory(struct hpi_adapter_obj
*pao
, int dsp_index
,
1878 u32 start_address
, u32 length
)
1882 u32 test_data
= 0, data
= 0;
1886 /* for 1st word, test each bit in the 32bit word, */
1887 /* dwLength specifies number of 32bit words to test */
1888 /*for(i=0; i<dwLength; i++) */
1891 test_addr
= start_address
+ i
* 4;
1892 test_data
= 0x00000001;
1893 for (j
= 0; j
< 32; j
++) {
1894 boot_loader_write_mem32(pao
, dsp_index
, test_addr
,
1896 data
= boot_loader_read_mem32(pao
, dsp_index
,
1898 if (data
!= test_data
) {
1899 HPI_DEBUG_LOG(VERBOSE
,
1900 "memtest error details "
1901 "%08x %08x %08x %i\n", test_addr
,
1902 test_data
, data
, dsp_index
);
1903 return 1; /* error */
1905 test_data
= test_data
<< 1;
1909 /* for the next 100 locations test each location, leaving it as zero */
1910 /* write a zero to the next word in memory before we read */
1911 /* the previous write to make sure every memory location is unique */
1912 for (i
= 0; i
< 100; i
++) {
1913 test_addr
= start_address
+ i
* 4;
1914 test_data
= 0xA5A55A5A;
1915 boot_loader_write_mem32(pao
, dsp_index
, test_addr
, test_data
);
1916 boot_loader_write_mem32(pao
, dsp_index
, test_addr
+ 4, 0);
1917 data
= boot_loader_read_mem32(pao
, dsp_index
, test_addr
);
1918 if (data
!= test_data
) {
1919 HPI_DEBUG_LOG(VERBOSE
,
1920 "memtest error details "
1921 "%08x %08x %08x %i\n", test_addr
, test_data
,
1923 return 1; /* error */
1925 /* leave location as zero */
1926 boot_loader_write_mem32(pao
, dsp_index
, test_addr
, 0x0);
1929 /* zero out entire memory block */
1930 for (i
= 0; i
< length
; i
++) {
1931 test_addr
= start_address
+ i
* 4;
1932 boot_loader_write_mem32(pao
, dsp_index
, test_addr
, 0x0);
1937 static u16
boot_loader_test_internal_memory(struct hpi_adapter_obj
*pao
,
1941 if (dsp_index
== 0) {
1942 /* DSP 0 is a C6205 */
1944 err
= boot_loader_test_memory(pao
, dsp_index
, 0x00000000,
1948 err
= boot_loader_test_memory(pao
, dsp_index
,
1949 0x80000000, 0x10000);
1950 } else if ((dsp_index
== 1) || (dsp_index
== 2)) {
1951 /* DSP 1&2 are a C6713 */
1952 /* 192K internal mem */
1953 err
= boot_loader_test_memory(pao
, dsp_index
, 0x00000000,
1956 /* 64K internal mem / L2 cache */
1957 err
= boot_loader_test_memory(pao
, dsp_index
,
1958 0x00030000, 0x10000);
1960 return hpi6205_error(dsp_index
, HPI6205_ERROR_BAD_DSPINDEX
);
1963 return hpi6205_error(dsp_index
, HPI6205_ERROR_DSP_INTMEM
);
1968 static u16
boot_loader_test_external_memory(struct hpi_adapter_obj
*pao
,
1971 u32 dRAM_start_address
= 0;
1974 if (dsp_index
== 0) {
1975 /* only test for SDRAM if an ASI5000 card */
1976 if (pao
->pci
.subsys_device_id
== 0x5000) {
1977 /* DSP 0 is always C6205 */
1978 dRAM_start_address
= 0x00400000;
1979 dRAM_size
= 0x200000;
1980 /*dwDRAMinc=1024; */
1983 } else if ((dsp_index
== 1) || (dsp_index
== 2)) {
1984 /* DSP 1 is a C6713 */
1985 dRAM_start_address
= 0x80000000;
1986 dRAM_size
= 0x200000;
1987 /*dwDRAMinc=1024; */
1989 return hpi6205_error(dsp_index
, HPI6205_ERROR_BAD_DSPINDEX
);
1991 if (boot_loader_test_memory(pao
, dsp_index
, dRAM_start_address
,
1993 return hpi6205_error(dsp_index
, HPI6205_ERROR_DSP_EXTMEM
);
1997 static u16
boot_loader_test_pld(struct hpi_adapter_obj
*pao
, int dsp_index
)
2000 if (dsp_index
== 0) {
2001 /* only test for DSP0 PLD on ASI5000 card */
2002 if (pao
->pci
.subsys_device_id
== 0x5000) {
2003 /* PLD is located at CE3=0x03000000 */
2004 data
= boot_loader_read_mem32(pao
, dsp_index
,
2006 if ((data
& 0xF) != 0x5)
2007 return hpi6205_error(dsp_index
,
2008 HPI6205_ERROR_DSP_PLD
);
2009 data
= boot_loader_read_mem32(pao
, dsp_index
,
2011 if ((data
& 0xF) != 0xA)
2012 return hpi6205_error(dsp_index
,
2013 HPI6205_ERROR_DSP_PLD
);
2015 } else if (dsp_index
== 1) {
2016 /* DSP 1 is a C6713 */
2017 if (pao
->pci
.subsys_device_id
== 0x8700) {
2018 /* PLD is located at CE1=0x90000000 */
2019 data
= boot_loader_read_mem32(pao
, dsp_index
,
2021 if ((data
& 0xFF) != 0xAA)
2022 return hpi6205_error(dsp_index
,
2023 HPI6205_ERROR_DSP_PLD
);
2025 boot_loader_write_mem32(pao
, dsp_index
, 0x90000000,
2032 /** Transfer data to or from DSP
2033 nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA
2035 static short hpi6205_transfer_data(struct hpi_adapter_obj
*pao
, u8
*p_data
,
2036 u32 data_size
, int operation
)
2038 struct hpi_hw_obj
*phw
= pao
->priv
;
2039 u32 data_transferred
= 0;
2041 #ifndef HPI6205_NO_HSR_POLL
2045 struct bus_master_interface
*interface
= phw
->p_interface_buffer
;
2048 return HPI_ERROR_INVALID_DATA_TRANSFER
;
2050 data_size
&= ~3L; /* round data_size down to nearest 4 bytes */
2052 /* make sure state is IDLE */
2053 if (!wait_dsp_ack(phw
, H620_HIF_IDLE
, HPI6205_TIMEOUT
))
2054 return HPI_ERROR_DSP_HARDWARE
;
2056 while (data_transferred
< data_size
) {
2057 u32 this_copy
= data_size
- data_transferred
;
2059 if (this_copy
> HPI6205_SIZEOF_DATA
)
2060 this_copy
= HPI6205_SIZEOF_DATA
;
2062 if (operation
== H620_HIF_SEND_DATA
)
2063 memcpy((void *)&interface
->u
.b_data
[0],
2064 &p_data
[data_transferred
], this_copy
);
2066 interface
->transfer_size_in_bytes
= this_copy
;
2068 #ifdef HPI6205_NO_HSR_POLL
2069 /* DSP must change this back to nOperation */
2070 interface
->dsp_ack
= H620_HIF_IDLE
;
2073 send_dsp_command(phw
, operation
);
2075 #ifdef HPI6205_NO_HSR_POLL
2076 temp2
= wait_dsp_ack(phw
, operation
, HPI6205_TIMEOUT
);
2077 HPI_DEBUG_LOG(DEBUG
, "spun %d times for data xfer of %d\n",
2078 HPI6205_TIMEOUT
- temp2
, this_copy
);
2082 HPI_DEBUG_LOG(ERROR
,
2083 "timed out waiting for " "state %d got %d\n",
2084 operation
, interface
->dsp_ack
);
2089 /* spin waiting on the result */
2090 time_out
= HPI6205_TIMEOUT
;
2092 while ((temp2
== 0) && time_out
--) {
2093 /* give 16k bus mastering transfer time to happen */
2094 /*(16k / 132Mbytes/s = 122usec) */
2095 hpios_delay_micro_seconds(20);
2096 temp2
= ioread32(phw
->prHSR
);
2097 temp2
&= C6205_HSR_INTSRC
;
2099 HPI_DEBUG_LOG(DEBUG
, "spun %d times for data xfer of %d\n",
2100 HPI6205_TIMEOUT
- time_out
, this_copy
);
2101 if (temp2
== C6205_HSR_INTSRC
) {
2102 HPI_DEBUG_LOG(VERBOSE
,
2103 "interrupt from HIF <data> OK\n");
2105 if(interface->dwDspAck != nOperation) {
2106 HPI_DEBUG_LOG(DEBUG("interface->dwDspAck=%d,
2108 interface->dwDspAck,nOperation);
2112 /* need to handle this differently... */
2114 HPI_DEBUG_LOG(ERROR
,
2115 "interrupt from HIF <data> BAD\n");
2116 err
= HPI_ERROR_DSP_HARDWARE
;
2119 /* reset the interrupt from the DSP */
2120 iowrite32(C6205_HSR_INTSRC
, phw
->prHSR
);
2122 if (operation
== H620_HIF_GET_DATA
)
2123 memcpy(&p_data
[data_transferred
],
2124 (void *)&interface
->u
.b_data
[0], this_copy
);
2126 data_transferred
+= this_copy
;
2128 if (interface
->dsp_ack
!= operation
)
2129 HPI_DEBUG_LOG(DEBUG
, "interface->dsp_ack=%d, expected %d\n",
2130 interface
->dsp_ack
, operation
);
2131 /* err=HPI_ERROR_DSP_HARDWARE; */
2133 send_dsp_command(phw
, H620_HIF_IDLE
);
2138 /* wait for up to timeout_us microseconds for the DSP
2139 to signal state by DMA into dwDspAck
2141 static int wait_dsp_ack(struct hpi_hw_obj
*phw
, int state
, int timeout_us
)
2143 struct bus_master_interface
*interface
= phw
->p_interface_buffer
;
2144 int t
= timeout_us
/ 4;
2146 rmb(); /* ensure interface->dsp_ack is up to date */
2147 while ((interface
->dsp_ack
!= state
) && --t
) {
2148 hpios_delay_micro_seconds(4);
2149 rmb(); /* DSP changes dsp_ack by DMA */
2152 /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */
2156 /* set the busmaster interface to cmd, then interrupt the DSP */
2157 static void send_dsp_command(struct hpi_hw_obj
*phw
, int cmd
)
2159 struct bus_master_interface
*interface
= phw
->p_interface_buffer
;
2163 interface
->host_cmd
= cmd
;
2164 wmb(); /* DSP gets state by DMA, make sure it is written to memory */
2165 /* before we interrupt the DSP */
2166 r
= ioread32(phw
->prHDCR
);
2167 r
|= (u32
)C6205_HDCR_DSPINT
;
2168 iowrite32(r
, phw
->prHDCR
);
2169 r
&= ~(u32
)C6205_HDCR_DSPINT
;
2170 iowrite32(r
, phw
->prHDCR
);
2173 static unsigned int message_count
;
2175 static u16
message_response_sequence(struct hpi_adapter_obj
*pao
,
2176 struct hpi_message
*phm
, struct hpi_response
*phr
)
2178 #ifndef HPI6205_NO_HSR_POLL
2181 u32 time_out
, time_out2
;
2182 struct hpi_hw_obj
*phw
= pao
->priv
;
2183 struct bus_master_interface
*interface
= phw
->p_interface_buffer
;
2187 /* Assume buffer of type struct bus_master_interface
2188 is allocated "noncacheable" */
2190 if (!wait_dsp_ack(phw
, H620_HIF_IDLE
, HPI6205_TIMEOUT
)) {
2191 HPI_DEBUG_LOG(DEBUG
, "timeout waiting for idle\n");
2192 return hpi6205_error(0, HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT
);
2194 interface
->u
.message_buffer
= *phm
;
2195 /* signal we want a response */
2196 send_dsp_command(phw
, H620_HIF_GET_RESP
);
2198 time_out2
= wait_dsp_ack(phw
, H620_HIF_GET_RESP
, HPI6205_TIMEOUT
);
2200 if (time_out2
== 0) {
2201 HPI_DEBUG_LOG(ERROR
,
2202 "(%u) timed out waiting for " "GET_RESP state [%x]\n",
2203 message_count
, interface
->dsp_ack
);
2205 HPI_DEBUG_LOG(VERBOSE
,
2206 "(%u) transition to GET_RESP after %u\n",
2207 message_count
, HPI6205_TIMEOUT
- time_out2
);
2209 /* spin waiting on HIF interrupt flag (end of msg process) */
2210 time_out
= HPI6205_TIMEOUT
;
2212 #ifndef HPI6205_NO_HSR_POLL
2214 while ((temp2
== 0) && --time_out
) {
2215 temp2
= ioread32(phw
->prHSR
);
2216 temp2
&= C6205_HSR_INTSRC
;
2217 hpios_delay_micro_seconds(1);
2219 if (temp2
== C6205_HSR_INTSRC
) {
2220 rmb(); /* ensure we see latest value for dsp_ack */
2221 if ((interface
->dsp_ack
!= H620_HIF_GET_RESP
)) {
2222 HPI_DEBUG_LOG(DEBUG
,
2223 "(%u)interface->dsp_ack(0x%x) != "
2224 "H620_HIF_GET_RESP, t=%u\n", message_count
,
2226 HPI6205_TIMEOUT
- time_out
);
2228 HPI_DEBUG_LOG(VERBOSE
,
2229 "(%u)int with GET_RESP after %u\n",
2230 message_count
, HPI6205_TIMEOUT
- time_out
);
2234 /* can we do anything else in response to the error ? */
2235 HPI_DEBUG_LOG(ERROR
,
2236 "interrupt from HIF module BAD (function %x)\n",
2240 /* reset the interrupt from the DSP */
2241 iowrite32(C6205_HSR_INTSRC
, phw
->prHSR
);
2244 /* read the result */
2246 *phr
= interface
->u
.response_buffer
;
2248 /* set interface back to idle */
2249 send_dsp_command(phw
, H620_HIF_IDLE
);
2251 if ((time_out
== 0) || (time_out2
== 0)) {
2252 HPI_DEBUG_LOG(DEBUG
, "something timed out!\n");
2253 return hpi6205_error(0, HPI6205_ERROR_MSG_RESP_TIMEOUT
);
2255 /* special case for adapter close - */
2256 /* wait for the DSP to indicate it is idle */
2257 if (phm
->function
== HPI_ADAPTER_CLOSE
) {
2258 if (!wait_dsp_ack(phw
, H620_HIF_IDLE
, HPI6205_TIMEOUT
)) {
2259 HPI_DEBUG_LOG(DEBUG
,
2260 "timeout waiting for idle "
2261 "(on adapter_close)\n");
2262 return hpi6205_error(0,
2263 HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT
);
2266 err
= hpi_validate_response(phm
, phr
);
2270 static void hw_message(struct hpi_adapter_obj
*pao
, struct hpi_message
*phm
,
2271 struct hpi_response
*phr
)
2276 hpios_dsplock_lock(pao
);
2278 err
= message_response_sequence(pao
, phm
, phr
);
2280 /* maybe an error response */
2282 /* something failed in the HPI/DSP interface */
2286 /* just the header of the response is valid */
2287 phr
->size
= sizeof(struct hpi_response_header
);
2290 pao
->dsp_crashed
= 0;
2292 if (phr
->error
!= 0) /* something failed in the DSP */
2295 switch (phm
->function
) {
2296 case HPI_OSTREAM_WRITE
:
2297 case HPI_ISTREAM_ANC_WRITE
:
2298 err
= hpi6205_transfer_data(pao
, phm
->u
.d
.u
.data
.pb_data
,
2299 phm
->u
.d
.u
.data
.data_size
, H620_HIF_SEND_DATA
);
2302 case HPI_ISTREAM_READ
:
2303 case HPI_OSTREAM_ANC_READ
:
2304 err
= hpi6205_transfer_data(pao
, phm
->u
.d
.u
.data
.pb_data
,
2305 phm
->u
.d
.u
.data
.data_size
, H620_HIF_GET_DATA
);
2308 case HPI_CONTROL_SET_STATE
:
2309 if (phm
->object
== HPI_OBJ_CONTROLEX
2310 && phm
->u
.cx
.attribute
== HPI_COBRANET_SET_DATA
)
2311 err
= hpi6205_transfer_data(pao
,
2312 phm
->u
.cx
.u
.cobranet_bigdata
.pb_data
,
2313 phm
->u
.cx
.u
.cobranet_bigdata
.byte_count
,
2314 H620_HIF_SEND_DATA
);
2317 case HPI_CONTROL_GET_STATE
:
2318 if (phm
->object
== HPI_OBJ_CONTROLEX
2319 && phm
->u
.cx
.attribute
== HPI_COBRANET_GET_DATA
)
2320 err
= hpi6205_transfer_data(pao
,
2321 phm
->u
.cx
.u
.cobranet_bigdata
.pb_data
,
2322 phr
->u
.cx
.u
.cobranet_data
.byte_count
,
2329 hpios_dsplock_unlock(pao
);