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ALSA: asihpi - Give more meaningful name to hpi request message type
[deliverable/linux.git] / sound / pci / asihpi / hpi6205.c
1 /******************************************************************************
2
3 AudioScience HPI driver
4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of version 2 of the GNU General Public License as
8 published by the Free Software Foundation;
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18
19 Hardware Programming Interface (HPI) for AudioScience
20 ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters.
21 These PCI and PCIe bus adapters are based on a
22 TMS320C6205 PCI bus mastering DSP,
23 and (except ASI50xx) TI TMS320C6xxx floating point DSP
24
25 Exported function:
26 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
27
28 (C) Copyright AudioScience Inc. 1998-2010
29 *******************************************************************************/
30 #define SOURCEFILE_NAME "hpi6205.c"
31
32 #include "hpi_internal.h"
33 #include "hpimsginit.h"
34 #include "hpidebug.h"
35 #include "hpi6205.h"
36 #include "hpidspcd.h"
37 #include "hpicmn.h"
38
39 /*****************************************************************************/
40 /* HPI6205 specific error codes */
41 #define HPI6205_ERROR_BASE 1000 /* not actually used anywhere */
42
43 /* operational/messaging errors */
44 #define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015
45 #define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016
46
47 /* initialization/bootload errors */
48 #define HPI6205_ERROR_6205_NO_IRQ 1002
49 #define HPI6205_ERROR_6205_INIT_FAILED 1003
50 #define HPI6205_ERROR_6205_REG 1006
51 #define HPI6205_ERROR_6205_DSPPAGE 1007
52 #define HPI6205_ERROR_C6713_HPIC 1009
53 #define HPI6205_ERROR_C6713_HPIA 1010
54 #define HPI6205_ERROR_C6713_PLL 1011
55 #define HPI6205_ERROR_DSP_INTMEM 1012
56 #define HPI6205_ERROR_DSP_EXTMEM 1013
57 #define HPI6205_ERROR_DSP_PLD 1014
58 #define HPI6205_ERROR_6205_EEPROM 1017
59 #define HPI6205_ERROR_DSP_EMIF 1018
60
61 /*****************************************************************************/
62 /* for C6205 PCI i/f */
63 /* Host Status Register (HSR) bitfields */
64 #define C6205_HSR_INTSRC 0x01
65 #define C6205_HSR_INTAVAL 0x02
66 #define C6205_HSR_INTAM 0x04
67 #define C6205_HSR_CFGERR 0x08
68 #define C6205_HSR_EEREAD 0x10
69 /* Host-to-DSP Control Register (HDCR) bitfields */
70 #define C6205_HDCR_WARMRESET 0x01
71 #define C6205_HDCR_DSPINT 0x02
72 #define C6205_HDCR_PCIBOOT 0x04
73 /* DSP Page Register (DSPP) bitfields, */
74 /* defines 4 Mbyte page that BAR0 points to */
75 #define C6205_DSPP_MAP1 0x400
76
77 /* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP.
78 * BAR1 maps to non-prefetchable 8 Mbyte memory block
79 * of DSP memory mapped registers (starting at 0x01800000).
80 * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this
81 * needs to be added to the BAR1 base address set in the PCI config reg
82 */
83 #define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L)
84 #define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET)
85 #define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4)
86 #define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8)
87
88 /* used to control LED (revA) and reset C6713 (revB) */
89 #define C6205_BAR0_TIMER1_CTL (0x01980000L)
90
91 /* For first 6713 in CE1 space, using DA17,16,2 */
92 #define HPICL_ADDR 0x01400000L
93 #define HPICH_ADDR 0x01400004L
94 #define HPIAL_ADDR 0x01410000L
95 #define HPIAH_ADDR 0x01410004L
96 #define HPIDIL_ADDR 0x01420000L
97 #define HPIDIH_ADDR 0x01420004L
98 #define HPIDL_ADDR 0x01430000L
99 #define HPIDH_ADDR 0x01430004L
100
101 #define C6713_EMIF_GCTL 0x01800000
102 #define C6713_EMIF_CE1 0x01800004
103 #define C6713_EMIF_CE0 0x01800008
104 #define C6713_EMIF_CE2 0x01800010
105 #define C6713_EMIF_CE3 0x01800014
106 #define C6713_EMIF_SDRAMCTL 0x01800018
107 #define C6713_EMIF_SDRAMTIMING 0x0180001C
108 #define C6713_EMIF_SDRAMEXT 0x01800020
109
110 struct hpi_hw_obj {
111 /* PCI registers */
112 __iomem u32 *prHSR;
113 __iomem u32 *prHDCR;
114 __iomem u32 *prDSPP;
115
116 u32 dsp_page;
117
118 struct consistent_dma_area h_locked_mem;
119 struct bus_master_interface *p_interface_buffer;
120
121 u16 flag_outstream_just_reset[HPI_MAX_STREAMS];
122 /* a non-NULL handle means there is an HPI allocated buffer */
123 struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS];
124 struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS];
125 /* non-zero size means a buffer exists, may be external */
126 u32 instream_host_buffer_size[HPI_MAX_STREAMS];
127 u32 outstream_host_buffer_size[HPI_MAX_STREAMS];
128
129 struct consistent_dma_area h_control_cache;
130 struct hpi_control_cache *p_cache;
131 };
132
133 /*****************************************************************************/
134 /* local prototypes */
135
136 #define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write)
137
138 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us);
139
140 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd);
141
142 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
143 u32 *pos_error_code);
144
145 static u16 message_response_sequence(struct hpi_adapter_obj *pao,
146 struct hpi_message *phm, struct hpi_response *phr);
147
148 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
149 struct hpi_response *phr);
150
151 #define HPI6205_TIMEOUT 1000000
152
153 static void subsys_create_adapter(struct hpi_message *phm,
154 struct hpi_response *phr);
155 static void adapter_delete(struct hpi_adapter_obj *pao,
156 struct hpi_message *phm, struct hpi_response *phr);
157
158 static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
159 u32 *pos_error_code);
160
161 static void delete_adapter_obj(struct hpi_adapter_obj *pao);
162
163 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
164 struct hpi_message *phm, struct hpi_response *phr);
165
166 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
167 struct hpi_message *phm, struct hpi_response *phr);
168
169 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
170 struct hpi_message *phm, struct hpi_response *phr);
171 static void outstream_write(struct hpi_adapter_obj *pao,
172 struct hpi_message *phm, struct hpi_response *phr);
173
174 static void outstream_get_info(struct hpi_adapter_obj *pao,
175 struct hpi_message *phm, struct hpi_response *phr);
176
177 static void outstream_start(struct hpi_adapter_obj *pao,
178 struct hpi_message *phm, struct hpi_response *phr);
179
180 static void outstream_open(struct hpi_adapter_obj *pao,
181 struct hpi_message *phm, struct hpi_response *phr);
182
183 static void outstream_reset(struct hpi_adapter_obj *pao,
184 struct hpi_message *phm, struct hpi_response *phr);
185
186 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
187 struct hpi_message *phm, struct hpi_response *phr);
188
189 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
190 struct hpi_message *phm, struct hpi_response *phr);
191
192 static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
193 struct hpi_message *phm, struct hpi_response *phr);
194
195 static void instream_read(struct hpi_adapter_obj *pao,
196 struct hpi_message *phm, struct hpi_response *phr);
197
198 static void instream_get_info(struct hpi_adapter_obj *pao,
199 struct hpi_message *phm, struct hpi_response *phr);
200
201 static void instream_start(struct hpi_adapter_obj *pao,
202 struct hpi_message *phm, struct hpi_response *phr);
203
204 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
205 u32 address);
206
207 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
208 int dsp_index, u32 address, u32 data);
209
210 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao,
211 int dsp_index);
212
213 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
214 u32 address, u32 length);
215
216 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
217 int dsp_index);
218
219 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
220 int dsp_index);
221
222 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index);
223
224 /*****************************************************************************/
225
226 static void subsys_message(struct hpi_adapter_obj *pao,
227 struct hpi_message *phm, struct hpi_response *phr)
228 {
229 switch (phm->function) {
230 case HPI_SUBSYS_CREATE_ADAPTER:
231 subsys_create_adapter(phm, phr);
232 break;
233 default:
234 phr->error = HPI_ERROR_INVALID_FUNC;
235 break;
236 }
237 }
238
239 static void control_message(struct hpi_adapter_obj *pao,
240 struct hpi_message *phm, struct hpi_response *phr)
241 {
242
243 struct hpi_hw_obj *phw = pao->priv;
244 u16 pending_cache_error = 0;
245
246 switch (phm->function) {
247 case HPI_CONTROL_GET_STATE:
248 if (pao->has_control_cache) {
249 rmb(); /* make sure we see updates DMAed from DSP */
250 if (hpi_check_control_cache(phw->p_cache, phm, phr)) {
251 break;
252 } else if (phm->u.c.attribute == HPI_METER_PEAK) {
253 pending_cache_error =
254 HPI_ERROR_CONTROL_CACHING;
255 }
256 }
257 hw_message(pao, phm, phr);
258 if (pending_cache_error && !phr->error)
259 phr->error = pending_cache_error;
260 break;
261 case HPI_CONTROL_GET_INFO:
262 hw_message(pao, phm, phr);
263 break;
264 case HPI_CONTROL_SET_STATE:
265 hw_message(pao, phm, phr);
266 if (pao->has_control_cache)
267 hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm,
268 phr);
269 break;
270 default:
271 phr->error = HPI_ERROR_INVALID_FUNC;
272 break;
273 }
274 }
275
276 static void adapter_message(struct hpi_adapter_obj *pao,
277 struct hpi_message *phm, struct hpi_response *phr)
278 {
279 switch (phm->function) {
280 case HPI_ADAPTER_DELETE:
281 adapter_delete(pao, phm, phr);
282 break;
283
284 default:
285 hw_message(pao, phm, phr);
286 break;
287 }
288 }
289
290 static void outstream_message(struct hpi_adapter_obj *pao,
291 struct hpi_message *phm, struct hpi_response *phr)
292 {
293
294 if (phm->obj_index >= HPI_MAX_STREAMS) {
295 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
296 HPI_DEBUG_LOG(WARNING,
297 "Message referencing invalid stream %d "
298 "on adapter index %d\n", phm->obj_index,
299 phm->adapter_index);
300 return;
301 }
302
303 switch (phm->function) {
304 case HPI_OSTREAM_WRITE:
305 outstream_write(pao, phm, phr);
306 break;
307 case HPI_OSTREAM_GET_INFO:
308 outstream_get_info(pao, phm, phr);
309 break;
310 case HPI_OSTREAM_HOSTBUFFER_ALLOC:
311 outstream_host_buffer_allocate(pao, phm, phr);
312 break;
313 case HPI_OSTREAM_HOSTBUFFER_GET_INFO:
314 outstream_host_buffer_get_info(pao, phm, phr);
315 break;
316 case HPI_OSTREAM_HOSTBUFFER_FREE:
317 outstream_host_buffer_free(pao, phm, phr);
318 break;
319 case HPI_OSTREAM_START:
320 outstream_start(pao, phm, phr);
321 break;
322 case HPI_OSTREAM_OPEN:
323 outstream_open(pao, phm, phr);
324 break;
325 case HPI_OSTREAM_RESET:
326 outstream_reset(pao, phm, phr);
327 break;
328 default:
329 hw_message(pao, phm, phr);
330 break;
331 }
332 }
333
334 static void instream_message(struct hpi_adapter_obj *pao,
335 struct hpi_message *phm, struct hpi_response *phr)
336 {
337
338 if (phm->obj_index >= HPI_MAX_STREAMS) {
339 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
340 HPI_DEBUG_LOG(WARNING,
341 "Message referencing invalid stream %d "
342 "on adapter index %d\n", phm->obj_index,
343 phm->adapter_index);
344 return;
345 }
346
347 switch (phm->function) {
348 case HPI_ISTREAM_READ:
349 instream_read(pao, phm, phr);
350 break;
351 case HPI_ISTREAM_GET_INFO:
352 instream_get_info(pao, phm, phr);
353 break;
354 case HPI_ISTREAM_HOSTBUFFER_ALLOC:
355 instream_host_buffer_allocate(pao, phm, phr);
356 break;
357 case HPI_ISTREAM_HOSTBUFFER_GET_INFO:
358 instream_host_buffer_get_info(pao, phm, phr);
359 break;
360 case HPI_ISTREAM_HOSTBUFFER_FREE:
361 instream_host_buffer_free(pao, phm, phr);
362 break;
363 case HPI_ISTREAM_START:
364 instream_start(pao, phm, phr);
365 break;
366 default:
367 hw_message(pao, phm, phr);
368 break;
369 }
370 }
371
372 /*****************************************************************************/
373 /** Entry point to this HPI backend
374 * All calls to the HPI start here
375 */
376 void _HPI_6205(struct hpi_adapter_obj *pao, struct hpi_message *phm,
377 struct hpi_response *phr)
378 {
379 if (pao && (pao->dsp_crashed >= 10)
380 && (phm->function != HPI_ADAPTER_DEBUG_READ)) {
381 /* allow last resort debug read even after crash */
382 hpi_init_response(phr, phm->object, phm->function,
383 HPI_ERROR_DSP_HARDWARE);
384 HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n", phm->object,
385 phm->function);
386 return;
387 }
388
389 /* Init default response */
390 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
391 phr->error = HPI_ERROR_PROCESSING_MESSAGE;
392
393 HPI_DEBUG_LOG(VERBOSE, "start of switch\n");
394 switch (phm->type) {
395 case HPI_TYPE_REQUEST:
396 switch (phm->object) {
397 case HPI_OBJ_SUBSYSTEM:
398 subsys_message(pao, phm, phr);
399 break;
400
401 case HPI_OBJ_ADAPTER:
402 adapter_message(pao, phm, phr);
403 break;
404
405 case HPI_OBJ_CONTROLEX:
406 case HPI_OBJ_CONTROL:
407 control_message(pao, phm, phr);
408 break;
409
410 case HPI_OBJ_OSTREAM:
411 outstream_message(pao, phm, phr);
412 break;
413
414 case HPI_OBJ_ISTREAM:
415 instream_message(pao, phm, phr);
416 break;
417
418 default:
419 hw_message(pao, phm, phr);
420 break;
421 }
422 break;
423
424 default:
425 phr->error = HPI_ERROR_INVALID_TYPE;
426 break;
427 }
428 }
429
430 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
431 {
432 struct hpi_adapter_obj *pao = NULL;
433
434 if (phm->object != HPI_OBJ_SUBSYSTEM) {
435 /* normal messages must have valid adapter index */
436 pao = hpi_find_adapter(phm->adapter_index);
437 } else {
438 /* subsys messages don't address an adapter */
439 _HPI_6205(NULL, phm, phr);
440 return;
441 }
442
443 if (pao)
444 _HPI_6205(pao, phm, phr);
445 else
446 hpi_init_response(phr, phm->object, phm->function,
447 HPI_ERROR_BAD_ADAPTER_NUMBER);
448 }
449
450 /*****************************************************************************/
451 /* SUBSYSTEM */
452
453 /** Create an adapter object and initialise it based on resource information
454 * passed in in the message
455 * *** NOTE - you cannot use this function AND the FindAdapters function at the
456 * same time, the application must use only one of them to get the adapters ***
457 */
458 static void subsys_create_adapter(struct hpi_message *phm,
459 struct hpi_response *phr)
460 {
461 /* create temp adapter obj, because we don't know what index yet */
462 struct hpi_adapter_obj ao;
463 u32 os_error_code;
464 u16 err;
465
466 HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n");
467
468 memset(&ao, 0, sizeof(ao));
469
470 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
471 if (!ao.priv) {
472 HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n");
473 phr->error = HPI_ERROR_MEMORY_ALLOC;
474 return;
475 }
476
477 ao.pci = *phm->u.s.resource.r.pci;
478 err = create_adapter_obj(&ao, &os_error_code);
479 if (err) {
480 delete_adapter_obj(&ao);
481 if (err >= HPI_ERROR_BACKEND_BASE) {
482 phr->error = HPI_ERROR_DSP_BOOTLOAD;
483 phr->specific_error = err;
484 } else {
485 phr->error = err;
486 }
487 phr->u.s.data = os_error_code;
488 return;
489 }
490
491 phr->u.s.adapter_type = ao.adapter_type;
492 phr->u.s.adapter_index = ao.index;
493 phr->error = 0;
494 }
495
496 /** delete an adapter - required by WDM driver */
497 static void adapter_delete(struct hpi_adapter_obj *pao,
498 struct hpi_message *phm, struct hpi_response *phr)
499 {
500 struct hpi_hw_obj *phw;
501
502 if (!pao) {
503 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
504 return;
505 }
506 phw = (struct hpi_hw_obj *)pao->priv;
507 /* reset adapter h/w */
508 /* Reset C6713 #1 */
509 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
510 /* reset C6205 */
511 iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR);
512
513 delete_adapter_obj(pao);
514 hpi_delete_adapter(pao);
515 phr->error = 0;
516 }
517
518 /** Create adapter object
519 allocate buffers, bootload DSPs, initialise control cache
520 */
521 static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
522 u32 *pos_error_code)
523 {
524 struct hpi_hw_obj *phw = pao->priv;
525 struct bus_master_interface *interface;
526 u32 phys_addr;
527 int i;
528 u16 err;
529
530 /* init error reporting */
531 pao->dsp_crashed = 0;
532
533 for (i = 0; i < HPI_MAX_STREAMS; i++)
534 phw->flag_outstream_just_reset[i] = 1;
535
536 /* The C6205 memory area 1 is 8Mbyte window into DSP registers */
537 phw->prHSR =
538 pao->pci.ap_mem_base[1] +
539 C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]);
540 phw->prHDCR =
541 pao->pci.ap_mem_base[1] +
542 C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]);
543 phw->prDSPP =
544 pao->pci.ap_mem_base[1] +
545 C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]);
546
547 pao->has_control_cache = 0;
548
549 if (hpios_locked_mem_alloc(&phw->h_locked_mem,
550 sizeof(struct bus_master_interface),
551 pao->pci.pci_dev))
552 phw->p_interface_buffer = NULL;
553 else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem,
554 (void *)&phw->p_interface_buffer))
555 phw->p_interface_buffer = NULL;
556
557 HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n",
558 phw->p_interface_buffer);
559
560 if (phw->p_interface_buffer) {
561 memset((void *)phw->p_interface_buffer, 0,
562 sizeof(struct bus_master_interface));
563 phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN;
564 }
565
566 err = adapter_boot_load_dsp(pao, pos_error_code);
567 if (err) {
568 HPI_DEBUG_LOG(ERROR, "DSP code load failed\n");
569 /* no need to clean up as SubSysCreateAdapter */
570 /* calls DeleteAdapter on error. */
571 return err;
572 }
573 HPI_DEBUG_LOG(INFO, "load DSP code OK\n");
574
575 /* allow boot load even if mem alloc wont work */
576 if (!phw->p_interface_buffer)
577 return HPI_ERROR_MEMORY_ALLOC;
578
579 interface = phw->p_interface_buffer;
580
581 /* make sure the DSP has started ok */
582 if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) {
583 HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n");
584 return HPI6205_ERROR_6205_INIT_FAILED;
585 }
586 /* Note that *pao, *phw are zeroed after allocation,
587 * so pointers and flags are NULL by default.
588 * Allocate bus mastering control cache buffer and tell the DSP about it
589 */
590 if (interface->control_cache.number_of_controls) {
591 u8 *p_control_cache_virtual;
592
593 err = hpios_locked_mem_alloc(&phw->h_control_cache,
594 interface->control_cache.size_in_bytes,
595 pao->pci.pci_dev);
596 if (!err)
597 err = hpios_locked_mem_get_virt_addr(&phw->
598 h_control_cache,
599 (void *)&p_control_cache_virtual);
600 if (!err) {
601 memset(p_control_cache_virtual, 0,
602 interface->control_cache.size_in_bytes);
603
604 phw->p_cache =
605 hpi_alloc_control_cache(interface->
606 control_cache.number_of_controls,
607 interface->control_cache.size_in_bytes,
608 p_control_cache_virtual);
609
610 if (!phw->p_cache)
611 err = HPI_ERROR_MEMORY_ALLOC;
612 }
613 if (!err) {
614 err = hpios_locked_mem_get_phys_addr(&phw->
615 h_control_cache, &phys_addr);
616 interface->control_cache.physical_address32 =
617 phys_addr;
618 }
619
620 if (!err)
621 pao->has_control_cache = 1;
622 else {
623 if (hpios_locked_mem_valid(&phw->h_control_cache))
624 hpios_locked_mem_free(&phw->h_control_cache);
625 pao->has_control_cache = 0;
626 }
627 }
628 send_dsp_command(phw, H620_HIF_IDLE);
629
630 {
631 struct hpi_message hm;
632 struct hpi_response hr;
633 u32 max_streams;
634
635 HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n");
636 memset(&hm, 0, sizeof(hm));
637 /* wAdapterIndex == version == 0 */
638 hm.type = HPI_TYPE_REQUEST;
639 hm.size = sizeof(hm);
640 hm.object = HPI_OBJ_ADAPTER;
641 hm.function = HPI_ADAPTER_GET_INFO;
642
643 memset(&hr, 0, sizeof(hr));
644 hr.size = sizeof(hr);
645
646 err = message_response_sequence(pao, &hm, &hr);
647 if (err) {
648 HPI_DEBUG_LOG(ERROR, "message transport error %d\n",
649 err);
650 return err;
651 }
652 if (hr.error)
653 return hr.error;
654
655 pao->adapter_type = hr.u.ax.info.adapter_type;
656 pao->index = hr.u.ax.info.adapter_index;
657
658 max_streams =
659 hr.u.ax.info.num_outstreams +
660 hr.u.ax.info.num_instreams;
661
662 hpios_locked_mem_prepare((max_streams * 6) / 10, max_streams,
663 65536, pao->pci.pci_dev);
664
665 HPI_DEBUG_LOG(VERBOSE,
666 "got adapter info type %x index %d serial %d\n",
667 hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index,
668 hr.u.ax.info.serial_number);
669 }
670
671 pao->open = 0; /* upon creation the adapter is closed */
672
673 if (phw->p_cache)
674 phw->p_cache->adap_idx = pao->index;
675
676 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
677
678 return hpi_add_adapter(pao);
679 }
680
681 /** Free memory areas allocated by adapter
682 * this routine is called from AdapterDelete,
683 * and SubSysCreateAdapter if duplicate index
684 */
685 static void delete_adapter_obj(struct hpi_adapter_obj *pao)
686 {
687 struct hpi_hw_obj *phw = pao->priv;
688 int i;
689
690 if (hpios_locked_mem_valid(&phw->h_control_cache)) {
691 hpios_locked_mem_free(&phw->h_control_cache);
692 hpi_free_control_cache(phw->p_cache);
693 }
694
695 if (hpios_locked_mem_valid(&phw->h_locked_mem)) {
696 hpios_locked_mem_free(&phw->h_locked_mem);
697 phw->p_interface_buffer = NULL;
698 }
699
700 for (i = 0; i < HPI_MAX_STREAMS; i++)
701 if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) {
702 hpios_locked_mem_free(&phw->instream_host_buffers[i]);
703 /*?phw->InStreamHostBuffers[i] = NULL; */
704 phw->instream_host_buffer_size[i] = 0;
705 }
706
707 for (i = 0; i < HPI_MAX_STREAMS; i++)
708 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) {
709 hpios_locked_mem_free(&phw->outstream_host_buffers
710 [i]);
711 phw->outstream_host_buffer_size[i] = 0;
712 }
713
714 hpios_locked_mem_unprepare(pao->pci.pci_dev);
715
716 kfree(phw);
717 }
718
719 /*****************************************************************************/
720 /* Adapter functions */
721
722 /*****************************************************************************/
723 /* OutStream Host buffer functions */
724
725 /** Allocate or attach buffer for busmastering
726 */
727 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
728 struct hpi_message *phm, struct hpi_response *phr)
729 {
730 u16 err = 0;
731 u32 command = phm->u.d.u.buffer.command;
732 struct hpi_hw_obj *phw = pao->priv;
733 struct bus_master_interface *interface = phw->p_interface_buffer;
734
735 hpi_init_response(phr, phm->object, phm->function, 0);
736
737 if (command == HPI_BUFFER_CMD_EXTERNAL
738 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
739 /* ALLOC phase, allocate a buffer with power of 2 size,
740 get its bus address for PCI bus mastering
741 */
742 phm->u.d.u.buffer.buffer_size =
743 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
744 /* return old size and allocated size,
745 so caller can detect change */
746 phr->u.d.u.stream_info.data_available =
747 phw->outstream_host_buffer_size[phm->obj_index];
748 phr->u.d.u.stream_info.buffer_size =
749 phm->u.d.u.buffer.buffer_size;
750
751 if (phw->outstream_host_buffer_size[phm->obj_index] ==
752 phm->u.d.u.buffer.buffer_size) {
753 /* Same size, no action required */
754 return;
755 }
756
757 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
758 obj_index]))
759 hpios_locked_mem_free(&phw->outstream_host_buffers
760 [phm->obj_index]);
761
762 err = hpios_locked_mem_alloc(&phw->outstream_host_buffers
763 [phm->obj_index], phm->u.d.u.buffer.buffer_size,
764 pao->pci.pci_dev);
765
766 if (err) {
767 phr->error = HPI_ERROR_INVALID_DATASIZE;
768 phw->outstream_host_buffer_size[phm->obj_index] = 0;
769 return;
770 }
771
772 err = hpios_locked_mem_get_phys_addr
773 (&phw->outstream_host_buffers[phm->obj_index],
774 &phm->u.d.u.buffer.pci_address);
775 /* get the phys addr into msg for single call alloc caller
776 * needs to do this for split alloc (or use the same message)
777 * return the phy address for split alloc in the respose too
778 */
779 phr->u.d.u.stream_info.auxiliary_data_available =
780 phm->u.d.u.buffer.pci_address;
781
782 if (err) {
783 hpios_locked_mem_free(&phw->outstream_host_buffers
784 [phm->obj_index]);
785 phw->outstream_host_buffer_size[phm->obj_index] = 0;
786 phr->error = HPI_ERROR_MEMORY_ALLOC;
787 return;
788 }
789 }
790
791 if (command == HPI_BUFFER_CMD_EXTERNAL
792 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
793 /* GRANT phase. Set up the BBM status, tell the DSP about
794 the buffer so it can start using BBM.
795 */
796 struct hpi_hostbuffer_status *status;
797
798 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
799 buffer_size - 1)) {
800 HPI_DEBUG_LOG(ERROR,
801 "Buffer size must be 2^N not %d\n",
802 phm->u.d.u.buffer.buffer_size);
803 phr->error = HPI_ERROR_INVALID_DATASIZE;
804 return;
805 }
806 phw->outstream_host_buffer_size[phm->obj_index] =
807 phm->u.d.u.buffer.buffer_size;
808 status = &interface->outstream_host_buffer_status[phm->
809 obj_index];
810 status->samples_processed = 0;
811 status->stream_state = HPI_STATE_STOPPED;
812 status->dSP_index = 0;
813 status->host_index = status->dSP_index;
814 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
815 status->auxiliary_data_available = 0;
816
817 hw_message(pao, phm, phr);
818
819 if (phr->error
820 && hpios_locked_mem_valid(&phw->
821 outstream_host_buffers[phm->obj_index])) {
822 hpios_locked_mem_free(&phw->outstream_host_buffers
823 [phm->obj_index]);
824 phw->outstream_host_buffer_size[phm->obj_index] = 0;
825 }
826 }
827 }
828
829 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
830 struct hpi_message *phm, struct hpi_response *phr)
831 {
832 struct hpi_hw_obj *phw = pao->priv;
833 struct bus_master_interface *interface = phw->p_interface_buffer;
834 struct hpi_hostbuffer_status *status;
835 u8 *p_bbm_data;
836
837 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
838 obj_index])) {
839 if (hpios_locked_mem_get_virt_addr(&phw->
840 outstream_host_buffers[phm->obj_index],
841 (void *)&p_bbm_data)) {
842 phr->error = HPI_ERROR_INVALID_OPERATION;
843 return;
844 }
845 status = &interface->outstream_host_buffer_status[phm->
846 obj_index];
847 hpi_init_response(phr, HPI_OBJ_OSTREAM,
848 HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0);
849 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
850 phr->u.d.u.hostbuffer_info.p_status = status;
851 } else {
852 hpi_init_response(phr, HPI_OBJ_OSTREAM,
853 HPI_OSTREAM_HOSTBUFFER_GET_INFO,
854 HPI_ERROR_INVALID_OPERATION);
855 }
856 }
857
858 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
859 struct hpi_message *phm, struct hpi_response *phr)
860 {
861 struct hpi_hw_obj *phw = pao->priv;
862 u32 command = phm->u.d.u.buffer.command;
863
864 if (phw->outstream_host_buffer_size[phm->obj_index]) {
865 if (command == HPI_BUFFER_CMD_EXTERNAL
866 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
867 phw->outstream_host_buffer_size[phm->obj_index] = 0;
868 hw_message(pao, phm, phr);
869 /* Tell adapter to stop using the host buffer. */
870 }
871 if (command == HPI_BUFFER_CMD_EXTERNAL
872 || command == HPI_BUFFER_CMD_INTERNAL_FREE)
873 hpios_locked_mem_free(&phw->outstream_host_buffers
874 [phm->obj_index]);
875 }
876 /* Should HPI_ERROR_INVALID_OPERATION be returned
877 if no host buffer is allocated? */
878 else
879 hpi_init_response(phr, HPI_OBJ_OSTREAM,
880 HPI_OSTREAM_HOSTBUFFER_FREE, 0);
881
882 }
883
884 static u32 outstream_get_space_available(struct hpi_hostbuffer_status *status)
885 {
886 return status->size_in_bytes - (status->host_index -
887 status->dSP_index);
888 }
889
890 static void outstream_write(struct hpi_adapter_obj *pao,
891 struct hpi_message *phm, struct hpi_response *phr)
892 {
893 struct hpi_hw_obj *phw = pao->priv;
894 struct bus_master_interface *interface = phw->p_interface_buffer;
895 struct hpi_hostbuffer_status *status;
896 u32 space_available;
897
898 if (!phw->outstream_host_buffer_size[phm->obj_index]) {
899 /* there is no BBM buffer, write via message */
900 hw_message(pao, phm, phr);
901 return;
902 }
903
904 hpi_init_response(phr, phm->object, phm->function, 0);
905 status = &interface->outstream_host_buffer_status[phm->obj_index];
906
907 space_available = outstream_get_space_available(status);
908 if (space_available < phm->u.d.u.data.data_size) {
909 phr->error = HPI_ERROR_INVALID_DATASIZE;
910 return;
911 }
912
913 /* HostBuffers is used to indicate host buffer is internally allocated.
914 otherwise, assumed external, data written externally */
915 if (phm->u.d.u.data.pb_data
916 && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
917 obj_index])) {
918 u8 *p_bbm_data;
919 u32 l_first_write;
920 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
921
922 if (hpios_locked_mem_get_virt_addr(&phw->
923 outstream_host_buffers[phm->obj_index],
924 (void *)&p_bbm_data)) {
925 phr->error = HPI_ERROR_INVALID_OPERATION;
926 return;
927 }
928
929 /* either all data,
930 or enough to fit from current to end of BBM buffer */
931 l_first_write =
932 min(phm->u.d.u.data.data_size,
933 status->size_in_bytes -
934 (status->host_index & (status->size_in_bytes - 1)));
935
936 memcpy(p_bbm_data +
937 (status->host_index & (status->size_in_bytes - 1)),
938 p_app_data, l_first_write);
939 /* remaining data if any */
940 memcpy(p_bbm_data, p_app_data + l_first_write,
941 phm->u.d.u.data.data_size - l_first_write);
942 }
943
944 /*
945 * This version relies on the DSP code triggering an OStream buffer
946 * update immediately following a SET_FORMAT call. The host has
947 * already written data into the BBM buffer, but the DSP won't know
948 * about it until dwHostIndex is adjusted.
949 */
950 if (phw->flag_outstream_just_reset[phm->obj_index]) {
951 /* Format can only change after reset. Must tell DSP. */
952 u16 function = phm->function;
953 phw->flag_outstream_just_reset[phm->obj_index] = 0;
954 phm->function = HPI_OSTREAM_SET_FORMAT;
955 hw_message(pao, phm, phr); /* send the format to the DSP */
956 phm->function = function;
957 if (phr->error)
958 return;
959 }
960
961 status->host_index += phm->u.d.u.data.data_size;
962 }
963
964 static void outstream_get_info(struct hpi_adapter_obj *pao,
965 struct hpi_message *phm, struct hpi_response *phr)
966 {
967 struct hpi_hw_obj *phw = pao->priv;
968 struct bus_master_interface *interface = phw->p_interface_buffer;
969 struct hpi_hostbuffer_status *status;
970
971 if (!phw->outstream_host_buffer_size[phm->obj_index]) {
972 hw_message(pao, phm, phr);
973 return;
974 }
975
976 hpi_init_response(phr, phm->object, phm->function, 0);
977
978 status = &interface->outstream_host_buffer_status[phm->obj_index];
979
980 phr->u.d.u.stream_info.state = (u16)status->stream_state;
981 phr->u.d.u.stream_info.samples_transferred =
982 status->samples_processed;
983 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
984 phr->u.d.u.stream_info.data_available =
985 status->size_in_bytes - outstream_get_space_available(status);
986 phr->u.d.u.stream_info.auxiliary_data_available =
987 status->auxiliary_data_available;
988 }
989
990 static void outstream_start(struct hpi_adapter_obj *pao,
991 struct hpi_message *phm, struct hpi_response *phr)
992 {
993 hw_message(pao, phm, phr);
994 }
995
996 static void outstream_reset(struct hpi_adapter_obj *pao,
997 struct hpi_message *phm, struct hpi_response *phr)
998 {
999 struct hpi_hw_obj *phw = pao->priv;
1000 phw->flag_outstream_just_reset[phm->obj_index] = 1;
1001 hw_message(pao, phm, phr);
1002 }
1003
1004 static void outstream_open(struct hpi_adapter_obj *pao,
1005 struct hpi_message *phm, struct hpi_response *phr)
1006 {
1007 outstream_reset(pao, phm, phr);
1008 }
1009
1010 /*****************************************************************************/
1011 /* InStream Host buffer functions */
1012
1013 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
1014 struct hpi_message *phm, struct hpi_response *phr)
1015 {
1016 u16 err = 0;
1017 u32 command = phm->u.d.u.buffer.command;
1018 struct hpi_hw_obj *phw = pao->priv;
1019 struct bus_master_interface *interface = phw->p_interface_buffer;
1020
1021 hpi_init_response(phr, phm->object, phm->function, 0);
1022
1023 if (command == HPI_BUFFER_CMD_EXTERNAL
1024 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
1025
1026 phm->u.d.u.buffer.buffer_size =
1027 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
1028 phr->u.d.u.stream_info.data_available =
1029 phw->instream_host_buffer_size[phm->obj_index];
1030 phr->u.d.u.stream_info.buffer_size =
1031 phm->u.d.u.buffer.buffer_size;
1032
1033 if (phw->instream_host_buffer_size[phm->obj_index] ==
1034 phm->u.d.u.buffer.buffer_size) {
1035 /* Same size, no action required */
1036 return;
1037 }
1038
1039 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1040 obj_index]))
1041 hpios_locked_mem_free(&phw->instream_host_buffers
1042 [phm->obj_index]);
1043
1044 err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm->
1045 obj_index], phm->u.d.u.buffer.buffer_size,
1046 pao->pci.pci_dev);
1047
1048 if (err) {
1049 phr->error = HPI_ERROR_INVALID_DATASIZE;
1050 phw->instream_host_buffer_size[phm->obj_index] = 0;
1051 return;
1052 }
1053
1054 err = hpios_locked_mem_get_phys_addr
1055 (&phw->instream_host_buffers[phm->obj_index],
1056 &phm->u.d.u.buffer.pci_address);
1057 /* get the phys addr into msg for single call alloc. Caller
1058 needs to do this for split alloc so return the phy address */
1059 phr->u.d.u.stream_info.auxiliary_data_available =
1060 phm->u.d.u.buffer.pci_address;
1061 if (err) {
1062 hpios_locked_mem_free(&phw->instream_host_buffers
1063 [phm->obj_index]);
1064 phw->instream_host_buffer_size[phm->obj_index] = 0;
1065 phr->error = HPI_ERROR_MEMORY_ALLOC;
1066 return;
1067 }
1068 }
1069
1070 if (command == HPI_BUFFER_CMD_EXTERNAL
1071 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
1072 struct hpi_hostbuffer_status *status;
1073
1074 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
1075 buffer_size - 1)) {
1076 HPI_DEBUG_LOG(ERROR,
1077 "Buffer size must be 2^N not %d\n",
1078 phm->u.d.u.buffer.buffer_size);
1079 phr->error = HPI_ERROR_INVALID_DATASIZE;
1080 return;
1081 }
1082
1083 phw->instream_host_buffer_size[phm->obj_index] =
1084 phm->u.d.u.buffer.buffer_size;
1085 status = &interface->instream_host_buffer_status[phm->
1086 obj_index];
1087 status->samples_processed = 0;
1088 status->stream_state = HPI_STATE_STOPPED;
1089 status->dSP_index = 0;
1090 status->host_index = status->dSP_index;
1091 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
1092 status->auxiliary_data_available = 0;
1093
1094 hw_message(pao, phm, phr);
1095
1096 if (phr->error
1097 && hpios_locked_mem_valid(&phw->
1098 instream_host_buffers[phm->obj_index])) {
1099 hpios_locked_mem_free(&phw->instream_host_buffers
1100 [phm->obj_index]);
1101 phw->instream_host_buffer_size[phm->obj_index] = 0;
1102 }
1103 }
1104 }
1105
1106 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
1107 struct hpi_message *phm, struct hpi_response *phr)
1108 {
1109 struct hpi_hw_obj *phw = pao->priv;
1110 struct bus_master_interface *interface = phw->p_interface_buffer;
1111 struct hpi_hostbuffer_status *status;
1112 u8 *p_bbm_data;
1113
1114 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1115 obj_index])) {
1116 if (hpios_locked_mem_get_virt_addr(&phw->
1117 instream_host_buffers[phm->obj_index],
1118 (void *)&p_bbm_data)) {
1119 phr->error = HPI_ERROR_INVALID_OPERATION;
1120 return;
1121 }
1122 status = &interface->instream_host_buffer_status[phm->
1123 obj_index];
1124 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1125 HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0);
1126 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
1127 phr->u.d.u.hostbuffer_info.p_status = status;
1128 } else {
1129 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1130 HPI_ISTREAM_HOSTBUFFER_GET_INFO,
1131 HPI_ERROR_INVALID_OPERATION);
1132 }
1133 }
1134
1135 static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
1136 struct hpi_message *phm, struct hpi_response *phr)
1137 {
1138 struct hpi_hw_obj *phw = pao->priv;
1139 u32 command = phm->u.d.u.buffer.command;
1140
1141 if (phw->instream_host_buffer_size[phm->obj_index]) {
1142 if (command == HPI_BUFFER_CMD_EXTERNAL
1143 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
1144 phw->instream_host_buffer_size[phm->obj_index] = 0;
1145 hw_message(pao, phm, phr);
1146 }
1147
1148 if (command == HPI_BUFFER_CMD_EXTERNAL
1149 || command == HPI_BUFFER_CMD_INTERNAL_FREE)
1150 hpios_locked_mem_free(&phw->instream_host_buffers
1151 [phm->obj_index]);
1152
1153 } else {
1154 /* Should HPI_ERROR_INVALID_OPERATION be returned
1155 if no host buffer is allocated? */
1156 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1157 HPI_ISTREAM_HOSTBUFFER_FREE, 0);
1158
1159 }
1160
1161 }
1162
1163 static void instream_start(struct hpi_adapter_obj *pao,
1164 struct hpi_message *phm, struct hpi_response *phr)
1165 {
1166 hw_message(pao, phm, phr);
1167 }
1168
1169 static u32 instream_get_bytes_available(struct hpi_hostbuffer_status *status)
1170 {
1171 return status->dSP_index - status->host_index;
1172 }
1173
1174 static void instream_read(struct hpi_adapter_obj *pao,
1175 struct hpi_message *phm, struct hpi_response *phr)
1176 {
1177 struct hpi_hw_obj *phw = pao->priv;
1178 struct bus_master_interface *interface = phw->p_interface_buffer;
1179 struct hpi_hostbuffer_status *status;
1180 u32 data_available;
1181 u8 *p_bbm_data;
1182 u32 l_first_read;
1183 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
1184
1185 if (!phw->instream_host_buffer_size[phm->obj_index]) {
1186 hw_message(pao, phm, phr);
1187 return;
1188 }
1189 hpi_init_response(phr, phm->object, phm->function, 0);
1190
1191 status = &interface->instream_host_buffer_status[phm->obj_index];
1192 data_available = instream_get_bytes_available(status);
1193 if (data_available < phm->u.d.u.data.data_size) {
1194 phr->error = HPI_ERROR_INVALID_DATASIZE;
1195 return;
1196 }
1197
1198 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1199 obj_index])) {
1200 if (hpios_locked_mem_get_virt_addr(&phw->
1201 instream_host_buffers[phm->obj_index],
1202 (void *)&p_bbm_data)) {
1203 phr->error = HPI_ERROR_INVALID_OPERATION;
1204 return;
1205 }
1206
1207 /* either all data,
1208 or enough to fit from current to end of BBM buffer */
1209 l_first_read =
1210 min(phm->u.d.u.data.data_size,
1211 status->size_in_bytes -
1212 (status->host_index & (status->size_in_bytes - 1)));
1213
1214 memcpy(p_app_data,
1215 p_bbm_data +
1216 (status->host_index & (status->size_in_bytes - 1)),
1217 l_first_read);
1218 /* remaining data if any */
1219 memcpy(p_app_data + l_first_read, p_bbm_data,
1220 phm->u.d.u.data.data_size - l_first_read);
1221 }
1222 status->host_index += phm->u.d.u.data.data_size;
1223 }
1224
1225 static void instream_get_info(struct hpi_adapter_obj *pao,
1226 struct hpi_message *phm, struct hpi_response *phr)
1227 {
1228 struct hpi_hw_obj *phw = pao->priv;
1229 struct bus_master_interface *interface = phw->p_interface_buffer;
1230 struct hpi_hostbuffer_status *status;
1231 if (!phw->instream_host_buffer_size[phm->obj_index]) {
1232 hw_message(pao, phm, phr);
1233 return;
1234 }
1235
1236 status = &interface->instream_host_buffer_status[phm->obj_index];
1237
1238 hpi_init_response(phr, phm->object, phm->function, 0);
1239
1240 phr->u.d.u.stream_info.state = (u16)status->stream_state;
1241 phr->u.d.u.stream_info.samples_transferred =
1242 status->samples_processed;
1243 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
1244 phr->u.d.u.stream_info.data_available =
1245 instream_get_bytes_available(status);
1246 phr->u.d.u.stream_info.auxiliary_data_available =
1247 status->auxiliary_data_available;
1248 }
1249
1250 /*****************************************************************************/
1251 /* LOW-LEVEL */
1252 #define HPI6205_MAX_FILES_TO_LOAD 2
1253
1254 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
1255 u32 *pos_error_code)
1256 {
1257 struct hpi_hw_obj *phw = pao->priv;
1258 struct dsp_code dsp_code;
1259 u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD];
1260 u32 temp;
1261 int dsp = 0, i = 0;
1262 u16 err = 0;
1263
1264 boot_code_id[0] = HPI_ADAPTER_ASI(0x6205);
1265
1266 boot_code_id[1] = pao->pci.pci_dev->subsystem_device;
1267 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(boot_code_id[1]);
1268
1269 /* fix up cases where bootcode id[1] != subsys id */
1270 switch (boot_code_id[1]) {
1271 case HPI_ADAPTER_FAMILY_ASI(0x5000):
1272 boot_code_id[0] = boot_code_id[1];
1273 boot_code_id[1] = 0;
1274 break;
1275 case HPI_ADAPTER_FAMILY_ASI(0x5300):
1276 case HPI_ADAPTER_FAMILY_ASI(0x5400):
1277 case HPI_ADAPTER_FAMILY_ASI(0x6300):
1278 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6400);
1279 break;
1280 case HPI_ADAPTER_FAMILY_ASI(0x5500):
1281 case HPI_ADAPTER_FAMILY_ASI(0x5600):
1282 case HPI_ADAPTER_FAMILY_ASI(0x6500):
1283 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6600);
1284 break;
1285 case HPI_ADAPTER_FAMILY_ASI(0x8800):
1286 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x8900);
1287 break;
1288 default:
1289 break;
1290 }
1291
1292 /* reset DSP by writing a 1 to the WARMRESET bit */
1293 temp = C6205_HDCR_WARMRESET;
1294 iowrite32(temp, phw->prHDCR);
1295 hpios_delay_micro_seconds(1000);
1296
1297 /* check that PCI i/f was configured by EEPROM */
1298 temp = ioread32(phw->prHSR);
1299 if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) !=
1300 C6205_HSR_EEREAD)
1301 return HPI6205_ERROR_6205_EEPROM;
1302 temp |= 0x04;
1303 /* disable PINTA interrupt */
1304 iowrite32(temp, phw->prHSR);
1305
1306 /* check control register reports PCI boot mode */
1307 temp = ioread32(phw->prHDCR);
1308 if (!(temp & C6205_HDCR_PCIBOOT))
1309 return HPI6205_ERROR_6205_REG;
1310
1311 /* try writing a few numbers to the DSP page register */
1312 /* and reading them back. */
1313 temp = 3;
1314 iowrite32(temp, phw->prDSPP);
1315 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1316 return HPI6205_ERROR_6205_DSPPAGE;
1317 temp = 2;
1318 iowrite32(temp, phw->prDSPP);
1319 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1320 return HPI6205_ERROR_6205_DSPPAGE;
1321 temp = 1;
1322 iowrite32(temp, phw->prDSPP);
1323 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1324 return HPI6205_ERROR_6205_DSPPAGE;
1325 /* reset DSP page to the correct number */
1326 temp = 0;
1327 iowrite32(temp, phw->prDSPP);
1328 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1329 return HPI6205_ERROR_6205_DSPPAGE;
1330 phw->dsp_page = 0;
1331
1332 /* release 6713 from reset before 6205 is bootloaded.
1333 This ensures that the EMIF is inactive,
1334 and the 6713 HPI gets the correct bootmode etc
1335 */
1336 if (boot_code_id[1] != 0) {
1337 /* DSP 1 is a C6713 */
1338 /* CLKX0 <- '1' release the C6205 bootmode pulldowns */
1339 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002202);
1340 hpios_delay_micro_seconds(100);
1341 /* Reset the 6713 #1 - revB */
1342 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
1343
1344 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1345 boot_loader_read_mem32(pao, 0, 0);
1346
1347 hpios_delay_micro_seconds(100);
1348 /* Release C6713 from reset - revB */
1349 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4);
1350 hpios_delay_micro_seconds(100);
1351 }
1352
1353 for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) {
1354 /* is there a DSP to load? */
1355 if (boot_code_id[dsp] == 0)
1356 continue;
1357
1358 err = boot_loader_config_emif(pao, dsp);
1359 if (err)
1360 return err;
1361
1362 err = boot_loader_test_internal_memory(pao, dsp);
1363 if (err)
1364 return err;
1365
1366 err = boot_loader_test_external_memory(pao, dsp);
1367 if (err)
1368 return err;
1369
1370 err = boot_loader_test_pld(pao, dsp);
1371 if (err)
1372 return err;
1373
1374 /* write the DSP code down into the DSPs memory */
1375 dsp_code.ps_dev = pao->pci.pci_dev;
1376 err = hpi_dsp_code_open(boot_code_id[dsp], &dsp_code,
1377 pos_error_code);
1378 if (err)
1379 return err;
1380
1381 while (1) {
1382 u32 length;
1383 u32 address;
1384 u32 type;
1385 u32 *pcode;
1386
1387 err = hpi_dsp_code_read_word(&dsp_code, &length);
1388 if (err)
1389 break;
1390 if (length == 0xFFFFFFFF)
1391 break; /* end of code */
1392
1393 err = hpi_dsp_code_read_word(&dsp_code, &address);
1394 if (err)
1395 break;
1396 err = hpi_dsp_code_read_word(&dsp_code, &type);
1397 if (err)
1398 break;
1399 err = hpi_dsp_code_read_block(length, &dsp_code,
1400 &pcode);
1401 if (err)
1402 break;
1403 for (i = 0; i < (int)length; i++) {
1404 boot_loader_write_mem32(pao, dsp, address,
1405 *pcode);
1406 /* dummy read every 4 words */
1407 /* for 6205 advisory 1.4.4 */
1408 if (i % 4 == 0)
1409 boot_loader_read_mem32(pao, dsp,
1410 address);
1411 pcode++;
1412 address += 4;
1413 }
1414
1415 }
1416 if (err) {
1417 hpi_dsp_code_close(&dsp_code);
1418 return err;
1419 }
1420
1421 /* verify code */
1422 hpi_dsp_code_rewind(&dsp_code);
1423 while (1) {
1424 u32 length = 0;
1425 u32 address = 0;
1426 u32 type = 0;
1427 u32 *pcode = NULL;
1428 u32 data = 0;
1429
1430 hpi_dsp_code_read_word(&dsp_code, &length);
1431 if (length == 0xFFFFFFFF)
1432 break; /* end of code */
1433
1434 hpi_dsp_code_read_word(&dsp_code, &address);
1435 hpi_dsp_code_read_word(&dsp_code, &type);
1436 hpi_dsp_code_read_block(length, &dsp_code, &pcode);
1437
1438 for (i = 0; i < (int)length; i++) {
1439 data = boot_loader_read_mem32(pao, dsp,
1440 address);
1441 if (data != *pcode) {
1442 err = 0;
1443 break;
1444 }
1445 pcode++;
1446 address += 4;
1447 }
1448 if (err)
1449 break;
1450 }
1451 hpi_dsp_code_close(&dsp_code);
1452 if (err)
1453 return err;
1454 }
1455
1456 /* After bootloading all DSPs, start DSP0 running
1457 * The DSP0 code will handle starting and synchronizing with its slaves
1458 */
1459 if (phw->p_interface_buffer) {
1460 /* we need to tell the card the physical PCI address */
1461 u32 physicalPC_iaddress;
1462 struct bus_master_interface *interface =
1463 phw->p_interface_buffer;
1464 u32 host_mailbox_address_on_dsp;
1465 u32 physicalPC_iaddress_verify = 0;
1466 int time_out = 10;
1467 /* set ack so we know when DSP is ready to go */
1468 /* (dwDspAck will be changed to HIF_RESET) */
1469 interface->dsp_ack = H620_HIF_UNKNOWN;
1470 wmb(); /* ensure ack is written before dsp writes back */
1471
1472 err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem,
1473 &physicalPC_iaddress);
1474
1475 /* locate the host mailbox on the DSP. */
1476 host_mailbox_address_on_dsp = 0x80000000;
1477 while ((physicalPC_iaddress != physicalPC_iaddress_verify)
1478 && time_out--) {
1479 boot_loader_write_mem32(pao, 0,
1480 host_mailbox_address_on_dsp,
1481 physicalPC_iaddress);
1482 physicalPC_iaddress_verify =
1483 boot_loader_read_mem32(pao, 0,
1484 host_mailbox_address_on_dsp);
1485 }
1486 }
1487 HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n");
1488 /* enable interrupts */
1489 temp = ioread32(phw->prHSR);
1490 temp &= ~(u32)C6205_HSR_INTAM;
1491 iowrite32(temp, phw->prHSR);
1492
1493 /* start code running... */
1494 temp = ioread32(phw->prHDCR);
1495 temp |= (u32)C6205_HDCR_DSPINT;
1496 iowrite32(temp, phw->prHDCR);
1497
1498 /* give the DSP 10ms to start up */
1499 hpios_delay_micro_seconds(10000);
1500 return err;
1501
1502 }
1503
1504 /*****************************************************************************/
1505 /* Bootloader utility functions */
1506
1507 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
1508 u32 address)
1509 {
1510 struct hpi_hw_obj *phw = pao->priv;
1511 u32 data = 0;
1512 __iomem u32 *p_data;
1513
1514 if (dsp_index == 0) {
1515 /* DSP 0 is always C6205 */
1516 if ((address >= 0x01800000) & (address < 0x02000000)) {
1517 /* BAR1 register access */
1518 p_data = pao->pci.ap_mem_base[1] +
1519 (address & 0x007fffff) /
1520 sizeof(*pao->pci.ap_mem_base[1]);
1521 /* HPI_DEBUG_LOG(WARNING,
1522 "BAR1 access %08x\n", dwAddress); */
1523 } else {
1524 u32 dw4M_page = address >> 22L;
1525 if (dw4M_page != phw->dsp_page) {
1526 phw->dsp_page = dw4M_page;
1527 /* *INDENT OFF* */
1528 iowrite32(phw->dsp_page, phw->prDSPP);
1529 /* *INDENT-ON* */
1530 }
1531 address &= 0x3fffff; /* address within 4M page */
1532 /* BAR0 memory access */
1533 p_data = pao->pci.ap_mem_base[0] +
1534 address / sizeof(u32);
1535 }
1536 data = ioread32(p_data);
1537 } else if (dsp_index == 1) {
1538 /* DSP 1 is a C6713 */
1539 u32 lsb;
1540 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1541 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1542 lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR);
1543 data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR);
1544 data = (data << 16) | (lsb & 0xFFFF);
1545 }
1546 return data;
1547 }
1548
1549 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
1550 int dsp_index, u32 address, u32 data)
1551 {
1552 struct hpi_hw_obj *phw = pao->priv;
1553 __iomem u32 *p_data;
1554 /* u32 dwVerifyData=0; */
1555
1556 if (dsp_index == 0) {
1557 /* DSP 0 is always C6205 */
1558 if ((address >= 0x01800000) & (address < 0x02000000)) {
1559 /* BAR1 - DSP register access using */
1560 /* Non-prefetchable PCI access */
1561 p_data = pao->pci.ap_mem_base[1] +
1562 (address & 0x007fffff) /
1563 sizeof(*pao->pci.ap_mem_base[1]);
1564 } else {
1565 /* BAR0 access - all of DSP memory using */
1566 /* pre-fetchable PCI access */
1567 u32 dw4M_page = address >> 22L;
1568 if (dw4M_page != phw->dsp_page) {
1569 phw->dsp_page = dw4M_page;
1570 /* *INDENT-OFF* */
1571 iowrite32(phw->dsp_page, phw->prDSPP);
1572 /* *INDENT-ON* */
1573 }
1574 address &= 0x3fffff; /* address within 4M page */
1575 p_data = pao->pci.ap_mem_base[0] +
1576 address / sizeof(u32);
1577 }
1578 iowrite32(data, p_data);
1579 } else if (dsp_index == 1) {
1580 /* DSP 1 is a C6713 */
1581 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1582 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1583
1584 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1585 boot_loader_read_mem32(pao, 0, 0);
1586
1587 boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data);
1588 boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16);
1589
1590 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1591 boot_loader_read_mem32(pao, 0, 0);
1592 }
1593 }
1594
1595 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index)
1596 {
1597 if (dsp_index == 0) {
1598 u32 setting;
1599
1600 /* DSP 0 is always C6205 */
1601
1602 /* Set the EMIF */
1603 /* memory map of C6205 */
1604 /* 00000000-0000FFFF 16Kx32 internal program */
1605 /* 00400000-00BFFFFF CE0 2Mx32 SDRAM running @ 100MHz */
1606
1607 /* EMIF config */
1608 /*------------ */
1609 /* Global EMIF control */
1610 boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779);
1611 #define WS_OFS 28
1612 #define WST_OFS 22
1613 #define WH_OFS 20
1614 #define RS_OFS 16
1615 #define RST_OFS 8
1616 #define MTYPE_OFS 4
1617 #define RH_OFS 0
1618
1619 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */
1620 setting = 0x00000030;
1621 boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting);
1622 if (setting != boot_loader_read_mem32(pao, dsp_index,
1623 0x01800008))
1624 return HPI6205_ERROR_DSP_EMIF;
1625
1626 /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */
1627 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1628 /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */
1629 /* WST should be 71, but 63 is max possible */
1630 setting =
1631 (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) |
1632 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1633 (2L << MTYPE_OFS);
1634 boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting);
1635 if (setting != boot_loader_read_mem32(pao, dsp_index,
1636 0x01800004))
1637 return HPI6205_ERROR_DSP_EMIF;
1638
1639 /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */
1640 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1641 /* plenty of wait states */
1642 setting =
1643 (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) |
1644 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1645 (2L << MTYPE_OFS);
1646 boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting);
1647 if (setting != boot_loader_read_mem32(pao, dsp_index,
1648 0x01800010))
1649 return HPI6205_ERROR_DSP_EMIF;
1650
1651 /* EMIF CE3 setup - 32 bit async. */
1652 /* This is the PLD on the ASI5000 cards only */
1653 setting =
1654 (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) |
1655 (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) |
1656 (2L << MTYPE_OFS);
1657 boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting);
1658 if (setting != boot_loader_read_mem32(pao, dsp_index,
1659 0x01800014))
1660 return HPI6205_ERROR_DSP_EMIF;
1661
1662 /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */
1663 /* need to use this else DSP code crashes? */
1664 boot_loader_write_mem32(pao, dsp_index, 0x01800018,
1665 0x07117000);
1666
1667 /* EMIF SDRAM Refresh Timing */
1668 /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */
1669 boot_loader_write_mem32(pao, dsp_index, 0x0180001C,
1670 0x00000410);
1671
1672 } else if (dsp_index == 1) {
1673 /* test access to the C6713s HPI registers */
1674 u32 write_data = 0, read_data = 0, i = 0;
1675
1676 /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */
1677 write_data = 1;
1678 boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data);
1679 boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data);
1680 /* C67 HPI is on lower 16bits of 32bit EMIF */
1681 read_data =
1682 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR);
1683 if (write_data != read_data) {
1684 HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data,
1685 read_data);
1686 return HPI6205_ERROR_C6713_HPIC;
1687 }
1688 /* HPIA - walking ones test */
1689 write_data = 1;
1690 for (i = 0; i < 32; i++) {
1691 boot_loader_write_mem32(pao, 0, HPIAL_ADDR,
1692 write_data);
1693 boot_loader_write_mem32(pao, 0, HPIAH_ADDR,
1694 (write_data >> 16));
1695 read_data =
1696 0xFFFF & boot_loader_read_mem32(pao, 0,
1697 HPIAL_ADDR);
1698 read_data =
1699 read_data | ((0xFFFF &
1700 boot_loader_read_mem32(pao, 0,
1701 HPIAH_ADDR))
1702 << 16);
1703 if (read_data != write_data) {
1704 HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n",
1705 write_data, read_data);
1706 return HPI6205_ERROR_C6713_HPIA;
1707 }
1708 write_data = write_data << 1;
1709 }
1710
1711 /* setup C67x PLL
1712 * ** C6713 datasheet says we cannot program PLL from HPI,
1713 * and indeed if we try to set the PLL multiply from the HPI,
1714 * the PLL does not seem to lock, so we enable the PLL and
1715 * use the default multiply of x 7, which for a 27MHz clock
1716 * gives a DSP speed of 189MHz
1717 */
1718 /* bypass PLL */
1719 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000);
1720 hpios_delay_micro_seconds(1000);
1721 /* EMIF = 189/3=63MHz */
1722 boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002);
1723 /* peri = 189/2 */
1724 boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001);
1725 /* cpu = 189/1 */
1726 boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000);
1727 hpios_delay_micro_seconds(1000);
1728 /* ** SGT test to take GPO3 high when we start the PLL */
1729 /* and low when the delay is completed */
1730 /* FSX0 <- '1' (GPO3) */
1731 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A);
1732 /* PLL not bypassed */
1733 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001);
1734 hpios_delay_micro_seconds(1000);
1735 /* FSX0 <- '0' (GPO3) */
1736 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02);
1737
1738 /* 6205 EMIF CE1 resetup - 32 bit async. */
1739 /* Now 6713 #1 is running at 189MHz can reduce waitstates */
1740 boot_loader_write_mem32(pao, 0, 0x01800004, /* CE1 */
1741 (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) |
1742 (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) |
1743 (2L << MTYPE_OFS));
1744
1745 hpios_delay_micro_seconds(1000);
1746
1747 /* check that we can read one of the PLL registers */
1748 /* PLL should not be bypassed! */
1749 if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF)
1750 != 0x0001) {
1751 return HPI6205_ERROR_C6713_PLL;
1752 }
1753 /* setup C67x EMIF (note this is the only use of
1754 BAR1 via BootLoader_WriteMem32) */
1755 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL,
1756 0x000034A8);
1757
1758 /* EMIF CE0 setup - 2Mx32 Sync DRAM
1759 31..28 Wr setup
1760 27..22 Wr strobe
1761 21..20 Wr hold
1762 19..16 Rd setup
1763 15..14 -
1764 13..8 Rd strobe
1765 7..4 MTYPE 0011 Sync DRAM 32bits
1766 3 Wr hold MSB
1767 2..0 Rd hold
1768 */
1769 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0,
1770 0x00000030);
1771
1772 /* EMIF SDRAM Extension
1773 0x00
1774 31-21 0000b 0000b 000b
1775 20 WR2RD = 2cycles-1 = 1b
1776
1777 19-18 WR2DEAC = 3cycle-1 = 10b
1778 17 WR2WR = 2cycle-1 = 1b
1779 16-15 R2WDQM = 4cycle-1 = 11b
1780 14-12 RD2WR = 6cycles-1 = 101b
1781
1782 11-10 RD2DEAC = 4cycle-1 = 11b
1783 9 RD2RD = 2cycle-1 = 1b
1784 8-7 THZP = 3cycle-1 = 10b
1785 6-5 TWR = 2cycle-1 = 01b (tWR = 17ns)
1786 4 TRRD = 2cycle = 0b (tRRD = 14ns)
1787 3-1 TRAS = 5cycle-1 = 100b (Tras=42ns)
1788 1 CAS latency = 3cyc = 1b
1789 (for Micron 2M32-7 operating at 100MHz)
1790 */
1791 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT,
1792 0x001BDF29);
1793
1794 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
1795 31 - 0b -
1796 30 SDBSZ 1b 4 bank
1797 29..28 SDRSZ 00b 11 row address pins
1798
1799 27..26 SDCSZ 01b 8 column address pins
1800 25 RFEN 1b refersh enabled
1801 24 INIT 1b init SDRAM!
1802
1803 23..20 TRCD 0001b (Trcd/Tcyc)-1 = (20/10)-1 = 1
1804
1805 19..16 TRP 0001b (Trp/Tcyc)-1 = (20/10)-1 = 1
1806
1807 15..12 TRC 0110b (Trc/Tcyc)-1 = (70/10)-1 = 6
1808
1809 11..0 - 0000b 0000b 0000b
1810 */
1811 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL,
1812 0x47116000);
1813
1814 /* SDRAM refresh timing
1815 Need 4,096 refresh cycles every 64ms = 15.625us = 1562cycles of 100MHz = 0x61A
1816 */
1817 boot_loader_write_mem32(pao, dsp_index,
1818 C6713_EMIF_SDRAMTIMING, 0x00000410);
1819
1820 hpios_delay_micro_seconds(1000);
1821 } else if (dsp_index == 2) {
1822 /* DSP 2 is a C6713 */
1823 }
1824
1825 return 0;
1826 }
1827
1828 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
1829 u32 start_address, u32 length)
1830 {
1831 u32 i = 0, j = 0;
1832 u32 test_addr = 0;
1833 u32 test_data = 0, data = 0;
1834
1835 length = 1000;
1836
1837 /* for 1st word, test each bit in the 32bit word, */
1838 /* dwLength specifies number of 32bit words to test */
1839 /*for(i=0; i<dwLength; i++) */
1840 i = 0;
1841 {
1842 test_addr = start_address + i * 4;
1843 test_data = 0x00000001;
1844 for (j = 0; j < 32; j++) {
1845 boot_loader_write_mem32(pao, dsp_index, test_addr,
1846 test_data);
1847 data = boot_loader_read_mem32(pao, dsp_index,
1848 test_addr);
1849 if (data != test_data) {
1850 HPI_DEBUG_LOG(VERBOSE,
1851 "Memtest error details "
1852 "%08x %08x %08x %i\n", test_addr,
1853 test_data, data, dsp_index);
1854 return 1; /* error */
1855 }
1856 test_data = test_data << 1;
1857 } /* for(j) */
1858 } /* for(i) */
1859
1860 /* for the next 100 locations test each location, leaving it as zero */
1861 /* write a zero to the next word in memory before we read */
1862 /* the previous write to make sure every memory location is unique */
1863 for (i = 0; i < 100; i++) {
1864 test_addr = start_address + i * 4;
1865 test_data = 0xA5A55A5A;
1866 boot_loader_write_mem32(pao, dsp_index, test_addr, test_data);
1867 boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0);
1868 data = boot_loader_read_mem32(pao, dsp_index, test_addr);
1869 if (data != test_data) {
1870 HPI_DEBUG_LOG(VERBOSE,
1871 "Memtest error details "
1872 "%08x %08x %08x %i\n", test_addr, test_data,
1873 data, dsp_index);
1874 return 1; /* error */
1875 }
1876 /* leave location as zero */
1877 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1878 }
1879
1880 /* zero out entire memory block */
1881 for (i = 0; i < length; i++) {
1882 test_addr = start_address + i * 4;
1883 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1884 }
1885 return 0;
1886 }
1887
1888 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
1889 int dsp_index)
1890 {
1891 int err = 0;
1892 if (dsp_index == 0) {
1893 /* DSP 0 is a C6205 */
1894 /* 64K prog mem */
1895 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1896 0x10000);
1897 if (!err)
1898 /* 64K data mem */
1899 err = boot_loader_test_memory(pao, dsp_index,
1900 0x80000000, 0x10000);
1901 } else if (dsp_index == 1) {
1902 /* DSP 1 is a C6713 */
1903 /* 192K internal mem */
1904 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1905 0x30000);
1906 if (!err)
1907 /* 64K internal mem / L2 cache */
1908 err = boot_loader_test_memory(pao, dsp_index,
1909 0x00030000, 0x10000);
1910 }
1911
1912 if (err)
1913 return HPI6205_ERROR_DSP_INTMEM;
1914 else
1915 return 0;
1916 }
1917
1918 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
1919 int dsp_index)
1920 {
1921 u32 dRAM_start_address = 0;
1922 u32 dRAM_size = 0;
1923
1924 if (dsp_index == 0) {
1925 /* only test for SDRAM if an ASI5000 card */
1926 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
1927 /* DSP 0 is always C6205 */
1928 dRAM_start_address = 0x00400000;
1929 dRAM_size = 0x200000;
1930 /*dwDRAMinc=1024; */
1931 } else
1932 return 0;
1933 } else if (dsp_index == 1) {
1934 /* DSP 1 is a C6713 */
1935 dRAM_start_address = 0x80000000;
1936 dRAM_size = 0x200000;
1937 /*dwDRAMinc=1024; */
1938 }
1939
1940 if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address,
1941 dRAM_size))
1942 return HPI6205_ERROR_DSP_EXTMEM;
1943 return 0;
1944 }
1945
1946 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index)
1947 {
1948 u32 data = 0;
1949 if (dsp_index == 0) {
1950 /* only test for DSP0 PLD on ASI5000 card */
1951 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
1952 /* PLD is located at CE3=0x03000000 */
1953 data = boot_loader_read_mem32(pao, dsp_index,
1954 0x03000008);
1955 if ((data & 0xF) != 0x5)
1956 return HPI6205_ERROR_DSP_PLD;
1957 data = boot_loader_read_mem32(pao, dsp_index,
1958 0x0300000C);
1959 if ((data & 0xF) != 0xA)
1960 return HPI6205_ERROR_DSP_PLD;
1961 }
1962 } else if (dsp_index == 1) {
1963 /* DSP 1 is a C6713 */
1964 if (pao->pci.pci_dev->subsystem_device == 0x8700) {
1965 /* PLD is located at CE1=0x90000000 */
1966 data = boot_loader_read_mem32(pao, dsp_index,
1967 0x90000010);
1968 if ((data & 0xFF) != 0xAA)
1969 return HPI6205_ERROR_DSP_PLD;
1970 /* 8713 - LED on */
1971 boot_loader_write_mem32(pao, dsp_index, 0x90000000,
1972 0x02);
1973 }
1974 }
1975 return 0;
1976 }
1977
1978 /** Transfer data to or from DSP
1979 nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA
1980 */
1981 static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data,
1982 u32 data_size, int operation)
1983 {
1984 struct hpi_hw_obj *phw = pao->priv;
1985 u32 data_transferred = 0;
1986 u16 err = 0;
1987 u32 temp2;
1988 struct bus_master_interface *interface = phw->p_interface_buffer;
1989
1990 if (!p_data)
1991 return HPI_ERROR_INVALID_DATA_POINTER;
1992
1993 data_size &= ~3L; /* round data_size down to nearest 4 bytes */
1994
1995 /* make sure state is IDLE */
1996 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT))
1997 return HPI_ERROR_DSP_HARDWARE;
1998
1999 while (data_transferred < data_size) {
2000 u32 this_copy = data_size - data_transferred;
2001
2002 if (this_copy > HPI6205_SIZEOF_DATA)
2003 this_copy = HPI6205_SIZEOF_DATA;
2004
2005 if (operation == H620_HIF_SEND_DATA)
2006 memcpy((void *)&interface->u.b_data[0],
2007 &p_data[data_transferred], this_copy);
2008
2009 interface->transfer_size_in_bytes = this_copy;
2010
2011 /* DSP must change this back to nOperation */
2012 interface->dsp_ack = H620_HIF_IDLE;
2013 send_dsp_command(phw, operation);
2014
2015 temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT);
2016 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
2017 HPI6205_TIMEOUT - temp2, this_copy);
2018
2019 if (!temp2) {
2020 /* timed out */
2021 HPI_DEBUG_LOG(ERROR,
2022 "Timed out waiting for " "state %d got %d\n",
2023 operation, interface->dsp_ack);
2024
2025 break;
2026 }
2027 if (operation == H620_HIF_GET_DATA)
2028 memcpy(&p_data[data_transferred],
2029 (void *)&interface->u.b_data[0], this_copy);
2030
2031 data_transferred += this_copy;
2032 }
2033 if (interface->dsp_ack != operation)
2034 HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n",
2035 interface->dsp_ack, operation);
2036 /* err=HPI_ERROR_DSP_HARDWARE; */
2037
2038 send_dsp_command(phw, H620_HIF_IDLE);
2039
2040 return err;
2041 }
2042
2043 /* wait for up to timeout_us microseconds for the DSP
2044 to signal state by DMA into dwDspAck
2045 */
2046 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us)
2047 {
2048 struct bus_master_interface *interface = phw->p_interface_buffer;
2049 int t = timeout_us / 4;
2050
2051 rmb(); /* ensure interface->dsp_ack is up to date */
2052 while ((interface->dsp_ack != state) && --t) {
2053 hpios_delay_micro_seconds(4);
2054 rmb(); /* DSP changes dsp_ack by DMA */
2055 }
2056
2057 /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */
2058 return t * 4;
2059 }
2060
2061 /* set the busmaster interface to cmd, then interrupt the DSP */
2062 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd)
2063 {
2064 struct bus_master_interface *interface = phw->p_interface_buffer;
2065 u32 r;
2066
2067 interface->host_cmd = cmd;
2068 wmb(); /* DSP gets state by DMA, make sure it is written to memory */
2069 /* before we interrupt the DSP */
2070 r = ioread32(phw->prHDCR);
2071 r |= (u32)C6205_HDCR_DSPINT;
2072 iowrite32(r, phw->prHDCR);
2073 r &= ~(u32)C6205_HDCR_DSPINT;
2074 iowrite32(r, phw->prHDCR);
2075 }
2076
2077 static unsigned int message_count;
2078
2079 static u16 message_response_sequence(struct hpi_adapter_obj *pao,
2080 struct hpi_message *phm, struct hpi_response *phr)
2081 {
2082 u32 time_out, time_out2;
2083 struct hpi_hw_obj *phw = pao->priv;
2084 struct bus_master_interface *interface = phw->p_interface_buffer;
2085 u16 err = 0;
2086
2087 message_count++;
2088 if (phm->size > sizeof(interface->u)) {
2089 phr->error = HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL;
2090 phr->specific_error = sizeof(interface->u);
2091 phr->size = sizeof(struct hpi_response_header);
2092 HPI_DEBUG_LOG(ERROR,
2093 "message len %d too big for buffer %zd \n", phm->size,
2094 sizeof(interface->u));
2095 return 0;
2096 }
2097
2098 /* Assume buffer of type struct bus_master_interface
2099 is allocated "noncacheable" */
2100
2101 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2102 HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n");
2103 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
2104 }
2105
2106 memcpy(&interface->u.message_buffer, phm, phm->size);
2107 /* signal we want a response */
2108 send_dsp_command(phw, H620_HIF_GET_RESP);
2109
2110 time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT);
2111
2112 if (!time_out2) {
2113 HPI_DEBUG_LOG(ERROR,
2114 "(%u) Timed out waiting for " "GET_RESP state [%x]\n",
2115 message_count, interface->dsp_ack);
2116 } else {
2117 HPI_DEBUG_LOG(VERBOSE,
2118 "(%u) transition to GET_RESP after %u\n",
2119 message_count, HPI6205_TIMEOUT - time_out2);
2120 }
2121 /* spin waiting on HIF interrupt flag (end of msg process) */
2122 time_out = HPI6205_TIMEOUT;
2123
2124 /* read the result */
2125 if (time_out) {
2126 if (interface->u.response_buffer.size <= phr->size)
2127 memcpy(phr, &interface->u.response_buffer,
2128 interface->u.response_buffer.size);
2129 else {
2130 HPI_DEBUG_LOG(ERROR,
2131 "response len %d too big for buffer %d\n",
2132 interface->u.response_buffer.size, phr->size);
2133 memcpy(phr, &interface->u.response_buffer,
2134 sizeof(struct hpi_response_header));
2135 phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL;
2136 phr->specific_error =
2137 interface->u.response_buffer.size;
2138 phr->size = sizeof(struct hpi_response_header);
2139 }
2140 }
2141 /* set interface back to idle */
2142 send_dsp_command(phw, H620_HIF_IDLE);
2143
2144 if (!time_out || !time_out2) {
2145 HPI_DEBUG_LOG(DEBUG, "something timed out!\n");
2146 return HPI6205_ERROR_MSG_RESP_TIMEOUT;
2147 }
2148 /* special case for adapter close - */
2149 /* wait for the DSP to indicate it is idle */
2150 if (phm->function == HPI_ADAPTER_CLOSE) {
2151 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2152 HPI_DEBUG_LOG(DEBUG,
2153 "Timeout waiting for idle "
2154 "(on adapter_close)\n");
2155 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
2156 }
2157 }
2158 err = hpi_validate_response(phm, phr);
2159 return err;
2160 }
2161
2162 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
2163 struct hpi_response *phr)
2164 {
2165
2166 u16 err = 0;
2167
2168 hpios_dsplock_lock(pao);
2169
2170 err = message_response_sequence(pao, phm, phr);
2171
2172 /* maybe an error response */
2173 if (err) {
2174 /* something failed in the HPI/DSP interface */
2175 if (err >= HPI_ERROR_BACKEND_BASE) {
2176 phr->error = HPI_ERROR_DSP_COMMUNICATION;
2177 phr->specific_error = err;
2178 } else {
2179 phr->error = err;
2180 }
2181
2182 pao->dsp_crashed++;
2183
2184 /* just the header of the response is valid */
2185 phr->size = sizeof(struct hpi_response_header);
2186 goto err;
2187 } else
2188 pao->dsp_crashed = 0;
2189
2190 if (phr->error != 0) /* something failed in the DSP */
2191 goto err;
2192
2193 switch (phm->function) {
2194 case HPI_OSTREAM_WRITE:
2195 case HPI_ISTREAM_ANC_WRITE:
2196 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2197 phm->u.d.u.data.data_size, H620_HIF_SEND_DATA);
2198 break;
2199
2200 case HPI_ISTREAM_READ:
2201 case HPI_OSTREAM_ANC_READ:
2202 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2203 phm->u.d.u.data.data_size, H620_HIF_GET_DATA);
2204 break;
2205
2206 case HPI_CONTROL_SET_STATE:
2207 if (phm->object == HPI_OBJ_CONTROLEX
2208 && phm->u.cx.attribute == HPI_COBRANET_SET_DATA)
2209 err = hpi6205_transfer_data(pao,
2210 phm->u.cx.u.cobranet_bigdata.pb_data,
2211 phm->u.cx.u.cobranet_bigdata.byte_count,
2212 H620_HIF_SEND_DATA);
2213 break;
2214
2215 case HPI_CONTROL_GET_STATE:
2216 if (phm->object == HPI_OBJ_CONTROLEX
2217 && phm->u.cx.attribute == HPI_COBRANET_GET_DATA)
2218 err = hpi6205_transfer_data(pao,
2219 phm->u.cx.u.cobranet_bigdata.pb_data,
2220 phr->u.cx.u.cobranet_data.byte_count,
2221 H620_HIF_GET_DATA);
2222 break;
2223 }
2224 phr->error = err;
2225
2226 err:
2227 hpios_dsplock_unlock(pao);
2228
2229 return;
2230 }
Linux kernel - Deliverables
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