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[ALSA] PCI168 snd-azt3328 Linux driver: another huge update
[deliverable/linux.git] / sound / pci / azt3328.c
1 /*
2 * azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
3 * Copyright (C) 2002, 2005 - 2008 by Andreas Mohr <andi AT lisas.de>
4 *
5 * Framework borrowed from Bart Hartgers's als4000.c.
6 * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801),
7 * found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
8 * Other versions are:
9 * PCI168 A(W), sub ID 1800
10 * PCI168 A/AP, sub ID 8000
11 * Please give me feedback in case you try my driver with one of these!!
12 *
13 * GPL LICENSE
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 * NOTES
29 * Since Aztech does not provide any chipset documentation,
30 * even on repeated request to various addresses,
31 * and the answer that was finally given was negative
32 * (and I was stupid enough to manage to get hold of a PCI168 soundcard
33 * in the first place >:-P}),
34 * I was forced to base this driver on reverse engineering
35 * (3 weeks' worth of evenings filled with driver work).
36 * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros)
37 *
38 * It is quite likely that the AZF3328 chip is the PCI cousin of the
39 * AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs.
40 *
41 * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
42 * for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec,
43 * Fincitec acquired by National Semiconductor in 2002, together with the
44 * Fincitec-related company ARSmikro) has the following features:
45 *
46 * - compatibility & compliance:
47 * - Microsoft PC 97 ("PC 97 Hardware Design Guide",
48 * http://www.microsoft.com/whdc/archive/pcguides.mspx)
49 * - Microsoft PC 98 Baseline Audio
50 * - MPU401 UART
51 * - Sound Blaster Emulation (DOS Box)
52 * - builtin AC97 conformant codec (SNR over 80dB)
53 * Note that "conformant" != "compliant"!! this chip's mixer register layout
54 * *differs* from the standard AC97 layout:
55 * they chose to not implement the headphone register (which is not a
56 * problem since it's merely optional), yet when doing this, they committed
57 * the grave sin of letting other registers follow immediately instead of
58 * keeping a headphone dummy register, thereby shifting the mixer register
59 * addresses illegally. So far unfortunately it looks like the very flexible
60 * ALSA AC97 support is still not enough to easily compensate for such a
61 * grave layout violation despite all tweaks and quirks mechanisms it offers.
62 * - builtin genuine OPL3 - verified to work fine, 20080506
63 * - full duplex 16bit playback/record at independent sampling rate
64 * - MPU401 (+ legacy address support, claimed by one official spec sheet)
65 * FIXME: how to enable legacy addr??
66 * - game port (legacy address support)
67 * - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven
68 * features supported). - See common term "Digital Enhanced Game Port"...
69 * (probably DirectInput 3.0 spec - confirm)
70 * - builtin 3D enhancement (said to be YAMAHA Ymersion)
71 * - built-in General DirectX timer having a 20 bits counter
72 * with 1us resolution (see below!)
73 * - I2S serial output port for external DAC
74 * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI
75 * - supports hardware volume control
76 * - single chip low cost solution (128 pin QFP)
77 * - supports programmable Sub-vendor and Sub-system ID
78 * required for Microsoft's logo compliance (FIXME: where?)
79 * At least the Trident 4D Wave DX has one bit somewhere
80 * to enable writes to PCI subsystem VID registers, that should be it.
81 * This might easily be in extended PCI reg space, since PCI168 also has
82 * some custom data starting at 0x80. What kind of config settings
83 * are located in our extended PCI space anyway??
84 * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms
85 *
86 * Note that this driver now is actually *better* than the Windows driver,
87 * since it additionally supports the card's 1MHz DirectX timer - just try
88 * the following snd-seq module parameters etc.:
89 * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
90 * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
91 * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
92 * - "timidity -iAv -B2,8 -Os -EFreverb=0"
93 * - "pmidi -p 128:0 jazz.mid"
94 *
95 * OPL3 hardware playback testing, try something like:
96 * cat /proc/asound/hwdep
97 * and
98 * aconnect -o
99 * Then use
100 * sbiload -Dhw:x,y --opl3 /usr/share/sounds/opl3/std.o3 ......./drums.o3
101 * where x,y is the xx-yy number as given in hwdep.
102 * Then try
103 * pmidi -p a:b jazz.mid
104 * where a:b is the client number plus 0 usually, as given by aconnect above.
105 * Oh, and make sure to unmute the FM mixer control (doh!)
106 * NOTE: power use during OPL3 playback is _VERY_ high (70W --> 90W!)
107 * despite no CPU activity, possibly due to hindering ACPI idling somehow.
108 * Shouldn't be a problem of the AZF3328 chip itself, I'd hope.
109 * Higher PCM / FM mixer levels seem to conflict (causes crackling),
110 * at least sometimes. Maybe even use with hardware sequencer timer above :)
111 * adplay/adplug-utils might soon offer hardware-based OPL3 playback, too.
112 *
113 * Certain PCI versions of this card are susceptible to DMA traffic underruns
114 * in some systems (resulting in sound crackling/clicking/popping),
115 * probably because they don't have a DMA FIFO buffer or so.
116 * Overview (PCI ID/PCI subID/PCI rev.):
117 * - no DMA crackling on SiS735: 0x50DC/0x1801/16
118 * - unknown performance: 0x50DC/0x1801/10
119 * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler)
120 *
121 * Crackling happens with VIA chipsets or, in my case, an SiS735, which is
122 * supposed to be very fast and supposed to get rid of crackling much
123 * better than a VIA, yet ironically I still get crackling, like many other
124 * people with the same chipset.
125 * Possible remedies:
126 * - use speaker (amplifier) output instead of headphone output
127 * (in case crackling is due to overloaded output clipping)
128 * - plug card into a different PCI slot, preferrably one that isn't shared
129 * too much (this helps a lot, but not completely!)
130 * - get rid of PCI VGA card, use AGP instead
131 * - upgrade or downgrade BIOS
132 * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX)
133 * Not too helpful.
134 * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS
135 *
136 * BUGS
137 * - full-duplex might *still* be problematic, however a recent test was fine
138 * - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated
139 * if you set PCM output switch to "pre 3D" instead of "post 3D".
140 * If this can't be set, then get a mixer application that Isn't Stupid (tm)
141 * (e.g. kmix, gamix) - unfortunately several are!!
142 * - locking is not entirely clean, especially the audio stream activity
143 * ints --> may be racy
144 * - an _unconnected_ secondary joystick at the gameport will be reported
145 * to be "active" (floating values, not precisely -1) due to the way we need
146 * to read the Digital Enhanced Game Port. Not sure whether it is fixable.
147 *
148 * TODO
149 * - test MPU401 MIDI playback etc.
150 * - add more power micro-management (disable various units of the card
151 * as long as they're unused). However this requires more I/O ports which I
152 * haven't figured out yet and which thus might not even exist...
153 * The standard suspend/resume functionality could probably make use of
154 * some improvement, too...
155 * - figure out what all unknown port bits are responsible for
156 * - figure out some cleverly evil scheme to possibly make ALSA AC97 code
157 * fully accept our quite incompatible ""AC97"" mixer and thus save some
158 * code (but I'm not too optimistic that doing this is possible at all)
159 * - use MMIO (memory-mapped I/O)? Slightly faster access, e.g. for gameport.
160 */
161
162 #include <asm/io.h>
163 #include <linux/init.h>
164 #include <linux/pci.h>
165 #include <linux/delay.h>
166 #include <linux/slab.h>
167 #include <linux/gameport.h>
168 #include <linux/moduleparam.h>
169 #include <linux/dma-mapping.h>
170 #include <sound/core.h>
171 #include <sound/control.h>
172 #include <sound/pcm.h>
173 #include <sound/rawmidi.h>
174 #include <sound/mpu401.h>
175 #include <sound/opl3.h>
176 #include <sound/initval.h>
177 #include "azt3328.h"
178
179 MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
180 MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
181 MODULE_LICENSE("GPL");
182 MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
183
184 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
185 #define SUPPORT_GAMEPORT 1
186 #endif
187
188 #define DEBUG_MISC 0
189 #define DEBUG_CALLS 0
190 #define DEBUG_MIXER 0
191 #define DEBUG_PLAY_REC 0
192 #define DEBUG_IO 0
193 #define DEBUG_TIMER 0
194 #define DEBUG_GAME 0
195 #define MIXER_TESTING 0
196
197 #if DEBUG_MISC
198 #define snd_azf3328_dbgmisc(format, args...) printk(KERN_ERR format, ##args)
199 #else
200 #define snd_azf3328_dbgmisc(format, args...)
201 #endif
202
203 #if DEBUG_CALLS
204 #define snd_azf3328_dbgcalls(format, args...) printk(format, ##args)
205 #define snd_azf3328_dbgcallenter() printk(KERN_ERR "--> %s\n", __func__)
206 #define snd_azf3328_dbgcallleave() printk(KERN_ERR "<-- %s\n", __func__)
207 #else
208 #define snd_azf3328_dbgcalls(format, args...)
209 #define snd_azf3328_dbgcallenter()
210 #define snd_azf3328_dbgcallleave()
211 #endif
212
213 #if DEBUG_MIXER
214 #define snd_azf3328_dbgmixer(format, args...) printk(format, ##args)
215 #else
216 #define snd_azf3328_dbgmixer(format, args...)
217 #endif
218
219 #if DEBUG_PLAY_REC
220 #define snd_azf3328_dbgplay(format, args...) printk(KERN_ERR format, ##args)
221 #else
222 #define snd_azf3328_dbgplay(format, args...)
223 #endif
224
225 #if DEBUG_MISC
226 #define snd_azf3328_dbgtimer(format, args...) printk(KERN_ERR format, ##args)
227 #else
228 #define snd_azf3328_dbgtimer(format, args...)
229 #endif
230
231 #if DEBUG_GAME
232 #define snd_azf3328_dbggame(format, args...) printk(KERN_ERR format, ##args)
233 #else
234 #define snd_azf3328_dbggame(format, args...)
235 #endif
236
237 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
238 module_param_array(index, int, NULL, 0444);
239 MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
240
241 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
242 module_param_array(id, charp, NULL, 0444);
243 MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
244
245 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
246 module_param_array(enable, bool, NULL, 0444);
247 MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
248
249 static int seqtimer_scaling = 128;
250 module_param(seqtimer_scaling, int, 0444);
251 MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
252
253 struct snd_azf3328_audio_stream {
254 struct snd_pcm_substream *substream;
255 int enabled;
256 int running;
257 unsigned long portbase;
258 };
259
260 enum snd_azf3328_stream_index {
261 AZF_PLAYBACK = 0,
262 AZF_CAPTURE = 1,
263 };
264
265 struct snd_azf3328 {
266 /* often-used fields towards beginning, then grouped */
267
268 unsigned long codec_io; /* usually 0xb000, size 128 */
269 unsigned long game_io; /* usually 0xb400, size 8 */
270 unsigned long mpu_io; /* usually 0xb800, size 4 */
271 unsigned long opl3_io; /* usually 0xbc00, size 8 */
272 unsigned long mixer_io; /* usually 0xc000, size 64 */
273
274 spinlock_t reg_lock;
275
276 struct snd_timer *timer;
277
278 struct snd_pcm *pcm;
279 struct snd_azf3328_audio_stream audio_stream[2];
280
281 struct snd_card *card;
282 struct snd_rawmidi *rmidi;
283
284 #ifdef SUPPORT_GAMEPORT
285 struct gameport *gameport;
286 int axes[4];
287 #endif
288
289 struct pci_dev *pci;
290 int irq;
291
292 #ifdef CONFIG_PM
293 /* register value containers for power management
294 * Note: not always full I/O range preserved (just like Win driver!) */
295 u16 saved_regs_codec[AZF_IO_SIZE_CODEC_PM / 2];
296 u16 saved_regs_game [AZF_IO_SIZE_GAME_PM / 2];
297 u16 saved_regs_mpu [AZF_IO_SIZE_MPU_PM / 2];
298 u16 saved_regs_opl3 [AZF_IO_SIZE_OPL3_PM / 2];
299 u16 saved_regs_mixer[AZF_IO_SIZE_MIXER_PM / 2];
300 #endif
301 };
302
303 static const struct pci_device_id snd_azf3328_ids[] = {
304 { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */
305 { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */
306 { 0, }
307 };
308
309 MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
310
311
312 static int
313 snd_azf3328_io_reg_setb(unsigned reg, u8 mask, int do_set)
314 {
315 u8 prev = inb(reg), new;
316
317 new = (do_set) ? (prev|mask) : (prev & ~mask);
318 /* we need to always write the new value no matter whether it differs
319 * or not, since some register bits don't indicate their setting */
320 outb(new, reg);
321 if (new != prev)
322 return 1;
323
324 return 0;
325 }
326
327 static int
328 snd_azf3328_io_reg_setw(unsigned reg, u16 mask, int do_set)
329 {
330 u16 prev = inw(reg), new;
331
332 new = (do_set) ? (prev|mask) : (prev & ~mask);
333 /* we need to always write the new value no matter whether it differs
334 * or not, since some register bits don't indicate their setting */
335 outw(new, reg);
336 if (new != prev)
337 return 1;
338
339 return 0;
340 }
341
342 static inline void
343 snd_azf3328_codec_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
344 {
345 outb(value, chip->codec_io + reg);
346 }
347
348 static inline u8
349 snd_azf3328_codec_inb(const struct snd_azf3328 *chip, unsigned reg)
350 {
351 return inb(chip->codec_io + reg);
352 }
353
354 static inline void
355 snd_azf3328_codec_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
356 {
357 outw(value, chip->codec_io + reg);
358 }
359
360 static inline u16
361 snd_azf3328_codec_inw(const struct snd_azf3328 *chip, unsigned reg)
362 {
363 return inw(chip->codec_io + reg);
364 }
365
366 static inline void
367 snd_azf3328_codec_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value)
368 {
369 outl(value, chip->codec_io + reg);
370 }
371
372 static inline u32
373 snd_azf3328_codec_inl(const struct snd_azf3328 *chip, unsigned reg)
374 {
375 return inl(chip->codec_io + reg);
376 }
377
378 static inline void
379 snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
380 {
381 outb(value, chip->game_io + reg);
382 }
383
384 static inline void
385 snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
386 {
387 outw(value, chip->game_io + reg);
388 }
389
390 static inline u8
391 snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg)
392 {
393 return inb(chip->game_io + reg);
394 }
395
396 static inline u16
397 snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg)
398 {
399 return inw(chip->game_io + reg);
400 }
401
402 static inline void
403 snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
404 {
405 outw(value, chip->mixer_io + reg);
406 }
407
408 static inline u16
409 snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg)
410 {
411 return inw(chip->mixer_io + reg);
412 }
413
414 #define AZF_MUTE_BIT 0x80
415
416 static int
417 snd_azf3328_mixer_set_mute(const struct snd_azf3328 *chip,
418 unsigned reg, int do_mute
419 )
420 {
421 unsigned long portbase = chip->mixer_io + reg + 1;
422 int updated;
423
424 /* the mute bit is on the *second* (i.e. right) register of a
425 * left/right channel setting */
426 updated = snd_azf3328_io_reg_setb(portbase, AZF_MUTE_BIT, do_mute);
427
428 /* indicate whether it was muted before */
429 return (do_mute) ? !updated : updated;
430 }
431
432 static void
433 snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip,
434 unsigned reg,
435 unsigned char dst_vol_left,
436 unsigned char dst_vol_right,
437 int chan_sel, int delay
438 )
439 {
440 unsigned long portbase = chip->mixer_io + reg;
441 unsigned char curr_vol_left = 0, curr_vol_right = 0;
442 int left_change = 0, right_change = 0;
443
444 snd_azf3328_dbgcallenter();
445
446 if (chan_sel & SET_CHAN_LEFT) {
447 curr_vol_left = inb(portbase + 1);
448
449 /* take care of muting flag contained in left channel */
450 if (curr_vol_left & AZF_MUTE_BIT)
451 dst_vol_left |= AZF_MUTE_BIT;
452 else
453 dst_vol_left &= ~AZF_MUTE_BIT;
454
455 left_change = (curr_vol_left > dst_vol_left) ? -1 : 1;
456 }
457
458 if (chan_sel & SET_CHAN_RIGHT) {
459 curr_vol_right = inb(portbase + 0);
460
461 right_change = (curr_vol_right > dst_vol_right) ? -1 : 1;
462 }
463
464 do {
465 if (left_change) {
466 if (curr_vol_left != dst_vol_left) {
467 curr_vol_left += left_change;
468 outb(curr_vol_left, portbase + 1);
469 } else
470 left_change = 0;
471 }
472 if (right_change) {
473 if (curr_vol_right != dst_vol_right) {
474 curr_vol_right += right_change;
475
476 /* during volume change, the right channel is crackling
477 * somewhat more than the left channel, unfortunately.
478 * This seems to be a hardware issue. */
479 outb(curr_vol_right, portbase + 0);
480 } else
481 right_change = 0;
482 }
483 if (delay)
484 mdelay(delay);
485 } while ((left_change) || (right_change));
486 snd_azf3328_dbgcallleave();
487 }
488
489 /*
490 * general mixer element
491 */
492 struct azf3328_mixer_reg {
493 unsigned reg;
494 unsigned int lchan_shift, rchan_shift;
495 unsigned int mask;
496 unsigned int invert: 1;
497 unsigned int stereo: 1;
498 unsigned int enum_c: 4;
499 };
500
501 #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
502 ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
503 (mask << 16) | \
504 (invert << 24) | \
505 (stereo << 25) | \
506 (enum_c << 26))
507
508 static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
509 {
510 r->reg = val & 0xff;
511 r->lchan_shift = (val >> 8) & 0x0f;
512 r->rchan_shift = (val >> 12) & 0x0f;
513 r->mask = (val >> 16) & 0xff;
514 r->invert = (val >> 24) & 1;
515 r->stereo = (val >> 25) & 1;
516 r->enum_c = (val >> 26) & 0x0f;
517 }
518
519 /*
520 * mixer switches/volumes
521 */
522
523 #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
524 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
525 .info = snd_azf3328_info_mixer, \
526 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
527 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
528 }
529
530 #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
531 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
532 .info = snd_azf3328_info_mixer, \
533 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
534 .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
535 }
536
537 #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
538 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
539 .info = snd_azf3328_info_mixer, \
540 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
541 .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
542 }
543
544 #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
545 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
546 .info = snd_azf3328_info_mixer, \
547 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
548 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
549 }
550
551 #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
552 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
553 .info = snd_azf3328_info_mixer_enum, \
554 .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
555 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
556 }
557
558 static int
559 snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
560 struct snd_ctl_elem_info *uinfo)
561 {
562 struct azf3328_mixer_reg reg;
563
564 snd_azf3328_dbgcallenter();
565 snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
566 uinfo->type = reg.mask == 1 ?
567 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
568 uinfo->count = reg.stereo + 1;
569 uinfo->value.integer.min = 0;
570 uinfo->value.integer.max = reg.mask;
571 snd_azf3328_dbgcallleave();
572 return 0;
573 }
574
575 static int
576 snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
577 struct snd_ctl_elem_value *ucontrol)
578 {
579 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
580 struct azf3328_mixer_reg reg;
581 unsigned int oreg, val;
582
583 snd_azf3328_dbgcallenter();
584 snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
585
586 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
587 val = (oreg >> reg.lchan_shift) & reg.mask;
588 if (reg.invert)
589 val = reg.mask - val;
590 ucontrol->value.integer.value[0] = val;
591 if (reg.stereo) {
592 val = (oreg >> reg.rchan_shift) & reg.mask;
593 if (reg.invert)
594 val = reg.mask - val;
595 ucontrol->value.integer.value[1] = val;
596 }
597 snd_azf3328_dbgmixer("get: %02x is %04x -> vol %02lx|%02lx "
598 "(shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
599 reg.reg, oreg,
600 ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
601 reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
602 snd_azf3328_dbgcallleave();
603 return 0;
604 }
605
606 static int
607 snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
608 struct snd_ctl_elem_value *ucontrol)
609 {
610 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
611 struct azf3328_mixer_reg reg;
612 unsigned int oreg, nreg, val;
613
614 snd_azf3328_dbgcallenter();
615 snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
616 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
617 val = ucontrol->value.integer.value[0] & reg.mask;
618 if (reg.invert)
619 val = reg.mask - val;
620 nreg = oreg & ~(reg.mask << reg.lchan_shift);
621 nreg |= (val << reg.lchan_shift);
622 if (reg.stereo) {
623 val = ucontrol->value.integer.value[1] & reg.mask;
624 if (reg.invert)
625 val = reg.mask - val;
626 nreg &= ~(reg.mask << reg.rchan_shift);
627 nreg |= (val << reg.rchan_shift);
628 }
629 if (reg.mask >= 0x07) /* it's a volume control, so better take care */
630 snd_azf3328_mixer_write_volume_gradually(
631 chip, reg.reg, nreg >> 8, nreg & 0xff,
632 /* just set both channels, doesn't matter */
633 SET_CHAN_LEFT|SET_CHAN_RIGHT,
634 0);
635 else
636 snd_azf3328_mixer_outw(chip, reg.reg, nreg);
637
638 snd_azf3328_dbgmixer("put: %02x to %02lx|%02lx, "
639 "oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
640 reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
641 oreg, reg.lchan_shift, reg.rchan_shift,
642 nreg, snd_azf3328_mixer_inw(chip, reg.reg));
643 snd_azf3328_dbgcallleave();
644 return (nreg != oreg);
645 }
646
647 static int
648 snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
649 struct snd_ctl_elem_info *uinfo)
650 {
651 static const char * const texts1[] = {
652 "Mic1", "Mic2"
653 };
654 static const char * const texts2[] = {
655 "Mix", "Mic"
656 };
657 static const char * const texts3[] = {
658 "Mic", "CD", "Video", "Aux",
659 "Line", "Mix", "Mix Mono", "Phone"
660 };
661 static const char * const texts4[] = {
662 "pre 3D", "post 3D"
663 };
664 struct azf3328_mixer_reg reg;
665 const char *p = NULL;
666
667 snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
668 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
669 uinfo->count = (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1;
670 uinfo->value.enumerated.items = reg.enum_c;
671 if (uinfo->value.enumerated.item > reg.enum_c - 1U)
672 uinfo->value.enumerated.item = reg.enum_c - 1U;
673 if (reg.reg == IDX_MIXER_ADVCTL2) {
674 switch(reg.lchan_shift) {
675 case 8: /* modem out sel */
676 p = texts1[uinfo->value.enumerated.item];
677 break;
678 case 9: /* mono sel source */
679 p = texts2[uinfo->value.enumerated.item];
680 break;
681 case 15: /* PCM Out Path */
682 p = texts4[uinfo->value.enumerated.item];
683 break;
684 }
685 } else
686 if (reg.reg == IDX_MIXER_REC_SELECT)
687 p = texts3[uinfo->value.enumerated.item];
688
689 strcpy(uinfo->value.enumerated.name, p);
690 return 0;
691 }
692
693 static int
694 snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
695 struct snd_ctl_elem_value *ucontrol)
696 {
697 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
698 struct azf3328_mixer_reg reg;
699 unsigned short val;
700
701 snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
702 val = snd_azf3328_mixer_inw(chip, reg.reg);
703 if (reg.reg == IDX_MIXER_REC_SELECT) {
704 ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
705 ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
706 } else
707 ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
708
709 snd_azf3328_dbgmixer("get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
710 reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
711 reg.lchan_shift, reg.enum_c);
712 return 0;
713 }
714
715 static int
716 snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
717 struct snd_ctl_elem_value *ucontrol)
718 {
719 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
720 struct azf3328_mixer_reg reg;
721 unsigned int oreg, nreg, val;
722
723 snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
724 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
725 val = oreg;
726 if (reg.reg == IDX_MIXER_REC_SELECT) {
727 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
728 ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
729 return -EINVAL;
730 val = (ucontrol->value.enumerated.item[0] << 8) |
731 (ucontrol->value.enumerated.item[1] << 0);
732 } else {
733 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
734 return -EINVAL;
735 val &= ~((reg.enum_c - 1) << reg.lchan_shift);
736 val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
737 }
738 snd_azf3328_mixer_outw(chip, reg.reg, val);
739 nreg = val;
740
741 snd_azf3328_dbgmixer("put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
742 return (nreg != oreg);
743 }
744
745 static struct snd_kcontrol_new snd_azf3328_mixer_controls[] __devinitdata = {
746 AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
747 AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
748 AZF3328_MIXER_SWITCH("Wave Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
749 AZF3328_MIXER_VOL_STEREO("Wave Playback Volume", IDX_MIXER_WAVEOUT, 0x1f, 1),
750 AZF3328_MIXER_SWITCH("Wave 3D Bypass Playback Switch", IDX_MIXER_ADVCTL2, 7, 1),
751 AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
752 AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
753 AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
754 AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
755 AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
756 AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
757 AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
758 AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
759 AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
760 AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
761 AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
762 AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
763 AZF3328_MIXER_SWITCH("PC Speaker Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
764 AZF3328_MIXER_VOL_SPECIAL("PC Speaker Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
765 AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
766 AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
767 AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
768 AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
769 AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
770 AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
771 AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
772 AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
773 AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8),
774 AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9),
775 AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */
776 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
777 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
778 AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
779 AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */
780 AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */
781 #if MIXER_TESTING
782 AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
783 AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
784 AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
785 AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
786 AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
787 AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
788 AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
789 AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
790 AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
791 AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
792 AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
793 AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
794 AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
795 AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
796 AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
797 AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
798 #endif
799 };
800
801 static u16 __devinitdata snd_azf3328_init_values[][2] = {
802 { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f },
803 { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f },
804 { IDX_MIXER_BASSTREBLE, 0x0000 },
805 { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f },
806 { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f },
807 { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f },
808 { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f },
809 { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f },
810 { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f },
811 { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f },
812 { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f },
813 { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f },
814 { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 },
815 };
816
817 static int __devinit
818 snd_azf3328_mixer_new(struct snd_azf3328 *chip)
819 {
820 struct snd_card *card;
821 const struct snd_kcontrol_new *sw;
822 unsigned int idx;
823 int err;
824
825 snd_azf3328_dbgcallenter();
826 snd_assert(chip != NULL && chip->card != NULL, return -EINVAL);
827
828 card = chip->card;
829
830 /* mixer reset */
831 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
832
833 /* mute and zero volume channels */
834 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) {
835 snd_azf3328_mixer_outw(chip,
836 snd_azf3328_init_values[idx][0],
837 snd_azf3328_init_values[idx][1]);
838 }
839
840 /* add mixer controls */
841 sw = snd_azf3328_mixer_controls;
842 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls);
843 ++idx, ++sw) {
844 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
845 return err;
846 }
847 snd_component_add(card, "AZF3328 mixer");
848 strcpy(card->mixername, "AZF3328 mixer");
849
850 snd_azf3328_dbgcallleave();
851 return 0;
852 }
853
854 static int
855 snd_azf3328_hw_params(struct snd_pcm_substream *substream,
856 struct snd_pcm_hw_params *hw_params)
857 {
858 int res;
859 snd_azf3328_dbgcallenter();
860 res = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
861 snd_azf3328_dbgcallleave();
862 return res;
863 }
864
865 static int
866 snd_azf3328_hw_free(struct snd_pcm_substream *substream)
867 {
868 snd_azf3328_dbgcallenter();
869 snd_pcm_lib_free_pages(substream);
870 snd_azf3328_dbgcallleave();
871 return 0;
872 }
873
874 static void
875 snd_azf3328_codec_setfmt(struct snd_azf3328 *chip,
876 unsigned reg,
877 unsigned int bitrate,
878 unsigned int format_width,
879 unsigned int channels
880 )
881 {
882 u16 val = 0xff00;
883 unsigned long flags;
884
885 snd_azf3328_dbgcallenter();
886 switch (bitrate) {
887 case AZF_FREQ_4000: val |= SOUNDFORMAT_FREQ_SUSPECTED_4000; break;
888 case AZF_FREQ_4800: val |= SOUNDFORMAT_FREQ_SUSPECTED_4800; break;
889 case AZF_FREQ_5512:
890 /* the AZF3328 names it "5510" for some strange reason */
891 val |= SOUNDFORMAT_FREQ_5510; break;
892 case AZF_FREQ_6620: val |= SOUNDFORMAT_FREQ_6620; break;
893 case AZF_FREQ_8000: val |= SOUNDFORMAT_FREQ_8000; break;
894 case AZF_FREQ_9600: val |= SOUNDFORMAT_FREQ_9600; break;
895 case AZF_FREQ_11025: val |= SOUNDFORMAT_FREQ_11025; break;
896 case AZF_FREQ_13240: val |= SOUNDFORMAT_FREQ_SUSPECTED_13240; break;
897 case AZF_FREQ_16000: val |= SOUNDFORMAT_FREQ_16000; break;
898 case AZF_FREQ_22050: val |= SOUNDFORMAT_FREQ_22050; break;
899 case AZF_FREQ_32000: val |= SOUNDFORMAT_FREQ_32000; break;
900 default:
901 snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
902 /* fall-through */
903 case AZF_FREQ_44100: val |= SOUNDFORMAT_FREQ_44100; break;
904 case AZF_FREQ_48000: val |= SOUNDFORMAT_FREQ_48000; break;
905 case AZF_FREQ_66200: val |= SOUNDFORMAT_FREQ_SUSPECTED_66200; break;
906 }
907 /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */
908 /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */
909 /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */
910 /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */
911 /* val = 0xff05; 5m11.556s (... -> 44100Hz) */
912 /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */
913 /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */
914 /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */
915 /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */
916
917 if (channels == 2)
918 val |= SOUNDFORMAT_FLAG_2CHANNELS;
919
920 if (format_width == 16)
921 val |= SOUNDFORMAT_FLAG_16BIT;
922
923 spin_lock_irqsave(&chip->reg_lock, flags);
924
925 /* set bitrate/format */
926 snd_azf3328_codec_outw(chip, reg, val);
927
928 /* changing the bitrate/format settings switches off the
929 * audio output with an annoying click in case of 8/16bit format change
930 * (maybe shutting down DAC/ADC?), thus immediately
931 * do some tweaking to reenable it and get rid of the clicking
932 * (FIXME: yes, it works, but what exactly am I doing here?? :)
933 * FIXME: does this have some side effects for full-duplex
934 * or other dramatic side effects? */
935 if (reg == IDX_IO_PLAY_SOUNDFORMAT) /* only do it for playback */
936 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
937 snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) |
938 DMA_PLAY_SOMETHING1 |
939 DMA_PLAY_SOMETHING2 |
940 SOMETHING_ALMOST_ALWAYS_SET |
941 DMA_EPILOGUE_SOMETHING |
942 DMA_SOMETHING_ELSE
943 );
944
945 spin_unlock_irqrestore(&chip->reg_lock, flags);
946 snd_azf3328_dbgcallleave();
947 }
948
949 static inline void
950 snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328 *chip,
951 unsigned reg
952 )
953 {
954 /* choose lowest frequency for low power consumption.
955 * While this will cause louder noise due to rather coarse frequency,
956 * it should never matter since output should always
957 * get disabled properly when idle anyway. */
958 snd_azf3328_codec_setfmt(chip, reg, AZF_FREQ_4000, 8, 1);
959 }
960
961 static inline void
962 snd_azf3328_codec_enable(struct snd_azf3328 *chip, int enable)
963 {
964 /* no idea what exactly is being done here, but I strongly assume it's
965 * PM related */
966 snd_azf3328_io_reg_setw(
967 chip->codec_io+IDX_IO_6AH,
968 IO_6A_PAUSE_PLAYBACK_BIT8,
969 !enable
970 );
971 }
972
973 static void
974 snd_azf3328_codec_activity(struct snd_azf3328 *chip,
975 enum snd_azf3328_stream_index stream_type,
976 int enable
977 )
978 {
979 int need_change = (chip->audio_stream[stream_type].running != enable);
980
981 snd_azf3328_dbgplay(
982 "codec_activity: type %d, enable %d, need_change %d\n",
983 stream_type, enable, need_change
984 );
985 if (need_change) {
986 enum snd_azf3328_stream_index other =
987 (stream_type == AZF_PLAYBACK) ?
988 AZF_CAPTURE : AZF_PLAYBACK;
989 /* small check to prevent shutting down the other party
990 * in case it's active */
991 if ((enable) || !(chip->audio_stream[other].running))
992 snd_azf3328_codec_enable(chip, enable);
993
994 /* ...and adjust clock, too
995 * (reduce noise and power consumption) */
996 if (!enable)
997 snd_azf3328_codec_setfmt_lowpower(
998 chip,
999 chip->audio_stream[stream_type].portbase
1000 + IDX_IO_PLAY_SOUNDFORMAT
1001 );
1002 }
1003 chip->audio_stream[stream_type].running = enable;
1004 }
1005
1006 static void
1007 snd_azf3328_setdmaa(struct snd_azf3328 *chip,
1008 long unsigned int addr,
1009 unsigned int count,
1010 unsigned int size,
1011 enum snd_azf3328_stream_index stream_type
1012 )
1013 {
1014 snd_azf3328_dbgcallenter();
1015 if (!chip->audio_stream[stream_type].running) {
1016 /* AZF3328 uses a two buffer pointer DMA playback approach */
1017
1018 unsigned long flags, portbase, addr_area2;
1019
1020 /* width 32bit (prevent overflow): */
1021 unsigned long count_areas, count_tmp;
1022
1023 portbase = chip->audio_stream[stream_type].portbase;
1024 count_areas = size/2;
1025 addr_area2 = addr+count_areas;
1026 count_areas--; /* max. index */
1027 snd_azf3328_dbgplay("set DMA: buf1 %08lx[%lu], buf2 %08lx[%lu]\n", addr, count_areas, addr_area2, count_areas);
1028
1029 /* build combined I/O buffer length word */
1030 count_tmp = count_areas;
1031 count_areas |= (count_tmp << 16);
1032 spin_lock_irqsave(&chip->reg_lock, flags);
1033 outl(addr, portbase + IDX_IO_PLAY_DMA_START_1);
1034 outl(addr_area2, portbase + IDX_IO_PLAY_DMA_START_2);
1035 outl(count_areas, portbase + IDX_IO_PLAY_DMA_LEN_1);
1036 spin_unlock_irqrestore(&chip->reg_lock, flags);
1037 }
1038 snd_azf3328_dbgcallleave();
1039 }
1040
1041 static int
1042 snd_azf3328_playback_prepare(struct snd_pcm_substream *substream)
1043 {
1044 #if 0
1045 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1046 struct snd_pcm_runtime *runtime = substream->runtime;
1047 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1048 unsigned int count = snd_pcm_lib_period_bytes(substream);
1049 #endif
1050
1051 snd_azf3328_dbgcallenter();
1052 #if 0
1053 snd_azf3328_codec_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
1054 runtime->rate,
1055 snd_pcm_format_width(runtime->format),
1056 runtime->channels);
1057 snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, AZF_PLAYBACK);
1058 #endif
1059 snd_azf3328_dbgcallleave();
1060 return 0;
1061 }
1062
1063 static int
1064 snd_azf3328_capture_prepare(struct snd_pcm_substream *substream)
1065 {
1066 #if 0
1067 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1068 struct snd_pcm_runtime *runtime = substream->runtime;
1069 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1070 unsigned int count = snd_pcm_lib_period_bytes(substream);
1071 #endif
1072
1073 snd_azf3328_dbgcallenter();
1074 #if 0
1075 snd_azf3328_codec_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
1076 runtime->rate,
1077 snd_pcm_format_width(runtime->format),
1078 runtime->channels);
1079 snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, AZF_CAPTURE);
1080 #endif
1081 snd_azf3328_dbgcallleave();
1082 return 0;
1083 }
1084
1085 static int
1086 snd_azf3328_playback_trigger(struct snd_pcm_substream *substream, int cmd)
1087 {
1088 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1089 struct snd_pcm_runtime *runtime = substream->runtime;
1090 int result = 0;
1091 unsigned int status1;
1092 int previously_muted;
1093
1094 snd_azf3328_dbgcalls("snd_azf3328_playback_trigger cmd %d\n", cmd);
1095
1096 switch (cmd) {
1097 case SNDRV_PCM_TRIGGER_START:
1098 snd_azf3328_dbgplay("START PLAYBACK\n");
1099
1100 /* mute WaveOut (avoid clicking during setup) */
1101 previously_muted =
1102 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
1103
1104 snd_azf3328_codec_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
1105 runtime->rate,
1106 snd_pcm_format_width(runtime->format),
1107 runtime->channels);
1108
1109 spin_lock(&chip->reg_lock);
1110 /* first, remember current value: */
1111 status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
1112
1113 /* stop playback */
1114 status1 &= ~DMA_RESUME;
1115 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
1116
1117 /* FIXME: clear interrupts or what??? */
1118 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_IRQTYPE, 0xffff);
1119 spin_unlock(&chip->reg_lock);
1120
1121 snd_azf3328_setdmaa(chip, runtime->dma_addr,
1122 snd_pcm_lib_period_bytes(substream),
1123 snd_pcm_lib_buffer_bytes(substream),
1124 AZF_PLAYBACK);
1125
1126 spin_lock(&chip->reg_lock);
1127 #ifdef WIN9X
1128 /* FIXME: enable playback/recording??? */
1129 status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
1130 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
1131
1132 /* start playback again */
1133 /* FIXME: what is this value (0x0010)??? */
1134 status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
1135 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
1136 #else /* NT4 */
1137 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
1138 0x0000);
1139 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
1140 DMA_PLAY_SOMETHING1);
1141 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
1142 DMA_PLAY_SOMETHING1 |
1143 DMA_PLAY_SOMETHING2);
1144 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
1145 DMA_RESUME |
1146 SOMETHING_ALMOST_ALWAYS_SET |
1147 DMA_EPILOGUE_SOMETHING |
1148 DMA_SOMETHING_ELSE);
1149 #endif
1150 spin_unlock(&chip->reg_lock);
1151 snd_azf3328_codec_activity(chip, AZF_PLAYBACK, 1);
1152
1153 /* now unmute WaveOut */
1154 if (!previously_muted)
1155 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
1156
1157 snd_azf3328_dbgplay("STARTED PLAYBACK\n");
1158 break;
1159 case SNDRV_PCM_TRIGGER_RESUME:
1160 snd_azf3328_dbgplay("RESUME PLAYBACK\n");
1161 /* resume playback if we were active */
1162 spin_lock(&chip->reg_lock);
1163 if (chip->audio_stream[AZF_PLAYBACK].running)
1164 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
1165 snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) | DMA_RESUME);
1166 spin_unlock(&chip->reg_lock);
1167 break;
1168 case SNDRV_PCM_TRIGGER_STOP:
1169 snd_azf3328_dbgplay("STOP PLAYBACK\n");
1170
1171 /* mute WaveOut (avoid clicking during setup) */
1172 previously_muted =
1173 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
1174
1175 spin_lock(&chip->reg_lock);
1176 /* first, remember current value: */
1177 status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
1178
1179 /* stop playback */
1180 status1 &= ~DMA_RESUME;
1181 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
1182
1183 /* hmm, is this really required? we're resetting the same bit
1184 * immediately thereafter... */
1185 status1 |= DMA_PLAY_SOMETHING1;
1186 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
1187
1188 status1 &= ~DMA_PLAY_SOMETHING1;
1189 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
1190 spin_unlock(&chip->reg_lock);
1191 snd_azf3328_codec_activity(chip, AZF_PLAYBACK, 0);
1192
1193 /* now unmute WaveOut */
1194 if (!previously_muted)
1195 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
1196
1197 snd_azf3328_dbgplay("STOPPED PLAYBACK\n");
1198 break;
1199 case SNDRV_PCM_TRIGGER_SUSPEND:
1200 snd_azf3328_dbgplay("SUSPEND PLAYBACK\n");
1201 /* make sure playback is stopped */
1202 snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
1203 snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) & ~DMA_RESUME);
1204 break;
1205 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1206 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
1207 break;
1208 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1209 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
1210 break;
1211 default:
1212 printk(KERN_ERR "FIXME: unknown trigger mode!\n");
1213 return -EINVAL;
1214 }
1215
1216 snd_azf3328_dbgcallleave();
1217 return result;
1218 }
1219
1220 /* this is just analogous to playback; I'm not quite sure whether recording
1221 * should actually be triggered like that */
1222 static int
1223 snd_azf3328_capture_trigger(struct snd_pcm_substream *substream, int cmd)
1224 {
1225 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1226 struct snd_pcm_runtime *runtime = substream->runtime;
1227 int result = 0;
1228 unsigned int status1;
1229
1230 snd_azf3328_dbgcalls("snd_azf3328_capture_trigger cmd %d\n", cmd);
1231
1232 switch (cmd) {
1233 case SNDRV_PCM_TRIGGER_START:
1234
1235 snd_azf3328_dbgplay("START CAPTURE\n");
1236
1237 snd_azf3328_codec_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
1238 runtime->rate,
1239 snd_pcm_format_width(runtime->format),
1240 runtime->channels);
1241
1242 spin_lock(&chip->reg_lock);
1243 /* first, remember current value: */
1244 status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
1245
1246 /* stop recording */
1247 status1 &= ~DMA_RESUME;
1248 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
1249
1250 /* FIXME: clear interrupts or what??? */
1251 snd_azf3328_codec_outw(chip, IDX_IO_REC_IRQTYPE, 0xffff);
1252 spin_unlock(&chip->reg_lock);
1253
1254 snd_azf3328_setdmaa(chip, runtime->dma_addr,
1255 snd_pcm_lib_period_bytes(substream),
1256 snd_pcm_lib_buffer_bytes(substream),
1257 AZF_CAPTURE);
1258
1259 spin_lock(&chip->reg_lock);
1260 #ifdef WIN9X
1261 /* FIXME: enable playback/recording??? */
1262 status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
1263 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
1264
1265 /* start capture again */
1266 /* FIXME: what is this value (0x0010)??? */
1267 status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
1268 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
1269 #else
1270 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
1271 0x0000);
1272 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
1273 DMA_PLAY_SOMETHING1);
1274 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
1275 DMA_PLAY_SOMETHING1 |
1276 DMA_PLAY_SOMETHING2);
1277 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
1278 DMA_RESUME |
1279 SOMETHING_ALMOST_ALWAYS_SET |
1280 DMA_EPILOGUE_SOMETHING |
1281 DMA_SOMETHING_ELSE);
1282 #endif
1283 spin_unlock(&chip->reg_lock);
1284 snd_azf3328_codec_activity(chip, AZF_CAPTURE, 1);
1285
1286 snd_azf3328_dbgplay("STARTED CAPTURE\n");
1287 break;
1288 case SNDRV_PCM_TRIGGER_RESUME:
1289 snd_azf3328_dbgplay("RESUME CAPTURE\n");
1290 /* resume recording if we were active */
1291 spin_lock(&chip->reg_lock);
1292 if (chip->audio_stream[AZF_CAPTURE].running)
1293 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
1294 snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) | DMA_RESUME);
1295 spin_unlock(&chip->reg_lock);
1296 break;
1297 case SNDRV_PCM_TRIGGER_STOP:
1298 snd_azf3328_dbgplay("STOP CAPTURE\n");
1299
1300 spin_lock(&chip->reg_lock);
1301 /* first, remember current value: */
1302 status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
1303
1304 /* stop recording */
1305 status1 &= ~DMA_RESUME;
1306 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
1307
1308 status1 |= DMA_PLAY_SOMETHING1;
1309 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
1310
1311 status1 &= ~DMA_PLAY_SOMETHING1;
1312 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
1313 spin_unlock(&chip->reg_lock);
1314 snd_azf3328_codec_activity(chip, AZF_CAPTURE, 0);
1315
1316 snd_azf3328_dbgplay("STOPPED CAPTURE\n");
1317 break;
1318 case SNDRV_PCM_TRIGGER_SUSPEND:
1319 snd_azf3328_dbgplay("SUSPEND CAPTURE\n");
1320 /* make sure recording is stopped */
1321 snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
1322 snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) & ~DMA_RESUME);
1323 break;
1324 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1325 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
1326 break;
1327 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1328 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
1329 break;
1330 default:
1331 printk(KERN_ERR "FIXME: unknown trigger mode!\n");
1332 return -EINVAL;
1333 }
1334
1335 snd_azf3328_dbgcallleave();
1336 return result;
1337 }
1338
1339 static snd_pcm_uframes_t
1340 snd_azf3328_playback_pointer(struct snd_pcm_substream *substream)
1341 {
1342 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1343 unsigned long bufptr, result;
1344 snd_pcm_uframes_t frmres;
1345
1346 #ifdef QUERY_HARDWARE
1347 bufptr = snd_azf3328_codec_inl(chip, IDX_IO_PLAY_DMA_START_1);
1348 #else
1349 bufptr = substream->runtime->dma_addr;
1350 #endif
1351 result = snd_azf3328_codec_inl(chip, IDX_IO_PLAY_DMA_CURRPOS);
1352
1353 /* calculate offset */
1354 result -= bufptr;
1355 frmres = bytes_to_frames( substream->runtime, result);
1356 snd_azf3328_dbgplay("PLAY @ 0x%8lx, frames %8ld\n", result, frmres);
1357 return frmres;
1358 }
1359
1360 static snd_pcm_uframes_t
1361 snd_azf3328_capture_pointer(struct snd_pcm_substream *substream)
1362 {
1363 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1364 unsigned long bufptr, result;
1365 snd_pcm_uframes_t frmres;
1366
1367 #ifdef QUERY_HARDWARE
1368 bufptr = snd_azf3328_codec_inl(chip, IDX_IO_REC_DMA_START_1);
1369 #else
1370 bufptr = substream->runtime->dma_addr;
1371 #endif
1372 result = snd_azf3328_codec_inl(chip, IDX_IO_REC_DMA_CURRPOS);
1373
1374 /* calculate offset */
1375 result -= bufptr;
1376 frmres = bytes_to_frames( substream->runtime, result);
1377 snd_azf3328_dbgplay("REC @ 0x%8lx, frames %8ld\n", result, frmres);
1378 return frmres;
1379 }
1380
1381 /******************************************************************/
1382
1383 #ifdef SUPPORT_GAMEPORT
1384 static inline void
1385 snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip, int enable)
1386 {
1387 snd_azf3328_io_reg_setb(
1388 chip->game_io+IDX_GAME_HWCONFIG,
1389 GAME_HWCFG_IRQ_ENABLE,
1390 enable
1391 );
1392 }
1393
1394 static inline void
1395 snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip, int enable)
1396 {
1397 snd_azf3328_io_reg_setb(
1398 chip->game_io+IDX_GAME_HWCONFIG,
1399 GAME_HWCFG_LEGACY_ADDRESS_ENABLE,
1400 enable
1401 );
1402 }
1403
1404 static inline void
1405 snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, int enable)
1406 {
1407 snd_azf3328_io_reg_setw(
1408 chip->codec_io+IDX_IO_6AH,
1409 IO_6A_SOMETHING2_GAMEPORT,
1410 !enable
1411 );
1412 }
1413
1414 static inline void
1415 snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1416 {
1417 /*
1418 * skeleton handler only
1419 * (we do not want axis reading in interrupt handler - too much load!)
1420 */
1421 snd_azf3328_dbggame("gameport irq\n");
1422
1423 /* this should ACK the gameport IRQ properly, hopefully. */
1424 snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE);
1425 }
1426
1427 static int
1428 snd_azf3328_gameport_open(struct gameport *gameport, int mode)
1429 {
1430 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1431 int res;
1432
1433 snd_azf3328_dbggame("gameport_open, mode %d\n", mode);
1434 switch (mode) {
1435 case GAMEPORT_MODE_COOKED:
1436 case GAMEPORT_MODE_RAW:
1437 res = 0;
1438 break;
1439 default:
1440 res = -1;
1441 break;
1442 }
1443
1444 snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0));
1445
1446 return res;
1447 }
1448
1449 static void
1450 snd_azf3328_gameport_close(struct gameport *gameport)
1451 {
1452 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1453
1454 snd_azf3328_dbggame("gameport_close\n");
1455 snd_azf3328_gameport_axis_circuit_enable(chip, 0);
1456 }
1457
1458 static int
1459 snd_azf3328_gameport_cooked_read(struct gameport *gameport,
1460 int *axes,
1461 int *buttons
1462 )
1463 {
1464 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1465 int i;
1466 u8 val;
1467 unsigned long flags;
1468
1469 snd_assert(chip, return 0);
1470
1471 spin_lock_irqsave(&chip->reg_lock, flags);
1472 val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE);
1473 *buttons = (~(val) >> 4) & 0xf;
1474
1475 /* ok, this one is a bit dirty: cooked_read is being polled by a timer,
1476 * thus we're atomic and cannot actively wait in here
1477 * (which would be useful for us since it probably would be better
1478 * to trigger a measurement in here, then wait a short amount of
1479 * time until it's finished, then read values of _this_ measurement).
1480 *
1481 * Thus we simply resort to reading values if they're available already
1482 * and trigger the next measurement.
1483 */
1484
1485 val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG);
1486 if (val & GAME_AXES_SAMPLING_READY) {
1487 for (i = 0; i < 4; ++i) {
1488 /* configure the axis to read */
1489 val = (i << 4) | 0x0f;
1490 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
1491
1492 chip->axes[i] = snd_azf3328_game_inw(
1493 chip, IDX_GAME_AXIS_VALUE
1494 );
1495 }
1496 }
1497
1498 /* trigger next axes sampling, to be evaluated the next time we
1499 * enter this function */
1500
1501 /* for some very, very strange reason we cannot enable
1502 * Measurement Ready monitoring for all axes here,
1503 * at least not when only one joystick connected */
1504 val = 0x03; /* we're able to monitor axes 1 and 2 only */
1505 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
1506
1507 snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff);
1508 spin_unlock_irqrestore(&chip->reg_lock, flags);
1509
1510 for (i = 0; i < 4; i++) {
1511 axes[i] = chip->axes[i];
1512 if (axes[i] == 0xffff)
1513 axes[i] = -1;
1514 }
1515
1516 snd_azf3328_dbggame("cooked_read: axes %d %d %d %d buttons %d\n",
1517 axes[0], axes[1], axes[2], axes[3], *buttons
1518 );
1519
1520 return 0;
1521 }
1522
1523 static int __devinit
1524 snd_azf3328_gameport(struct snd_azf3328 *chip, int dev)
1525 {
1526 struct gameport *gp;
1527
1528 int io_port = chip->game_io;
1529
1530 chip->gameport = gp = gameport_allocate_port();
1531 if (!gp) {
1532 printk(KERN_ERR "azt3328: cannot alloc memory for gameport\n");
1533 return -ENOMEM;
1534 }
1535
1536 gameport_set_name(gp, "AZF3328 Gameport");
1537 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1538 gameport_set_dev_parent(gp, &chip->pci->dev);
1539 gp->io = io_port;
1540 gameport_set_port_data(gp, chip);
1541
1542 gp->open = snd_azf3328_gameport_open;
1543 gp->close = snd_azf3328_gameport_close;
1544 gp->fuzz = 16; /* seems ok */
1545 gp->cooked_read = snd_azf3328_gameport_cooked_read;
1546
1547 /* DISABLE legacy address: we don't need it! */
1548 snd_azf3328_gameport_legacy_address_enable(chip, 0);
1549
1550 snd_azf3328_gameport_axis_circuit_enable(chip, 0);
1551
1552 gameport_register_port(chip->gameport);
1553
1554 return 0;
1555 }
1556
1557 static void
1558 snd_azf3328_gameport_free(struct snd_azf3328 *chip)
1559 {
1560 if (chip->gameport) {
1561 gameport_unregister_port(chip->gameport);
1562 chip->gameport = NULL;
1563 }
1564 snd_azf3328_gameport_irq_enable(chip, 0);
1565 }
1566 #else
1567 static inline int
1568 snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
1569 static inline void
1570 snd_azf3328_gameport_free(struct snd_azf3328 *chip) { }
1571 static inline void
1572 snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1573 {
1574 printk(KERN_WARNING "huh, game port IRQ occurred!?\n");
1575 }
1576 #endif /* SUPPORT_GAMEPORT */
1577
1578 /******************************************************************/
1579
1580 static irqreturn_t
1581 snd_azf3328_interrupt(int irq, void *dev_id)
1582 {
1583 struct snd_azf3328 *chip = dev_id;
1584 u8 status, which;
1585 #if DEBUG_PLAY_REC
1586 static unsigned long irq_count;
1587 #endif
1588
1589 status = snd_azf3328_codec_inb(chip, IDX_IO_IRQSTATUS);
1590
1591 /* fast path out, to ease interrupt sharing */
1592 if (!(status &
1593 (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER)
1594 ))
1595 return IRQ_NONE; /* must be interrupt for another device */
1596
1597 snd_azf3328_dbgplay("Interrupt %ld!\nIDX_IO_PLAY_FLAGS %04x, IDX_IO_PLAY_IRQTYPE %04x, IDX_IO_IRQSTATUS %04x\n",
1598 irq_count++ /* debug-only */,
1599 snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS),
1600 snd_azf3328_codec_inw(chip, IDX_IO_PLAY_IRQTYPE),
1601 status);
1602
1603 if (status & IRQ_TIMER) {
1604 /* snd_azf3328_dbgplay("timer %ld\n",
1605 snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE)
1606 & TIMER_VALUE_MASK
1607 ); */
1608 if (chip->timer)
1609 snd_timer_interrupt(chip->timer, chip->timer->sticks);
1610 /* ACK timer */
1611 spin_lock(&chip->reg_lock);
1612 snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
1613 spin_unlock(&chip->reg_lock);
1614 snd_azf3328_dbgplay("azt3328: timer IRQ\n");
1615 }
1616 if (status & IRQ_PLAYBACK) {
1617 spin_lock(&chip->reg_lock);
1618 which = snd_azf3328_codec_inb(chip, IDX_IO_PLAY_IRQTYPE);
1619 /* ack all IRQ types immediately */
1620 snd_azf3328_codec_outb(chip, IDX_IO_PLAY_IRQTYPE, which);
1621 spin_unlock(&chip->reg_lock);
1622
1623 if (chip->pcm && chip->audio_stream[AZF_PLAYBACK].substream) {
1624 snd_pcm_period_elapsed(
1625 chip->audio_stream[AZF_PLAYBACK].substream
1626 );
1627 snd_azf3328_dbgplay("PLAY period done (#%x), @ %x\n",
1628 which,
1629 snd_azf3328_codec_inl(
1630 chip, IDX_IO_PLAY_DMA_CURRPOS
1631 )
1632 );
1633 } else
1634 snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
1635 if (which & IRQ_PLAY_SOMETHING)
1636 snd_azf3328_dbgplay("azt3328: unknown play IRQ type occurred, please report!\n");
1637 }
1638 if (status & IRQ_RECORDING) {
1639 spin_lock(&chip->reg_lock);
1640 which = snd_azf3328_codec_inb(chip, IDX_IO_REC_IRQTYPE);
1641 /* ack all IRQ types immediately */
1642 snd_azf3328_codec_outb(chip, IDX_IO_REC_IRQTYPE, which);
1643 spin_unlock(&chip->reg_lock);
1644
1645 if (chip->pcm && chip->audio_stream[AZF_CAPTURE].substream) {
1646 snd_pcm_period_elapsed(
1647 chip->audio_stream[AZF_CAPTURE].substream
1648 );
1649 snd_azf3328_dbgplay("REC period done (#%x), @ %x\n",
1650 which,
1651 snd_azf3328_codec_inl(
1652 chip, IDX_IO_REC_DMA_CURRPOS
1653 )
1654 );
1655 } else
1656 snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
1657 if (which & IRQ_REC_SOMETHING)
1658 snd_azf3328_dbgplay("azt3328: unknown rec IRQ type occurred, please report!\n");
1659 }
1660 if (status & IRQ_GAMEPORT)
1661 snd_azf3328_gameport_interrupt(chip);
1662 /* MPU401 has less critical IRQ requirements
1663 * than timer and playback/recording, right? */
1664 if (status & IRQ_MPU401) {
1665 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1666
1667 /* hmm, do we have to ack the IRQ here somehow?
1668 * If so, then I don't know how... */
1669 snd_azf3328_dbgplay("azt3328: MPU401 IRQ\n");
1670 }
1671 return IRQ_HANDLED;
1672 }
1673
1674 /*****************************************************************/
1675
1676 static const struct snd_pcm_hardware snd_azf3328_playback =
1677 {
1678 /* FIXME!! Correct? */
1679 .info = SNDRV_PCM_INFO_MMAP |
1680 SNDRV_PCM_INFO_INTERLEAVED |
1681 SNDRV_PCM_INFO_MMAP_VALID,
1682 .formats = SNDRV_PCM_FMTBIT_S8 |
1683 SNDRV_PCM_FMTBIT_U8 |
1684 SNDRV_PCM_FMTBIT_S16_LE |
1685 SNDRV_PCM_FMTBIT_U16_LE,
1686 .rates = SNDRV_PCM_RATE_5512 |
1687 SNDRV_PCM_RATE_8000_48000 |
1688 SNDRV_PCM_RATE_KNOT,
1689 .rate_min = AZF_FREQ_4000,
1690 .rate_max = AZF_FREQ_66200,
1691 .channels_min = 1,
1692 .channels_max = 2,
1693 .buffer_bytes_max = 65536,
1694 .period_bytes_min = 64,
1695 .period_bytes_max = 65536,
1696 .periods_min = 1,
1697 .periods_max = 1024,
1698 /* FIXME: maybe that card actually has a FIFO?
1699 * Hmm, it seems newer revisions do have one, but we still don't know
1700 * its size... */
1701 .fifo_size = 0,
1702 };
1703
1704 static const struct snd_pcm_hardware snd_azf3328_capture =
1705 {
1706 /* FIXME */
1707 .info = SNDRV_PCM_INFO_MMAP |
1708 SNDRV_PCM_INFO_INTERLEAVED |
1709 SNDRV_PCM_INFO_MMAP_VALID,
1710 .formats = SNDRV_PCM_FMTBIT_S8 |
1711 SNDRV_PCM_FMTBIT_U8 |
1712 SNDRV_PCM_FMTBIT_S16_LE |
1713 SNDRV_PCM_FMTBIT_U16_LE,
1714 .rates = SNDRV_PCM_RATE_5512 |
1715 SNDRV_PCM_RATE_8000_48000 |
1716 SNDRV_PCM_RATE_KNOT,
1717 .rate_min = AZF_FREQ_4000,
1718 .rate_max = AZF_FREQ_66200,
1719 .channels_min = 1,
1720 .channels_max = 2,
1721 .buffer_bytes_max = 65536,
1722 .period_bytes_min = 64,
1723 .period_bytes_max = 65536,
1724 .periods_min = 1,
1725 .periods_max = 1024,
1726 .fifo_size = 0,
1727 };
1728
1729
1730 static unsigned int snd_azf3328_fixed_rates[] = {
1731 AZF_FREQ_4000,
1732 AZF_FREQ_4800,
1733 AZF_FREQ_5512,
1734 AZF_FREQ_6620,
1735 AZF_FREQ_8000,
1736 AZF_FREQ_9600,
1737 AZF_FREQ_11025,
1738 AZF_FREQ_13240,
1739 AZF_FREQ_16000,
1740 AZF_FREQ_22050,
1741 AZF_FREQ_32000,
1742 AZF_FREQ_44100,
1743 AZF_FREQ_48000,
1744 AZF_FREQ_66200
1745 };
1746
1747 static struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
1748 .count = ARRAY_SIZE(snd_azf3328_fixed_rates),
1749 .list = snd_azf3328_fixed_rates,
1750 .mask = 0,
1751 };
1752
1753 /*****************************************************************/
1754
1755 static int
1756 snd_azf3328_playback_open(struct snd_pcm_substream *substream)
1757 {
1758 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1759 struct snd_pcm_runtime *runtime = substream->runtime;
1760
1761 snd_azf3328_dbgcallenter();
1762 chip->audio_stream[AZF_PLAYBACK].substream = substream;
1763 runtime->hw = snd_azf3328_playback;
1764 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1765 &snd_azf3328_hw_constraints_rates);
1766 snd_azf3328_dbgcallleave();
1767 return 0;
1768 }
1769
1770 static int
1771 snd_azf3328_capture_open(struct snd_pcm_substream *substream)
1772 {
1773 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1774 struct snd_pcm_runtime *runtime = substream->runtime;
1775
1776 snd_azf3328_dbgcallenter();
1777 chip->audio_stream[AZF_CAPTURE].substream = substream;
1778 runtime->hw = snd_azf3328_capture;
1779 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1780 &snd_azf3328_hw_constraints_rates);
1781 snd_azf3328_dbgcallleave();
1782 return 0;
1783 }
1784
1785 static int
1786 snd_azf3328_playback_close(struct snd_pcm_substream *substream)
1787 {
1788 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1789
1790 snd_azf3328_dbgcallenter();
1791 chip->audio_stream[AZF_PLAYBACK].substream = NULL;
1792 snd_azf3328_dbgcallleave();
1793 return 0;
1794 }
1795
1796 static int
1797 snd_azf3328_capture_close(struct snd_pcm_substream *substream)
1798 {
1799 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1800
1801 snd_azf3328_dbgcallenter();
1802 chip->audio_stream[AZF_CAPTURE].substream = NULL;
1803 snd_azf3328_dbgcallleave();
1804 return 0;
1805 }
1806
1807 /******************************************************************/
1808
1809 static struct snd_pcm_ops snd_azf3328_playback_ops = {
1810 .open = snd_azf3328_playback_open,
1811 .close = snd_azf3328_playback_close,
1812 .ioctl = snd_pcm_lib_ioctl,
1813 .hw_params = snd_azf3328_hw_params,
1814 .hw_free = snd_azf3328_hw_free,
1815 .prepare = snd_azf3328_playback_prepare,
1816 .trigger = snd_azf3328_playback_trigger,
1817 .pointer = snd_azf3328_playback_pointer
1818 };
1819
1820 static struct snd_pcm_ops snd_azf3328_capture_ops = {
1821 .open = snd_azf3328_capture_open,
1822 .close = snd_azf3328_capture_close,
1823 .ioctl = snd_pcm_lib_ioctl,
1824 .hw_params = snd_azf3328_hw_params,
1825 .hw_free = snd_azf3328_hw_free,
1826 .prepare = snd_azf3328_capture_prepare,
1827 .trigger = snd_azf3328_capture_trigger,
1828 .pointer = snd_azf3328_capture_pointer
1829 };
1830
1831 static int __devinit
1832 snd_azf3328_pcm(struct snd_azf3328 *chip, int device)
1833 {
1834 struct snd_pcm *pcm;
1835 int err;
1836
1837 snd_azf3328_dbgcallenter();
1838 if ((err = snd_pcm_new(chip->card, "AZF3328 DSP", device, 1, 1, &pcm)) < 0)
1839 return err;
1840 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_azf3328_playback_ops);
1841 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_azf3328_capture_ops);
1842
1843 pcm->private_data = chip;
1844 pcm->info_flags = 0;
1845 strcpy(pcm->name, chip->card->shortname);
1846 chip->pcm = pcm;
1847
1848 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1849 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1850
1851 snd_azf3328_dbgcallleave();
1852 return 0;
1853 }
1854
1855 /******************************************************************/
1856
1857 /*** NOTE: the physical timer resolution actually is 1024000 ticks per second
1858 *** (probably derived from main crystal via a divider of 24),
1859 *** but announcing those attributes to user-space would make programs
1860 *** configure the timer to a 1 tick value, resulting in an absolutely fatal
1861 *** timer IRQ storm.
1862 *** Thus I chose to announce a down-scaled virtual timer to the outside and
1863 *** calculate real timer countdown values internally.
1864 *** (the scale factor can be set via module parameter "seqtimer_scaling").
1865 ***/
1866
1867 static int
1868 snd_azf3328_timer_start(struct snd_timer *timer)
1869 {
1870 struct snd_azf3328 *chip;
1871 unsigned long flags;
1872 unsigned int delay;
1873
1874 snd_azf3328_dbgcallenter();
1875 chip = snd_timer_chip(timer);
1876 delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
1877 if (delay < 49) {
1878 /* uhoh, that's not good, since user-space won't know about
1879 * this timing tweak
1880 * (we need to do it to avoid a lockup, though) */
1881
1882 snd_azf3328_dbgtimer("delay was too low (%d)!\n", delay);
1883 delay = 49; /* minimum time is 49 ticks */
1884 }
1885 snd_azf3328_dbgtimer("setting timer countdown value %d, add COUNTDOWN|IRQ\n", delay);
1886 delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE;
1887 spin_lock_irqsave(&chip->reg_lock, flags);
1888 snd_azf3328_codec_outl(chip, IDX_IO_TIMER_VALUE, delay);
1889 spin_unlock_irqrestore(&chip->reg_lock, flags);
1890 snd_azf3328_dbgcallleave();
1891 return 0;
1892 }
1893
1894 static int
1895 snd_azf3328_timer_stop(struct snd_timer *timer)
1896 {
1897 struct snd_azf3328 *chip;
1898 unsigned long flags;
1899
1900 snd_azf3328_dbgcallenter();
1901 chip = snd_timer_chip(timer);
1902 spin_lock_irqsave(&chip->reg_lock, flags);
1903 /* disable timer countdown and interrupt */
1904 /* FIXME: should we write TIMER_IRQ_ACK here? */
1905 snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0);
1906 spin_unlock_irqrestore(&chip->reg_lock, flags);
1907 snd_azf3328_dbgcallleave();
1908 return 0;
1909 }
1910
1911
1912 static int
1913 snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
1914 unsigned long *num, unsigned long *den)
1915 {
1916 snd_azf3328_dbgcallenter();
1917 *num = 1;
1918 *den = 1024000 / seqtimer_scaling;
1919 snd_azf3328_dbgcallleave();
1920 return 0;
1921 }
1922
1923 static struct snd_timer_hardware snd_azf3328_timer_hw = {
1924 .flags = SNDRV_TIMER_HW_AUTO,
1925 .resolution = 977, /* 1000000/1024000 = 0.9765625us */
1926 .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */
1927 .start = snd_azf3328_timer_start,
1928 .stop = snd_azf3328_timer_stop,
1929 .precise_resolution = snd_azf3328_timer_precise_resolution,
1930 };
1931
1932 static int __devinit
1933 snd_azf3328_timer(struct snd_azf3328 *chip, int device)
1934 {
1935 struct snd_timer *timer = NULL;
1936 struct snd_timer_id tid;
1937 int err;
1938
1939 snd_azf3328_dbgcallenter();
1940 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1941 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1942 tid.card = chip->card->number;
1943 tid.device = device;
1944 tid.subdevice = 0;
1945
1946 snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
1947 snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
1948
1949 err = snd_timer_new(chip->card, "AZF3328", &tid, &timer);
1950 if (err < 0)
1951 goto out;
1952
1953 strcpy(timer->name, "AZF3328 timer");
1954 timer->private_data = chip;
1955 timer->hw = snd_azf3328_timer_hw;
1956
1957 chip->timer = timer;
1958
1959 snd_azf3328_timer_stop(timer);
1960
1961 err = 0;
1962
1963 out:
1964 snd_azf3328_dbgcallleave();
1965 return err;
1966 }
1967
1968 /******************************************************************/
1969
1970 static int
1971 snd_azf3328_free(struct snd_azf3328 *chip)
1972 {
1973 if (chip->irq < 0)
1974 goto __end_hw;
1975
1976 /* reset (close) mixer:
1977 * first mute master volume, then reset
1978 */
1979 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
1980 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
1981
1982 snd_azf3328_timer_stop(chip->timer);
1983 snd_azf3328_gameport_free(chip);
1984
1985 if (chip->irq >= 0)
1986 synchronize_irq(chip->irq);
1987 __end_hw:
1988 if (chip->irq >= 0)
1989 free_irq(chip->irq, chip);
1990 pci_release_regions(chip->pci);
1991 pci_disable_device(chip->pci);
1992
1993 kfree(chip);
1994 return 0;
1995 }
1996
1997 static int
1998 snd_azf3328_dev_free(struct snd_device *device)
1999 {
2000 struct snd_azf3328 *chip = device->device_data;
2001 return snd_azf3328_free(chip);
2002 }
2003
2004 #if 0
2005 /* check whether a bit can be modified */
2006 static void
2007 snd_azf3328_test_bit(unsigned unsigned reg, int bit)
2008 {
2009 unsigned char val, valoff, valon;
2010
2011 val = inb(reg);
2012
2013 outb(val & ~(1 << bit), reg);
2014 valoff = inb(reg);
2015
2016 outb(val|(1 << bit), reg);
2017 valon = inb(reg);
2018
2019 outb(val, reg);
2020
2021 printk(KERN_ERR "reg %04x bit %d: %02x %02x %02x\n",
2022 reg, bit, val, valoff, valon
2023 );
2024 }
2025 #endif
2026
2027 static inline void
2028 snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
2029 {
2030 #if DEBUG_MISC
2031 u16 tmp;
2032
2033 snd_azf3328_dbgmisc(
2034 "codec_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, "
2035 "opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n",
2036 chip->codec_io, chip->game_io, chip->mpu_io,
2037 chip->opl3_io, chip->mixer_io, chip->irq
2038 );
2039
2040 snd_azf3328_dbgmisc("game %02x %02x %02x %02x %02x %02x\n",
2041 snd_azf3328_game_inb(chip, 0),
2042 snd_azf3328_game_inb(chip, 1),
2043 snd_azf3328_game_inb(chip, 2),
2044 snd_azf3328_game_inb(chip, 3),
2045 snd_azf3328_game_inb(chip, 4),
2046 snd_azf3328_game_inb(chip, 5)
2047 );
2048
2049 for (tmp = 0; tmp < 0x07; tmp += 1)
2050 snd_azf3328_dbgmisc("mpu_io 0x%04x\n", inb(chip->mpu_io + tmp));
2051
2052 for (tmp = 0; tmp <= 0x07; tmp += 1)
2053 snd_azf3328_dbgmisc("0x%02x: game200 0x%04x, game208 0x%04x\n",
2054 tmp, inb(0x200 + tmp), inb(0x208 + tmp));
2055
2056 for (tmp = 0; tmp <= 0x01; tmp += 1)
2057 snd_azf3328_dbgmisc(
2058 "0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, "
2059 "mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n",
2060 tmp,
2061 inb(0x300 + tmp),
2062 inb(0x310 + tmp),
2063 inb(0x320 + tmp),
2064 inb(0x330 + tmp),
2065 inb(0x388 + tmp),
2066 inb(0x38c + tmp)
2067 );
2068
2069 for (tmp = 0; tmp < AZF_IO_SIZE_CODEC; tmp += 2)
2070 snd_azf3328_dbgmisc("codec 0x%02x: 0x%04x\n",
2071 tmp, snd_azf3328_codec_inw(chip, tmp)
2072 );
2073
2074 for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2)
2075 snd_azf3328_dbgmisc("mixer 0x%02x: 0x%04x\n",
2076 tmp, snd_azf3328_mixer_inw(chip, tmp)
2077 );
2078 #endif /* DEBUG_MISC */
2079 }
2080
2081 static int __devinit
2082 snd_azf3328_create(struct snd_card *card,
2083 struct pci_dev *pci,
2084 unsigned long device_type,
2085 struct snd_azf3328 **rchip)
2086 {
2087 struct snd_azf3328 *chip;
2088 int err;
2089 static struct snd_device_ops ops = {
2090 .dev_free = snd_azf3328_dev_free,
2091 };
2092 u16 tmp;
2093
2094 *rchip = NULL;
2095
2096 err = pci_enable_device(pci);
2097 if (err < 0)
2098 return err;
2099
2100 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2101 if (chip == NULL) {
2102 err = -ENOMEM;
2103 goto out_err;
2104 }
2105 spin_lock_init(&chip->reg_lock);
2106 chip->card = card;
2107 chip->pci = pci;
2108 chip->irq = -1;
2109
2110 /* check if we can restrict PCI DMA transfers to 24 bits */
2111 if (pci_set_dma_mask(pci, DMA_24BIT_MASK) < 0 ||
2112 pci_set_consistent_dma_mask(pci, DMA_24BIT_MASK) < 0) {
2113 snd_printk(KERN_ERR "architecture does not support "
2114 "24bit PCI busmaster DMA\n"
2115 );
2116 err = -ENXIO;
2117 goto out_err;
2118 }
2119
2120 err = pci_request_regions(pci, "Aztech AZF3328");
2121 if (err < 0)
2122 goto out_err;
2123
2124 chip->codec_io = pci_resource_start(pci, 0);
2125 chip->game_io = pci_resource_start(pci, 1);
2126 chip->mpu_io = pci_resource_start(pci, 2);
2127 chip->opl3_io = pci_resource_start(pci, 3);
2128 chip->mixer_io = pci_resource_start(pci, 4);
2129
2130 chip->audio_stream[AZF_PLAYBACK].portbase = chip->codec_io + 0x00;
2131 chip->audio_stream[AZF_CAPTURE].portbase = chip->codec_io + 0x20;
2132
2133 if (request_irq(pci->irq, snd_azf3328_interrupt,
2134 IRQF_SHARED, card->shortname, chip)) {
2135 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2136 err = -EBUSY;
2137 goto out_err;
2138 }
2139 chip->irq = pci->irq;
2140 pci_set_master(pci);
2141 synchronize_irq(chip->irq);
2142
2143 snd_azf3328_debug_show_ports(chip);
2144
2145 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2146 if (err < 0)
2147 goto out_err;
2148
2149 /* create mixer interface & switches */
2150 err = snd_azf3328_mixer_new(chip);
2151 if (err < 0)
2152 goto out_err;
2153
2154 /* shutdown codecs to save power */
2155 /* have snd_azf3328_codec_activity() act properly */
2156 chip->audio_stream[AZF_PLAYBACK].running = 1;
2157 snd_azf3328_codec_activity(chip, AZF_PLAYBACK, 0);
2158
2159 /* standard chip init stuff */
2160 /* default IRQ init value */
2161 tmp = DMA_PLAY_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
2162
2163 spin_lock_irq(&chip->reg_lock);
2164 snd_azf3328_codec_outb(chip, IDX_IO_PLAY_FLAGS, tmp);
2165 snd_azf3328_codec_outb(chip, IDX_IO_REC_FLAGS, tmp);
2166 snd_azf3328_codec_outb(chip, IDX_IO_SOMETHING_FLAGS, tmp);
2167 spin_unlock_irq(&chip->reg_lock);
2168
2169 snd_card_set_dev(card, &pci->dev);
2170
2171 *rchip = chip;
2172
2173 err = 0;
2174 goto out;
2175
2176 out_err:
2177 if (chip)
2178 snd_azf3328_free(chip);
2179 pci_disable_device(pci);
2180
2181 out:
2182 return err;
2183 }
2184
2185 static int __devinit
2186 snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2187 {
2188 static int dev;
2189 struct snd_card *card;
2190 struct snd_azf3328 *chip;
2191 struct snd_opl3 *opl3;
2192 int err;
2193
2194 snd_azf3328_dbgcallenter();
2195 if (dev >= SNDRV_CARDS)
2196 return -ENODEV;
2197 if (!enable[dev]) {
2198 dev++;
2199 return -ENOENT;
2200 }
2201
2202 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2203 if (card == NULL)
2204 return -ENOMEM;
2205
2206 strcpy(card->driver, "AZF3328");
2207 strcpy(card->shortname, "Aztech AZF3328 (PCI168)");
2208
2209 err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip);
2210 if (err < 0)
2211 goto out_err;
2212
2213 card->private_data = chip;
2214
2215 err = snd_mpu401_uart_new(
2216 card, 0, MPU401_HW_MPU401, chip->mpu_io, MPU401_INFO_INTEGRATED,
2217 pci->irq, 0, &chip->rmidi
2218 );
2219 if (err < 0) {
2220 snd_printk(KERN_ERR "azf3328: no MPU-401 device at 0x%lx?\n",
2221 chip->mpu_io
2222 );
2223 goto out_err;
2224 }
2225
2226 err = snd_azf3328_timer(chip, 0);
2227 if (err < 0)
2228 goto out_err;
2229
2230 err = snd_azf3328_pcm(chip, 0);
2231 if (err < 0)
2232 goto out_err;
2233
2234 if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2,
2235 OPL3_HW_AUTO, 1, &opl3) < 0) {
2236 snd_printk(KERN_ERR "azf3328: no OPL3 device at 0x%lx-0x%lx?\n",
2237 chip->opl3_io, chip->opl3_io+2
2238 );
2239 } else {
2240 /* need to use IDs 1, 2 since ID 0 is snd_azf3328_timer above */
2241 err = snd_opl3_timer_new(opl3, 1, 2);
2242 if (err < 0)
2243 goto out_err;
2244 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
2245 if (err < 0)
2246 goto out_err;
2247 }
2248
2249 opl3->private_data = chip;
2250
2251 sprintf(card->longname, "%s at 0x%lx, irq %i",
2252 card->shortname, chip->codec_io, chip->irq);
2253
2254 err = snd_card_register(card);
2255 if (err < 0)
2256 goto out_err;
2257
2258 #ifdef MODULE
2259 printk(
2260 "azt3328: Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n"
2261 "azt3328: Hardware was completely undocumented, unfortunately.\n"
2262 "azt3328: Feel free to contact andi AT lisas.de for bug reports etc.!\n"
2263 "azt3328: User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
2264 1024000 / seqtimer_scaling, seqtimer_scaling);
2265 #endif
2266
2267 snd_azf3328_gameport(chip, dev);
2268
2269 pci_set_drvdata(pci, card);
2270 dev++;
2271
2272 err = 0;
2273 goto out;
2274
2275 out_err:
2276 snd_printk(KERN_ERR "azf3328: something failed, exiting\n");
2277 snd_card_free(card);
2278
2279 out:
2280 snd_azf3328_dbgcallleave();
2281 return err;
2282 }
2283
2284 static void __devexit
2285 snd_azf3328_remove(struct pci_dev *pci)
2286 {
2287 snd_azf3328_dbgcallenter();
2288 snd_card_free(pci_get_drvdata(pci));
2289 pci_set_drvdata(pci, NULL);
2290 snd_azf3328_dbgcallleave();
2291 }
2292
2293 #ifdef CONFIG_PM
2294 static int
2295 snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state)
2296 {
2297 struct snd_card *card = pci_get_drvdata(pci);
2298 struct snd_azf3328 *chip = card->private_data;
2299 unsigned reg;
2300
2301 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2302
2303 snd_pcm_suspend_all(chip->pcm);
2304
2305 for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; ++reg)
2306 chip->saved_regs_mixer[reg] = inw(chip->mixer_io + reg * 2);
2307
2308 /* make sure to disable master volume etc. to prevent looping sound */
2309 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
2310 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
2311
2312 for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; ++reg)
2313 chip->saved_regs_codec[reg] = inw(chip->codec_io + reg * 2);
2314 for (reg = 0; reg < AZF_IO_SIZE_GAME_PM / 2; ++reg)
2315 chip->saved_regs_game[reg] = inw(chip->game_io + reg * 2);
2316 for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; ++reg)
2317 chip->saved_regs_mpu[reg] = inw(chip->mpu_io + reg * 2);
2318 for (reg = 0; reg < AZF_IO_SIZE_OPL3_PM / 2; ++reg)
2319 chip->saved_regs_opl3[reg] = inw(chip->opl3_io + reg * 2);
2320
2321 pci_disable_device(pci);
2322 pci_save_state(pci);
2323 pci_set_power_state(pci, pci_choose_state(pci, state));
2324 return 0;
2325 }
2326
2327 static int
2328 snd_azf3328_resume(struct pci_dev *pci)
2329 {
2330 struct snd_card *card = pci_get_drvdata(pci);
2331 struct snd_azf3328 *chip = card->private_data;
2332 unsigned reg;
2333
2334 pci_set_power_state(pci, PCI_D0);
2335 pci_restore_state(pci);
2336 if (pci_enable_device(pci) < 0) {
2337 printk(KERN_ERR "azt3328: pci_enable_device failed, "
2338 "disabling device\n");
2339 snd_card_disconnect(card);
2340 return -EIO;
2341 }
2342 pci_set_master(pci);
2343
2344 for (reg = 0; reg < AZF_IO_SIZE_GAME_PM / 2; ++reg)
2345 outw(chip->saved_regs_game[reg], chip->game_io + reg * 2);
2346 for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; ++reg)
2347 outw(chip->saved_regs_mpu[reg], chip->mpu_io + reg * 2);
2348 for (reg = 0; reg < AZF_IO_SIZE_OPL3_PM / 2; ++reg)
2349 outw(chip->saved_regs_opl3[reg], chip->opl3_io + reg * 2);
2350 for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; ++reg)
2351 outw(chip->saved_regs_mixer[reg], chip->mixer_io + reg * 2);
2352 for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; ++reg)
2353 outw(chip->saved_regs_codec[reg], chip->codec_io + reg * 2);
2354
2355 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2356 return 0;
2357 }
2358 #endif /* CONFIG_PM */
2359
2360
2361 static struct pci_driver driver = {
2362 .name = "AZF3328",
2363 .id_table = snd_azf3328_ids,
2364 .probe = snd_azf3328_probe,
2365 .remove = __devexit_p(snd_azf3328_remove),
2366 #ifdef CONFIG_PM
2367 .suspend = snd_azf3328_suspend,
2368 .resume = snd_azf3328_resume,
2369 #endif
2370 };
2371
2372 static int __init
2373 alsa_card_azf3328_init(void)
2374 {
2375 int err;
2376 snd_azf3328_dbgcallenter();
2377 err = pci_register_driver(&driver);
2378 snd_azf3328_dbgcallleave();
2379 return err;
2380 }
2381
2382 static void __exit
2383 alsa_card_azf3328_exit(void)
2384 {
2385 snd_azf3328_dbgcallenter();
2386 pci_unregister_driver(&driver);
2387 snd_azf3328_dbgcallleave();
2388 }
2389
2390 module_init(alsa_card_azf3328_init)
2391 module_exit(alsa_card_azf3328_exit)
Linux kernel - Deliverables
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