projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[ALSA] cmipci: update register definitions
[deliverable/linux.git] / sound / pci / cmipci.c
1 /*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
22
23 #include <sound/driver.h>
24 #include <asm/io.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <linux/mutex.h>
33 #include <sound/core.h>
34 #include <sound/info.h>
35 #include <sound/control.h>
36 #include <sound/pcm.h>
37 #include <sound/rawmidi.h>
38 #include <sound/mpu401.h>
39 #include <sound/opl3.h>
40 #include <sound/sb.h>
41 #include <sound/asoundef.h>
42 #include <sound/initval.h>
43
44 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
45 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
48 "{C-Media,CMI8738B},"
49 "{C-Media,CMI8338A},"
50 "{C-Media,CMI8338B}}");
51
52 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
53 #define SUPPORT_JOYSTICK 1
54 #endif
55
56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
59 static long mpu_port[SNDRV_CARDS];
60 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
62 #ifdef SUPPORT_JOYSTICK
63 static int joystick_port[SNDRV_CARDS];
64 #endif
65
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
68 module_param_array(id, charp, NULL, 0444);
69 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
70 module_param_array(enable, bool, NULL, 0444);
71 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
72 module_param_array(mpu_port, long, NULL, 0444);
73 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
74 module_param_array(fm_port, long, NULL, 0444);
75 MODULE_PARM_DESC(fm_port, "FM port.");
76 module_param_array(soft_ac3, bool, NULL, 0444);
77 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
78 #ifdef SUPPORT_JOYSTICK
79 module_param_array(joystick_port, int, NULL, 0444);
80 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
81 #endif
82
83 /*
84 * CM8x38 registers definition
85 */
86
87 #define CM_REG_FUNCTRL0 0x00
88 #define CM_RST_CH1 0x00080000
89 #define CM_RST_CH0 0x00040000
90 #define CM_CHEN1 0x00020000 /* ch1: enable */
91 #define CM_CHEN0 0x00010000 /* ch0: enable */
92 #define CM_PAUSE1 0x00000008 /* ch1: pause */
93 #define CM_PAUSE0 0x00000004 /* ch0: pause */
94 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
95 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
96
97 #define CM_REG_FUNCTRL1 0x04
98 #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
99 #define CM_DSFC_SHIFT 13
100 #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
101 #define CM_ASFC_SHIFT 10
102 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
103 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
104 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
105 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
106 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
107 #define CM_BREQ 0x00000010 /* bus master enabled */
108 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
109 #define CM_UART_EN 0x00000004 /* legacy UART */
110 #define CM_JYSTK_EN 0x00000002 /* legacy joystick */
111 #define CM_ZVPORT 0x00000001 /* ZVPORT */
112
113 #define CM_REG_CHFORMAT 0x08
114
115 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
116 #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
117 #define CM_CHB3D 0x20000000 /* 4 channels */
118
119 #define CM_CHIP_MASK1 0x1f000000
120 #define CM_CHIP_037 0x01000000
121 #define CM_SETLAT48 0x00800000 /* set latency timer 48h */
122 #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
123 #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
124 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
125 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
126 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
127 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
128
129 #define CM_ADCBITLEN_MASK 0x0000C000
130 #define CM_ADCBITLEN_16 0x00000000
131 #define CM_ADCBITLEN_15 0x00004000
132 #define CM_ADCBITLEN_14 0x00008000
133 #define CM_ADCBITLEN_13 0x0000C000
134
135 #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
136 #define CM_ADCDACLEN_060 0x00000000
137 #define CM_ADCDACLEN_066 0x00001000
138 #define CM_ADCDACLEN_130 0x00002000
139 #define CM_ADCDACLEN_280 0x00003000
140
141 #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
142 #define CM_ADCDLEN_ORIGINAL 0x00000000
143 #define CM_ADCDLEN_EXTRA 0x00001000
144 #define CM_ADCDLEN_24K 0x00002000
145 #define CM_ADCDLEN_WEIGHT 0x00003000
146
147 #define CM_CH1_SRATE_176K 0x00000800
148 #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
149 #define CM_CH1_SRATE_88K 0x00000400
150 #define CM_CH0_SRATE_176K 0x00000200
151 #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
152 #define CM_CH0_SRATE_88K 0x00000100
153
154 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
155 #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
156 #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
157 #define CM_SPDLOCKED 0x00000010
158
159 #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
160 #define CM_CH1FMT_SHIFT 2
161 #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
162 #define CM_CH0FMT_SHIFT 0
163
164 #define CM_REG_INT_HLDCLR 0x0C
165 #define CM_CHIP_MASK2 0xff000000
166 #define CM_CHIP_8768 0x20000000
167 #define CM_CHIP_055 0x08000000
168 #define CM_CHIP_039 0x04000000
169 #define CM_CHIP_039_6CH 0x01000000
170 #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
171 #define CM_TDMA_INT_EN 0x00040000
172 #define CM_CH1_INT_EN 0x00020000
173 #define CM_CH0_INT_EN 0x00010000
174
175 #define CM_REG_INT_STATUS 0x10
176 #define CM_INTR 0x80000000
177 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
178 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
179 #define CM_UARTINT 0x00010000
180 #define CM_LTDMAINT 0x00008000
181 #define CM_HTDMAINT 0x00004000
182 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
183 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
184 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
185 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
186 #define CM_CH1BUSY 0x00000008
187 #define CM_CH0BUSY 0x00000004
188 #define CM_CHINT1 0x00000002
189 #define CM_CHINT0 0x00000001
190
191 #define CM_REG_LEGACY_CTRL 0x14
192 #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
193 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
194 #define CM_VMPU_330 0x00000000
195 #define CM_VMPU_320 0x20000000
196 #define CM_VMPU_310 0x40000000
197 #define CM_VMPU_300 0x60000000
198 #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
199 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
200 #define CM_VSBSEL_220 0x00000000
201 #define CM_VSBSEL_240 0x04000000
202 #define CM_VSBSEL_260 0x08000000
203 #define CM_VSBSEL_280 0x0C000000
204 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
205 #define CM_FMSEL_388 0x00000000
206 #define CM_FMSEL_3C8 0x01000000
207 #define CM_FMSEL_3E0 0x02000000
208 #define CM_FMSEL_3E8 0x03000000
209 #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
210 #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
211 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
212 #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
213 #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
214 #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
215 #define CM_C_EECS 0x00040000
216 #define CM_C_EEDI46 0x00020000
217 #define CM_C_EECK46 0x00010000
218 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
219 #define CM_CENTR2LIN 0x00004000 /* line-in as center out */
220 #define CM_BASE2LIN 0x00002000 /* line-in as bass out */
221 #define CM_EXBASEN 0x00001000 /* external bass input enable */
222
223 #define CM_REG_MISC_CTRL 0x18
224 #define CM_PWD 0x80000000 /* power down */
225 #define CM_RESET 0x40000000
226 #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
227 #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
228 #define CM_TXVX 0x08000000 /* model 037? */
229 #define CM_N4SPK3D 0x04000000 /* copy front to rear */
230 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
231 #define CM_SPDIF48K 0x01000000 /* write */
232 #define CM_SPATUS48K 0x01000000 /* read */
233 #define CM_ENDBDAC 0x00800000 /* enable double dac */
234 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
235 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
236 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
237 #define CM_FM_EN 0x00080000 /* enable legacy FM */
238 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
239 #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
240 #define CM_VIDWPDSB 0x00010000 /* model 037? */
241 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
242 #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
243 #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
244 #define CM_VIDWPPRT 0x00002000 /* model 037? */
245 #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
246 #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
247 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
248 #define CM_ENCENTER 0x00000080
249 #define CM_FLINKON 0x00000080 /* force modem link detection on, model 037 */
250 #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
251 #define CM_FLINKOFF 0x00000040 /* force modem link detection off, model 037 */
252 #define CM_UNKNOWN_18_5 0x00000020 /* ? */
253 #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
254 #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
255 #define CM_UPDDMA_2048 0x00000000
256 #define CM_UPDDMA_1024 0x00000004
257 #define CM_UPDDMA_512 0x00000008
258 #define CM_UPDDMA_256 0x0000000C
259 #define CM_TWAIT_MASK 0x00000003 /* model 037 */
260 #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
261 #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
262
263 #define CM_REG_TDMA_POSITION 0x1C
264 #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
265 #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
266
267 /* byte */
268 #define CM_REG_MIXER0 0x20
269 #define CM_REG_SBVR 0x20 /* write: sb16 version */
270 #define CM_REG_DEV 0x20 /* read: hardware device version */
271
272 #define CM_REG_MIXER21 0x21
273 #define CM_UNKNOWN_21_MASK 0x78 /* ? */
274 #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
275 #define CM_PROINV 0x02 /* SBPro left/right channel switching */
276 #define CM_X_SB16 0x01 /* SB16 compatible */
277
278 #define CM_REG_SB16_DATA 0x22
279 #define CM_REG_SB16_ADDR 0x23
280
281 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
282 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
283 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
284 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
285
286 #define CM_REG_MIXER1 0x24
287 #define CM_FMMUTE 0x80 /* mute FM */
288 #define CM_FMMUTE_SHIFT 7
289 #define CM_WSMUTE 0x40 /* mute PCM */
290 #define CM_WSMUTE_SHIFT 6
291 #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
292 #define CM_REAR2LIN_SHIFT 5
293 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
294 #define CM_REAR2FRONT_SHIFT 4
295 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
296 #define CM_WAVEINL_SHIFT 3
297 #define CM_WAVEINR 0x04 /* digical wave rec. right */
298 #define CM_WAVEINR_SHIFT 2
299 #define CM_X3DEN 0x02 /* 3D surround enable */
300 #define CM_X3DEN_SHIFT 1
301 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
302 #define CM_CDPLAY_SHIFT 0
303
304 #define CM_REG_MIXER2 0x25
305 #define CM_RAUXREN 0x80 /* AUX right capture */
306 #define CM_RAUXREN_SHIFT 7
307 #define CM_RAUXLEN 0x40 /* AUX left capture */
308 #define CM_RAUXLEN_SHIFT 6
309 #define CM_VAUXRM 0x20 /* AUX right mute */
310 #define CM_VAUXRM_SHIFT 5
311 #define CM_VAUXLM 0x10 /* AUX left mute */
312 #define CM_VAUXLM_SHIFT 4
313 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
314 #define CM_VADMIC_SHIFT 1
315 #define CM_MICGAINZ 0x01 /* mic boost */
316 #define CM_MICGAINZ_SHIFT 0
317
318 #define CM_REG_MIXER3 0x24
319 #define CM_REG_AUX_VOL 0x26
320 #define CM_VAUXL_MASK 0xf0
321 #define CM_VAUXR_MASK 0x0f
322
323 #define CM_REG_MISC 0x27
324 #define CM_UNKNOWN_27_MASK 0xd8 /* ? */
325 #define CM_XGPO1 0x20
326 // #define CM_XGPBIO 0x04
327 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
328 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
329 #define CM_SPDVALID 0x02 /* spdif input valid check */
330 #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
331
332 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
333 /*
334 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
335 * or identical with AC97 codec?
336 */
337 #define CM_REG_EXTERN_CODEC CM_REG_AC97
338
339 /*
340 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
341 */
342 #define CM_REG_MPU_PCI 0x40
343
344 /*
345 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
346 */
347 #define CM_REG_FM_PCI 0x50
348
349 /*
350 * access from SB-mixer port
351 */
352 #define CM_REG_EXTENT_IND 0xf0
353 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
354 #define CM_VPHONE_SHIFT 5
355 #define CM_VPHOM 0x10 /* Phone mute control */
356 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
357 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
358 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
359 #define CM_VADMIC3 0x01 /* Mic record boost */
360
361 /*
362 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
363 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
364 * unit (readonly?).
365 */
366 #define CM_REG_PLL 0xf8
367
368 /*
369 * extended registers
370 */
371 #define CM_REG_CH0_FRAME1 0x80 /* write: base address */
372 #define CM_REG_CH0_FRAME2 0x84 /* read: current address */
373 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
374 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
375
376 #define CM_REG_EXT_MISC 0x90
377 #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
378 #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
379 #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
380 #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
381 #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
382 #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
383 #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
384 #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
385
386 /*
387 * size of i/o region
388 */
389 #define CM_EXTENT_CODEC 0x100
390 #define CM_EXTENT_MIDI 0x2
391 #define CM_EXTENT_SYNTH 0x4
392
393
394 /*
395 * channels for playback / capture
396 */
397 #define CM_CH_PLAY 0
398 #define CM_CH_CAPT 1
399
400 /*
401 * flags to check device open/close
402 */
403 #define CM_OPEN_NONE 0
404 #define CM_OPEN_CH_MASK 0x01
405 #define CM_OPEN_DAC 0x10
406 #define CM_OPEN_ADC 0x20
407 #define CM_OPEN_SPDIF 0x40
408 #define CM_OPEN_MCHAN 0x80
409 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
410 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
411 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
412 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
413 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
414 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
415
416
417 #if CM_CH_PLAY == 1
418 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
419 #define CM_PLAYBACK_SPDF CM_SPDF_1
420 #define CM_CAPTURE_SPDF CM_SPDF_0
421 #else
422 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
423 #define CM_PLAYBACK_SPDF CM_SPDF_0
424 #define CM_CAPTURE_SPDF CM_SPDF_1
425 #endif
426
427
428 /*
429 * driver data
430 */
431
432 struct cmipci_pcm {
433 struct snd_pcm_substream *substream;
434 int running; /* dac/adc running? */
435 unsigned int dma_size; /* in frames */
436 unsigned int period_size; /* in frames */
437 unsigned int offset; /* physical address of the buffer */
438 unsigned int fmt; /* format bits */
439 int ch; /* channel (0/1) */
440 unsigned int is_dac; /* is dac? */
441 int bytes_per_frame;
442 int shift;
443 };
444
445 /* mixer elements toggled/resumed during ac3 playback */
446 struct cmipci_mixer_auto_switches {
447 const char *name; /* switch to toggle */
448 int toggle_on; /* value to change when ac3 mode */
449 };
450 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
451 {"PCM Playback Switch", 0},
452 {"IEC958 Output Switch", 1},
453 {"IEC958 Mix Analog", 0},
454 // {"IEC958 Out To DAC", 1}, // no longer used
455 {"IEC958 Loop", 0},
456 };
457 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
458
459 struct cmipci {
460 struct snd_card *card;
461
462 struct pci_dev *pci;
463 unsigned int device; /* device ID */
464 int irq;
465
466 unsigned long iobase;
467 unsigned int ctrl; /* FUNCTRL0 current value */
468
469 struct snd_pcm *pcm; /* DAC/ADC PCM */
470 struct snd_pcm *pcm2; /* 2nd DAC */
471 struct snd_pcm *pcm_spdif; /* SPDIF */
472
473 int chip_version;
474 int max_channels;
475 unsigned int can_ac3_sw: 1;
476 unsigned int can_ac3_hw: 1;
477 unsigned int can_multi_ch: 1;
478 unsigned int do_soft_ac3: 1;
479
480 unsigned int spdif_playback_avail: 1; /* spdif ready? */
481 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
482 int spdif_counter; /* for software AC3 */
483
484 unsigned int dig_status;
485 unsigned int dig_pcm_status;
486
487 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
488
489 int opened[2]; /* open mode */
490 struct mutex open_mutex;
491
492 unsigned int mixer_insensitive: 1;
493 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
494 int mixer_res_status[CM_SAVED_MIXERS];
495
496 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
497
498 /* external MIDI */
499 struct snd_rawmidi *rmidi;
500
501 #ifdef SUPPORT_JOYSTICK
502 struct gameport *gameport;
503 #endif
504
505 spinlock_t reg_lock;
506
507 #ifdef CONFIG_PM
508 unsigned int saved_regs[0x20];
509 unsigned char saved_mixers[0x20];
510 #endif
511 };
512
513
514 /* read/write operations for dword register */
515 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
516 {
517 outl(data, cm->iobase + cmd);
518 }
519
520 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
521 {
522 return inl(cm->iobase + cmd);
523 }
524
525 /* read/write operations for word register */
526 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
527 {
528 outw(data, cm->iobase + cmd);
529 }
530
531 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
532 {
533 return inw(cm->iobase + cmd);
534 }
535
536 /* read/write operations for byte register */
537 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
538 {
539 outb(data, cm->iobase + cmd);
540 }
541
542 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
543 {
544 return inb(cm->iobase + cmd);
545 }
546
547 /* bit operations for dword register */
548 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
549 {
550 unsigned int val, oval;
551 val = oval = inl(cm->iobase + cmd);
552 val |= flag;
553 if (val == oval)
554 return 0;
555 outl(val, cm->iobase + cmd);
556 return 1;
557 }
558
559 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
560 {
561 unsigned int val, oval;
562 val = oval = inl(cm->iobase + cmd);
563 val &= ~flag;
564 if (val == oval)
565 return 0;
566 outl(val, cm->iobase + cmd);
567 return 1;
568 }
569
570 /* bit operations for byte register */
571 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
572 {
573 unsigned char val, oval;
574 val = oval = inb(cm->iobase + cmd);
575 val |= flag;
576 if (val == oval)
577 return 0;
578 outb(val, cm->iobase + cmd);
579 return 1;
580 }
581
582 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
583 {
584 unsigned char val, oval;
585 val = oval = inb(cm->iobase + cmd);
586 val &= ~flag;
587 if (val == oval)
588 return 0;
589 outb(val, cm->iobase + cmd);
590 return 1;
591 }
592
593
594 /*
595 * PCM interface
596 */
597
598 /*
599 * calculate frequency
600 */
601
602 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
603
604 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
605 {
606 unsigned int i;
607 for (i = 0; i < ARRAY_SIZE(rates); i++) {
608 if (rates[i] == rate)
609 return i;
610 }
611 snd_BUG();
612 return 0;
613 }
614
615 #ifdef USE_VAR48KRATE
616 /*
617 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
618 * does it this way .. maybe not. Never get any information from C-Media about
619 * that <werner@suse.de>.
620 */
621 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
622 {
623 unsigned int delta, tolerance;
624 int xm, xn, xr;
625
626 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
627 rate <<= 1;
628 *n = -1;
629 if (*r > 0xff)
630 goto out;
631 tolerance = rate*CM_TOLERANCE_RATE;
632
633 for (xn = (1+2); xn < (0x1f+2); xn++) {
634 for (xm = (1+2); xm < (0xff+2); xm++) {
635 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
636
637 if (xr < rate)
638 delta = rate - xr;
639 else
640 delta = xr - rate;
641
642 /*
643 * If we found one, remember this,
644 * and try to find a closer one
645 */
646 if (delta < tolerance) {
647 tolerance = delta;
648 *m = xm - 2;
649 *n = xn - 2;
650 }
651 }
652 }
653 out:
654 return (*n > -1);
655 }
656
657 /*
658 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
659 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
660 * at the register CM_REG_FUNCTRL1 (0x04).
661 * Problem: other ways are also possible (any information about that?)
662 */
663 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
664 {
665 unsigned int reg = CM_REG_PLL + slot;
666 /*
667 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
668 * for DSFC/ASFC (000 upto 111).
669 */
670
671 /* FIXME: Init (Do we've to set an other register first before programming?) */
672
673 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
674 snd_cmipci_write_b(cm, reg, rate>>8);
675 snd_cmipci_write_b(cm, reg, rate&0xff);
676
677 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
678 }
679 #endif /* USE_VAR48KRATE */
680
681 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
682 struct snd_pcm_hw_params *hw_params)
683 {
684 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
685 }
686
687 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
688 struct snd_pcm_hw_params *hw_params)
689 {
690 struct cmipci *cm = snd_pcm_substream_chip(substream);
691 if (params_channels(hw_params) > 2) {
692 mutex_lock(&cm->open_mutex);
693 if (cm->opened[CM_CH_PLAY]) {
694 mutex_unlock(&cm->open_mutex);
695 return -EBUSY;
696 }
697 /* reserve the channel A */
698 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
699 mutex_unlock(&cm->open_mutex);
700 }
701 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
702 }
703
704 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
705 {
706 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
707 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
708 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
709 udelay(10);
710 }
711
712 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
713 {
714 return snd_pcm_lib_free_pages(substream);
715 }
716
717
718 /*
719 */
720
721 static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8};
722 static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
723 .count = 3,
724 .list = hw_channels,
725 .mask = 0,
726 };
727 static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
728 .count = 5,
729 .list = hw_channels,
730 .mask = 0,
731 };
732 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
733 .count = 6,
734 .list = hw_channels,
735 .mask = 0,
736 };
737
738 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
739 {
740 if (channels > 2) {
741 if (! cm->can_multi_ch)
742 return -EINVAL;
743 if (rec->fmt != 0x03) /* stereo 16bit only */
744 return -EINVAL;
745
746 spin_lock_irq(&cm->reg_lock);
747 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
748 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
749 if (channels > 4) {
750 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
751 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
752 } else {
753 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
754 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
755 }
756 if (channels >= 6) {
757 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
758 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
759 } else {
760 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
761 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
762 }
763 if (cm->chip_version == 68) {
764 if (channels == 8) {
765 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
766 } else {
767 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
768 }
769 }
770 spin_unlock_irq(&cm->reg_lock);
771
772 } else {
773 if (cm->can_multi_ch) {
774 spin_lock_irq(&cm->reg_lock);
775 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
776 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
777 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
778 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
779 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER);
780 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
781 spin_unlock_irq(&cm->reg_lock);
782 }
783 }
784 return 0;
785 }
786
787
788 /*
789 * prepare playback/capture channel
790 * channel to be used must have been set in rec->ch.
791 */
792 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
793 struct snd_pcm_substream *substream)
794 {
795 unsigned int reg, freq, val;
796 struct snd_pcm_runtime *runtime = substream->runtime;
797
798 rec->fmt = 0;
799 rec->shift = 0;
800 if (snd_pcm_format_width(runtime->format) >= 16) {
801 rec->fmt |= 0x02;
802 if (snd_pcm_format_width(runtime->format) > 16)
803 rec->shift++; /* 24/32bit */
804 }
805 if (runtime->channels > 1)
806 rec->fmt |= 0x01;
807 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
808 snd_printd("cannot set dac channels\n");
809 return -EINVAL;
810 }
811
812 rec->offset = runtime->dma_addr;
813 /* buffer and period sizes in frame */
814 rec->dma_size = runtime->buffer_size << rec->shift;
815 rec->period_size = runtime->period_size << rec->shift;
816 if (runtime->channels > 2) {
817 /* multi-channels */
818 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
819 rec->period_size = (rec->period_size * runtime->channels) / 2;
820 }
821
822 spin_lock_irq(&cm->reg_lock);
823
824 /* set buffer address */
825 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
826 snd_cmipci_write(cm, reg, rec->offset);
827 /* program sample counts */
828 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
829 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
830 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1);
831
832 /* set adc/dac flag */
833 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
834 if (rec->is_dac)
835 cm->ctrl &= ~val;
836 else
837 cm->ctrl |= val;
838 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
839 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
840
841 /* set sample rate */
842 freq = snd_cmipci_rate_freq(runtime->rate);
843 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
844 if (rec->ch) {
845 val &= ~CM_DSFC_MASK;
846 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
847 } else {
848 val &= ~CM_ASFC_MASK;
849 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
850 }
851 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
852 //snd_printd("cmipci: functrl1 = %08x\n", val);
853
854 /* set format */
855 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
856 if (rec->ch) {
857 val &= ~CM_CH1FMT_MASK;
858 val |= rec->fmt << CM_CH1FMT_SHIFT;
859 } else {
860 val &= ~CM_CH0FMT_MASK;
861 val |= rec->fmt << CM_CH0FMT_SHIFT;
862 }
863 if (cm->chip_version == 68) {
864 if (runtime->rate == 88200)
865 val |= CM_CH0_SRATE_88K << (rec->ch * 2);
866 else
867 val &= ~(CM_CH0_SRATE_88K << (rec->ch * 2));
868 if (runtime->rate == 96000)
869 val |= CM_CH0_SRATE_96K << (rec->ch * 2);
870 else
871 val &= ~(CM_CH0_SRATE_96K << (rec->ch * 2));
872 }
873 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
874 //snd_printd("cmipci: chformat = %08x\n", val);
875
876 rec->running = 0;
877 spin_unlock_irq(&cm->reg_lock);
878
879 return 0;
880 }
881
882 /*
883 * PCM trigger/stop
884 */
885 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
886 struct snd_pcm_substream *substream, int cmd)
887 {
888 unsigned int inthld, chen, reset, pause;
889 int result = 0;
890
891 inthld = CM_CH0_INT_EN << rec->ch;
892 chen = CM_CHEN0 << rec->ch;
893 reset = CM_RST_CH0 << rec->ch;
894 pause = CM_PAUSE0 << rec->ch;
895
896 spin_lock(&cm->reg_lock);
897 switch (cmd) {
898 case SNDRV_PCM_TRIGGER_START:
899 rec->running = 1;
900 /* set interrupt */
901 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
902 cm->ctrl |= chen;
903 /* enable channel */
904 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
905 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
906 break;
907 case SNDRV_PCM_TRIGGER_STOP:
908 rec->running = 0;
909 /* disable interrupt */
910 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
911 /* reset */
912 cm->ctrl &= ~chen;
913 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
914 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
915 break;
916 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
917 case SNDRV_PCM_TRIGGER_SUSPEND:
918 cm->ctrl |= pause;
919 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
920 break;
921 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
922 case SNDRV_PCM_TRIGGER_RESUME:
923 cm->ctrl &= ~pause;
924 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
925 break;
926 default:
927 result = -EINVAL;
928 break;
929 }
930 spin_unlock(&cm->reg_lock);
931 return result;
932 }
933
934 /*
935 * return the current pointer
936 */
937 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
938 struct snd_pcm_substream *substream)
939 {
940 size_t ptr;
941 unsigned int reg;
942 if (!rec->running)
943 return 0;
944 #if 1 // this seems better..
945 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
946 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
947 ptr >>= rec->shift;
948 #else
949 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
950 ptr = snd_cmipci_read(cm, reg) - rec->offset;
951 ptr = bytes_to_frames(substream->runtime, ptr);
952 #endif
953 if (substream->runtime->channels > 2)
954 ptr = (ptr * 2) / substream->runtime->channels;
955 return ptr;
956 }
957
958 /*
959 * playback
960 */
961
962 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
963 int cmd)
964 {
965 struct cmipci *cm = snd_pcm_substream_chip(substream);
966 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd);
967 }
968
969 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
970 {
971 struct cmipci *cm = snd_pcm_substream_chip(substream);
972 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
973 }
974
975
976
977 /*
978 * capture
979 */
980
981 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
982 int cmd)
983 {
984 struct cmipci *cm = snd_pcm_substream_chip(substream);
985 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd);
986 }
987
988 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
989 {
990 struct cmipci *cm = snd_pcm_substream_chip(substream);
991 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
992 }
993
994
995 /*
996 * hw preparation for spdif
997 */
998
999 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_info *uinfo)
1001 {
1002 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1003 uinfo->count = 1;
1004 return 0;
1005 }
1006
1007 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
1008 struct snd_ctl_elem_value *ucontrol)
1009 {
1010 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1011 int i;
1012
1013 spin_lock_irq(&chip->reg_lock);
1014 for (i = 0; i < 4; i++)
1015 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1016 spin_unlock_irq(&chip->reg_lock);
1017 return 0;
1018 }
1019
1020 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1021 struct snd_ctl_elem_value *ucontrol)
1022 {
1023 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1024 int i, change;
1025 unsigned int val;
1026
1027 val = 0;
1028 spin_lock_irq(&chip->reg_lock);
1029 for (i = 0; i < 4; i++)
1030 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1031 change = val != chip->dig_status;
1032 chip->dig_status = val;
1033 spin_unlock_irq(&chip->reg_lock);
1034 return change;
1035 }
1036
1037 static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata =
1038 {
1039 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1040 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1041 .info = snd_cmipci_spdif_default_info,
1042 .get = snd_cmipci_spdif_default_get,
1043 .put = snd_cmipci_spdif_default_put
1044 };
1045
1046 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1047 struct snd_ctl_elem_info *uinfo)
1048 {
1049 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1050 uinfo->count = 1;
1051 return 0;
1052 }
1053
1054 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1055 struct snd_ctl_elem_value *ucontrol)
1056 {
1057 ucontrol->value.iec958.status[0] = 0xff;
1058 ucontrol->value.iec958.status[1] = 0xff;
1059 ucontrol->value.iec958.status[2] = 0xff;
1060 ucontrol->value.iec958.status[3] = 0xff;
1061 return 0;
1062 }
1063
1064 static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata =
1065 {
1066 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1067 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1068 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1069 .info = snd_cmipci_spdif_mask_info,
1070 .get = snd_cmipci_spdif_mask_get,
1071 };
1072
1073 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1074 struct snd_ctl_elem_info *uinfo)
1075 {
1076 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1077 uinfo->count = 1;
1078 return 0;
1079 }
1080
1081 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1082 struct snd_ctl_elem_value *ucontrol)
1083 {
1084 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1085 int i;
1086
1087 spin_lock_irq(&chip->reg_lock);
1088 for (i = 0; i < 4; i++)
1089 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1090 spin_unlock_irq(&chip->reg_lock);
1091 return 0;
1092 }
1093
1094 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1095 struct snd_ctl_elem_value *ucontrol)
1096 {
1097 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1098 int i, change;
1099 unsigned int val;
1100
1101 val = 0;
1102 spin_lock_irq(&chip->reg_lock);
1103 for (i = 0; i < 4; i++)
1104 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1105 change = val != chip->dig_pcm_status;
1106 chip->dig_pcm_status = val;
1107 spin_unlock_irq(&chip->reg_lock);
1108 return change;
1109 }
1110
1111 static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata =
1112 {
1113 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1114 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1115 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1116 .info = snd_cmipci_spdif_stream_info,
1117 .get = snd_cmipci_spdif_stream_get,
1118 .put = snd_cmipci_spdif_stream_put
1119 };
1120
1121 /*
1122 */
1123
1124 /* save mixer setting and mute for AC3 playback */
1125 static int save_mixer_state(struct cmipci *cm)
1126 {
1127 if (! cm->mixer_insensitive) {
1128 struct snd_ctl_elem_value *val;
1129 unsigned int i;
1130
1131 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1132 if (!val)
1133 return -ENOMEM;
1134 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1135 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1136 if (ctl) {
1137 int event;
1138 memset(val, 0, sizeof(*val));
1139 ctl->get(ctl, val);
1140 cm->mixer_res_status[i] = val->value.integer.value[0];
1141 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1142 event = SNDRV_CTL_EVENT_MASK_INFO;
1143 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1144 ctl->put(ctl, val); /* toggle */
1145 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1146 }
1147 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1148 snd_ctl_notify(cm->card, event, &ctl->id);
1149 }
1150 }
1151 kfree(val);
1152 cm->mixer_insensitive = 1;
1153 }
1154 return 0;
1155 }
1156
1157
1158 /* restore the previously saved mixer status */
1159 static void restore_mixer_state(struct cmipci *cm)
1160 {
1161 if (cm->mixer_insensitive) {
1162 struct snd_ctl_elem_value *val;
1163 unsigned int i;
1164
1165 val = kmalloc(sizeof(*val), GFP_KERNEL);
1166 if (!val)
1167 return;
1168 cm->mixer_insensitive = 0; /* at first clear this;
1169 otherwise the changes will be ignored */
1170 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1171 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1172 if (ctl) {
1173 int event;
1174
1175 memset(val, 0, sizeof(*val));
1176 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1177 ctl->get(ctl, val);
1178 event = SNDRV_CTL_EVENT_MASK_INFO;
1179 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1180 val->value.integer.value[0] = cm->mixer_res_status[i];
1181 ctl->put(ctl, val);
1182 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1183 }
1184 snd_ctl_notify(cm->card, event, &ctl->id);
1185 }
1186 }
1187 kfree(val);
1188 }
1189 }
1190
1191 /* spinlock held! */
1192 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1193 {
1194 if (do_ac3) {
1195 /* AC3EN for 037 */
1196 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1197 /* AC3EN for 039 */
1198 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1199
1200 if (cm->can_ac3_hw) {
1201 /* SPD24SEL for 037, 0x02 */
1202 /* SPD24SEL for 039, 0x20, but cannot be set */
1203 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1204 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1205 } else { /* can_ac3_sw */
1206 /* SPD32SEL for 037 & 039, 0x20 */
1207 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1208 /* set 176K sample rate to fix 033 HW bug */
1209 if (cm->chip_version == 33) {
1210 if (rate >= 48000) {
1211 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1212 } else {
1213 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1214 }
1215 }
1216 }
1217
1218 } else {
1219 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1220 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1221
1222 if (cm->can_ac3_hw) {
1223 /* chip model >= 37 */
1224 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1225 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1226 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1227 } else {
1228 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1229 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1230 }
1231 } else {
1232 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1233 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1234 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1235 }
1236 }
1237 }
1238
1239 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1240 {
1241 int rate, err;
1242
1243 rate = subs->runtime->rate;
1244
1245 if (up && do_ac3)
1246 if ((err = save_mixer_state(cm)) < 0)
1247 return err;
1248
1249 spin_lock_irq(&cm->reg_lock);
1250 cm->spdif_playback_avail = up;
1251 if (up) {
1252 /* they are controlled via "IEC958 Output Switch" */
1253 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1254 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1255 if (cm->spdif_playback_enabled)
1256 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1257 setup_ac3(cm, subs, do_ac3, rate);
1258
1259 if (rate == 48000 || rate == 96000)
1260 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1261 else
1262 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1263 if (rate > 48000)
1264 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1265 else
1266 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1267 } else {
1268 /* they are controlled via "IEC958 Output Switch" */
1269 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1270 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1271 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1272 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1273 setup_ac3(cm, subs, 0, 0);
1274 }
1275 spin_unlock_irq(&cm->reg_lock);
1276 return 0;
1277 }
1278
1279
1280 /*
1281 * preparation
1282 */
1283
1284 /* playback - enable spdif only on the certain condition */
1285 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1286 {
1287 struct cmipci *cm = snd_pcm_substream_chip(substream);
1288 int rate = substream->runtime->rate;
1289 int err, do_spdif, do_ac3 = 0;
1290
1291 do_spdif = (rate >= 44100 &&
1292 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1293 substream->runtime->channels == 2);
1294 if (do_spdif && cm->can_ac3_hw)
1295 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1296 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1297 return err;
1298 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1299 }
1300
1301 /* playback (via device #2) - enable spdif always */
1302 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1303 {
1304 struct cmipci *cm = snd_pcm_substream_chip(substream);
1305 int err, do_ac3;
1306
1307 if (cm->can_ac3_hw)
1308 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1309 else
1310 do_ac3 = 1; /* doesn't matter */
1311 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1312 return err;
1313 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1314 }
1315
1316 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1317 {
1318 struct cmipci *cm = snd_pcm_substream_chip(substream);
1319 setup_spdif_playback(cm, substream, 0, 0);
1320 restore_mixer_state(cm);
1321 return snd_cmipci_hw_free(substream);
1322 }
1323
1324 /* capture */
1325 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1326 {
1327 struct cmipci *cm = snd_pcm_substream_chip(substream);
1328 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1329 }
1330
1331 /* capture with spdif (via device #2) */
1332 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1333 {
1334 struct cmipci *cm = snd_pcm_substream_chip(substream);
1335
1336 spin_lock_irq(&cm->reg_lock);
1337 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1338 spin_unlock_irq(&cm->reg_lock);
1339
1340 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1341 }
1342
1343 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1344 {
1345 struct cmipci *cm = snd_pcm_substream_chip(subs);
1346
1347 spin_lock_irq(&cm->reg_lock);
1348 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1349 spin_unlock_irq(&cm->reg_lock);
1350
1351 return snd_cmipci_hw_free(subs);
1352 }
1353
1354
1355 /*
1356 * interrupt handler
1357 */
1358 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1359 {
1360 struct cmipci *cm = dev_id;
1361 unsigned int status, mask = 0;
1362
1363 /* fastpath out, to ease interrupt sharing */
1364 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1365 if (!(status & CM_INTR))
1366 return IRQ_NONE;
1367
1368 /* acknowledge interrupt */
1369 spin_lock(&cm->reg_lock);
1370 if (status & CM_CHINT0)
1371 mask |= CM_CH0_INT_EN;
1372 if (status & CM_CHINT1)
1373 mask |= CM_CH1_INT_EN;
1374 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1375 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1376 spin_unlock(&cm->reg_lock);
1377
1378 if (cm->rmidi && (status & CM_UARTINT))
1379 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1380
1381 if (cm->pcm) {
1382 if ((status & CM_CHINT0) && cm->channel[0].running)
1383 snd_pcm_period_elapsed(cm->channel[0].substream);
1384 if ((status & CM_CHINT1) && cm->channel[1].running)
1385 snd_pcm_period_elapsed(cm->channel[1].substream);
1386 }
1387 return IRQ_HANDLED;
1388 }
1389
1390 /*
1391 * h/w infos
1392 */
1393
1394 /* playback on channel A */
1395 static struct snd_pcm_hardware snd_cmipci_playback =
1396 {
1397 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1398 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1399 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1400 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1401 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1402 .rate_min = 5512,
1403 .rate_max = 48000,
1404 .channels_min = 1,
1405 .channels_max = 2,
1406 .buffer_bytes_max = (128*1024),
1407 .period_bytes_min = 64,
1408 .period_bytes_max = (128*1024),
1409 .periods_min = 2,
1410 .periods_max = 1024,
1411 .fifo_size = 0,
1412 };
1413
1414 /* capture on channel B */
1415 static struct snd_pcm_hardware snd_cmipci_capture =
1416 {
1417 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1418 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1419 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1420 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1421 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1422 .rate_min = 5512,
1423 .rate_max = 48000,
1424 .channels_min = 1,
1425 .channels_max = 2,
1426 .buffer_bytes_max = (128*1024),
1427 .period_bytes_min = 64,
1428 .period_bytes_max = (128*1024),
1429 .periods_min = 2,
1430 .periods_max = 1024,
1431 .fifo_size = 0,
1432 };
1433
1434 /* playback on channel B - stereo 16bit only? */
1435 static struct snd_pcm_hardware snd_cmipci_playback2 =
1436 {
1437 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1438 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1439 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1440 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1441 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1442 .rate_min = 5512,
1443 .rate_max = 48000,
1444 .channels_min = 2,
1445 .channels_max = 2,
1446 .buffer_bytes_max = (128*1024),
1447 .period_bytes_min = 64,
1448 .period_bytes_max = (128*1024),
1449 .periods_min = 2,
1450 .periods_max = 1024,
1451 .fifo_size = 0,
1452 };
1453
1454 /* spdif playback on channel A */
1455 static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1456 {
1457 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1458 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1459 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1460 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1461 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1462 .rate_min = 44100,
1463 .rate_max = 48000,
1464 .channels_min = 2,
1465 .channels_max = 2,
1466 .buffer_bytes_max = (128*1024),
1467 .period_bytes_min = 64,
1468 .period_bytes_max = (128*1024),
1469 .periods_min = 2,
1470 .periods_max = 1024,
1471 .fifo_size = 0,
1472 };
1473
1474 /* spdif playback on channel A (32bit, IEC958 subframes) */
1475 static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1476 {
1477 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1478 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1479 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1480 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1481 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1482 .rate_min = 44100,
1483 .rate_max = 48000,
1484 .channels_min = 2,
1485 .channels_max = 2,
1486 .buffer_bytes_max = (128*1024),
1487 .period_bytes_min = 64,
1488 .period_bytes_max = (128*1024),
1489 .periods_min = 2,
1490 .periods_max = 1024,
1491 .fifo_size = 0,
1492 };
1493
1494 /* spdif capture on channel B */
1495 static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1496 {
1497 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1498 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1499 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1500 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1501 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1502 .rate_min = 44100,
1503 .rate_max = 48000,
1504 .channels_min = 2,
1505 .channels_max = 2,
1506 .buffer_bytes_max = (128*1024),
1507 .period_bytes_min = 64,
1508 .period_bytes_max = (128*1024),
1509 .periods_min = 2,
1510 .periods_max = 1024,
1511 .fifo_size = 0,
1512 };
1513
1514 /*
1515 * check device open/close
1516 */
1517 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1518 {
1519 int ch = mode & CM_OPEN_CH_MASK;
1520
1521 /* FIXME: a file should wait until the device becomes free
1522 * when it's opened on blocking mode. however, since the current
1523 * pcm framework doesn't pass file pointer before actually opened,
1524 * we can't know whether blocking mode or not in open callback..
1525 */
1526 mutex_lock(&cm->open_mutex);
1527 if (cm->opened[ch]) {
1528 mutex_unlock(&cm->open_mutex);
1529 return -EBUSY;
1530 }
1531 cm->opened[ch] = mode;
1532 cm->channel[ch].substream = subs;
1533 if (! (mode & CM_OPEN_DAC)) {
1534 /* disable dual DAC mode */
1535 cm->channel[ch].is_dac = 0;
1536 spin_lock_irq(&cm->reg_lock);
1537 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1538 spin_unlock_irq(&cm->reg_lock);
1539 }
1540 mutex_unlock(&cm->open_mutex);
1541 return 0;
1542 }
1543
1544 static void close_device_check(struct cmipci *cm, int mode)
1545 {
1546 int ch = mode & CM_OPEN_CH_MASK;
1547
1548 mutex_lock(&cm->open_mutex);
1549 if (cm->opened[ch] == mode) {
1550 if (cm->channel[ch].substream) {
1551 snd_cmipci_ch_reset(cm, ch);
1552 cm->channel[ch].running = 0;
1553 cm->channel[ch].substream = NULL;
1554 }
1555 cm->opened[ch] = 0;
1556 if (! cm->channel[ch].is_dac) {
1557 /* enable dual DAC mode again */
1558 cm->channel[ch].is_dac = 1;
1559 spin_lock_irq(&cm->reg_lock);
1560 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1561 spin_unlock_irq(&cm->reg_lock);
1562 }
1563 }
1564 mutex_unlock(&cm->open_mutex);
1565 }
1566
1567 /*
1568 */
1569
1570 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1571 {
1572 struct cmipci *cm = snd_pcm_substream_chip(substream);
1573 struct snd_pcm_runtime *runtime = substream->runtime;
1574 int err;
1575
1576 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1577 return err;
1578 runtime->hw = snd_cmipci_playback;
1579 if (cm->chip_version == 68) {
1580 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1581 SNDRV_PCM_RATE_96000;
1582 runtime->hw.rate_max = 96000;
1583 }
1584 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1585 cm->dig_pcm_status = cm->dig_status;
1586 return 0;
1587 }
1588
1589 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1590 {
1591 struct cmipci *cm = snd_pcm_substream_chip(substream);
1592 struct snd_pcm_runtime *runtime = substream->runtime;
1593 int err;
1594
1595 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1596 return err;
1597 runtime->hw = snd_cmipci_capture;
1598 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1599 runtime->hw.rate_min = 41000;
1600 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1601 }
1602 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1603 return 0;
1604 }
1605
1606 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1607 {
1608 struct cmipci *cm = snd_pcm_substream_chip(substream);
1609 struct snd_pcm_runtime *runtime = substream->runtime;
1610 int err;
1611
1612 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1613 return err;
1614 runtime->hw = snd_cmipci_playback2;
1615 mutex_lock(&cm->open_mutex);
1616 if (! cm->opened[CM_CH_PLAY]) {
1617 if (cm->can_multi_ch) {
1618 runtime->hw.channels_max = cm->max_channels;
1619 if (cm->max_channels == 4)
1620 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1621 else if (cm->max_channels == 6)
1622 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1623 else if (cm->max_channels == 8)
1624 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1625 }
1626 if (cm->chip_version == 68) {
1627 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1628 SNDRV_PCM_RATE_96000;
1629 runtime->hw.rate_max = 96000;
1630 }
1631 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1632 }
1633 mutex_unlock(&cm->open_mutex);
1634 return 0;
1635 }
1636
1637 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1638 {
1639 struct cmipci *cm = snd_pcm_substream_chip(substream);
1640 struct snd_pcm_runtime *runtime = substream->runtime;
1641 int err;
1642
1643 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1644 return err;
1645 if (cm->can_ac3_hw) {
1646 runtime->hw = snd_cmipci_playback_spdif;
1647 if (cm->chip_version >= 37) {
1648 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1649 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1650 }
1651 if (cm->chip_version == 68) {
1652 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1653 SNDRV_PCM_RATE_96000;
1654 runtime->hw.rate_max = 96000;
1655 }
1656 } else {
1657 runtime->hw = snd_cmipci_playback_iec958_subframe;
1658 }
1659 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1660 cm->dig_pcm_status = cm->dig_status;
1661 return 0;
1662 }
1663
1664 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1665 {
1666 struct cmipci *cm = snd_pcm_substream_chip(substream);
1667 struct snd_pcm_runtime *runtime = substream->runtime;
1668 int err;
1669
1670 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1671 return err;
1672 runtime->hw = snd_cmipci_capture_spdif;
1673 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1674 return 0;
1675 }
1676
1677
1678 /*
1679 */
1680
1681 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1682 {
1683 struct cmipci *cm = snd_pcm_substream_chip(substream);
1684 close_device_check(cm, CM_OPEN_PLAYBACK);
1685 return 0;
1686 }
1687
1688 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1689 {
1690 struct cmipci *cm = snd_pcm_substream_chip(substream);
1691 close_device_check(cm, CM_OPEN_CAPTURE);
1692 return 0;
1693 }
1694
1695 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1696 {
1697 struct cmipci *cm = snd_pcm_substream_chip(substream);
1698 close_device_check(cm, CM_OPEN_PLAYBACK2);
1699 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1700 return 0;
1701 }
1702
1703 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1704 {
1705 struct cmipci *cm = snd_pcm_substream_chip(substream);
1706 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1707 return 0;
1708 }
1709
1710 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1711 {
1712 struct cmipci *cm = snd_pcm_substream_chip(substream);
1713 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1714 return 0;
1715 }
1716
1717
1718 /*
1719 */
1720
1721 static struct snd_pcm_ops snd_cmipci_playback_ops = {
1722 .open = snd_cmipci_playback_open,
1723 .close = snd_cmipci_playback_close,
1724 .ioctl = snd_pcm_lib_ioctl,
1725 .hw_params = snd_cmipci_hw_params,
1726 .hw_free = snd_cmipci_playback_hw_free,
1727 .prepare = snd_cmipci_playback_prepare,
1728 .trigger = snd_cmipci_playback_trigger,
1729 .pointer = snd_cmipci_playback_pointer,
1730 };
1731
1732 static struct snd_pcm_ops snd_cmipci_capture_ops = {
1733 .open = snd_cmipci_capture_open,
1734 .close = snd_cmipci_capture_close,
1735 .ioctl = snd_pcm_lib_ioctl,
1736 .hw_params = snd_cmipci_hw_params,
1737 .hw_free = snd_cmipci_hw_free,
1738 .prepare = snd_cmipci_capture_prepare,
1739 .trigger = snd_cmipci_capture_trigger,
1740 .pointer = snd_cmipci_capture_pointer,
1741 };
1742
1743 static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1744 .open = snd_cmipci_playback2_open,
1745 .close = snd_cmipci_playback2_close,
1746 .ioctl = snd_pcm_lib_ioctl,
1747 .hw_params = snd_cmipci_playback2_hw_params,
1748 .hw_free = snd_cmipci_hw_free,
1749 .prepare = snd_cmipci_capture_prepare, /* channel B */
1750 .trigger = snd_cmipci_capture_trigger, /* channel B */
1751 .pointer = snd_cmipci_capture_pointer, /* channel B */
1752 };
1753
1754 static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1755 .open = snd_cmipci_playback_spdif_open,
1756 .close = snd_cmipci_playback_spdif_close,
1757 .ioctl = snd_pcm_lib_ioctl,
1758 .hw_params = snd_cmipci_hw_params,
1759 .hw_free = snd_cmipci_playback_hw_free,
1760 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1761 .trigger = snd_cmipci_playback_trigger,
1762 .pointer = snd_cmipci_playback_pointer,
1763 };
1764
1765 static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1766 .open = snd_cmipci_capture_spdif_open,
1767 .close = snd_cmipci_capture_spdif_close,
1768 .ioctl = snd_pcm_lib_ioctl,
1769 .hw_params = snd_cmipci_hw_params,
1770 .hw_free = snd_cmipci_capture_spdif_hw_free,
1771 .prepare = snd_cmipci_capture_spdif_prepare,
1772 .trigger = snd_cmipci_capture_trigger,
1773 .pointer = snd_cmipci_capture_pointer,
1774 };
1775
1776
1777 /*
1778 */
1779
1780 static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device)
1781 {
1782 struct snd_pcm *pcm;
1783 int err;
1784
1785 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1786 if (err < 0)
1787 return err;
1788
1789 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1790 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1791
1792 pcm->private_data = cm;
1793 pcm->info_flags = 0;
1794 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1795 cm->pcm = pcm;
1796
1797 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1798 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1799
1800 return 0;
1801 }
1802
1803 static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1804 {
1805 struct snd_pcm *pcm;
1806 int err;
1807
1808 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1809 if (err < 0)
1810 return err;
1811
1812 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1813
1814 pcm->private_data = cm;
1815 pcm->info_flags = 0;
1816 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1817 cm->pcm2 = pcm;
1818
1819 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1820 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1821
1822 return 0;
1823 }
1824
1825 static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1826 {
1827 struct snd_pcm *pcm;
1828 int err;
1829
1830 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1831 if (err < 0)
1832 return err;
1833
1834 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1835 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1836
1837 pcm->private_data = cm;
1838 pcm->info_flags = 0;
1839 strcpy(pcm->name, "C-Media PCI IEC958");
1840 cm->pcm_spdif = pcm;
1841
1842 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1843 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1844
1845 return 0;
1846 }
1847
1848 /*
1849 * mixer interface:
1850 * - CM8338/8738 has a compatible mixer interface with SB16, but
1851 * lack of some elements like tone control, i/o gain and AGC.
1852 * - Access to native registers:
1853 * - A 3D switch
1854 * - Output mute switches
1855 */
1856
1857 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1858 {
1859 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1860 outb(data, s->iobase + CM_REG_SB16_DATA);
1861 }
1862
1863 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1864 {
1865 unsigned char v;
1866
1867 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1868 v = inb(s->iobase + CM_REG_SB16_DATA);
1869 return v;
1870 }
1871
1872 /*
1873 * general mixer element
1874 */
1875 struct cmipci_sb_reg {
1876 unsigned int left_reg, right_reg;
1877 unsigned int left_shift, right_shift;
1878 unsigned int mask;
1879 unsigned int invert: 1;
1880 unsigned int stereo: 1;
1881 };
1882
1883 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1884 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1885
1886 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1887 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1888 .info = snd_cmipci_info_volume, \
1889 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1890 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1891 }
1892
1893 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1894 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1895 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1896 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1897
1898 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1899 {
1900 r->left_reg = val & 0xff;
1901 r->right_reg = (val >> 8) & 0xff;
1902 r->left_shift = (val >> 16) & 0x07;
1903 r->right_shift = (val >> 19) & 0x07;
1904 r->invert = (val >> 22) & 1;
1905 r->stereo = (val >> 23) & 1;
1906 r->mask = (val >> 24) & 0xff;
1907 }
1908
1909 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
1910 struct snd_ctl_elem_info *uinfo)
1911 {
1912 struct cmipci_sb_reg reg;
1913
1914 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1915 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1916 uinfo->count = reg.stereo + 1;
1917 uinfo->value.integer.min = 0;
1918 uinfo->value.integer.max = reg.mask;
1919 return 0;
1920 }
1921
1922 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
1923 struct snd_ctl_elem_value *ucontrol)
1924 {
1925 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1926 struct cmipci_sb_reg reg;
1927 int val;
1928
1929 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1930 spin_lock_irq(&cm->reg_lock);
1931 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1932 if (reg.invert)
1933 val = reg.mask - val;
1934 ucontrol->value.integer.value[0] = val;
1935 if (reg.stereo) {
1936 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1937 if (reg.invert)
1938 val = reg.mask - val;
1939 ucontrol->value.integer.value[1] = val;
1940 }
1941 spin_unlock_irq(&cm->reg_lock);
1942 return 0;
1943 }
1944
1945 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
1946 struct snd_ctl_elem_value *ucontrol)
1947 {
1948 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1949 struct cmipci_sb_reg reg;
1950 int change;
1951 int left, right, oleft, oright;
1952
1953 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1954 left = ucontrol->value.integer.value[0] & reg.mask;
1955 if (reg.invert)
1956 left = reg.mask - left;
1957 left <<= reg.left_shift;
1958 if (reg.stereo) {
1959 right = ucontrol->value.integer.value[1] & reg.mask;
1960 if (reg.invert)
1961 right = reg.mask - right;
1962 right <<= reg.right_shift;
1963 } else
1964 right = 0;
1965 spin_lock_irq(&cm->reg_lock);
1966 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
1967 left |= oleft & ~(reg.mask << reg.left_shift);
1968 change = left != oleft;
1969 if (reg.stereo) {
1970 if (reg.left_reg != reg.right_reg) {
1971 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1972 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
1973 } else
1974 oright = left;
1975 right |= oright & ~(reg.mask << reg.right_shift);
1976 change |= right != oright;
1977 snd_cmipci_mixer_write(cm, reg.right_reg, right);
1978 } else
1979 snd_cmipci_mixer_write(cm, reg.left_reg, left);
1980 spin_unlock_irq(&cm->reg_lock);
1981 return change;
1982 }
1983
1984 /*
1985 * input route (left,right) -> (left,right)
1986 */
1987 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1988 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1989 .info = snd_cmipci_info_input_sw, \
1990 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1991 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1992 }
1993
1994 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
1995 struct snd_ctl_elem_info *uinfo)
1996 {
1997 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1998 uinfo->count = 4;
1999 uinfo->value.integer.min = 0;
2000 uinfo->value.integer.max = 1;
2001 return 0;
2002 }
2003
2004 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2005 struct snd_ctl_elem_value *ucontrol)
2006 {
2007 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2008 struct cmipci_sb_reg reg;
2009 int val1, val2;
2010
2011 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2012 spin_lock_irq(&cm->reg_lock);
2013 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2014 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2015 spin_unlock_irq(&cm->reg_lock);
2016 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2017 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2018 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2019 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2020 return 0;
2021 }
2022
2023 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2024 struct snd_ctl_elem_value *ucontrol)
2025 {
2026 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2027 struct cmipci_sb_reg reg;
2028 int change;
2029 int val1, val2, oval1, oval2;
2030
2031 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2032 spin_lock_irq(&cm->reg_lock);
2033 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2034 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2035 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2036 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2037 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2038 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2039 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2040 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2041 change = val1 != oval1 || val2 != oval2;
2042 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2043 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2044 spin_unlock_irq(&cm->reg_lock);
2045 return change;
2046 }
2047
2048 /*
2049 * native mixer switches/volumes
2050 */
2051
2052 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2053 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2054 .info = snd_cmipci_info_native_mixer, \
2055 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2056 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2057 }
2058
2059 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2060 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2061 .info = snd_cmipci_info_native_mixer, \
2062 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2063 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2064 }
2065
2066 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2067 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2068 .info = snd_cmipci_info_native_mixer, \
2069 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2070 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2071 }
2072
2073 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2074 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2075 .info = snd_cmipci_info_native_mixer, \
2076 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2077 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2078 }
2079
2080 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2081 struct snd_ctl_elem_info *uinfo)
2082 {
2083 struct cmipci_sb_reg reg;
2084
2085 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2086 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2087 uinfo->count = reg.stereo + 1;
2088 uinfo->value.integer.min = 0;
2089 uinfo->value.integer.max = reg.mask;
2090 return 0;
2091
2092 }
2093
2094 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2095 struct snd_ctl_elem_value *ucontrol)
2096 {
2097 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2098 struct cmipci_sb_reg reg;
2099 unsigned char oreg, val;
2100
2101 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2102 spin_lock_irq(&cm->reg_lock);
2103 oreg = inb(cm->iobase + reg.left_reg);
2104 val = (oreg >> reg.left_shift) & reg.mask;
2105 if (reg.invert)
2106 val = reg.mask - val;
2107 ucontrol->value.integer.value[0] = val;
2108 if (reg.stereo) {
2109 val = (oreg >> reg.right_shift) & reg.mask;
2110 if (reg.invert)
2111 val = reg.mask - val;
2112 ucontrol->value.integer.value[1] = val;
2113 }
2114 spin_unlock_irq(&cm->reg_lock);
2115 return 0;
2116 }
2117
2118 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2119 struct snd_ctl_elem_value *ucontrol)
2120 {
2121 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2122 struct cmipci_sb_reg reg;
2123 unsigned char oreg, nreg, val;
2124
2125 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2126 spin_lock_irq(&cm->reg_lock);
2127 oreg = inb(cm->iobase + reg.left_reg);
2128 val = ucontrol->value.integer.value[0] & reg.mask;
2129 if (reg.invert)
2130 val = reg.mask - val;
2131 nreg = oreg & ~(reg.mask << reg.left_shift);
2132 nreg |= (val << reg.left_shift);
2133 if (reg.stereo) {
2134 val = ucontrol->value.integer.value[1] & reg.mask;
2135 if (reg.invert)
2136 val = reg.mask - val;
2137 nreg &= ~(reg.mask << reg.right_shift);
2138 nreg |= (val << reg.right_shift);
2139 }
2140 outb(nreg, cm->iobase + reg.left_reg);
2141 spin_unlock_irq(&cm->reg_lock);
2142 return (nreg != oreg);
2143 }
2144
2145 /*
2146 * special case - check mixer sensitivity
2147 */
2148 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2149 struct snd_ctl_elem_value *ucontrol)
2150 {
2151 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2152 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2153 }
2154
2155 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2156 struct snd_ctl_elem_value *ucontrol)
2157 {
2158 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2159 if (cm->mixer_insensitive) {
2160 /* ignored */
2161 return 0;
2162 }
2163 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2164 }
2165
2166
2167 static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = {
2168 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2169 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2170 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2171 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2172 { /* switch with sensitivity */
2173 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2174 .name = "PCM Playback Switch",
2175 .info = snd_cmipci_info_native_mixer,
2176 .get = snd_cmipci_get_native_mixer_sensitive,
2177 .put = snd_cmipci_put_native_mixer_sensitive,
2178 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2179 },
2180 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2181 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2182 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2183 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2184 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2185 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2186 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2187 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2188 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2189 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2190 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2191 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2192 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2193 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2194 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2195 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2196 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2197 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2198 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2199 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2200 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2201 CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2202 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2203 };
2204
2205 /*
2206 * other switches
2207 */
2208
2209 struct cmipci_switch_args {
2210 int reg; /* register index */
2211 unsigned int mask; /* mask bits */
2212 unsigned int mask_on; /* mask bits to turn on */
2213 unsigned int is_byte: 1; /* byte access? */
2214 unsigned int ac3_sensitive: 1; /* access forbidden during
2215 * non-audio operation?
2216 */
2217 };
2218
2219 #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2220
2221 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2222 struct snd_ctl_elem_value *ucontrol,
2223 struct cmipci_switch_args *args)
2224 {
2225 unsigned int val;
2226 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2227
2228 spin_lock_irq(&cm->reg_lock);
2229 if (args->ac3_sensitive && cm->mixer_insensitive) {
2230 ucontrol->value.integer.value[0] = 0;
2231 spin_unlock_irq(&cm->reg_lock);
2232 return 0;
2233 }
2234 if (args->is_byte)
2235 val = inb(cm->iobase + args->reg);
2236 else
2237 val = snd_cmipci_read(cm, args->reg);
2238 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2239 spin_unlock_irq(&cm->reg_lock);
2240 return 0;
2241 }
2242
2243 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2244 struct snd_ctl_elem_value *ucontrol)
2245 {
2246 struct cmipci_switch_args *args;
2247 args = (struct cmipci_switch_args *)kcontrol->private_value;
2248 snd_assert(args != NULL, return -EINVAL);
2249 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2250 }
2251
2252 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2253 struct snd_ctl_elem_value *ucontrol,
2254 struct cmipci_switch_args *args)
2255 {
2256 unsigned int val;
2257 int change;
2258 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2259
2260 spin_lock_irq(&cm->reg_lock);
2261 if (args->ac3_sensitive && cm->mixer_insensitive) {
2262 /* ignored */
2263 spin_unlock_irq(&cm->reg_lock);
2264 return 0;
2265 }
2266 if (args->is_byte)
2267 val = inb(cm->iobase + args->reg);
2268 else
2269 val = snd_cmipci_read(cm, args->reg);
2270 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2271 args->mask_on : (args->mask & ~args->mask_on));
2272 if (change) {
2273 val &= ~args->mask;
2274 if (ucontrol->value.integer.value[0])
2275 val |= args->mask_on;
2276 else
2277 val |= (args->mask & ~args->mask_on);
2278 if (args->is_byte)
2279 outb((unsigned char)val, cm->iobase + args->reg);
2280 else
2281 snd_cmipci_write(cm, args->reg, val);
2282 }
2283 spin_unlock_irq(&cm->reg_lock);
2284 return change;
2285 }
2286
2287 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2288 struct snd_ctl_elem_value *ucontrol)
2289 {
2290 struct cmipci_switch_args *args;
2291 args = (struct cmipci_switch_args *)kcontrol->private_value;
2292 snd_assert(args != NULL, return -EINVAL);
2293 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2294 }
2295
2296 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2297 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2298 .reg = xreg, \
2299 .mask = xmask, \
2300 .mask_on = xmask_on, \
2301 .is_byte = xis_byte, \
2302 .ac3_sensitive = xac3, \
2303 }
2304
2305 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2306 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2307
2308 #if 0 /* these will be controlled in pcm device */
2309 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2310 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2311 #endif
2312 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2313 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2314 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2315 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2316 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2317 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2318 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2319 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2320 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2321 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2322 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2323 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2324 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2325 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2326 #if CM_CH_PLAY == 1
2327 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2328 #else
2329 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2330 #endif
2331 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2332 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2333 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2334 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2335 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2336
2337 #define DEFINE_SWITCH(sname, stype, sarg) \
2338 { .name = sname, \
2339 .iface = stype, \
2340 .info = snd_cmipci_uswitch_info, \
2341 .get = snd_cmipci_uswitch_get, \
2342 .put = snd_cmipci_uswitch_put, \
2343 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2344 }
2345
2346 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2347 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2348
2349
2350 /*
2351 * callbacks for spdif output switch
2352 * needs toggle two registers..
2353 */
2354 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2355 struct snd_ctl_elem_value *ucontrol)
2356 {
2357 int changed;
2358 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2359 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2360 return changed;
2361 }
2362
2363 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2364 struct snd_ctl_elem_value *ucontrol)
2365 {
2366 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2367 int changed;
2368 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2369 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2370 if (changed) {
2371 if (ucontrol->value.integer.value[0]) {
2372 if (chip->spdif_playback_avail)
2373 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2374 } else {
2375 if (chip->spdif_playback_avail)
2376 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2377 }
2378 }
2379 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2380 return changed;
2381 }
2382
2383
2384 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2385 struct snd_ctl_elem_info *uinfo)
2386 {
2387 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2388 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2389 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2390 uinfo->count = 1;
2391 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2392 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2393 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2394 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2395 return 0;
2396 }
2397
2398 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2399 {
2400 unsigned int val;
2401 if (cm->chip_version >= 39) {
2402 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2403 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2404 return 2;
2405 }
2406 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2407 if (val & CM_REAR2LIN)
2408 return 1;
2409 return 0;
2410 }
2411
2412 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2413 struct snd_ctl_elem_value *ucontrol)
2414 {
2415 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2416
2417 spin_lock_irq(&cm->reg_lock);
2418 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2419 spin_unlock_irq(&cm->reg_lock);
2420 return 0;
2421 }
2422
2423 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2424 struct snd_ctl_elem_value *ucontrol)
2425 {
2426 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2427 int change;
2428
2429 spin_lock_irq(&cm->reg_lock);
2430 if (ucontrol->value.enumerated.item[0] == 2)
2431 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2432 else
2433 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2434 if (ucontrol->value.enumerated.item[0] == 1)
2435 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2436 else
2437 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2438 spin_unlock_irq(&cm->reg_lock);
2439 return change;
2440 }
2441
2442 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2443 struct snd_ctl_elem_info *uinfo)
2444 {
2445 static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2446 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2447 uinfo->count = 1;
2448 uinfo->value.enumerated.items = 2;
2449 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2450 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2451 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2452 return 0;
2453 }
2454
2455 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2456 struct snd_ctl_elem_value *ucontrol)
2457 {
2458 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2459 /* same bit as spdi_phase */
2460 spin_lock_irq(&cm->reg_lock);
2461 ucontrol->value.enumerated.item[0] =
2462 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2463 spin_unlock_irq(&cm->reg_lock);
2464 return 0;
2465 }
2466
2467 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2468 struct snd_ctl_elem_value *ucontrol)
2469 {
2470 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2471 int change;
2472
2473 spin_lock_irq(&cm->reg_lock);
2474 if (ucontrol->value.enumerated.item[0])
2475 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2476 else
2477 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2478 spin_unlock_irq(&cm->reg_lock);
2479 return change;
2480 }
2481
2482 /* both for CM8338/8738 */
2483 static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = {
2484 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2485 {
2486 .name = "Line-In Mode",
2487 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2488 .info = snd_cmipci_line_in_mode_info,
2489 .get = snd_cmipci_line_in_mode_get,
2490 .put = snd_cmipci_line_in_mode_put,
2491 },
2492 };
2493
2494 /* for non-multichannel chips */
2495 static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata =
2496 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2497
2498 /* only for CM8738 */
2499 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = {
2500 #if 0 /* controlled in pcm device */
2501 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2502 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2503 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2504 #endif
2505 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2506 { .name = "IEC958 Output Switch",
2507 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2508 .info = snd_cmipci_uswitch_info,
2509 .get = snd_cmipci_spdout_enable_get,
2510 .put = snd_cmipci_spdout_enable_put,
2511 },
2512 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2513 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2514 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2515 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2516 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2517 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2518 };
2519
2520 /* only for model 033/037 */
2521 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = {
2522 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2523 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2524 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2525 };
2526
2527 /* only for model 039 or later */
2528 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = {
2529 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2530 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2531 {
2532 .name = "Mic-In Mode",
2533 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2534 .info = snd_cmipci_mic_in_mode_info,
2535 .get = snd_cmipci_mic_in_mode_get,
2536 .put = snd_cmipci_mic_in_mode_put,
2537 }
2538 };
2539
2540 /* card control switches */
2541 static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = {
2542 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2543 DEFINE_CARD_SWITCH("Modem", modem),
2544 };
2545
2546
2547 static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2548 {
2549 struct snd_card *card;
2550 struct snd_kcontrol_new *sw;
2551 struct snd_kcontrol *kctl;
2552 unsigned int idx;
2553 int err;
2554
2555 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2556
2557 card = cm->card;
2558
2559 strcpy(card->mixername, "CMedia PCI");
2560
2561 spin_lock_irq(&cm->reg_lock);
2562 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2563 spin_unlock_irq(&cm->reg_lock);
2564
2565 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2566 if (cm->chip_version == 68) { // 8768 has no PCM volume
2567 if (!strcmp(snd_cmipci_mixers[idx].name,
2568 "PCM Playback Volume"))
2569 continue;
2570 }
2571 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2572 return err;
2573 }
2574
2575 /* mixer switches */
2576 sw = snd_cmipci_mixer_switches;
2577 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2578 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2579 if (err < 0)
2580 return err;
2581 }
2582 if (! cm->can_multi_ch) {
2583 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2584 if (err < 0)
2585 return err;
2586 }
2587 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2588 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2589 sw = snd_cmipci_8738_mixer_switches;
2590 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2591 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2592 if (err < 0)
2593 return err;
2594 }
2595 if (cm->can_ac3_hw) {
2596 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2597 return err;
2598 kctl->id.device = pcm_spdif_device;
2599 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2600 return err;
2601 kctl->id.device = pcm_spdif_device;
2602 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2603 return err;
2604 kctl->id.device = pcm_spdif_device;
2605 }
2606 if (cm->chip_version <= 37) {
2607 sw = snd_cmipci_old_mixer_switches;
2608 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2609 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2610 if (err < 0)
2611 return err;
2612 }
2613 }
2614 }
2615 if (cm->chip_version >= 39) {
2616 sw = snd_cmipci_extra_mixer_switches;
2617 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2618 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2619 if (err < 0)
2620 return err;
2621 }
2622 }
2623
2624 /* card switches */
2625 sw = snd_cmipci_control_switches;
2626 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2627 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2628 if (err < 0)
2629 return err;
2630 }
2631
2632 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2633 struct snd_ctl_elem_id id;
2634 struct snd_kcontrol *ctl;
2635 memset(&id, 0, sizeof(id));
2636 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2637 strcpy(id.name, cm_saved_mixer[idx].name);
2638 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2639 cm->mixer_res_ctl[idx] = ctl;
2640 }
2641
2642 return 0;
2643 }
2644
2645
2646 /*
2647 * proc interface
2648 */
2649
2650 #ifdef CONFIG_PROC_FS
2651 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2652 struct snd_info_buffer *buffer)
2653 {
2654 struct cmipci *cm = entry->private_data;
2655 int i;
2656
2657 snd_iprintf(buffer, "%s\n\n", cm->card->longname);
2658 for (i = 0; i < 0x40; i++) {
2659 int v = inb(cm->iobase + i);
2660 if (i % 4 == 0)
2661 snd_iprintf(buffer, "%02x: ", i);
2662 snd_iprintf(buffer, "%02x", v);
2663 if (i % 4 == 3)
2664 snd_iprintf(buffer, "\n");
2665 else
2666 snd_iprintf(buffer, " ");
2667 }
2668 }
2669
2670 static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
2671 {
2672 struct snd_info_entry *entry;
2673
2674 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2675 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read);
2676 }
2677 #else /* !CONFIG_PROC_FS */
2678 static inline void snd_cmipci_proc_init(struct cmipci *cm) {}
2679 #endif
2680
2681
2682 static struct pci_device_id snd_cmipci_ids[] = {
2683 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2684 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2685 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2686 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2687 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2688 {0,},
2689 };
2690
2691
2692 /*
2693 * check chip version and capabilities
2694 * driver name is modified according to the chip model
2695 */
2696 static void __devinit query_chip(struct cmipci *cm)
2697 {
2698 unsigned int detect;
2699
2700 /* check reg 0Ch, bit 24-31 */
2701 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2702 if (! detect) {
2703 /* check reg 08h, bit 24-28 */
2704 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2705 switch (detect) {
2706 case 0:
2707 cm->chip_version = 33;
2708 if (cm->do_soft_ac3)
2709 cm->can_ac3_sw = 1;
2710 else
2711 cm->can_ac3_hw = 1;
2712 break;
2713 case CM_CHIP_037:
2714 cm->chip_version = 37;
2715 cm->can_ac3_hw = 1;
2716 break;
2717 default:
2718 cm->chip_version = 39;
2719 cm->can_ac3_hw = 1;
2720 break;
2721 }
2722 cm->max_channels = 2;
2723 } else {
2724 if (detect & CM_CHIP_039) {
2725 cm->chip_version = 39;
2726 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2727 cm->max_channels = 6;
2728 else
2729 cm->max_channels = 4;
2730 } else if (detect & CM_CHIP_8768) {
2731 cm->chip_version = 68;
2732 cm->max_channels = 8;
2733 } else {
2734 cm->chip_version = 55;
2735 cm->max_channels = 6;
2736 }
2737 cm->can_ac3_hw = 1;
2738 cm->can_multi_ch = 1;
2739 }
2740 }
2741
2742 #ifdef SUPPORT_JOYSTICK
2743 static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2744 {
2745 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2746 struct gameport *gp;
2747 struct resource *r = NULL;
2748 int i, io_port = 0;
2749
2750 if (joystick_port[dev] == 0)
2751 return -ENODEV;
2752
2753 if (joystick_port[dev] == 1) { /* auto-detect */
2754 for (i = 0; ports[i]; i++) {
2755 io_port = ports[i];
2756 r = request_region(io_port, 1, "CMIPCI gameport");
2757 if (r)
2758 break;
2759 }
2760 } else {
2761 io_port = joystick_port[dev];
2762 r = request_region(io_port, 1, "CMIPCI gameport");
2763 }
2764
2765 if (!r) {
2766 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2767 return -EBUSY;
2768 }
2769
2770 cm->gameport = gp = gameport_allocate_port();
2771 if (!gp) {
2772 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2773 release_and_free_resource(r);
2774 return -ENOMEM;
2775 }
2776 gameport_set_name(gp, "C-Media Gameport");
2777 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2778 gameport_set_dev_parent(gp, &cm->pci->dev);
2779 gp->io = io_port;
2780 gameport_set_port_data(gp, r);
2781
2782 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2783
2784 gameport_register_port(cm->gameport);
2785
2786 return 0;
2787 }
2788
2789 static void snd_cmipci_free_gameport(struct cmipci *cm)
2790 {
2791 if (cm->gameport) {
2792 struct resource *r = gameport_get_port_data(cm->gameport);
2793
2794 gameport_unregister_port(cm->gameport);
2795 cm->gameport = NULL;
2796
2797 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2798 release_and_free_resource(r);
2799 }
2800 }
2801 #else
2802 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2803 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2804 #endif
2805
2806 static int snd_cmipci_free(struct cmipci *cm)
2807 {
2808 if (cm->irq >= 0) {
2809 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2810 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2811 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2812 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2813 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2814 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2815 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2816
2817 /* reset mixer */
2818 snd_cmipci_mixer_write(cm, 0, 0);
2819
2820 synchronize_irq(cm->irq);
2821
2822 free_irq(cm->irq, cm);
2823 }
2824
2825 snd_cmipci_free_gameport(cm);
2826 pci_release_regions(cm->pci);
2827 pci_disable_device(cm->pci);
2828 kfree(cm);
2829 return 0;
2830 }
2831
2832 static int snd_cmipci_dev_free(struct snd_device *device)
2833 {
2834 struct cmipci *cm = device->device_data;
2835 return snd_cmipci_free(cm);
2836 }
2837
2838 static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2839 {
2840 long iosynth;
2841 unsigned int val;
2842 struct snd_opl3 *opl3;
2843 int err;
2844
2845 if (!fm_port)
2846 goto disable_fm;
2847
2848 if (cm->chip_version >= 39) {
2849 /* first try FM regs in PCI port range */
2850 iosynth = cm->iobase + CM_REG_FM_PCI;
2851 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2852 OPL3_HW_OPL3, 1, &opl3);
2853 } else {
2854 err = -EIO;
2855 }
2856 if (err < 0) {
2857 /* then try legacy ports */
2858 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2859 iosynth = fm_port;
2860 switch (iosynth) {
2861 case 0x3E8: val |= CM_FMSEL_3E8; break;
2862 case 0x3E0: val |= CM_FMSEL_3E0; break;
2863 case 0x3C8: val |= CM_FMSEL_3C8; break;
2864 case 0x388: val |= CM_FMSEL_388; break;
2865 default:
2866 goto disable_fm;
2867 }
2868 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2869 /* enable FM */
2870 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2871
2872 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2873 OPL3_HW_OPL3, 0, &opl3) < 0) {
2874 printk(KERN_ERR "cmipci: no OPL device at %#lx, "
2875 "skipping...\n", iosynth);
2876 goto disable_fm;
2877 }
2878 }
2879 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2880 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2881 return err;
2882 }
2883 return 0;
2884
2885 disable_fm:
2886 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2887 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2888 return 0;
2889 }
2890
2891 static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2892 int dev, struct cmipci **rcmipci)
2893 {
2894 struct cmipci *cm;
2895 int err;
2896 static struct snd_device_ops ops = {
2897 .dev_free = snd_cmipci_dev_free,
2898 };
2899 unsigned int val;
2900 long iomidi;
2901 int integrated_midi = 0;
2902 char modelstr[16];
2903 int pcm_index, pcm_spdif_index;
2904 static struct pci_device_id intel_82437vx[] = {
2905 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2906 { },
2907 };
2908
2909 *rcmipci = NULL;
2910
2911 if ((err = pci_enable_device(pci)) < 0)
2912 return err;
2913
2914 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
2915 if (cm == NULL) {
2916 pci_disable_device(pci);
2917 return -ENOMEM;
2918 }
2919
2920 spin_lock_init(&cm->reg_lock);
2921 mutex_init(&cm->open_mutex);
2922 cm->device = pci->device;
2923 cm->card = card;
2924 cm->pci = pci;
2925 cm->irq = -1;
2926 cm->channel[0].ch = 0;
2927 cm->channel[1].ch = 1;
2928 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2929
2930 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2931 kfree(cm);
2932 pci_disable_device(pci);
2933 return err;
2934 }
2935 cm->iobase = pci_resource_start(pci, 0);
2936
2937 if (request_irq(pci->irq, snd_cmipci_interrupt,
2938 IRQF_SHARED, card->driver, cm)) {
2939 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2940 snd_cmipci_free(cm);
2941 return -EBUSY;
2942 }
2943 cm->irq = pci->irq;
2944
2945 pci_set_master(cm->pci);
2946
2947 /*
2948 * check chip version, max channels and capabilities
2949 */
2950
2951 cm->chip_version = 0;
2952 cm->max_channels = 2;
2953 cm->do_soft_ac3 = soft_ac3[dev];
2954
2955 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
2956 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
2957 query_chip(cm);
2958 /* added -MCx suffix for chip supporting multi-channels */
2959 if (cm->can_multi_ch)
2960 sprintf(cm->card->driver + strlen(cm->card->driver),
2961 "-MC%d", cm->max_channels);
2962 else if (cm->can_ac3_sw)
2963 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
2964
2965 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2966 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2967
2968 #if CM_CH_PLAY == 1
2969 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
2970 #else
2971 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
2972 #endif
2973
2974 /* initialize codec registers */
2975 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2976 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2977 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2978 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2979 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2980
2981 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
2982 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
2983 #if CM_CH_PLAY == 1
2984 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2985 #else
2986 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
2987 #endif
2988 /* Set Bus Master Request */
2989 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
2990
2991 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2992 switch (pci->device) {
2993 case PCI_DEVICE_ID_CMEDIA_CM8738:
2994 case PCI_DEVICE_ID_CMEDIA_CM8738B:
2995 if (!pci_dev_present(intel_82437vx))
2996 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
2997 break;
2998 default:
2999 break;
3000 }
3001
3002 if (cm->chip_version < 68) {
3003 val = pci->device < 0x110 ? 8338 : 8738;
3004 } else {
3005 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3006 case 0:
3007 val = 8769;
3008 break;
3009 case 2:
3010 val = 8762;
3011 break;
3012 default:
3013 switch ((pci->subsystem_vendor << 16) |
3014 pci->subsystem_device) {
3015 case 0x13f69761:
3016 case 0x584d3741:
3017 case 0x584d3751:
3018 case 0x584d3761:
3019 case 0x584d3771:
3020 case 0x72848384:
3021 val = 8770;
3022 break;
3023 default:
3024 val = 8768;
3025 break;
3026 }
3027 }
3028 }
3029 sprintf(card->shortname, "C-Media CMI%d", val);
3030 if (cm->chip_version < 68)
3031 sprintf(modelstr, " (model %d)", cm->chip_version);
3032 else
3033 modelstr[0] = '\0';
3034 sprintf(card->longname, "%s%s at %#lx, irq %i",
3035 card->shortname, modelstr, cm->iobase, cm->irq);
3036
3037 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3038 snd_cmipci_free(cm);
3039 return err;
3040 }
3041
3042 if (cm->chip_version >= 39) {
3043 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3044 if (val != 0x00 && val != 0xff) {
3045 iomidi = cm->iobase + CM_REG_MPU_PCI;
3046 integrated_midi = 1;
3047 }
3048 }
3049 if (!integrated_midi) {
3050 val = 0;
3051 iomidi = mpu_port[dev];
3052 switch (iomidi) {
3053 case 0x320: val = CM_VMPU_320; break;
3054 case 0x310: val = CM_VMPU_310; break;
3055 case 0x300: val = CM_VMPU_300; break;
3056 case 0x330: val = CM_VMPU_330; break;
3057 default:
3058 iomidi = 0; break;
3059 }
3060 if (iomidi > 0) {
3061 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3062 /* enable UART */
3063 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3064 if (inb(iomidi + 1) == 0xff) {
3065 snd_printk(KERN_ERR "cannot enable MPU-401 port"
3066 " at %#lx\n", iomidi);
3067 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3068 CM_UART_EN);
3069 iomidi = 0;
3070 }
3071 }
3072 }
3073
3074 if (cm->chip_version < 68) {
3075 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3076 if (err < 0)
3077 return err;
3078 }
3079
3080 /* reset mixer */
3081 snd_cmipci_mixer_write(cm, 0, 0);
3082
3083 snd_cmipci_proc_init(cm);
3084
3085 /* create pcm devices */
3086 pcm_index = pcm_spdif_index = 0;
3087 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3088 return err;
3089 pcm_index++;
3090 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3091 return err;
3092 pcm_index++;
3093 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3094 pcm_spdif_index = pcm_index;
3095 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3096 return err;
3097 }
3098
3099 /* create mixer interface & switches */
3100 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3101 return err;
3102
3103 if (iomidi > 0) {
3104 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3105 iomidi,
3106 (integrated_midi ?
3107 MPU401_INFO_INTEGRATED : 0),
3108 cm->irq, 0, &cm->rmidi)) < 0) {
3109 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
3110 }
3111 }
3112
3113 #ifdef USE_VAR48KRATE
3114 for (val = 0; val < ARRAY_SIZE(rates); val++)
3115 snd_cmipci_set_pll(cm, rates[val], val);
3116
3117 /*
3118 * (Re-)Enable external switch spdo_48k
3119 */
3120 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3121 #endif /* USE_VAR48KRATE */
3122
3123 if (snd_cmipci_create_gameport(cm, dev) < 0)
3124 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3125
3126 snd_card_set_dev(card, &pci->dev);
3127
3128 *rcmipci = cm;
3129 return 0;
3130 }
3131
3132 /*
3133 */
3134
3135 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3136
3137 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3138 const struct pci_device_id *pci_id)
3139 {
3140 static int dev;
3141 struct snd_card *card;
3142 struct cmipci *cm;
3143 int err;
3144
3145 if (dev >= SNDRV_CARDS)
3146 return -ENODEV;
3147 if (! enable[dev]) {
3148 dev++;
3149 return -ENOENT;
3150 }
3151
3152 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3153 if (card == NULL)
3154 return -ENOMEM;
3155
3156 switch (pci->device) {
3157 case PCI_DEVICE_ID_CMEDIA_CM8738:
3158 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3159 strcpy(card->driver, "CMI8738");
3160 break;
3161 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3162 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3163 strcpy(card->driver, "CMI8338");
3164 break;
3165 default:
3166 strcpy(card->driver, "CMIPCI");
3167 break;
3168 }
3169
3170 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3171 snd_card_free(card);
3172 return err;
3173 }
3174 card->private_data = cm;
3175
3176 if ((err = snd_card_register(card)) < 0) {
3177 snd_card_free(card);
3178 return err;
3179 }
3180 pci_set_drvdata(pci, card);
3181 dev++;
3182 return 0;
3183
3184 }
3185
3186 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3187 {
3188 snd_card_free(pci_get_drvdata(pci));
3189 pci_set_drvdata(pci, NULL);
3190 }
3191
3192
3193 #ifdef CONFIG_PM
3194 /*
3195 * power management
3196 */
3197 static unsigned char saved_regs[] = {
3198 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3199 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3200 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3201 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3202 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3203 };
3204
3205 static unsigned char saved_mixers[] = {
3206 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3207 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3208 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3209 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3210 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3211 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3212 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3213 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3214 };
3215
3216 static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state)
3217 {
3218 struct snd_card *card = pci_get_drvdata(pci);
3219 struct cmipci *cm = card->private_data;
3220 int i;
3221
3222 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3223
3224 snd_pcm_suspend_all(cm->pcm);
3225 snd_pcm_suspend_all(cm->pcm2);
3226 snd_pcm_suspend_all(cm->pcm_spdif);
3227
3228 /* save registers */
3229 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3230 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3231 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3232 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3233
3234 /* disable ints */
3235 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3236
3237 pci_disable_device(pci);
3238 pci_save_state(pci);
3239 pci_set_power_state(pci, pci_choose_state(pci, state));
3240 return 0;
3241 }
3242
3243 static int snd_cmipci_resume(struct pci_dev *pci)
3244 {
3245 struct snd_card *card = pci_get_drvdata(pci);
3246 struct cmipci *cm = card->private_data;
3247 int i;
3248
3249 pci_set_power_state(pci, PCI_D0);
3250 pci_restore_state(pci);
3251 if (pci_enable_device(pci) < 0) {
3252 printk(KERN_ERR "cmipci: pci_enable_device failed, "
3253 "disabling device\n");
3254 snd_card_disconnect(card);
3255 return -EIO;
3256 }
3257 pci_set_master(pci);
3258
3259 /* reset / initialize to a sane state */
3260 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3261 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3262 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3263 snd_cmipci_mixer_write(cm, 0, 0);
3264
3265 /* restore registers */
3266 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3267 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3268 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3269 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3270
3271 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3272 return 0;
3273 }
3274 #endif /* CONFIG_PM */
3275
3276 static struct pci_driver driver = {
3277 .name = "C-Media PCI",
3278 .id_table = snd_cmipci_ids,
3279 .probe = snd_cmipci_probe,
3280 .remove = __devexit_p(snd_cmipci_remove),
3281 #ifdef CONFIG_PM
3282 .suspend = snd_cmipci_suspend,
3283 .resume = snd_cmipci_resume,
3284 #endif
3285 };
3286
3287 static int __init alsa_card_cmipci_init(void)
3288 {
3289 return pci_register_driver(&driver);
3290 }
3291
3292 static void __exit alsa_card_cmipci_exit(void)
3293 {
3294 pci_unregister_driver(&driver);
3295 }
3296
3297 module_init(alsa_card_cmipci_init)
3298 module_exit(alsa_card_cmipci_exit)
Linux kernel - Deliverables
This page took 0.197697 seconds and 5 git commands to generate.