2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
3 * Abramo Bagnara <abramo@alsa-project.org>
5 * Routines for control of Cirrus Logic CS461x chips
8 * - Sometimes the SPDIF input DSP tasks get's unsynchronized
9 * and the SPDIF get somewhat "distorcionated", or/and left right channel
10 * are swapped. To get around this problem when it happens, mute and unmute
11 * the SPDIF input mixer control.
12 * - On the Hercules Game Theater XP the amplifier are sometimes turned
13 * off on inadecuate moments which causes distorcions on sound.
16 * - Secondary CODEC on some soundcards
17 * - SPDIF input support for other sample rates then 48khz
18 * - Posibility to mix the SPDIF output with analog sources.
19 * - PCM channels for Center and LFE on secondary codec
21 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
22 * is default configuration), no SPDIF, no secondary codec, no
23 * multi channel PCM. But known to work.
25 * FINALLY: A credit to the developers Tom and Jordan
26 * at Cirrus for have helping me out with the DSP, however we
27 * still don't have sufficient documentation and technical
28 * references to be able to implement all fancy feutures
29 * supported by the cs46xx DSP's.
30 * Benny <benny@hostmobility.com>
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License as published by
34 * the Free Software Foundation; either version 2 of the License, or
35 * (at your option) any later version.
37 * This program is distributed in the hope that it will be useful,
38 * but WITHOUT ANY WARRANTY; without even the implied warranty of
39 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
40 * GNU General Public License for more details.
42 * You should have received a copy of the GNU General Public License
43 * along with this program; if not, write to the Free Software
44 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
48 #include <linux/delay.h>
49 #include <linux/pci.h>
51 #include <linux/init.h>
52 #include <linux/interrupt.h>
53 #include <linux/slab.h>
54 #include <linux/gameport.h>
55 #include <linux/mutex.h>
56 #include <linux/export.h>
57 #include <linux/module.h>
58 #include <linux/firmware.h>
59 #include <linux/vmalloc.h>
61 #include <sound/core.h>
62 #include <sound/control.h>
63 #include <sound/info.h>
64 #include <sound/pcm.h>
65 #include <sound/pcm_params.h>
70 #include "cs46xx_lib.h"
73 static void amp_voyetra(struct snd_cs46xx
*chip
, int change
);
75 #ifdef CONFIG_SND_CS46XX_NEW_DSP
76 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops
;
77 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops
;
78 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops
;
79 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops
;
80 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops
;
81 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops
;
84 static struct snd_pcm_ops snd_cs46xx_playback_ops
;
85 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops
;
86 static struct snd_pcm_ops snd_cs46xx_capture_ops
;
87 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops
;
89 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx
*chip
,
94 unsigned short result
,tmp
;
97 if (snd_BUG_ON(codec_index
!= CS46XX_PRIMARY_CODEC_INDEX
&&
98 codec_index
!= CS46XX_SECONDARY_CODEC_INDEX
))
101 chip
->active_ctrl(chip
, 1);
103 if (codec_index
== CS46XX_SECONDARY_CODEC_INDEX
)
104 offset
= CS46XX_SECONDARY_CODEC_OFFSET
;
107 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
108 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
109 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
110 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
111 * 5. if DCV not cleared, break and return error
112 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
115 snd_cs46xx_peekBA0(chip
, BA0_ACSDA
+ offset
);
117 tmp
= snd_cs46xx_peekBA0(chip
, BA0_ACCTL
);
118 if ((tmp
& ACCTL_VFRM
) == 0) {
119 dev_warn(chip
->card
->dev
, "ACCTL_VFRM not set 0x%x\n", tmp
);
120 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, (tmp
& (~ACCTL_ESYN
)) | ACCTL_VFRM
);
122 tmp
= snd_cs46xx_peekBA0(chip
, BA0_ACCTL
+ offset
);
123 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, tmp
| ACCTL_ESYN
| ACCTL_VFRM
);
128 * Setup the AC97 control registers on the CS461x to send the
129 * appropriate command to the AC97 to perform the read.
130 * ACCAD = Command Address Register = 46Ch
131 * ACCDA = Command Data Register = 470h
132 * ACCTL = Control Register = 460h
133 * set DCV - will clear when process completed
134 * set CRW - Read command
135 * set VFRM - valid frame enabled
136 * set ESYN - ASYNC generation enabled
137 * set RSTN - ARST# inactive, AC97 codec not reset
140 snd_cs46xx_pokeBA0(chip
, BA0_ACCAD
, reg
);
141 snd_cs46xx_pokeBA0(chip
, BA0_ACCDA
, 0);
142 if (codec_index
== CS46XX_PRIMARY_CODEC_INDEX
) {
143 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
,/* clear ACCTL_DCV */ ACCTL_CRW
|
144 ACCTL_VFRM
| ACCTL_ESYN
|
146 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_DCV
| ACCTL_CRW
|
147 ACCTL_VFRM
| ACCTL_ESYN
|
150 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_DCV
| ACCTL_TC
|
151 ACCTL_CRW
| ACCTL_VFRM
| ACCTL_ESYN
|
156 * Wait for the read to occur.
158 for (count
= 0; count
< 1000; count
++) {
160 * First, we want to wait for a short time.
164 * Now, check to see if the read has completed.
165 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
167 if (!(snd_cs46xx_peekBA0(chip
, BA0_ACCTL
) & ACCTL_DCV
))
171 dev_err(chip
->card
->dev
,
172 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg
);
178 * Wait for the valid status bit to go active.
180 for (count
= 0; count
< 100; count
++) {
182 * Read the AC97 status register.
183 * ACSTS = Status Register = 464h
184 * VSTS - Valid Status
186 if (snd_cs46xx_peekBA0(chip
, BA0_ACSTS
+ offset
) & ACSTS_VSTS
)
191 dev_err(chip
->card
->dev
,
192 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n",
199 * Read the data returned from the AC97 register.
200 * ACSDA = Status Data Register = 474h
203 dev_dbg(chip
->card
->dev
,
204 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg
,
205 snd_cs46xx_peekBA0(chip
, BA0_ACSDA
),
206 snd_cs46xx_peekBA0(chip
, BA0_ACCAD
));
209 //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
210 result
= snd_cs46xx_peekBA0(chip
, BA0_ACSDA
+ offset
);
212 chip
->active_ctrl(chip
, -1);
216 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97
* ac97
,
219 struct snd_cs46xx
*chip
= ac97
->private_data
;
221 int codec_index
= ac97
->num
;
223 if (snd_BUG_ON(codec_index
!= CS46XX_PRIMARY_CODEC_INDEX
&&
224 codec_index
!= CS46XX_SECONDARY_CODEC_INDEX
))
227 val
= snd_cs46xx_codec_read(chip
, reg
, codec_index
);
233 static void snd_cs46xx_codec_write(struct snd_cs46xx
*chip
,
240 if (snd_BUG_ON(codec_index
!= CS46XX_PRIMARY_CODEC_INDEX
&&
241 codec_index
!= CS46XX_SECONDARY_CODEC_INDEX
))
244 chip
->active_ctrl(chip
, 1);
247 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
248 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
249 * 3. Write ACCTL = Control Register = 460h for initiating the write
250 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
251 * 5. if DCV not cleared, break and return error
255 * Setup the AC97 control registers on the CS461x to send the
256 * appropriate command to the AC97 to perform the read.
257 * ACCAD = Command Address Register = 46Ch
258 * ACCDA = Command Data Register = 470h
259 * ACCTL = Control Register = 460h
260 * set DCV - will clear when process completed
261 * reset CRW - Write command
262 * set VFRM - valid frame enabled
263 * set ESYN - ASYNC generation enabled
264 * set RSTN - ARST# inactive, AC97 codec not reset
266 snd_cs46xx_pokeBA0(chip
, BA0_ACCAD
, reg
);
267 snd_cs46xx_pokeBA0(chip
, BA0_ACCDA
, val
);
268 snd_cs46xx_peekBA0(chip
, BA0_ACCTL
);
270 if (codec_index
== CS46XX_PRIMARY_CODEC_INDEX
) {
271 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, /* clear ACCTL_DCV */ ACCTL_VFRM
|
272 ACCTL_ESYN
| ACCTL_RSTN
);
273 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_DCV
| ACCTL_VFRM
|
274 ACCTL_ESYN
| ACCTL_RSTN
);
276 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_DCV
| ACCTL_TC
|
277 ACCTL_VFRM
| ACCTL_ESYN
| ACCTL_RSTN
);
280 for (count
= 0; count
< 4000; count
++) {
282 * First, we want to wait for a short time.
286 * Now, check to see if the write has completed.
287 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
289 if (!(snd_cs46xx_peekBA0(chip
, BA0_ACCTL
) & ACCTL_DCV
)) {
293 dev_err(chip
->card
->dev
,
294 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n",
295 codec_index
, reg
, val
);
297 chip
->active_ctrl(chip
, -1);
300 static void snd_cs46xx_ac97_write(struct snd_ac97
*ac97
,
304 struct snd_cs46xx
*chip
= ac97
->private_data
;
305 int codec_index
= ac97
->num
;
307 if (snd_BUG_ON(codec_index
!= CS46XX_PRIMARY_CODEC_INDEX
&&
308 codec_index
!= CS46XX_SECONDARY_CODEC_INDEX
))
311 snd_cs46xx_codec_write(chip
, reg
, val
, codec_index
);
316 * Chip initialization
319 int snd_cs46xx_download(struct snd_cs46xx
*chip
,
321 unsigned long offset
,
325 unsigned int bank
= offset
>> 16;
326 offset
= offset
& 0xffff;
328 if (snd_BUG_ON((offset
& 3) || (len
& 3)))
330 dst
= chip
->region
.idx
[bank
+1].remap_addr
+ offset
;
333 /* writel already converts 32-bit value to right endianess */
341 static inline void memcpy_le32(void *dst
, const void *src
, unsigned int len
)
343 #ifdef __LITTLE_ENDIAN
344 memcpy(dst
, src
, len
);
347 const __le32
*_src
= src
;
350 *_dst
++ = le32_to_cpu(*_src
++);
354 #ifdef CONFIG_SND_CS46XX_NEW_DSP
356 static const char *module_names
[CS46XX_DSP_MODULES
] = {
357 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma"
360 MODULE_FIRMWARE("cs46xx/cwc4630");
361 MODULE_FIRMWARE("cs46xx/cwcasync");
362 MODULE_FIRMWARE("cs46xx/cwcsnoop");
363 MODULE_FIRMWARE("cs46xx/cwcbinhack");
364 MODULE_FIRMWARE("cs46xx/cwcdma");
366 static void free_module_desc(struct dsp_module_desc
*module
)
370 kfree(module
->module_name
);
371 kfree(module
->symbol_table
.symbols
);
372 if (module
->segments
) {
374 for (i
= 0; i
< module
->nsegments
; i
++)
375 kfree(module
->segments
[i
].data
);
376 kfree(module
->segments
);
381 /* firmware binary format:
385 * char symbol_name[DSP_MAX_SYMBOL_NAME];
387 * } symbols[nsymbols];
394 * } segments[nsegments];
397 static int load_firmware(struct snd_cs46xx
*chip
,
398 struct dsp_module_desc
**module_ret
,
402 unsigned int nums
, fwlen
, fwsize
;
404 struct dsp_module_desc
*module
= NULL
;
405 const struct firmware
*fw
;
408 sprintf(fw_path
, "cs46xx/%s", fw_name
);
409 err
= request_firmware(&fw
, fw_path
, &chip
->pci
->dev
);
412 fwsize
= fw
->size
/ 4;
419 module
= kzalloc(sizeof(*module
), GFP_KERNEL
);
422 module
->module_name
= kstrdup(fw_name
, GFP_KERNEL
);
423 if (!module
->module_name
)
427 fwdat
= (const __le32
*)fw
->data
;
428 nums
= module
->symbol_table
.nsymbols
= le32_to_cpu(fwdat
[fwlen
++]);
431 module
->symbol_table
.symbols
=
432 kcalloc(nums
, sizeof(struct dsp_symbol_entry
), GFP_KERNEL
);
433 if (!module
->symbol_table
.symbols
)
435 for (i
= 0; i
< nums
; i
++) {
436 struct dsp_symbol_entry
*entry
=
437 &module
->symbol_table
.symbols
[i
];
438 if (fwlen
+ 2 + DSP_MAX_SYMBOL_NAME
/ 4 > fwsize
)
440 entry
->address
= le32_to_cpu(fwdat
[fwlen
++]);
441 memcpy(entry
->symbol_name
, &fwdat
[fwlen
], DSP_MAX_SYMBOL_NAME
- 1);
442 fwlen
+= DSP_MAX_SYMBOL_NAME
/ 4;
443 entry
->symbol_type
= le32_to_cpu(fwdat
[fwlen
++]);
448 nums
= module
->nsegments
= le32_to_cpu(fwdat
[fwlen
++]);
452 kcalloc(nums
, sizeof(struct dsp_segment_desc
), GFP_KERNEL
);
453 if (!module
->segments
)
455 for (i
= 0; i
< nums
; i
++) {
456 struct dsp_segment_desc
*entry
= &module
->segments
[i
];
457 if (fwlen
+ 3 > fwsize
)
459 entry
->segment_type
= le32_to_cpu(fwdat
[fwlen
++]);
460 entry
->offset
= le32_to_cpu(fwdat
[fwlen
++]);
461 entry
->size
= le32_to_cpu(fwdat
[fwlen
++]);
462 if (fwlen
+ entry
->size
> fwsize
)
464 entry
->data
= kmalloc(entry
->size
* 4, GFP_KERNEL
);
467 memcpy_le32(entry
->data
, &fwdat
[fwlen
], entry
->size
* 4);
468 fwlen
+= entry
->size
;
471 *module_ret
= module
;
472 release_firmware(fw
);
478 free_module_desc(module
);
479 release_firmware(fw
);
483 int snd_cs46xx_clear_BA1(struct snd_cs46xx
*chip
,
484 unsigned long offset
,
488 unsigned int bank
= offset
>> 16;
489 offset
= offset
& 0xffff;
491 if (snd_BUG_ON((offset
& 3) || (len
& 3)))
493 dst
= chip
->region
.idx
[bank
+1].remap_addr
+ offset
;
496 /* writel already converts 32-bit value to right endianess */
504 #else /* old DSP image */
510 } memory
[BA1_MEMORY_COUNT
];
511 u32 map
[BA1_DWORD_SIZE
];
514 MODULE_FIRMWARE("cs46xx/ba1");
516 static int load_firmware(struct snd_cs46xx
*chip
)
518 const struct firmware
*fw
;
521 err
= request_firmware(&fw
, "cs46xx/ba1", &chip
->pci
->dev
);
524 if (fw
->size
!= sizeof(*chip
->ba1
)) {
529 chip
->ba1
= vmalloc(sizeof(*chip
->ba1
));
535 memcpy_le32(chip
->ba1
, fw
->data
, sizeof(*chip
->ba1
));
539 for (i
= 0; i
< BA1_MEMORY_COUNT
; i
++)
540 size
+= chip
->ba1
->memory
[i
].size
;
541 if (size
> BA1_DWORD_SIZE
* 4)
545 release_firmware(fw
);
549 int snd_cs46xx_download_image(struct snd_cs46xx
*chip
)
552 unsigned int offset
= 0;
553 struct ba1_struct
*ba1
= chip
->ba1
;
555 for (idx
= 0; idx
< BA1_MEMORY_COUNT
; idx
++) {
556 err
= snd_cs46xx_download(chip
,
558 ba1
->memory
[idx
].offset
,
559 ba1
->memory
[idx
].size
);
562 offset
+= ba1
->memory
[idx
].size
>> 2;
566 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
572 static void snd_cs46xx_reset(struct snd_cs46xx
*chip
)
577 * Write the reset bit of the SP control register.
579 snd_cs46xx_poke(chip
, BA1_SPCR
, SPCR_RSTSP
);
582 * Write the control register.
584 snd_cs46xx_poke(chip
, BA1_SPCR
, SPCR_DRQEN
);
587 * Clear the trap registers.
589 for (idx
= 0; idx
< 8; idx
++) {
590 snd_cs46xx_poke(chip
, BA1_DREG
, DREG_REGID_TRAP_SELECT
+ idx
);
591 snd_cs46xx_poke(chip
, BA1_TWPR
, 0xFFFF);
593 snd_cs46xx_poke(chip
, BA1_DREG
, 0);
596 * Set the frame timer to reflect the number of cycles per frame.
598 snd_cs46xx_poke(chip
, BA1_FRMT
, 0xadf);
601 static int cs46xx_wait_for_fifo(struct snd_cs46xx
* chip
,int retry_timeout
)
605 * Make sure the previous FIFO write operation has completed.
607 for(i
= 0; i
< 50; i
++){
608 status
= snd_cs46xx_peekBA0(chip
, BA0_SERBST
);
610 if( !(status
& SERBST_WBSY
) )
613 mdelay(retry_timeout
);
616 if(status
& SERBST_WBSY
) {
617 dev_err(chip
->card
->dev
,
618 "failure waiting for FIFO command to complete\n");
625 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx
*chip
)
627 int idx
, powerdown
= 0;
631 * See if the devices are powered down. If so, we must power them up first
632 * or they will not respond.
634 tmp
= snd_cs46xx_peekBA0(chip
, BA0_CLKCR1
);
635 if (!(tmp
& CLKCR1_SWCE
)) {
636 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
| CLKCR1_SWCE
);
641 * We want to clear out the serial port FIFOs so we don't end up playing
642 * whatever random garbage happens to be in them. We fill the sample FIFOS
643 * with zero (silence).
645 snd_cs46xx_pokeBA0(chip
, BA0_SERBWP
, 0);
648 * Fill all 256 sample FIFO locations.
650 for (idx
= 0; idx
< 0xFF; idx
++) {
652 * Make sure the previous FIFO write operation has completed.
654 if (cs46xx_wait_for_fifo(chip
,1)) {
655 dev_dbg(chip
->card
->dev
,
656 "failed waiting for FIFO at addr (%02X)\n",
660 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
);
665 * Write the serial port FIFO index.
667 snd_cs46xx_pokeBA0(chip
, BA0_SERBAD
, idx
);
669 * Tell the serial port to load the new value into the FIFO location.
671 snd_cs46xx_pokeBA0(chip
, BA0_SERBCM
, SERBCM_WRC
);
674 * Now, if we powered up the devices, then power them back down again.
675 * This is kinda ugly, but should never happen.
678 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
);
681 static void snd_cs46xx_proc_start(struct snd_cs46xx
*chip
)
686 * Set the frame timer to reflect the number of cycles per frame.
688 snd_cs46xx_poke(chip
, BA1_FRMT
, 0xadf);
690 * Turn on the run, run at frame, and DMA enable bits in the local copy of
691 * the SP control register.
693 snd_cs46xx_poke(chip
, BA1_SPCR
, SPCR_RUN
| SPCR_RUNFR
| SPCR_DRQEN
);
695 * Wait until the run at frame bit resets itself in the SP control
698 for (cnt
= 0; cnt
< 25; cnt
++) {
700 if (!(snd_cs46xx_peek(chip
, BA1_SPCR
) & SPCR_RUNFR
))
704 if (snd_cs46xx_peek(chip
, BA1_SPCR
) & SPCR_RUNFR
)
705 dev_err(chip
->card
->dev
, "SPCR_RUNFR never reset\n");
708 static void snd_cs46xx_proc_stop(struct snd_cs46xx
*chip
)
711 * Turn off the run, run at frame, and DMA enable bits in the local copy of
712 * the SP control register.
714 snd_cs46xx_poke(chip
, BA1_SPCR
, 0);
718 * Sample rate routines
721 #define GOF_PER_SEC 200
723 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx
*chip
, unsigned int rate
)
726 unsigned int tmp1
, tmp2
;
727 unsigned int phiIncr
;
728 unsigned int correctionPerGOF
, correctionPerSec
;
731 * Compute the values used to drive the actual sample rate conversion.
732 * The following formulas are being computed, using inline assembly
733 * since we need to use 64 bit arithmetic to compute the values:
735 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
736 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
738 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
739 * GOF_PER_SEC * correctionPerGOF
743 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
744 * correctionPerGOF:correctionPerSec =
745 * dividend:remainder(ulOther / GOF_PER_SEC)
748 phiIncr
= tmp1
/ 48000;
749 tmp1
-= phiIncr
* 48000;
754 tmp1
-= tmp2
* 48000;
755 correctionPerGOF
= tmp1
/ GOF_PER_SEC
;
756 tmp1
-= correctionPerGOF
* GOF_PER_SEC
;
757 correctionPerSec
= tmp1
;
760 * Fill in the SampleRateConverter control block.
762 spin_lock_irqsave(&chip
->reg_lock
, flags
);
763 snd_cs46xx_poke(chip
, BA1_PSRC
,
764 ((correctionPerSec
<< 16) & 0xFFFF0000) | (correctionPerGOF
& 0xFFFF));
765 snd_cs46xx_poke(chip
, BA1_PPI
, phiIncr
);
766 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
769 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx
*chip
, unsigned int rate
)
772 unsigned int phiIncr
, coeffIncr
, tmp1
, tmp2
;
773 unsigned int correctionPerGOF
, correctionPerSec
, initialDelay
;
774 unsigned int frameGroupLength
, cnt
;
777 * We can only decimate by up to a factor of 1/9th the hardware rate.
778 * Correct the value if an attempt is made to stray outside that limit.
780 if ((rate
* 9) < 48000)
784 * We can not capture at at rate greater than the Input Rate (48000).
785 * Return an error if an attempt is made to stray outside that limit.
791 * Compute the values used to drive the actual sample rate conversion.
792 * The following formulas are being computed, using inline assembly
793 * since we need to use 64 bit arithmetic to compute the values:
795 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
796 * phiIncr = floor((Fs,in * 2^26) / Fs,out)
797 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
799 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
800 * GOF_PER_SEC * correctionPerGOF
801 * initialDelay = ceil((24 * Fs,in) / Fs,out)
805 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
806 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
807 * correctionPerGOF:correctionPerSec =
808 * dividend:remainder(ulOther / GOF_PER_SEC)
809 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
813 coeffIncr
= tmp1
/ 48000;
814 tmp1
-= coeffIncr
* 48000;
817 coeffIncr
+= tmp1
/ 48000;
818 coeffIncr
^= 0xFFFFFFFF;
821 phiIncr
= tmp1
/ rate
;
822 tmp1
-= phiIncr
* rate
;
828 correctionPerGOF
= tmp1
/ GOF_PER_SEC
;
829 tmp1
-= correctionPerGOF
* GOF_PER_SEC
;
830 correctionPerSec
= tmp1
;
831 initialDelay
= ((48000 * 24) + rate
- 1) / rate
;
834 * Fill in the VariDecimate control block.
836 spin_lock_irqsave(&chip
->reg_lock
, flags
);
837 snd_cs46xx_poke(chip
, BA1_CSRC
,
838 ((correctionPerSec
<< 16) & 0xFFFF0000) | (correctionPerGOF
& 0xFFFF));
839 snd_cs46xx_poke(chip
, BA1_CCI
, coeffIncr
);
840 snd_cs46xx_poke(chip
, BA1_CD
,
841 (((BA1_VARIDEC_BUF_1
+ (initialDelay
<< 2)) << 16) & 0xFFFF0000) | 0x80);
842 snd_cs46xx_poke(chip
, BA1_CPI
, phiIncr
);
843 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
846 * Figure out the frame group length for the write back task. Basically,
847 * this is just the factors of 24000 (2^6*3*5^3) that are not present in
848 * the output sample rate.
850 frameGroupLength
= 1;
851 for (cnt
= 2; cnt
<= 64; cnt
*= 2) {
852 if (((rate
/ cnt
) * cnt
) != rate
)
853 frameGroupLength
*= 2;
855 if (((rate
/ 3) * 3) != rate
) {
856 frameGroupLength
*= 3;
858 for (cnt
= 5; cnt
<= 125; cnt
*= 5) {
859 if (((rate
/ cnt
) * cnt
) != rate
)
860 frameGroupLength
*= 5;
864 * Fill in the WriteBack control block.
866 spin_lock_irqsave(&chip
->reg_lock
, flags
);
867 snd_cs46xx_poke(chip
, BA1_CFG1
, frameGroupLength
);
868 snd_cs46xx_poke(chip
, BA1_CFG2
, (0x00800000 | frameGroupLength
));
869 snd_cs46xx_poke(chip
, BA1_CCST
, 0x0000FFFF);
870 snd_cs46xx_poke(chip
, BA1_CSPB
, ((65536 * rate
) / 24000));
871 snd_cs46xx_poke(chip
, (BA1_CSPB
+ 4), 0x0000FFFF);
872 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
879 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream
*substream
,
880 struct snd_pcm_indirect
*rec
, size_t bytes
)
882 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
883 struct snd_cs46xx_pcm
* cpcm
= runtime
->private_data
;
884 memcpy(cpcm
->hw_buf
.area
+ rec
->hw_data
, runtime
->dma_area
+ rec
->sw_data
, bytes
);
887 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream
*substream
)
889 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
890 struct snd_cs46xx_pcm
* cpcm
= runtime
->private_data
;
891 snd_pcm_indirect_playback_transfer(substream
, &cpcm
->pcm_rec
, snd_cs46xx_pb_trans_copy
);
895 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream
*substream
,
896 struct snd_pcm_indirect
*rec
, size_t bytes
)
898 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
899 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
900 memcpy(runtime
->dma_area
+ rec
->sw_data
,
901 chip
->capt
.hw_buf
.area
+ rec
->hw_data
, bytes
);
904 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream
*substream
)
906 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
907 snd_pcm_indirect_capture_transfer(substream
, &chip
->capt
.pcm_rec
, snd_cs46xx_cp_trans_copy
);
911 static snd_pcm_uframes_t
snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream
*substream
)
913 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
915 struct snd_cs46xx_pcm
*cpcm
= substream
->runtime
->private_data
;
917 if (snd_BUG_ON(!cpcm
->pcm_channel
))
920 #ifdef CONFIG_SND_CS46XX_NEW_DSP
921 ptr
= snd_cs46xx_peek(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+ 2) << 2);
923 ptr
= snd_cs46xx_peek(chip
, BA1_PBA
);
925 ptr
-= cpcm
->hw_buf
.addr
;
926 return ptr
>> cpcm
->shift
;
929 static snd_pcm_uframes_t
snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream
*substream
)
931 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
933 struct snd_cs46xx_pcm
*cpcm
= substream
->runtime
->private_data
;
935 #ifdef CONFIG_SND_CS46XX_NEW_DSP
936 if (snd_BUG_ON(!cpcm
->pcm_channel
))
938 ptr
= snd_cs46xx_peek(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+ 2) << 2);
940 ptr
= snd_cs46xx_peek(chip
, BA1_PBA
);
942 ptr
-= cpcm
->hw_buf
.addr
;
943 return snd_pcm_indirect_playback_pointer(substream
, &cpcm
->pcm_rec
, ptr
);
946 static snd_pcm_uframes_t
snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream
*substream
)
948 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
949 size_t ptr
= snd_cs46xx_peek(chip
, BA1_CBA
) - chip
->capt
.hw_buf
.addr
;
950 return ptr
>> chip
->capt
.shift
;
953 static snd_pcm_uframes_t
snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream
*substream
)
955 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
956 size_t ptr
= snd_cs46xx_peek(chip
, BA1_CBA
) - chip
->capt
.hw_buf
.addr
;
957 return snd_pcm_indirect_capture_pointer(substream
, &chip
->capt
.pcm_rec
, ptr
);
960 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream
*substream
,
963 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
964 /*struct snd_pcm_runtime *runtime = substream->runtime;*/
967 #ifdef CONFIG_SND_CS46XX_NEW_DSP
968 struct snd_cs46xx_pcm
*cpcm
= substream
->runtime
->private_data
;
969 if (! cpcm
->pcm_channel
) {
974 case SNDRV_PCM_TRIGGER_START
:
975 case SNDRV_PCM_TRIGGER_RESUME
:
976 #ifdef CONFIG_SND_CS46XX_NEW_DSP
977 /* magic value to unmute PCM stream playback volume */
978 snd_cs46xx_poke(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+
979 SCBVolumeCtrl
) << 2, 0x80008000);
981 if (cpcm
->pcm_channel
->unlinked
)
982 cs46xx_dsp_pcm_link(chip
,cpcm
->pcm_channel
);
984 if (substream
->runtime
->periods
!= CS46XX_FRAGS
)
985 snd_cs46xx_playback_transfer(substream
);
987 spin_lock(&chip
->reg_lock
);
988 if (substream
->runtime
->periods
!= CS46XX_FRAGS
)
989 snd_cs46xx_playback_transfer(substream
);
991 tmp
= snd_cs46xx_peek(chip
, BA1_PCTL
);
993 snd_cs46xx_poke(chip
, BA1_PCTL
, chip
->play_ctl
| tmp
);
995 spin_unlock(&chip
->reg_lock
);
998 case SNDRV_PCM_TRIGGER_STOP
:
999 case SNDRV_PCM_TRIGGER_SUSPEND
:
1000 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1001 /* magic mute channel */
1002 snd_cs46xx_poke(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+
1003 SCBVolumeCtrl
) << 2, 0xffffffff);
1005 if (!cpcm
->pcm_channel
->unlinked
)
1006 cs46xx_dsp_pcm_unlink(chip
,cpcm
->pcm_channel
);
1008 spin_lock(&chip
->reg_lock
);
1010 tmp
= snd_cs46xx_peek(chip
, BA1_PCTL
);
1012 snd_cs46xx_poke(chip
, BA1_PCTL
, tmp
);
1014 spin_unlock(&chip
->reg_lock
);
1025 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream
*substream
,
1028 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1032 spin_lock(&chip
->reg_lock
);
1034 case SNDRV_PCM_TRIGGER_START
:
1035 case SNDRV_PCM_TRIGGER_RESUME
:
1036 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
1038 snd_cs46xx_poke(chip
, BA1_CCTL
, chip
->capt
.ctl
| tmp
);
1040 case SNDRV_PCM_TRIGGER_STOP
:
1041 case SNDRV_PCM_TRIGGER_SUSPEND
:
1042 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
1044 snd_cs46xx_poke(chip
, BA1_CCTL
, tmp
);
1050 spin_unlock(&chip
->reg_lock
);
1055 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1056 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx
*chip
, struct snd_cs46xx_pcm
*cpcm
,
1060 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
1061 if ( cpcm
->pcm_channel
== NULL
) {
1062 cpcm
->pcm_channel
= cs46xx_dsp_create_pcm_channel (chip
, sample_rate
,
1063 cpcm
, cpcm
->hw_buf
.addr
,cpcm
->pcm_channel_id
);
1064 if (cpcm
->pcm_channel
== NULL
) {
1065 dev_err(chip
->card
->dev
,
1066 "failed to create virtual PCM channel\n");
1069 cpcm
->pcm_channel
->sample_rate
= sample_rate
;
1071 /* if sample rate is changed */
1072 if ((int)cpcm
->pcm_channel
->sample_rate
!= sample_rate
) {
1073 int unlinked
= cpcm
->pcm_channel
->unlinked
;
1074 cs46xx_dsp_destroy_pcm_channel (chip
,cpcm
->pcm_channel
);
1076 if ( (cpcm
->pcm_channel
= cs46xx_dsp_create_pcm_channel (chip
, sample_rate
, cpcm
,
1078 cpcm
->pcm_channel_id
)) == NULL
) {
1079 dev_err(chip
->card
->dev
,
1080 "failed to re-create virtual PCM channel\n");
1084 if (!unlinked
) cs46xx_dsp_pcm_link (chip
,cpcm
->pcm_channel
);
1085 cpcm
->pcm_channel
->sample_rate
= sample_rate
;
1093 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream
*substream
,
1094 struct snd_pcm_hw_params
*hw_params
)
1096 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1097 struct snd_cs46xx_pcm
*cpcm
;
1099 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1100 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1101 int sample_rate
= params_rate(hw_params
);
1102 int period_size
= params_period_bytes(hw_params
);
1104 cpcm
= runtime
->private_data
;
1106 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1107 if (snd_BUG_ON(!sample_rate
))
1110 mutex_lock(&chip
->spos_mutex
);
1112 if (_cs46xx_adjust_sample_rate (chip
,cpcm
,sample_rate
)) {
1113 mutex_unlock(&chip
->spos_mutex
);
1117 snd_BUG_ON(!cpcm
->pcm_channel
);
1118 if (!cpcm
->pcm_channel
) {
1119 mutex_unlock(&chip
->spos_mutex
);
1124 if (cs46xx_dsp_pcm_channel_set_period (chip
,cpcm
->pcm_channel
,period_size
)) {
1125 mutex_unlock(&chip
->spos_mutex
);
1129 dev_dbg(chip
->card
->dev
,
1130 "period_size (%d), periods (%d) buffer_size(%d)\n",
1131 period_size
, params_periods(hw_params
),
1132 params_buffer_bytes(hw_params
));
1135 if (params_periods(hw_params
) == CS46XX_FRAGS
) {
1136 if (runtime
->dma_area
!= cpcm
->hw_buf
.area
)
1137 snd_pcm_lib_free_pages(substream
);
1138 runtime
->dma_area
= cpcm
->hw_buf
.area
;
1139 runtime
->dma_addr
= cpcm
->hw_buf
.addr
;
1140 runtime
->dma_bytes
= cpcm
->hw_buf
.bytes
;
1143 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1144 if (cpcm
->pcm_channel_id
== DSP_PCM_MAIN_CHANNEL
) {
1145 substream
->ops
= &snd_cs46xx_playback_ops
;
1146 } else if (cpcm
->pcm_channel_id
== DSP_PCM_REAR_CHANNEL
) {
1147 substream
->ops
= &snd_cs46xx_playback_rear_ops
;
1148 } else if (cpcm
->pcm_channel_id
== DSP_PCM_CENTER_LFE_CHANNEL
) {
1149 substream
->ops
= &snd_cs46xx_playback_clfe_ops
;
1150 } else if (cpcm
->pcm_channel_id
== DSP_IEC958_CHANNEL
) {
1151 substream
->ops
= &snd_cs46xx_playback_iec958_ops
;
1156 substream
->ops
= &snd_cs46xx_playback_ops
;
1160 if (runtime
->dma_area
== cpcm
->hw_buf
.area
) {
1161 runtime
->dma_area
= NULL
;
1162 runtime
->dma_addr
= 0;
1163 runtime
->dma_bytes
= 0;
1165 if ((err
= snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
))) < 0) {
1166 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1167 mutex_unlock(&chip
->spos_mutex
);
1172 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1173 if (cpcm
->pcm_channel_id
== DSP_PCM_MAIN_CHANNEL
) {
1174 substream
->ops
= &snd_cs46xx_playback_indirect_ops
;
1175 } else if (cpcm
->pcm_channel_id
== DSP_PCM_REAR_CHANNEL
) {
1176 substream
->ops
= &snd_cs46xx_playback_indirect_rear_ops
;
1177 } else if (cpcm
->pcm_channel_id
== DSP_PCM_CENTER_LFE_CHANNEL
) {
1178 substream
->ops
= &snd_cs46xx_playback_indirect_clfe_ops
;
1179 } else if (cpcm
->pcm_channel_id
== DSP_IEC958_CHANNEL
) {
1180 substream
->ops
= &snd_cs46xx_playback_indirect_iec958_ops
;
1185 substream
->ops
= &snd_cs46xx_playback_indirect_ops
;
1190 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1191 mutex_unlock(&chip
->spos_mutex
);
1197 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream
*substream
)
1199 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1200 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1201 struct snd_cs46xx_pcm
*cpcm
;
1203 cpcm
= runtime
->private_data
;
1205 /* if play_back open fails, then this function
1206 is called and cpcm can actually be NULL here */
1207 if (!cpcm
) return -ENXIO
;
1209 if (runtime
->dma_area
!= cpcm
->hw_buf
.area
)
1210 snd_pcm_lib_free_pages(substream
);
1212 runtime
->dma_area
= NULL
;
1213 runtime
->dma_addr
= 0;
1214 runtime
->dma_bytes
= 0;
1219 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream
*substream
)
1223 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1224 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1225 struct snd_cs46xx_pcm
*cpcm
;
1227 cpcm
= runtime
->private_data
;
1229 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1230 if (snd_BUG_ON(!cpcm
->pcm_channel
))
1233 pfie
= snd_cs46xx_peek(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+ 1) << 2 );
1234 pfie
&= ~0x0000f03f;
1237 pfie
= snd_cs46xx_peek(chip
, BA1_PFIE
);
1238 pfie
&= ~0x0000f03f;
1242 /* if to convert from stereo to mono */
1243 if (runtime
->channels
== 1) {
1247 /* if to convert from 8 bit to 16 bit */
1248 if (snd_pcm_format_width(runtime
->format
) == 8) {
1252 /* if to convert to unsigned */
1253 if (snd_pcm_format_unsigned(runtime
->format
))
1256 /* Never convert byte order when sample stream is 8 bit */
1257 if (snd_pcm_format_width(runtime
->format
) != 8) {
1258 /* convert from big endian to little endian */
1259 if (snd_pcm_format_big_endian(runtime
->format
))
1263 memset(&cpcm
->pcm_rec
, 0, sizeof(cpcm
->pcm_rec
));
1264 cpcm
->pcm_rec
.sw_buffer_size
= snd_pcm_lib_buffer_bytes(substream
);
1265 cpcm
->pcm_rec
.hw_buffer_size
= runtime
->period_size
* CS46XX_FRAGS
<< cpcm
->shift
;
1267 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1269 tmp
= snd_cs46xx_peek(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
) << 2);
1271 tmp
|= (4 << cpcm
->shift
) - 1;
1272 /* playback transaction count register */
1273 snd_cs46xx_poke(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
) << 2, tmp
);
1275 /* playback format && interrupt enable */
1276 snd_cs46xx_poke(chip
, (cpcm
->pcm_channel
->pcm_reader_scb
->address
+ 1) << 2, pfie
| cpcm
->pcm_channel
->pcm_slot
);
1278 snd_cs46xx_poke(chip
, BA1_PBA
, cpcm
->hw_buf
.addr
);
1279 tmp
= snd_cs46xx_peek(chip
, BA1_PDTC
);
1281 tmp
|= (4 << cpcm
->shift
) - 1;
1282 snd_cs46xx_poke(chip
, BA1_PDTC
, tmp
);
1283 snd_cs46xx_poke(chip
, BA1_PFIE
, pfie
);
1284 snd_cs46xx_set_play_sample_rate(chip
, runtime
->rate
);
1290 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream
*substream
,
1291 struct snd_pcm_hw_params
*hw_params
)
1293 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1294 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1297 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1298 cs46xx_dsp_pcm_ostream_set_period (chip
, params_period_bytes(hw_params
));
1300 if (runtime
->periods
== CS46XX_FRAGS
) {
1301 if (runtime
->dma_area
!= chip
->capt
.hw_buf
.area
)
1302 snd_pcm_lib_free_pages(substream
);
1303 runtime
->dma_area
= chip
->capt
.hw_buf
.area
;
1304 runtime
->dma_addr
= chip
->capt
.hw_buf
.addr
;
1305 runtime
->dma_bytes
= chip
->capt
.hw_buf
.bytes
;
1306 substream
->ops
= &snd_cs46xx_capture_ops
;
1308 if (runtime
->dma_area
== chip
->capt
.hw_buf
.area
) {
1309 runtime
->dma_area
= NULL
;
1310 runtime
->dma_addr
= 0;
1311 runtime
->dma_bytes
= 0;
1313 if ((err
= snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
))) < 0)
1315 substream
->ops
= &snd_cs46xx_capture_indirect_ops
;
1321 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream
*substream
)
1323 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1324 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1326 if (runtime
->dma_area
!= chip
->capt
.hw_buf
.area
)
1327 snd_pcm_lib_free_pages(substream
);
1328 runtime
->dma_area
= NULL
;
1329 runtime
->dma_addr
= 0;
1330 runtime
->dma_bytes
= 0;
1335 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream
*substream
)
1337 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1338 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1340 snd_cs46xx_poke(chip
, BA1_CBA
, chip
->capt
.hw_buf
.addr
);
1341 chip
->capt
.shift
= 2;
1342 memset(&chip
->capt
.pcm_rec
, 0, sizeof(chip
->capt
.pcm_rec
));
1343 chip
->capt
.pcm_rec
.sw_buffer_size
= snd_pcm_lib_buffer_bytes(substream
);
1344 chip
->capt
.pcm_rec
.hw_buffer_size
= runtime
->period_size
* CS46XX_FRAGS
<< 2;
1345 snd_cs46xx_set_capture_sample_rate(chip
, runtime
->rate
);
1350 static irqreturn_t
snd_cs46xx_interrupt(int irq
, void *dev_id
)
1352 struct snd_cs46xx
*chip
= dev_id
;
1354 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1355 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
1358 struct snd_cs46xx_pcm
*cpcm
= NULL
;
1362 * Read the Interrupt Status Register to clear the interrupt
1364 status1
= snd_cs46xx_peekBA0(chip
, BA0_HISR
);
1365 if ((status1
& 0x7fffffff) == 0) {
1366 snd_cs46xx_pokeBA0(chip
, BA0_HICR
, HICR_CHGM
| HICR_IEV
);
1370 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1371 status2
= snd_cs46xx_peekBA0(chip
, BA0_HSR0
);
1373 for (i
= 0; i
< DSP_MAX_PCM_CHANNELS
; ++i
) {
1375 if ( status1
& (1 << i
) ) {
1376 if (i
== CS46XX_DSP_CAPTURE_CHANNEL
) {
1377 if (chip
->capt
.substream
)
1378 snd_pcm_period_elapsed(chip
->capt
.substream
);
1380 if (ins
->pcm_channels
[i
].active
&&
1381 ins
->pcm_channels
[i
].private_data
&&
1382 !ins
->pcm_channels
[i
].unlinked
) {
1383 cpcm
= ins
->pcm_channels
[i
].private_data
;
1384 snd_pcm_period_elapsed(cpcm
->substream
);
1389 if ( status2
& (1 << (i
- 16))) {
1390 if (ins
->pcm_channels
[i
].active
&&
1391 ins
->pcm_channels
[i
].private_data
&&
1392 !ins
->pcm_channels
[i
].unlinked
) {
1393 cpcm
= ins
->pcm_channels
[i
].private_data
;
1394 snd_pcm_period_elapsed(cpcm
->substream
);
1402 if ((status1
& HISR_VC0
) && chip
->playback_pcm
) {
1403 if (chip
->playback_pcm
->substream
)
1404 snd_pcm_period_elapsed(chip
->playback_pcm
->substream
);
1406 if ((status1
& HISR_VC1
) && chip
->pcm
) {
1407 if (chip
->capt
.substream
)
1408 snd_pcm_period_elapsed(chip
->capt
.substream
);
1412 if ((status1
& HISR_MIDI
) && chip
->rmidi
) {
1415 spin_lock(&chip
->reg_lock
);
1416 while ((snd_cs46xx_peekBA0(chip
, BA0_MIDSR
) & MIDSR_RBE
) == 0) {
1417 c
= snd_cs46xx_peekBA0(chip
, BA0_MIDRP
);
1418 if ((chip
->midcr
& MIDCR_RIE
) == 0)
1420 snd_rawmidi_receive(chip
->midi_input
, &c
, 1);
1422 while ((snd_cs46xx_peekBA0(chip
, BA0_MIDSR
) & MIDSR_TBF
) == 0) {
1423 if ((chip
->midcr
& MIDCR_TIE
) == 0)
1425 if (snd_rawmidi_transmit(chip
->midi_output
, &c
, 1) != 1) {
1426 chip
->midcr
&= ~MIDCR_TIE
;
1427 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
1430 snd_cs46xx_pokeBA0(chip
, BA0_MIDWP
, c
);
1432 spin_unlock(&chip
->reg_lock
);
1435 * EOI to the PCI part....reenables interrupts
1437 snd_cs46xx_pokeBA0(chip
, BA0_HICR
, HICR_CHGM
| HICR_IEV
);
1442 static struct snd_pcm_hardware snd_cs46xx_playback
=
1444 .info
= (SNDRV_PCM_INFO_MMAP
|
1445 SNDRV_PCM_INFO_INTERLEAVED
|
1446 SNDRV_PCM_INFO_BLOCK_TRANSFER
/*|*/
1447 /*SNDRV_PCM_INFO_RESUME*/),
1448 .formats
= (SNDRV_PCM_FMTBIT_S8
| SNDRV_PCM_FMTBIT_U8
|
1449 SNDRV_PCM_FMTBIT_S16_LE
| SNDRV_PCM_FMTBIT_S16_BE
|
1450 SNDRV_PCM_FMTBIT_U16_LE
| SNDRV_PCM_FMTBIT_U16_BE
),
1451 .rates
= SNDRV_PCM_RATE_CONTINUOUS
| SNDRV_PCM_RATE_8000_48000
,
1456 .buffer_bytes_max
= (256 * 1024),
1457 .period_bytes_min
= CS46XX_MIN_PERIOD_SIZE
,
1458 .period_bytes_max
= CS46XX_MAX_PERIOD_SIZE
,
1459 .periods_min
= CS46XX_FRAGS
,
1460 .periods_max
= 1024,
1464 static struct snd_pcm_hardware snd_cs46xx_capture
=
1466 .info
= (SNDRV_PCM_INFO_MMAP
|
1467 SNDRV_PCM_INFO_INTERLEAVED
|
1468 SNDRV_PCM_INFO_BLOCK_TRANSFER
/*|*/
1469 /*SNDRV_PCM_INFO_RESUME*/),
1470 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1471 .rates
= SNDRV_PCM_RATE_CONTINUOUS
| SNDRV_PCM_RATE_8000_48000
,
1476 .buffer_bytes_max
= (256 * 1024),
1477 .period_bytes_min
= CS46XX_MIN_PERIOD_SIZE
,
1478 .period_bytes_max
= CS46XX_MAX_PERIOD_SIZE
,
1479 .periods_min
= CS46XX_FRAGS
,
1480 .periods_max
= 1024,
1484 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1486 static unsigned int period_sizes
[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1488 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes
= {
1489 .count
= ARRAY_SIZE(period_sizes
),
1490 .list
= period_sizes
,
1496 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime
*runtime
)
1498 kfree(runtime
->private_data
);
1501 static int _cs46xx_playback_open_channel (struct snd_pcm_substream
*substream
,int pcm_channel_id
)
1503 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1504 struct snd_cs46xx_pcm
* cpcm
;
1505 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1507 cpcm
= kzalloc(sizeof(*cpcm
), GFP_KERNEL
);
1510 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1511 PAGE_SIZE
, &cpcm
->hw_buf
) < 0) {
1516 runtime
->hw
= snd_cs46xx_playback
;
1517 runtime
->private_data
= cpcm
;
1518 runtime
->private_free
= snd_cs46xx_pcm_free_substream
;
1520 cpcm
->substream
= substream
;
1521 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1522 mutex_lock(&chip
->spos_mutex
);
1523 cpcm
->pcm_channel
= NULL
;
1524 cpcm
->pcm_channel_id
= pcm_channel_id
;
1527 snd_pcm_hw_constraint_list(runtime
, 0,
1528 SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1529 &hw_constraints_period_sizes
);
1531 mutex_unlock(&chip
->spos_mutex
);
1533 chip
->playback_pcm
= cpcm
; /* HACK */
1536 if (chip
->accept_valid
)
1537 substream
->runtime
->hw
.info
|= SNDRV_PCM_INFO_MMAP_VALID
;
1538 chip
->active_ctrl(chip
, 1);
1543 static int snd_cs46xx_playback_open(struct snd_pcm_substream
*substream
)
1545 dev_dbg(substream
->pcm
->card
->dev
, "open front channel\n");
1546 return _cs46xx_playback_open_channel(substream
,DSP_PCM_MAIN_CHANNEL
);
1549 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1550 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream
*substream
)
1552 dev_dbg(substream
->pcm
->card
->dev
, "open rear channel\n");
1553 return _cs46xx_playback_open_channel(substream
,DSP_PCM_REAR_CHANNEL
);
1556 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream
*substream
)
1558 dev_dbg(substream
->pcm
->card
->dev
, "open center - LFE channel\n");
1559 return _cs46xx_playback_open_channel(substream
,DSP_PCM_CENTER_LFE_CHANNEL
);
1562 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream
*substream
)
1564 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1566 dev_dbg(chip
->card
->dev
, "open raw iec958 channel\n");
1568 mutex_lock(&chip
->spos_mutex
);
1569 cs46xx_iec958_pre_open (chip
);
1570 mutex_unlock(&chip
->spos_mutex
);
1572 return _cs46xx_playback_open_channel(substream
,DSP_IEC958_CHANNEL
);
1575 static int snd_cs46xx_playback_close(struct snd_pcm_substream
*substream
);
1577 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream
*substream
)
1580 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1582 dev_dbg(chip
->card
->dev
, "close raw iec958 channel\n");
1584 err
= snd_cs46xx_playback_close(substream
);
1586 mutex_lock(&chip
->spos_mutex
);
1587 cs46xx_iec958_post_close (chip
);
1588 mutex_unlock(&chip
->spos_mutex
);
1594 static int snd_cs46xx_capture_open(struct snd_pcm_substream
*substream
)
1596 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1598 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1599 PAGE_SIZE
, &chip
->capt
.hw_buf
) < 0)
1601 chip
->capt
.substream
= substream
;
1602 substream
->runtime
->hw
= snd_cs46xx_capture
;
1604 if (chip
->accept_valid
)
1605 substream
->runtime
->hw
.info
|= SNDRV_PCM_INFO_MMAP_VALID
;
1607 chip
->active_ctrl(chip
, 1);
1609 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1610 snd_pcm_hw_constraint_list(substream
->runtime
, 0,
1611 SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1612 &hw_constraints_period_sizes
);
1617 static int snd_cs46xx_playback_close(struct snd_pcm_substream
*substream
)
1619 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1620 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1621 struct snd_cs46xx_pcm
* cpcm
;
1623 cpcm
= runtime
->private_data
;
1625 /* when playback_open fails, then cpcm can be NULL */
1626 if (!cpcm
) return -ENXIO
;
1628 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1629 mutex_lock(&chip
->spos_mutex
);
1630 if (cpcm
->pcm_channel
) {
1631 cs46xx_dsp_destroy_pcm_channel(chip
,cpcm
->pcm_channel
);
1632 cpcm
->pcm_channel
= NULL
;
1634 mutex_unlock(&chip
->spos_mutex
);
1636 chip
->playback_pcm
= NULL
;
1639 cpcm
->substream
= NULL
;
1640 snd_dma_free_pages(&cpcm
->hw_buf
);
1641 chip
->active_ctrl(chip
, -1);
1646 static int snd_cs46xx_capture_close(struct snd_pcm_substream
*substream
)
1648 struct snd_cs46xx
*chip
= snd_pcm_substream_chip(substream
);
1650 chip
->capt
.substream
= NULL
;
1651 snd_dma_free_pages(&chip
->capt
.hw_buf
);
1652 chip
->active_ctrl(chip
, -1);
1657 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1658 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops
= {
1659 .open
= snd_cs46xx_playback_open_rear
,
1660 .close
= snd_cs46xx_playback_close
,
1661 .ioctl
= snd_pcm_lib_ioctl
,
1662 .hw_params
= snd_cs46xx_playback_hw_params
,
1663 .hw_free
= snd_cs46xx_playback_hw_free
,
1664 .prepare
= snd_cs46xx_playback_prepare
,
1665 .trigger
= snd_cs46xx_playback_trigger
,
1666 .pointer
= snd_cs46xx_playback_direct_pointer
,
1669 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops
= {
1670 .open
= snd_cs46xx_playback_open_rear
,
1671 .close
= snd_cs46xx_playback_close
,
1672 .ioctl
= snd_pcm_lib_ioctl
,
1673 .hw_params
= snd_cs46xx_playback_hw_params
,
1674 .hw_free
= snd_cs46xx_playback_hw_free
,
1675 .prepare
= snd_cs46xx_playback_prepare
,
1676 .trigger
= snd_cs46xx_playback_trigger
,
1677 .pointer
= snd_cs46xx_playback_indirect_pointer
,
1678 .ack
= snd_cs46xx_playback_transfer
,
1681 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops
= {
1682 .open
= snd_cs46xx_playback_open_clfe
,
1683 .close
= snd_cs46xx_playback_close
,
1684 .ioctl
= snd_pcm_lib_ioctl
,
1685 .hw_params
= snd_cs46xx_playback_hw_params
,
1686 .hw_free
= snd_cs46xx_playback_hw_free
,
1687 .prepare
= snd_cs46xx_playback_prepare
,
1688 .trigger
= snd_cs46xx_playback_trigger
,
1689 .pointer
= snd_cs46xx_playback_direct_pointer
,
1692 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops
= {
1693 .open
= snd_cs46xx_playback_open_clfe
,
1694 .close
= snd_cs46xx_playback_close
,
1695 .ioctl
= snd_pcm_lib_ioctl
,
1696 .hw_params
= snd_cs46xx_playback_hw_params
,
1697 .hw_free
= snd_cs46xx_playback_hw_free
,
1698 .prepare
= snd_cs46xx_playback_prepare
,
1699 .trigger
= snd_cs46xx_playback_trigger
,
1700 .pointer
= snd_cs46xx_playback_indirect_pointer
,
1701 .ack
= snd_cs46xx_playback_transfer
,
1704 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops
= {
1705 .open
= snd_cs46xx_playback_open_iec958
,
1706 .close
= snd_cs46xx_playback_close_iec958
,
1707 .ioctl
= snd_pcm_lib_ioctl
,
1708 .hw_params
= snd_cs46xx_playback_hw_params
,
1709 .hw_free
= snd_cs46xx_playback_hw_free
,
1710 .prepare
= snd_cs46xx_playback_prepare
,
1711 .trigger
= snd_cs46xx_playback_trigger
,
1712 .pointer
= snd_cs46xx_playback_direct_pointer
,
1715 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops
= {
1716 .open
= snd_cs46xx_playback_open_iec958
,
1717 .close
= snd_cs46xx_playback_close_iec958
,
1718 .ioctl
= snd_pcm_lib_ioctl
,
1719 .hw_params
= snd_cs46xx_playback_hw_params
,
1720 .hw_free
= snd_cs46xx_playback_hw_free
,
1721 .prepare
= snd_cs46xx_playback_prepare
,
1722 .trigger
= snd_cs46xx_playback_trigger
,
1723 .pointer
= snd_cs46xx_playback_indirect_pointer
,
1724 .ack
= snd_cs46xx_playback_transfer
,
1729 static struct snd_pcm_ops snd_cs46xx_playback_ops
= {
1730 .open
= snd_cs46xx_playback_open
,
1731 .close
= snd_cs46xx_playback_close
,
1732 .ioctl
= snd_pcm_lib_ioctl
,
1733 .hw_params
= snd_cs46xx_playback_hw_params
,
1734 .hw_free
= snd_cs46xx_playback_hw_free
,
1735 .prepare
= snd_cs46xx_playback_prepare
,
1736 .trigger
= snd_cs46xx_playback_trigger
,
1737 .pointer
= snd_cs46xx_playback_direct_pointer
,
1740 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops
= {
1741 .open
= snd_cs46xx_playback_open
,
1742 .close
= snd_cs46xx_playback_close
,
1743 .ioctl
= snd_pcm_lib_ioctl
,
1744 .hw_params
= snd_cs46xx_playback_hw_params
,
1745 .hw_free
= snd_cs46xx_playback_hw_free
,
1746 .prepare
= snd_cs46xx_playback_prepare
,
1747 .trigger
= snd_cs46xx_playback_trigger
,
1748 .pointer
= snd_cs46xx_playback_indirect_pointer
,
1749 .ack
= snd_cs46xx_playback_transfer
,
1752 static struct snd_pcm_ops snd_cs46xx_capture_ops
= {
1753 .open
= snd_cs46xx_capture_open
,
1754 .close
= snd_cs46xx_capture_close
,
1755 .ioctl
= snd_pcm_lib_ioctl
,
1756 .hw_params
= snd_cs46xx_capture_hw_params
,
1757 .hw_free
= snd_cs46xx_capture_hw_free
,
1758 .prepare
= snd_cs46xx_capture_prepare
,
1759 .trigger
= snd_cs46xx_capture_trigger
,
1760 .pointer
= snd_cs46xx_capture_direct_pointer
,
1763 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops
= {
1764 .open
= snd_cs46xx_capture_open
,
1765 .close
= snd_cs46xx_capture_close
,
1766 .ioctl
= snd_pcm_lib_ioctl
,
1767 .hw_params
= snd_cs46xx_capture_hw_params
,
1768 .hw_free
= snd_cs46xx_capture_hw_free
,
1769 .prepare
= snd_cs46xx_capture_prepare
,
1770 .trigger
= snd_cs46xx_capture_trigger
,
1771 .pointer
= snd_cs46xx_capture_indirect_pointer
,
1772 .ack
= snd_cs46xx_capture_transfer
,
1775 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1776 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
1778 #define MAX_PLAYBACK_CHANNELS 1
1781 int snd_cs46xx_pcm(struct snd_cs46xx
*chip
, int device
)
1783 struct snd_pcm
*pcm
;
1786 if ((err
= snd_pcm_new(chip
->card
, "CS46xx", device
, MAX_PLAYBACK_CHANNELS
, 1, &pcm
)) < 0)
1789 pcm
->private_data
= chip
;
1791 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cs46xx_playback_ops
);
1792 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_cs46xx_capture_ops
);
1795 pcm
->info_flags
= 0;
1796 strcpy(pcm
->name
, "CS46xx");
1799 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1800 snd_dma_pci_data(chip
->pci
), 64*1024, 256*1024);
1806 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1807 int snd_cs46xx_pcm_rear(struct snd_cs46xx
*chip
, int device
)
1809 struct snd_pcm
*pcm
;
1812 if ((err
= snd_pcm_new(chip
->card
, "CS46xx - Rear", device
, MAX_PLAYBACK_CHANNELS
, 0, &pcm
)) < 0)
1815 pcm
->private_data
= chip
;
1817 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cs46xx_playback_rear_ops
);
1820 pcm
->info_flags
= 0;
1821 strcpy(pcm
->name
, "CS46xx - Rear");
1822 chip
->pcm_rear
= pcm
;
1824 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1825 snd_dma_pci_data(chip
->pci
), 64*1024, 256*1024);
1830 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx
*chip
, int device
)
1832 struct snd_pcm
*pcm
;
1835 if ((err
= snd_pcm_new(chip
->card
, "CS46xx - Center LFE", device
, MAX_PLAYBACK_CHANNELS
, 0, &pcm
)) < 0)
1838 pcm
->private_data
= chip
;
1840 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cs46xx_playback_clfe_ops
);
1843 pcm
->info_flags
= 0;
1844 strcpy(pcm
->name
, "CS46xx - Center LFE");
1845 chip
->pcm_center_lfe
= pcm
;
1847 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1848 snd_dma_pci_data(chip
->pci
), 64*1024, 256*1024);
1853 int snd_cs46xx_pcm_iec958(struct snd_cs46xx
*chip
, int device
)
1855 struct snd_pcm
*pcm
;
1858 if ((err
= snd_pcm_new(chip
->card
, "CS46xx - IEC958", device
, 1, 0, &pcm
)) < 0)
1861 pcm
->private_data
= chip
;
1863 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cs46xx_playback_iec958_ops
);
1866 pcm
->info_flags
= 0;
1867 strcpy(pcm
->name
, "CS46xx - IEC958");
1868 chip
->pcm_rear
= pcm
;
1870 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1871 snd_dma_pci_data(chip
->pci
), 64*1024, 256*1024);
1880 static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus
*bus
)
1882 struct snd_cs46xx
*chip
= bus
->private_data
;
1884 chip
->ac97_bus
= NULL
;
1887 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97
*ac97
)
1889 struct snd_cs46xx
*chip
= ac97
->private_data
;
1891 if (snd_BUG_ON(ac97
!= chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
] &&
1892 ac97
!= chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
]))
1895 if (ac97
== chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
]) {
1896 chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
] = NULL
;
1897 chip
->eapd_switch
= NULL
;
1900 chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
] = NULL
;
1903 static int snd_cs46xx_vol_info(struct snd_kcontrol
*kcontrol
,
1904 struct snd_ctl_elem_info
*uinfo
)
1906 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
1908 uinfo
->value
.integer
.min
= 0;
1909 uinfo
->value
.integer
.max
= 0x7fff;
1913 static int snd_cs46xx_vol_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1915 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
1916 int reg
= kcontrol
->private_value
;
1917 unsigned int val
= snd_cs46xx_peek(chip
, reg
);
1918 ucontrol
->value
.integer
.value
[0] = 0xffff - (val
>> 16);
1919 ucontrol
->value
.integer
.value
[1] = 0xffff - (val
& 0xffff);
1923 static int snd_cs46xx_vol_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1925 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
1926 int reg
= kcontrol
->private_value
;
1927 unsigned int val
= ((0xffff - ucontrol
->value
.integer
.value
[0]) << 16 |
1928 (0xffff - ucontrol
->value
.integer
.value
[1]));
1929 unsigned int old
= snd_cs46xx_peek(chip
, reg
);
1930 int change
= (old
!= val
);
1933 snd_cs46xx_poke(chip
, reg
, val
);
1939 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1941 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1943 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
1945 ucontrol
->value
.integer
.value
[0] = chip
->dsp_spos_instance
->dac_volume_left
;
1946 ucontrol
->value
.integer
.value
[1] = chip
->dsp_spos_instance
->dac_volume_right
;
1951 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1953 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
1956 if (chip
->dsp_spos_instance
->dac_volume_right
!= ucontrol
->value
.integer
.value
[0] ||
1957 chip
->dsp_spos_instance
->dac_volume_left
!= ucontrol
->value
.integer
.value
[1]) {
1958 cs46xx_dsp_set_dac_volume(chip
,
1959 ucontrol
->value
.integer
.value
[0],
1960 ucontrol
->value
.integer
.value
[1]);
1968 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1970 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
1972 ucontrol
->value
.integer
.value
[0] = chip
->dsp_spos_instance
->spdif_input_volume_left
;
1973 ucontrol
->value
.integer
.value
[1] = chip
->dsp_spos_instance
->spdif_input_volume_right
;
1977 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1979 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
1982 if (chip
->dsp_spos_instance
->spdif_input_volume_left
!= ucontrol
->value
.integer
.value
[0] ||
1983 chip
->dsp_spos_instance
->spdif_input_volume_right
!= ucontrol
->value
.integer
.value
[1]) {
1984 cs46xx_dsp_set_iec958_volume (chip
,
1985 ucontrol
->value
.integer
.value
[0],
1986 ucontrol
->value
.integer
.value
[1]);
1994 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info
1996 static int snd_cs46xx_iec958_get(struct snd_kcontrol
*kcontrol
,
1997 struct snd_ctl_elem_value
*ucontrol
)
1999 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2000 int reg
= kcontrol
->private_value
;
2002 if (reg
== CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT
)
2003 ucontrol
->value
.integer
.value
[0] = (chip
->dsp_spos_instance
->spdif_status_out
& DSP_SPDIF_STATUS_OUTPUT_ENABLED
);
2005 ucontrol
->value
.integer
.value
[0] = chip
->dsp_spos_instance
->spdif_status_in
;
2010 static int snd_cs46xx_iec958_put(struct snd_kcontrol
*kcontrol
,
2011 struct snd_ctl_elem_value
*ucontrol
)
2013 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2016 switch (kcontrol
->private_value
) {
2017 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT
:
2018 mutex_lock(&chip
->spos_mutex
);
2019 change
= (chip
->dsp_spos_instance
->spdif_status_out
& DSP_SPDIF_STATUS_OUTPUT_ENABLED
);
2020 if (ucontrol
->value
.integer
.value
[0] && !change
)
2021 cs46xx_dsp_enable_spdif_out(chip
);
2022 else if (change
&& !ucontrol
->value
.integer
.value
[0])
2023 cs46xx_dsp_disable_spdif_out(chip
);
2025 res
= (change
!= (chip
->dsp_spos_instance
->spdif_status_out
& DSP_SPDIF_STATUS_OUTPUT_ENABLED
));
2026 mutex_unlock(&chip
->spos_mutex
);
2028 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT
:
2029 change
= chip
->dsp_spos_instance
->spdif_status_in
;
2030 if (ucontrol
->value
.integer
.value
[0] && !change
) {
2031 cs46xx_dsp_enable_spdif_in(chip
);
2032 /* restore volume */
2034 else if (change
&& !ucontrol
->value
.integer
.value
[0])
2035 cs46xx_dsp_disable_spdif_in(chip
);
2037 res
= (change
!= chip
->dsp_spos_instance
->spdif_status_in
);
2041 snd_BUG(); /* should never happen ... */
2047 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol
*kcontrol
,
2048 struct snd_ctl_elem_value
*ucontrol
)
2050 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2051 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2053 if (ins
->adc_input
!= NULL
)
2054 ucontrol
->value
.integer
.value
[0] = 1;
2056 ucontrol
->value
.integer
.value
[0] = 0;
2061 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol
*kcontrol
,
2062 struct snd_ctl_elem_value
*ucontrol
)
2064 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2065 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2068 if (ucontrol
->value
.integer
.value
[0] && !ins
->adc_input
) {
2069 cs46xx_dsp_enable_adc_capture(chip
);
2071 } else if (!ucontrol
->value
.integer
.value
[0] && ins
->adc_input
) {
2072 cs46xx_dsp_disable_adc_capture(chip
);
2078 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol
*kcontrol
,
2079 struct snd_ctl_elem_value
*ucontrol
)
2081 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2082 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2084 if (ins
->pcm_input
!= NULL
)
2085 ucontrol
->value
.integer
.value
[0] = 1;
2087 ucontrol
->value
.integer
.value
[0] = 0;
2093 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol
*kcontrol
,
2094 struct snd_ctl_elem_value
*ucontrol
)
2096 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2097 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2100 if (ucontrol
->value
.integer
.value
[0] && !ins
->pcm_input
) {
2101 cs46xx_dsp_enable_pcm_capture(chip
);
2103 } else if (!ucontrol
->value
.integer
.value
[0] && ins
->pcm_input
) {
2104 cs46xx_dsp_disable_pcm_capture(chip
);
2111 static int snd_herc_spdif_select_get(struct snd_kcontrol
*kcontrol
,
2112 struct snd_ctl_elem_value
*ucontrol
)
2114 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2116 int val1
= snd_cs46xx_peekBA0(chip
, BA0_EGPIODR
);
2118 if (val1
& EGPIODR_GPOE0
)
2119 ucontrol
->value
.integer
.value
[0] = 1;
2121 ucontrol
->value
.integer
.value
[0] = 0;
2127 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
2129 static int snd_herc_spdif_select_put(struct snd_kcontrol
*kcontrol
,
2130 struct snd_ctl_elem_value
*ucontrol
)
2132 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2133 int val1
= snd_cs46xx_peekBA0(chip
, BA0_EGPIODR
);
2134 int val2
= snd_cs46xx_peekBA0(chip
, BA0_EGPIOPTR
);
2136 if (ucontrol
->value
.integer
.value
[0]) {
2137 /* optical is default */
2138 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
,
2139 EGPIODR_GPOE0
| val1
); /* enable EGPIO0 output */
2140 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
,
2141 EGPIOPTR_GPPT0
| val2
); /* open-drain on output */
2144 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
, val1
& ~EGPIODR_GPOE0
); /* disable */
2145 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
, val2
& ~EGPIOPTR_GPPT0
); /* disable */
2148 /* checking diff from the EGPIO direction register
2150 return (val1
!= (int)snd_cs46xx_peekBA0(chip
, BA0_EGPIODR
));
2154 static int snd_cs46xx_spdif_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2156 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
2161 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol
*kcontrol
,
2162 struct snd_ctl_elem_value
*ucontrol
)
2164 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2165 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2167 mutex_lock(&chip
->spos_mutex
);
2168 ucontrol
->value
.iec958
.status
[0] = _wrap_all_bits((ins
->spdif_csuv_default
>> 24) & 0xff);
2169 ucontrol
->value
.iec958
.status
[1] = _wrap_all_bits((ins
->spdif_csuv_default
>> 16) & 0xff);
2170 ucontrol
->value
.iec958
.status
[2] = 0;
2171 ucontrol
->value
.iec958
.status
[3] = _wrap_all_bits((ins
->spdif_csuv_default
) & 0xff);
2172 mutex_unlock(&chip
->spos_mutex
);
2177 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol
*kcontrol
,
2178 struct snd_ctl_elem_value
*ucontrol
)
2180 struct snd_cs46xx
* chip
= snd_kcontrol_chip(kcontrol
);
2181 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2185 mutex_lock(&chip
->spos_mutex
);
2186 val
= ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[0]) << 24) |
2187 ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[2]) << 16) |
2188 ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[3])) |
2189 /* left and right validity bit */
2190 (1 << 13) | (1 << 12);
2193 change
= (unsigned int)ins
->spdif_csuv_default
!= val
;
2194 ins
->spdif_csuv_default
= val
;
2196 if ( !(ins
->spdif_status_out
& DSP_SPDIF_STATUS_PLAYBACK_OPEN
) )
2197 cs46xx_poke_via_dsp (chip
,SP_SPDOUT_CSUV
,val
);
2199 mutex_unlock(&chip
->spos_mutex
);
2204 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol
*kcontrol
,
2205 struct snd_ctl_elem_value
*ucontrol
)
2207 ucontrol
->value
.iec958
.status
[0] = 0xff;
2208 ucontrol
->value
.iec958
.status
[1] = 0xff;
2209 ucontrol
->value
.iec958
.status
[2] = 0x00;
2210 ucontrol
->value
.iec958
.status
[3] = 0xff;
2214 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol
*kcontrol
,
2215 struct snd_ctl_elem_value
*ucontrol
)
2217 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2218 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2220 mutex_lock(&chip
->spos_mutex
);
2221 ucontrol
->value
.iec958
.status
[0] = _wrap_all_bits((ins
->spdif_csuv_stream
>> 24) & 0xff);
2222 ucontrol
->value
.iec958
.status
[1] = _wrap_all_bits((ins
->spdif_csuv_stream
>> 16) & 0xff);
2223 ucontrol
->value
.iec958
.status
[2] = 0;
2224 ucontrol
->value
.iec958
.status
[3] = _wrap_all_bits((ins
->spdif_csuv_stream
) & 0xff);
2225 mutex_unlock(&chip
->spos_mutex
);
2230 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol
*kcontrol
,
2231 struct snd_ctl_elem_value
*ucontrol
)
2233 struct snd_cs46xx
* chip
= snd_kcontrol_chip(kcontrol
);
2234 struct dsp_spos_instance
* ins
= chip
->dsp_spos_instance
;
2238 mutex_lock(&chip
->spos_mutex
);
2239 val
= ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[0]) << 24) |
2240 ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[1]) << 16) |
2241 ((unsigned int)_wrap_all_bits(ucontrol
->value
.iec958
.status
[3])) |
2242 /* left and right validity bit */
2243 (1 << 13) | (1 << 12);
2246 change
= ins
->spdif_csuv_stream
!= val
;
2247 ins
->spdif_csuv_stream
= val
;
2249 if ( ins
->spdif_status_out
& DSP_SPDIF_STATUS_PLAYBACK_OPEN
)
2250 cs46xx_poke_via_dsp (chip
,SP_SPDOUT_CSUV
,val
);
2252 mutex_unlock(&chip
->spos_mutex
);
2257 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2260 static struct snd_kcontrol_new snd_cs46xx_controls
[] = {
2262 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2263 .name
= "DAC Volume",
2264 .info
= snd_cs46xx_vol_info
,
2265 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2266 .get
= snd_cs46xx_vol_get
,
2267 .put
= snd_cs46xx_vol_put
,
2268 .private_value
= BA1_PVOL
,
2270 .get
= snd_cs46xx_vol_dac_get
,
2271 .put
= snd_cs46xx_vol_dac_put
,
2276 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2277 .name
= "ADC Volume",
2278 .info
= snd_cs46xx_vol_info
,
2279 .get
= snd_cs46xx_vol_get
,
2280 .put
= snd_cs46xx_vol_put
,
2281 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2282 .private_value
= BA1_CVOL
,
2284 .private_value
= (VARIDECIMATE_SCB_ADDR
+ 0xE) << 2,
2287 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2289 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2290 .name
= "ADC Capture Switch",
2291 .info
= snd_mixer_boolean_info
,
2292 .get
= snd_cs46xx_adc_capture_get
,
2293 .put
= snd_cs46xx_adc_capture_put
2296 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2297 .name
= "DAC Capture Switch",
2298 .info
= snd_mixer_boolean_info
,
2299 .get
= snd_cs46xx_pcm_capture_get
,
2300 .put
= snd_cs46xx_pcm_capture_put
2303 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2304 .name
= SNDRV_CTL_NAME_IEC958("Output ",NONE
,SWITCH
),
2305 .info
= snd_mixer_boolean_info
,
2306 .get
= snd_cs46xx_iec958_get
,
2307 .put
= snd_cs46xx_iec958_put
,
2308 .private_value
= CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT
,
2311 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2312 .name
= SNDRV_CTL_NAME_IEC958("Input ",NONE
,SWITCH
),
2313 .info
= snd_mixer_boolean_info
,
2314 .get
= snd_cs46xx_iec958_get
,
2315 .put
= snd_cs46xx_iec958_put
,
2316 .private_value
= CS46XX_MIXER_SPDIF_INPUT_ELEMENT
,
2319 /* Input IEC958 volume does not work for the moment. (Benny) */
2321 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2322 .name
= SNDRV_CTL_NAME_IEC958("Input ",NONE
,VOLUME
),
2323 .info
= snd_cs46xx_vol_info
,
2324 .get
= snd_cs46xx_vol_iec958_get
,
2325 .put
= snd_cs46xx_vol_iec958_put
,
2326 .private_value
= (ASYNCRX_SCB_ADDR
+ 0xE) << 2,
2330 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2331 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,DEFAULT
),
2332 .info
= snd_cs46xx_spdif_info
,
2333 .get
= snd_cs46xx_spdif_default_get
,
2334 .put
= snd_cs46xx_spdif_default_put
,
2337 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2338 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,MASK
),
2339 .info
= snd_cs46xx_spdif_info
,
2340 .get
= snd_cs46xx_spdif_mask_get
,
2341 .access
= SNDRV_CTL_ELEM_ACCESS_READ
2344 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2345 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PCM_STREAM
),
2346 .info
= snd_cs46xx_spdif_info
,
2347 .get
= snd_cs46xx_spdif_stream_get
,
2348 .put
= snd_cs46xx_spdif_stream_put
2354 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2355 /* set primary cs4294 codec into Extended Audio Mode */
2356 static int snd_cs46xx_front_dup_get(struct snd_kcontrol
*kcontrol
,
2357 struct snd_ctl_elem_value
*ucontrol
)
2359 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2361 val
= snd_ac97_read(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
], AC97_CSR_ACMODE
);
2362 ucontrol
->value
.integer
.value
[0] = (val
& 0x200) ? 0 : 1;
2366 static int snd_cs46xx_front_dup_put(struct snd_kcontrol
*kcontrol
,
2367 struct snd_ctl_elem_value
*ucontrol
)
2369 struct snd_cs46xx
*chip
= snd_kcontrol_chip(kcontrol
);
2370 return snd_ac97_update_bits(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
],
2371 AC97_CSR_ACMODE
, 0x200,
2372 ucontrol
->value
.integer
.value
[0] ? 0 : 0x200);
2375 static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl
= {
2376 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2377 .name
= "Duplicate Front",
2378 .info
= snd_mixer_boolean_info
,
2379 .get
= snd_cs46xx_front_dup_get
,
2380 .put
= snd_cs46xx_front_dup_put
,
2384 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2385 /* Only available on the Hercules Game Theater XP soundcard */
2386 static struct snd_kcontrol_new snd_hercules_controls
[] = {
2388 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2389 .name
= "Optical/Coaxial SPDIF Input Switch",
2390 .info
= snd_mixer_boolean_info
,
2391 .get
= snd_herc_spdif_select_get
,
2392 .put
= snd_herc_spdif_select_put
,
2397 static void snd_cs46xx_codec_reset (struct snd_ac97
* ac97
)
2399 unsigned long end_time
;
2402 /* reset to defaults */
2403 snd_ac97_write(ac97
, AC97_RESET
, 0);
2405 /* set the desired CODEC mode */
2406 if (ac97
->num
== CS46XX_PRIMARY_CODEC_INDEX
) {
2407 dev_dbg(ac97
->bus
->card
->dev
, "CODEC1 mode %04x\n", 0x0);
2408 snd_cs46xx_ac97_write(ac97
, AC97_CSR_ACMODE
, 0x0);
2409 } else if (ac97
->num
== CS46XX_SECONDARY_CODEC_INDEX
) {
2410 dev_dbg(ac97
->bus
->card
->dev
, "CODEC2 mode %04x\n", 0x3);
2411 snd_cs46xx_ac97_write(ac97
, AC97_CSR_ACMODE
, 0x3);
2413 snd_BUG(); /* should never happen ... */
2418 /* it's necessary to wait awhile until registers are accessible after RESET */
2419 /* because the PCM or MASTER volume registers can be modified, */
2420 /* the REC_GAIN register is used for tests */
2421 end_time
= jiffies
+ HZ
;
2423 unsigned short ext_mid
;
2425 /* use preliminary reads to settle the communication */
2426 snd_ac97_read(ac97
, AC97_RESET
);
2427 snd_ac97_read(ac97
, AC97_VENDOR_ID1
);
2428 snd_ac97_read(ac97
, AC97_VENDOR_ID2
);
2430 ext_mid
= snd_ac97_read(ac97
, AC97_EXTENDED_MID
);
2431 if (ext_mid
!= 0xffff && (ext_mid
& 1) != 0)
2434 /* test if we can write to the record gain volume register */
2435 snd_ac97_write(ac97
, AC97_REC_GAIN
, 0x8a05);
2436 if ((err
= snd_ac97_read(ac97
, AC97_REC_GAIN
)) == 0x8a05)
2440 } while (time_after_eq(end_time
, jiffies
));
2442 dev_err(ac97
->bus
->card
->dev
,
2443 "CS46xx secondary codec doesn't respond!\n");
2447 static int cs46xx_detect_codec(struct snd_cs46xx
*chip
, int codec
)
2450 struct snd_ac97_template ac97
;
2452 memset(&ac97
, 0, sizeof(ac97
));
2453 ac97
.private_data
= chip
;
2454 ac97
.private_free
= snd_cs46xx_mixer_free_ac97
;
2456 if (chip
->amplifier_ctrl
== amp_voyetra
)
2457 ac97
.scaps
= AC97_SCAP_INV_EAPD
;
2459 if (codec
== CS46XX_SECONDARY_CODEC_INDEX
) {
2460 snd_cs46xx_codec_write(chip
, AC97_RESET
, 0, codec
);
2462 if (snd_cs46xx_codec_read(chip
, AC97_RESET
, codec
) & 0x8000) {
2463 dev_dbg(chip
->card
->dev
,
2464 "seconadry codec not present\n");
2469 snd_cs46xx_codec_write(chip
, AC97_MASTER
, 0x8000, codec
);
2470 for (idx
= 0; idx
< 100; ++idx
) {
2471 if (snd_cs46xx_codec_read(chip
, AC97_MASTER
, codec
) == 0x8000) {
2472 err
= snd_ac97_mixer(chip
->ac97_bus
, &ac97
, &chip
->ac97
[codec
]);
2477 dev_dbg(chip
->card
->dev
, "codec %d detection timeout\n", codec
);
2481 int snd_cs46xx_mixer(struct snd_cs46xx
*chip
, int spdif_device
)
2483 struct snd_card
*card
= chip
->card
;
2484 struct snd_ctl_elem_id id
;
2487 static struct snd_ac97_bus_ops ops
= {
2488 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2489 .reset
= snd_cs46xx_codec_reset
,
2491 .write
= snd_cs46xx_ac97_write
,
2492 .read
= snd_cs46xx_ac97_read
,
2495 /* detect primary codec */
2496 chip
->nr_ac97_codecs
= 0;
2497 dev_dbg(chip
->card
->dev
, "detecting primary codec\n");
2498 if ((err
= snd_ac97_bus(card
, 0, &ops
, chip
, &chip
->ac97_bus
)) < 0)
2500 chip
->ac97_bus
->private_free
= snd_cs46xx_mixer_free_ac97_bus
;
2502 if (cs46xx_detect_codec(chip
, CS46XX_PRIMARY_CODEC_INDEX
) < 0)
2504 chip
->nr_ac97_codecs
= 1;
2506 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2507 dev_dbg(chip
->card
->dev
, "detecting seconadry codec\n");
2508 /* try detect a secondary codec */
2509 if (! cs46xx_detect_codec(chip
, CS46XX_SECONDARY_CODEC_INDEX
))
2510 chip
->nr_ac97_codecs
= 2;
2511 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2513 /* add cs4630 mixer controls */
2514 for (idx
= 0; idx
< ARRAY_SIZE(snd_cs46xx_controls
); idx
++) {
2515 struct snd_kcontrol
*kctl
;
2516 kctl
= snd_ctl_new1(&snd_cs46xx_controls
[idx
], chip
);
2517 if (kctl
&& kctl
->id
.iface
== SNDRV_CTL_ELEM_IFACE_PCM
)
2518 kctl
->id
.device
= spdif_device
;
2519 if ((err
= snd_ctl_add(card
, kctl
)) < 0)
2523 /* get EAPD mixer switch (for voyetra hack) */
2524 memset(&id
, 0, sizeof(id
));
2525 id
.iface
= SNDRV_CTL_ELEM_IFACE_MIXER
;
2526 strcpy(id
.name
, "External Amplifier");
2527 chip
->eapd_switch
= snd_ctl_find_id(chip
->card
, &id
);
2529 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2530 if (chip
->nr_ac97_codecs
== 1) {
2531 unsigned int id2
= chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
]->id
& 0xffff;
2532 if (id2
== 0x592b || id2
== 0x592d) {
2533 err
= snd_ctl_add(card
, snd_ctl_new1(&snd_cs46xx_front_dup_ctl
, chip
));
2536 snd_ac97_write_cache(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
],
2537 AC97_CSR_ACMODE
, 0x200);
2540 /* do soundcard specific mixer setup */
2541 if (chip
->mixer_init
) {
2542 dev_dbg(chip
->card
->dev
, "calling chip->mixer_init(chip);\n");
2543 chip
->mixer_init(chip
);
2547 /* turn on amplifier */
2548 chip
->amplifier_ctrl(chip
, 1);
2557 static void snd_cs46xx_midi_reset(struct snd_cs46xx
*chip
)
2559 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, MIDCR_MRST
);
2561 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2564 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream
*substream
)
2566 struct snd_cs46xx
*chip
= substream
->rmidi
->private_data
;
2568 chip
->active_ctrl(chip
, 1);
2569 spin_lock_irq(&chip
->reg_lock
);
2570 chip
->uartm
|= CS46XX_MODE_INPUT
;
2571 chip
->midcr
|= MIDCR_RXE
;
2572 chip
->midi_input
= substream
;
2573 if (!(chip
->uartm
& CS46XX_MODE_OUTPUT
)) {
2574 snd_cs46xx_midi_reset(chip
);
2576 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2578 spin_unlock_irq(&chip
->reg_lock
);
2582 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream
*substream
)
2584 struct snd_cs46xx
*chip
= substream
->rmidi
->private_data
;
2586 spin_lock_irq(&chip
->reg_lock
);
2587 chip
->midcr
&= ~(MIDCR_RXE
| MIDCR_RIE
);
2588 chip
->midi_input
= NULL
;
2589 if (!(chip
->uartm
& CS46XX_MODE_OUTPUT
)) {
2590 snd_cs46xx_midi_reset(chip
);
2592 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2594 chip
->uartm
&= ~CS46XX_MODE_INPUT
;
2595 spin_unlock_irq(&chip
->reg_lock
);
2596 chip
->active_ctrl(chip
, -1);
2600 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream
*substream
)
2602 struct snd_cs46xx
*chip
= substream
->rmidi
->private_data
;
2604 chip
->active_ctrl(chip
, 1);
2606 spin_lock_irq(&chip
->reg_lock
);
2607 chip
->uartm
|= CS46XX_MODE_OUTPUT
;
2608 chip
->midcr
|= MIDCR_TXE
;
2609 chip
->midi_output
= substream
;
2610 if (!(chip
->uartm
& CS46XX_MODE_INPUT
)) {
2611 snd_cs46xx_midi_reset(chip
);
2613 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2615 spin_unlock_irq(&chip
->reg_lock
);
2619 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream
*substream
)
2621 struct snd_cs46xx
*chip
= substream
->rmidi
->private_data
;
2623 spin_lock_irq(&chip
->reg_lock
);
2624 chip
->midcr
&= ~(MIDCR_TXE
| MIDCR_TIE
);
2625 chip
->midi_output
= NULL
;
2626 if (!(chip
->uartm
& CS46XX_MODE_INPUT
)) {
2627 snd_cs46xx_midi_reset(chip
);
2629 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2631 chip
->uartm
&= ~CS46XX_MODE_OUTPUT
;
2632 spin_unlock_irq(&chip
->reg_lock
);
2633 chip
->active_ctrl(chip
, -1);
2637 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream
*substream
, int up
)
2639 unsigned long flags
;
2640 struct snd_cs46xx
*chip
= substream
->rmidi
->private_data
;
2642 spin_lock_irqsave(&chip
->reg_lock
, flags
);
2644 if ((chip
->midcr
& MIDCR_RIE
) == 0) {
2645 chip
->midcr
|= MIDCR_RIE
;
2646 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2649 if (chip
->midcr
& MIDCR_RIE
) {
2650 chip
->midcr
&= ~MIDCR_RIE
;
2651 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2654 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
2657 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream
*substream
, int up
)
2659 unsigned long flags
;
2660 struct snd_cs46xx
*chip
= substream
->rmidi
->private_data
;
2663 spin_lock_irqsave(&chip
->reg_lock
, flags
);
2665 if ((chip
->midcr
& MIDCR_TIE
) == 0) {
2666 chip
->midcr
|= MIDCR_TIE
;
2667 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2668 while ((chip
->midcr
& MIDCR_TIE
) &&
2669 (snd_cs46xx_peekBA0(chip
, BA0_MIDSR
) & MIDSR_TBF
) == 0) {
2670 if (snd_rawmidi_transmit(substream
, &byte
, 1) != 1) {
2671 chip
->midcr
&= ~MIDCR_TIE
;
2673 snd_cs46xx_pokeBA0(chip
, BA0_MIDWP
, byte
);
2676 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2679 if (chip
->midcr
& MIDCR_TIE
) {
2680 chip
->midcr
&= ~MIDCR_TIE
;
2681 snd_cs46xx_pokeBA0(chip
, BA0_MIDCR
, chip
->midcr
);
2684 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
2687 static struct snd_rawmidi_ops snd_cs46xx_midi_output
=
2689 .open
= snd_cs46xx_midi_output_open
,
2690 .close
= snd_cs46xx_midi_output_close
,
2691 .trigger
= snd_cs46xx_midi_output_trigger
,
2694 static struct snd_rawmidi_ops snd_cs46xx_midi_input
=
2696 .open
= snd_cs46xx_midi_input_open
,
2697 .close
= snd_cs46xx_midi_input_close
,
2698 .trigger
= snd_cs46xx_midi_input_trigger
,
2701 int snd_cs46xx_midi(struct snd_cs46xx
*chip
, int device
)
2703 struct snd_rawmidi
*rmidi
;
2706 if ((err
= snd_rawmidi_new(chip
->card
, "CS46XX", device
, 1, 1, &rmidi
)) < 0)
2708 strcpy(rmidi
->name
, "CS46XX");
2709 snd_rawmidi_set_ops(rmidi
, SNDRV_RAWMIDI_STREAM_OUTPUT
, &snd_cs46xx_midi_output
);
2710 snd_rawmidi_set_ops(rmidi
, SNDRV_RAWMIDI_STREAM_INPUT
, &snd_cs46xx_midi_input
);
2711 rmidi
->info_flags
|= SNDRV_RAWMIDI_INFO_OUTPUT
| SNDRV_RAWMIDI_INFO_INPUT
| SNDRV_RAWMIDI_INFO_DUPLEX
;
2712 rmidi
->private_data
= chip
;
2713 chip
->rmidi
= rmidi
;
2719 * gameport interface
2722 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2724 static void snd_cs46xx_gameport_trigger(struct gameport
*gameport
)
2726 struct snd_cs46xx
*chip
= gameport_get_port_data(gameport
);
2728 if (snd_BUG_ON(!chip
))
2730 snd_cs46xx_pokeBA0(chip
, BA0_JSPT
, 0xFF); //outb(gameport->io, 0xFF);
2733 static unsigned char snd_cs46xx_gameport_read(struct gameport
*gameport
)
2735 struct snd_cs46xx
*chip
= gameport_get_port_data(gameport
);
2737 if (snd_BUG_ON(!chip
))
2739 return snd_cs46xx_peekBA0(chip
, BA0_JSPT
); //inb(gameport->io);
2742 static int snd_cs46xx_gameport_cooked_read(struct gameport
*gameport
, int *axes
, int *buttons
)
2744 struct snd_cs46xx
*chip
= gameport_get_port_data(gameport
);
2745 unsigned js1
, js2
, jst
;
2747 if (snd_BUG_ON(!chip
))
2750 js1
= snd_cs46xx_peekBA0(chip
, BA0_JSC1
);
2751 js2
= snd_cs46xx_peekBA0(chip
, BA0_JSC2
);
2752 jst
= snd_cs46xx_peekBA0(chip
, BA0_JSPT
);
2754 *buttons
= (~jst
>> 4) & 0x0F;
2756 axes
[0] = ((js1
& JSC1_Y1V_MASK
) >> JSC1_Y1V_SHIFT
) & 0xFFFF;
2757 axes
[1] = ((js1
& JSC1_X1V_MASK
) >> JSC1_X1V_SHIFT
) & 0xFFFF;
2758 axes
[2] = ((js2
& JSC2_Y2V_MASK
) >> JSC2_Y2V_SHIFT
) & 0xFFFF;
2759 axes
[3] = ((js2
& JSC2_X2V_MASK
) >> JSC2_X2V_SHIFT
) & 0xFFFF;
2761 for(jst
=0;jst
<4;++jst
)
2762 if(axes
[jst
]==0xFFFF) axes
[jst
] = -1;
2766 static int snd_cs46xx_gameport_open(struct gameport
*gameport
, int mode
)
2769 case GAMEPORT_MODE_COOKED
:
2771 case GAMEPORT_MODE_RAW
:
2779 int snd_cs46xx_gameport(struct snd_cs46xx
*chip
)
2781 struct gameport
*gp
;
2783 chip
->gameport
= gp
= gameport_allocate_port();
2785 dev_err(chip
->card
->dev
,
2786 "cannot allocate memory for gameport\n");
2790 gameport_set_name(gp
, "CS46xx Gameport");
2791 gameport_set_phys(gp
, "pci%s/gameport0", pci_name(chip
->pci
));
2792 gameport_set_dev_parent(gp
, &chip
->pci
->dev
);
2793 gameport_set_port_data(gp
, chip
);
2795 gp
->open
= snd_cs46xx_gameport_open
;
2796 gp
->read
= snd_cs46xx_gameport_read
;
2797 gp
->trigger
= snd_cs46xx_gameport_trigger
;
2798 gp
->cooked_read
= snd_cs46xx_gameport_cooked_read
;
2800 snd_cs46xx_pokeBA0(chip
, BA0_JSIO
, 0xFF); // ?
2801 snd_cs46xx_pokeBA0(chip
, BA0_JSCTL
, JSCTL_SP_MEDIUM_SLOW
);
2803 gameport_register_port(gp
);
2808 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx
*chip
)
2810 if (chip
->gameport
) {
2811 gameport_unregister_port(chip
->gameport
);
2812 chip
->gameport
= NULL
;
2816 int snd_cs46xx_gameport(struct snd_cs46xx
*chip
) { return -ENOSYS
; }
2817 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx
*chip
) { }
2818 #endif /* CONFIG_GAMEPORT */
2820 #ifdef CONFIG_PROC_FS
2825 static ssize_t
snd_cs46xx_io_read(struct snd_info_entry
*entry
,
2826 void *file_private_data
,
2827 struct file
*file
, char __user
*buf
,
2828 size_t count
, loff_t pos
)
2830 struct snd_cs46xx_region
*region
= entry
->private_data
;
2832 if (copy_to_user_fromio(buf
, region
->remap_addr
+ pos
, count
))
2837 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops
= {
2838 .read
= snd_cs46xx_io_read
,
2841 static int snd_cs46xx_proc_init(struct snd_card
*card
, struct snd_cs46xx
*chip
)
2843 struct snd_info_entry
*entry
;
2846 for (idx
= 0; idx
< 5; idx
++) {
2847 struct snd_cs46xx_region
*region
= &chip
->region
.idx
[idx
];
2848 if (! snd_card_proc_new(card
, region
->name
, &entry
)) {
2849 entry
->content
= SNDRV_INFO_CONTENT_DATA
;
2850 entry
->private_data
= chip
;
2851 entry
->c
.ops
= &snd_cs46xx_proc_io_ops
;
2852 entry
->size
= region
->size
;
2853 entry
->mode
= S_IFREG
| S_IRUSR
;
2856 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2857 cs46xx_dsp_proc_init(card
, chip
);
2862 static int snd_cs46xx_proc_done(struct snd_cs46xx
*chip
)
2864 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2865 cs46xx_dsp_proc_done(chip
);
2869 #else /* !CONFIG_PROC_FS */
2870 #define snd_cs46xx_proc_init(card, chip)
2871 #define snd_cs46xx_proc_done(chip)
2877 static void snd_cs46xx_hw_stop(struct snd_cs46xx
*chip
)
2881 tmp
= snd_cs46xx_peek(chip
, BA1_PFIE
);
2884 snd_cs46xx_poke(chip
, BA1_PFIE
, tmp
); /* playback interrupt disable */
2886 tmp
= snd_cs46xx_peek(chip
, BA1_CIE
);
2889 snd_cs46xx_poke(chip
, BA1_CIE
, tmp
); /* capture interrupt disable */
2892 * Stop playback DMA.
2894 tmp
= snd_cs46xx_peek(chip
, BA1_PCTL
);
2895 snd_cs46xx_poke(chip
, BA1_PCTL
, tmp
& 0x0000ffff);
2900 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
2901 snd_cs46xx_poke(chip
, BA1_CCTL
, tmp
& 0xffff0000);
2904 * Reset the processor.
2906 snd_cs46xx_reset(chip
);
2908 snd_cs46xx_proc_stop(chip
);
2911 * Power down the PLL.
2913 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, 0);
2916 * Turn off the Processor by turning off the software clock enable flag in
2917 * the clock control register.
2919 tmp
= snd_cs46xx_peekBA0(chip
, BA0_CLKCR1
) & ~CLKCR1_SWCE
;
2920 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
);
2924 static int snd_cs46xx_free(struct snd_cs46xx
*chip
)
2928 if (snd_BUG_ON(!chip
))
2931 if (chip
->active_ctrl
)
2932 chip
->active_ctrl(chip
, 1);
2934 snd_cs46xx_remove_gameport(chip
);
2936 if (chip
->amplifier_ctrl
)
2937 chip
->amplifier_ctrl(chip
, -chip
->amplifier
); /* force to off */
2939 snd_cs46xx_proc_done(chip
);
2941 if (chip
->region
.idx
[0].resource
)
2942 snd_cs46xx_hw_stop(chip
);
2945 free_irq(chip
->irq
, chip
);
2947 if (chip
->active_ctrl
)
2948 chip
->active_ctrl(chip
, -chip
->amplifier
);
2950 for (idx
= 0; idx
< 5; idx
++) {
2951 struct snd_cs46xx_region
*region
= &chip
->region
.idx
[idx
];
2953 iounmap(region
->remap_addr
);
2954 release_and_free_resource(region
->resource
);
2957 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2958 if (chip
->dsp_spos_instance
) {
2959 cs46xx_dsp_spos_destroy(chip
);
2960 chip
->dsp_spos_instance
= NULL
;
2962 for (idx
= 0; idx
< CS46XX_DSP_MODULES
; idx
++)
2963 free_module_desc(chip
->modules
[idx
]);
2968 #ifdef CONFIG_PM_SLEEP
2969 kfree(chip
->saved_regs
);
2972 pci_disable_device(chip
->pci
);
2977 static int snd_cs46xx_dev_free(struct snd_device
*device
)
2979 struct snd_cs46xx
*chip
= device
->device_data
;
2980 return snd_cs46xx_free(chip
);
2986 static int snd_cs46xx_chip_init(struct snd_cs46xx
*chip
)
2991 * First, blast the clock control register to zero so that the PLL starts
2992 * out in a known state, and blast the master serial port control register
2993 * to zero so that the serial ports also start out in a known state.
2995 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, 0);
2996 snd_cs46xx_pokeBA0(chip
, BA0_SERMC1
, 0);
2999 * If we are in AC97 mode, then we must set the part to a host controlled
3000 * AC-link. Otherwise, we won't be able to bring up the link.
3002 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3003 snd_cs46xx_pokeBA0(chip
, BA0_SERACC
, SERACC_HSP
| SERACC_CHIP_TYPE_2_0
|
3004 SERACC_TWO_CODECS
); /* 2.00 dual codecs */
3005 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
3007 snd_cs46xx_pokeBA0(chip
, BA0_SERACC
, SERACC_HSP
| SERACC_CHIP_TYPE_1_03
); /* 1.03 codec */
3011 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
3012 * spec) and then drive it high. This is done for non AC97 modes since
3013 * there might be logic external to the CS461x that uses the ARST# line
3016 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, 0);
3017 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3018 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL2
, 0);
3021 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_RSTN
);
3022 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3023 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL2
, ACCTL_RSTN
);
3027 * The first thing we do here is to enable sync generation. As soon
3028 * as we start receiving bit clock, we'll start producing the SYNC
3031 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_ESYN
| ACCTL_RSTN
);
3032 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3033 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL2
, ACCTL_ESYN
| ACCTL_RSTN
);
3037 * Now wait for a short while to allow the AC97 part to start
3038 * generating bit clock (so we don't try to start the PLL without an
3044 * Set the serial port timing configuration, so that
3045 * the clock control circuit gets its clock from the correct place.
3047 snd_cs46xx_pokeBA0(chip
, BA0_SERMC1
, SERMC1_PTC_AC97
);
3050 * Write the selected clock control setup to the hardware. Do not turn on
3051 * SWCE yet (if requested), so that the devices clocked by the output of
3052 * PLL are not clocked until the PLL is stable.
3054 snd_cs46xx_pokeBA0(chip
, BA0_PLLCC
, PLLCC_LPF_1050_2780_KHZ
| PLLCC_CDR_73_104_MHZ
);
3055 snd_cs46xx_pokeBA0(chip
, BA0_PLLM
, 0x3a);
3056 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR2
, CLKCR2_PDIVS_8
);
3061 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, CLKCR1_PLLP
);
3064 * Wait until the PLL has stabilized.
3069 * Turn on clocking of the core so that we can setup the serial ports.
3071 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, CLKCR1_PLLP
| CLKCR1_SWCE
);
3074 * Enable FIFO Host Bypass
3076 snd_cs46xx_pokeBA0(chip
, BA0_SERBCF
, SERBCF_HBP
);
3079 * Fill the serial port FIFOs with silence.
3081 snd_cs46xx_clear_serial_FIFOs(chip
);
3084 * Set the serial port FIFO pointer to the first sample in the FIFO.
3086 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
3089 * Write the serial port configuration to the part. The master
3090 * enable bit is not set until all other values have been written.
3092 snd_cs46xx_pokeBA0(chip
, BA0_SERC1
, SERC1_SO1F_AC97
| SERC1_SO1EN
);
3093 snd_cs46xx_pokeBA0(chip
, BA0_SERC2
, SERC2_SI1F_AC97
| SERC1_SO1EN
);
3094 snd_cs46xx_pokeBA0(chip
, BA0_SERMC1
, SERMC1_PTC_AC97
| SERMC1_MSPE
);
3097 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3098 snd_cs46xx_pokeBA0(chip
, BA0_SERC7
, SERC7_ASDI2EN
);
3099 snd_cs46xx_pokeBA0(chip
, BA0_SERC3
, 0);
3100 snd_cs46xx_pokeBA0(chip
, BA0_SERC4
, 0);
3101 snd_cs46xx_pokeBA0(chip
, BA0_SERC5
, 0);
3102 snd_cs46xx_pokeBA0(chip
, BA0_SERC6
, 1);
3109 * Wait for the codec ready signal from the AC97 codec.
3112 while (timeout
-- > 0) {
3114 * Read the AC97 status register to see if we've seen a CODEC READY
3115 * signal from the AC97 codec.
3117 if (snd_cs46xx_peekBA0(chip
, BA0_ACSTS
) & ACSTS_CRDY
)
3123 dev_err(chip
->card
->dev
,
3124 "create - never read codec ready from AC'97\n");
3125 dev_err(chip
->card
->dev
,
3126 "it is not probably bug, try to use CS4236 driver\n");
3129 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3132 for (count
= 0; count
< 150; count
++) {
3133 /* First, we want to wait for a short time. */
3136 if (snd_cs46xx_peekBA0(chip
, BA0_ACSTS2
) & ACSTS_CRDY
)
3141 * Make sure CODEC is READY.
3143 if (!(snd_cs46xx_peekBA0(chip
, BA0_ACSTS2
) & ACSTS_CRDY
))
3144 dev_dbg(chip
->card
->dev
,
3145 "never read card ready from secondary AC'97\n");
3150 * Assert the vaid frame signal so that we can start sending commands
3151 * to the AC97 codec.
3153 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL
, ACCTL_VFRM
| ACCTL_ESYN
| ACCTL_RSTN
);
3154 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3155 snd_cs46xx_pokeBA0(chip
, BA0_ACCTL2
, ACCTL_VFRM
| ACCTL_ESYN
| ACCTL_RSTN
);
3160 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
3161 * the codec is pumping ADC data across the AC-link.
3164 while (timeout
-- > 0) {
3166 * Read the input slot valid register and see if input slots 3 and
3169 if ((snd_cs46xx_peekBA0(chip
, BA0_ACISV
) & (ACISV_ISV3
| ACISV_ISV4
)) == (ACISV_ISV3
| ACISV_ISV4
))
3174 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3175 dev_err(chip
->card
->dev
,
3176 "create - never read ISV3 & ISV4 from AC'97\n");
3179 /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3180 Reloading the driver may help, if there's other soundcards
3181 with the same problem I would like to know. (Benny) */
3183 dev_err(chip
->card
->dev
, "never read ISV3 & ISV4 from AC'97\n");
3184 dev_err(chip
->card
->dev
,
3185 "Try reloading the ALSA driver, if you find something\n");
3186 dev_err(chip
->card
->dev
,
3187 "broken or not working on your soundcard upon\n");
3188 dev_err(chip
->card
->dev
,
3189 "this message please report to alsa-devel@alsa-project.org\n");
3196 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
3197 * commense the transfer of digital audio data to the AC97 codec.
3200 snd_cs46xx_pokeBA0(chip
, BA0_ACOSV
, ACOSV_SLV3
| ACOSV_SLV4
);
3204 * Power down the DAC and ADC. We will power them up (if) when we need
3207 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3210 * Turn off the Processor by turning off the software clock enable flag in
3211 * the clock control register.
3213 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3214 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3220 * start and load DSP
3223 static void cs46xx_enable_stream_irqs(struct snd_cs46xx
*chip
)
3227 snd_cs46xx_pokeBA0(chip
, BA0_HICR
, HICR_IEV
| HICR_CHGM
);
3229 tmp
= snd_cs46xx_peek(chip
, BA1_PFIE
);
3231 snd_cs46xx_poke(chip
, BA1_PFIE
, tmp
); /* playback interrupt enable */
3233 tmp
= snd_cs46xx_peek(chip
, BA1_CIE
);
3236 snd_cs46xx_poke(chip
, BA1_CIE
, tmp
); /* capture interrupt enable */
3239 int snd_cs46xx_start_dsp(struct snd_cs46xx
*chip
)
3242 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3248 * Reset the processor.
3250 snd_cs46xx_reset(chip
);
3252 * Download the image to the processor.
3254 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3255 for (i
= 0; i
< CS46XX_DSP_MODULES
; i
++) {
3256 err
= load_firmware(chip
, &chip
->modules
[i
], module_names
[i
]);
3258 dev_err(chip
->card
->dev
, "firmware load error [%s]\n",
3262 err
= cs46xx_dsp_load_module(chip
, chip
->modules
[i
]);
3264 dev_err(chip
->card
->dev
, "image download error [%s]\n",
3270 if (cs46xx_dsp_scb_and_task_init(chip
) < 0)
3273 err
= load_firmware(chip
);
3278 err
= snd_cs46xx_download_image(chip
);
3280 dev_err(chip
->card
->dev
, "image download error\n");
3285 * Stop playback DMA.
3287 tmp
= snd_cs46xx_peek(chip
, BA1_PCTL
);
3288 chip
->play_ctl
= tmp
& 0xffff0000;
3289 snd_cs46xx_poke(chip
, BA1_PCTL
, tmp
& 0x0000ffff);
3295 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
3296 chip
->capt
.ctl
= tmp
& 0x0000ffff;
3297 snd_cs46xx_poke(chip
, BA1_CCTL
, tmp
& 0xffff0000);
3301 snd_cs46xx_set_play_sample_rate(chip
, 8000);
3302 snd_cs46xx_set_capture_sample_rate(chip
, 8000);
3304 snd_cs46xx_proc_start(chip
);
3306 cs46xx_enable_stream_irqs(chip
);
3308 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3309 /* set the attenuation to 0dB */
3310 snd_cs46xx_poke(chip
, BA1_PVOL
, 0x80008000);
3311 snd_cs46xx_poke(chip
, BA1_CVOL
, 0x80008000);
3319 * AMP control - null AMP
3322 static void amp_none(struct snd_cs46xx
*chip
, int change
)
3326 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3327 static int voyetra_setup_eapd_slot(struct snd_cs46xx
*chip
)
3330 u32 idx
, valid_slots
,tmp
,powerdown
= 0;
3331 u16 modem_power
,pin_config
,logic_type
;
3333 dev_dbg(chip
->card
->dev
, "cs46xx_setup_eapd_slot()+\n");
3336 * See if the devices are powered down. If so, we must power them up first
3337 * or they will not respond.
3339 tmp
= snd_cs46xx_peekBA0(chip
, BA0_CLKCR1
);
3341 if (!(tmp
& CLKCR1_SWCE
)) {
3342 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
| CLKCR1_SWCE
);
3347 * Clear PRA. The Bonzo chip will be used for GPIO not for modem
3350 if(chip
->nr_ac97_codecs
!= 2) {
3351 dev_err(chip
->card
->dev
,
3352 "cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3356 modem_power
= snd_cs46xx_codec_read (chip
,
3357 AC97_EXTENDED_MSTATUS
,
3358 CS46XX_SECONDARY_CODEC_INDEX
);
3359 modem_power
&=0xFEFF;
3361 snd_cs46xx_codec_write(chip
,
3362 AC97_EXTENDED_MSTATUS
, modem_power
,
3363 CS46XX_SECONDARY_CODEC_INDEX
);
3366 * Set GPIO pin's 7 and 8 so that they are configured for output.
3368 pin_config
= snd_cs46xx_codec_read (chip
,
3370 CS46XX_SECONDARY_CODEC_INDEX
);
3373 snd_cs46xx_codec_write(chip
,
3374 AC97_GPIO_CFG
, pin_config
,
3375 CS46XX_SECONDARY_CODEC_INDEX
);
3378 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3381 logic_type
= snd_cs46xx_codec_read(chip
, AC97_GPIO_POLARITY
,
3382 CS46XX_SECONDARY_CODEC_INDEX
);
3385 snd_cs46xx_codec_write (chip
, AC97_GPIO_POLARITY
, logic_type
,
3386 CS46XX_SECONDARY_CODEC_INDEX
);
3388 valid_slots
= snd_cs46xx_peekBA0(chip
, BA0_ACOSV
);
3389 valid_slots
|= 0x200;
3390 snd_cs46xx_pokeBA0(chip
, BA0_ACOSV
, valid_slots
);
3392 if ( cs46xx_wait_for_fifo(chip
,1) ) {
3393 dev_dbg(chip
->card
->dev
, "FIFO is busy\n");
3399 * Fill slots 12 with the correct value for the GPIO pins.
3401 for(idx
= 0x90; idx
<= 0x9F; idx
++) {
3403 * Initialize the fifo so that bits 7 and 8 are on.
3405 * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3406 * the left. 0x1800 corresponds to bits 7 and 8.
3408 snd_cs46xx_pokeBA0(chip
, BA0_SERBWP
, 0x1800);
3411 * Wait for command to complete
3413 if ( cs46xx_wait_for_fifo(chip
,200) ) {
3414 dev_dbg(chip
->card
->dev
,
3415 "failed waiting for FIFO at addr (%02X)\n",
3422 * Write the serial port FIFO index.
3424 snd_cs46xx_pokeBA0(chip
, BA0_SERBAD
, idx
);
3427 * Tell the serial port to load the new value into the FIFO location.
3429 snd_cs46xx_pokeBA0(chip
, BA0_SERBCM
, SERBCM_WRC
);
3432 /* wait for last command to complete */
3433 cs46xx_wait_for_fifo(chip
,200);
3436 * Now, if we powered up the devices, then power them back down again.
3437 * This is kinda ugly, but should never happen.
3440 snd_cs46xx_pokeBA0(chip
, BA0_CLKCR1
, tmp
);
3450 static void amp_voyetra(struct snd_cs46xx
*chip
, int change
)
3452 /* Manage the EAPD bit on the Crystal 4297
3453 and the Analog AD1885 */
3455 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3456 int old
= chip
->amplifier
;
3460 chip
->amplifier
+= change
;
3461 oval
= snd_cs46xx_codec_read(chip
, AC97_POWERDOWN
,
3462 CS46XX_PRIMARY_CODEC_INDEX
);
3464 if (chip
->amplifier
) {
3465 /* Turn the EAPD amp on */
3468 /* Turn the EAPD amp off */
3472 snd_cs46xx_codec_write(chip
, AC97_POWERDOWN
, val
,
3473 CS46XX_PRIMARY_CODEC_INDEX
);
3474 if (chip
->eapd_switch
)
3475 snd_ctl_notify(chip
->card
, SNDRV_CTL_EVENT_MASK_VALUE
,
3476 &chip
->eapd_switch
->id
);
3479 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3480 if (chip
->amplifier
&& !old
) {
3481 voyetra_setup_eapd_slot(chip
);
3486 static void hercules_init(struct snd_cs46xx
*chip
)
3488 /* default: AMP off, and SPDIF input optical */
3489 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
, EGPIODR_GPOE0
);
3490 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
, EGPIODR_GPOE0
);
3495 * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3497 static void amp_hercules(struct snd_cs46xx
*chip
, int change
)
3499 int old
= chip
->amplifier
;
3500 int val1
= snd_cs46xx_peekBA0(chip
, BA0_EGPIODR
);
3501 int val2
= snd_cs46xx_peekBA0(chip
, BA0_EGPIOPTR
);
3503 chip
->amplifier
+= change
;
3504 if (chip
->amplifier
&& !old
) {
3505 dev_dbg(chip
->card
->dev
, "Hercules amplifier ON\n");
3507 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
,
3508 EGPIODR_GPOE2
| val1
); /* enable EGPIO2 output */
3509 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
,
3510 EGPIOPTR_GPPT2
| val2
); /* open-drain on output */
3511 } else if (old
&& !chip
->amplifier
) {
3512 dev_dbg(chip
->card
->dev
, "Hercules amplifier OFF\n");
3513 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
, val1
& ~EGPIODR_GPOE2
); /* disable */
3514 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
, val2
& ~EGPIOPTR_GPPT2
); /* disable */
3518 static void voyetra_mixer_init (struct snd_cs46xx
*chip
)
3520 dev_dbg(chip
->card
->dev
, "initializing Voyetra mixer\n");
3522 /* Enable SPDIF out */
3523 snd_cs46xx_pokeBA0(chip
, BA0_EGPIODR
, EGPIODR_GPOE0
);
3524 snd_cs46xx_pokeBA0(chip
, BA0_EGPIOPTR
, EGPIODR_GPOE0
);
3527 static void hercules_mixer_init (struct snd_cs46xx
*chip
)
3529 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3532 struct snd_card
*card
= chip
->card
;
3535 /* set EGPIO to default */
3536 hercules_init(chip
);
3538 dev_dbg(chip
->card
->dev
, "initializing Hercules mixer\n");
3540 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3541 if (chip
->in_suspend
)
3544 for (idx
= 0 ; idx
< ARRAY_SIZE(snd_hercules_controls
); idx
++) {
3545 struct snd_kcontrol
*kctl
;
3547 kctl
= snd_ctl_new1(&snd_hercules_controls
[idx
], chip
);
3548 if ((err
= snd_ctl_add(card
, kctl
)) < 0) {
3550 "failed to initialize Hercules mixer (%d)\n",
3564 static void amp_voyetra_4294(struct snd_cs46xx
*chip
, int change
)
3566 chip
->amplifier
+= change
;
3568 if (chip
->amplifier
) {
3569 /* Switch the GPIO pins 7 and 8 to open drain */
3570 snd_cs46xx_codec_write(chip
, 0x4C,
3571 snd_cs46xx_codec_read(chip
, 0x4C) & 0xFE7F);
3572 snd_cs46xx_codec_write(chip
, 0x4E,
3573 snd_cs46xx_codec_read(chip
, 0x4E) | 0x0180);
3574 /* Now wake the AMP (this might be backwards) */
3575 snd_cs46xx_codec_write(chip
, 0x54,
3576 snd_cs46xx_codec_read(chip
, 0x54) & ~0x0180);
3578 snd_cs46xx_codec_write(chip
, 0x54,
3579 snd_cs46xx_codec_read(chip
, 0x54) | 0x0180);
3586 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3587 * whenever we need to beat on the chip.
3589 * The original idea and code for this hack comes from David Kaiser at
3590 * Linuxcare. Perhaps one day Crystal will document their chips well
3591 * enough to make them useful.
3594 static void clkrun_hack(struct snd_cs46xx
*chip
, int change
)
3598 if (!chip
->acpi_port
)
3601 chip
->amplifier
+= change
;
3603 /* Read ACPI port */
3604 nval
= control
= inw(chip
->acpi_port
+ 0x10);
3606 /* Flip CLKRUN off while running */
3607 if (! chip
->amplifier
)
3611 if (nval
!= control
)
3612 outw(nval
, chip
->acpi_port
+ 0x10);
3617 * detect intel piix4
3619 static void clkrun_init(struct snd_cs46xx
*chip
)
3621 struct pci_dev
*pdev
;
3624 chip
->acpi_port
= 0;
3626 pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
,
3627 PCI_DEVICE_ID_INTEL_82371AB_3
, NULL
);
3629 return; /* Not a thinkpad thats for sure */
3631 /* Find the control port */
3632 pci_read_config_byte(pdev
, 0x41, &pp
);
3633 chip
->acpi_port
= pp
<< 8;
3647 void (*init
)(struct snd_cs46xx
*);
3648 void (*amp
)(struct snd_cs46xx
*, int);
3649 void (*active
)(struct snd_cs46xx
*, int);
3650 void (*mixer_init
)(struct snd_cs46xx
*);
3653 static struct cs_card_type cards
[] = {
3657 .name
= "Genius Soundmaker 128 value",
3658 /* nothing special */
3665 .mixer_init
= voyetra_mixer_init
,
3670 .name
= "Mitac MI6020/21",
3673 /* Hercules Game Theatre XP */
3675 .vendor
= 0x14af, /* Guillemot Corporation */
3677 .name
= "Hercules Game Theatre XP",
3678 .amp
= amp_hercules
,
3679 .mixer_init
= hercules_mixer_init
,
3684 .name
= "Hercules Game Theatre XP",
3685 .amp
= amp_hercules
,
3686 .mixer_init
= hercules_mixer_init
,
3691 .name
= "Hercules Game Theatre XP",
3692 .amp
= amp_hercules
,
3693 .mixer_init
= hercules_mixer_init
,
3699 .name
= "Hercules Game Theatre XP",
3700 .amp
= amp_hercules
,
3701 .mixer_init
= hercules_mixer_init
,
3706 .name
= "Hercules Game Theatre XP",
3707 .amp
= amp_hercules
,
3708 .mixer_init
= hercules_mixer_init
,
3713 .name
= "Hercules Game Theatre XP",
3714 .amp
= amp_hercules
,
3715 .mixer_init
= hercules_mixer_init
,
3717 /* Herculess Fortissimo */
3721 .name
= "Hercules Gamesurround Fortissimo II",
3726 .name
= "Hercules Gamesurround Fortissimo III 7.1",
3732 .name
= "Terratec DMX XFire 1024",
3737 .name
= "Terratec SiXPack 5.1",
3739 /* Not sure if the 570 needs the clkrun hack */
3741 .vendor
= PCI_VENDOR_ID_IBM
,
3743 .name
= "Thinkpad 570",
3744 .init
= clkrun_init
,
3745 .active
= clkrun_hack
,
3748 .vendor
= PCI_VENDOR_ID_IBM
,
3750 .name
= "Thinkpad 600X/A20/T20",
3751 .init
= clkrun_init
,
3752 .active
= clkrun_hack
,
3755 .vendor
= PCI_VENDOR_ID_IBM
,
3757 .name
= "Thinkpad 600E (unsupported)",
3766 #ifdef CONFIG_PM_SLEEP
3767 static unsigned int saved_regs
[] = {
3775 static int snd_cs46xx_suspend(struct device
*dev
)
3777 struct pci_dev
*pci
= to_pci_dev(dev
);
3778 struct snd_card
*card
= dev_get_drvdata(dev
);
3779 struct snd_cs46xx
*chip
= card
->private_data
;
3782 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
3783 chip
->in_suspend
= 1;
3784 snd_pcm_suspend_all(chip
->pcm
);
3785 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3786 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3788 snd_ac97_suspend(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
]);
3789 snd_ac97_suspend(chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
]);
3791 /* save some registers */
3792 for (i
= 0; i
< ARRAY_SIZE(saved_regs
); i
++)
3793 chip
->saved_regs
[i
] = snd_cs46xx_peekBA0(chip
, saved_regs
[i
]);
3795 amp_saved
= chip
->amplifier
;
3797 chip
->amplifier_ctrl(chip
, -chip
->amplifier
);
3798 snd_cs46xx_hw_stop(chip
);
3799 /* disable CLKRUN */
3800 chip
->active_ctrl(chip
, -chip
->amplifier
);
3801 chip
->amplifier
= amp_saved
; /* restore the status */
3803 pci_disable_device(pci
);
3804 pci_save_state(pci
);
3805 pci_set_power_state(pci
, PCI_D3hot
);
3809 static int snd_cs46xx_resume(struct device
*dev
)
3811 struct pci_dev
*pci
= to_pci_dev(dev
);
3812 struct snd_card
*card
= dev_get_drvdata(dev
);
3813 struct snd_cs46xx
*chip
= card
->private_data
;
3815 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3820 pci_set_power_state(pci
, PCI_D0
);
3821 pci_restore_state(pci
);
3822 if (pci_enable_device(pci
) < 0) {
3823 dev_err(dev
, "pci_enable_device failed, disabling device\n");
3824 snd_card_disconnect(card
);
3827 pci_set_master(pci
);
3829 amp_saved
= chip
->amplifier
;
3830 chip
->amplifier
= 0;
3831 chip
->active_ctrl(chip
, 1); /* force to on */
3833 snd_cs46xx_chip_init(chip
);
3835 snd_cs46xx_reset(chip
);
3836 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3837 cs46xx_dsp_resume(chip
);
3838 /* restore some registers */
3839 for (i
= 0; i
< ARRAY_SIZE(saved_regs
); i
++)
3840 snd_cs46xx_pokeBA0(chip
, saved_regs
[i
], chip
->saved_regs
[i
]);
3842 snd_cs46xx_download_image(chip
);
3846 snd_cs46xx_codec_write(chip
, BA0_AC97_GENERAL_PURPOSE
,
3847 chip
->ac97_general_purpose
);
3848 snd_cs46xx_codec_write(chip
, AC97_POWER_CONTROL
,
3849 chip
->ac97_powerdown
);
3851 snd_cs46xx_codec_write(chip
, BA0_AC97_POWERDOWN
,
3852 chip
->ac97_powerdown
);
3856 snd_ac97_resume(chip
->ac97
[CS46XX_PRIMARY_CODEC_INDEX
]);
3857 snd_ac97_resume(chip
->ac97
[CS46XX_SECONDARY_CODEC_INDEX
]);
3862 tmp
= snd_cs46xx_peek(chip
, BA1_CCTL
);
3863 chip
->capt
.ctl
= tmp
& 0x0000ffff;
3864 snd_cs46xx_poke(chip
, BA1_CCTL
, tmp
& 0xffff0000);
3868 /* reset playback/capture */
3869 snd_cs46xx_set_play_sample_rate(chip
, 8000);
3870 snd_cs46xx_set_capture_sample_rate(chip
, 8000);
3871 snd_cs46xx_proc_start(chip
);
3873 cs46xx_enable_stream_irqs(chip
);
3876 chip
->amplifier_ctrl(chip
, 1); /* turn amp on */
3878 chip
->active_ctrl(chip
, -1); /* disable CLKRUN */
3879 chip
->amplifier
= amp_saved
;
3880 chip
->in_suspend
= 0;
3881 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
3885 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm
, snd_cs46xx_suspend
, snd_cs46xx_resume
);
3886 #endif /* CONFIG_PM_SLEEP */
3892 int snd_cs46xx_create(struct snd_card
*card
,
3893 struct pci_dev
*pci
,
3894 int external_amp
, int thinkpad
,
3895 struct snd_cs46xx
**rchip
)
3897 struct snd_cs46xx
*chip
;
3899 struct snd_cs46xx_region
*region
;
3900 struct cs_card_type
*cp
;
3901 u16 ss_card
, ss_vendor
;
3902 static struct snd_device_ops ops
= {
3903 .dev_free
= snd_cs46xx_dev_free
,
3908 /* enable PCI device */
3909 if ((err
= pci_enable_device(pci
)) < 0)
3912 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
3914 pci_disable_device(pci
);
3917 spin_lock_init(&chip
->reg_lock
);
3918 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3919 mutex_init(&chip
->spos_mutex
);
3924 chip
->ba0_addr
= pci_resource_start(pci
, 0);
3925 chip
->ba1_addr
= pci_resource_start(pci
, 1);
3926 if (chip
->ba0_addr
== 0 || chip
->ba0_addr
== (unsigned long)~0 ||
3927 chip
->ba1_addr
== 0 || chip
->ba1_addr
== (unsigned long)~0) {
3928 dev_err(chip
->card
->dev
,
3929 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3930 chip
->ba0_addr
, chip
->ba1_addr
);
3931 snd_cs46xx_free(chip
);
3935 region
= &chip
->region
.name
.ba0
;
3936 strcpy(region
->name
, "CS46xx_BA0");
3937 region
->base
= chip
->ba0_addr
;
3938 region
->size
= CS46XX_BA0_SIZE
;
3940 region
= &chip
->region
.name
.data0
;
3941 strcpy(region
->name
, "CS46xx_BA1_data0");
3942 region
->base
= chip
->ba1_addr
+ BA1_SP_DMEM0
;
3943 region
->size
= CS46XX_BA1_DATA0_SIZE
;
3945 region
= &chip
->region
.name
.data1
;
3946 strcpy(region
->name
, "CS46xx_BA1_data1");
3947 region
->base
= chip
->ba1_addr
+ BA1_SP_DMEM1
;
3948 region
->size
= CS46XX_BA1_DATA1_SIZE
;
3950 region
= &chip
->region
.name
.pmem
;
3951 strcpy(region
->name
, "CS46xx_BA1_pmem");
3952 region
->base
= chip
->ba1_addr
+ BA1_SP_PMEM
;
3953 region
->size
= CS46XX_BA1_PRG_SIZE
;
3955 region
= &chip
->region
.name
.reg
;
3956 strcpy(region
->name
, "CS46xx_BA1_reg");
3957 region
->base
= chip
->ba1_addr
+ BA1_SP_REG
;
3958 region
->size
= CS46XX_BA1_REG_SIZE
;
3960 /* set up amp and clkrun hack */
3961 pci_read_config_word(pci
, PCI_SUBSYSTEM_VENDOR_ID
, &ss_vendor
);
3962 pci_read_config_word(pci
, PCI_SUBSYSTEM_ID
, &ss_card
);
3964 for (cp
= &cards
[0]; cp
->name
; cp
++) {
3965 if (cp
->vendor
== ss_vendor
&& cp
->id
== ss_card
) {
3966 dev_dbg(chip
->card
->dev
, "hack for %s enabled\n",
3969 chip
->amplifier_ctrl
= cp
->amp
;
3970 chip
->active_ctrl
= cp
->active
;
3971 chip
->mixer_init
= cp
->mixer_init
;
3980 dev_info(chip
->card
->dev
,
3981 "Crystal EAPD support forced on.\n");
3982 chip
->amplifier_ctrl
= amp_voyetra
;
3986 dev_info(chip
->card
->dev
,
3987 "Activating CLKRUN hack for Thinkpad.\n");
3988 chip
->active_ctrl
= clkrun_hack
;
3992 if (chip
->amplifier_ctrl
== NULL
)
3993 chip
->amplifier_ctrl
= amp_none
;
3994 if (chip
->active_ctrl
== NULL
)
3995 chip
->active_ctrl
= amp_none
;
3997 chip
->active_ctrl(chip
, 1); /* enable CLKRUN */
3999 pci_set_master(pci
);
4001 for (idx
= 0; idx
< 5; idx
++) {
4002 region
= &chip
->region
.idx
[idx
];
4003 if ((region
->resource
= request_mem_region(region
->base
, region
->size
,
4004 region
->name
)) == NULL
) {
4005 dev_err(chip
->card
->dev
,
4006 "unable to request memory region 0x%lx-0x%lx\n",
4007 region
->base
, region
->base
+ region
->size
- 1);
4008 snd_cs46xx_free(chip
);
4011 region
->remap_addr
= ioremap_nocache(region
->base
, region
->size
);
4012 if (region
->remap_addr
== NULL
) {
4013 dev_err(chip
->card
->dev
,
4014 "%s ioremap problem\n", region
->name
);
4015 snd_cs46xx_free(chip
);
4020 if (request_irq(pci
->irq
, snd_cs46xx_interrupt
, IRQF_SHARED
,
4021 KBUILD_MODNAME
, chip
)) {
4022 dev_err(chip
->card
->dev
, "unable to grab IRQ %d\n", pci
->irq
);
4023 snd_cs46xx_free(chip
);
4026 chip
->irq
= pci
->irq
;
4028 #ifdef CONFIG_SND_CS46XX_NEW_DSP
4029 chip
->dsp_spos_instance
= cs46xx_dsp_spos_create(chip
);
4030 if (chip
->dsp_spos_instance
== NULL
) {
4031 snd_cs46xx_free(chip
);
4036 err
= snd_cs46xx_chip_init(chip
);
4038 snd_cs46xx_free(chip
);
4042 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
)) < 0) {
4043 snd_cs46xx_free(chip
);
4047 snd_cs46xx_proc_init(card
, chip
);
4049 #ifdef CONFIG_PM_SLEEP
4050 chip
->saved_regs
= kmalloc(sizeof(*chip
->saved_regs
) *
4051 ARRAY_SIZE(saved_regs
), GFP_KERNEL
);
4052 if (!chip
->saved_regs
) {
4053 snd_cs46xx_free(chip
);
4058 chip
->active_ctrl(chip
, -1); /* disable CLKRUN */