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Merge branch 'drm-next-3.11' of git://people.freedesktop.org/~agd5f/linux into drm...
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65 #include "hda_i915.h"
66
67
68 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
69 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
70 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
71 static char *model[SNDRV_CARDS];
72 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
73 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
75 static int probe_only[SNDRV_CARDS];
76 static int jackpoll_ms[SNDRV_CARDS];
77 static bool single_cmd;
78 static int enable_msi = -1;
79 #ifdef CONFIG_SND_HDA_PATCH_LOADER
80 static char *patch[SNDRV_CARDS];
81 #endif
82 #ifdef CONFIG_SND_HDA_INPUT_BEEP
83 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
84 CONFIG_SND_HDA_INPUT_BEEP_MODE};
85 #endif
86
87 module_param_array(index, int, NULL, 0444);
88 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
89 module_param_array(id, charp, NULL, 0444);
90 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
91 module_param_array(enable, bool, NULL, 0444);
92 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
93 module_param_array(model, charp, NULL, 0444);
94 MODULE_PARM_DESC(model, "Use the given board model.");
95 module_param_array(position_fix, int, NULL, 0444);
96 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
97 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
98 module_param_array(bdl_pos_adj, int, NULL, 0644);
99 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
100 module_param_array(probe_mask, int, NULL, 0444);
101 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
102 module_param_array(probe_only, int, NULL, 0444);
103 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
104 module_param_array(jackpoll_ms, int, NULL, 0444);
105 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
106 module_param(single_cmd, bool, 0444);
107 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
108 "(for debugging only).");
109 module_param(enable_msi, bint, 0444);
110 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
111 #ifdef CONFIG_SND_HDA_PATCH_LOADER
112 module_param_array(patch, charp, NULL, 0444);
113 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
114 #endif
115 #ifdef CONFIG_SND_HDA_INPUT_BEEP
116 module_param_array(beep_mode, bool, NULL, 0444);
117 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
118 "(0=off, 1=on) (default=1).");
119 #endif
120
121 #ifdef CONFIG_PM
122 static int param_set_xint(const char *val, const struct kernel_param *kp);
123 static struct kernel_param_ops param_ops_xint = {
124 .set = param_set_xint,
125 .get = param_get_int,
126 };
127 #define param_check_xint param_check_int
128
129 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
130 module_param(power_save, xint, 0644);
131 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
132 "(in second, 0 = disable).");
133
134 /* reset the HD-audio controller in power save mode.
135 * this may give more power-saving, but will take longer time to
136 * wake up.
137 */
138 static bool power_save_controller = 1;
139 module_param(power_save_controller, bool, 0644);
140 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
141 #endif /* CONFIG_PM */
142
143 static int align_buffer_size = -1;
144 module_param(align_buffer_size, bint, 0644);
145 MODULE_PARM_DESC(align_buffer_size,
146 "Force buffer and period sizes to be multiple of 128 bytes.");
147
148 #ifdef CONFIG_X86
149 static bool hda_snoop = true;
150 module_param_named(snoop, hda_snoop, bool, 0444);
151 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
152 #define azx_snoop(chip) (chip)->snoop
153 #else
154 #define hda_snoop true
155 #define azx_snoop(chip) true
156 #endif
157
158
159 MODULE_LICENSE("GPL");
160 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
161 "{Intel, ICH6M},"
162 "{Intel, ICH7},"
163 "{Intel, ESB2},"
164 "{Intel, ICH8},"
165 "{Intel, ICH9},"
166 "{Intel, ICH10},"
167 "{Intel, PCH},"
168 "{Intel, CPT},"
169 "{Intel, PPT},"
170 "{Intel, LPT},"
171 "{Intel, LPT_LP},"
172 "{Intel, HPT},"
173 "{Intel, PBG},"
174 "{Intel, SCH},"
175 "{ATI, SB450},"
176 "{ATI, SB600},"
177 "{ATI, RS600},"
178 "{ATI, RS690},"
179 "{ATI, RS780},"
180 "{ATI, R600},"
181 "{ATI, RV630},"
182 "{ATI, RV610},"
183 "{ATI, RV670},"
184 "{ATI, RV635},"
185 "{ATI, RV620},"
186 "{ATI, RV770},"
187 "{VIA, VT8251},"
188 "{VIA, VT8237A},"
189 "{SiS, SIS966},"
190 "{ULI, M5461}}");
191 MODULE_DESCRIPTION("Intel HDA driver");
192
193 #ifdef CONFIG_SND_VERBOSE_PRINTK
194 #define SFX /* nop */
195 #else
196 #define SFX "hda-intel "
197 #endif
198
199 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
200 #ifdef CONFIG_SND_HDA_CODEC_HDMI
201 #define SUPPORT_VGA_SWITCHEROO
202 #endif
203 #endif
204
205
206 /*
207 * registers
208 */
209 #define ICH6_REG_GCAP 0x00
210 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
211 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
212 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
213 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
214 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
215 #define ICH6_REG_VMIN 0x02
216 #define ICH6_REG_VMAJ 0x03
217 #define ICH6_REG_OUTPAY 0x04
218 #define ICH6_REG_INPAY 0x06
219 #define ICH6_REG_GCTL 0x08
220 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
221 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
222 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
223 #define ICH6_REG_WAKEEN 0x0c
224 #define ICH6_REG_STATESTS 0x0e
225 #define ICH6_REG_GSTS 0x10
226 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
227 #define ICH6_REG_INTCTL 0x20
228 #define ICH6_REG_INTSTS 0x24
229 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
230 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
231 #define ICH6_REG_SSYNC 0x38
232 #define ICH6_REG_CORBLBASE 0x40
233 #define ICH6_REG_CORBUBASE 0x44
234 #define ICH6_REG_CORBWP 0x48
235 #define ICH6_REG_CORBRP 0x4a
236 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
237 #define ICH6_REG_CORBCTL 0x4c
238 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
239 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
240 #define ICH6_REG_CORBSTS 0x4d
241 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
242 #define ICH6_REG_CORBSIZE 0x4e
243
244 #define ICH6_REG_RIRBLBASE 0x50
245 #define ICH6_REG_RIRBUBASE 0x54
246 #define ICH6_REG_RIRBWP 0x58
247 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
248 #define ICH6_REG_RINTCNT 0x5a
249 #define ICH6_REG_RIRBCTL 0x5c
250 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
251 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
252 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
253 #define ICH6_REG_RIRBSTS 0x5d
254 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
255 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
256 #define ICH6_REG_RIRBSIZE 0x5e
257
258 #define ICH6_REG_IC 0x60
259 #define ICH6_REG_IR 0x64
260 #define ICH6_REG_IRS 0x68
261 #define ICH6_IRS_VALID (1<<1)
262 #define ICH6_IRS_BUSY (1<<0)
263
264 #define ICH6_REG_DPLBASE 0x70
265 #define ICH6_REG_DPUBASE 0x74
266 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
267
268 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
269 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
270
271 /* stream register offsets from stream base */
272 #define ICH6_REG_SD_CTL 0x00
273 #define ICH6_REG_SD_STS 0x03
274 #define ICH6_REG_SD_LPIB 0x04
275 #define ICH6_REG_SD_CBL 0x08
276 #define ICH6_REG_SD_LVI 0x0c
277 #define ICH6_REG_SD_FIFOW 0x0e
278 #define ICH6_REG_SD_FIFOSIZE 0x10
279 #define ICH6_REG_SD_FORMAT 0x12
280 #define ICH6_REG_SD_BDLPL 0x18
281 #define ICH6_REG_SD_BDLPU 0x1c
282
283 /* PCI space */
284 #define ICH6_PCIREG_TCSEL 0x44
285
286 /*
287 * other constants
288 */
289
290 /* max number of SDs */
291 /* ICH, ATI and VIA have 4 playback and 4 capture */
292 #define ICH6_NUM_CAPTURE 4
293 #define ICH6_NUM_PLAYBACK 4
294
295 /* ULI has 6 playback and 5 capture */
296 #define ULI_NUM_CAPTURE 5
297 #define ULI_NUM_PLAYBACK 6
298
299 /* ATI HDMI has 1 playback and 0 capture */
300 #define ATIHDMI_NUM_CAPTURE 0
301 #define ATIHDMI_NUM_PLAYBACK 1
302
303 /* TERA has 4 playback and 3 capture */
304 #define TERA_NUM_CAPTURE 3
305 #define TERA_NUM_PLAYBACK 4
306
307 /* this number is statically defined for simplicity */
308 #define MAX_AZX_DEV 16
309
310 /* max number of fragments - we may use more if allocating more pages for BDL */
311 #define BDL_SIZE 4096
312 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
313 #define AZX_MAX_FRAG 32
314 /* max buffer size - no h/w limit, you can increase as you like */
315 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
316
317 /* RIRB int mask: overrun[2], response[0] */
318 #define RIRB_INT_RESPONSE 0x01
319 #define RIRB_INT_OVERRUN 0x04
320 #define RIRB_INT_MASK 0x05
321
322 /* STATESTS int mask: S3,SD2,SD1,SD0 */
323 #define AZX_MAX_CODECS 8
324 #define AZX_DEFAULT_CODECS 4
325 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
326
327 /* SD_CTL bits */
328 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
329 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
330 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
331 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
332 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
333 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
334 #define SD_CTL_STREAM_TAG_SHIFT 20
335
336 /* SD_CTL and SD_STS */
337 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
338 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
339 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
340 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
341 SD_INT_COMPLETE)
342
343 /* SD_STS */
344 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
345
346 /* INTCTL and INTSTS */
347 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
348 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
349 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
350
351 /* below are so far hardcoded - should read registers in future */
352 #define ICH6_MAX_CORB_ENTRIES 256
353 #define ICH6_MAX_RIRB_ENTRIES 256
354
355 /* position fix mode */
356 enum {
357 POS_FIX_AUTO,
358 POS_FIX_LPIB,
359 POS_FIX_POSBUF,
360 POS_FIX_VIACOMBO,
361 POS_FIX_COMBO,
362 };
363
364 /* Defines for ATI HD Audio support in SB450 south bridge */
365 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
366 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
367
368 /* Defines for Nvidia HDA support */
369 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
370 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
371 #define NVIDIA_HDA_ISTRM_COH 0x4d
372 #define NVIDIA_HDA_OSTRM_COH 0x4c
373 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
374
375 /* Defines for Intel SCH HDA snoop control */
376 #define INTEL_SCH_HDA_DEVC 0x78
377 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
378
379 /* Define IN stream 0 FIFO size offset in VIA controller */
380 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
381 /* Define VIA HD Audio Device ID*/
382 #define VIA_HDAC_DEVICE_ID 0x3288
383
384 /* HD Audio class code */
385 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
386
387 /*
388 */
389
390 struct azx_dev {
391 struct snd_dma_buffer bdl; /* BDL buffer */
392 u32 *posbuf; /* position buffer pointer */
393
394 unsigned int bufsize; /* size of the play buffer in bytes */
395 unsigned int period_bytes; /* size of the period in bytes */
396 unsigned int frags; /* number for period in the play buffer */
397 unsigned int fifo_size; /* FIFO size */
398 unsigned long start_wallclk; /* start + minimum wallclk */
399 unsigned long period_wallclk; /* wallclk for period */
400
401 void __iomem *sd_addr; /* stream descriptor pointer */
402
403 u32 sd_int_sta_mask; /* stream int status mask */
404
405 /* pcm support */
406 struct snd_pcm_substream *substream; /* assigned substream,
407 * set in PCM open
408 */
409 unsigned int format_val; /* format value to be set in the
410 * controller and the codec
411 */
412 unsigned char stream_tag; /* assigned stream */
413 unsigned char index; /* stream index */
414 int assigned_key; /* last device# key assigned to */
415
416 unsigned int opened :1;
417 unsigned int running :1;
418 unsigned int irq_pending :1;
419 unsigned int prepared:1;
420 unsigned int locked:1;
421 /*
422 * For VIA:
423 * A flag to ensure DMA position is 0
424 * when link position is not greater than FIFO size
425 */
426 unsigned int insufficient :1;
427 unsigned int wc_marked:1;
428 unsigned int no_period_wakeup:1;
429
430 struct timecounter azx_tc;
431 struct cyclecounter azx_cc;
432
433 #ifdef CONFIG_SND_HDA_DSP_LOADER
434 struct mutex dsp_mutex;
435 #endif
436 };
437
438 /* DSP lock helpers */
439 #ifdef CONFIG_SND_HDA_DSP_LOADER
440 #define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
441 #define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
442 #define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
443 #define dsp_is_locked(dev) ((dev)->locked)
444 #else
445 #define dsp_lock_init(dev) do {} while (0)
446 #define dsp_lock(dev) do {} while (0)
447 #define dsp_unlock(dev) do {} while (0)
448 #define dsp_is_locked(dev) 0
449 #endif
450
451 /* CORB/RIRB */
452 struct azx_rb {
453 u32 *buf; /* CORB/RIRB buffer
454 * Each CORB entry is 4byte, RIRB is 8byte
455 */
456 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
457 /* for RIRB */
458 unsigned short rp, wp; /* read/write pointers */
459 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
460 u32 res[AZX_MAX_CODECS]; /* last read value */
461 };
462
463 struct azx_pcm {
464 struct azx *chip;
465 struct snd_pcm *pcm;
466 struct hda_codec *codec;
467 struct hda_pcm_stream *hinfo[2];
468 struct list_head list;
469 };
470
471 struct azx {
472 struct snd_card *card;
473 struct pci_dev *pci;
474 int dev_index;
475
476 /* chip type specific */
477 int driver_type;
478 unsigned int driver_caps;
479 int playback_streams;
480 int playback_index_offset;
481 int capture_streams;
482 int capture_index_offset;
483 int num_streams;
484
485 /* pci resources */
486 unsigned long addr;
487 void __iomem *remap_addr;
488 int irq;
489
490 /* locks */
491 spinlock_t reg_lock;
492 struct mutex open_mutex;
493 struct completion probe_wait;
494
495 /* streams (x num_streams) */
496 struct azx_dev *azx_dev;
497
498 /* PCM */
499 struct list_head pcm_list; /* azx_pcm list */
500
501 /* HD codec */
502 unsigned short codec_mask;
503 int codec_probe_mask; /* copied from probe_mask option */
504 struct hda_bus *bus;
505 unsigned int beep_mode;
506
507 /* CORB/RIRB */
508 struct azx_rb corb;
509 struct azx_rb rirb;
510
511 /* CORB/RIRB and position buffers */
512 struct snd_dma_buffer rb;
513 struct snd_dma_buffer posbuf;
514
515 #ifdef CONFIG_SND_HDA_PATCH_LOADER
516 const struct firmware *fw;
517 #endif
518
519 /* flags */
520 int position_fix[2]; /* for both playback/capture streams */
521 int poll_count;
522 unsigned int running :1;
523 unsigned int initialized :1;
524 unsigned int single_cmd :1;
525 unsigned int polling_mode :1;
526 unsigned int msi :1;
527 unsigned int irq_pending_warned :1;
528 unsigned int probing :1; /* codec probing phase */
529 unsigned int snoop:1;
530 unsigned int align_buffer_size:1;
531 unsigned int region_requested:1;
532
533 /* VGA-switcheroo setup */
534 unsigned int use_vga_switcheroo:1;
535 unsigned int vga_switcheroo_registered:1;
536 unsigned int init_failed:1; /* delayed init failed */
537 unsigned int disabled:1; /* disabled by VGA-switcher */
538
539 /* for debugging */
540 unsigned int last_cmd[AZX_MAX_CODECS];
541
542 /* for pending irqs */
543 struct work_struct irq_pending_work;
544
545 #ifdef CONFIG_SND_HDA_I915
546 struct work_struct probe_work;
547 #endif
548
549 /* reboot notifier (for mysterious hangup problem at power-down) */
550 struct notifier_block reboot_notifier;
551
552 /* card list (for power_save trigger) */
553 struct list_head list;
554
555 #ifdef CONFIG_SND_HDA_DSP_LOADER
556 struct azx_dev saved_azx_dev;
557 #endif
558 };
559
560 #define CREATE_TRACE_POINTS
561 #include "hda_intel_trace.h"
562
563 /* driver types */
564 enum {
565 AZX_DRIVER_ICH,
566 AZX_DRIVER_PCH,
567 AZX_DRIVER_SCH,
568 AZX_DRIVER_ATI,
569 AZX_DRIVER_ATIHDMI,
570 AZX_DRIVER_ATIHDMI_NS,
571 AZX_DRIVER_VIA,
572 AZX_DRIVER_SIS,
573 AZX_DRIVER_ULI,
574 AZX_DRIVER_NVIDIA,
575 AZX_DRIVER_TERA,
576 AZX_DRIVER_CTX,
577 AZX_DRIVER_CTHDA,
578 AZX_DRIVER_GENERIC,
579 AZX_NUM_DRIVERS, /* keep this as last entry */
580 };
581
582 /* driver quirks (capabilities) */
583 /* bits 0-7 are used for indicating driver type */
584 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
585 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
586 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
587 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
588 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
589 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
590 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
591 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
592 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
593 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
594 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
595 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
596 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
597 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
598 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
599 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
600 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
601 #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
602 #define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 power well support */
603
604 /* quirks for Intel PCH */
605 #define AZX_DCAPS_INTEL_PCH_NOPM \
606 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
607 AZX_DCAPS_COUNT_LPIB_DELAY)
608
609 #define AZX_DCAPS_INTEL_PCH \
610 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
611
612 /* quirks for ATI SB / AMD Hudson */
613 #define AZX_DCAPS_PRESET_ATI_SB \
614 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
615 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
616
617 /* quirks for ATI/AMD HDMI */
618 #define AZX_DCAPS_PRESET_ATI_HDMI \
619 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
620
621 /* quirks for Nvidia */
622 #define AZX_DCAPS_PRESET_NVIDIA \
623 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
624 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
625
626 #define AZX_DCAPS_PRESET_CTHDA \
627 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
628
629 /*
630 * VGA-switcher support
631 */
632 #ifdef SUPPORT_VGA_SWITCHEROO
633 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
634 #else
635 #define use_vga_switcheroo(chip) 0
636 #endif
637
638 static char *driver_short_names[] = {
639 [AZX_DRIVER_ICH] = "HDA Intel",
640 [AZX_DRIVER_PCH] = "HDA Intel PCH",
641 [AZX_DRIVER_SCH] = "HDA Intel MID",
642 [AZX_DRIVER_ATI] = "HDA ATI SB",
643 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
644 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
645 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
646 [AZX_DRIVER_SIS] = "HDA SIS966",
647 [AZX_DRIVER_ULI] = "HDA ULI M5461",
648 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
649 [AZX_DRIVER_TERA] = "HDA Teradici",
650 [AZX_DRIVER_CTX] = "HDA Creative",
651 [AZX_DRIVER_CTHDA] = "HDA Creative",
652 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
653 };
654
655 /*
656 * macros for easy use
657 */
658 #define azx_writel(chip,reg,value) \
659 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
660 #define azx_readl(chip,reg) \
661 readl((chip)->remap_addr + ICH6_REG_##reg)
662 #define azx_writew(chip,reg,value) \
663 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
664 #define azx_readw(chip,reg) \
665 readw((chip)->remap_addr + ICH6_REG_##reg)
666 #define azx_writeb(chip,reg,value) \
667 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
668 #define azx_readb(chip,reg) \
669 readb((chip)->remap_addr + ICH6_REG_##reg)
670
671 #define azx_sd_writel(dev,reg,value) \
672 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
673 #define azx_sd_readl(dev,reg) \
674 readl((dev)->sd_addr + ICH6_REG_##reg)
675 #define azx_sd_writew(dev,reg,value) \
676 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
677 #define azx_sd_readw(dev,reg) \
678 readw((dev)->sd_addr + ICH6_REG_##reg)
679 #define azx_sd_writeb(dev,reg,value) \
680 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
681 #define azx_sd_readb(dev,reg) \
682 readb((dev)->sd_addr + ICH6_REG_##reg)
683
684 /* for pcm support */
685 #define get_azx_dev(substream) (substream->runtime->private_data)
686
687 #ifdef CONFIG_X86
688 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
689 {
690 int pages;
691
692 if (azx_snoop(chip))
693 return;
694 if (!dmab || !dmab->area || !dmab->bytes)
695 return;
696
697 #ifdef CONFIG_SND_DMA_SGBUF
698 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
699 struct snd_sg_buf *sgbuf = dmab->private_data;
700 if (on)
701 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
702 else
703 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
704 return;
705 }
706 #endif
707
708 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
709 if (on)
710 set_memory_wc((unsigned long)dmab->area, pages);
711 else
712 set_memory_wb((unsigned long)dmab->area, pages);
713 }
714
715 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
716 bool on)
717 {
718 __mark_pages_wc(chip, buf, on);
719 }
720 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
721 struct snd_pcm_substream *substream, bool on)
722 {
723 if (azx_dev->wc_marked != on) {
724 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
725 azx_dev->wc_marked = on;
726 }
727 }
728 #else
729 /* NOP for other archs */
730 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
731 bool on)
732 {
733 }
734 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
735 struct snd_pcm_substream *substream, bool on)
736 {
737 }
738 #endif
739
740 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
741 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
742 /*
743 * Interface for HD codec
744 */
745
746 /*
747 * CORB / RIRB interface
748 */
749 static int azx_alloc_cmd_io(struct azx *chip)
750 {
751 int err;
752
753 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
754 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
755 snd_dma_pci_data(chip->pci),
756 PAGE_SIZE, &chip->rb);
757 if (err < 0) {
758 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
759 return err;
760 }
761 mark_pages_wc(chip, &chip->rb, true);
762 return 0;
763 }
764
765 static void azx_init_cmd_io(struct azx *chip)
766 {
767 spin_lock_irq(&chip->reg_lock);
768 /* CORB set up */
769 chip->corb.addr = chip->rb.addr;
770 chip->corb.buf = (u32 *)chip->rb.area;
771 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
772 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
773
774 /* set the corb size to 256 entries (ULI requires explicitly) */
775 azx_writeb(chip, CORBSIZE, 0x02);
776 /* set the corb write pointer to 0 */
777 azx_writew(chip, CORBWP, 0);
778 /* reset the corb hw read pointer */
779 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
780 /* enable corb dma */
781 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
782
783 /* RIRB set up */
784 chip->rirb.addr = chip->rb.addr + 2048;
785 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
786 chip->rirb.wp = chip->rirb.rp = 0;
787 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
788 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
789 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
790
791 /* set the rirb size to 256 entries (ULI requires explicitly) */
792 azx_writeb(chip, RIRBSIZE, 0x02);
793 /* reset the rirb hw write pointer */
794 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
795 /* set N=1, get RIRB response interrupt for new entry */
796 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
797 azx_writew(chip, RINTCNT, 0xc0);
798 else
799 azx_writew(chip, RINTCNT, 1);
800 /* enable rirb dma and response irq */
801 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
802 spin_unlock_irq(&chip->reg_lock);
803 }
804
805 static void azx_free_cmd_io(struct azx *chip)
806 {
807 spin_lock_irq(&chip->reg_lock);
808 /* disable ringbuffer DMAs */
809 azx_writeb(chip, RIRBCTL, 0);
810 azx_writeb(chip, CORBCTL, 0);
811 spin_unlock_irq(&chip->reg_lock);
812 }
813
814 static unsigned int azx_command_addr(u32 cmd)
815 {
816 unsigned int addr = cmd >> 28;
817
818 if (addr >= AZX_MAX_CODECS) {
819 snd_BUG();
820 addr = 0;
821 }
822
823 return addr;
824 }
825
826 static unsigned int azx_response_addr(u32 res)
827 {
828 unsigned int addr = res & 0xf;
829
830 if (addr >= AZX_MAX_CODECS) {
831 snd_BUG();
832 addr = 0;
833 }
834
835 return addr;
836 }
837
838 /* send a command */
839 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
840 {
841 struct azx *chip = bus->private_data;
842 unsigned int addr = azx_command_addr(val);
843 unsigned int wp, rp;
844
845 spin_lock_irq(&chip->reg_lock);
846
847 /* add command to corb */
848 wp = azx_readw(chip, CORBWP);
849 if (wp == 0xffff) {
850 /* something wrong, controller likely turned to D3 */
851 spin_unlock_irq(&chip->reg_lock);
852 return -EIO;
853 }
854 wp++;
855 wp %= ICH6_MAX_CORB_ENTRIES;
856
857 rp = azx_readw(chip, CORBRP);
858 if (wp == rp) {
859 /* oops, it's full */
860 spin_unlock_irq(&chip->reg_lock);
861 return -EAGAIN;
862 }
863
864 chip->rirb.cmds[addr]++;
865 chip->corb.buf[wp] = cpu_to_le32(val);
866 azx_writel(chip, CORBWP, wp);
867
868 spin_unlock_irq(&chip->reg_lock);
869
870 return 0;
871 }
872
873 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
874
875 /* retrieve RIRB entry - called from interrupt handler */
876 static void azx_update_rirb(struct azx *chip)
877 {
878 unsigned int rp, wp;
879 unsigned int addr;
880 u32 res, res_ex;
881
882 wp = azx_readw(chip, RIRBWP);
883 if (wp == 0xffff) {
884 /* something wrong, controller likely turned to D3 */
885 return;
886 }
887
888 if (wp == chip->rirb.wp)
889 return;
890 chip->rirb.wp = wp;
891
892 while (chip->rirb.rp != wp) {
893 chip->rirb.rp++;
894 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
895
896 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
897 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
898 res = le32_to_cpu(chip->rirb.buf[rp]);
899 addr = azx_response_addr(res_ex);
900 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
901 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
902 else if (chip->rirb.cmds[addr]) {
903 chip->rirb.res[addr] = res;
904 smp_wmb();
905 chip->rirb.cmds[addr]--;
906 } else
907 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
908 "last cmd=%#08x\n",
909 pci_name(chip->pci),
910 res, res_ex,
911 chip->last_cmd[addr]);
912 }
913 }
914
915 /* receive a response */
916 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
917 unsigned int addr)
918 {
919 struct azx *chip = bus->private_data;
920 unsigned long timeout;
921 unsigned long loopcounter;
922 int do_poll = 0;
923
924 again:
925 timeout = jiffies + msecs_to_jiffies(1000);
926
927 for (loopcounter = 0;; loopcounter++) {
928 if (chip->polling_mode || do_poll) {
929 spin_lock_irq(&chip->reg_lock);
930 azx_update_rirb(chip);
931 spin_unlock_irq(&chip->reg_lock);
932 }
933 if (!chip->rirb.cmds[addr]) {
934 smp_rmb();
935 bus->rirb_error = 0;
936
937 if (!do_poll)
938 chip->poll_count = 0;
939 return chip->rirb.res[addr]; /* the last value */
940 }
941 if (time_after(jiffies, timeout))
942 break;
943 if (bus->needs_damn_long_delay || loopcounter > 3000)
944 msleep(2); /* temporary workaround */
945 else {
946 udelay(10);
947 cond_resched();
948 }
949 }
950
951 if (!chip->polling_mode && chip->poll_count < 2) {
952 snd_printdd(SFX "%s: azx_get_response timeout, "
953 "polling the codec once: last cmd=0x%08x\n",
954 pci_name(chip->pci), chip->last_cmd[addr]);
955 do_poll = 1;
956 chip->poll_count++;
957 goto again;
958 }
959
960
961 if (!chip->polling_mode) {
962 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
963 "switching to polling mode: last cmd=0x%08x\n",
964 pci_name(chip->pci), chip->last_cmd[addr]);
965 chip->polling_mode = 1;
966 goto again;
967 }
968
969 if (chip->msi) {
970 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
971 "disabling MSI: last cmd=0x%08x\n",
972 pci_name(chip->pci), chip->last_cmd[addr]);
973 free_irq(chip->irq, chip);
974 chip->irq = -1;
975 pci_disable_msi(chip->pci);
976 chip->msi = 0;
977 if (azx_acquire_irq(chip, 1) < 0) {
978 bus->rirb_error = 1;
979 return -1;
980 }
981 goto again;
982 }
983
984 if (chip->probing) {
985 /* If this critical timeout happens during the codec probing
986 * phase, this is likely an access to a non-existing codec
987 * slot. Better to return an error and reset the system.
988 */
989 return -1;
990 }
991
992 /* a fatal communication error; need either to reset or to fallback
993 * to the single_cmd mode
994 */
995 bus->rirb_error = 1;
996 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
997 bus->response_reset = 1;
998 return -1; /* give a chance to retry */
999 }
1000
1001 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
1002 "switching to single_cmd mode: last cmd=0x%08x\n",
1003 chip->last_cmd[addr]);
1004 chip->single_cmd = 1;
1005 bus->response_reset = 0;
1006 /* release CORB/RIRB */
1007 azx_free_cmd_io(chip);
1008 /* disable unsolicited responses */
1009 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1010 return -1;
1011 }
1012
1013 /*
1014 * Use the single immediate command instead of CORB/RIRB for simplicity
1015 *
1016 * Note: according to Intel, this is not preferred use. The command was
1017 * intended for the BIOS only, and may get confused with unsolicited
1018 * responses. So, we shouldn't use it for normal operation from the
1019 * driver.
1020 * I left the codes, however, for debugging/testing purposes.
1021 */
1022
1023 /* receive a response */
1024 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1025 {
1026 int timeout = 50;
1027
1028 while (timeout--) {
1029 /* check IRV busy bit */
1030 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1031 /* reuse rirb.res as the response return value */
1032 chip->rirb.res[addr] = azx_readl(chip, IR);
1033 return 0;
1034 }
1035 udelay(1);
1036 }
1037 if (printk_ratelimit())
1038 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1039 pci_name(chip->pci), azx_readw(chip, IRS));
1040 chip->rirb.res[addr] = -1;
1041 return -EIO;
1042 }
1043
1044 /* send a command */
1045 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1046 {
1047 struct azx *chip = bus->private_data;
1048 unsigned int addr = azx_command_addr(val);
1049 int timeout = 50;
1050
1051 bus->rirb_error = 0;
1052 while (timeout--) {
1053 /* check ICB busy bit */
1054 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1055 /* Clear IRV valid bit */
1056 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1057 ICH6_IRS_VALID);
1058 azx_writel(chip, IC, val);
1059 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1060 ICH6_IRS_BUSY);
1061 return azx_single_wait_for_response(chip, addr);
1062 }
1063 udelay(1);
1064 }
1065 if (printk_ratelimit())
1066 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1067 pci_name(chip->pci), azx_readw(chip, IRS), val);
1068 return -EIO;
1069 }
1070
1071 /* receive a response */
1072 static unsigned int azx_single_get_response(struct hda_bus *bus,
1073 unsigned int addr)
1074 {
1075 struct azx *chip = bus->private_data;
1076 return chip->rirb.res[addr];
1077 }
1078
1079 /*
1080 * The below are the main callbacks from hda_codec.
1081 *
1082 * They are just the skeleton to call sub-callbacks according to the
1083 * current setting of chip->single_cmd.
1084 */
1085
1086 /* send a command */
1087 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1088 {
1089 struct azx *chip = bus->private_data;
1090
1091 if (chip->disabled)
1092 return 0;
1093 chip->last_cmd[azx_command_addr(val)] = val;
1094 if (chip->single_cmd)
1095 return azx_single_send_cmd(bus, val);
1096 else
1097 return azx_corb_send_cmd(bus, val);
1098 }
1099
1100 /* get a response */
1101 static unsigned int azx_get_response(struct hda_bus *bus,
1102 unsigned int addr)
1103 {
1104 struct azx *chip = bus->private_data;
1105 if (chip->disabled)
1106 return 0;
1107 if (chip->single_cmd)
1108 return azx_single_get_response(bus, addr);
1109 else
1110 return azx_rirb_get_response(bus, addr);
1111 }
1112
1113 #ifdef CONFIG_PM
1114 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1115 #endif
1116
1117 #ifdef CONFIG_SND_HDA_DSP_LOADER
1118 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1119 unsigned int byte_size,
1120 struct snd_dma_buffer *bufp);
1121 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1122 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1123 struct snd_dma_buffer *dmab);
1124 #endif
1125
1126 /* reset codec link */
1127 static int azx_reset(struct azx *chip, int full_reset)
1128 {
1129 unsigned long timeout;
1130
1131 if (!full_reset)
1132 goto __skip;
1133
1134 /* clear STATESTS */
1135 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1136
1137 /* reset controller */
1138 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1139
1140 timeout = jiffies + msecs_to_jiffies(100);
1141 while (azx_readb(chip, GCTL) &&
1142 time_before(jiffies, timeout))
1143 usleep_range(500, 1000);
1144
1145 /* delay for >= 100us for codec PLL to settle per spec
1146 * Rev 0.9 section 5.5.1
1147 */
1148 usleep_range(500, 1000);
1149
1150 /* Bring controller out of reset */
1151 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1152
1153 timeout = jiffies + msecs_to_jiffies(100);
1154 while (!azx_readb(chip, GCTL) &&
1155 time_before(jiffies, timeout))
1156 usleep_range(500, 1000);
1157
1158 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1159 usleep_range(1000, 1200);
1160
1161 __skip:
1162 /* check to see if controller is ready */
1163 if (!azx_readb(chip, GCTL)) {
1164 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1165 return -EBUSY;
1166 }
1167
1168 /* Accept unsolicited responses */
1169 if (!chip->single_cmd)
1170 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1171 ICH6_GCTL_UNSOL);
1172
1173 /* detect codecs */
1174 if (!chip->codec_mask) {
1175 chip->codec_mask = azx_readw(chip, STATESTS);
1176 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1177 }
1178
1179 return 0;
1180 }
1181
1182
1183 /*
1184 * Lowlevel interface
1185 */
1186
1187 /* enable interrupts */
1188 static void azx_int_enable(struct azx *chip)
1189 {
1190 /* enable controller CIE and GIE */
1191 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1192 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1193 }
1194
1195 /* disable interrupts */
1196 static void azx_int_disable(struct azx *chip)
1197 {
1198 int i;
1199
1200 /* disable interrupts in stream descriptor */
1201 for (i = 0; i < chip->num_streams; i++) {
1202 struct azx_dev *azx_dev = &chip->azx_dev[i];
1203 azx_sd_writeb(azx_dev, SD_CTL,
1204 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1205 }
1206
1207 /* disable SIE for all streams */
1208 azx_writeb(chip, INTCTL, 0);
1209
1210 /* disable controller CIE and GIE */
1211 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1212 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1213 }
1214
1215 /* clear interrupts */
1216 static void azx_int_clear(struct azx *chip)
1217 {
1218 int i;
1219
1220 /* clear stream status */
1221 for (i = 0; i < chip->num_streams; i++) {
1222 struct azx_dev *azx_dev = &chip->azx_dev[i];
1223 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1224 }
1225
1226 /* clear STATESTS */
1227 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1228
1229 /* clear rirb status */
1230 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1231
1232 /* clear int status */
1233 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1234 }
1235
1236 /* start a stream */
1237 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1238 {
1239 /*
1240 * Before stream start, initialize parameter
1241 */
1242 azx_dev->insufficient = 1;
1243
1244 /* enable SIE */
1245 azx_writel(chip, INTCTL,
1246 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1247 /* set DMA start and interrupt mask */
1248 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1249 SD_CTL_DMA_START | SD_INT_MASK);
1250 }
1251
1252 /* stop DMA */
1253 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1254 {
1255 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1256 ~(SD_CTL_DMA_START | SD_INT_MASK));
1257 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1258 }
1259
1260 /* stop a stream */
1261 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1262 {
1263 azx_stream_clear(chip, azx_dev);
1264 /* disable SIE */
1265 azx_writel(chip, INTCTL,
1266 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1267 }
1268
1269
1270 /*
1271 * reset and start the controller registers
1272 */
1273 static void azx_init_chip(struct azx *chip, int full_reset)
1274 {
1275 if (chip->initialized)
1276 return;
1277
1278 /* reset controller */
1279 azx_reset(chip, full_reset);
1280
1281 /* initialize interrupts */
1282 azx_int_clear(chip);
1283 azx_int_enable(chip);
1284
1285 /* initialize the codec command I/O */
1286 if (!chip->single_cmd)
1287 azx_init_cmd_io(chip);
1288
1289 /* program the position buffer */
1290 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1291 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1292
1293 chip->initialized = 1;
1294 }
1295
1296 /*
1297 * initialize the PCI registers
1298 */
1299 /* update bits in a PCI register byte */
1300 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1301 unsigned char mask, unsigned char val)
1302 {
1303 unsigned char data;
1304
1305 pci_read_config_byte(pci, reg, &data);
1306 data &= ~mask;
1307 data |= (val & mask);
1308 pci_write_config_byte(pci, reg, data);
1309 }
1310
1311 static void azx_init_pci(struct azx *chip)
1312 {
1313 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1314 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1315 * Ensuring these bits are 0 clears playback static on some HD Audio
1316 * codecs.
1317 * The PCI register TCSEL is defined in the Intel manuals.
1318 */
1319 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1320 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1321 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1322 }
1323
1324 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1325 * we need to enable snoop.
1326 */
1327 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1328 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1329 update_pci_byte(chip->pci,
1330 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1331 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1332 }
1333
1334 /* For NVIDIA HDA, enable snoop */
1335 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1336 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1337 update_pci_byte(chip->pci,
1338 NVIDIA_HDA_TRANSREG_ADDR,
1339 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1340 update_pci_byte(chip->pci,
1341 NVIDIA_HDA_ISTRM_COH,
1342 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1343 update_pci_byte(chip->pci,
1344 NVIDIA_HDA_OSTRM_COH,
1345 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1346 }
1347
1348 /* Enable SCH/PCH snoop if needed */
1349 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1350 unsigned short snoop;
1351 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1352 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1353 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1354 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1355 if (!azx_snoop(chip))
1356 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1357 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1358 pci_read_config_word(chip->pci,
1359 INTEL_SCH_HDA_DEVC, &snoop);
1360 }
1361 snd_printdd(SFX "%s: SCH snoop: %s\n",
1362 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1363 ? "Disabled" : "Enabled");
1364 }
1365 }
1366
1367
1368 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1369
1370 /*
1371 * interrupt handler
1372 */
1373 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1374 {
1375 struct azx *chip = dev_id;
1376 struct azx_dev *azx_dev;
1377 u32 status;
1378 u8 sd_status;
1379 int i, ok;
1380
1381 #ifdef CONFIG_PM_RUNTIME
1382 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1383 return IRQ_NONE;
1384 #endif
1385
1386 spin_lock(&chip->reg_lock);
1387
1388 if (chip->disabled) {
1389 spin_unlock(&chip->reg_lock);
1390 return IRQ_NONE;
1391 }
1392
1393 status = azx_readl(chip, INTSTS);
1394 if (status == 0) {
1395 spin_unlock(&chip->reg_lock);
1396 return IRQ_NONE;
1397 }
1398
1399 for (i = 0; i < chip->num_streams; i++) {
1400 azx_dev = &chip->azx_dev[i];
1401 if (status & azx_dev->sd_int_sta_mask) {
1402 sd_status = azx_sd_readb(azx_dev, SD_STS);
1403 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1404 if (!azx_dev->substream || !azx_dev->running ||
1405 !(sd_status & SD_INT_COMPLETE))
1406 continue;
1407 /* check whether this IRQ is really acceptable */
1408 ok = azx_position_ok(chip, azx_dev);
1409 if (ok == 1) {
1410 azx_dev->irq_pending = 0;
1411 spin_unlock(&chip->reg_lock);
1412 snd_pcm_period_elapsed(azx_dev->substream);
1413 spin_lock(&chip->reg_lock);
1414 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1415 /* bogus IRQ, process it later */
1416 azx_dev->irq_pending = 1;
1417 queue_work(chip->bus->workq,
1418 &chip->irq_pending_work);
1419 }
1420 }
1421 }
1422
1423 /* clear rirb int */
1424 status = azx_readb(chip, RIRBSTS);
1425 if (status & RIRB_INT_MASK) {
1426 if (status & RIRB_INT_RESPONSE) {
1427 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1428 udelay(80);
1429 azx_update_rirb(chip);
1430 }
1431 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1432 }
1433
1434 #if 0
1435 /* clear state status int */
1436 if (azx_readb(chip, STATESTS) & 0x04)
1437 azx_writeb(chip, STATESTS, 0x04);
1438 #endif
1439 spin_unlock(&chip->reg_lock);
1440
1441 return IRQ_HANDLED;
1442 }
1443
1444
1445 /*
1446 * set up a BDL entry
1447 */
1448 static int setup_bdle(struct azx *chip,
1449 struct snd_dma_buffer *dmab,
1450 struct azx_dev *azx_dev, u32 **bdlp,
1451 int ofs, int size, int with_ioc)
1452 {
1453 u32 *bdl = *bdlp;
1454
1455 while (size > 0) {
1456 dma_addr_t addr;
1457 int chunk;
1458
1459 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1460 return -EINVAL;
1461
1462 addr = snd_sgbuf_get_addr(dmab, ofs);
1463 /* program the address field of the BDL entry */
1464 bdl[0] = cpu_to_le32((u32)addr);
1465 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1466 /* program the size field of the BDL entry */
1467 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1468 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1469 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1470 u32 remain = 0x1000 - (ofs & 0xfff);
1471 if (chunk > remain)
1472 chunk = remain;
1473 }
1474 bdl[2] = cpu_to_le32(chunk);
1475 /* program the IOC to enable interrupt
1476 * only when the whole fragment is processed
1477 */
1478 size -= chunk;
1479 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1480 bdl += 4;
1481 azx_dev->frags++;
1482 ofs += chunk;
1483 }
1484 *bdlp = bdl;
1485 return ofs;
1486 }
1487
1488 /*
1489 * set up BDL entries
1490 */
1491 static int azx_setup_periods(struct azx *chip,
1492 struct snd_pcm_substream *substream,
1493 struct azx_dev *azx_dev)
1494 {
1495 u32 *bdl;
1496 int i, ofs, periods, period_bytes;
1497 int pos_adj;
1498
1499 /* reset BDL address */
1500 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1501 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1502
1503 period_bytes = azx_dev->period_bytes;
1504 periods = azx_dev->bufsize / period_bytes;
1505
1506 /* program the initial BDL entries */
1507 bdl = (u32 *)azx_dev->bdl.area;
1508 ofs = 0;
1509 azx_dev->frags = 0;
1510 pos_adj = bdl_pos_adj[chip->dev_index];
1511 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1512 struct snd_pcm_runtime *runtime = substream->runtime;
1513 int pos_align = pos_adj;
1514 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1515 if (!pos_adj)
1516 pos_adj = pos_align;
1517 else
1518 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1519 pos_align;
1520 pos_adj = frames_to_bytes(runtime, pos_adj);
1521 if (pos_adj >= period_bytes) {
1522 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1523 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1524 pos_adj = 0;
1525 } else {
1526 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1527 azx_dev,
1528 &bdl, ofs, pos_adj, true);
1529 if (ofs < 0)
1530 goto error;
1531 }
1532 } else
1533 pos_adj = 0;
1534 for (i = 0; i < periods; i++) {
1535 if (i == periods - 1 && pos_adj)
1536 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1537 azx_dev, &bdl, ofs,
1538 period_bytes - pos_adj, 0);
1539 else
1540 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1541 azx_dev, &bdl, ofs,
1542 period_bytes,
1543 !azx_dev->no_period_wakeup);
1544 if (ofs < 0)
1545 goto error;
1546 }
1547 return 0;
1548
1549 error:
1550 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1551 pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1552 return -EINVAL;
1553 }
1554
1555 /* reset stream */
1556 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1557 {
1558 unsigned char val;
1559 int timeout;
1560
1561 azx_stream_clear(chip, azx_dev);
1562
1563 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1564 SD_CTL_STREAM_RESET);
1565 udelay(3);
1566 timeout = 300;
1567 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1568 --timeout)
1569 ;
1570 val &= ~SD_CTL_STREAM_RESET;
1571 azx_sd_writeb(azx_dev, SD_CTL, val);
1572 udelay(3);
1573
1574 timeout = 300;
1575 /* waiting for hardware to report that the stream is out of reset */
1576 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1577 --timeout)
1578 ;
1579
1580 /* reset first position - may not be synced with hw at this time */
1581 *azx_dev->posbuf = 0;
1582 }
1583
1584 /*
1585 * set up the SD for streaming
1586 */
1587 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1588 {
1589 unsigned int val;
1590 /* make sure the run bit is zero for SD */
1591 azx_stream_clear(chip, azx_dev);
1592 /* program the stream_tag */
1593 val = azx_sd_readl(azx_dev, SD_CTL);
1594 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1595 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1596 if (!azx_snoop(chip))
1597 val |= SD_CTL_TRAFFIC_PRIO;
1598 azx_sd_writel(azx_dev, SD_CTL, val);
1599
1600 /* program the length of samples in cyclic buffer */
1601 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1602
1603 /* program the stream format */
1604 /* this value needs to be the same as the one programmed */
1605 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1606
1607 /* program the stream LVI (last valid index) of the BDL */
1608 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1609
1610 /* program the BDL address */
1611 /* lower BDL address */
1612 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1613 /* upper BDL address */
1614 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1615
1616 /* enable the position buffer */
1617 if (chip->position_fix[0] != POS_FIX_LPIB ||
1618 chip->position_fix[1] != POS_FIX_LPIB) {
1619 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1620 azx_writel(chip, DPLBASE,
1621 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1622 }
1623
1624 /* set the interrupt enable bits in the descriptor control register */
1625 azx_sd_writel(azx_dev, SD_CTL,
1626 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1627
1628 return 0;
1629 }
1630
1631 /*
1632 * Probe the given codec address
1633 */
1634 static int probe_codec(struct azx *chip, int addr)
1635 {
1636 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1637 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1638 unsigned int res;
1639
1640 mutex_lock(&chip->bus->cmd_mutex);
1641 chip->probing = 1;
1642 azx_send_cmd(chip->bus, cmd);
1643 res = azx_get_response(chip->bus, addr);
1644 chip->probing = 0;
1645 mutex_unlock(&chip->bus->cmd_mutex);
1646 if (res == -1)
1647 return -EIO;
1648 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1649 return 0;
1650 }
1651
1652 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1653 struct hda_pcm *cpcm);
1654 static void azx_stop_chip(struct azx *chip);
1655
1656 static void azx_bus_reset(struct hda_bus *bus)
1657 {
1658 struct azx *chip = bus->private_data;
1659
1660 bus->in_reset = 1;
1661 azx_stop_chip(chip);
1662 azx_init_chip(chip, 1);
1663 #ifdef CONFIG_PM
1664 if (chip->initialized) {
1665 struct azx_pcm *p;
1666 list_for_each_entry(p, &chip->pcm_list, list)
1667 snd_pcm_suspend_all(p->pcm);
1668 snd_hda_suspend(chip->bus);
1669 snd_hda_resume(chip->bus);
1670 }
1671 #endif
1672 bus->in_reset = 0;
1673 }
1674
1675 static int get_jackpoll_interval(struct azx *chip)
1676 {
1677 int i = jackpoll_ms[chip->dev_index];
1678 unsigned int j;
1679 if (i == 0)
1680 return 0;
1681 if (i < 50 || i > 60000)
1682 j = 0;
1683 else
1684 j = msecs_to_jiffies(i);
1685 if (j == 0)
1686 snd_printk(KERN_WARNING SFX
1687 "jackpoll_ms value out of range: %d\n", i);
1688 return j;
1689 }
1690
1691 /*
1692 * Codec initialization
1693 */
1694
1695 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1696 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1697 [AZX_DRIVER_NVIDIA] = 8,
1698 [AZX_DRIVER_TERA] = 1,
1699 };
1700
1701 static int azx_codec_create(struct azx *chip, const char *model)
1702 {
1703 struct hda_bus_template bus_temp;
1704 int c, codecs, err;
1705 int max_slots;
1706
1707 memset(&bus_temp, 0, sizeof(bus_temp));
1708 bus_temp.private_data = chip;
1709 bus_temp.modelname = model;
1710 bus_temp.pci = chip->pci;
1711 bus_temp.ops.command = azx_send_cmd;
1712 bus_temp.ops.get_response = azx_get_response;
1713 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1714 bus_temp.ops.bus_reset = azx_bus_reset;
1715 #ifdef CONFIG_PM
1716 bus_temp.power_save = &power_save;
1717 bus_temp.ops.pm_notify = azx_power_notify;
1718 #endif
1719 #ifdef CONFIG_SND_HDA_DSP_LOADER
1720 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1721 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1722 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1723 #endif
1724
1725 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1726 if (err < 0)
1727 return err;
1728
1729 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1730 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1731 chip->bus->needs_damn_long_delay = 1;
1732 }
1733
1734 codecs = 0;
1735 max_slots = azx_max_codecs[chip->driver_type];
1736 if (!max_slots)
1737 max_slots = AZX_DEFAULT_CODECS;
1738
1739 /* First try to probe all given codec slots */
1740 for (c = 0; c < max_slots; c++) {
1741 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1742 if (probe_codec(chip, c) < 0) {
1743 /* Some BIOSen give you wrong codec addresses
1744 * that don't exist
1745 */
1746 snd_printk(KERN_WARNING SFX
1747 "%s: Codec #%d probe error; "
1748 "disabling it...\n", pci_name(chip->pci), c);
1749 chip->codec_mask &= ~(1 << c);
1750 /* More badly, accessing to a non-existing
1751 * codec often screws up the controller chip,
1752 * and disturbs the further communications.
1753 * Thus if an error occurs during probing,
1754 * better to reset the controller chip to
1755 * get back to the sanity state.
1756 */
1757 azx_stop_chip(chip);
1758 azx_init_chip(chip, 1);
1759 }
1760 }
1761 }
1762
1763 /* AMD chipsets often cause the communication stalls upon certain
1764 * sequence like the pin-detection. It seems that forcing the synced
1765 * access works around the stall. Grrr...
1766 */
1767 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1768 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1769 pci_name(chip->pci));
1770 chip->bus->sync_write = 1;
1771 chip->bus->allow_bus_reset = 1;
1772 }
1773
1774 /* Then create codec instances */
1775 for (c = 0; c < max_slots; c++) {
1776 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1777 struct hda_codec *codec;
1778 err = snd_hda_codec_new(chip->bus, c, &codec);
1779 if (err < 0)
1780 continue;
1781 codec->jackpoll_interval = get_jackpoll_interval(chip);
1782 codec->beep_mode = chip->beep_mode;
1783 codecs++;
1784 }
1785 }
1786 if (!codecs) {
1787 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1788 return -ENXIO;
1789 }
1790 return 0;
1791 }
1792
1793 /* configure each codec instance */
1794 static int azx_codec_configure(struct azx *chip)
1795 {
1796 struct hda_codec *codec;
1797 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1798 snd_hda_codec_configure(codec);
1799 }
1800 return 0;
1801 }
1802
1803
1804 /*
1805 * PCM support
1806 */
1807
1808 /* assign a stream for the PCM */
1809 static inline struct azx_dev *
1810 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1811 {
1812 int dev, i, nums;
1813 struct azx_dev *res = NULL;
1814 /* make a non-zero unique key for the substream */
1815 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1816 (substream->stream + 1);
1817
1818 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1819 dev = chip->playback_index_offset;
1820 nums = chip->playback_streams;
1821 } else {
1822 dev = chip->capture_index_offset;
1823 nums = chip->capture_streams;
1824 }
1825 for (i = 0; i < nums; i++, dev++) {
1826 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1827 dsp_lock(azx_dev);
1828 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1829 res = azx_dev;
1830 if (res->assigned_key == key) {
1831 res->opened = 1;
1832 res->assigned_key = key;
1833 dsp_unlock(azx_dev);
1834 return azx_dev;
1835 }
1836 }
1837 dsp_unlock(azx_dev);
1838 }
1839 if (res) {
1840 dsp_lock(res);
1841 res->opened = 1;
1842 res->assigned_key = key;
1843 dsp_unlock(res);
1844 }
1845 return res;
1846 }
1847
1848 /* release the assigned stream */
1849 static inline void azx_release_device(struct azx_dev *azx_dev)
1850 {
1851 azx_dev->opened = 0;
1852 }
1853
1854 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1855 {
1856 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1857 struct snd_pcm_substream *substream = azx_dev->substream;
1858 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1859 struct azx *chip = apcm->chip;
1860
1861 return azx_readl(chip, WALLCLK);
1862 }
1863
1864 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1865 bool force, cycle_t last)
1866 {
1867 struct azx_dev *azx_dev = get_azx_dev(substream);
1868 struct timecounter *tc = &azx_dev->azx_tc;
1869 struct cyclecounter *cc = &azx_dev->azx_cc;
1870 u64 nsec;
1871
1872 cc->read = azx_cc_read;
1873 cc->mask = CLOCKSOURCE_MASK(32);
1874
1875 /*
1876 * Converting from 24 MHz to ns means applying a 125/3 factor.
1877 * To avoid any saturation issues in intermediate operations,
1878 * the 125 factor is applied first. The division is applied
1879 * last after reading the timecounter value.
1880 * Applying the 1/3 factor as part of the multiplication
1881 * requires at least 20 bits for a decent precision, however
1882 * overflows occur after about 4 hours or less, not a option.
1883 */
1884
1885 cc->mult = 125; /* saturation after 195 years */
1886 cc->shift = 0;
1887
1888 nsec = 0; /* audio time is elapsed time since trigger */
1889 timecounter_init(tc, cc, nsec);
1890 if (force)
1891 /*
1892 * force timecounter to use predefined value,
1893 * used for synchronized starts
1894 */
1895 tc->cycle_last = last;
1896 }
1897
1898 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
1899 u64 nsec)
1900 {
1901 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1902 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1903 u64 codec_frames, codec_nsecs;
1904
1905 if (!hinfo->ops.get_delay)
1906 return nsec;
1907
1908 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1909 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1910 substream->runtime->rate);
1911
1912 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1913 return nsec + codec_nsecs;
1914
1915 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1916 }
1917
1918 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1919 struct timespec *ts)
1920 {
1921 struct azx_dev *azx_dev = get_azx_dev(substream);
1922 u64 nsec;
1923
1924 nsec = timecounter_read(&azx_dev->azx_tc);
1925 nsec = div_u64(nsec, 3); /* can be optimized */
1926 nsec = azx_adjust_codec_delay(substream, nsec);
1927
1928 *ts = ns_to_timespec(nsec);
1929
1930 return 0;
1931 }
1932
1933 static struct snd_pcm_hardware azx_pcm_hw = {
1934 .info = (SNDRV_PCM_INFO_MMAP |
1935 SNDRV_PCM_INFO_INTERLEAVED |
1936 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1937 SNDRV_PCM_INFO_MMAP_VALID |
1938 /* No full-resume yet implemented */
1939 /* SNDRV_PCM_INFO_RESUME |*/
1940 SNDRV_PCM_INFO_PAUSE |
1941 SNDRV_PCM_INFO_SYNC_START |
1942 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1943 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1944 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1945 .rates = SNDRV_PCM_RATE_48000,
1946 .rate_min = 48000,
1947 .rate_max = 48000,
1948 .channels_min = 2,
1949 .channels_max = 2,
1950 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1951 .period_bytes_min = 128,
1952 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1953 .periods_min = 2,
1954 .periods_max = AZX_MAX_FRAG,
1955 .fifo_size = 0,
1956 };
1957
1958 static int azx_pcm_open(struct snd_pcm_substream *substream)
1959 {
1960 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1961 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1962 struct azx *chip = apcm->chip;
1963 struct azx_dev *azx_dev;
1964 struct snd_pcm_runtime *runtime = substream->runtime;
1965 unsigned long flags;
1966 int err;
1967 int buff_step;
1968
1969 mutex_lock(&chip->open_mutex);
1970 azx_dev = azx_assign_device(chip, substream);
1971 if (azx_dev == NULL) {
1972 mutex_unlock(&chip->open_mutex);
1973 return -EBUSY;
1974 }
1975 runtime->hw = azx_pcm_hw;
1976 runtime->hw.channels_min = hinfo->channels_min;
1977 runtime->hw.channels_max = hinfo->channels_max;
1978 runtime->hw.formats = hinfo->formats;
1979 runtime->hw.rates = hinfo->rates;
1980 snd_pcm_limit_hw_rates(runtime);
1981 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1982
1983 /* avoid wrap-around with wall-clock */
1984 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1985 20,
1986 178000000);
1987
1988 if (chip->align_buffer_size)
1989 /* constrain buffer sizes to be multiple of 128
1990 bytes. This is more efficient in terms of memory
1991 access but isn't required by the HDA spec and
1992 prevents users from specifying exact period/buffer
1993 sizes. For example for 44.1kHz, a period size set
1994 to 20ms will be rounded to 19.59ms. */
1995 buff_step = 128;
1996 else
1997 /* Don't enforce steps on buffer sizes, still need to
1998 be multiple of 4 bytes (HDA spec). Tested on Intel
1999 HDA controllers, may not work on all devices where
2000 option needs to be disabled */
2001 buff_step = 4;
2002
2003 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2004 buff_step);
2005 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2006 buff_step);
2007 snd_hda_power_up_d3wait(apcm->codec);
2008 err = hinfo->ops.open(hinfo, apcm->codec, substream);
2009 if (err < 0) {
2010 azx_release_device(azx_dev);
2011 snd_hda_power_down(apcm->codec);
2012 mutex_unlock(&chip->open_mutex);
2013 return err;
2014 }
2015 snd_pcm_limit_hw_rates(runtime);
2016 /* sanity check */
2017 if (snd_BUG_ON(!runtime->hw.channels_min) ||
2018 snd_BUG_ON(!runtime->hw.channels_max) ||
2019 snd_BUG_ON(!runtime->hw.formats) ||
2020 snd_BUG_ON(!runtime->hw.rates)) {
2021 azx_release_device(azx_dev);
2022 hinfo->ops.close(hinfo, apcm->codec, substream);
2023 snd_hda_power_down(apcm->codec);
2024 mutex_unlock(&chip->open_mutex);
2025 return -EINVAL;
2026 }
2027
2028 /* disable WALLCLOCK timestamps for capture streams
2029 until we figure out how to handle digital inputs */
2030 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2031 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2032
2033 spin_lock_irqsave(&chip->reg_lock, flags);
2034 azx_dev->substream = substream;
2035 azx_dev->running = 0;
2036 spin_unlock_irqrestore(&chip->reg_lock, flags);
2037
2038 runtime->private_data = azx_dev;
2039 snd_pcm_set_sync(substream);
2040 mutex_unlock(&chip->open_mutex);
2041 return 0;
2042 }
2043
2044 static int azx_pcm_close(struct snd_pcm_substream *substream)
2045 {
2046 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2047 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2048 struct azx *chip = apcm->chip;
2049 struct azx_dev *azx_dev = get_azx_dev(substream);
2050 unsigned long flags;
2051
2052 mutex_lock(&chip->open_mutex);
2053 spin_lock_irqsave(&chip->reg_lock, flags);
2054 azx_dev->substream = NULL;
2055 azx_dev->running = 0;
2056 spin_unlock_irqrestore(&chip->reg_lock, flags);
2057 azx_release_device(azx_dev);
2058 hinfo->ops.close(hinfo, apcm->codec, substream);
2059 snd_hda_power_down(apcm->codec);
2060 mutex_unlock(&chip->open_mutex);
2061 return 0;
2062 }
2063
2064 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2065 struct snd_pcm_hw_params *hw_params)
2066 {
2067 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2068 struct azx *chip = apcm->chip;
2069 struct azx_dev *azx_dev = get_azx_dev(substream);
2070 int ret;
2071
2072 dsp_lock(azx_dev);
2073 if (dsp_is_locked(azx_dev)) {
2074 ret = -EBUSY;
2075 goto unlock;
2076 }
2077
2078 mark_runtime_wc(chip, azx_dev, substream, false);
2079 azx_dev->bufsize = 0;
2080 azx_dev->period_bytes = 0;
2081 azx_dev->format_val = 0;
2082 ret = snd_pcm_lib_malloc_pages(substream,
2083 params_buffer_bytes(hw_params));
2084 if (ret < 0)
2085 goto unlock;
2086 mark_runtime_wc(chip, azx_dev, substream, true);
2087 unlock:
2088 dsp_unlock(azx_dev);
2089 return ret;
2090 }
2091
2092 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2093 {
2094 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2095 struct azx_dev *azx_dev = get_azx_dev(substream);
2096 struct azx *chip = apcm->chip;
2097 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2098
2099 /* reset BDL address */
2100 dsp_lock(azx_dev);
2101 if (!dsp_is_locked(azx_dev)) {
2102 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2103 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2104 azx_sd_writel(azx_dev, SD_CTL, 0);
2105 azx_dev->bufsize = 0;
2106 azx_dev->period_bytes = 0;
2107 azx_dev->format_val = 0;
2108 }
2109
2110 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2111
2112 mark_runtime_wc(chip, azx_dev, substream, false);
2113 azx_dev->prepared = 0;
2114 dsp_unlock(azx_dev);
2115 return snd_pcm_lib_free_pages(substream);
2116 }
2117
2118 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2119 {
2120 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2121 struct azx *chip = apcm->chip;
2122 struct azx_dev *azx_dev = get_azx_dev(substream);
2123 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2124 struct snd_pcm_runtime *runtime = substream->runtime;
2125 unsigned int bufsize, period_bytes, format_val, stream_tag;
2126 int err;
2127 struct hda_spdif_out *spdif =
2128 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2129 unsigned short ctls = spdif ? spdif->ctls : 0;
2130
2131 dsp_lock(azx_dev);
2132 if (dsp_is_locked(azx_dev)) {
2133 err = -EBUSY;
2134 goto unlock;
2135 }
2136
2137 azx_stream_reset(chip, azx_dev);
2138 format_val = snd_hda_calc_stream_format(runtime->rate,
2139 runtime->channels,
2140 runtime->format,
2141 hinfo->maxbps,
2142 ctls);
2143 if (!format_val) {
2144 snd_printk(KERN_ERR SFX
2145 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2146 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2147 err = -EINVAL;
2148 goto unlock;
2149 }
2150
2151 bufsize = snd_pcm_lib_buffer_bytes(substream);
2152 period_bytes = snd_pcm_lib_period_bytes(substream);
2153
2154 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2155 pci_name(chip->pci), bufsize, format_val);
2156
2157 if (bufsize != azx_dev->bufsize ||
2158 period_bytes != azx_dev->period_bytes ||
2159 format_val != azx_dev->format_val ||
2160 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2161 azx_dev->bufsize = bufsize;
2162 azx_dev->period_bytes = period_bytes;
2163 azx_dev->format_val = format_val;
2164 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2165 err = azx_setup_periods(chip, substream, azx_dev);
2166 if (err < 0)
2167 goto unlock;
2168 }
2169
2170 /* wallclk has 24Mhz clock source */
2171 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2172 runtime->rate) * 1000);
2173 azx_setup_controller(chip, azx_dev);
2174 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2175 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2176 else
2177 azx_dev->fifo_size = 0;
2178
2179 stream_tag = azx_dev->stream_tag;
2180 /* CA-IBG chips need the playback stream starting from 1 */
2181 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2182 stream_tag > chip->capture_streams)
2183 stream_tag -= chip->capture_streams;
2184 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2185 azx_dev->format_val, substream);
2186
2187 unlock:
2188 if (!err)
2189 azx_dev->prepared = 1;
2190 dsp_unlock(azx_dev);
2191 return err;
2192 }
2193
2194 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2195 {
2196 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2197 struct azx *chip = apcm->chip;
2198 struct azx_dev *azx_dev;
2199 struct snd_pcm_substream *s;
2200 int rstart = 0, start, nsync = 0, sbits = 0;
2201 int nwait, timeout;
2202
2203 azx_dev = get_azx_dev(substream);
2204 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2205
2206 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2207 return -EPIPE;
2208
2209 switch (cmd) {
2210 case SNDRV_PCM_TRIGGER_START:
2211 rstart = 1;
2212 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2213 case SNDRV_PCM_TRIGGER_RESUME:
2214 start = 1;
2215 break;
2216 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2217 case SNDRV_PCM_TRIGGER_SUSPEND:
2218 case SNDRV_PCM_TRIGGER_STOP:
2219 start = 0;
2220 break;
2221 default:
2222 return -EINVAL;
2223 }
2224
2225 snd_pcm_group_for_each_entry(s, substream) {
2226 if (s->pcm->card != substream->pcm->card)
2227 continue;
2228 azx_dev = get_azx_dev(s);
2229 sbits |= 1 << azx_dev->index;
2230 nsync++;
2231 snd_pcm_trigger_done(s, substream);
2232 }
2233
2234 spin_lock(&chip->reg_lock);
2235
2236 /* first, set SYNC bits of corresponding streams */
2237 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2238 azx_writel(chip, OLD_SSYNC,
2239 azx_readl(chip, OLD_SSYNC) | sbits);
2240 else
2241 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2242
2243 snd_pcm_group_for_each_entry(s, substream) {
2244 if (s->pcm->card != substream->pcm->card)
2245 continue;
2246 azx_dev = get_azx_dev(s);
2247 if (start) {
2248 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2249 if (!rstart)
2250 azx_dev->start_wallclk -=
2251 azx_dev->period_wallclk;
2252 azx_stream_start(chip, azx_dev);
2253 } else {
2254 azx_stream_stop(chip, azx_dev);
2255 }
2256 azx_dev->running = start;
2257 }
2258 spin_unlock(&chip->reg_lock);
2259 if (start) {
2260 /* wait until all FIFOs get ready */
2261 for (timeout = 5000; timeout; timeout--) {
2262 nwait = 0;
2263 snd_pcm_group_for_each_entry(s, substream) {
2264 if (s->pcm->card != substream->pcm->card)
2265 continue;
2266 azx_dev = get_azx_dev(s);
2267 if (!(azx_sd_readb(azx_dev, SD_STS) &
2268 SD_STS_FIFO_READY))
2269 nwait++;
2270 }
2271 if (!nwait)
2272 break;
2273 cpu_relax();
2274 }
2275 } else {
2276 /* wait until all RUN bits are cleared */
2277 for (timeout = 5000; timeout; timeout--) {
2278 nwait = 0;
2279 snd_pcm_group_for_each_entry(s, substream) {
2280 if (s->pcm->card != substream->pcm->card)
2281 continue;
2282 azx_dev = get_azx_dev(s);
2283 if (azx_sd_readb(azx_dev, SD_CTL) &
2284 SD_CTL_DMA_START)
2285 nwait++;
2286 }
2287 if (!nwait)
2288 break;
2289 cpu_relax();
2290 }
2291 }
2292 spin_lock(&chip->reg_lock);
2293 /* reset SYNC bits */
2294 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2295 azx_writel(chip, OLD_SSYNC,
2296 azx_readl(chip, OLD_SSYNC) & ~sbits);
2297 else
2298 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2299 if (start) {
2300 azx_timecounter_init(substream, 0, 0);
2301 if (nsync > 1) {
2302 cycle_t cycle_last;
2303
2304 /* same start cycle for master and group */
2305 azx_dev = get_azx_dev(substream);
2306 cycle_last = azx_dev->azx_tc.cycle_last;
2307
2308 snd_pcm_group_for_each_entry(s, substream) {
2309 if (s->pcm->card != substream->pcm->card)
2310 continue;
2311 azx_timecounter_init(s, 1, cycle_last);
2312 }
2313 }
2314 }
2315 spin_unlock(&chip->reg_lock);
2316 return 0;
2317 }
2318
2319 /* get the current DMA position with correction on VIA chips */
2320 static unsigned int azx_via_get_position(struct azx *chip,
2321 struct azx_dev *azx_dev)
2322 {
2323 unsigned int link_pos, mini_pos, bound_pos;
2324 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2325 unsigned int fifo_size;
2326
2327 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2328 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2329 /* Playback, no problem using link position */
2330 return link_pos;
2331 }
2332
2333 /* Capture */
2334 /* For new chipset,
2335 * use mod to get the DMA position just like old chipset
2336 */
2337 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2338 mod_dma_pos %= azx_dev->period_bytes;
2339
2340 /* azx_dev->fifo_size can't get FIFO size of in stream.
2341 * Get from base address + offset.
2342 */
2343 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2344
2345 if (azx_dev->insufficient) {
2346 /* Link position never gather than FIFO size */
2347 if (link_pos <= fifo_size)
2348 return 0;
2349
2350 azx_dev->insufficient = 0;
2351 }
2352
2353 if (link_pos <= fifo_size)
2354 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2355 else
2356 mini_pos = link_pos - fifo_size;
2357
2358 /* Find nearest previous boudary */
2359 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2360 mod_link_pos = link_pos % azx_dev->period_bytes;
2361 if (mod_link_pos >= fifo_size)
2362 bound_pos = link_pos - mod_link_pos;
2363 else if (mod_dma_pos >= mod_mini_pos)
2364 bound_pos = mini_pos - mod_mini_pos;
2365 else {
2366 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2367 if (bound_pos >= azx_dev->bufsize)
2368 bound_pos = 0;
2369 }
2370
2371 /* Calculate real DMA position we want */
2372 return bound_pos + mod_dma_pos;
2373 }
2374
2375 static unsigned int azx_get_position(struct azx *chip,
2376 struct azx_dev *azx_dev,
2377 bool with_check)
2378 {
2379 struct snd_pcm_substream *substream = azx_dev->substream;
2380 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2381 unsigned int pos;
2382 int stream = substream->stream;
2383 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2384 int delay = 0;
2385
2386 switch (chip->position_fix[stream]) {
2387 case POS_FIX_LPIB:
2388 /* read LPIB */
2389 pos = azx_sd_readl(azx_dev, SD_LPIB);
2390 break;
2391 case POS_FIX_VIACOMBO:
2392 pos = azx_via_get_position(chip, azx_dev);
2393 break;
2394 default:
2395 /* use the position buffer */
2396 pos = le32_to_cpu(*azx_dev->posbuf);
2397 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2398 if (!pos || pos == (u32)-1) {
2399 printk(KERN_WARNING
2400 "hda-intel: Invalid position buffer, "
2401 "using LPIB read method instead.\n");
2402 chip->position_fix[stream] = POS_FIX_LPIB;
2403 pos = azx_sd_readl(azx_dev, SD_LPIB);
2404 } else
2405 chip->position_fix[stream] = POS_FIX_POSBUF;
2406 }
2407 break;
2408 }
2409
2410 if (pos >= azx_dev->bufsize)
2411 pos = 0;
2412
2413 /* calculate runtime delay from LPIB */
2414 if (substream->runtime &&
2415 chip->position_fix[stream] == POS_FIX_POSBUF &&
2416 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2417 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2418 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2419 delay = pos - lpib_pos;
2420 else
2421 delay = lpib_pos - pos;
2422 if (delay < 0)
2423 delay += azx_dev->bufsize;
2424 if (delay >= azx_dev->period_bytes) {
2425 snd_printk(KERN_WARNING SFX
2426 "%s: Unstable LPIB (%d >= %d); "
2427 "disabling LPIB delay counting\n",
2428 pci_name(chip->pci), delay, azx_dev->period_bytes);
2429 delay = 0;
2430 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2431 }
2432 delay = bytes_to_frames(substream->runtime, delay);
2433 }
2434
2435 if (substream->runtime) {
2436 if (hinfo->ops.get_delay)
2437 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2438 substream);
2439 substream->runtime->delay = delay;
2440 }
2441
2442 trace_azx_get_position(chip, azx_dev, pos, delay);
2443 return pos;
2444 }
2445
2446 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2447 {
2448 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2449 struct azx *chip = apcm->chip;
2450 struct azx_dev *azx_dev = get_azx_dev(substream);
2451 return bytes_to_frames(substream->runtime,
2452 azx_get_position(chip, azx_dev, false));
2453 }
2454
2455 /*
2456 * Check whether the current DMA position is acceptable for updating
2457 * periods. Returns non-zero if it's OK.
2458 *
2459 * Many HD-audio controllers appear pretty inaccurate about
2460 * the update-IRQ timing. The IRQ is issued before actually the
2461 * data is processed. So, we need to process it afterwords in a
2462 * workqueue.
2463 */
2464 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2465 {
2466 u32 wallclk;
2467 unsigned int pos;
2468
2469 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2470 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2471 return -1; /* bogus (too early) interrupt */
2472
2473 pos = azx_get_position(chip, azx_dev, true);
2474
2475 if (WARN_ONCE(!azx_dev->period_bytes,
2476 "hda-intel: zero azx_dev->period_bytes"))
2477 return -1; /* this shouldn't happen! */
2478 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2479 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2480 /* NG - it's below the first next period boundary */
2481 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2482 azx_dev->start_wallclk += wallclk;
2483 return 1; /* OK, it's fine */
2484 }
2485
2486 /*
2487 * The work for pending PCM period updates.
2488 */
2489 static void azx_irq_pending_work(struct work_struct *work)
2490 {
2491 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2492 int i, pending, ok;
2493
2494 if (!chip->irq_pending_warned) {
2495 printk(KERN_WARNING
2496 "hda-intel: IRQ timing workaround is activated "
2497 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2498 chip->card->number);
2499 chip->irq_pending_warned = 1;
2500 }
2501
2502 for (;;) {
2503 pending = 0;
2504 spin_lock_irq(&chip->reg_lock);
2505 for (i = 0; i < chip->num_streams; i++) {
2506 struct azx_dev *azx_dev = &chip->azx_dev[i];
2507 if (!azx_dev->irq_pending ||
2508 !azx_dev->substream ||
2509 !azx_dev->running)
2510 continue;
2511 ok = azx_position_ok(chip, azx_dev);
2512 if (ok > 0) {
2513 azx_dev->irq_pending = 0;
2514 spin_unlock(&chip->reg_lock);
2515 snd_pcm_period_elapsed(azx_dev->substream);
2516 spin_lock(&chip->reg_lock);
2517 } else if (ok < 0) {
2518 pending = 0; /* too early */
2519 } else
2520 pending++;
2521 }
2522 spin_unlock_irq(&chip->reg_lock);
2523 if (!pending)
2524 return;
2525 msleep(1);
2526 }
2527 }
2528
2529 /* clear irq_pending flags and assure no on-going workq */
2530 static void azx_clear_irq_pending(struct azx *chip)
2531 {
2532 int i;
2533
2534 spin_lock_irq(&chip->reg_lock);
2535 for (i = 0; i < chip->num_streams; i++)
2536 chip->azx_dev[i].irq_pending = 0;
2537 spin_unlock_irq(&chip->reg_lock);
2538 }
2539
2540 #ifdef CONFIG_X86
2541 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2542 struct vm_area_struct *area)
2543 {
2544 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2545 struct azx *chip = apcm->chip;
2546 if (!azx_snoop(chip))
2547 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2548 return snd_pcm_lib_default_mmap(substream, area);
2549 }
2550 #else
2551 #define azx_pcm_mmap NULL
2552 #endif
2553
2554 static struct snd_pcm_ops azx_pcm_ops = {
2555 .open = azx_pcm_open,
2556 .close = azx_pcm_close,
2557 .ioctl = snd_pcm_lib_ioctl,
2558 .hw_params = azx_pcm_hw_params,
2559 .hw_free = azx_pcm_hw_free,
2560 .prepare = azx_pcm_prepare,
2561 .trigger = azx_pcm_trigger,
2562 .pointer = azx_pcm_pointer,
2563 .wall_clock = azx_get_wallclock_tstamp,
2564 .mmap = azx_pcm_mmap,
2565 .page = snd_pcm_sgbuf_ops_page,
2566 };
2567
2568 static void azx_pcm_free(struct snd_pcm *pcm)
2569 {
2570 struct azx_pcm *apcm = pcm->private_data;
2571 if (apcm) {
2572 list_del(&apcm->list);
2573 kfree(apcm);
2574 }
2575 }
2576
2577 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2578
2579 static int
2580 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2581 struct hda_pcm *cpcm)
2582 {
2583 struct azx *chip = bus->private_data;
2584 struct snd_pcm *pcm;
2585 struct azx_pcm *apcm;
2586 int pcm_dev = cpcm->device;
2587 unsigned int size;
2588 int s, err;
2589
2590 list_for_each_entry(apcm, &chip->pcm_list, list) {
2591 if (apcm->pcm->device == pcm_dev) {
2592 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2593 pci_name(chip->pci), pcm_dev);
2594 return -EBUSY;
2595 }
2596 }
2597 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2598 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2599 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2600 &pcm);
2601 if (err < 0)
2602 return err;
2603 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2604 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2605 if (apcm == NULL)
2606 return -ENOMEM;
2607 apcm->chip = chip;
2608 apcm->pcm = pcm;
2609 apcm->codec = codec;
2610 pcm->private_data = apcm;
2611 pcm->private_free = azx_pcm_free;
2612 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2613 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2614 list_add_tail(&apcm->list, &chip->pcm_list);
2615 cpcm->pcm = pcm;
2616 for (s = 0; s < 2; s++) {
2617 apcm->hinfo[s] = &cpcm->stream[s];
2618 if (cpcm->stream[s].substreams)
2619 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2620 }
2621 /* buffer pre-allocation */
2622 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2623 if (size > MAX_PREALLOC_SIZE)
2624 size = MAX_PREALLOC_SIZE;
2625 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2626 snd_dma_pci_data(chip->pci),
2627 size, MAX_PREALLOC_SIZE);
2628 return 0;
2629 }
2630
2631 /*
2632 * mixer creation - all stuff is implemented in hda module
2633 */
2634 static int azx_mixer_create(struct azx *chip)
2635 {
2636 return snd_hda_build_controls(chip->bus);
2637 }
2638
2639
2640 /*
2641 * initialize SD streams
2642 */
2643 static int azx_init_stream(struct azx *chip)
2644 {
2645 int i;
2646
2647 /* initialize each stream (aka device)
2648 * assign the starting bdl address to each stream (device)
2649 * and initialize
2650 */
2651 for (i = 0; i < chip->num_streams; i++) {
2652 struct azx_dev *azx_dev = &chip->azx_dev[i];
2653 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2654 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2655 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2656 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2657 azx_dev->sd_int_sta_mask = 1 << i;
2658 /* stream tag: must be non-zero and unique */
2659 azx_dev->index = i;
2660 azx_dev->stream_tag = i + 1;
2661 }
2662
2663 return 0;
2664 }
2665
2666 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2667 {
2668 if (request_irq(chip->pci->irq, azx_interrupt,
2669 chip->msi ? 0 : IRQF_SHARED,
2670 KBUILD_MODNAME, chip)) {
2671 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2672 "disabling device\n", chip->pci->irq);
2673 if (do_disconnect)
2674 snd_card_disconnect(chip->card);
2675 return -1;
2676 }
2677 chip->irq = chip->pci->irq;
2678 pci_intx(chip->pci, !chip->msi);
2679 return 0;
2680 }
2681
2682
2683 static void azx_stop_chip(struct azx *chip)
2684 {
2685 if (!chip->initialized)
2686 return;
2687
2688 /* disable interrupts */
2689 azx_int_disable(chip);
2690 azx_int_clear(chip);
2691
2692 /* disable CORB/RIRB */
2693 azx_free_cmd_io(chip);
2694
2695 /* disable position buffer */
2696 azx_writel(chip, DPLBASE, 0);
2697 azx_writel(chip, DPUBASE, 0);
2698
2699 chip->initialized = 0;
2700 }
2701
2702 #ifdef CONFIG_SND_HDA_DSP_LOADER
2703 /*
2704 * DSP loading code (e.g. for CA0132)
2705 */
2706
2707 /* use the first stream for loading DSP */
2708 static struct azx_dev *
2709 azx_get_dsp_loader_dev(struct azx *chip)
2710 {
2711 return &chip->azx_dev[chip->playback_index_offset];
2712 }
2713
2714 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2715 unsigned int byte_size,
2716 struct snd_dma_buffer *bufp)
2717 {
2718 u32 *bdl;
2719 struct azx *chip = bus->private_data;
2720 struct azx_dev *azx_dev;
2721 int err;
2722
2723 azx_dev = azx_get_dsp_loader_dev(chip);
2724
2725 dsp_lock(azx_dev);
2726 spin_lock_irq(&chip->reg_lock);
2727 if (azx_dev->running || azx_dev->locked) {
2728 spin_unlock_irq(&chip->reg_lock);
2729 err = -EBUSY;
2730 goto unlock;
2731 }
2732 azx_dev->prepared = 0;
2733 chip->saved_azx_dev = *azx_dev;
2734 azx_dev->locked = 1;
2735 spin_unlock_irq(&chip->reg_lock);
2736
2737 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2738 snd_dma_pci_data(chip->pci),
2739 byte_size, bufp);
2740 if (err < 0)
2741 goto err_alloc;
2742
2743 mark_pages_wc(chip, bufp, true);
2744 azx_dev->bufsize = byte_size;
2745 azx_dev->period_bytes = byte_size;
2746 azx_dev->format_val = format;
2747
2748 azx_stream_reset(chip, azx_dev);
2749
2750 /* reset BDL address */
2751 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2752 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2753
2754 azx_dev->frags = 0;
2755 bdl = (u32 *)azx_dev->bdl.area;
2756 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2757 if (err < 0)
2758 goto error;
2759
2760 azx_setup_controller(chip, azx_dev);
2761 dsp_unlock(azx_dev);
2762 return azx_dev->stream_tag;
2763
2764 error:
2765 mark_pages_wc(chip, bufp, false);
2766 snd_dma_free_pages(bufp);
2767 err_alloc:
2768 spin_lock_irq(&chip->reg_lock);
2769 if (azx_dev->opened)
2770 *azx_dev = chip->saved_azx_dev;
2771 azx_dev->locked = 0;
2772 spin_unlock_irq(&chip->reg_lock);
2773 unlock:
2774 dsp_unlock(azx_dev);
2775 return err;
2776 }
2777
2778 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2779 {
2780 struct azx *chip = bus->private_data;
2781 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2782
2783 if (start)
2784 azx_stream_start(chip, azx_dev);
2785 else
2786 azx_stream_stop(chip, azx_dev);
2787 azx_dev->running = start;
2788 }
2789
2790 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2791 struct snd_dma_buffer *dmab)
2792 {
2793 struct azx *chip = bus->private_data;
2794 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2795
2796 if (!dmab->area || !azx_dev->locked)
2797 return;
2798
2799 dsp_lock(azx_dev);
2800 /* reset BDL address */
2801 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2802 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2803 azx_sd_writel(azx_dev, SD_CTL, 0);
2804 azx_dev->bufsize = 0;
2805 azx_dev->period_bytes = 0;
2806 azx_dev->format_val = 0;
2807
2808 mark_pages_wc(chip, dmab, false);
2809 snd_dma_free_pages(dmab);
2810 dmab->area = NULL;
2811
2812 spin_lock_irq(&chip->reg_lock);
2813 if (azx_dev->opened)
2814 *azx_dev = chip->saved_azx_dev;
2815 azx_dev->locked = 0;
2816 spin_unlock_irq(&chip->reg_lock);
2817 dsp_unlock(azx_dev);
2818 }
2819 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2820
2821 #ifdef CONFIG_PM
2822 /* power-up/down the controller */
2823 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2824 {
2825 struct azx *chip = bus->private_data;
2826
2827 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2828 return;
2829
2830 if (power_up)
2831 pm_runtime_get_sync(&chip->pci->dev);
2832 else
2833 pm_runtime_put_sync(&chip->pci->dev);
2834 }
2835
2836 static DEFINE_MUTEX(card_list_lock);
2837 static LIST_HEAD(card_list);
2838
2839 static void azx_add_card_list(struct azx *chip)
2840 {
2841 mutex_lock(&card_list_lock);
2842 list_add(&chip->list, &card_list);
2843 mutex_unlock(&card_list_lock);
2844 }
2845
2846 static void azx_del_card_list(struct azx *chip)
2847 {
2848 mutex_lock(&card_list_lock);
2849 list_del_init(&chip->list);
2850 mutex_unlock(&card_list_lock);
2851 }
2852
2853 /* trigger power-save check at writing parameter */
2854 static int param_set_xint(const char *val, const struct kernel_param *kp)
2855 {
2856 struct azx *chip;
2857 struct hda_codec *c;
2858 int prev = power_save;
2859 int ret = param_set_int(val, kp);
2860
2861 if (ret || prev == power_save)
2862 return ret;
2863
2864 mutex_lock(&card_list_lock);
2865 list_for_each_entry(chip, &card_list, list) {
2866 if (!chip->bus || chip->disabled)
2867 continue;
2868 list_for_each_entry(c, &chip->bus->codec_list, list)
2869 snd_hda_power_sync(c);
2870 }
2871 mutex_unlock(&card_list_lock);
2872 return 0;
2873 }
2874 #else
2875 #define azx_add_card_list(chip) /* NOP */
2876 #define azx_del_card_list(chip) /* NOP */
2877 #endif /* CONFIG_PM */
2878
2879 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2880 /*
2881 * power management
2882 */
2883 static int azx_suspend(struct device *dev)
2884 {
2885 struct pci_dev *pci = to_pci_dev(dev);
2886 struct snd_card *card = dev_get_drvdata(dev);
2887 struct azx *chip = card->private_data;
2888 struct azx_pcm *p;
2889
2890 if (chip->disabled)
2891 return 0;
2892
2893 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2894 azx_clear_irq_pending(chip);
2895 list_for_each_entry(p, &chip->pcm_list, list)
2896 snd_pcm_suspend_all(p->pcm);
2897 if (chip->initialized)
2898 snd_hda_suspend(chip->bus);
2899 azx_stop_chip(chip);
2900 if (chip->irq >= 0) {
2901 free_irq(chip->irq, chip);
2902 chip->irq = -1;
2903 }
2904 if (chip->msi)
2905 pci_disable_msi(chip->pci);
2906 pci_disable_device(pci);
2907 pci_save_state(pci);
2908 pci_set_power_state(pci, PCI_D3hot);
2909 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2910 hda_display_power(false);
2911 return 0;
2912 }
2913
2914 static int azx_resume(struct device *dev)
2915 {
2916 struct pci_dev *pci = to_pci_dev(dev);
2917 struct snd_card *card = dev_get_drvdata(dev);
2918 struct azx *chip = card->private_data;
2919
2920 if (chip->disabled)
2921 return 0;
2922
2923 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2924 hda_display_power(true);
2925 pci_set_power_state(pci, PCI_D0);
2926 pci_restore_state(pci);
2927 if (pci_enable_device(pci) < 0) {
2928 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2929 "disabling device\n");
2930 snd_card_disconnect(card);
2931 return -EIO;
2932 }
2933 pci_set_master(pci);
2934 if (chip->msi)
2935 if (pci_enable_msi(pci) < 0)
2936 chip->msi = 0;
2937 if (azx_acquire_irq(chip, 1) < 0)
2938 return -EIO;
2939 azx_init_pci(chip);
2940
2941 azx_init_chip(chip, 1);
2942
2943 snd_hda_resume(chip->bus);
2944 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2945 return 0;
2946 }
2947 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2948
2949 #ifdef CONFIG_PM_RUNTIME
2950 static int azx_runtime_suspend(struct device *dev)
2951 {
2952 struct snd_card *card = dev_get_drvdata(dev);
2953 struct azx *chip = card->private_data;
2954
2955 azx_stop_chip(chip);
2956 azx_clear_irq_pending(chip);
2957 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2958 hda_display_power(false);
2959 return 0;
2960 }
2961
2962 static int azx_runtime_resume(struct device *dev)
2963 {
2964 struct snd_card *card = dev_get_drvdata(dev);
2965 struct azx *chip = card->private_data;
2966
2967 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2968 hda_display_power(true);
2969 azx_init_pci(chip);
2970 azx_init_chip(chip, 1);
2971 return 0;
2972 }
2973
2974 static int azx_runtime_idle(struct device *dev)
2975 {
2976 struct snd_card *card = dev_get_drvdata(dev);
2977 struct azx *chip = card->private_data;
2978
2979 if (!power_save_controller ||
2980 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2981 return -EBUSY;
2982
2983 return 0;
2984 }
2985
2986 #endif /* CONFIG_PM_RUNTIME */
2987
2988 #ifdef CONFIG_PM
2989 static const struct dev_pm_ops azx_pm = {
2990 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2991 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
2992 };
2993
2994 #define AZX_PM_OPS &azx_pm
2995 #else
2996 #define AZX_PM_OPS NULL
2997 #endif /* CONFIG_PM */
2998
2999
3000 /*
3001 * reboot notifier for hang-up problem at power-down
3002 */
3003 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3004 {
3005 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
3006 snd_hda_bus_reboot_notify(chip->bus);
3007 azx_stop_chip(chip);
3008 return NOTIFY_OK;
3009 }
3010
3011 static void azx_notifier_register(struct azx *chip)
3012 {
3013 chip->reboot_notifier.notifier_call = azx_halt;
3014 register_reboot_notifier(&chip->reboot_notifier);
3015 }
3016
3017 static void azx_notifier_unregister(struct azx *chip)
3018 {
3019 if (chip->reboot_notifier.notifier_call)
3020 unregister_reboot_notifier(&chip->reboot_notifier);
3021 }
3022
3023 static int azx_probe_continue(struct azx *chip);
3024
3025 #ifdef SUPPORT_VGA_SWITCHEROO
3026 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
3027
3028 static void azx_vs_set_state(struct pci_dev *pci,
3029 enum vga_switcheroo_state state)
3030 {
3031 struct snd_card *card = pci_get_drvdata(pci);
3032 struct azx *chip = card->private_data;
3033 bool disabled;
3034
3035 wait_for_completion(&chip->probe_wait);
3036 if (chip->init_failed)
3037 return;
3038
3039 disabled = (state == VGA_SWITCHEROO_OFF);
3040 if (chip->disabled == disabled)
3041 return;
3042
3043 if (!chip->bus) {
3044 chip->disabled = disabled;
3045 if (!disabled) {
3046 snd_printk(KERN_INFO SFX
3047 "%s: Start delayed initialization\n",
3048 pci_name(chip->pci));
3049 if (azx_probe_continue(chip) < 0) {
3050 snd_printk(KERN_ERR SFX
3051 "%s: initialization error\n",
3052 pci_name(chip->pci));
3053 chip->init_failed = true;
3054 }
3055 }
3056 } else {
3057 snd_printk(KERN_INFO SFX
3058 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3059 disabled ? "Disabling" : "Enabling");
3060 if (disabled) {
3061 azx_suspend(&pci->dev);
3062 chip->disabled = true;
3063 if (snd_hda_lock_devices(chip->bus))
3064 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3065 pci_name(chip->pci));
3066 } else {
3067 snd_hda_unlock_devices(chip->bus);
3068 chip->disabled = false;
3069 azx_resume(&pci->dev);
3070 }
3071 }
3072 }
3073
3074 static bool azx_vs_can_switch(struct pci_dev *pci)
3075 {
3076 struct snd_card *card = pci_get_drvdata(pci);
3077 struct azx *chip = card->private_data;
3078
3079 wait_for_completion(&chip->probe_wait);
3080 if (chip->init_failed)
3081 return false;
3082 if (chip->disabled || !chip->bus)
3083 return true;
3084 if (snd_hda_lock_devices(chip->bus))
3085 return false;
3086 snd_hda_unlock_devices(chip->bus);
3087 return true;
3088 }
3089
3090 static void init_vga_switcheroo(struct azx *chip)
3091 {
3092 struct pci_dev *p = get_bound_vga(chip->pci);
3093 if (p) {
3094 snd_printk(KERN_INFO SFX
3095 "%s: Handle VGA-switcheroo audio client\n",
3096 pci_name(chip->pci));
3097 chip->use_vga_switcheroo = 1;
3098 pci_dev_put(p);
3099 }
3100 }
3101
3102 static const struct vga_switcheroo_client_ops azx_vs_ops = {
3103 .set_gpu_state = azx_vs_set_state,
3104 .can_switch = azx_vs_can_switch,
3105 };
3106
3107 static int register_vga_switcheroo(struct azx *chip)
3108 {
3109 int err;
3110
3111 if (!chip->use_vga_switcheroo)
3112 return 0;
3113 /* FIXME: currently only handling DIS controller
3114 * is there any machine with two switchable HDMI audio controllers?
3115 */
3116 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
3117 VGA_SWITCHEROO_DIS,
3118 chip->bus != NULL);
3119 if (err < 0)
3120 return err;
3121 chip->vga_switcheroo_registered = 1;
3122 return 0;
3123 }
3124 #else
3125 #define init_vga_switcheroo(chip) /* NOP */
3126 #define register_vga_switcheroo(chip) 0
3127 #define check_hdmi_disabled(pci) false
3128 #endif /* SUPPORT_VGA_SWITCHER */
3129
3130 /*
3131 * destructor
3132 */
3133 static int azx_free(struct azx *chip)
3134 {
3135 struct pci_dev *pci = chip->pci;
3136 int i;
3137
3138 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
3139 && chip->running)
3140 pm_runtime_get_noresume(&pci->dev);
3141
3142 azx_del_card_list(chip);
3143
3144 azx_notifier_unregister(chip);
3145
3146 chip->init_failed = 1; /* to be sure */
3147 complete_all(&chip->probe_wait);
3148
3149 if (use_vga_switcheroo(chip)) {
3150 if (chip->disabled && chip->bus)
3151 snd_hda_unlock_devices(chip->bus);
3152 if (chip->vga_switcheroo_registered)
3153 vga_switcheroo_unregister_client(chip->pci);
3154 }
3155
3156 if (chip->initialized) {
3157 azx_clear_irq_pending(chip);
3158 for (i = 0; i < chip->num_streams; i++)
3159 azx_stream_stop(chip, &chip->azx_dev[i]);
3160 azx_stop_chip(chip);
3161 }
3162
3163 if (chip->irq >= 0)
3164 free_irq(chip->irq, (void*)chip);
3165 if (chip->msi)
3166 pci_disable_msi(chip->pci);
3167 if (chip->remap_addr)
3168 iounmap(chip->remap_addr);
3169
3170 if (chip->azx_dev) {
3171 for (i = 0; i < chip->num_streams; i++)
3172 if (chip->azx_dev[i].bdl.area) {
3173 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
3174 snd_dma_free_pages(&chip->azx_dev[i].bdl);
3175 }
3176 }
3177 if (chip->rb.area) {
3178 mark_pages_wc(chip, &chip->rb, false);
3179 snd_dma_free_pages(&chip->rb);
3180 }
3181 if (chip->posbuf.area) {
3182 mark_pages_wc(chip, &chip->posbuf, false);
3183 snd_dma_free_pages(&chip->posbuf);
3184 }
3185 if (chip->region_requested)
3186 pci_release_regions(chip->pci);
3187 pci_disable_device(chip->pci);
3188 kfree(chip->azx_dev);
3189 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3190 if (chip->fw)
3191 release_firmware(chip->fw);
3192 #endif
3193 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3194 hda_display_power(false);
3195 hda_i915_exit();
3196 }
3197 kfree(chip);
3198
3199 return 0;
3200 }
3201
3202 static int azx_dev_free(struct snd_device *device)
3203 {
3204 return azx_free(device->device_data);
3205 }
3206
3207 #ifdef SUPPORT_VGA_SWITCHEROO
3208 /*
3209 * Check of disabled HDMI controller by vga-switcheroo
3210 */
3211 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
3212 {
3213 struct pci_dev *p;
3214
3215 /* check only discrete GPU */
3216 switch (pci->vendor) {
3217 case PCI_VENDOR_ID_ATI:
3218 case PCI_VENDOR_ID_AMD:
3219 case PCI_VENDOR_ID_NVIDIA:
3220 if (pci->devfn == 1) {
3221 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3222 pci->bus->number, 0);
3223 if (p) {
3224 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3225 return p;
3226 pci_dev_put(p);
3227 }
3228 }
3229 break;
3230 }
3231 return NULL;
3232 }
3233
3234 static bool check_hdmi_disabled(struct pci_dev *pci)
3235 {
3236 bool vga_inactive = false;
3237 struct pci_dev *p = get_bound_vga(pci);
3238
3239 if (p) {
3240 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
3241 vga_inactive = true;
3242 pci_dev_put(p);
3243 }
3244 return vga_inactive;
3245 }
3246 #endif /* SUPPORT_VGA_SWITCHEROO */
3247
3248 /*
3249 * white/black-listing for position_fix
3250 */
3251 static struct snd_pci_quirk position_fix_list[] = {
3252 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3253 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3254 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
3255 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3256 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3257 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3258 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3259 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3260 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3261 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3262 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3263 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3264 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3265 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3266 {}
3267 };
3268
3269 static int check_position_fix(struct azx *chip, int fix)
3270 {
3271 const struct snd_pci_quirk *q;
3272
3273 switch (fix) {
3274 case POS_FIX_AUTO:
3275 case POS_FIX_LPIB:
3276 case POS_FIX_POSBUF:
3277 case POS_FIX_VIACOMBO:
3278 case POS_FIX_COMBO:
3279 return fix;
3280 }
3281
3282 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3283 if (q) {
3284 printk(KERN_INFO
3285 "hda_intel: position_fix set to %d "
3286 "for device %04x:%04x\n",
3287 q->value, q->subvendor, q->subdevice);
3288 return q->value;
3289 }
3290
3291 /* Check VIA/ATI HD Audio Controller exist */
3292 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3293 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3294 return POS_FIX_VIACOMBO;
3295 }
3296 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3297 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3298 return POS_FIX_LPIB;
3299 }
3300 return POS_FIX_AUTO;
3301 }
3302
3303 /*
3304 * black-lists for probe_mask
3305 */
3306 static struct snd_pci_quirk probe_mask_list[] = {
3307 /* Thinkpad often breaks the controller communication when accessing
3308 * to the non-working (or non-existing) modem codec slot.
3309 */
3310 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3311 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3312 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3313 /* broken BIOS */
3314 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3315 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3316 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3317 /* forced codec slots */
3318 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3319 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3320 /* WinFast VP200 H (Teradici) user reported broken communication */
3321 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3322 {}
3323 };
3324
3325 #define AZX_FORCE_CODEC_MASK 0x100
3326
3327 static void check_probe_mask(struct azx *chip, int dev)
3328 {
3329 const struct snd_pci_quirk *q;
3330
3331 chip->codec_probe_mask = probe_mask[dev];
3332 if (chip->codec_probe_mask == -1) {
3333 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3334 if (q) {
3335 printk(KERN_INFO
3336 "hda_intel: probe_mask set to 0x%x "
3337 "for device %04x:%04x\n",
3338 q->value, q->subvendor, q->subdevice);
3339 chip->codec_probe_mask = q->value;
3340 }
3341 }
3342
3343 /* check forced option */
3344 if (chip->codec_probe_mask != -1 &&
3345 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3346 chip->codec_mask = chip->codec_probe_mask & 0xff;
3347 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3348 chip->codec_mask);
3349 }
3350 }
3351
3352 /*
3353 * white/black-list for enable_msi
3354 */
3355 static struct snd_pci_quirk msi_black_list[] = {
3356 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3357 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3358 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3359 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3360 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3361 {}
3362 };
3363
3364 static void check_msi(struct azx *chip)
3365 {
3366 const struct snd_pci_quirk *q;
3367
3368 if (enable_msi >= 0) {
3369 chip->msi = !!enable_msi;
3370 return;
3371 }
3372 chip->msi = 1; /* enable MSI as default */
3373 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3374 if (q) {
3375 printk(KERN_INFO
3376 "hda_intel: msi for device %04x:%04x set to %d\n",
3377 q->subvendor, q->subdevice, q->value);
3378 chip->msi = q->value;
3379 return;
3380 }
3381
3382 /* NVidia chipsets seem to cause troubles with MSI */
3383 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3384 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3385 chip->msi = 0;
3386 }
3387 }
3388
3389 /* check the snoop mode availability */
3390 static void azx_check_snoop_available(struct azx *chip)
3391 {
3392 bool snoop = chip->snoop;
3393
3394 switch (chip->driver_type) {
3395 case AZX_DRIVER_VIA:
3396 /* force to non-snoop mode for a new VIA controller
3397 * when BIOS is set
3398 */
3399 if (snoop) {
3400 u8 val;
3401 pci_read_config_byte(chip->pci, 0x42, &val);
3402 if (!(val & 0x80) && chip->pci->revision == 0x30)
3403 snoop = false;
3404 }
3405 break;
3406 case AZX_DRIVER_ATIHDMI_NS:
3407 /* new ATI HDMI requires non-snoop */
3408 snoop = false;
3409 break;
3410 case AZX_DRIVER_CTHDA:
3411 snoop = false;
3412 break;
3413 }
3414
3415 if (snoop != chip->snoop) {
3416 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3417 pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3418 chip->snoop = snoop;
3419 }
3420 }
3421
3422 #ifdef CONFIG_SND_HDA_I915
3423 static void azx_probe_work(struct work_struct *work)
3424 {
3425 azx_probe_continue(container_of(work, struct azx, probe_work));
3426 }
3427 #endif
3428
3429 /*
3430 * constructor
3431 */
3432 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3433 int dev, unsigned int driver_caps,
3434 struct azx **rchip)
3435 {
3436 static struct snd_device_ops ops = {
3437 .dev_free = azx_dev_free,
3438 };
3439 struct azx *chip;
3440 int err;
3441
3442 *rchip = NULL;
3443
3444 err = pci_enable_device(pci);
3445 if (err < 0)
3446 return err;
3447
3448 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3449 if (!chip) {
3450 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3451 pci_disable_device(pci);
3452 return -ENOMEM;
3453 }
3454
3455 spin_lock_init(&chip->reg_lock);
3456 mutex_init(&chip->open_mutex);
3457 chip->card = card;
3458 chip->pci = pci;
3459 chip->irq = -1;
3460 chip->driver_caps = driver_caps;
3461 chip->driver_type = driver_caps & 0xff;
3462 check_msi(chip);
3463 chip->dev_index = dev;
3464 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3465 INIT_LIST_HEAD(&chip->pcm_list);
3466 INIT_LIST_HEAD(&chip->list);
3467 init_vga_switcheroo(chip);
3468 init_completion(&chip->probe_wait);
3469
3470 chip->position_fix[0] = chip->position_fix[1] =
3471 check_position_fix(chip, position_fix[dev]);
3472 /* combo mode uses LPIB for playback */
3473 if (chip->position_fix[0] == POS_FIX_COMBO) {
3474 chip->position_fix[0] = POS_FIX_LPIB;
3475 chip->position_fix[1] = POS_FIX_AUTO;
3476 }
3477
3478 check_probe_mask(chip, dev);
3479
3480 chip->single_cmd = single_cmd;
3481 chip->snoop = hda_snoop;
3482 azx_check_snoop_available(chip);
3483
3484 if (bdl_pos_adj[dev] < 0) {
3485 switch (chip->driver_type) {
3486 case AZX_DRIVER_ICH:
3487 case AZX_DRIVER_PCH:
3488 bdl_pos_adj[dev] = 1;
3489 break;
3490 default:
3491 bdl_pos_adj[dev] = 32;
3492 break;
3493 }
3494 }
3495
3496 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3497 if (err < 0) {
3498 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3499 pci_name(chip->pci));
3500 azx_free(chip);
3501 return err;
3502 }
3503
3504 #ifdef CONFIG_SND_HDA_I915
3505 /* continue probing in work context as may trigger request module */
3506 INIT_WORK(&chip->probe_work, azx_probe_work);
3507 #endif
3508
3509 *rchip = chip;
3510
3511 return 0;
3512 }
3513
3514 static int azx_first_init(struct azx *chip)
3515 {
3516 int dev = chip->dev_index;
3517 struct pci_dev *pci = chip->pci;
3518 struct snd_card *card = chip->card;
3519 int i, err;
3520 unsigned short gcap;
3521
3522 #if BITS_PER_LONG != 64
3523 /* Fix up base address on ULI M5461 */
3524 if (chip->driver_type == AZX_DRIVER_ULI) {
3525 u16 tmp3;
3526 pci_read_config_word(pci, 0x40, &tmp3);
3527 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3528 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3529 }
3530 #endif
3531
3532 err = pci_request_regions(pci, "ICH HD audio");
3533 if (err < 0)
3534 return err;
3535 chip->region_requested = 1;
3536
3537 chip->addr = pci_resource_start(pci, 0);
3538 chip->remap_addr = pci_ioremap_bar(pci, 0);
3539 if (chip->remap_addr == NULL) {
3540 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3541 return -ENXIO;
3542 }
3543
3544 if (chip->msi)
3545 if (pci_enable_msi(pci) < 0)
3546 chip->msi = 0;
3547
3548 if (azx_acquire_irq(chip, 0) < 0)
3549 return -EBUSY;
3550
3551 pci_set_master(pci);
3552 synchronize_irq(chip->irq);
3553
3554 gcap = azx_readw(chip, GCAP);
3555 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3556
3557 /* disable SB600 64bit support for safety */
3558 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3559 struct pci_dev *p_smbus;
3560 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3561 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3562 NULL);
3563 if (p_smbus) {
3564 if (p_smbus->revision < 0x30)
3565 gcap &= ~ICH6_GCAP_64OK;
3566 pci_dev_put(p_smbus);
3567 }
3568 }
3569
3570 /* disable 64bit DMA address on some devices */
3571 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3572 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3573 gcap &= ~ICH6_GCAP_64OK;
3574 }
3575
3576 /* disable buffer size rounding to 128-byte multiples if supported */
3577 if (align_buffer_size >= 0)
3578 chip->align_buffer_size = !!align_buffer_size;
3579 else {
3580 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3581 chip->align_buffer_size = 0;
3582 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3583 chip->align_buffer_size = 1;
3584 else
3585 chip->align_buffer_size = 1;
3586 }
3587
3588 /* allow 64bit DMA address if supported by H/W */
3589 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3590 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3591 else {
3592 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3593 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3594 }
3595
3596 /* read number of streams from GCAP register instead of using
3597 * hardcoded value
3598 */
3599 chip->capture_streams = (gcap >> 8) & 0x0f;
3600 chip->playback_streams = (gcap >> 12) & 0x0f;
3601 if (!chip->playback_streams && !chip->capture_streams) {
3602 /* gcap didn't give any info, switching to old method */
3603
3604 switch (chip->driver_type) {
3605 case AZX_DRIVER_ULI:
3606 chip->playback_streams = ULI_NUM_PLAYBACK;
3607 chip->capture_streams = ULI_NUM_CAPTURE;
3608 break;
3609 case AZX_DRIVER_ATIHDMI:
3610 case AZX_DRIVER_ATIHDMI_NS:
3611 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3612 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3613 break;
3614 case AZX_DRIVER_GENERIC:
3615 default:
3616 chip->playback_streams = ICH6_NUM_PLAYBACK;
3617 chip->capture_streams = ICH6_NUM_CAPTURE;
3618 break;
3619 }
3620 }
3621 chip->capture_index_offset = 0;
3622 chip->playback_index_offset = chip->capture_streams;
3623 chip->num_streams = chip->playback_streams + chip->capture_streams;
3624 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3625 GFP_KERNEL);
3626 if (!chip->azx_dev) {
3627 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
3628 return -ENOMEM;
3629 }
3630
3631 for (i = 0; i < chip->num_streams; i++) {
3632 dsp_lock_init(&chip->azx_dev[i]);
3633 /* allocate memory for the BDL for each stream */
3634 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3635 snd_dma_pci_data(chip->pci),
3636 BDL_SIZE, &chip->azx_dev[i].bdl);
3637 if (err < 0) {
3638 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
3639 return -ENOMEM;
3640 }
3641 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3642 }
3643 /* allocate memory for the position buffer */
3644 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3645 snd_dma_pci_data(chip->pci),
3646 chip->num_streams * 8, &chip->posbuf);
3647 if (err < 0) {
3648 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
3649 return -ENOMEM;
3650 }
3651 mark_pages_wc(chip, &chip->posbuf, true);
3652 /* allocate CORB/RIRB */
3653 err = azx_alloc_cmd_io(chip);
3654 if (err < 0)
3655 return err;
3656
3657 /* initialize streams */
3658 azx_init_stream(chip);
3659
3660 /* initialize chip */
3661 azx_init_pci(chip);
3662 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3663
3664 /* codec detection */
3665 if (!chip->codec_mask) {
3666 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
3667 return -ENODEV;
3668 }
3669
3670 strcpy(card->driver, "HDA-Intel");
3671 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3672 sizeof(card->shortname));
3673 snprintf(card->longname, sizeof(card->longname),
3674 "%s at 0x%lx irq %i",
3675 card->shortname, chip->addr, chip->irq);
3676
3677 return 0;
3678 }
3679
3680 static void power_down_all_codecs(struct azx *chip)
3681 {
3682 #ifdef CONFIG_PM
3683 /* The codecs were powered up in snd_hda_codec_new().
3684 * Now all initialization done, so turn them down if possible
3685 */
3686 struct hda_codec *codec;
3687 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3688 snd_hda_power_down(codec);
3689 }
3690 #endif
3691 }
3692
3693 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3694 /* callback from request_firmware_nowait() */
3695 static void azx_firmware_cb(const struct firmware *fw, void *context)
3696 {
3697 struct snd_card *card = context;
3698 struct azx *chip = card->private_data;
3699 struct pci_dev *pci = chip->pci;
3700
3701 if (!fw) {
3702 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3703 pci_name(chip->pci));
3704 goto error;
3705 }
3706
3707 chip->fw = fw;
3708 if (!chip->disabled) {
3709 /* continue probing */
3710 if (azx_probe_continue(chip))
3711 goto error;
3712 }
3713 return; /* OK */
3714
3715 error:
3716 snd_card_free(card);
3717 pci_set_drvdata(pci, NULL);
3718 }
3719 #endif
3720
3721 static int azx_probe(struct pci_dev *pci,
3722 const struct pci_device_id *pci_id)
3723 {
3724 static int dev;
3725 struct snd_card *card;
3726 struct azx *chip;
3727 bool probe_now;
3728 int err;
3729
3730 if (dev >= SNDRV_CARDS)
3731 return -ENODEV;
3732 if (!enable[dev]) {
3733 dev++;
3734 return -ENOENT;
3735 }
3736
3737 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3738 if (err < 0) {
3739 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
3740 return err;
3741 }
3742
3743 snd_card_set_dev(card, &pci->dev);
3744
3745 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3746 if (err < 0)
3747 goto out_free;
3748 card->private_data = chip;
3749
3750 pci_set_drvdata(pci, card);
3751
3752 err = register_vga_switcheroo(chip);
3753 if (err < 0) {
3754 snd_printk(KERN_ERR SFX
3755 "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
3756 goto out_free;
3757 }
3758
3759 if (check_hdmi_disabled(pci)) {
3760 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
3761 pci_name(pci));
3762 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
3763 chip->disabled = true;
3764 }
3765
3766 probe_now = !chip->disabled;
3767
3768 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3769 if (patch[dev] && *patch[dev]) {
3770 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3771 pci_name(pci), patch[dev]);
3772 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3773 &pci->dev, GFP_KERNEL, card,
3774 azx_firmware_cb);
3775 if (err < 0)
3776 goto out_free;
3777 probe_now = false; /* continued in azx_firmware_cb() */
3778 }
3779 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3780
3781 /* continue probing in work context, avoid request_module deadlock */
3782 if (probe_now && (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)) {
3783 #ifdef CONFIG_SND_HDA_I915
3784 probe_now = false;
3785 schedule_work(&chip->probe_work);
3786 #else
3787 snd_printk(KERN_ERR SFX "Haswell must build in CONFIG_SND_HDA_I915\n");
3788 #endif
3789 }
3790
3791 if (probe_now) {
3792 err = azx_probe_continue(chip);
3793 if (err < 0)
3794 goto out_free;
3795 }
3796
3797 dev++;
3798 complete_all(&chip->probe_wait);
3799 return 0;
3800
3801 out_free:
3802 snd_card_free(card);
3803 pci_set_drvdata(pci, NULL);
3804 return err;
3805 }
3806
3807 static int azx_probe_continue(struct azx *chip)
3808 {
3809 struct pci_dev *pci = chip->pci;
3810 int dev = chip->dev_index;
3811 int err;
3812
3813 /* Request power well for Haswell HDA controller and codec */
3814 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3815 err = hda_i915_init();
3816 if (err < 0) {
3817 snd_printk(KERN_ERR SFX "Error request power-well from i915\n");
3818 goto out_free;
3819 }
3820 hda_display_power(true);
3821 }
3822
3823 err = azx_first_init(chip);
3824 if (err < 0)
3825 goto out_free;
3826
3827 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3828 chip->beep_mode = beep_mode[dev];
3829 #endif
3830
3831 /* create codec instances */
3832 err = azx_codec_create(chip, model[dev]);
3833 if (err < 0)
3834 goto out_free;
3835 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3836 if (chip->fw) {
3837 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3838 chip->fw->data);
3839 if (err < 0)
3840 goto out_free;
3841 #ifndef CONFIG_PM
3842 release_firmware(chip->fw); /* no longer needed */
3843 chip->fw = NULL;
3844 #endif
3845 }
3846 #endif
3847 if ((probe_only[dev] & 1) == 0) {
3848 err = azx_codec_configure(chip);
3849 if (err < 0)
3850 goto out_free;
3851 }
3852
3853 /* create PCM streams */
3854 err = snd_hda_build_pcms(chip->bus);
3855 if (err < 0)
3856 goto out_free;
3857
3858 /* create mixer controls */
3859 err = azx_mixer_create(chip);
3860 if (err < 0)
3861 goto out_free;
3862
3863 err = snd_card_register(chip->card);
3864 if (err < 0)
3865 goto out_free;
3866
3867 chip->running = 1;
3868 power_down_all_codecs(chip);
3869 azx_notifier_register(chip);
3870 azx_add_card_list(chip);
3871 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
3872 pm_runtime_put_noidle(&pci->dev);
3873
3874 return 0;
3875
3876 out_free:
3877 chip->init_failed = 1;
3878 return err;
3879 }
3880
3881 static void azx_remove(struct pci_dev *pci)
3882 {
3883 struct snd_card *card = pci_get_drvdata(pci);
3884
3885 if (card)
3886 snd_card_free(card);
3887 pci_set_drvdata(pci, NULL);
3888 }
3889
3890 /* PCI IDs */
3891 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3892 /* CPT */
3893 { PCI_DEVICE(0x8086, 0x1c20),
3894 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3895 /* PBG */
3896 { PCI_DEVICE(0x8086, 0x1d20),
3897 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3898 /* Panther Point */
3899 { PCI_DEVICE(0x8086, 0x1e20),
3900 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3901 /* Lynx Point */
3902 { PCI_DEVICE(0x8086, 0x8c20),
3903 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3904 /* Wellsburg */
3905 { PCI_DEVICE(0x8086, 0x8d20),
3906 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3907 { PCI_DEVICE(0x8086, 0x8d21),
3908 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3909 /* Lynx Point-LP */
3910 { PCI_DEVICE(0x8086, 0x9c20),
3911 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3912 /* Lynx Point-LP */
3913 { PCI_DEVICE(0x8086, 0x9c21),
3914 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3915 /* Haswell */
3916 { PCI_DEVICE(0x8086, 0x0a0c),
3917 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
3918 AZX_DCAPS_I915_POWERWELL },
3919 { PCI_DEVICE(0x8086, 0x0c0c),
3920 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
3921 AZX_DCAPS_I915_POWERWELL },
3922 { PCI_DEVICE(0x8086, 0x0d0c),
3923 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH |
3924 AZX_DCAPS_I915_POWERWELL },
3925 /* 5 Series/3400 */
3926 { PCI_DEVICE(0x8086, 0x3b56),
3927 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3928 /* Poulsbo */
3929 { PCI_DEVICE(0x8086, 0x811b),
3930 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3931 /* Oaktrail */
3932 { PCI_DEVICE(0x8086, 0x080a),
3933 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3934 /* ICH */
3935 { PCI_DEVICE(0x8086, 0x2668),
3936 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3937 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3938 { PCI_DEVICE(0x8086, 0x27d8),
3939 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3940 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3941 { PCI_DEVICE(0x8086, 0x269a),
3942 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3943 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3944 { PCI_DEVICE(0x8086, 0x284b),
3945 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3946 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3947 { PCI_DEVICE(0x8086, 0x293e),
3948 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3949 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3950 { PCI_DEVICE(0x8086, 0x293f),
3951 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3952 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3953 { PCI_DEVICE(0x8086, 0x3a3e),
3954 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3955 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3956 { PCI_DEVICE(0x8086, 0x3a6e),
3957 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3958 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3959 /* Generic Intel */
3960 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3961 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3962 .class_mask = 0xffffff,
3963 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3964 /* ATI SB 450/600/700/800/900 */
3965 { PCI_DEVICE(0x1002, 0x437b),
3966 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3967 { PCI_DEVICE(0x1002, 0x4383),
3968 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3969 /* AMD Hudson */
3970 { PCI_DEVICE(0x1022, 0x780d),
3971 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3972 /* ATI HDMI */
3973 { PCI_DEVICE(0x1002, 0x793b),
3974 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3975 { PCI_DEVICE(0x1002, 0x7919),
3976 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3977 { PCI_DEVICE(0x1002, 0x960f),
3978 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3979 { PCI_DEVICE(0x1002, 0x970f),
3980 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3981 { PCI_DEVICE(0x1002, 0xaa00),
3982 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3983 { PCI_DEVICE(0x1002, 0xaa08),
3984 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3985 { PCI_DEVICE(0x1002, 0xaa10),
3986 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3987 { PCI_DEVICE(0x1002, 0xaa18),
3988 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3989 { PCI_DEVICE(0x1002, 0xaa20),
3990 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3991 { PCI_DEVICE(0x1002, 0xaa28),
3992 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3993 { PCI_DEVICE(0x1002, 0xaa30),
3994 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3995 { PCI_DEVICE(0x1002, 0xaa38),
3996 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3997 { PCI_DEVICE(0x1002, 0xaa40),
3998 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3999 { PCI_DEVICE(0x1002, 0xaa48),
4000 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4001 { PCI_DEVICE(0x1002, 0x9902),
4002 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4003 { PCI_DEVICE(0x1002, 0xaaa0),
4004 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4005 { PCI_DEVICE(0x1002, 0xaaa8),
4006 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4007 { PCI_DEVICE(0x1002, 0xaab0),
4008 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4009 /* VIA VT8251/VT8237A */
4010 { PCI_DEVICE(0x1106, 0x3288),
4011 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
4012 /* VIA GFX VT7122/VX900 */
4013 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
4014 /* VIA GFX VT6122/VX11 */
4015 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
4016 /* SIS966 */
4017 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
4018 /* ULI M5461 */
4019 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
4020 /* NVIDIA MCP */
4021 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
4022 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4023 .class_mask = 0xffffff,
4024 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
4025 /* Teradici */
4026 { PCI_DEVICE(0x6549, 0x1200),
4027 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4028 { PCI_DEVICE(0x6549, 0x2200),
4029 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4030 /* Creative X-Fi (CA0110-IBG) */
4031 /* CTHDA chips */
4032 { PCI_DEVICE(0x1102, 0x0010),
4033 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4034 { PCI_DEVICE(0x1102, 0x0012),
4035 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4036 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
4037 /* the following entry conflicts with snd-ctxfi driver,
4038 * as ctxfi driver mutates from HD-audio to native mode with
4039 * a special command sequence.
4040 */
4041 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4042 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4043 .class_mask = 0xffffff,
4044 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4045 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4046 #else
4047 /* this entry seems still valid -- i.e. without emu20kx chip */
4048 { PCI_DEVICE(0x1102, 0x0009),
4049 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4050 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4051 #endif
4052 /* Vortex86MX */
4053 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
4054 /* VMware HDAudio */
4055 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
4056 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
4057 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4058 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4059 .class_mask = 0xffffff,
4060 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4061 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4062 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4063 .class_mask = 0xffffff,
4064 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4065 { 0, }
4066 };
4067 MODULE_DEVICE_TABLE(pci, azx_ids);
4068
4069 /* pci_driver definition */
4070 static struct pci_driver azx_driver = {
4071 .name = KBUILD_MODNAME,
4072 .id_table = azx_ids,
4073 .probe = azx_probe,
4074 .remove = azx_remove,
4075 .driver = {
4076 .pm = AZX_PM_OPS,
4077 },
4078 };
4079
4080 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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