3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 * Matt Jared matt.jared@intel.com
27 * Andy Kopp andy.kopp@intel.com
28 * Dan Kogan dan.d.kogan@intel.com
32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
36 #include <sound/driver.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
52 static int index
= SNDRV_DEFAULT_IDX1
;
53 static char *id
= SNDRV_DEFAULT_STR1
;
55 static int position_fix
;
56 static int probe_mask
= -1;
57 static int single_cmd
;
58 static int disable_msi
;
60 module_param(index
, int, 0444);
61 MODULE_PARM_DESC(index
, "Index value for Intel HD audio interface.");
62 module_param(id
, charp
, 0444);
63 MODULE_PARM_DESC(id
, "ID string for Intel HD audio interface.");
64 module_param(model
, charp
, 0444);
65 MODULE_PARM_DESC(model
, "Use the given board model.");
66 module_param(position_fix
, int, 0444);
67 MODULE_PARM_DESC(position_fix
, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
68 module_param(probe_mask
, int, 0444);
69 MODULE_PARM_DESC(probe_mask
, "Bitmask to probe codecs (default = -1).");
70 module_param(single_cmd
, bool, 0444);
71 MODULE_PARM_DESC(single_cmd
, "Use single command to communicate with codecs (for debugging only).");
72 module_param(disable_msi
, int, 0);
73 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
76 /* just for backward compatibility */
78 module_param(enable
, bool, 0444);
80 MODULE_LICENSE("GPL");
81 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
93 MODULE_DESCRIPTION("Intel HDA driver");
95 #define SFX "hda-intel: "
100 #define ICH6_REG_GCAP 0x00
101 #define ICH6_REG_VMIN 0x02
102 #define ICH6_REG_VMAJ 0x03
103 #define ICH6_REG_OUTPAY 0x04
104 #define ICH6_REG_INPAY 0x06
105 #define ICH6_REG_GCTL 0x08
106 #define ICH6_REG_WAKEEN 0x0c
107 #define ICH6_REG_STATESTS 0x0e
108 #define ICH6_REG_GSTS 0x10
109 #define ICH6_REG_INTCTL 0x20
110 #define ICH6_REG_INTSTS 0x24
111 #define ICH6_REG_WALCLK 0x30
112 #define ICH6_REG_SYNC 0x34
113 #define ICH6_REG_CORBLBASE 0x40
114 #define ICH6_REG_CORBUBASE 0x44
115 #define ICH6_REG_CORBWP 0x48
116 #define ICH6_REG_CORBRP 0x4A
117 #define ICH6_REG_CORBCTL 0x4c
118 #define ICH6_REG_CORBSTS 0x4d
119 #define ICH6_REG_CORBSIZE 0x4e
121 #define ICH6_REG_RIRBLBASE 0x50
122 #define ICH6_REG_RIRBUBASE 0x54
123 #define ICH6_REG_RIRBWP 0x58
124 #define ICH6_REG_RINTCNT 0x5a
125 #define ICH6_REG_RIRBCTL 0x5c
126 #define ICH6_REG_RIRBSTS 0x5d
127 #define ICH6_REG_RIRBSIZE 0x5e
129 #define ICH6_REG_IC 0x60
130 #define ICH6_REG_IR 0x64
131 #define ICH6_REG_IRS 0x68
132 #define ICH6_IRS_VALID (1<<1)
133 #define ICH6_IRS_BUSY (1<<0)
135 #define ICH6_REG_DPLBASE 0x70
136 #define ICH6_REG_DPUBASE 0x74
137 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
139 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
140 enum { SDI0
, SDI1
, SDI2
, SDI3
, SDO0
, SDO1
, SDO2
, SDO3
};
142 /* stream register offsets from stream base */
143 #define ICH6_REG_SD_CTL 0x00
144 #define ICH6_REG_SD_STS 0x03
145 #define ICH6_REG_SD_LPIB 0x04
146 #define ICH6_REG_SD_CBL 0x08
147 #define ICH6_REG_SD_LVI 0x0c
148 #define ICH6_REG_SD_FIFOW 0x0e
149 #define ICH6_REG_SD_FIFOSIZE 0x10
150 #define ICH6_REG_SD_FORMAT 0x12
151 #define ICH6_REG_SD_BDLPL 0x18
152 #define ICH6_REG_SD_BDLPU 0x1c
155 #define ICH6_PCIREG_TCSEL 0x44
161 /* max number of SDs */
162 /* ICH, ATI and VIA have 4 playback and 4 capture */
163 #define ICH6_CAPTURE_INDEX 0
164 #define ICH6_NUM_CAPTURE 4
165 #define ICH6_PLAYBACK_INDEX 4
166 #define ICH6_NUM_PLAYBACK 4
168 /* ULI has 6 playback and 5 capture */
169 #define ULI_CAPTURE_INDEX 0
170 #define ULI_NUM_CAPTURE 5
171 #define ULI_PLAYBACK_INDEX 5
172 #define ULI_NUM_PLAYBACK 6
174 /* ATI HDMI has 1 playback and 0 capture */
175 #define ATIHDMI_CAPTURE_INDEX 0
176 #define ATIHDMI_NUM_CAPTURE 0
177 #define ATIHDMI_PLAYBACK_INDEX 0
178 #define ATIHDMI_NUM_PLAYBACK 1
180 /* this number is statically defined for simplicity */
181 #define MAX_AZX_DEV 16
183 /* max number of fragments - we may use more if allocating more pages for BDL */
184 #define BDL_SIZE PAGE_ALIGN(8192)
185 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
186 /* max buffer size - no h/w limit, you can increase as you like */
187 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
188 /* max number of PCM devics per card */
189 #define AZX_MAX_AUDIO_PCMS 6
190 #define AZX_MAX_MODEM_PCMS 2
191 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
193 /* RIRB int mask: overrun[2], response[0] */
194 #define RIRB_INT_RESPONSE 0x01
195 #define RIRB_INT_OVERRUN 0x04
196 #define RIRB_INT_MASK 0x05
198 /* STATESTS int mask: SD2,SD1,SD0 */
199 #define STATESTS_INT_MASK 0x07
200 #define AZX_MAX_CODECS 4
203 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
204 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
205 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
206 #define SD_CTL_STREAM_TAG_SHIFT 20
208 /* SD_CTL and SD_STS */
209 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
210 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
211 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
212 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
215 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
217 /* INTCTL and INTSTS */
218 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
219 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
220 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
222 /* GCTL unsolicited response enable bit */
223 #define ICH6_GCTL_UREN (1<<8)
226 #define ICH6_GCTL_RESET (1<<0)
228 /* CORB/RIRB control, read/write pointer */
229 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
230 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
231 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
232 /* below are so far hardcoded - should read registers in future */
233 #define ICH6_MAX_CORB_ENTRIES 256
234 #define ICH6_MAX_RIRB_ENTRIES 256
236 /* position fix mode */
244 /* Defines for ATI HD Audio support in SB450 south bridge */
245 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
246 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
248 /* Defines for Nvidia HDA support */
249 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
250 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
256 u32
*bdl
; /* virtual address of the BDL */
257 dma_addr_t bdl_addr
; /* physical address of the BDL */
258 u32
*posbuf
; /* position buffer pointer */
260 unsigned int bufsize
; /* size of the play buffer in bytes */
261 unsigned int fragsize
; /* size of each period in bytes */
262 unsigned int frags
; /* number for period in the play buffer */
263 unsigned int fifo_size
; /* FIFO size */
265 void __iomem
*sd_addr
; /* stream descriptor pointer */
267 u32 sd_int_sta_mask
; /* stream int status mask */
270 struct snd_pcm_substream
*substream
; /* assigned substream, set in PCM open */
271 unsigned int format_val
; /* format value to be set in the controller and the codec */
272 unsigned char stream_tag
; /* assigned stream */
273 unsigned char index
; /* stream index */
274 /* for sanity check of position buffer */
275 unsigned int period_intr
;
277 unsigned int opened
:1;
278 unsigned int running
:1;
283 u32
*buf
; /* CORB/RIRB buffer
284 * Each CORB entry is 4byte, RIRB is 8byte
286 dma_addr_t addr
; /* physical address of CORB/RIRB buffer */
288 unsigned short rp
, wp
; /* read/write pointers */
289 int cmds
; /* number of pending requests */
290 u32 res
; /* last read value */
294 struct snd_card
*card
;
297 /* chip type specific */
299 int playback_streams
;
300 int playback_index_offset
;
302 int capture_index_offset
;
307 void __iomem
*remap_addr
;
312 struct mutex open_mutex
;
314 /* streams (x num_streams) */
315 struct azx_dev
*azx_dev
;
318 unsigned int pcm_devs
;
319 struct snd_pcm
*pcm
[AZX_MAX_PCMS
];
322 unsigned short codec_mask
;
329 /* BDL, CORB/RIRB and position buffers */
330 struct snd_dma_buffer bdl
;
331 struct snd_dma_buffer rb
;
332 struct snd_dma_buffer posbuf
;
336 unsigned int initialized
:1;
337 unsigned int single_cmd
:1;
338 unsigned int polling_mode
:1;
352 static char *driver_short_names
[] __devinitdata
= {
353 [AZX_DRIVER_ICH
] = "HDA Intel",
354 [AZX_DRIVER_ATI
] = "HDA ATI SB",
355 [AZX_DRIVER_ATIHDMI
] = "HDA ATI HDMI",
356 [AZX_DRIVER_VIA
] = "HDA VIA VT82xx",
357 [AZX_DRIVER_SIS
] = "HDA SIS966",
358 [AZX_DRIVER_ULI
] = "HDA ULI M5461",
359 [AZX_DRIVER_NVIDIA
] = "HDA NVidia",
363 * macros for easy use
365 #define azx_writel(chip,reg,value) \
366 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
367 #define azx_readl(chip,reg) \
368 readl((chip)->remap_addr + ICH6_REG_##reg)
369 #define azx_writew(chip,reg,value) \
370 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
371 #define azx_readw(chip,reg) \
372 readw((chip)->remap_addr + ICH6_REG_##reg)
373 #define azx_writeb(chip,reg,value) \
374 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
375 #define azx_readb(chip,reg) \
376 readb((chip)->remap_addr + ICH6_REG_##reg)
378 #define azx_sd_writel(dev,reg,value) \
379 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
380 #define azx_sd_readl(dev,reg) \
381 readl((dev)->sd_addr + ICH6_REG_##reg)
382 #define azx_sd_writew(dev,reg,value) \
383 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
384 #define azx_sd_readw(dev,reg) \
385 readw((dev)->sd_addr + ICH6_REG_##reg)
386 #define azx_sd_writeb(dev,reg,value) \
387 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
388 #define azx_sd_readb(dev,reg) \
389 readb((dev)->sd_addr + ICH6_REG_##reg)
391 /* for pcm support */
392 #define get_azx_dev(substream) (substream->runtime->private_data)
394 /* Get the upper 32bit of the given dma_addr_t
395 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
397 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
401 * Interface for HD codec
405 * CORB / RIRB interface
407 static int azx_alloc_cmd_io(struct azx
*chip
)
411 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
412 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
413 PAGE_SIZE
, &chip
->rb
);
415 snd_printk(KERN_ERR SFX
"cannot allocate CORB/RIRB\n");
421 static void azx_init_cmd_io(struct azx
*chip
)
424 chip
->corb
.addr
= chip
->rb
.addr
;
425 chip
->corb
.buf
= (u32
*)chip
->rb
.area
;
426 azx_writel(chip
, CORBLBASE
, (u32
)chip
->corb
.addr
);
427 azx_writel(chip
, CORBUBASE
, upper_32bit(chip
->corb
.addr
));
429 /* set the corb size to 256 entries (ULI requires explicitly) */
430 azx_writeb(chip
, CORBSIZE
, 0x02);
431 /* set the corb write pointer to 0 */
432 azx_writew(chip
, CORBWP
, 0);
433 /* reset the corb hw read pointer */
434 azx_writew(chip
, CORBRP
, ICH6_RBRWP_CLR
);
435 /* enable corb dma */
436 azx_writeb(chip
, CORBCTL
, ICH6_RBCTL_DMA_EN
);
439 chip
->rirb
.addr
= chip
->rb
.addr
+ 2048;
440 chip
->rirb
.buf
= (u32
*)(chip
->rb
.area
+ 2048);
441 azx_writel(chip
, RIRBLBASE
, (u32
)chip
->rirb
.addr
);
442 azx_writel(chip
, RIRBUBASE
, upper_32bit(chip
->rirb
.addr
));
444 /* set the rirb size to 256 entries (ULI requires explicitly) */
445 azx_writeb(chip
, RIRBSIZE
, 0x02);
446 /* reset the rirb hw write pointer */
447 azx_writew(chip
, RIRBWP
, ICH6_RBRWP_CLR
);
448 /* set N=1, get RIRB response interrupt for new entry */
449 azx_writew(chip
, RINTCNT
, 1);
450 /* enable rirb dma and response irq */
451 azx_writeb(chip
, RIRBCTL
, ICH6_RBCTL_DMA_EN
| ICH6_RBCTL_IRQ_EN
);
452 chip
->rirb
.rp
= chip
->rirb
.cmds
= 0;
455 static void azx_free_cmd_io(struct azx
*chip
)
457 /* disable ringbuffer DMAs */
458 azx_writeb(chip
, RIRBCTL
, 0);
459 azx_writeb(chip
, CORBCTL
, 0);
463 static int azx_corb_send_cmd(struct hda_codec
*codec
, hda_nid_t nid
, int direct
,
464 unsigned int verb
, unsigned int para
)
466 struct azx
*chip
= codec
->bus
->private_data
;
470 val
= (u32
)(codec
->addr
& 0x0f) << 28;
471 val
|= (u32
)direct
<< 27;
472 val
|= (u32
)nid
<< 20;
476 /* add command to corb */
477 wp
= azx_readb(chip
, CORBWP
);
479 wp
%= ICH6_MAX_CORB_ENTRIES
;
481 spin_lock_irq(&chip
->reg_lock
);
483 chip
->corb
.buf
[wp
] = cpu_to_le32(val
);
484 azx_writel(chip
, CORBWP
, wp
);
485 spin_unlock_irq(&chip
->reg_lock
);
490 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
492 /* retrieve RIRB entry - called from interrupt handler */
493 static void azx_update_rirb(struct azx
*chip
)
498 wp
= azx_readb(chip
, RIRBWP
);
499 if (wp
== chip
->rirb
.wp
)
503 while (chip
->rirb
.rp
!= wp
) {
505 chip
->rirb
.rp
%= ICH6_MAX_RIRB_ENTRIES
;
507 rp
= chip
->rirb
.rp
<< 1; /* an RIRB entry is 8-bytes */
508 res_ex
= le32_to_cpu(chip
->rirb
.buf
[rp
+ 1]);
509 res
= le32_to_cpu(chip
->rirb
.buf
[rp
]);
510 if (res_ex
& ICH6_RIRB_EX_UNSOL_EV
)
511 snd_hda_queue_unsol_event(chip
->bus
, res
, res_ex
);
512 else if (chip
->rirb
.cmds
) {
514 chip
->rirb
.res
= res
;
519 /* receive a response */
520 static unsigned int azx_rirb_get_response(struct hda_codec
*codec
)
522 struct azx
*chip
= codec
->bus
->private_data
;
526 if (chip
->polling_mode
) {
527 spin_lock_irq(&chip
->reg_lock
);
528 azx_update_rirb(chip
);
529 spin_unlock_irq(&chip
->reg_lock
);
531 if (! chip
->rirb
.cmds
)
534 if (! chip
->polling_mode
) {
535 snd_printk(KERN_WARNING
"hda_intel: "
536 "azx_get_response timeout, "
537 "switching to polling mode...\n");
538 chip
->polling_mode
= 1;
543 "hda_intel: azx_get_response timeout, "
544 "switching to single_cmd mode...\n");
545 chip
->rirb
.rp
= azx_readb(chip
, RIRBWP
);
547 /* switch to single_cmd mode */
548 chip
->single_cmd
= 1;
549 azx_free_cmd_io(chip
);
554 return chip
->rirb
.res
; /* the last value */
558 * Use the single immediate command instead of CORB/RIRB for simplicity
560 * Note: according to Intel, this is not preferred use. The command was
561 * intended for the BIOS only, and may get confused with unsolicited
562 * responses. So, we shouldn't use it for normal operation from the
564 * I left the codes, however, for debugging/testing purposes.
568 static int azx_single_send_cmd(struct hda_codec
*codec
, hda_nid_t nid
,
569 int direct
, unsigned int verb
,
572 struct azx
*chip
= codec
->bus
->private_data
;
576 val
= (u32
)(codec
->addr
& 0x0f) << 28;
577 val
|= (u32
)direct
<< 27;
578 val
|= (u32
)nid
<< 20;
583 /* check ICB busy bit */
584 if (! (azx_readw(chip
, IRS
) & ICH6_IRS_BUSY
)) {
585 /* Clear IRV valid bit */
586 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) | ICH6_IRS_VALID
);
587 azx_writel(chip
, IC
, val
);
588 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) | ICH6_IRS_BUSY
);
593 snd_printd(SFX
"send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip
, IRS
), val
);
597 /* receive a response */
598 static unsigned int azx_single_get_response(struct hda_codec
*codec
)
600 struct azx
*chip
= codec
->bus
->private_data
;
604 /* check IRV busy bit */
605 if (azx_readw(chip
, IRS
) & ICH6_IRS_VALID
)
606 return azx_readl(chip
, IR
);
609 snd_printd(SFX
"get_response timeout: IRS=0x%x\n", azx_readw(chip
, IRS
));
610 return (unsigned int)-1;
614 * The below are the main callbacks from hda_codec.
616 * They are just the skeleton to call sub-callbacks according to the
617 * current setting of chip->single_cmd.
621 static int azx_send_cmd(struct hda_codec
*codec
, hda_nid_t nid
,
622 int direct
, unsigned int verb
,
625 struct azx
*chip
= codec
->bus
->private_data
;
626 if (chip
->single_cmd
)
627 return azx_single_send_cmd(codec
, nid
, direct
, verb
, para
);
629 return azx_corb_send_cmd(codec
, nid
, direct
, verb
, para
);
633 static unsigned int azx_get_response(struct hda_codec
*codec
)
635 struct azx
*chip
= codec
->bus
->private_data
;
636 if (chip
->single_cmd
)
637 return azx_single_get_response(codec
);
639 return azx_rirb_get_response(codec
);
643 /* reset codec link */
644 static int azx_reset(struct azx
*chip
)
648 /* reset controller */
649 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) & ~ICH6_GCTL_RESET
);
652 while (azx_readb(chip
, GCTL
) && --count
)
655 /* delay for >= 100us for codec PLL to settle per spec
656 * Rev 0.9 section 5.5.1
660 /* Bring controller out of reset */
661 azx_writeb(chip
, GCTL
, azx_readb(chip
, GCTL
) | ICH6_GCTL_RESET
);
664 while (!azx_readb(chip
, GCTL
) && --count
)
667 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
670 /* check to see if controller is ready */
671 if (!azx_readb(chip
, GCTL
)) {
672 snd_printd("azx_reset: controller not ready!\n");
676 /* Accept unsolicited responses */
677 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) | ICH6_GCTL_UREN
);
680 if (!chip
->codec_mask
) {
681 chip
->codec_mask
= azx_readw(chip
, STATESTS
);
682 snd_printdd("codec_mask = 0x%x\n", chip
->codec_mask
);
693 /* enable interrupts */
694 static void azx_int_enable(struct azx
*chip
)
696 /* enable controller CIE and GIE */
697 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) |
698 ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
);
701 /* disable interrupts */
702 static void azx_int_disable(struct azx
*chip
)
706 /* disable interrupts in stream descriptor */
707 for (i
= 0; i
< chip
->num_streams
; i
++) {
708 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
709 azx_sd_writeb(azx_dev
, SD_CTL
,
710 azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_INT_MASK
);
713 /* disable SIE for all streams */
714 azx_writeb(chip
, INTCTL
, 0);
716 /* disable controller CIE and GIE */
717 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) &
718 ~(ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
));
721 /* clear interrupts */
722 static void azx_int_clear(struct azx
*chip
)
726 /* clear stream status */
727 for (i
= 0; i
< chip
->num_streams
; i
++) {
728 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
729 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
733 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
735 /* clear rirb status */
736 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
738 /* clear int status */
739 azx_writel(chip
, INTSTS
, ICH6_INT_CTRL_EN
| ICH6_INT_ALL_STREAM
);
743 static void azx_stream_start(struct azx
*chip
, struct azx_dev
*azx_dev
)
746 azx_writeb(chip
, INTCTL
,
747 azx_readb(chip
, INTCTL
) | (1 << azx_dev
->index
));
748 /* set DMA start and interrupt mask */
749 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
750 SD_CTL_DMA_START
| SD_INT_MASK
);
754 static void azx_stream_stop(struct azx
*chip
, struct azx_dev
*azx_dev
)
757 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) &
758 ~(SD_CTL_DMA_START
| SD_INT_MASK
));
759 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
); /* to be sure */
761 azx_writeb(chip
, INTCTL
,
762 azx_readb(chip
, INTCTL
) & ~(1 << azx_dev
->index
));
767 * initialize the chip
769 static void azx_init_chip(struct azx
*chip
)
773 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
774 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
775 * Ensuring these bits are 0 clears playback static on some HD Audio codecs
777 pci_read_config_byte (chip
->pci
, ICH6_PCIREG_TCSEL
, ®
);
778 pci_write_config_byte(chip
->pci
, ICH6_PCIREG_TCSEL
, reg
& 0xf8);
780 /* reset controller */
783 /* initialize interrupts */
785 azx_int_enable(chip
);
787 /* initialize the codec command I/O */
788 if (!chip
->single_cmd
)
789 azx_init_cmd_io(chip
);
791 /* program the position buffer */
792 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
);
793 azx_writel(chip
, DPUBASE
, upper_32bit(chip
->posbuf
.addr
));
795 switch (chip
->driver_type
) {
797 /* For ATI SB450 azalia HD audio, we need to enable snoop */
798 pci_read_config_byte(chip
->pci
, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
,
800 pci_write_config_byte(chip
->pci
, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
,
801 (reg
& 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP
);
803 case AZX_DRIVER_NVIDIA
:
804 /* For NVIDIA HDA, enable snoop */
805 pci_read_config_byte(chip
->pci
,NVIDIA_HDA_TRANSREG_ADDR
, ®
);
806 pci_write_config_byte(chip
->pci
,NVIDIA_HDA_TRANSREG_ADDR
,
807 (reg
& 0xf0) | NVIDIA_HDA_ENABLE_COHBITS
);
816 static irqreturn_t
azx_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
818 struct azx
*chip
= dev_id
;
819 struct azx_dev
*azx_dev
;
823 spin_lock(&chip
->reg_lock
);
825 status
= azx_readl(chip
, INTSTS
);
827 spin_unlock(&chip
->reg_lock
);
831 for (i
= 0; i
< chip
->num_streams
; i
++) {
832 azx_dev
= &chip
->azx_dev
[i
];
833 if (status
& azx_dev
->sd_int_sta_mask
) {
834 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
835 if (azx_dev
->substream
&& azx_dev
->running
) {
836 azx_dev
->period_intr
++;
837 spin_unlock(&chip
->reg_lock
);
838 snd_pcm_period_elapsed(azx_dev
->substream
);
839 spin_lock(&chip
->reg_lock
);
845 status
= azx_readb(chip
, RIRBSTS
);
846 if (status
& RIRB_INT_MASK
) {
847 if (! chip
->single_cmd
&& (status
& RIRB_INT_RESPONSE
))
848 azx_update_rirb(chip
);
849 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
853 /* clear state status int */
854 if (azx_readb(chip
, STATESTS
) & 0x04)
855 azx_writeb(chip
, STATESTS
, 0x04);
857 spin_unlock(&chip
->reg_lock
);
866 static void azx_setup_periods(struct azx_dev
*azx_dev
)
868 u32
*bdl
= azx_dev
->bdl
;
869 dma_addr_t dma_addr
= azx_dev
->substream
->runtime
->dma_addr
;
872 /* reset BDL address */
873 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
874 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
876 /* program the initial BDL entries */
877 for (idx
= 0; idx
< azx_dev
->frags
; idx
++) {
878 unsigned int off
= idx
<< 2; /* 4 dword step */
879 dma_addr_t addr
= dma_addr
+ idx
* azx_dev
->fragsize
;
880 /* program the address field of the BDL entry */
881 bdl
[off
] = cpu_to_le32((u32
)addr
);
882 bdl
[off
+1] = cpu_to_le32(upper_32bit(addr
));
884 /* program the size field of the BDL entry */
885 bdl
[off
+2] = cpu_to_le32(azx_dev
->fragsize
);
887 /* program the IOC to enable interrupt when buffer completes */
888 bdl
[off
+3] = cpu_to_le32(0x01);
893 * set up the SD for streaming
895 static int azx_setup_controller(struct azx
*chip
, struct azx_dev
*azx_dev
)
900 /* make sure the run bit is zero for SD */
901 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_CTL_DMA_START
);
903 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) | SD_CTL_STREAM_RESET
);
906 while (!((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
909 val
&= ~SD_CTL_STREAM_RESET
;
910 azx_sd_writeb(azx_dev
, SD_CTL
, val
);
914 /* waiting for hardware to report that the stream is out of reset */
915 while (((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
919 /* program the stream_tag */
920 azx_sd_writel(azx_dev
, SD_CTL
,
921 (azx_sd_readl(azx_dev
, SD_CTL
) & ~SD_CTL_STREAM_TAG_MASK
) |
922 (azx_dev
->stream_tag
<< SD_CTL_STREAM_TAG_SHIFT
));
924 /* program the length of samples in cyclic buffer */
925 azx_sd_writel(azx_dev
, SD_CBL
, azx_dev
->bufsize
);
927 /* program the stream format */
928 /* this value needs to be the same as the one programmed */
929 azx_sd_writew(azx_dev
, SD_FORMAT
, azx_dev
->format_val
);
931 /* program the stream LVI (last valid index) of the BDL */
932 azx_sd_writew(azx_dev
, SD_LVI
, azx_dev
->frags
- 1);
934 /* program the BDL address */
935 /* lower BDL address */
936 azx_sd_writel(azx_dev
, SD_BDLPL
, (u32
)azx_dev
->bdl_addr
);
937 /* upper BDL address */
938 azx_sd_writel(azx_dev
, SD_BDLPU
, upper_32bit(azx_dev
->bdl_addr
));
940 /* enable the position buffer */
941 if (! (azx_readl(chip
, DPLBASE
) & ICH6_DPLBASE_ENABLE
))
942 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
| ICH6_DPLBASE_ENABLE
);
944 /* set the interrupt enable bits in the descriptor control register */
945 azx_sd_writel(azx_dev
, SD_CTL
, azx_sd_readl(azx_dev
, SD_CTL
) | SD_INT_MASK
);
952 * Codec initialization
955 static int __devinit
azx_codec_create(struct azx
*chip
, const char *model
)
957 struct hda_bus_template bus_temp
;
960 memset(&bus_temp
, 0, sizeof(bus_temp
));
961 bus_temp
.private_data
= chip
;
962 bus_temp
.modelname
= model
;
963 bus_temp
.pci
= chip
->pci
;
964 bus_temp
.ops
.command
= azx_send_cmd
;
965 bus_temp
.ops
.get_response
= azx_get_response
;
967 if ((err
= snd_hda_bus_new(chip
->card
, &bus_temp
, &chip
->bus
)) < 0)
971 for (c
= 0; c
< AZX_MAX_CODECS
; c
++) {
972 if ((chip
->codec_mask
& (1 << c
)) & probe_mask
) {
973 err
= snd_hda_codec_new(chip
->bus
, c
, NULL
);
980 snd_printk(KERN_ERR SFX
"no codecs initialized\n");
992 /* assign a stream for the PCM */
993 static inline struct azx_dev
*azx_assign_device(struct azx
*chip
, int stream
)
996 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
997 dev
= chip
->playback_index_offset
;
998 nums
= chip
->playback_streams
;
1000 dev
= chip
->capture_index_offset
;
1001 nums
= chip
->capture_streams
;
1003 for (i
= 0; i
< nums
; i
++, dev
++)
1004 if (! chip
->azx_dev
[dev
].opened
) {
1005 chip
->azx_dev
[dev
].opened
= 1;
1006 return &chip
->azx_dev
[dev
];
1011 /* release the assigned stream */
1012 static inline void azx_release_device(struct azx_dev
*azx_dev
)
1014 azx_dev
->opened
= 0;
1017 static struct snd_pcm_hardware azx_pcm_hw
= {
1018 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1019 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1020 SNDRV_PCM_INFO_MMAP_VALID
|
1021 /* No full-resume yet implemented */
1022 /* SNDRV_PCM_INFO_RESUME |*/
1023 SNDRV_PCM_INFO_PAUSE
),
1024 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1025 .rates
= SNDRV_PCM_RATE_48000
,
1030 .buffer_bytes_max
= AZX_MAX_BUF_SIZE
,
1031 .period_bytes_min
= 128,
1032 .period_bytes_max
= AZX_MAX_BUF_SIZE
/ 2,
1034 .periods_max
= AZX_MAX_FRAG
,
1040 struct hda_codec
*codec
;
1041 struct hda_pcm_stream
*hinfo
[2];
1044 static int azx_pcm_open(struct snd_pcm_substream
*substream
)
1046 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1047 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1048 struct azx
*chip
= apcm
->chip
;
1049 struct azx_dev
*azx_dev
;
1050 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1051 unsigned long flags
;
1054 mutex_lock(&chip
->open_mutex
);
1055 azx_dev
= azx_assign_device(chip
, substream
->stream
);
1056 if (azx_dev
== NULL
) {
1057 mutex_unlock(&chip
->open_mutex
);
1060 runtime
->hw
= azx_pcm_hw
;
1061 runtime
->hw
.channels_min
= hinfo
->channels_min
;
1062 runtime
->hw
.channels_max
= hinfo
->channels_max
;
1063 runtime
->hw
.formats
= hinfo
->formats
;
1064 runtime
->hw
.rates
= hinfo
->rates
;
1065 snd_pcm_limit_hw_rates(runtime
);
1066 snd_pcm_hw_constraint_integer(runtime
, SNDRV_PCM_HW_PARAM_PERIODS
);
1067 if ((err
= hinfo
->ops
.open(hinfo
, apcm
->codec
, substream
)) < 0) {
1068 azx_release_device(azx_dev
);
1069 mutex_unlock(&chip
->open_mutex
);
1072 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1073 azx_dev
->substream
= substream
;
1074 azx_dev
->running
= 0;
1075 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1077 runtime
->private_data
= azx_dev
;
1078 mutex_unlock(&chip
->open_mutex
);
1082 static int azx_pcm_close(struct snd_pcm_substream
*substream
)
1084 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1085 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1086 struct azx
*chip
= apcm
->chip
;
1087 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1088 unsigned long flags
;
1090 mutex_lock(&chip
->open_mutex
);
1091 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1092 azx_dev
->substream
= NULL
;
1093 azx_dev
->running
= 0;
1094 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1095 azx_release_device(azx_dev
);
1096 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1097 mutex_unlock(&chip
->open_mutex
);
1101 static int azx_pcm_hw_params(struct snd_pcm_substream
*substream
, struct snd_pcm_hw_params
*hw_params
)
1103 return snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
));
1106 static int azx_pcm_hw_free(struct snd_pcm_substream
*substream
)
1108 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1109 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1110 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1112 /* reset BDL address */
1113 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1114 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1115 azx_sd_writel(azx_dev
, SD_CTL
, 0);
1117 hinfo
->ops
.cleanup(hinfo
, apcm
->codec
, substream
);
1119 return snd_pcm_lib_free_pages(substream
);
1122 static int azx_pcm_prepare(struct snd_pcm_substream
*substream
)
1124 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1125 struct azx
*chip
= apcm
->chip
;
1126 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1127 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1128 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1130 azx_dev
->bufsize
= snd_pcm_lib_buffer_bytes(substream
);
1131 azx_dev
->fragsize
= snd_pcm_lib_period_bytes(substream
);
1132 azx_dev
->frags
= azx_dev
->bufsize
/ azx_dev
->fragsize
;
1133 azx_dev
->format_val
= snd_hda_calc_stream_format(runtime
->rate
,
1137 if (! azx_dev
->format_val
) {
1138 snd_printk(KERN_ERR SFX
"invalid format_val, rate=%d, ch=%d, format=%d\n",
1139 runtime
->rate
, runtime
->channels
, runtime
->format
);
1143 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1144 azx_dev
->bufsize
, azx_dev
->fragsize
, azx_dev
->format_val
);
1145 azx_setup_periods(azx_dev
);
1146 azx_setup_controller(chip
, azx_dev
);
1147 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1148 azx_dev
->fifo_size
= azx_sd_readw(azx_dev
, SD_FIFOSIZE
) + 1;
1150 azx_dev
->fifo_size
= 0;
1152 return hinfo
->ops
.prepare(hinfo
, apcm
->codec
, azx_dev
->stream_tag
,
1153 azx_dev
->format_val
, substream
);
1156 static int azx_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
)
1158 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1159 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1160 struct azx
*chip
= apcm
->chip
;
1163 spin_lock(&chip
->reg_lock
);
1165 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1166 case SNDRV_PCM_TRIGGER_RESUME
:
1167 case SNDRV_PCM_TRIGGER_START
:
1168 azx_stream_start(chip
, azx_dev
);
1169 azx_dev
->running
= 1;
1171 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1172 case SNDRV_PCM_TRIGGER_SUSPEND
:
1173 case SNDRV_PCM_TRIGGER_STOP
:
1174 azx_stream_stop(chip
, azx_dev
);
1175 azx_dev
->running
= 0;
1180 spin_unlock(&chip
->reg_lock
);
1181 if (cmd
== SNDRV_PCM_TRIGGER_PAUSE_PUSH
||
1182 cmd
== SNDRV_PCM_TRIGGER_SUSPEND
||
1183 cmd
== SNDRV_PCM_TRIGGER_STOP
) {
1185 while (azx_sd_readb(azx_dev
, SD_CTL
) & SD_CTL_DMA_START
&& --timeout
)
1191 static snd_pcm_uframes_t
azx_pcm_pointer(struct snd_pcm_substream
*substream
)
1193 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1194 struct azx
*chip
= apcm
->chip
;
1195 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1198 if (chip
->position_fix
== POS_FIX_POSBUF
||
1199 chip
->position_fix
== POS_FIX_AUTO
) {
1200 /* use the position buffer */
1201 pos
= le32_to_cpu(*azx_dev
->posbuf
);
1202 if (chip
->position_fix
== POS_FIX_AUTO
&&
1203 azx_dev
->period_intr
== 1 && ! pos
) {
1205 "hda-intel: Invalid position buffer, "
1206 "using LPIB read method instead.\n");
1207 chip
->position_fix
= POS_FIX_NONE
;
1213 pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1214 if (chip
->position_fix
== POS_FIX_FIFO
)
1215 pos
+= azx_dev
->fifo_size
;
1217 if (pos
>= azx_dev
->bufsize
)
1219 return bytes_to_frames(substream
->runtime
, pos
);
1222 static struct snd_pcm_ops azx_pcm_ops
= {
1223 .open
= azx_pcm_open
,
1224 .close
= azx_pcm_close
,
1225 .ioctl
= snd_pcm_lib_ioctl
,
1226 .hw_params
= azx_pcm_hw_params
,
1227 .hw_free
= azx_pcm_hw_free
,
1228 .prepare
= azx_pcm_prepare
,
1229 .trigger
= azx_pcm_trigger
,
1230 .pointer
= azx_pcm_pointer
,
1233 static void azx_pcm_free(struct snd_pcm
*pcm
)
1235 kfree(pcm
->private_data
);
1238 static int __devinit
create_codec_pcm(struct azx
*chip
, struct hda_codec
*codec
,
1239 struct hda_pcm
*cpcm
, int pcm_dev
)
1242 struct snd_pcm
*pcm
;
1243 struct azx_pcm
*apcm
;
1245 /* if no substreams are defined for both playback and capture,
1246 * it's just a placeholder. ignore it.
1248 if (!cpcm
->stream
[0].substreams
&& !cpcm
->stream
[1].substreams
)
1251 snd_assert(cpcm
->name
, return -EINVAL
);
1253 err
= snd_pcm_new(chip
->card
, cpcm
->name
, pcm_dev
,
1254 cpcm
->stream
[0].substreams
, cpcm
->stream
[1].substreams
,
1258 strcpy(pcm
->name
, cpcm
->name
);
1259 apcm
= kmalloc(sizeof(*apcm
), GFP_KERNEL
);
1263 apcm
->codec
= codec
;
1264 apcm
->hinfo
[0] = &cpcm
->stream
[0];
1265 apcm
->hinfo
[1] = &cpcm
->stream
[1];
1266 pcm
->private_data
= apcm
;
1267 pcm
->private_free
= azx_pcm_free
;
1268 if (cpcm
->stream
[0].substreams
)
1269 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &azx_pcm_ops
);
1270 if (cpcm
->stream
[1].substreams
)
1271 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &azx_pcm_ops
);
1272 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1273 snd_dma_pci_data(chip
->pci
),
1274 1024 * 64, 1024 * 128);
1275 chip
->pcm
[pcm_dev
] = pcm
;
1276 if (chip
->pcm_devs
< pcm_dev
+ 1)
1277 chip
->pcm_devs
= pcm_dev
+ 1;
1282 static int __devinit
azx_pcm_create(struct azx
*chip
)
1284 struct list_head
*p
;
1285 struct hda_codec
*codec
;
1289 if ((err
= snd_hda_build_pcms(chip
->bus
)) < 0)
1292 /* create audio PCMs */
1294 list_for_each(p
, &chip
->bus
->codec_list
) {
1295 codec
= list_entry(p
, struct hda_codec
, list
);
1296 for (c
= 0; c
< codec
->num_pcms
; c
++) {
1297 if (codec
->pcm_info
[c
].is_modem
)
1298 continue; /* create later */
1299 if (pcm_dev
>= AZX_MAX_AUDIO_PCMS
) {
1300 snd_printk(KERN_ERR SFX
"Too many audio PCMs\n");
1303 err
= create_codec_pcm(chip
, codec
, &codec
->pcm_info
[c
], pcm_dev
);
1310 /* create modem PCMs */
1311 pcm_dev
= AZX_MAX_AUDIO_PCMS
;
1312 list_for_each(p
, &chip
->bus
->codec_list
) {
1313 codec
= list_entry(p
, struct hda_codec
, list
);
1314 for (c
= 0; c
< codec
->num_pcms
; c
++) {
1315 if (! codec
->pcm_info
[c
].is_modem
)
1316 continue; /* already created */
1317 if (pcm_dev
>= AZX_MAX_PCMS
) {
1318 snd_printk(KERN_ERR SFX
"Too many modem PCMs\n");
1321 err
= create_codec_pcm(chip
, codec
, &codec
->pcm_info
[c
], pcm_dev
);
1324 chip
->pcm
[pcm_dev
]->dev_class
= SNDRV_PCM_CLASS_MODEM
;
1332 * mixer creation - all stuff is implemented in hda module
1334 static int __devinit
azx_mixer_create(struct azx
*chip
)
1336 return snd_hda_build_controls(chip
->bus
);
1341 * initialize SD streams
1343 static int __devinit
azx_init_stream(struct azx
*chip
)
1347 /* initialize each stream (aka device)
1348 * assign the starting bdl address to each stream (device) and initialize
1350 for (i
= 0; i
< chip
->num_streams
; i
++) {
1351 unsigned int off
= sizeof(u32
) * (i
* AZX_MAX_FRAG
* 4);
1352 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
1353 azx_dev
->bdl
= (u32
*)(chip
->bdl
.area
+ off
);
1354 azx_dev
->bdl_addr
= chip
->bdl
.addr
+ off
;
1355 azx_dev
->posbuf
= (u32 __iomem
*)(chip
->posbuf
.area
+ i
* 8);
1356 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1357 azx_dev
->sd_addr
= chip
->remap_addr
+ (0x20 * i
+ 0x80);
1358 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1359 azx_dev
->sd_int_sta_mask
= 1 << i
;
1360 /* stream tag: must be non-zero and unique */
1362 azx_dev
->stream_tag
= i
+ 1;
1373 static int azx_suspend(struct pci_dev
*pci
, pm_message_t state
)
1375 struct snd_card
*card
= pci_get_drvdata(pci
);
1376 struct azx
*chip
= card
->private_data
;
1379 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
1380 for (i
= 0; i
< chip
->pcm_devs
; i
++)
1381 snd_pcm_suspend_all(chip
->pcm
[i
]);
1382 snd_hda_suspend(chip
->bus
, state
);
1383 azx_free_cmd_io(chip
);
1385 free_irq(chip
->irq
, chip
);
1387 pci_disable_msi(chip
->pci
);
1388 pci_disable_device(pci
);
1389 pci_save_state(pci
);
1393 static int azx_resume(struct pci_dev
*pci
)
1395 struct snd_card
*card
= pci_get_drvdata(pci
);
1396 struct azx
*chip
= card
->private_data
;
1398 pci_restore_state(pci
);
1399 pci_enable_device(pci
);
1401 pci_enable_msi(pci
);
1402 /* FIXME: need proper error handling */
1403 request_irq(pci
->irq
, azx_interrupt
, IRQF_DISABLED
|IRQF_SHARED
,
1405 chip
->irq
= pci
->irq
;
1406 pci_set_master(pci
);
1407 azx_init_chip(chip
);
1408 snd_hda_resume(chip
->bus
);
1409 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
1412 #endif /* CONFIG_PM */
1418 static int azx_free(struct azx
*chip
)
1420 if (chip
->initialized
) {
1423 for (i
= 0; i
< chip
->num_streams
; i
++)
1424 azx_stream_stop(chip
, &chip
->azx_dev
[i
]);
1426 /* disable interrupts */
1427 azx_int_disable(chip
);
1428 azx_int_clear(chip
);
1430 /* disable CORB/RIRB */
1431 azx_free_cmd_io(chip
);
1433 /* disable position buffer */
1434 azx_writel(chip
, DPLBASE
, 0);
1435 azx_writel(chip
, DPUBASE
, 0);
1437 synchronize_irq(chip
->irq
);
1440 if (chip
->irq
>= 0) {
1441 free_irq(chip
->irq
, (void*)chip
);
1443 pci_disable_msi(chip
->pci
);
1445 if (chip
->remap_addr
)
1446 iounmap(chip
->remap_addr
);
1449 snd_dma_free_pages(&chip
->bdl
);
1451 snd_dma_free_pages(&chip
->rb
);
1452 if (chip
->posbuf
.area
)
1453 snd_dma_free_pages(&chip
->posbuf
);
1454 pci_release_regions(chip
->pci
);
1455 pci_disable_device(chip
->pci
);
1456 kfree(chip
->azx_dev
);
1462 static int azx_dev_free(struct snd_device
*device
)
1464 return azx_free(device
->device_data
);
1470 static int __devinit
azx_create(struct snd_card
*card
, struct pci_dev
*pci
,
1476 static struct snd_device_ops ops
= {
1477 .dev_free
= azx_dev_free
,
1482 err
= pci_enable_device(pci
);
1486 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
1488 snd_printk(KERN_ERR SFX
"cannot allocate chip\n");
1489 pci_disable_device(pci
);
1493 spin_lock_init(&chip
->reg_lock
);
1494 mutex_init(&chip
->open_mutex
);
1498 chip
->driver_type
= driver_type
;
1500 chip
->position_fix
= position_fix
;
1501 chip
->single_cmd
= single_cmd
;
1503 #if BITS_PER_LONG != 64
1504 /* Fix up base address on ULI M5461 */
1505 if (chip
->driver_type
== AZX_DRIVER_ULI
) {
1507 pci_read_config_word(pci
, 0x40, &tmp3
);
1508 pci_write_config_word(pci
, 0x40, tmp3
| 0x10);
1509 pci_write_config_dword(pci
, PCI_BASE_ADDRESS_1
, 0);
1513 err
= pci_request_regions(pci
, "ICH HD audio");
1516 pci_disable_device(pci
);
1520 chip
->addr
= pci_resource_start(pci
, 0);
1521 chip
->remap_addr
= ioremap_nocache(chip
->addr
, pci_resource_len(pci
,0));
1522 if (chip
->remap_addr
== NULL
) {
1523 snd_printk(KERN_ERR SFX
"ioremap error\n");
1529 pci_enable_msi(pci
);
1531 if (request_irq(pci
->irq
, azx_interrupt
, IRQF_DISABLED
|IRQF_SHARED
,
1532 "HDA Intel", (void*)chip
)) {
1533 snd_printk(KERN_ERR SFX
"unable to grab IRQ %d\n", pci
->irq
);
1537 chip
->irq
= pci
->irq
;
1539 pci_set_master(pci
);
1540 synchronize_irq(chip
->irq
);
1542 switch (chip
->driver_type
) {
1543 case AZX_DRIVER_ULI
:
1544 chip
->playback_streams
= ULI_NUM_PLAYBACK
;
1545 chip
->capture_streams
= ULI_NUM_CAPTURE
;
1546 chip
->playback_index_offset
= ULI_PLAYBACK_INDEX
;
1547 chip
->capture_index_offset
= ULI_CAPTURE_INDEX
;
1549 case AZX_DRIVER_ATIHDMI
:
1550 chip
->playback_streams
= ATIHDMI_NUM_PLAYBACK
;
1551 chip
->capture_streams
= ATIHDMI_NUM_CAPTURE
;
1552 chip
->playback_index_offset
= ATIHDMI_PLAYBACK_INDEX
;
1553 chip
->capture_index_offset
= ATIHDMI_CAPTURE_INDEX
;
1556 chip
->playback_streams
= ICH6_NUM_PLAYBACK
;
1557 chip
->capture_streams
= ICH6_NUM_CAPTURE
;
1558 chip
->playback_index_offset
= ICH6_PLAYBACK_INDEX
;
1559 chip
->capture_index_offset
= ICH6_CAPTURE_INDEX
;
1562 chip
->num_streams
= chip
->playback_streams
+ chip
->capture_streams
;
1563 chip
->azx_dev
= kcalloc(chip
->num_streams
, sizeof(*chip
->azx_dev
), GFP_KERNEL
);
1564 if (!chip
->azx_dev
) {
1565 snd_printk(KERN_ERR
"cannot malloc azx_dev\n");
1569 /* allocate memory for the BDL for each stream */
1570 if ((err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1571 BDL_SIZE
, &chip
->bdl
)) < 0) {
1572 snd_printk(KERN_ERR SFX
"cannot allocate BDL\n");
1575 /* allocate memory for the position buffer */
1576 if ((err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(chip
->pci
),
1577 chip
->num_streams
* 8, &chip
->posbuf
)) < 0) {
1578 snd_printk(KERN_ERR SFX
"cannot allocate posbuf\n");
1581 /* allocate CORB/RIRB */
1582 if (! chip
->single_cmd
)
1583 if ((err
= azx_alloc_cmd_io(chip
)) < 0)
1586 /* initialize streams */
1587 azx_init_stream(chip
);
1589 /* initialize chip */
1590 azx_init_chip(chip
);
1592 chip
->initialized
= 1;
1594 /* codec detection */
1595 if (!chip
->codec_mask
) {
1596 snd_printk(KERN_ERR SFX
"no codecs found!\n");
1601 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
)) <0) {
1602 snd_printk(KERN_ERR SFX
"Error creating device [card]!\n");
1606 strcpy(card
->driver
, "HDA-Intel");
1607 strcpy(card
->shortname
, driver_short_names
[chip
->driver_type
]);
1608 sprintf(card
->longname
, "%s at 0x%lx irq %i", card
->shortname
, chip
->addr
, chip
->irq
);
1618 static int __devinit
azx_probe(struct pci_dev
*pci
, const struct pci_device_id
*pci_id
)
1620 struct snd_card
*card
;
1624 card
= snd_card_new(index
, id
, THIS_MODULE
, 0);
1626 snd_printk(KERN_ERR SFX
"Error creating card!\n");
1630 err
= azx_create(card
, pci
, pci_id
->driver_data
, &chip
);
1632 snd_card_free(card
);
1635 card
->private_data
= chip
;
1637 /* create codec instances */
1638 if ((err
= azx_codec_create(chip
, model
)) < 0) {
1639 snd_card_free(card
);
1643 /* create PCM streams */
1644 if ((err
= azx_pcm_create(chip
)) < 0) {
1645 snd_card_free(card
);
1649 /* create mixer controls */
1650 if ((err
= azx_mixer_create(chip
)) < 0) {
1651 snd_card_free(card
);
1655 snd_card_set_dev(card
, &pci
->dev
);
1657 if ((err
= snd_card_register(card
)) < 0) {
1658 snd_card_free(card
);
1662 pci_set_drvdata(pci
, card
);
1667 static void __devexit
azx_remove(struct pci_dev
*pci
)
1669 snd_card_free(pci_get_drvdata(pci
));
1670 pci_set_drvdata(pci
, NULL
);
1674 static struct pci_device_id azx_ids
[] = {
1675 { 0x8086, 0x2668, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH6 */
1676 { 0x8086, 0x27d8, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH7 */
1677 { 0x8086, 0x269a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ESB2 */
1678 { 0x8086, 0x284b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ICH
}, /* ICH8 */
1679 { 0x1002, 0x437b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATI
}, /* ATI SB450 */
1680 { 0x1002, 0x4383, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATI
}, /* ATI SB600 */
1681 { 0x1002, 0x793b, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ATIHDMI
}, /* ATI RS600 HDMI */
1682 { 0x1106, 0x3288, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_VIA
}, /* VIA VT8251/VT8237A */
1683 { 0x1039, 0x7502, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_SIS
}, /* SIS966 */
1684 { 0x10b9, 0x5461, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_ULI
}, /* ULI M5461 */
1685 { 0x10de, 0x026c, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA 026c */
1686 { 0x10de, 0x0371, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, AZX_DRIVER_NVIDIA
}, /* NVIDIA 0371 */
1689 MODULE_DEVICE_TABLE(pci
, azx_ids
);
1691 /* pci_driver definition */
1692 static struct pci_driver driver
= {
1693 .name
= "HDA Intel",
1694 .id_table
= azx_ids
,
1696 .remove
= __devexit_p(azx_remove
),
1698 .suspend
= azx_suspend
,
1699 .resume
= azx_resume
,
1703 static int __init
alsa_card_azx_init(void)
1705 return pci_register_driver(&driver
);
1708 static void __exit
alsa_card_azx_exit(void)
1710 pci_unregister_driver(&driver
);
1713 module_init(alsa_card_azx_init
)
1714 module_exit(alsa_card_azx_exit
)