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[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65 #include "hda_i915.h"
66 #include "hda_controller.h"
67 #include "hda_priv.h"
68
69
70 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
71 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
72 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
73 static char *model[SNDRV_CARDS];
74 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
75 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
76 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
77 static int probe_only[SNDRV_CARDS];
78 static int jackpoll_ms[SNDRV_CARDS];
79 static bool single_cmd;
80 static int enable_msi = -1;
81 #ifdef CONFIG_SND_HDA_PATCH_LOADER
82 static char *patch[SNDRV_CARDS];
83 #endif
84 #ifdef CONFIG_SND_HDA_INPUT_BEEP
85 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
86 CONFIG_SND_HDA_INPUT_BEEP_MODE};
87 #endif
88
89 module_param_array(index, int, NULL, 0444);
90 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
91 module_param_array(id, charp, NULL, 0444);
92 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
93 module_param_array(enable, bool, NULL, 0444);
94 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
95 module_param_array(model, charp, NULL, 0444);
96 MODULE_PARM_DESC(model, "Use the given board model.");
97 module_param_array(position_fix, int, NULL, 0444);
98 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
99 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
100 module_param_array(bdl_pos_adj, int, NULL, 0644);
101 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
102 module_param_array(probe_mask, int, NULL, 0444);
103 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
104 module_param_array(probe_only, int, NULL, 0444);
105 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
106 module_param_array(jackpoll_ms, int, NULL, 0444);
107 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
108 module_param(single_cmd, bool, 0444);
109 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
110 "(for debugging only).");
111 module_param(enable_msi, bint, 0444);
112 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
113 #ifdef CONFIG_SND_HDA_PATCH_LOADER
114 module_param_array(patch, charp, NULL, 0444);
115 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
116 #endif
117 #ifdef CONFIG_SND_HDA_INPUT_BEEP
118 module_param_array(beep_mode, bool, NULL, 0444);
119 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
120 "(0=off, 1=on) (default=1).");
121 #endif
122
123 #ifdef CONFIG_PM
124 static int param_set_xint(const char *val, const struct kernel_param *kp);
125 static struct kernel_param_ops param_ops_xint = {
126 .set = param_set_xint,
127 .get = param_get_int,
128 };
129 #define param_check_xint param_check_int
130
131 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
132 static int *power_save_addr = &power_save;
133 module_param(power_save, xint, 0644);
134 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
135 "(in second, 0 = disable).");
136
137 /* reset the HD-audio controller in power save mode.
138 * this may give more power-saving, but will take longer time to
139 * wake up.
140 */
141 static bool power_save_controller = 1;
142 module_param(power_save_controller, bool, 0644);
143 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
144 #else
145 static int *power_save_addr;
146 #endif /* CONFIG_PM */
147
148 static int align_buffer_size = -1;
149 module_param(align_buffer_size, bint, 0644);
150 MODULE_PARM_DESC(align_buffer_size,
151 "Force buffer and period sizes to be multiple of 128 bytes.");
152
153 #ifdef CONFIG_X86
154 static bool hda_snoop = true;
155 module_param_named(snoop, hda_snoop, bool, 0444);
156 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
157 #else
158 #define hda_snoop true
159 #endif
160
161
162 MODULE_LICENSE("GPL");
163 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
164 "{Intel, ICH6M},"
165 "{Intel, ICH7},"
166 "{Intel, ESB2},"
167 "{Intel, ICH8},"
168 "{Intel, ICH9},"
169 "{Intel, ICH10},"
170 "{Intel, PCH},"
171 "{Intel, CPT},"
172 "{Intel, PPT},"
173 "{Intel, LPT},"
174 "{Intel, LPT_LP},"
175 "{Intel, WPT_LP},"
176 "{Intel, HPT},"
177 "{Intel, PBG},"
178 "{Intel, SCH},"
179 "{ATI, SB450},"
180 "{ATI, SB600},"
181 "{ATI, RS600},"
182 "{ATI, RS690},"
183 "{ATI, RS780},"
184 "{ATI, R600},"
185 "{ATI, RV630},"
186 "{ATI, RV610},"
187 "{ATI, RV670},"
188 "{ATI, RV635},"
189 "{ATI, RV620},"
190 "{ATI, RV770},"
191 "{VIA, VT8251},"
192 "{VIA, VT8237A},"
193 "{SiS, SIS966},"
194 "{ULI, M5461}}");
195 MODULE_DESCRIPTION("Intel HDA driver");
196
197 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
198 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
199 #define SUPPORT_VGA_SWITCHEROO
200 #endif
201 #endif
202
203
204 /*
205 */
206
207 /* driver types */
208 enum {
209 AZX_DRIVER_ICH,
210 AZX_DRIVER_PCH,
211 AZX_DRIVER_SCH,
212 AZX_DRIVER_HDMI,
213 AZX_DRIVER_ATI,
214 AZX_DRIVER_ATIHDMI,
215 AZX_DRIVER_ATIHDMI_NS,
216 AZX_DRIVER_VIA,
217 AZX_DRIVER_SIS,
218 AZX_DRIVER_ULI,
219 AZX_DRIVER_NVIDIA,
220 AZX_DRIVER_TERA,
221 AZX_DRIVER_CTX,
222 AZX_DRIVER_CTHDA,
223 AZX_DRIVER_GENERIC,
224 AZX_NUM_DRIVERS, /* keep this as last entry */
225 };
226
227 /* quirks for Intel PCH */
228 #define AZX_DCAPS_INTEL_PCH_NOPM \
229 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
230 AZX_DCAPS_COUNT_LPIB_DELAY)
231
232 #define AZX_DCAPS_INTEL_PCH \
233 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
234
235 #define AZX_DCAPS_INTEL_HASWELL \
236 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
237 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
238 AZX_DCAPS_I915_POWERWELL)
239
240 /* quirks for ATI SB / AMD Hudson */
241 #define AZX_DCAPS_PRESET_ATI_SB \
242 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
243 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
244
245 /* quirks for ATI/AMD HDMI */
246 #define AZX_DCAPS_PRESET_ATI_HDMI \
247 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
248
249 /* quirks for Nvidia */
250 #define AZX_DCAPS_PRESET_NVIDIA \
251 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
252 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
253
254 #define AZX_DCAPS_PRESET_CTHDA \
255 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
256
257 /*
258 * VGA-switcher support
259 */
260 #ifdef SUPPORT_VGA_SWITCHEROO
261 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
262 #else
263 #define use_vga_switcheroo(chip) 0
264 #endif
265
266 static char *driver_short_names[] = {
267 [AZX_DRIVER_ICH] = "HDA Intel",
268 [AZX_DRIVER_PCH] = "HDA Intel PCH",
269 [AZX_DRIVER_SCH] = "HDA Intel MID",
270 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
271 [AZX_DRIVER_ATI] = "HDA ATI SB",
272 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
273 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
274 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
275 [AZX_DRIVER_SIS] = "HDA SIS966",
276 [AZX_DRIVER_ULI] = "HDA ULI M5461",
277 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
278 [AZX_DRIVER_TERA] = "HDA Teradici",
279 [AZX_DRIVER_CTX] = "HDA Creative",
280 [AZX_DRIVER_CTHDA] = "HDA Creative",
281 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
282 };
283
284 #ifdef CONFIG_X86
285 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
286 {
287 int pages;
288
289 if (azx_snoop(chip))
290 return;
291 if (!dmab || !dmab->area || !dmab->bytes)
292 return;
293
294 #ifdef CONFIG_SND_DMA_SGBUF
295 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
296 struct snd_sg_buf *sgbuf = dmab->private_data;
297 if (on)
298 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
299 else
300 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
301 return;
302 }
303 #endif
304
305 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
306 if (on)
307 set_memory_wc((unsigned long)dmab->area, pages);
308 else
309 set_memory_wb((unsigned long)dmab->area, pages);
310 }
311
312 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
313 bool on)
314 {
315 __mark_pages_wc(chip, buf, on);
316 }
317 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
318 struct snd_pcm_substream *substream, bool on)
319 {
320 if (azx_dev->wc_marked != on) {
321 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
322 azx_dev->wc_marked = on;
323 }
324 }
325 #else
326 /* NOP for other archs */
327 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
328 bool on)
329 {
330 }
331 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
332 struct snd_pcm_substream *substream, bool on)
333 {
334 }
335 #endif
336
337 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
338
339 #ifdef CONFIG_PM
340 static void azx_power_notify(struct hda_bus *bus, bool power_up);
341 #endif
342
343 /*
344 * initialize the PCI registers
345 */
346 /* update bits in a PCI register byte */
347 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
348 unsigned char mask, unsigned char val)
349 {
350 unsigned char data;
351
352 pci_read_config_byte(pci, reg, &data);
353 data &= ~mask;
354 data |= (val & mask);
355 pci_write_config_byte(pci, reg, data);
356 }
357
358 static void azx_init_pci(struct azx *chip)
359 {
360 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
361 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
362 * Ensuring these bits are 0 clears playback static on some HD Audio
363 * codecs.
364 * The PCI register TCSEL is defined in the Intel manuals.
365 */
366 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
367 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
368 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
369 }
370
371 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
372 * we need to enable snoop.
373 */
374 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
375 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
376 azx_snoop(chip));
377 update_pci_byte(chip->pci,
378 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
379 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
380 }
381
382 /* For NVIDIA HDA, enable snoop */
383 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
384 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
385 azx_snoop(chip));
386 update_pci_byte(chip->pci,
387 NVIDIA_HDA_TRANSREG_ADDR,
388 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
389 update_pci_byte(chip->pci,
390 NVIDIA_HDA_ISTRM_COH,
391 0x01, NVIDIA_HDA_ENABLE_COHBIT);
392 update_pci_byte(chip->pci,
393 NVIDIA_HDA_OSTRM_COH,
394 0x01, NVIDIA_HDA_ENABLE_COHBIT);
395 }
396
397 /* Enable SCH/PCH snoop if needed */
398 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
399 unsigned short snoop;
400 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
401 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
402 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
403 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
404 if (!azx_snoop(chip))
405 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
406 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
407 pci_read_config_word(chip->pci,
408 INTEL_SCH_HDA_DEVC, &snoop);
409 }
410 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
411 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
412 "Disabled" : "Enabled");
413 }
414 }
415
416
417 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
418
419 /* called from IRQ */
420 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
421 {
422 int ok;
423
424 ok = azx_position_ok(chip, azx_dev);
425 if (ok == 1) {
426 azx_dev->irq_pending = 0;
427 return ok;
428 } else if (ok == 0 && chip->bus && chip->bus->workq) {
429 /* bogus IRQ, process it later */
430 azx_dev->irq_pending = 1;
431 queue_work(chip->bus->workq, &chip->irq_pending_work);
432 }
433 return 0;
434 }
435
436 /*
437 * interrupt handler
438 */
439 static irqreturn_t azx_interrupt(int irq, void *dev_id)
440 {
441 struct azx *chip = dev_id;
442 struct azx_dev *azx_dev;
443 u32 status;
444 u8 sd_status;
445 int i;
446
447 #ifdef CONFIG_PM_RUNTIME
448 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
449 if (chip->card->dev->power.runtime_status != RPM_ACTIVE)
450 return IRQ_NONE;
451 #endif
452
453 spin_lock(&chip->reg_lock);
454
455 if (chip->disabled) {
456 spin_unlock(&chip->reg_lock);
457 return IRQ_NONE;
458 }
459
460 status = azx_readl(chip, INTSTS);
461 if (status == 0 || status == 0xffffffff) {
462 spin_unlock(&chip->reg_lock);
463 return IRQ_NONE;
464 }
465
466 for (i = 0; i < chip->num_streams; i++) {
467 azx_dev = &chip->azx_dev[i];
468 if (status & azx_dev->sd_int_sta_mask) {
469 sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
470 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
471 if (!azx_dev->substream || !azx_dev->running ||
472 !(sd_status & SD_INT_COMPLETE))
473 continue;
474 /* check whether this IRQ is really acceptable */
475 if (!chip->ops->position_check ||
476 chip->ops->position_check(chip, azx_dev)) {
477 spin_unlock(&chip->reg_lock);
478 snd_pcm_period_elapsed(azx_dev->substream);
479 spin_lock(&chip->reg_lock);
480 }
481 }
482 }
483
484 /* clear rirb int */
485 status = azx_readb(chip, RIRBSTS);
486 if (status & RIRB_INT_MASK) {
487 if (status & RIRB_INT_RESPONSE) {
488 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
489 udelay(80);
490 azx_update_rirb(chip);
491 }
492 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
493 }
494
495 spin_unlock(&chip->reg_lock);
496
497 return IRQ_HANDLED;
498 }
499
500 /*
501 * Probe the given codec address
502 */
503 static int probe_codec(struct azx *chip, int addr)
504 {
505 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
506 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
507 unsigned int res;
508
509 mutex_lock(&chip->bus->cmd_mutex);
510 chip->probing = 1;
511 azx_send_cmd(chip->bus, cmd);
512 res = azx_get_response(chip->bus, addr);
513 chip->probing = 0;
514 mutex_unlock(&chip->bus->cmd_mutex);
515 if (res == -1)
516 return -EIO;
517 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
518 return 0;
519 }
520
521 static void azx_bus_reset(struct hda_bus *bus)
522 {
523 struct azx *chip = bus->private_data;
524
525 bus->in_reset = 1;
526 azx_stop_chip(chip);
527 azx_init_chip(chip, 1);
528 #ifdef CONFIG_PM
529 if (chip->initialized) {
530 struct azx_pcm *p;
531 list_for_each_entry(p, &chip->pcm_list, list)
532 snd_pcm_suspend_all(p->pcm);
533 snd_hda_suspend(chip->bus);
534 snd_hda_resume(chip->bus);
535 }
536 #endif
537 bus->in_reset = 0;
538 }
539
540 static int get_jackpoll_interval(struct azx *chip)
541 {
542 int i;
543 unsigned int j;
544
545 if (!chip->jackpoll_ms)
546 return 0;
547
548 i = chip->jackpoll_ms[chip->dev_index];
549 if (i == 0)
550 return 0;
551 if (i < 50 || i > 60000)
552 j = 0;
553 else
554 j = msecs_to_jiffies(i);
555 if (j == 0)
556 dev_warn(chip->card->dev,
557 "jackpoll_ms value out of range: %d\n", i);
558 return j;
559 }
560
561 /*
562 * Codec initialization
563 */
564
565 static int azx_codec_create(struct azx *chip, const char *model,
566 unsigned int max_slots,
567 int *power_save_to)
568 {
569 struct hda_bus_template bus_temp;
570 int c, codecs, err;
571
572 memset(&bus_temp, 0, sizeof(bus_temp));
573 bus_temp.private_data = chip;
574 bus_temp.modelname = model;
575 bus_temp.pci = chip->pci;
576 bus_temp.ops.command = azx_send_cmd;
577 bus_temp.ops.get_response = azx_get_response;
578 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
579 bus_temp.ops.bus_reset = azx_bus_reset;
580 #ifdef CONFIG_PM
581 bus_temp.power_save = power_save_to;
582 bus_temp.ops.pm_notify = azx_power_notify;
583 #endif
584 #ifdef CONFIG_SND_HDA_DSP_LOADER
585 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
586 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
587 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
588 #endif
589
590 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
591 if (err < 0)
592 return err;
593
594 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
595 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
596 chip->bus->needs_damn_long_delay = 1;
597 }
598
599 codecs = 0;
600 if (!max_slots)
601 max_slots = AZX_DEFAULT_CODECS;
602
603 /* First try to probe all given codec slots */
604 for (c = 0; c < max_slots; c++) {
605 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
606 if (probe_codec(chip, c) < 0) {
607 /* Some BIOSen give you wrong codec addresses
608 * that don't exist
609 */
610 dev_warn(chip->card->dev,
611 "Codec #%d probe error; disabling it...\n", c);
612 chip->codec_mask &= ~(1 << c);
613 /* More badly, accessing to a non-existing
614 * codec often screws up the controller chip,
615 * and disturbs the further communications.
616 * Thus if an error occurs during probing,
617 * better to reset the controller chip to
618 * get back to the sanity state.
619 */
620 azx_stop_chip(chip);
621 azx_init_chip(chip, 1);
622 }
623 }
624 }
625
626 /* AMD chipsets often cause the communication stalls upon certain
627 * sequence like the pin-detection. It seems that forcing the synced
628 * access works around the stall. Grrr...
629 */
630 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
631 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
632 chip->bus->sync_write = 1;
633 chip->bus->allow_bus_reset = 1;
634 }
635
636 /* Then create codec instances */
637 for (c = 0; c < max_slots; c++) {
638 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
639 struct hda_codec *codec;
640 err = snd_hda_codec_new(chip->bus, c, &codec);
641 if (err < 0)
642 continue;
643 codec->jackpoll_interval = get_jackpoll_interval(chip);
644 codec->beep_mode = chip->beep_mode;
645 codecs++;
646 }
647 }
648 if (!codecs) {
649 dev_err(chip->card->dev, "no codecs initialized\n");
650 return -ENXIO;
651 }
652 return 0;
653 }
654
655 /* configure each codec instance */
656 static int azx_codec_configure(struct azx *chip)
657 {
658 struct hda_codec *codec;
659 list_for_each_entry(codec, &chip->bus->codec_list, list) {
660 snd_hda_codec_configure(codec);
661 }
662 return 0;
663 }
664
665 /*
666 * Check whether the current DMA position is acceptable for updating
667 * periods. Returns non-zero if it's OK.
668 *
669 * Many HD-audio controllers appear pretty inaccurate about
670 * the update-IRQ timing. The IRQ is issued before actually the
671 * data is processed. So, we need to process it afterwords in a
672 * workqueue.
673 */
674 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
675 {
676 u32 wallclk;
677 unsigned int pos;
678
679 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
680 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
681 return -1; /* bogus (too early) interrupt */
682
683 pos = azx_get_position(chip, azx_dev, true);
684
685 if (WARN_ONCE(!azx_dev->period_bytes,
686 "hda-intel: zero azx_dev->period_bytes"))
687 return -1; /* this shouldn't happen! */
688 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
689 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
690 /* NG - it's below the first next period boundary */
691 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
692 azx_dev->start_wallclk += wallclk;
693 return 1; /* OK, it's fine */
694 }
695
696 /*
697 * The work for pending PCM period updates.
698 */
699 static void azx_irq_pending_work(struct work_struct *work)
700 {
701 struct azx *chip = container_of(work, struct azx, irq_pending_work);
702 int i, pending, ok;
703
704 if (!chip->irq_pending_warned) {
705 dev_info(chip->card->dev,
706 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
707 chip->card->number);
708 chip->irq_pending_warned = 1;
709 }
710
711 for (;;) {
712 pending = 0;
713 spin_lock_irq(&chip->reg_lock);
714 for (i = 0; i < chip->num_streams; i++) {
715 struct azx_dev *azx_dev = &chip->azx_dev[i];
716 if (!azx_dev->irq_pending ||
717 !azx_dev->substream ||
718 !azx_dev->running)
719 continue;
720 ok = azx_position_ok(chip, azx_dev);
721 if (ok > 0) {
722 azx_dev->irq_pending = 0;
723 spin_unlock(&chip->reg_lock);
724 snd_pcm_period_elapsed(azx_dev->substream);
725 spin_lock(&chip->reg_lock);
726 } else if (ok < 0) {
727 pending = 0; /* too early */
728 } else
729 pending++;
730 }
731 spin_unlock_irq(&chip->reg_lock);
732 if (!pending)
733 return;
734 msleep(1);
735 }
736 }
737
738 /* clear irq_pending flags and assure no on-going workq */
739 static void azx_clear_irq_pending(struct azx *chip)
740 {
741 int i;
742
743 spin_lock_irq(&chip->reg_lock);
744 for (i = 0; i < chip->num_streams; i++)
745 chip->azx_dev[i].irq_pending = 0;
746 spin_unlock_irq(&chip->reg_lock);
747 }
748
749 /*
750 * mixer creation - all stuff is implemented in hda module
751 */
752 static int azx_mixer_create(struct azx *chip)
753 {
754 return snd_hda_build_controls(chip->bus);
755 }
756
757
758 /*
759 * initialize SD streams
760 */
761 static int azx_init_stream(struct azx *chip)
762 {
763 int i;
764
765 /* initialize each stream (aka device)
766 * assign the starting bdl address to each stream (device)
767 * and initialize
768 */
769 for (i = 0; i < chip->num_streams; i++) {
770 struct azx_dev *azx_dev = &chip->azx_dev[i];
771 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
772 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
773 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
774 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
775 azx_dev->sd_int_sta_mask = 1 << i;
776 /* stream tag: must be non-zero and unique */
777 azx_dev->index = i;
778 azx_dev->stream_tag = i + 1;
779 }
780
781 return 0;
782 }
783
784 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
785 {
786 if (request_irq(chip->pci->irq, azx_interrupt,
787 chip->msi ? 0 : IRQF_SHARED,
788 KBUILD_MODNAME, chip)) {
789 dev_err(chip->card->dev,
790 "unable to grab IRQ %d, disabling device\n",
791 chip->pci->irq);
792 if (do_disconnect)
793 snd_card_disconnect(chip->card);
794 return -1;
795 }
796 chip->irq = chip->pci->irq;
797 pci_intx(chip->pci, !chip->msi);
798 return 0;
799 }
800
801 #ifdef CONFIG_PM
802 /* power-up/down the controller */
803 static void azx_power_notify(struct hda_bus *bus, bool power_up)
804 {
805 struct azx *chip = bus->private_data;
806
807 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
808 return;
809
810 if (power_up)
811 pm_runtime_get_sync(chip->card->dev);
812 else
813 pm_runtime_put_sync(chip->card->dev);
814 }
815
816 static DEFINE_MUTEX(card_list_lock);
817 static LIST_HEAD(card_list);
818
819 static void azx_add_card_list(struct azx *chip)
820 {
821 mutex_lock(&card_list_lock);
822 list_add(&chip->list, &card_list);
823 mutex_unlock(&card_list_lock);
824 }
825
826 static void azx_del_card_list(struct azx *chip)
827 {
828 mutex_lock(&card_list_lock);
829 list_del_init(&chip->list);
830 mutex_unlock(&card_list_lock);
831 }
832
833 /* trigger power-save check at writing parameter */
834 static int param_set_xint(const char *val, const struct kernel_param *kp)
835 {
836 struct azx *chip;
837 struct hda_codec *c;
838 int prev = power_save;
839 int ret = param_set_int(val, kp);
840
841 if (ret || prev == power_save)
842 return ret;
843
844 mutex_lock(&card_list_lock);
845 list_for_each_entry(chip, &card_list, list) {
846 if (!chip->bus || chip->disabled)
847 continue;
848 list_for_each_entry(c, &chip->bus->codec_list, list)
849 snd_hda_power_sync(c);
850 }
851 mutex_unlock(&card_list_lock);
852 return 0;
853 }
854 #else
855 #define azx_add_card_list(chip) /* NOP */
856 #define azx_del_card_list(chip) /* NOP */
857 #endif /* CONFIG_PM */
858
859 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
860 /*
861 * power management
862 */
863 static int azx_suspend(struct device *dev)
864 {
865 struct pci_dev *pci = to_pci_dev(dev);
866 struct snd_card *card = dev_get_drvdata(dev);
867 struct azx *chip = card->private_data;
868 struct azx_pcm *p;
869
870 if (chip->disabled)
871 return 0;
872
873 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
874 azx_clear_irq_pending(chip);
875 list_for_each_entry(p, &chip->pcm_list, list)
876 snd_pcm_suspend_all(p->pcm);
877 if (chip->initialized)
878 snd_hda_suspend(chip->bus);
879 azx_stop_chip(chip);
880 azx_enter_link_reset(chip);
881 if (chip->irq >= 0) {
882 free_irq(chip->irq, chip);
883 chip->irq = -1;
884 }
885 if (chip->msi)
886 pci_disable_msi(chip->pci);
887 pci_disable_device(pci);
888 pci_save_state(pci);
889 pci_set_power_state(pci, PCI_D3hot);
890 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
891 hda_display_power(false);
892 return 0;
893 }
894
895 static int azx_resume(struct device *dev)
896 {
897 struct pci_dev *pci = to_pci_dev(dev);
898 struct snd_card *card = dev_get_drvdata(dev);
899 struct azx *chip = card->private_data;
900
901 if (chip->disabled)
902 return 0;
903
904 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
905 hda_display_power(true);
906 pci_set_power_state(pci, PCI_D0);
907 pci_restore_state(pci);
908 if (pci_enable_device(pci) < 0) {
909 dev_err(chip->card->dev,
910 "pci_enable_device failed, disabling device\n");
911 snd_card_disconnect(card);
912 return -EIO;
913 }
914 pci_set_master(pci);
915 if (chip->msi)
916 if (pci_enable_msi(pci) < 0)
917 chip->msi = 0;
918 if (azx_acquire_irq(chip, 1) < 0)
919 return -EIO;
920 azx_init_pci(chip);
921
922 azx_init_chip(chip, 1);
923
924 snd_hda_resume(chip->bus);
925 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
926 return 0;
927 }
928 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
929
930 #ifdef CONFIG_PM_RUNTIME
931 static int azx_runtime_suspend(struct device *dev)
932 {
933 struct snd_card *card = dev_get_drvdata(dev);
934 struct azx *chip = card->private_data;
935
936 if (chip->disabled)
937 return 0;
938
939 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
940 return 0;
941
942 /* enable controller wake up event */
943 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
944 STATESTS_INT_MASK);
945
946 azx_stop_chip(chip);
947 azx_enter_link_reset(chip);
948 azx_clear_irq_pending(chip);
949 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
950 hda_display_power(false);
951 return 0;
952 }
953
954 static int azx_runtime_resume(struct device *dev)
955 {
956 struct snd_card *card = dev_get_drvdata(dev);
957 struct azx *chip = card->private_data;
958 struct hda_bus *bus;
959 struct hda_codec *codec;
960 int status;
961
962 if (chip->disabled)
963 return 0;
964
965 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
966 return 0;
967
968 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
969 hda_display_power(true);
970
971 /* Read STATESTS before controller reset */
972 status = azx_readw(chip, STATESTS);
973
974 azx_init_pci(chip);
975 azx_init_chip(chip, 1);
976
977 bus = chip->bus;
978 if (status && bus) {
979 list_for_each_entry(codec, &bus->codec_list, list)
980 if (status & (1 << codec->addr))
981 queue_delayed_work(codec->bus->workq,
982 &codec->jackpoll_work, codec->jackpoll_interval);
983 }
984
985 /* disable controller Wake Up event*/
986 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
987 ~STATESTS_INT_MASK);
988
989 return 0;
990 }
991
992 static int azx_runtime_idle(struct device *dev)
993 {
994 struct snd_card *card = dev_get_drvdata(dev);
995 struct azx *chip = card->private_data;
996
997 if (chip->disabled)
998 return 0;
999
1000 if (!power_save_controller ||
1001 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
1002 return -EBUSY;
1003
1004 return 0;
1005 }
1006
1007 #endif /* CONFIG_PM_RUNTIME */
1008
1009 #ifdef CONFIG_PM
1010 static const struct dev_pm_ops azx_pm = {
1011 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1012 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1013 };
1014
1015 #define AZX_PM_OPS &azx_pm
1016 #else
1017 #define AZX_PM_OPS NULL
1018 #endif /* CONFIG_PM */
1019
1020
1021 /*
1022 * reboot notifier for hang-up problem at power-down
1023 */
1024 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1025 {
1026 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
1027 snd_hda_bus_reboot_notify(chip->bus);
1028 azx_stop_chip(chip);
1029 return NOTIFY_OK;
1030 }
1031
1032 static void azx_notifier_register(struct azx *chip)
1033 {
1034 chip->reboot_notifier.notifier_call = azx_halt;
1035 register_reboot_notifier(&chip->reboot_notifier);
1036 }
1037
1038 static void azx_notifier_unregister(struct azx *chip)
1039 {
1040 if (chip->reboot_notifier.notifier_call)
1041 unregister_reboot_notifier(&chip->reboot_notifier);
1042 }
1043
1044 static int azx_probe_continue(struct azx *chip);
1045
1046 #ifdef SUPPORT_VGA_SWITCHEROO
1047 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1048
1049 static void azx_vs_set_state(struct pci_dev *pci,
1050 enum vga_switcheroo_state state)
1051 {
1052 struct snd_card *card = pci_get_drvdata(pci);
1053 struct azx *chip = card->private_data;
1054 bool disabled;
1055
1056 wait_for_completion(&chip->probe_wait);
1057 if (chip->init_failed)
1058 return;
1059
1060 disabled = (state == VGA_SWITCHEROO_OFF);
1061 if (chip->disabled == disabled)
1062 return;
1063
1064 if (!chip->bus) {
1065 chip->disabled = disabled;
1066 if (!disabled) {
1067 dev_info(chip->card->dev,
1068 "Start delayed initialization\n");
1069 if (azx_probe_continue(chip) < 0) {
1070 dev_err(chip->card->dev, "initialization error\n");
1071 chip->init_failed = true;
1072 }
1073 }
1074 } else {
1075 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1076 disabled ? "Disabling" : "Enabling");
1077 if (disabled) {
1078 pm_runtime_put_sync_suspend(card->dev);
1079 azx_suspend(card->dev);
1080 /* when we get suspended by vga switcheroo we end up in D3cold,
1081 * however we have no ACPI handle, so pci/acpi can't put us there,
1082 * put ourselves there */
1083 pci->current_state = PCI_D3cold;
1084 chip->disabled = true;
1085 if (snd_hda_lock_devices(chip->bus))
1086 dev_warn(chip->card->dev,
1087 "Cannot lock devices!\n");
1088 } else {
1089 snd_hda_unlock_devices(chip->bus);
1090 pm_runtime_get_noresume(card->dev);
1091 chip->disabled = false;
1092 azx_resume(card->dev);
1093 }
1094 }
1095 }
1096
1097 static bool azx_vs_can_switch(struct pci_dev *pci)
1098 {
1099 struct snd_card *card = pci_get_drvdata(pci);
1100 struct azx *chip = card->private_data;
1101
1102 wait_for_completion(&chip->probe_wait);
1103 if (chip->init_failed)
1104 return false;
1105 if (chip->disabled || !chip->bus)
1106 return true;
1107 if (snd_hda_lock_devices(chip->bus))
1108 return false;
1109 snd_hda_unlock_devices(chip->bus);
1110 return true;
1111 }
1112
1113 static void init_vga_switcheroo(struct azx *chip)
1114 {
1115 struct pci_dev *p = get_bound_vga(chip->pci);
1116 if (p) {
1117 dev_info(chip->card->dev,
1118 "Handle VGA-switcheroo audio client\n");
1119 chip->use_vga_switcheroo = 1;
1120 pci_dev_put(p);
1121 }
1122 }
1123
1124 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1125 .set_gpu_state = azx_vs_set_state,
1126 .can_switch = azx_vs_can_switch,
1127 };
1128
1129 static int register_vga_switcheroo(struct azx *chip)
1130 {
1131 int err;
1132
1133 if (!chip->use_vga_switcheroo)
1134 return 0;
1135 /* FIXME: currently only handling DIS controller
1136 * is there any machine with two switchable HDMI audio controllers?
1137 */
1138 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1139 VGA_SWITCHEROO_DIS,
1140 chip->bus != NULL);
1141 if (err < 0)
1142 return err;
1143 chip->vga_switcheroo_registered = 1;
1144
1145 /* register as an optimus hdmi audio power domain */
1146 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1147 &chip->hdmi_pm_domain);
1148 return 0;
1149 }
1150 #else
1151 #define init_vga_switcheroo(chip) /* NOP */
1152 #define register_vga_switcheroo(chip) 0
1153 #define check_hdmi_disabled(pci) false
1154 #endif /* SUPPORT_VGA_SWITCHER */
1155
1156 /*
1157 * destructor
1158 */
1159 static int azx_free(struct azx *chip)
1160 {
1161 struct pci_dev *pci = chip->pci;
1162 int i;
1163
1164 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1165 && chip->running)
1166 pm_runtime_get_noresume(&pci->dev);
1167
1168 azx_del_card_list(chip);
1169
1170 azx_notifier_unregister(chip);
1171
1172 chip->init_failed = 1; /* to be sure */
1173 complete_all(&chip->probe_wait);
1174
1175 if (use_vga_switcheroo(chip)) {
1176 if (chip->disabled && chip->bus)
1177 snd_hda_unlock_devices(chip->bus);
1178 if (chip->vga_switcheroo_registered)
1179 vga_switcheroo_unregister_client(chip->pci);
1180 }
1181
1182 if (chip->initialized) {
1183 azx_clear_irq_pending(chip);
1184 for (i = 0; i < chip->num_streams; i++)
1185 azx_stream_stop(chip, &chip->azx_dev[i]);
1186 azx_stop_chip(chip);
1187 }
1188
1189 if (chip->irq >= 0)
1190 free_irq(chip->irq, (void*)chip);
1191 if (chip->msi)
1192 pci_disable_msi(chip->pci);
1193 if (chip->remap_addr)
1194 iounmap(chip->remap_addr);
1195
1196 azx_free_stream_pages(chip);
1197 if (chip->region_requested)
1198 pci_release_regions(chip->pci);
1199 pci_disable_device(chip->pci);
1200 kfree(chip->azx_dev);
1201 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1202 if (chip->fw)
1203 release_firmware(chip->fw);
1204 #endif
1205 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1206 hda_display_power(false);
1207 hda_i915_exit();
1208 }
1209 kfree(chip);
1210
1211 return 0;
1212 }
1213
1214 static int azx_dev_free(struct snd_device *device)
1215 {
1216 return azx_free(device->device_data);
1217 }
1218
1219 #ifdef SUPPORT_VGA_SWITCHEROO
1220 /*
1221 * Check of disabled HDMI controller by vga-switcheroo
1222 */
1223 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1224 {
1225 struct pci_dev *p;
1226
1227 /* check only discrete GPU */
1228 switch (pci->vendor) {
1229 case PCI_VENDOR_ID_ATI:
1230 case PCI_VENDOR_ID_AMD:
1231 case PCI_VENDOR_ID_NVIDIA:
1232 if (pci->devfn == 1) {
1233 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1234 pci->bus->number, 0);
1235 if (p) {
1236 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1237 return p;
1238 pci_dev_put(p);
1239 }
1240 }
1241 break;
1242 }
1243 return NULL;
1244 }
1245
1246 static bool check_hdmi_disabled(struct pci_dev *pci)
1247 {
1248 bool vga_inactive = false;
1249 struct pci_dev *p = get_bound_vga(pci);
1250
1251 if (p) {
1252 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1253 vga_inactive = true;
1254 pci_dev_put(p);
1255 }
1256 return vga_inactive;
1257 }
1258 #endif /* SUPPORT_VGA_SWITCHEROO */
1259
1260 /*
1261 * white/black-listing for position_fix
1262 */
1263 static struct snd_pci_quirk position_fix_list[] = {
1264 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1265 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1266 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1267 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1268 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1269 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1270 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1271 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1272 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1273 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1274 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1275 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1276 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1277 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1278 {}
1279 };
1280
1281 static int check_position_fix(struct azx *chip, int fix)
1282 {
1283 const struct snd_pci_quirk *q;
1284
1285 switch (fix) {
1286 case POS_FIX_AUTO:
1287 case POS_FIX_LPIB:
1288 case POS_FIX_POSBUF:
1289 case POS_FIX_VIACOMBO:
1290 case POS_FIX_COMBO:
1291 return fix;
1292 }
1293
1294 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1295 if (q) {
1296 dev_info(chip->card->dev,
1297 "position_fix set to %d for device %04x:%04x\n",
1298 q->value, q->subvendor, q->subdevice);
1299 return q->value;
1300 }
1301
1302 /* Check VIA/ATI HD Audio Controller exist */
1303 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1304 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1305 return POS_FIX_VIACOMBO;
1306 }
1307 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1308 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1309 return POS_FIX_LPIB;
1310 }
1311 return POS_FIX_AUTO;
1312 }
1313
1314 /*
1315 * black-lists for probe_mask
1316 */
1317 static struct snd_pci_quirk probe_mask_list[] = {
1318 /* Thinkpad often breaks the controller communication when accessing
1319 * to the non-working (or non-existing) modem codec slot.
1320 */
1321 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1322 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1323 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1324 /* broken BIOS */
1325 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1326 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1327 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1328 /* forced codec slots */
1329 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1330 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1331 /* WinFast VP200 H (Teradici) user reported broken communication */
1332 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1333 {}
1334 };
1335
1336 #define AZX_FORCE_CODEC_MASK 0x100
1337
1338 static void check_probe_mask(struct azx *chip, int dev)
1339 {
1340 const struct snd_pci_quirk *q;
1341
1342 chip->codec_probe_mask = probe_mask[dev];
1343 if (chip->codec_probe_mask == -1) {
1344 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1345 if (q) {
1346 dev_info(chip->card->dev,
1347 "probe_mask set to 0x%x for device %04x:%04x\n",
1348 q->value, q->subvendor, q->subdevice);
1349 chip->codec_probe_mask = q->value;
1350 }
1351 }
1352
1353 /* check forced option */
1354 if (chip->codec_probe_mask != -1 &&
1355 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1356 chip->codec_mask = chip->codec_probe_mask & 0xff;
1357 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1358 chip->codec_mask);
1359 }
1360 }
1361
1362 /*
1363 * white/black-list for enable_msi
1364 */
1365 static struct snd_pci_quirk msi_black_list[] = {
1366 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1367 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1368 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1369 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1370 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1371 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1372 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1373 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1374 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1375 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1376 {}
1377 };
1378
1379 static void check_msi(struct azx *chip)
1380 {
1381 const struct snd_pci_quirk *q;
1382
1383 if (enable_msi >= 0) {
1384 chip->msi = !!enable_msi;
1385 return;
1386 }
1387 chip->msi = 1; /* enable MSI as default */
1388 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1389 if (q) {
1390 dev_info(chip->card->dev,
1391 "msi for device %04x:%04x set to %d\n",
1392 q->subvendor, q->subdevice, q->value);
1393 chip->msi = q->value;
1394 return;
1395 }
1396
1397 /* NVidia chipsets seem to cause troubles with MSI */
1398 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1399 dev_info(chip->card->dev, "Disabling MSI\n");
1400 chip->msi = 0;
1401 }
1402 }
1403
1404 /* check the snoop mode availability */
1405 static void azx_check_snoop_available(struct azx *chip)
1406 {
1407 bool snoop = chip->snoop;
1408
1409 switch (chip->driver_type) {
1410 case AZX_DRIVER_VIA:
1411 /* force to non-snoop mode for a new VIA controller
1412 * when BIOS is set
1413 */
1414 if (snoop) {
1415 u8 val;
1416 pci_read_config_byte(chip->pci, 0x42, &val);
1417 if (!(val & 0x80) && chip->pci->revision == 0x30)
1418 snoop = false;
1419 }
1420 break;
1421 case AZX_DRIVER_ATIHDMI_NS:
1422 /* new ATI HDMI requires non-snoop */
1423 snoop = false;
1424 break;
1425 case AZX_DRIVER_CTHDA:
1426 snoop = false;
1427 break;
1428 }
1429
1430 if (snoop != chip->snoop) {
1431 dev_info(chip->card->dev, "Force to %s mode\n",
1432 snoop ? "snoop" : "non-snoop");
1433 chip->snoop = snoop;
1434 }
1435 }
1436
1437 static void azx_probe_work(struct work_struct *work)
1438 {
1439 azx_probe_continue(container_of(work, struct azx, probe_work));
1440 }
1441
1442 /*
1443 * constructor
1444 */
1445 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1446 int dev, unsigned int driver_caps,
1447 const struct hda_controller_ops *hda_ops,
1448 struct azx **rchip)
1449 {
1450 static struct snd_device_ops ops = {
1451 .dev_free = azx_dev_free,
1452 };
1453 struct azx *chip;
1454 int err;
1455
1456 *rchip = NULL;
1457
1458 err = pci_enable_device(pci);
1459 if (err < 0)
1460 return err;
1461
1462 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1463 if (!chip) {
1464 dev_err(card->dev, "Cannot allocate chip\n");
1465 pci_disable_device(pci);
1466 return -ENOMEM;
1467 }
1468
1469 spin_lock_init(&chip->reg_lock);
1470 mutex_init(&chip->open_mutex);
1471 chip->card = card;
1472 chip->pci = pci;
1473 chip->ops = hda_ops;
1474 chip->irq = -1;
1475 chip->driver_caps = driver_caps;
1476 chip->driver_type = driver_caps & 0xff;
1477 check_msi(chip);
1478 chip->dev_index = dev;
1479 chip->jackpoll_ms = jackpoll_ms;
1480 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
1481 INIT_LIST_HEAD(&chip->pcm_list);
1482 INIT_LIST_HEAD(&chip->list);
1483 init_vga_switcheroo(chip);
1484 init_completion(&chip->probe_wait);
1485
1486 chip->position_fix[0] = chip->position_fix[1] =
1487 check_position_fix(chip, position_fix[dev]);
1488 /* combo mode uses LPIB for playback */
1489 if (chip->position_fix[0] == POS_FIX_COMBO) {
1490 chip->position_fix[0] = POS_FIX_LPIB;
1491 chip->position_fix[1] = POS_FIX_AUTO;
1492 }
1493
1494 check_probe_mask(chip, dev);
1495
1496 chip->single_cmd = single_cmd;
1497 chip->snoop = hda_snoop;
1498 azx_check_snoop_available(chip);
1499
1500 if (bdl_pos_adj[dev] < 0) {
1501 switch (chip->driver_type) {
1502 case AZX_DRIVER_ICH:
1503 case AZX_DRIVER_PCH:
1504 bdl_pos_adj[dev] = 1;
1505 break;
1506 default:
1507 bdl_pos_adj[dev] = 32;
1508 break;
1509 }
1510 }
1511 chip->bdl_pos_adj = bdl_pos_adj;
1512
1513 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1514 if (err < 0) {
1515 dev_err(card->dev, "Error creating device [card]!\n");
1516 azx_free(chip);
1517 return err;
1518 }
1519
1520 /* continue probing in work context as may trigger request module */
1521 INIT_WORK(&chip->probe_work, azx_probe_work);
1522
1523 *rchip = chip;
1524
1525 return 0;
1526 }
1527
1528 static int azx_first_init(struct azx *chip)
1529 {
1530 int dev = chip->dev_index;
1531 struct pci_dev *pci = chip->pci;
1532 struct snd_card *card = chip->card;
1533 int err;
1534 unsigned short gcap;
1535
1536 #if BITS_PER_LONG != 64
1537 /* Fix up base address on ULI M5461 */
1538 if (chip->driver_type == AZX_DRIVER_ULI) {
1539 u16 tmp3;
1540 pci_read_config_word(pci, 0x40, &tmp3);
1541 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1542 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1543 }
1544 #endif
1545
1546 err = pci_request_regions(pci, "ICH HD audio");
1547 if (err < 0)
1548 return err;
1549 chip->region_requested = 1;
1550
1551 chip->addr = pci_resource_start(pci, 0);
1552 chip->remap_addr = pci_ioremap_bar(pci, 0);
1553 if (chip->remap_addr == NULL) {
1554 dev_err(card->dev, "ioremap error\n");
1555 return -ENXIO;
1556 }
1557
1558 if (chip->msi)
1559 if (pci_enable_msi(pci) < 0)
1560 chip->msi = 0;
1561
1562 if (azx_acquire_irq(chip, 0) < 0)
1563 return -EBUSY;
1564
1565 pci_set_master(pci);
1566 synchronize_irq(chip->irq);
1567
1568 gcap = azx_readw(chip, GCAP);
1569 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1570
1571 /* disable SB600 64bit support for safety */
1572 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1573 struct pci_dev *p_smbus;
1574 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1575 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1576 NULL);
1577 if (p_smbus) {
1578 if (p_smbus->revision < 0x30)
1579 gcap &= ~ICH6_GCAP_64OK;
1580 pci_dev_put(p_smbus);
1581 }
1582 }
1583
1584 /* disable 64bit DMA address on some devices */
1585 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1586 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1587 gcap &= ~ICH6_GCAP_64OK;
1588 }
1589
1590 /* disable buffer size rounding to 128-byte multiples if supported */
1591 if (align_buffer_size >= 0)
1592 chip->align_buffer_size = !!align_buffer_size;
1593 else {
1594 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
1595 chip->align_buffer_size = 0;
1596 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
1597 chip->align_buffer_size = 1;
1598 else
1599 chip->align_buffer_size = 1;
1600 }
1601
1602 /* allow 64bit DMA address if supported by H/W */
1603 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
1604 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
1605 else {
1606 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1607 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
1608 }
1609
1610 /* read number of streams from GCAP register instead of using
1611 * hardcoded value
1612 */
1613 chip->capture_streams = (gcap >> 8) & 0x0f;
1614 chip->playback_streams = (gcap >> 12) & 0x0f;
1615 if (!chip->playback_streams && !chip->capture_streams) {
1616 /* gcap didn't give any info, switching to old method */
1617
1618 switch (chip->driver_type) {
1619 case AZX_DRIVER_ULI:
1620 chip->playback_streams = ULI_NUM_PLAYBACK;
1621 chip->capture_streams = ULI_NUM_CAPTURE;
1622 break;
1623 case AZX_DRIVER_ATIHDMI:
1624 case AZX_DRIVER_ATIHDMI_NS:
1625 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1626 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1627 break;
1628 case AZX_DRIVER_GENERIC:
1629 default:
1630 chip->playback_streams = ICH6_NUM_PLAYBACK;
1631 chip->capture_streams = ICH6_NUM_CAPTURE;
1632 break;
1633 }
1634 }
1635 chip->capture_index_offset = 0;
1636 chip->playback_index_offset = chip->capture_streams;
1637 chip->num_streams = chip->playback_streams + chip->capture_streams;
1638 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1639 GFP_KERNEL);
1640 if (!chip->azx_dev) {
1641 dev_err(card->dev, "cannot malloc azx_dev\n");
1642 return -ENOMEM;
1643 }
1644
1645 err = azx_alloc_stream_pages(chip);
1646 if (err < 0)
1647 return err;
1648
1649 /* initialize streams */
1650 azx_init_stream(chip);
1651
1652 /* initialize chip */
1653 azx_init_pci(chip);
1654 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1655
1656 /* codec detection */
1657 if (!chip->codec_mask) {
1658 dev_err(card->dev, "no codecs found!\n");
1659 return -ENODEV;
1660 }
1661
1662 strcpy(card->driver, "HDA-Intel");
1663 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1664 sizeof(card->shortname));
1665 snprintf(card->longname, sizeof(card->longname),
1666 "%s at 0x%lx irq %i",
1667 card->shortname, chip->addr, chip->irq);
1668
1669 return 0;
1670 }
1671
1672 static void power_down_all_codecs(struct azx *chip)
1673 {
1674 #ifdef CONFIG_PM
1675 /* The codecs were powered up in snd_hda_codec_new().
1676 * Now all initialization done, so turn them down if possible
1677 */
1678 struct hda_codec *codec;
1679 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1680 snd_hda_power_down(codec);
1681 }
1682 #endif
1683 }
1684
1685 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1686 /* callback from request_firmware_nowait() */
1687 static void azx_firmware_cb(const struct firmware *fw, void *context)
1688 {
1689 struct snd_card *card = context;
1690 struct azx *chip = card->private_data;
1691 struct pci_dev *pci = chip->pci;
1692
1693 if (!fw) {
1694 dev_err(card->dev, "Cannot load firmware, aborting\n");
1695 goto error;
1696 }
1697
1698 chip->fw = fw;
1699 if (!chip->disabled) {
1700 /* continue probing */
1701 if (azx_probe_continue(chip))
1702 goto error;
1703 }
1704 return; /* OK */
1705
1706 error:
1707 snd_card_free(card);
1708 pci_set_drvdata(pci, NULL);
1709 }
1710 #endif
1711
1712 /*
1713 * HDA controller ops.
1714 */
1715
1716 /* PCI register access. */
1717 static void pci_azx_writel(u32 value, u32 *addr)
1718 {
1719 writel(value, addr);
1720 }
1721
1722 static u32 pci_azx_readl(u32 *addr)
1723 {
1724 return readl(addr);
1725 }
1726
1727 static void pci_azx_writew(u16 value, u16 *addr)
1728 {
1729 writew(value, addr);
1730 }
1731
1732 static u16 pci_azx_readw(u16 *addr)
1733 {
1734 return readw(addr);
1735 }
1736
1737 static void pci_azx_writeb(u8 value, u8 *addr)
1738 {
1739 writeb(value, addr);
1740 }
1741
1742 static u8 pci_azx_readb(u8 *addr)
1743 {
1744 return readb(addr);
1745 }
1746
1747 static int disable_msi_reset_irq(struct azx *chip)
1748 {
1749 int err;
1750
1751 free_irq(chip->irq, chip);
1752 chip->irq = -1;
1753 pci_disable_msi(chip->pci);
1754 chip->msi = 0;
1755 err = azx_acquire_irq(chip, 1);
1756 if (err < 0)
1757 return err;
1758
1759 return 0;
1760 }
1761
1762 /* DMA page allocation helpers. */
1763 static int dma_alloc_pages(struct azx *chip,
1764 int type,
1765 size_t size,
1766 struct snd_dma_buffer *buf)
1767 {
1768 int err;
1769
1770 err = snd_dma_alloc_pages(type,
1771 chip->card->dev,
1772 size, buf);
1773 if (err < 0)
1774 return err;
1775 mark_pages_wc(chip, buf, true);
1776 return 0;
1777 }
1778
1779 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1780 {
1781 mark_pages_wc(chip, buf, false);
1782 snd_dma_free_pages(buf);
1783 }
1784
1785 static int substream_alloc_pages(struct azx *chip,
1786 struct snd_pcm_substream *substream,
1787 size_t size)
1788 {
1789 struct azx_dev *azx_dev = get_azx_dev(substream);
1790 int ret;
1791
1792 mark_runtime_wc(chip, azx_dev, substream, false);
1793 azx_dev->bufsize = 0;
1794 azx_dev->period_bytes = 0;
1795 azx_dev->format_val = 0;
1796 ret = snd_pcm_lib_malloc_pages(substream, size);
1797 if (ret < 0)
1798 return ret;
1799 mark_runtime_wc(chip, azx_dev, substream, true);
1800 return 0;
1801 }
1802
1803 static int substream_free_pages(struct azx *chip,
1804 struct snd_pcm_substream *substream)
1805 {
1806 struct azx_dev *azx_dev = get_azx_dev(substream);
1807 mark_runtime_wc(chip, azx_dev, substream, false);
1808 return snd_pcm_lib_free_pages(substream);
1809 }
1810
1811 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1812 struct vm_area_struct *area)
1813 {
1814 #ifdef CONFIG_X86
1815 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1816 struct azx *chip = apcm->chip;
1817 if (!azx_snoop(chip))
1818 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1819 #endif
1820 }
1821
1822 static const struct hda_controller_ops pci_hda_ops = {
1823 .writel = pci_azx_writel,
1824 .readl = pci_azx_readl,
1825 .writew = pci_azx_writew,
1826 .readw = pci_azx_readw,
1827 .writeb = pci_azx_writeb,
1828 .readb = pci_azx_readb,
1829 .disable_msi_reset_irq = disable_msi_reset_irq,
1830 .dma_alloc_pages = dma_alloc_pages,
1831 .dma_free_pages = dma_free_pages,
1832 .substream_alloc_pages = substream_alloc_pages,
1833 .substream_free_pages = substream_free_pages,
1834 .pcm_mmap_prepare = pcm_mmap_prepare,
1835 .position_check = azx_position_check,
1836 };
1837
1838 static int azx_probe(struct pci_dev *pci,
1839 const struct pci_device_id *pci_id)
1840 {
1841 static int dev;
1842 struct snd_card *card;
1843 struct azx *chip;
1844 bool schedule_probe;
1845 int err;
1846
1847 if (dev >= SNDRV_CARDS)
1848 return -ENODEV;
1849 if (!enable[dev]) {
1850 dev++;
1851 return -ENOENT;
1852 }
1853
1854 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1855 0, &card);
1856 if (err < 0) {
1857 dev_err(&pci->dev, "Error creating card!\n");
1858 return err;
1859 }
1860
1861 err = azx_create(card, pci, dev, pci_id->driver_data,
1862 &pci_hda_ops, &chip);
1863 if (err < 0)
1864 goto out_free;
1865 card->private_data = chip;
1866
1867 pci_set_drvdata(pci, card);
1868
1869 err = register_vga_switcheroo(chip);
1870 if (err < 0) {
1871 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
1872 goto out_free;
1873 }
1874
1875 if (check_hdmi_disabled(pci)) {
1876 dev_info(card->dev, "VGA controller is disabled\n");
1877 dev_info(card->dev, "Delaying initialization\n");
1878 chip->disabled = true;
1879 }
1880
1881 schedule_probe = !chip->disabled;
1882
1883 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1884 if (patch[dev] && *patch[dev]) {
1885 dev_info(card->dev, "Applying patch firmware '%s'\n",
1886 patch[dev]);
1887 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1888 &pci->dev, GFP_KERNEL, card,
1889 azx_firmware_cb);
1890 if (err < 0)
1891 goto out_free;
1892 schedule_probe = false; /* continued in azx_firmware_cb() */
1893 }
1894 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1895
1896 #ifndef CONFIG_SND_HDA_I915
1897 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1898 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1899 #endif
1900
1901 if (schedule_probe)
1902 schedule_work(&chip->probe_work);
1903
1904 dev++;
1905 if (chip->disabled)
1906 complete_all(&chip->probe_wait);
1907 return 0;
1908
1909 out_free:
1910 snd_card_free(card);
1911 return err;
1912 }
1913
1914 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1915 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1916 [AZX_DRIVER_NVIDIA] = 8,
1917 [AZX_DRIVER_TERA] = 1,
1918 };
1919
1920 static int azx_probe_continue(struct azx *chip)
1921 {
1922 struct pci_dev *pci = chip->pci;
1923 int dev = chip->dev_index;
1924 int err;
1925
1926 /* Request power well for Haswell HDA controller and codec */
1927 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1928 #ifdef CONFIG_SND_HDA_I915
1929 err = hda_i915_init();
1930 if (err < 0) {
1931 dev_err(chip->card->dev,
1932 "Error request power-well from i915\n");
1933 goto out_free;
1934 }
1935 #endif
1936 hda_display_power(true);
1937 }
1938
1939 err = azx_first_init(chip);
1940 if (err < 0)
1941 goto out_free;
1942
1943 #ifdef CONFIG_SND_HDA_INPUT_BEEP
1944 chip->beep_mode = beep_mode[dev];
1945 #endif
1946
1947 /* create codec instances */
1948 err = azx_codec_create(chip, model[dev],
1949 azx_max_codecs[chip->driver_type],
1950 power_save_addr);
1951
1952 if (err < 0)
1953 goto out_free;
1954 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1955 if (chip->fw) {
1956 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1957 chip->fw->data);
1958 if (err < 0)
1959 goto out_free;
1960 #ifndef CONFIG_PM
1961 release_firmware(chip->fw); /* no longer needed */
1962 chip->fw = NULL;
1963 #endif
1964 }
1965 #endif
1966 if ((probe_only[dev] & 1) == 0) {
1967 err = azx_codec_configure(chip);
1968 if (err < 0)
1969 goto out_free;
1970 }
1971
1972 /* create PCM streams */
1973 err = snd_hda_build_pcms(chip->bus);
1974 if (err < 0)
1975 goto out_free;
1976
1977 /* create mixer controls */
1978 err = azx_mixer_create(chip);
1979 if (err < 0)
1980 goto out_free;
1981
1982 err = snd_card_register(chip->card);
1983 if (err < 0)
1984 goto out_free;
1985
1986 chip->running = 1;
1987 power_down_all_codecs(chip);
1988 azx_notifier_register(chip);
1989 azx_add_card_list(chip);
1990 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
1991 pm_runtime_put_noidle(&pci->dev);
1992
1993 out_free:
1994 if (err < 0)
1995 chip->init_failed = 1;
1996 complete_all(&chip->probe_wait);
1997 return err;
1998 }
1999
2000 static void azx_remove(struct pci_dev *pci)
2001 {
2002 struct snd_card *card = pci_get_drvdata(pci);
2003
2004 if (card)
2005 snd_card_free(card);
2006 }
2007
2008 /* PCI IDs */
2009 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2010 /* CPT */
2011 { PCI_DEVICE(0x8086, 0x1c20),
2012 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2013 /* PBG */
2014 { PCI_DEVICE(0x8086, 0x1d20),
2015 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2016 /* Panther Point */
2017 { PCI_DEVICE(0x8086, 0x1e20),
2018 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2019 /* Lynx Point */
2020 { PCI_DEVICE(0x8086, 0x8c20),
2021 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2022 /* Wellsburg */
2023 { PCI_DEVICE(0x8086, 0x8d20),
2024 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2025 { PCI_DEVICE(0x8086, 0x8d21),
2026 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2027 /* Lynx Point-LP */
2028 { PCI_DEVICE(0x8086, 0x9c20),
2029 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2030 /* Lynx Point-LP */
2031 { PCI_DEVICE(0x8086, 0x9c21),
2032 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2033 /* Wildcat Point-LP */
2034 { PCI_DEVICE(0x8086, 0x9ca0),
2035 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2036 /* Haswell */
2037 { PCI_DEVICE(0x8086, 0x0a0c),
2038 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2039 { PCI_DEVICE(0x8086, 0x0c0c),
2040 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2041 { PCI_DEVICE(0x8086, 0x0d0c),
2042 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2043 /* Broadwell */
2044 { PCI_DEVICE(0x8086, 0x160c),
2045 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2046 /* 5 Series/3400 */
2047 { PCI_DEVICE(0x8086, 0x3b56),
2048 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2049 /* Poulsbo */
2050 { PCI_DEVICE(0x8086, 0x811b),
2051 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2052 /* Oaktrail */
2053 { PCI_DEVICE(0x8086, 0x080a),
2054 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2055 /* BayTrail */
2056 { PCI_DEVICE(0x8086, 0x0f04),
2057 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2058 /* ICH */
2059 { PCI_DEVICE(0x8086, 0x2668),
2060 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2061 AZX_DCAPS_BUFSIZE }, /* ICH6 */
2062 { PCI_DEVICE(0x8086, 0x27d8),
2063 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2064 AZX_DCAPS_BUFSIZE }, /* ICH7 */
2065 { PCI_DEVICE(0x8086, 0x269a),
2066 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2067 AZX_DCAPS_BUFSIZE }, /* ESB2 */
2068 { PCI_DEVICE(0x8086, 0x284b),
2069 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2070 AZX_DCAPS_BUFSIZE }, /* ICH8 */
2071 { PCI_DEVICE(0x8086, 0x293e),
2072 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2073 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2074 { PCI_DEVICE(0x8086, 0x293f),
2075 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2076 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2077 { PCI_DEVICE(0x8086, 0x3a3e),
2078 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2079 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2080 { PCI_DEVICE(0x8086, 0x3a6e),
2081 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2082 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2083 /* Generic Intel */
2084 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2085 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2086 .class_mask = 0xffffff,
2087 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
2088 /* ATI SB 450/600/700/800/900 */
2089 { PCI_DEVICE(0x1002, 0x437b),
2090 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2091 { PCI_DEVICE(0x1002, 0x4383),
2092 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2093 /* AMD Hudson */
2094 { PCI_DEVICE(0x1022, 0x780d),
2095 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2096 /* ATI HDMI */
2097 { PCI_DEVICE(0x1002, 0x793b),
2098 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2099 { PCI_DEVICE(0x1002, 0x7919),
2100 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2101 { PCI_DEVICE(0x1002, 0x960f),
2102 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2103 { PCI_DEVICE(0x1002, 0x970f),
2104 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2105 { PCI_DEVICE(0x1002, 0xaa00),
2106 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2107 { PCI_DEVICE(0x1002, 0xaa08),
2108 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2109 { PCI_DEVICE(0x1002, 0xaa10),
2110 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2111 { PCI_DEVICE(0x1002, 0xaa18),
2112 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2113 { PCI_DEVICE(0x1002, 0xaa20),
2114 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2115 { PCI_DEVICE(0x1002, 0xaa28),
2116 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2117 { PCI_DEVICE(0x1002, 0xaa30),
2118 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2119 { PCI_DEVICE(0x1002, 0xaa38),
2120 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2121 { PCI_DEVICE(0x1002, 0xaa40),
2122 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2123 { PCI_DEVICE(0x1002, 0xaa48),
2124 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2125 { PCI_DEVICE(0x1002, 0xaa50),
2126 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2127 { PCI_DEVICE(0x1002, 0xaa58),
2128 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2129 { PCI_DEVICE(0x1002, 0xaa60),
2130 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2131 { PCI_DEVICE(0x1002, 0xaa68),
2132 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2133 { PCI_DEVICE(0x1002, 0xaa80),
2134 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2135 { PCI_DEVICE(0x1002, 0xaa88),
2136 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2137 { PCI_DEVICE(0x1002, 0xaa90),
2138 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2139 { PCI_DEVICE(0x1002, 0xaa98),
2140 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2141 { PCI_DEVICE(0x1002, 0x9902),
2142 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2143 { PCI_DEVICE(0x1002, 0xaaa0),
2144 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2145 { PCI_DEVICE(0x1002, 0xaaa8),
2146 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2147 { PCI_DEVICE(0x1002, 0xaab0),
2148 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2149 /* VIA VT8251/VT8237A */
2150 { PCI_DEVICE(0x1106, 0x3288),
2151 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2152 /* VIA GFX VT7122/VX900 */
2153 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2154 /* VIA GFX VT6122/VX11 */
2155 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2156 /* SIS966 */
2157 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2158 /* ULI M5461 */
2159 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2160 /* NVIDIA MCP */
2161 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2162 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2163 .class_mask = 0xffffff,
2164 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2165 /* Teradici */
2166 { PCI_DEVICE(0x6549, 0x1200),
2167 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2168 { PCI_DEVICE(0x6549, 0x2200),
2169 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2170 /* Creative X-Fi (CA0110-IBG) */
2171 /* CTHDA chips */
2172 { PCI_DEVICE(0x1102, 0x0010),
2173 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2174 { PCI_DEVICE(0x1102, 0x0012),
2175 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2176 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2177 /* the following entry conflicts with snd-ctxfi driver,
2178 * as ctxfi driver mutates from HD-audio to native mode with
2179 * a special command sequence.
2180 */
2181 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2182 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2183 .class_mask = 0xffffff,
2184 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2185 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2186 #else
2187 /* this entry seems still valid -- i.e. without emu20kx chip */
2188 { PCI_DEVICE(0x1102, 0x0009),
2189 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2190 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2191 #endif
2192 /* Vortex86MX */
2193 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2194 /* VMware HDAudio */
2195 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2196 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2197 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2198 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2199 .class_mask = 0xffffff,
2200 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2201 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2202 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2203 .class_mask = 0xffffff,
2204 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2205 { 0, }
2206 };
2207 MODULE_DEVICE_TABLE(pci, azx_ids);
2208
2209 /* pci_driver definition */
2210 static struct pci_driver azx_driver = {
2211 .name = KBUILD_MODNAME,
2212 .id_table = azx_ids,
2213 .probe = azx_probe,
2214 .remove = azx_remove,
2215 .driver = {
2216 .pm = AZX_PM_OPS,
2217 },
2218 };
2219
2220 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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