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Merge branch 'topic/hda' into for-next
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <linux/vgaarb.h>
61 #include <linux/vga_switcheroo.h>
62 #include <linux/firmware.h>
63 #include "hda_codec.h"
64 #include "hda_controller.h"
65 #include "hda_intel.h"
66
67 /* position fix mode */
68 enum {
69 POS_FIX_AUTO,
70 POS_FIX_LPIB,
71 POS_FIX_POSBUF,
72 POS_FIX_VIACOMBO,
73 POS_FIX_COMBO,
74 };
75
76 /* Defines for ATI HD Audio support in SB450 south bridge */
77 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
78 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
79
80 /* Defines for Nvidia HDA support */
81 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
82 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
83 #define NVIDIA_HDA_ISTRM_COH 0x4d
84 #define NVIDIA_HDA_OSTRM_COH 0x4c
85 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
86
87 /* Defines for Intel SCH HDA snoop control */
88 #define INTEL_SCH_HDA_DEVC 0x78
89 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
90
91 /* Define IN stream 0 FIFO size offset in VIA controller */
92 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
93 /* Define VIA HD Audio Device ID*/
94 #define VIA_HDAC_DEVICE_ID 0x3288
95
96 /* max number of SDs */
97 /* ICH, ATI and VIA have 4 playback and 4 capture */
98 #define ICH6_NUM_CAPTURE 4
99 #define ICH6_NUM_PLAYBACK 4
100
101 /* ULI has 6 playback and 5 capture */
102 #define ULI_NUM_CAPTURE 5
103 #define ULI_NUM_PLAYBACK 6
104
105 /* ATI HDMI may have up to 8 playbacks and 0 capture */
106 #define ATIHDMI_NUM_CAPTURE 0
107 #define ATIHDMI_NUM_PLAYBACK 8
108
109 /* TERA has 4 playback and 3 capture */
110 #define TERA_NUM_CAPTURE 3
111 #define TERA_NUM_PLAYBACK 4
112
113
114 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
115 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
116 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
117 static char *model[SNDRV_CARDS];
118 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
119 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
120 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
121 static int probe_only[SNDRV_CARDS];
122 static int jackpoll_ms[SNDRV_CARDS];
123 static bool single_cmd;
124 static int enable_msi = -1;
125 #ifdef CONFIG_SND_HDA_PATCH_LOADER
126 static char *patch[SNDRV_CARDS];
127 #endif
128 #ifdef CONFIG_SND_HDA_INPUT_BEEP
129 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
130 CONFIG_SND_HDA_INPUT_BEEP_MODE};
131 #endif
132
133 module_param_array(index, int, NULL, 0444);
134 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
135 module_param_array(id, charp, NULL, 0444);
136 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
137 module_param_array(enable, bool, NULL, 0444);
138 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
139 module_param_array(model, charp, NULL, 0444);
140 MODULE_PARM_DESC(model, "Use the given board model.");
141 module_param_array(position_fix, int, NULL, 0444);
142 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
143 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
144 module_param_array(bdl_pos_adj, int, NULL, 0644);
145 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
146 module_param_array(probe_mask, int, NULL, 0444);
147 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
148 module_param_array(probe_only, int, NULL, 0444);
149 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
150 module_param_array(jackpoll_ms, int, NULL, 0444);
151 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
152 module_param(single_cmd, bool, 0444);
153 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
154 "(for debugging only).");
155 module_param(enable_msi, bint, 0444);
156 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
157 #ifdef CONFIG_SND_HDA_PATCH_LOADER
158 module_param_array(patch, charp, NULL, 0444);
159 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
160 #endif
161 #ifdef CONFIG_SND_HDA_INPUT_BEEP
162 module_param_array(beep_mode, bool, NULL, 0444);
163 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
164 "(0=off, 1=on) (default=1).");
165 #endif
166
167 #ifdef CONFIG_PM
168 static int param_set_xint(const char *val, const struct kernel_param *kp);
169 static struct kernel_param_ops param_ops_xint = {
170 .set = param_set_xint,
171 .get = param_get_int,
172 };
173 #define param_check_xint param_check_int
174
175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
176 module_param(power_save, xint, 0644);
177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
178 "(in second, 0 = disable).");
179
180 /* reset the HD-audio controller in power save mode.
181 * this may give more power-saving, but will take longer time to
182 * wake up.
183 */
184 static bool power_save_controller = 1;
185 module_param(power_save_controller, bool, 0644);
186 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
187 #else
188 #define power_save 0
189 #endif /* CONFIG_PM */
190
191 static int align_buffer_size = -1;
192 module_param(align_buffer_size, bint, 0644);
193 MODULE_PARM_DESC(align_buffer_size,
194 "Force buffer and period sizes to be multiple of 128 bytes.");
195
196 #ifdef CONFIG_X86
197 static int hda_snoop = -1;
198 module_param_named(snoop, hda_snoop, bint, 0444);
199 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
200 #else
201 #define hda_snoop true
202 #endif
203
204
205 MODULE_LICENSE("GPL");
206 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
207 "{Intel, ICH6M},"
208 "{Intel, ICH7},"
209 "{Intel, ESB2},"
210 "{Intel, ICH8},"
211 "{Intel, ICH9},"
212 "{Intel, ICH10},"
213 "{Intel, PCH},"
214 "{Intel, CPT},"
215 "{Intel, PPT},"
216 "{Intel, LPT},"
217 "{Intel, LPT_LP},"
218 "{Intel, WPT_LP},"
219 "{Intel, SPT},"
220 "{Intel, SPT_LP},"
221 "{Intel, HPT},"
222 "{Intel, PBG},"
223 "{Intel, SCH},"
224 "{ATI, SB450},"
225 "{ATI, SB600},"
226 "{ATI, RS600},"
227 "{ATI, RS690},"
228 "{ATI, RS780},"
229 "{ATI, R600},"
230 "{ATI, RV630},"
231 "{ATI, RV610},"
232 "{ATI, RV670},"
233 "{ATI, RV635},"
234 "{ATI, RV620},"
235 "{ATI, RV770},"
236 "{VIA, VT8251},"
237 "{VIA, VT8237A},"
238 "{SiS, SIS966},"
239 "{ULI, M5461}}");
240 MODULE_DESCRIPTION("Intel HDA driver");
241
242 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
243 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
244 #define SUPPORT_VGA_SWITCHEROO
245 #endif
246 #endif
247
248
249 /*
250 */
251
252 /* driver types */
253 enum {
254 AZX_DRIVER_ICH,
255 AZX_DRIVER_PCH,
256 AZX_DRIVER_SCH,
257 AZX_DRIVER_HDMI,
258 AZX_DRIVER_ATI,
259 AZX_DRIVER_ATIHDMI,
260 AZX_DRIVER_ATIHDMI_NS,
261 AZX_DRIVER_VIA,
262 AZX_DRIVER_SIS,
263 AZX_DRIVER_ULI,
264 AZX_DRIVER_NVIDIA,
265 AZX_DRIVER_TERA,
266 AZX_DRIVER_CTX,
267 AZX_DRIVER_CTHDA,
268 AZX_DRIVER_CMEDIA,
269 AZX_DRIVER_GENERIC,
270 AZX_NUM_DRIVERS, /* keep this as last entry */
271 };
272
273 #define azx_get_snoop_type(chip) \
274 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
275 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
276
277 /* quirks for old Intel chipsets */
278 #define AZX_DCAPS_INTEL_ICH \
279 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
280
281 /* quirks for Intel PCH */
282 #define AZX_DCAPS_INTEL_PCH_NOPM \
283 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
284 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
285
286 #define AZX_DCAPS_INTEL_PCH \
287 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
288
289 #define AZX_DCAPS_INTEL_HASWELL \
290 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
291 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
292 AZX_DCAPS_SNOOP_TYPE(SCH))
293
294 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
295 #define AZX_DCAPS_INTEL_BROADWELL \
296 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
297 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
298 AZX_DCAPS_SNOOP_TYPE(SCH))
299
300 #define AZX_DCAPS_INTEL_BAYTRAIL \
301 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
302
303 #define AZX_DCAPS_INTEL_BRASWELL \
304 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
305
306 #define AZX_DCAPS_INTEL_SKYLAKE \
307 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
308 AZX_DCAPS_I915_POWERWELL)
309
310 /* quirks for ATI SB / AMD Hudson */
311 #define AZX_DCAPS_PRESET_ATI_SB \
312 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
313 AZX_DCAPS_SNOOP_TYPE(ATI))
314
315 /* quirks for ATI/AMD HDMI */
316 #define AZX_DCAPS_PRESET_ATI_HDMI \
317 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
318 AZX_DCAPS_NO_MSI64)
319
320 /* quirks for ATI HDMI with snoop off */
321 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
322 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
323
324 /* quirks for Nvidia */
325 #define AZX_DCAPS_PRESET_NVIDIA \
326 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
327 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
328 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
329
330 #define AZX_DCAPS_PRESET_CTHDA \
331 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
332 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
333
334 /*
335 * VGA-switcher support
336 */
337 #ifdef SUPPORT_VGA_SWITCHEROO
338 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
339 #else
340 #define use_vga_switcheroo(chip) 0
341 #endif
342
343 static char *driver_short_names[] = {
344 [AZX_DRIVER_ICH] = "HDA Intel",
345 [AZX_DRIVER_PCH] = "HDA Intel PCH",
346 [AZX_DRIVER_SCH] = "HDA Intel MID",
347 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
348 [AZX_DRIVER_ATI] = "HDA ATI SB",
349 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
350 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
351 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
352 [AZX_DRIVER_SIS] = "HDA SIS966",
353 [AZX_DRIVER_ULI] = "HDA ULI M5461",
354 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
355 [AZX_DRIVER_TERA] = "HDA Teradici",
356 [AZX_DRIVER_CTX] = "HDA Creative",
357 [AZX_DRIVER_CTHDA] = "HDA Creative",
358 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
359 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
360 };
361
362 #ifdef CONFIG_X86
363 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
364 {
365 int pages;
366
367 if (azx_snoop(chip))
368 return;
369 if (!dmab || !dmab->area || !dmab->bytes)
370 return;
371
372 #ifdef CONFIG_SND_DMA_SGBUF
373 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
374 struct snd_sg_buf *sgbuf = dmab->private_data;
375 if (chip->driver_type == AZX_DRIVER_CMEDIA)
376 return; /* deal with only CORB/RIRB buffers */
377 if (on)
378 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
379 else
380 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
381 return;
382 }
383 #endif
384
385 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
386 if (on)
387 set_memory_wc((unsigned long)dmab->area, pages);
388 else
389 set_memory_wb((unsigned long)dmab->area, pages);
390 }
391
392 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
393 bool on)
394 {
395 __mark_pages_wc(chip, buf, on);
396 }
397 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
398 struct snd_pcm_substream *substream, bool on)
399 {
400 if (azx_dev->wc_marked != on) {
401 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
402 azx_dev->wc_marked = on;
403 }
404 }
405 #else
406 /* NOP for other archs */
407 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
408 bool on)
409 {
410 }
411 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
412 struct snd_pcm_substream *substream, bool on)
413 {
414 }
415 #endif
416
417 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
418
419 /*
420 * initialize the PCI registers
421 */
422 /* update bits in a PCI register byte */
423 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
424 unsigned char mask, unsigned char val)
425 {
426 unsigned char data;
427
428 pci_read_config_byte(pci, reg, &data);
429 data &= ~mask;
430 data |= (val & mask);
431 pci_write_config_byte(pci, reg, data);
432 }
433
434 static void azx_init_pci(struct azx *chip)
435 {
436 int snoop_type = azx_get_snoop_type(chip);
437
438 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
439 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
440 * Ensuring these bits are 0 clears playback static on some HD Audio
441 * codecs.
442 * The PCI register TCSEL is defined in the Intel manuals.
443 */
444 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
445 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
446 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
447 }
448
449 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
450 * we need to enable snoop.
451 */
452 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
453 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
454 azx_snoop(chip));
455 update_pci_byte(chip->pci,
456 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
457 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
458 }
459
460 /* For NVIDIA HDA, enable snoop */
461 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
462 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
463 azx_snoop(chip));
464 update_pci_byte(chip->pci,
465 NVIDIA_HDA_TRANSREG_ADDR,
466 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
467 update_pci_byte(chip->pci,
468 NVIDIA_HDA_ISTRM_COH,
469 0x01, NVIDIA_HDA_ENABLE_COHBIT);
470 update_pci_byte(chip->pci,
471 NVIDIA_HDA_OSTRM_COH,
472 0x01, NVIDIA_HDA_ENABLE_COHBIT);
473 }
474
475 /* Enable SCH/PCH snoop if needed */
476 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
477 unsigned short snoop;
478 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
479 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
480 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
481 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
482 if (!azx_snoop(chip))
483 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
484 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
485 pci_read_config_word(chip->pci,
486 INTEL_SCH_HDA_DEVC, &snoop);
487 }
488 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
489 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
490 "Disabled" : "Enabled");
491 }
492 }
493
494 /* calculate runtime delay from LPIB */
495 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
496 unsigned int pos)
497 {
498 struct snd_pcm_substream *substream = azx_dev->core.substream;
499 int stream = substream->stream;
500 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
501 int delay;
502
503 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
504 delay = pos - lpib_pos;
505 else
506 delay = lpib_pos - pos;
507 if (delay < 0) {
508 if (delay >= azx_dev->core.delay_negative_threshold)
509 delay = 0;
510 else
511 delay += azx_dev->core.bufsize;
512 }
513
514 if (delay >= azx_dev->core.period_bytes) {
515 dev_info(chip->card->dev,
516 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
517 delay, azx_dev->core.period_bytes);
518 delay = 0;
519 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
520 chip->get_delay[stream] = NULL;
521 }
522
523 return bytes_to_frames(substream->runtime, delay);
524 }
525
526 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
527
528 /* called from IRQ */
529 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
530 {
531 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
532 int ok;
533
534 ok = azx_position_ok(chip, azx_dev);
535 if (ok == 1) {
536 azx_dev->irq_pending = 0;
537 return ok;
538 } else if (ok == 0) {
539 /* bogus IRQ, process it later */
540 azx_dev->irq_pending = 1;
541 schedule_work(&hda->irq_pending_work);
542 }
543 return 0;
544 }
545
546 /* Enable/disable i915 display power for the link */
547 static int azx_intel_link_power(struct azx *chip, bool enable)
548 {
549 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
550
551 return hda_display_power(hda, enable);
552 }
553
554 /*
555 * Check whether the current DMA position is acceptable for updating
556 * periods. Returns non-zero if it's OK.
557 *
558 * Many HD-audio controllers appear pretty inaccurate about
559 * the update-IRQ timing. The IRQ is issued before actually the
560 * data is processed. So, we need to process it afterwords in a
561 * workqueue.
562 */
563 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
564 {
565 struct snd_pcm_substream *substream = azx_dev->core.substream;
566 int stream = substream->stream;
567 u32 wallclk;
568 unsigned int pos;
569
570 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
571 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
572 return -1; /* bogus (too early) interrupt */
573
574 if (chip->get_position[stream])
575 pos = chip->get_position[stream](chip, azx_dev);
576 else { /* use the position buffer as default */
577 pos = azx_get_pos_posbuf(chip, azx_dev);
578 if (!pos || pos == (u32)-1) {
579 dev_info(chip->card->dev,
580 "Invalid position buffer, using LPIB read method instead.\n");
581 chip->get_position[stream] = azx_get_pos_lpib;
582 if (chip->get_position[0] == azx_get_pos_lpib &&
583 chip->get_position[1] == azx_get_pos_lpib)
584 azx_bus(chip)->use_posbuf = false;
585 pos = azx_get_pos_lpib(chip, azx_dev);
586 chip->get_delay[stream] = NULL;
587 } else {
588 chip->get_position[stream] = azx_get_pos_posbuf;
589 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
590 chip->get_delay[stream] = azx_get_delay_from_lpib;
591 }
592 }
593
594 if (pos >= azx_dev->core.bufsize)
595 pos = 0;
596
597 if (WARN_ONCE(!azx_dev->core.period_bytes,
598 "hda-intel: zero azx_dev->period_bytes"))
599 return -1; /* this shouldn't happen! */
600 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
601 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
602 /* NG - it's below the first next period boundary */
603 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
604 azx_dev->core.start_wallclk += wallclk;
605 return 1; /* OK, it's fine */
606 }
607
608 /*
609 * The work for pending PCM period updates.
610 */
611 static void azx_irq_pending_work(struct work_struct *work)
612 {
613 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
614 struct azx *chip = &hda->chip;
615 struct hdac_bus *bus = azx_bus(chip);
616 struct hdac_stream *s;
617 int pending, ok;
618
619 if (!hda->irq_pending_warned) {
620 dev_info(chip->card->dev,
621 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
622 chip->card->number);
623 hda->irq_pending_warned = 1;
624 }
625
626 for (;;) {
627 pending = 0;
628 spin_lock_irq(&bus->reg_lock);
629 list_for_each_entry(s, &bus->stream_list, list) {
630 struct azx_dev *azx_dev = stream_to_azx_dev(s);
631 if (!azx_dev->irq_pending ||
632 !s->substream ||
633 !s->running)
634 continue;
635 ok = azx_position_ok(chip, azx_dev);
636 if (ok > 0) {
637 azx_dev->irq_pending = 0;
638 spin_unlock(&bus->reg_lock);
639 snd_pcm_period_elapsed(s->substream);
640 spin_lock(&bus->reg_lock);
641 } else if (ok < 0) {
642 pending = 0; /* too early */
643 } else
644 pending++;
645 }
646 spin_unlock_irq(&bus->reg_lock);
647 if (!pending)
648 return;
649 msleep(1);
650 }
651 }
652
653 /* clear irq_pending flags and assure no on-going workq */
654 static void azx_clear_irq_pending(struct azx *chip)
655 {
656 struct hdac_bus *bus = azx_bus(chip);
657 struct hdac_stream *s;
658
659 spin_lock_irq(&bus->reg_lock);
660 list_for_each_entry(s, &bus->stream_list, list) {
661 struct azx_dev *azx_dev = stream_to_azx_dev(s);
662 azx_dev->irq_pending = 0;
663 }
664 spin_unlock_irq(&bus->reg_lock);
665 }
666
667 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
668 {
669 struct hdac_bus *bus = azx_bus(chip);
670
671 if (request_irq(chip->pci->irq, azx_interrupt,
672 chip->msi ? 0 : IRQF_SHARED,
673 KBUILD_MODNAME, chip)) {
674 dev_err(chip->card->dev,
675 "unable to grab IRQ %d, disabling device\n",
676 chip->pci->irq);
677 if (do_disconnect)
678 snd_card_disconnect(chip->card);
679 return -1;
680 }
681 bus->irq = chip->pci->irq;
682 pci_intx(chip->pci, !chip->msi);
683 return 0;
684 }
685
686 /* get the current DMA position with correction on VIA chips */
687 static unsigned int azx_via_get_position(struct azx *chip,
688 struct azx_dev *azx_dev)
689 {
690 unsigned int link_pos, mini_pos, bound_pos;
691 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
692 unsigned int fifo_size;
693
694 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
695 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
696 /* Playback, no problem using link position */
697 return link_pos;
698 }
699
700 /* Capture */
701 /* For new chipset,
702 * use mod to get the DMA position just like old chipset
703 */
704 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
705 mod_dma_pos %= azx_dev->core.period_bytes;
706
707 /* azx_dev->fifo_size can't get FIFO size of in stream.
708 * Get from base address + offset.
709 */
710 fifo_size = readw(azx_bus(chip)->remap_addr +
711 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
712
713 if (azx_dev->insufficient) {
714 /* Link position never gather than FIFO size */
715 if (link_pos <= fifo_size)
716 return 0;
717
718 azx_dev->insufficient = 0;
719 }
720
721 if (link_pos <= fifo_size)
722 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
723 else
724 mini_pos = link_pos - fifo_size;
725
726 /* Find nearest previous boudary */
727 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
728 mod_link_pos = link_pos % azx_dev->core.period_bytes;
729 if (mod_link_pos >= fifo_size)
730 bound_pos = link_pos - mod_link_pos;
731 else if (mod_dma_pos >= mod_mini_pos)
732 bound_pos = mini_pos - mod_mini_pos;
733 else {
734 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
735 if (bound_pos >= azx_dev->core.bufsize)
736 bound_pos = 0;
737 }
738
739 /* Calculate real DMA position we want */
740 return bound_pos + mod_dma_pos;
741 }
742
743 #ifdef CONFIG_PM
744 static DEFINE_MUTEX(card_list_lock);
745 static LIST_HEAD(card_list);
746
747 static void azx_add_card_list(struct azx *chip)
748 {
749 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
750 mutex_lock(&card_list_lock);
751 list_add(&hda->list, &card_list);
752 mutex_unlock(&card_list_lock);
753 }
754
755 static void azx_del_card_list(struct azx *chip)
756 {
757 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
758 mutex_lock(&card_list_lock);
759 list_del_init(&hda->list);
760 mutex_unlock(&card_list_lock);
761 }
762
763 /* trigger power-save check at writing parameter */
764 static int param_set_xint(const char *val, const struct kernel_param *kp)
765 {
766 struct hda_intel *hda;
767 struct azx *chip;
768 int prev = power_save;
769 int ret = param_set_int(val, kp);
770
771 if (ret || prev == power_save)
772 return ret;
773
774 mutex_lock(&card_list_lock);
775 list_for_each_entry(hda, &card_list, list) {
776 chip = &hda->chip;
777 if (!hda->probe_continued || chip->disabled)
778 continue;
779 snd_hda_set_power_save(&chip->bus, power_save * 1000);
780 }
781 mutex_unlock(&card_list_lock);
782 return 0;
783 }
784 #else
785 #define azx_add_card_list(chip) /* NOP */
786 #define azx_del_card_list(chip) /* NOP */
787 #endif /* CONFIG_PM */
788
789 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
790 /*
791 * power management
792 */
793 static int azx_suspend(struct device *dev)
794 {
795 struct snd_card *card = dev_get_drvdata(dev);
796 struct azx *chip;
797 struct hda_intel *hda;
798 struct hdac_bus *bus;
799
800 if (!card)
801 return 0;
802
803 chip = card->private_data;
804 hda = container_of(chip, struct hda_intel, chip);
805 if (chip->disabled || hda->init_failed)
806 return 0;
807
808 bus = azx_bus(chip);
809 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
810 azx_clear_irq_pending(chip);
811 azx_stop_chip(chip);
812 azx_enter_link_reset(chip);
813 if (bus->irq >= 0) {
814 free_irq(bus->irq, chip);
815 bus->irq = -1;
816 }
817
818 if (chip->msi)
819 pci_disable_msi(chip->pci);
820 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
821 && hda->need_i915_power)
822 hda_display_power(hda, false);
823 return 0;
824 }
825
826 static int azx_resume(struct device *dev)
827 {
828 struct pci_dev *pci = to_pci_dev(dev);
829 struct snd_card *card = dev_get_drvdata(dev);
830 struct azx *chip;
831 struct hda_intel *hda;
832
833 if (!card)
834 return 0;
835
836 chip = card->private_data;
837 hda = container_of(chip, struct hda_intel, chip);
838 if (chip->disabled || hda->init_failed)
839 return 0;
840
841 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
842 && hda->need_i915_power) {
843 hda_display_power(hda, true);
844 haswell_set_bclk(hda);
845 }
846 if (chip->msi)
847 if (pci_enable_msi(pci) < 0)
848 chip->msi = 0;
849 if (azx_acquire_irq(chip, 1) < 0)
850 return -EIO;
851 azx_init_pci(chip);
852
853 azx_init_chip(chip, true);
854
855 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
856 return 0;
857 }
858 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
859
860 #ifdef CONFIG_PM
861 static int azx_runtime_suspend(struct device *dev)
862 {
863 struct snd_card *card = dev_get_drvdata(dev);
864 struct azx *chip;
865 struct hda_intel *hda;
866
867 if (!card)
868 return 0;
869
870 chip = card->private_data;
871 hda = container_of(chip, struct hda_intel, chip);
872 if (chip->disabled || hda->init_failed)
873 return 0;
874
875 if (!azx_has_pm_runtime(chip))
876 return 0;
877
878 /* enable controller wake up event */
879 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
880 STATESTS_INT_MASK);
881
882 azx_stop_chip(chip);
883 azx_enter_link_reset(chip);
884 azx_clear_irq_pending(chip);
885 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
886 && hda->need_i915_power)
887 hda_display_power(hda, false);
888
889 return 0;
890 }
891
892 static int azx_runtime_resume(struct device *dev)
893 {
894 struct snd_card *card = dev_get_drvdata(dev);
895 struct azx *chip;
896 struct hda_intel *hda;
897 struct hda_codec *codec;
898 int status;
899
900 if (!card)
901 return 0;
902
903 chip = card->private_data;
904 hda = container_of(chip, struct hda_intel, chip);
905 if (chip->disabled || hda->init_failed)
906 return 0;
907
908 if (!azx_has_pm_runtime(chip))
909 return 0;
910
911 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
912 && hda->need_i915_power) {
913 hda_display_power(hda, true);
914 haswell_set_bclk(hda);
915 }
916
917 /* Read STATESTS before controller reset */
918 status = azx_readw(chip, STATESTS);
919
920 azx_init_pci(chip);
921 azx_init_chip(chip, true);
922
923 if (status) {
924 list_for_each_codec(codec, &chip->bus)
925 if (status & (1 << codec->addr))
926 schedule_delayed_work(&codec->jackpoll_work,
927 codec->jackpoll_interval);
928 }
929
930 /* disable controller Wake Up event*/
931 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
932 ~STATESTS_INT_MASK);
933
934 return 0;
935 }
936
937 static int azx_runtime_idle(struct device *dev)
938 {
939 struct snd_card *card = dev_get_drvdata(dev);
940 struct azx *chip;
941 struct hda_intel *hda;
942
943 if (!card)
944 return 0;
945
946 chip = card->private_data;
947 hda = container_of(chip, struct hda_intel, chip);
948 if (chip->disabled || hda->init_failed)
949 return 0;
950
951 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
952 azx_bus(chip)->codec_powered)
953 return -EBUSY;
954
955 return 0;
956 }
957
958 static const struct dev_pm_ops azx_pm = {
959 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
960 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
961 };
962
963 #define AZX_PM_OPS &azx_pm
964 #else
965 #define AZX_PM_OPS NULL
966 #endif /* CONFIG_PM */
967
968
969 static int azx_probe_continue(struct azx *chip);
970
971 #ifdef SUPPORT_VGA_SWITCHEROO
972 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
973
974 static void azx_vs_set_state(struct pci_dev *pci,
975 enum vga_switcheroo_state state)
976 {
977 struct snd_card *card = pci_get_drvdata(pci);
978 struct azx *chip = card->private_data;
979 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
980 bool disabled;
981
982 wait_for_completion(&hda->probe_wait);
983 if (hda->init_failed)
984 return;
985
986 disabled = (state == VGA_SWITCHEROO_OFF);
987 if (chip->disabled == disabled)
988 return;
989
990 if (!hda->probe_continued) {
991 chip->disabled = disabled;
992 if (!disabled) {
993 dev_info(chip->card->dev,
994 "Start delayed initialization\n");
995 if (azx_probe_continue(chip) < 0) {
996 dev_err(chip->card->dev, "initialization error\n");
997 hda->init_failed = true;
998 }
999 }
1000 } else {
1001 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1002 disabled ? "Disabling" : "Enabling");
1003 if (disabled) {
1004 pm_runtime_put_sync_suspend(card->dev);
1005 azx_suspend(card->dev);
1006 /* when we get suspended by vga switcheroo we end up in D3cold,
1007 * however we have no ACPI handle, so pci/acpi can't put us there,
1008 * put ourselves there */
1009 pci->current_state = PCI_D3cold;
1010 chip->disabled = true;
1011 if (snd_hda_lock_devices(&chip->bus))
1012 dev_warn(chip->card->dev,
1013 "Cannot lock devices!\n");
1014 } else {
1015 snd_hda_unlock_devices(&chip->bus);
1016 pm_runtime_get_noresume(card->dev);
1017 chip->disabled = false;
1018 azx_resume(card->dev);
1019 }
1020 }
1021 }
1022
1023 static bool azx_vs_can_switch(struct pci_dev *pci)
1024 {
1025 struct snd_card *card = pci_get_drvdata(pci);
1026 struct azx *chip = card->private_data;
1027 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1028
1029 wait_for_completion(&hda->probe_wait);
1030 if (hda->init_failed)
1031 return false;
1032 if (chip->disabled || !hda->probe_continued)
1033 return true;
1034 if (snd_hda_lock_devices(&chip->bus))
1035 return false;
1036 snd_hda_unlock_devices(&chip->bus);
1037 return true;
1038 }
1039
1040 static void init_vga_switcheroo(struct azx *chip)
1041 {
1042 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1043 struct pci_dev *p = get_bound_vga(chip->pci);
1044 if (p) {
1045 dev_info(chip->card->dev,
1046 "Handle VGA-switcheroo audio client\n");
1047 hda->use_vga_switcheroo = 1;
1048 pci_dev_put(p);
1049 }
1050 }
1051
1052 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1053 .set_gpu_state = azx_vs_set_state,
1054 .can_switch = azx_vs_can_switch,
1055 };
1056
1057 static int register_vga_switcheroo(struct azx *chip)
1058 {
1059 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1060 int err;
1061
1062 if (!hda->use_vga_switcheroo)
1063 return 0;
1064 /* FIXME: currently only handling DIS controller
1065 * is there any machine with two switchable HDMI audio controllers?
1066 */
1067 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1068 VGA_SWITCHEROO_DIS,
1069 hda->probe_continued);
1070 if (err < 0)
1071 return err;
1072 hda->vga_switcheroo_registered = 1;
1073
1074 /* register as an optimus hdmi audio power domain */
1075 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1076 &hda->hdmi_pm_domain);
1077 return 0;
1078 }
1079 #else
1080 #define init_vga_switcheroo(chip) /* NOP */
1081 #define register_vga_switcheroo(chip) 0
1082 #define check_hdmi_disabled(pci) false
1083 #endif /* SUPPORT_VGA_SWITCHER */
1084
1085 /*
1086 * destructor
1087 */
1088 static int azx_free(struct azx *chip)
1089 {
1090 struct pci_dev *pci = chip->pci;
1091 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1092 struct hdac_bus *bus = azx_bus(chip);
1093
1094 if (azx_has_pm_runtime(chip) && chip->running)
1095 pm_runtime_get_noresume(&pci->dev);
1096
1097 azx_del_card_list(chip);
1098
1099 hda->init_failed = 1; /* to be sure */
1100 complete_all(&hda->probe_wait);
1101
1102 if (use_vga_switcheroo(hda)) {
1103 if (chip->disabled && hda->probe_continued)
1104 snd_hda_unlock_devices(&chip->bus);
1105 if (hda->vga_switcheroo_registered)
1106 vga_switcheroo_unregister_client(chip->pci);
1107 }
1108
1109 if (bus->chip_init) {
1110 azx_clear_irq_pending(chip);
1111 azx_stop_all_streams(chip);
1112 azx_stop_chip(chip);
1113 }
1114
1115 if (bus->irq >= 0)
1116 free_irq(bus->irq, (void*)chip);
1117 if (chip->msi)
1118 pci_disable_msi(chip->pci);
1119 iounmap(bus->remap_addr);
1120
1121 azx_free_stream_pages(chip);
1122 azx_free_streams(chip);
1123 snd_hdac_bus_exit(bus);
1124
1125 if (chip->region_requested)
1126 pci_release_regions(chip->pci);
1127
1128 pci_disable_device(chip->pci);
1129 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1130 release_firmware(chip->fw);
1131 #endif
1132 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1133 if (hda->need_i915_power)
1134 hda_display_power(hda, false);
1135 hda_i915_exit(hda);
1136 }
1137 kfree(hda);
1138
1139 return 0;
1140 }
1141
1142 static int azx_dev_disconnect(struct snd_device *device)
1143 {
1144 struct azx *chip = device->device_data;
1145
1146 chip->bus.shutdown = 1;
1147 return 0;
1148 }
1149
1150 static int azx_dev_free(struct snd_device *device)
1151 {
1152 return azx_free(device->device_data);
1153 }
1154
1155 #ifdef SUPPORT_VGA_SWITCHEROO
1156 /*
1157 * Check of disabled HDMI controller by vga-switcheroo
1158 */
1159 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1160 {
1161 struct pci_dev *p;
1162
1163 /* check only discrete GPU */
1164 switch (pci->vendor) {
1165 case PCI_VENDOR_ID_ATI:
1166 case PCI_VENDOR_ID_AMD:
1167 case PCI_VENDOR_ID_NVIDIA:
1168 if (pci->devfn == 1) {
1169 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1170 pci->bus->number, 0);
1171 if (p) {
1172 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1173 return p;
1174 pci_dev_put(p);
1175 }
1176 }
1177 break;
1178 }
1179 return NULL;
1180 }
1181
1182 static bool check_hdmi_disabled(struct pci_dev *pci)
1183 {
1184 bool vga_inactive = false;
1185 struct pci_dev *p = get_bound_vga(pci);
1186
1187 if (p) {
1188 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1189 vga_inactive = true;
1190 pci_dev_put(p);
1191 }
1192 return vga_inactive;
1193 }
1194 #endif /* SUPPORT_VGA_SWITCHEROO */
1195
1196 /*
1197 * white/black-listing for position_fix
1198 */
1199 static struct snd_pci_quirk position_fix_list[] = {
1200 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1201 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1202 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1203 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1204 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1205 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1206 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1207 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1208 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1209 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1210 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1211 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1212 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1213 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1214 {}
1215 };
1216
1217 static int check_position_fix(struct azx *chip, int fix)
1218 {
1219 const struct snd_pci_quirk *q;
1220
1221 switch (fix) {
1222 case POS_FIX_AUTO:
1223 case POS_FIX_LPIB:
1224 case POS_FIX_POSBUF:
1225 case POS_FIX_VIACOMBO:
1226 case POS_FIX_COMBO:
1227 return fix;
1228 }
1229
1230 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1231 if (q) {
1232 dev_info(chip->card->dev,
1233 "position_fix set to %d for device %04x:%04x\n",
1234 q->value, q->subvendor, q->subdevice);
1235 return q->value;
1236 }
1237
1238 /* Check VIA/ATI HD Audio Controller exist */
1239 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1240 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1241 return POS_FIX_VIACOMBO;
1242 }
1243 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1244 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1245 return POS_FIX_LPIB;
1246 }
1247 return POS_FIX_AUTO;
1248 }
1249
1250 static void assign_position_fix(struct azx *chip, int fix)
1251 {
1252 static azx_get_pos_callback_t callbacks[] = {
1253 [POS_FIX_AUTO] = NULL,
1254 [POS_FIX_LPIB] = azx_get_pos_lpib,
1255 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1256 [POS_FIX_VIACOMBO] = azx_via_get_position,
1257 [POS_FIX_COMBO] = azx_get_pos_lpib,
1258 };
1259
1260 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1261
1262 /* combo mode uses LPIB only for playback */
1263 if (fix == POS_FIX_COMBO)
1264 chip->get_position[1] = NULL;
1265
1266 if (fix == POS_FIX_POSBUF &&
1267 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1268 chip->get_delay[0] = chip->get_delay[1] =
1269 azx_get_delay_from_lpib;
1270 }
1271
1272 }
1273
1274 /*
1275 * black-lists for probe_mask
1276 */
1277 static struct snd_pci_quirk probe_mask_list[] = {
1278 /* Thinkpad often breaks the controller communication when accessing
1279 * to the non-working (or non-existing) modem codec slot.
1280 */
1281 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1282 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1283 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1284 /* broken BIOS */
1285 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1286 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1287 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1288 /* forced codec slots */
1289 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1290 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1291 /* WinFast VP200 H (Teradici) user reported broken communication */
1292 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1293 {}
1294 };
1295
1296 #define AZX_FORCE_CODEC_MASK 0x100
1297
1298 static void check_probe_mask(struct azx *chip, int dev)
1299 {
1300 const struct snd_pci_quirk *q;
1301
1302 chip->codec_probe_mask = probe_mask[dev];
1303 if (chip->codec_probe_mask == -1) {
1304 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1305 if (q) {
1306 dev_info(chip->card->dev,
1307 "probe_mask set to 0x%x for device %04x:%04x\n",
1308 q->value, q->subvendor, q->subdevice);
1309 chip->codec_probe_mask = q->value;
1310 }
1311 }
1312
1313 /* check forced option */
1314 if (chip->codec_probe_mask != -1 &&
1315 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1316 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1317 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1318 (int)azx_bus(chip)->codec_mask);
1319 }
1320 }
1321
1322 /*
1323 * white/black-list for enable_msi
1324 */
1325 static struct snd_pci_quirk msi_black_list[] = {
1326 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1327 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1328 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1329 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1330 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1331 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1332 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1333 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1334 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1335 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1336 {}
1337 };
1338
1339 static void check_msi(struct azx *chip)
1340 {
1341 const struct snd_pci_quirk *q;
1342
1343 if (enable_msi >= 0) {
1344 chip->msi = !!enable_msi;
1345 return;
1346 }
1347 chip->msi = 1; /* enable MSI as default */
1348 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1349 if (q) {
1350 dev_info(chip->card->dev,
1351 "msi for device %04x:%04x set to %d\n",
1352 q->subvendor, q->subdevice, q->value);
1353 chip->msi = q->value;
1354 return;
1355 }
1356
1357 /* NVidia chipsets seem to cause troubles with MSI */
1358 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1359 dev_info(chip->card->dev, "Disabling MSI\n");
1360 chip->msi = 0;
1361 }
1362 }
1363
1364 /* check the snoop mode availability */
1365 static void azx_check_snoop_available(struct azx *chip)
1366 {
1367 int snoop = hda_snoop;
1368
1369 if (snoop >= 0) {
1370 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1371 snoop ? "snoop" : "non-snoop");
1372 chip->snoop = snoop;
1373 return;
1374 }
1375
1376 snoop = true;
1377 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1378 chip->driver_type == AZX_DRIVER_VIA) {
1379 /* force to non-snoop mode for a new VIA controller
1380 * when BIOS is set
1381 */
1382 u8 val;
1383 pci_read_config_byte(chip->pci, 0x42, &val);
1384 if (!(val & 0x80) && chip->pci->revision == 0x30)
1385 snoop = false;
1386 }
1387
1388 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1389 snoop = false;
1390
1391 chip->snoop = snoop;
1392 if (!snoop)
1393 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1394 }
1395
1396 static void azx_probe_work(struct work_struct *work)
1397 {
1398 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1399 azx_probe_continue(&hda->chip);
1400 }
1401
1402 /*
1403 * constructor
1404 */
1405 static const struct hdac_io_ops pci_hda_io_ops;
1406 static const struct hda_controller_ops pci_hda_ops;
1407
1408 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1409 int dev, unsigned int driver_caps,
1410 struct azx **rchip)
1411 {
1412 static struct snd_device_ops ops = {
1413 .dev_disconnect = azx_dev_disconnect,
1414 .dev_free = azx_dev_free,
1415 };
1416 struct hda_intel *hda;
1417 struct azx *chip;
1418 int err;
1419
1420 *rchip = NULL;
1421
1422 err = pci_enable_device(pci);
1423 if (err < 0)
1424 return err;
1425
1426 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1427 if (!hda) {
1428 pci_disable_device(pci);
1429 return -ENOMEM;
1430 }
1431
1432 chip = &hda->chip;
1433 mutex_init(&chip->open_mutex);
1434 chip->card = card;
1435 chip->pci = pci;
1436 chip->ops = &pci_hda_ops;
1437 chip->driver_caps = driver_caps;
1438 chip->driver_type = driver_caps & 0xff;
1439 check_msi(chip);
1440 chip->dev_index = dev;
1441 chip->jackpoll_ms = jackpoll_ms;
1442 INIT_LIST_HEAD(&chip->pcm_list);
1443 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1444 INIT_LIST_HEAD(&hda->list);
1445 init_vga_switcheroo(chip);
1446 init_completion(&hda->probe_wait);
1447
1448 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1449
1450 check_probe_mask(chip, dev);
1451
1452 chip->single_cmd = single_cmd;
1453 azx_check_snoop_available(chip);
1454
1455 if (bdl_pos_adj[dev] < 0) {
1456 switch (chip->driver_type) {
1457 case AZX_DRIVER_ICH:
1458 case AZX_DRIVER_PCH:
1459 bdl_pos_adj[dev] = 1;
1460 break;
1461 default:
1462 bdl_pos_adj[dev] = 32;
1463 break;
1464 }
1465 }
1466 chip->bdl_pos_adj = bdl_pos_adj;
1467
1468 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1469 if (err < 0) {
1470 kfree(hda);
1471 pci_disable_device(pci);
1472 return err;
1473 }
1474
1475 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1476 if (err < 0) {
1477 dev_err(card->dev, "Error creating device [card]!\n");
1478 azx_free(chip);
1479 return err;
1480 }
1481
1482 /* continue probing in work context as may trigger request module */
1483 INIT_WORK(&hda->probe_work, azx_probe_work);
1484
1485 *rchip = chip;
1486
1487 return 0;
1488 }
1489
1490 static int azx_first_init(struct azx *chip)
1491 {
1492 int dev = chip->dev_index;
1493 struct pci_dev *pci = chip->pci;
1494 struct snd_card *card = chip->card;
1495 struct hdac_bus *bus = azx_bus(chip);
1496 int err;
1497 unsigned short gcap;
1498 unsigned int dma_bits = 64;
1499
1500 #if BITS_PER_LONG != 64
1501 /* Fix up base address on ULI M5461 */
1502 if (chip->driver_type == AZX_DRIVER_ULI) {
1503 u16 tmp3;
1504 pci_read_config_word(pci, 0x40, &tmp3);
1505 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1506 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1507 }
1508 #endif
1509
1510 err = pci_request_regions(pci, "ICH HD audio");
1511 if (err < 0)
1512 return err;
1513 chip->region_requested = 1;
1514
1515 bus->addr = pci_resource_start(pci, 0);
1516 bus->remap_addr = pci_ioremap_bar(pci, 0);
1517 if (bus->remap_addr == NULL) {
1518 dev_err(card->dev, "ioremap error\n");
1519 return -ENXIO;
1520 }
1521
1522 if (chip->msi) {
1523 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1524 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1525 pci->no_64bit_msi = true;
1526 }
1527 if (pci_enable_msi(pci) < 0)
1528 chip->msi = 0;
1529 }
1530
1531 if (azx_acquire_irq(chip, 0) < 0)
1532 return -EBUSY;
1533
1534 pci_set_master(pci);
1535 synchronize_irq(bus->irq);
1536
1537 gcap = azx_readw(chip, GCAP);
1538 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1539
1540 /* AMD devices support 40 or 48bit DMA, take the safe one */
1541 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1542 dma_bits = 40;
1543
1544 /* disable SB600 64bit support for safety */
1545 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1546 struct pci_dev *p_smbus;
1547 dma_bits = 40;
1548 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1549 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1550 NULL);
1551 if (p_smbus) {
1552 if (p_smbus->revision < 0x30)
1553 gcap &= ~AZX_GCAP_64OK;
1554 pci_dev_put(p_smbus);
1555 }
1556 }
1557
1558 /* disable 64bit DMA address on some devices */
1559 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1560 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1561 gcap &= ~AZX_GCAP_64OK;
1562 }
1563
1564 /* disable buffer size rounding to 128-byte multiples if supported */
1565 if (align_buffer_size >= 0)
1566 chip->align_buffer_size = !!align_buffer_size;
1567 else {
1568 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1569 chip->align_buffer_size = 0;
1570 else
1571 chip->align_buffer_size = 1;
1572 }
1573
1574 /* allow 64bit DMA address if supported by H/W */
1575 if (!(gcap & AZX_GCAP_64OK))
1576 dma_bits = 32;
1577 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1578 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1579 } else {
1580 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1581 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1582 }
1583
1584 /* read number of streams from GCAP register instead of using
1585 * hardcoded value
1586 */
1587 chip->capture_streams = (gcap >> 8) & 0x0f;
1588 chip->playback_streams = (gcap >> 12) & 0x0f;
1589 if (!chip->playback_streams && !chip->capture_streams) {
1590 /* gcap didn't give any info, switching to old method */
1591
1592 switch (chip->driver_type) {
1593 case AZX_DRIVER_ULI:
1594 chip->playback_streams = ULI_NUM_PLAYBACK;
1595 chip->capture_streams = ULI_NUM_CAPTURE;
1596 break;
1597 case AZX_DRIVER_ATIHDMI:
1598 case AZX_DRIVER_ATIHDMI_NS:
1599 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1600 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1601 break;
1602 case AZX_DRIVER_GENERIC:
1603 default:
1604 chip->playback_streams = ICH6_NUM_PLAYBACK;
1605 chip->capture_streams = ICH6_NUM_CAPTURE;
1606 break;
1607 }
1608 }
1609 chip->capture_index_offset = 0;
1610 chip->playback_index_offset = chip->capture_streams;
1611 chip->num_streams = chip->playback_streams + chip->capture_streams;
1612
1613 /* initialize streams */
1614 err = azx_init_streams(chip);
1615 if (err < 0)
1616 return err;
1617
1618 err = azx_alloc_stream_pages(chip);
1619 if (err < 0)
1620 return err;
1621
1622 /* initialize chip */
1623 azx_init_pci(chip);
1624
1625 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1626 struct hda_intel *hda;
1627
1628 hda = container_of(chip, struct hda_intel, chip);
1629 haswell_set_bclk(hda);
1630 }
1631
1632 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1633
1634 /* codec detection */
1635 if (!azx_bus(chip)->codec_mask) {
1636 dev_err(card->dev, "no codecs found!\n");
1637 return -ENODEV;
1638 }
1639
1640 strcpy(card->driver, "HDA-Intel");
1641 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1642 sizeof(card->shortname));
1643 snprintf(card->longname, sizeof(card->longname),
1644 "%s at 0x%lx irq %i",
1645 card->shortname, bus->addr, bus->irq);
1646
1647 return 0;
1648 }
1649
1650 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1651 /* callback from request_firmware_nowait() */
1652 static void azx_firmware_cb(const struct firmware *fw, void *context)
1653 {
1654 struct snd_card *card = context;
1655 struct azx *chip = card->private_data;
1656 struct pci_dev *pci = chip->pci;
1657
1658 if (!fw) {
1659 dev_err(card->dev, "Cannot load firmware, aborting\n");
1660 goto error;
1661 }
1662
1663 chip->fw = fw;
1664 if (!chip->disabled) {
1665 /* continue probing */
1666 if (azx_probe_continue(chip))
1667 goto error;
1668 }
1669 return; /* OK */
1670
1671 error:
1672 snd_card_free(card);
1673 pci_set_drvdata(pci, NULL);
1674 }
1675 #endif
1676
1677 /*
1678 * HDA controller ops.
1679 */
1680
1681 /* PCI register access. */
1682 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1683 {
1684 writel(value, addr);
1685 }
1686
1687 static u32 pci_azx_readl(u32 __iomem *addr)
1688 {
1689 return readl(addr);
1690 }
1691
1692 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1693 {
1694 writew(value, addr);
1695 }
1696
1697 static u16 pci_azx_readw(u16 __iomem *addr)
1698 {
1699 return readw(addr);
1700 }
1701
1702 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1703 {
1704 writeb(value, addr);
1705 }
1706
1707 static u8 pci_azx_readb(u8 __iomem *addr)
1708 {
1709 return readb(addr);
1710 }
1711
1712 static int disable_msi_reset_irq(struct azx *chip)
1713 {
1714 struct hdac_bus *bus = azx_bus(chip);
1715 int err;
1716
1717 free_irq(bus->irq, chip);
1718 bus->irq = -1;
1719 pci_disable_msi(chip->pci);
1720 chip->msi = 0;
1721 err = azx_acquire_irq(chip, 1);
1722 if (err < 0)
1723 return err;
1724
1725 return 0;
1726 }
1727
1728 /* DMA page allocation helpers. */
1729 static int dma_alloc_pages(struct hdac_bus *bus,
1730 int type,
1731 size_t size,
1732 struct snd_dma_buffer *buf)
1733 {
1734 struct azx *chip = bus_to_azx(bus);
1735 int err;
1736
1737 err = snd_dma_alloc_pages(type,
1738 bus->dev,
1739 size, buf);
1740 if (err < 0)
1741 return err;
1742 mark_pages_wc(chip, buf, true);
1743 return 0;
1744 }
1745
1746 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1747 {
1748 struct azx *chip = bus_to_azx(bus);
1749
1750 mark_pages_wc(chip, buf, false);
1751 snd_dma_free_pages(buf);
1752 }
1753
1754 static int substream_alloc_pages(struct azx *chip,
1755 struct snd_pcm_substream *substream,
1756 size_t size)
1757 {
1758 struct azx_dev *azx_dev = get_azx_dev(substream);
1759 int ret;
1760
1761 mark_runtime_wc(chip, azx_dev, substream, false);
1762 ret = snd_pcm_lib_malloc_pages(substream, size);
1763 if (ret < 0)
1764 return ret;
1765 mark_runtime_wc(chip, azx_dev, substream, true);
1766 return 0;
1767 }
1768
1769 static int substream_free_pages(struct azx *chip,
1770 struct snd_pcm_substream *substream)
1771 {
1772 struct azx_dev *azx_dev = get_azx_dev(substream);
1773 mark_runtime_wc(chip, azx_dev, substream, false);
1774 return snd_pcm_lib_free_pages(substream);
1775 }
1776
1777 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1778 struct vm_area_struct *area)
1779 {
1780 #ifdef CONFIG_X86
1781 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1782 struct azx *chip = apcm->chip;
1783 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1784 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1785 #endif
1786 }
1787
1788 static const struct hdac_io_ops pci_hda_io_ops = {
1789 .reg_writel = pci_azx_writel,
1790 .reg_readl = pci_azx_readl,
1791 .reg_writew = pci_azx_writew,
1792 .reg_readw = pci_azx_readw,
1793 .reg_writeb = pci_azx_writeb,
1794 .reg_readb = pci_azx_readb,
1795 .dma_alloc_pages = dma_alloc_pages,
1796 .dma_free_pages = dma_free_pages,
1797 };
1798
1799 static const struct hda_controller_ops pci_hda_ops = {
1800 .disable_msi_reset_irq = disable_msi_reset_irq,
1801 .substream_alloc_pages = substream_alloc_pages,
1802 .substream_free_pages = substream_free_pages,
1803 .pcm_mmap_prepare = pcm_mmap_prepare,
1804 .position_check = azx_position_check,
1805 .link_power = azx_intel_link_power,
1806 };
1807
1808 static int azx_probe(struct pci_dev *pci,
1809 const struct pci_device_id *pci_id)
1810 {
1811 static int dev;
1812 struct snd_card *card;
1813 struct hda_intel *hda;
1814 struct azx *chip;
1815 bool schedule_probe;
1816 int err;
1817
1818 if (dev >= SNDRV_CARDS)
1819 return -ENODEV;
1820 if (!enable[dev]) {
1821 dev++;
1822 return -ENOENT;
1823 }
1824
1825 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1826 0, &card);
1827 if (err < 0) {
1828 dev_err(&pci->dev, "Error creating card!\n");
1829 return err;
1830 }
1831
1832 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1833 if (err < 0)
1834 goto out_free;
1835 card->private_data = chip;
1836 hda = container_of(chip, struct hda_intel, chip);
1837
1838 pci_set_drvdata(pci, card);
1839
1840 err = register_vga_switcheroo(chip);
1841 if (err < 0) {
1842 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
1843 goto out_free;
1844 }
1845
1846 if (check_hdmi_disabled(pci)) {
1847 dev_info(card->dev, "VGA controller is disabled\n");
1848 dev_info(card->dev, "Delaying initialization\n");
1849 chip->disabled = true;
1850 }
1851
1852 schedule_probe = !chip->disabled;
1853
1854 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1855 if (patch[dev] && *patch[dev]) {
1856 dev_info(card->dev, "Applying patch firmware '%s'\n",
1857 patch[dev]);
1858 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1859 &pci->dev, GFP_KERNEL, card,
1860 azx_firmware_cb);
1861 if (err < 0)
1862 goto out_free;
1863 schedule_probe = false; /* continued in azx_firmware_cb() */
1864 }
1865 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1866
1867 #ifndef CONFIG_SND_HDA_I915
1868 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1869 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1870 #endif
1871
1872 if (schedule_probe)
1873 schedule_work(&hda->probe_work);
1874
1875 dev++;
1876 if (chip->disabled)
1877 complete_all(&hda->probe_wait);
1878 return 0;
1879
1880 out_free:
1881 snd_card_free(card);
1882 return err;
1883 }
1884
1885 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1886 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1887 [AZX_DRIVER_NVIDIA] = 8,
1888 [AZX_DRIVER_TERA] = 1,
1889 };
1890
1891 static int azx_probe_continue(struct azx *chip)
1892 {
1893 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1894 struct pci_dev *pci = chip->pci;
1895 int dev = chip->dev_index;
1896 int err;
1897
1898 hda->probe_continued = 1;
1899
1900 /* Request display power well for the HDA controller or codec. For
1901 * Haswell/Broadwell, both the display HDA controller and codec need
1902 * this power. For other platforms, like Baytrail/Braswell, only the
1903 * display codec needs the power and it can be released after probe.
1904 */
1905 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1906 /* Baytral/Braswell controllers don't need this power */
1907 if (pci->device != 0x0f04 && pci->device != 0x2284)
1908 hda->need_i915_power = 1;
1909
1910
1911 #ifdef CONFIG_SND_HDA_I915
1912 err = hda_i915_init(hda);
1913 if (err < 0)
1914 goto i915_power_fail;
1915
1916 err = hda_display_power(hda, true);
1917 if (err < 0) {
1918 dev_err(chip->card->dev,
1919 "Cannot turn on display power on i915\n");
1920 goto i915_power_fail;
1921 }
1922 #endif
1923 }
1924
1925 err = azx_first_init(chip);
1926 if (err < 0)
1927 goto out_free;
1928
1929 #ifdef CONFIG_SND_HDA_INPUT_BEEP
1930 chip->beep_mode = beep_mode[dev];
1931 #endif
1932
1933 /* create codec instances */
1934 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
1935 if (err < 0)
1936 goto out_free;
1937
1938 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1939 if (chip->fw) {
1940 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
1941 chip->fw->data);
1942 if (err < 0)
1943 goto out_free;
1944 #ifndef CONFIG_PM
1945 release_firmware(chip->fw); /* no longer needed */
1946 chip->fw = NULL;
1947 #endif
1948 }
1949 #endif
1950 if ((probe_only[dev] & 1) == 0) {
1951 err = azx_codec_configure(chip);
1952 if (err < 0)
1953 goto out_free;
1954 }
1955
1956 err = snd_card_register(chip->card);
1957 if (err < 0)
1958 goto out_free;
1959
1960 chip->running = 1;
1961 azx_add_card_list(chip);
1962 snd_hda_set_power_save(&chip->bus, power_save * 1000);
1963 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
1964 pm_runtime_put_noidle(&pci->dev);
1965
1966 out_free:
1967 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1968 && !hda->need_i915_power)
1969 hda_display_power(hda, false);
1970
1971 i915_power_fail:
1972 if (err < 0)
1973 hda->init_failed = 1;
1974 complete_all(&hda->probe_wait);
1975 return err;
1976 }
1977
1978 static void azx_remove(struct pci_dev *pci)
1979 {
1980 struct snd_card *card = pci_get_drvdata(pci);
1981
1982 if (card)
1983 snd_card_free(card);
1984 }
1985
1986 static void azx_shutdown(struct pci_dev *pci)
1987 {
1988 struct snd_card *card = pci_get_drvdata(pci);
1989 struct azx *chip;
1990
1991 if (!card)
1992 return;
1993 chip = card->private_data;
1994 if (chip && chip->running)
1995 azx_stop_chip(chip);
1996 }
1997
1998 /* PCI IDs */
1999 static const struct pci_device_id azx_ids[] = {
2000 /* CPT */
2001 { PCI_DEVICE(0x8086, 0x1c20),
2002 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2003 /* PBG */
2004 { PCI_DEVICE(0x8086, 0x1d20),
2005 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2006 /* Panther Point */
2007 { PCI_DEVICE(0x8086, 0x1e20),
2008 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2009 /* Lynx Point */
2010 { PCI_DEVICE(0x8086, 0x8c20),
2011 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2012 /* 9 Series */
2013 { PCI_DEVICE(0x8086, 0x8ca0),
2014 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2015 /* Wellsburg */
2016 { PCI_DEVICE(0x8086, 0x8d20),
2017 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2018 { PCI_DEVICE(0x8086, 0x8d21),
2019 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2020 /* Lynx Point-LP */
2021 { PCI_DEVICE(0x8086, 0x9c20),
2022 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2023 /* Lynx Point-LP */
2024 { PCI_DEVICE(0x8086, 0x9c21),
2025 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2026 /* Wildcat Point-LP */
2027 { PCI_DEVICE(0x8086, 0x9ca0),
2028 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2029 /* Sunrise Point */
2030 { PCI_DEVICE(0x8086, 0xa170),
2031 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2032 /* Sunrise Point-LP */
2033 { PCI_DEVICE(0x8086, 0x9d70),
2034 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2035 /* Haswell */
2036 { PCI_DEVICE(0x8086, 0x0a0c),
2037 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2038 { PCI_DEVICE(0x8086, 0x0c0c),
2039 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2040 { PCI_DEVICE(0x8086, 0x0d0c),
2041 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2042 /* Broadwell */
2043 { PCI_DEVICE(0x8086, 0x160c),
2044 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2045 /* 5 Series/3400 */
2046 { PCI_DEVICE(0x8086, 0x3b56),
2047 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2048 /* Poulsbo */
2049 { PCI_DEVICE(0x8086, 0x811b),
2050 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2051 /* Oaktrail */
2052 { PCI_DEVICE(0x8086, 0x080a),
2053 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2054 /* BayTrail */
2055 { PCI_DEVICE(0x8086, 0x0f04),
2056 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2057 /* Braswell */
2058 { PCI_DEVICE(0x8086, 0x2284),
2059 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2060 /* ICH6 */
2061 { PCI_DEVICE(0x8086, 0x2668),
2062 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2063 /* ICH7 */
2064 { PCI_DEVICE(0x8086, 0x27d8),
2065 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2066 /* ESB2 */
2067 { PCI_DEVICE(0x8086, 0x269a),
2068 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2069 /* ICH8 */
2070 { PCI_DEVICE(0x8086, 0x284b),
2071 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2072 /* ICH9 */
2073 { PCI_DEVICE(0x8086, 0x293e),
2074 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2075 /* ICH9 */
2076 { PCI_DEVICE(0x8086, 0x293f),
2077 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2078 /* ICH10 */
2079 { PCI_DEVICE(0x8086, 0x3a3e),
2080 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2081 /* ICH10 */
2082 { PCI_DEVICE(0x8086, 0x3a6e),
2083 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2084 /* Generic Intel */
2085 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2086 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2087 .class_mask = 0xffffff,
2088 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2089 /* ATI SB 450/600/700/800/900 */
2090 { PCI_DEVICE(0x1002, 0x437b),
2091 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2092 { PCI_DEVICE(0x1002, 0x4383),
2093 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2094 /* AMD Hudson */
2095 { PCI_DEVICE(0x1022, 0x780d),
2096 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2097 /* ATI HDMI */
2098 { PCI_DEVICE(0x1002, 0x793b),
2099 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2100 { PCI_DEVICE(0x1002, 0x7919),
2101 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2102 { PCI_DEVICE(0x1002, 0x960f),
2103 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2104 { PCI_DEVICE(0x1002, 0x970f),
2105 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2106 { PCI_DEVICE(0x1002, 0xaa00),
2107 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2108 { PCI_DEVICE(0x1002, 0xaa08),
2109 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2110 { PCI_DEVICE(0x1002, 0xaa10),
2111 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2112 { PCI_DEVICE(0x1002, 0xaa18),
2113 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2114 { PCI_DEVICE(0x1002, 0xaa20),
2115 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2116 { PCI_DEVICE(0x1002, 0xaa28),
2117 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2118 { PCI_DEVICE(0x1002, 0xaa30),
2119 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2120 { PCI_DEVICE(0x1002, 0xaa38),
2121 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2122 { PCI_DEVICE(0x1002, 0xaa40),
2123 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2124 { PCI_DEVICE(0x1002, 0xaa48),
2125 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2126 { PCI_DEVICE(0x1002, 0xaa50),
2127 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2128 { PCI_DEVICE(0x1002, 0xaa58),
2129 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2130 { PCI_DEVICE(0x1002, 0xaa60),
2131 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2132 { PCI_DEVICE(0x1002, 0xaa68),
2133 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2134 { PCI_DEVICE(0x1002, 0xaa80),
2135 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2136 { PCI_DEVICE(0x1002, 0xaa88),
2137 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2138 { PCI_DEVICE(0x1002, 0xaa90),
2139 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2140 { PCI_DEVICE(0x1002, 0xaa98),
2141 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2142 { PCI_DEVICE(0x1002, 0x9902),
2143 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2144 { PCI_DEVICE(0x1002, 0xaaa0),
2145 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2146 { PCI_DEVICE(0x1002, 0xaaa8),
2147 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2148 { PCI_DEVICE(0x1002, 0xaab0),
2149 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2150 /* VIA VT8251/VT8237A */
2151 { PCI_DEVICE(0x1106, 0x3288),
2152 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2153 /* VIA GFX VT7122/VX900 */
2154 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2155 /* VIA GFX VT6122/VX11 */
2156 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2157 /* SIS966 */
2158 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2159 /* ULI M5461 */
2160 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2161 /* NVIDIA MCP */
2162 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2163 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2164 .class_mask = 0xffffff,
2165 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2166 /* Teradici */
2167 { PCI_DEVICE(0x6549, 0x1200),
2168 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2169 { PCI_DEVICE(0x6549, 0x2200),
2170 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2171 /* Creative X-Fi (CA0110-IBG) */
2172 /* CTHDA chips */
2173 { PCI_DEVICE(0x1102, 0x0010),
2174 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2175 { PCI_DEVICE(0x1102, 0x0012),
2176 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2177 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2178 /* the following entry conflicts with snd-ctxfi driver,
2179 * as ctxfi driver mutates from HD-audio to native mode with
2180 * a special command sequence.
2181 */
2182 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2183 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2184 .class_mask = 0xffffff,
2185 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2186 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2187 #else
2188 /* this entry seems still valid -- i.e. without emu20kx chip */
2189 { PCI_DEVICE(0x1102, 0x0009),
2190 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2191 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2192 #endif
2193 /* CM8888 */
2194 { PCI_DEVICE(0x13f6, 0x5011),
2195 .driver_data = AZX_DRIVER_CMEDIA |
2196 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2197 /* Vortex86MX */
2198 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2199 /* VMware HDAudio */
2200 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2201 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2202 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2203 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2204 .class_mask = 0xffffff,
2205 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2206 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2207 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2208 .class_mask = 0xffffff,
2209 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2210 { 0, }
2211 };
2212 MODULE_DEVICE_TABLE(pci, azx_ids);
2213
2214 /* pci_driver definition */
2215 static struct pci_driver azx_driver = {
2216 .name = KBUILD_MODNAME,
2217 .id_table = azx_ids,
2218 .probe = azx_probe,
2219 .remove = azx_remove,
2220 .shutdown = azx_shutdown,
2221 .driver = {
2222 .pm = AZX_PM_OPS,
2223 },
2224 };
2225
2226 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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