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ALSA: hda - Add AZX_DCAPS_SNOOP_OFF (and refactor snoop setup)
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <linux/vgaarb.h>
61 #include <linux/vga_switcheroo.h>
62 #include <linux/firmware.h>
63 #include "hda_codec.h"
64 #include "hda_controller.h"
65 #include "hda_priv.h"
66 #include "hda_i915.h"
67
68 /* position fix mode */
69 enum {
70 POS_FIX_AUTO,
71 POS_FIX_LPIB,
72 POS_FIX_POSBUF,
73 POS_FIX_VIACOMBO,
74 POS_FIX_COMBO,
75 };
76
77 /* Defines for ATI HD Audio support in SB450 south bridge */
78 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
79 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
80
81 /* Defines for Nvidia HDA support */
82 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
83 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
84 #define NVIDIA_HDA_ISTRM_COH 0x4d
85 #define NVIDIA_HDA_OSTRM_COH 0x4c
86 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
87
88 /* Defines for Intel SCH HDA snoop control */
89 #define INTEL_SCH_HDA_DEVC 0x78
90 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
91
92 /* Define IN stream 0 FIFO size offset in VIA controller */
93 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
94 /* Define VIA HD Audio Device ID*/
95 #define VIA_HDAC_DEVICE_ID 0x3288
96
97 /* max number of SDs */
98 /* ICH, ATI and VIA have 4 playback and 4 capture */
99 #define ICH6_NUM_CAPTURE 4
100 #define ICH6_NUM_PLAYBACK 4
101
102 /* ULI has 6 playback and 5 capture */
103 #define ULI_NUM_CAPTURE 5
104 #define ULI_NUM_PLAYBACK 6
105
106 /* ATI HDMI may have up to 8 playbacks and 0 capture */
107 #define ATIHDMI_NUM_CAPTURE 0
108 #define ATIHDMI_NUM_PLAYBACK 8
109
110 /* TERA has 4 playback and 3 capture */
111 #define TERA_NUM_CAPTURE 3
112 #define TERA_NUM_PLAYBACK 4
113
114
115 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
116 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
117 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
118 static char *model[SNDRV_CARDS];
119 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
120 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
121 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
122 static int probe_only[SNDRV_CARDS];
123 static int jackpoll_ms[SNDRV_CARDS];
124 static bool single_cmd;
125 static int enable_msi = -1;
126 #ifdef CONFIG_SND_HDA_PATCH_LOADER
127 static char *patch[SNDRV_CARDS];
128 #endif
129 #ifdef CONFIG_SND_HDA_INPUT_BEEP
130 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
131 CONFIG_SND_HDA_INPUT_BEEP_MODE};
132 #endif
133
134 module_param_array(index, int, NULL, 0444);
135 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
136 module_param_array(id, charp, NULL, 0444);
137 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
138 module_param_array(enable, bool, NULL, 0444);
139 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
140 module_param_array(model, charp, NULL, 0444);
141 MODULE_PARM_DESC(model, "Use the given board model.");
142 module_param_array(position_fix, int, NULL, 0444);
143 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
144 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
145 module_param_array(bdl_pos_adj, int, NULL, 0644);
146 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
147 module_param_array(probe_mask, int, NULL, 0444);
148 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
149 module_param_array(probe_only, int, NULL, 0444);
150 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
151 module_param_array(jackpoll_ms, int, NULL, 0444);
152 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
153 module_param(single_cmd, bool, 0444);
154 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
155 "(for debugging only).");
156 module_param(enable_msi, bint, 0444);
157 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
158 #ifdef CONFIG_SND_HDA_PATCH_LOADER
159 module_param_array(patch, charp, NULL, 0444);
160 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
161 #endif
162 #ifdef CONFIG_SND_HDA_INPUT_BEEP
163 module_param_array(beep_mode, bool, NULL, 0444);
164 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
165 "(0=off, 1=on) (default=1).");
166 #endif
167
168 #ifdef CONFIG_PM
169 static int param_set_xint(const char *val, const struct kernel_param *kp);
170 static struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173 };
174 #define param_check_xint param_check_int
175
176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
177 static int *power_save_addr = &power_save;
178 module_param(power_save, xint, 0644);
179 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
180 "(in second, 0 = disable).");
181
182 /* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
186 static bool power_save_controller = 1;
187 module_param(power_save_controller, bool, 0644);
188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
189 #else
190 static int *power_save_addr;
191 #endif /* CONFIG_PM */
192
193 static int align_buffer_size = -1;
194 module_param(align_buffer_size, bint, 0644);
195 MODULE_PARM_DESC(align_buffer_size,
196 "Force buffer and period sizes to be multiple of 128 bytes.");
197
198 #ifdef CONFIG_X86
199 static bool hda_snoop = true;
200 module_param_named(snoop, hda_snoop, bool, 0444);
201 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
202 #else
203 #define hda_snoop true
204 #endif
205
206
207 MODULE_LICENSE("GPL");
208 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
209 "{Intel, ICH6M},"
210 "{Intel, ICH7},"
211 "{Intel, ESB2},"
212 "{Intel, ICH8},"
213 "{Intel, ICH9},"
214 "{Intel, ICH10},"
215 "{Intel, PCH},"
216 "{Intel, CPT},"
217 "{Intel, PPT},"
218 "{Intel, LPT},"
219 "{Intel, LPT_LP},"
220 "{Intel, WPT_LP},"
221 "{Intel, SPT},"
222 "{Intel, SPT_LP},"
223 "{Intel, HPT},"
224 "{Intel, PBG},"
225 "{Intel, SCH},"
226 "{ATI, SB450},"
227 "{ATI, SB600},"
228 "{ATI, RS600},"
229 "{ATI, RS690},"
230 "{ATI, RS780},"
231 "{ATI, R600},"
232 "{ATI, RV630},"
233 "{ATI, RV610},"
234 "{ATI, RV670},"
235 "{ATI, RV635},"
236 "{ATI, RV620},"
237 "{ATI, RV770},"
238 "{VIA, VT8251},"
239 "{VIA, VT8237A},"
240 "{SiS, SIS966},"
241 "{ULI, M5461}}");
242 MODULE_DESCRIPTION("Intel HDA driver");
243
244 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
245 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
246 #define SUPPORT_VGA_SWITCHEROO
247 #endif
248 #endif
249
250
251 /*
252 */
253
254 /* driver types */
255 enum {
256 AZX_DRIVER_ICH,
257 AZX_DRIVER_PCH,
258 AZX_DRIVER_SCH,
259 AZX_DRIVER_HDMI,
260 AZX_DRIVER_ATI,
261 AZX_DRIVER_ATIHDMI,
262 AZX_DRIVER_ATIHDMI_NS,
263 AZX_DRIVER_VIA,
264 AZX_DRIVER_SIS,
265 AZX_DRIVER_ULI,
266 AZX_DRIVER_NVIDIA,
267 AZX_DRIVER_TERA,
268 AZX_DRIVER_CTX,
269 AZX_DRIVER_CTHDA,
270 AZX_DRIVER_CMEDIA,
271 AZX_DRIVER_GENERIC,
272 AZX_NUM_DRIVERS, /* keep this as last entry */
273 };
274
275 #define azx_get_snoop_type(chip) \
276 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
277 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
278
279 /* quirks for Intel PCH */
280 #define AZX_DCAPS_INTEL_PCH_NOPM \
281 (AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
282 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
283
284 #define AZX_DCAPS_INTEL_PCH \
285 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
286
287 #define AZX_DCAPS_INTEL_HASWELL \
288 (AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
289 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
290 AZX_DCAPS_SNOOP_TYPE(SCH))
291
292 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
293 #define AZX_DCAPS_INTEL_BROADWELL \
294 (AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_POSFIX_LPIB |\
295 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
296 AZX_DCAPS_SNOOP_TYPE(SCH))
297
298 /* quirks for ATI SB / AMD Hudson */
299 #define AZX_DCAPS_PRESET_ATI_SB \
300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
301 AZX_DCAPS_SNOOP_TYPE(ATI))
302
303 /* quirks for ATI/AMD HDMI */
304 #define AZX_DCAPS_PRESET_ATI_HDMI \
305 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
306
307 /* quirks for ATI HDMI with snoop off */
308 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
309 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
310
311 /* quirks for Nvidia */
312 #define AZX_DCAPS_PRESET_NVIDIA \
313 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | AZX_DCAPS_ALIGN_BUFSIZE |\
314 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
315 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
316
317 #define AZX_DCAPS_PRESET_CTHDA \
318 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
319 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
320
321 /*
322 * VGA-switcher support
323 */
324 #ifdef SUPPORT_VGA_SWITCHEROO
325 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
326 #else
327 #define use_vga_switcheroo(chip) 0
328 #endif
329
330 static char *driver_short_names[] = {
331 [AZX_DRIVER_ICH] = "HDA Intel",
332 [AZX_DRIVER_PCH] = "HDA Intel PCH",
333 [AZX_DRIVER_SCH] = "HDA Intel MID",
334 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
335 [AZX_DRIVER_ATI] = "HDA ATI SB",
336 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
337 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
338 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
339 [AZX_DRIVER_SIS] = "HDA SIS966",
340 [AZX_DRIVER_ULI] = "HDA ULI M5461",
341 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
342 [AZX_DRIVER_TERA] = "HDA Teradici",
343 [AZX_DRIVER_CTX] = "HDA Creative",
344 [AZX_DRIVER_CTHDA] = "HDA Creative",
345 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
346 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
347 };
348
349 struct hda_intel {
350 struct azx chip;
351
352 /* for pending irqs */
353 struct work_struct irq_pending_work;
354
355 /* sync probing */
356 struct completion probe_wait;
357 struct work_struct probe_work;
358
359 /* card list (for power_save trigger) */
360 struct list_head list;
361
362 /* extra flags */
363 unsigned int irq_pending_warned:1;
364
365 /* VGA-switcheroo setup */
366 unsigned int use_vga_switcheroo:1;
367 unsigned int vga_switcheroo_registered:1;
368 unsigned int init_failed:1; /* delayed init failed */
369
370 /* secondary power domain for hdmi audio under vga device */
371 struct dev_pm_domain hdmi_pm_domain;
372 };
373
374 #ifdef CONFIG_X86
375 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
376 {
377 int pages;
378
379 if (azx_snoop(chip))
380 return;
381 if (!dmab || !dmab->area || !dmab->bytes)
382 return;
383
384 #ifdef CONFIG_SND_DMA_SGBUF
385 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
386 struct snd_sg_buf *sgbuf = dmab->private_data;
387 if (chip->driver_type == AZX_DRIVER_CMEDIA)
388 return; /* deal with only CORB/RIRB buffers */
389 if (on)
390 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
391 else
392 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
393 return;
394 }
395 #endif
396
397 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
398 if (on)
399 set_memory_wc((unsigned long)dmab->area, pages);
400 else
401 set_memory_wb((unsigned long)dmab->area, pages);
402 }
403
404 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
405 bool on)
406 {
407 __mark_pages_wc(chip, buf, on);
408 }
409 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
410 struct snd_pcm_substream *substream, bool on)
411 {
412 if (azx_dev->wc_marked != on) {
413 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
414 azx_dev->wc_marked = on;
415 }
416 }
417 #else
418 /* NOP for other archs */
419 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
420 bool on)
421 {
422 }
423 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
424 struct snd_pcm_substream *substream, bool on)
425 {
426 }
427 #endif
428
429 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
430
431 /*
432 * initialize the PCI registers
433 */
434 /* update bits in a PCI register byte */
435 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
436 unsigned char mask, unsigned char val)
437 {
438 unsigned char data;
439
440 pci_read_config_byte(pci, reg, &data);
441 data &= ~mask;
442 data |= (val & mask);
443 pci_write_config_byte(pci, reg, data);
444 }
445
446 static void azx_init_pci(struct azx *chip)
447 {
448 int snoop_type = azx_get_snoop_type(chip);
449
450 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
451 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
452 * Ensuring these bits are 0 clears playback static on some HD Audio
453 * codecs.
454 * The PCI register TCSEL is defined in the Intel manuals.
455 */
456 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
457 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
458 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
459 }
460
461 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
462 * we need to enable snoop.
463 */
464 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
465 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
466 azx_snoop(chip));
467 update_pci_byte(chip->pci,
468 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
469 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
470 }
471
472 /* For NVIDIA HDA, enable snoop */
473 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
474 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
475 azx_snoop(chip));
476 update_pci_byte(chip->pci,
477 NVIDIA_HDA_TRANSREG_ADDR,
478 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
479 update_pci_byte(chip->pci,
480 NVIDIA_HDA_ISTRM_COH,
481 0x01, NVIDIA_HDA_ENABLE_COHBIT);
482 update_pci_byte(chip->pci,
483 NVIDIA_HDA_OSTRM_COH,
484 0x01, NVIDIA_HDA_ENABLE_COHBIT);
485 }
486
487 /* Enable SCH/PCH snoop if needed */
488 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
489 unsigned short snoop;
490 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
491 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
492 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
493 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
494 if (!azx_snoop(chip))
495 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
496 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
497 pci_read_config_word(chip->pci,
498 INTEL_SCH_HDA_DEVC, &snoop);
499 }
500 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
501 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
502 "Disabled" : "Enabled");
503 }
504 }
505
506 /* calculate runtime delay from LPIB */
507 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
508 unsigned int pos)
509 {
510 struct snd_pcm_substream *substream = azx_dev->substream;
511 int stream = substream->stream;
512 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
513 int delay;
514
515 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
516 delay = pos - lpib_pos;
517 else
518 delay = lpib_pos - pos;
519 if (delay < 0) {
520 if (delay >= azx_dev->delay_negative_threshold)
521 delay = 0;
522 else
523 delay += azx_dev->bufsize;
524 }
525
526 if (delay >= azx_dev->period_bytes) {
527 dev_info(chip->card->dev,
528 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
529 delay, azx_dev->period_bytes);
530 delay = 0;
531 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
532 chip->get_delay[stream] = NULL;
533 }
534
535 return bytes_to_frames(substream->runtime, delay);
536 }
537
538 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
539
540 /* called from IRQ */
541 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
542 {
543 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
544 int ok;
545
546 ok = azx_position_ok(chip, azx_dev);
547 if (ok == 1) {
548 azx_dev->irq_pending = 0;
549 return ok;
550 } else if (ok == 0 && chip->bus && chip->bus->workq) {
551 /* bogus IRQ, process it later */
552 azx_dev->irq_pending = 1;
553 queue_work(chip->bus->workq, &hda->irq_pending_work);
554 }
555 return 0;
556 }
557
558 /*
559 * Check whether the current DMA position is acceptable for updating
560 * periods. Returns non-zero if it's OK.
561 *
562 * Many HD-audio controllers appear pretty inaccurate about
563 * the update-IRQ timing. The IRQ is issued before actually the
564 * data is processed. So, we need to process it afterwords in a
565 * workqueue.
566 */
567 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
568 {
569 struct snd_pcm_substream *substream = azx_dev->substream;
570 int stream = substream->stream;
571 u32 wallclk;
572 unsigned int pos;
573
574 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
575 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
576 return -1; /* bogus (too early) interrupt */
577
578 if (chip->get_position[stream])
579 pos = chip->get_position[stream](chip, azx_dev);
580 else { /* use the position buffer as default */
581 pos = azx_get_pos_posbuf(chip, azx_dev);
582 if (!pos || pos == (u32)-1) {
583 dev_info(chip->card->dev,
584 "Invalid position buffer, using LPIB read method instead.\n");
585 chip->get_position[stream] = azx_get_pos_lpib;
586 pos = azx_get_pos_lpib(chip, azx_dev);
587 chip->get_delay[stream] = NULL;
588 } else {
589 chip->get_position[stream] = azx_get_pos_posbuf;
590 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
591 chip->get_delay[stream] = azx_get_delay_from_lpib;
592 }
593 }
594
595 if (pos >= azx_dev->bufsize)
596 pos = 0;
597
598 if (WARN_ONCE(!azx_dev->period_bytes,
599 "hda-intel: zero azx_dev->period_bytes"))
600 return -1; /* this shouldn't happen! */
601 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
602 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
603 /* NG - it's below the first next period boundary */
604 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
605 azx_dev->start_wallclk += wallclk;
606 return 1; /* OK, it's fine */
607 }
608
609 /*
610 * The work for pending PCM period updates.
611 */
612 static void azx_irq_pending_work(struct work_struct *work)
613 {
614 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
615 struct azx *chip = &hda->chip;
616 int i, pending, ok;
617
618 if (!hda->irq_pending_warned) {
619 dev_info(chip->card->dev,
620 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
621 chip->card->number);
622 hda->irq_pending_warned = 1;
623 }
624
625 for (;;) {
626 pending = 0;
627 spin_lock_irq(&chip->reg_lock);
628 for (i = 0; i < chip->num_streams; i++) {
629 struct azx_dev *azx_dev = &chip->azx_dev[i];
630 if (!azx_dev->irq_pending ||
631 !azx_dev->substream ||
632 !azx_dev->running)
633 continue;
634 ok = azx_position_ok(chip, azx_dev);
635 if (ok > 0) {
636 azx_dev->irq_pending = 0;
637 spin_unlock(&chip->reg_lock);
638 snd_pcm_period_elapsed(azx_dev->substream);
639 spin_lock(&chip->reg_lock);
640 } else if (ok < 0) {
641 pending = 0; /* too early */
642 } else
643 pending++;
644 }
645 spin_unlock_irq(&chip->reg_lock);
646 if (!pending)
647 return;
648 msleep(1);
649 }
650 }
651
652 /* clear irq_pending flags and assure no on-going workq */
653 static void azx_clear_irq_pending(struct azx *chip)
654 {
655 int i;
656
657 spin_lock_irq(&chip->reg_lock);
658 for (i = 0; i < chip->num_streams; i++)
659 chip->azx_dev[i].irq_pending = 0;
660 spin_unlock_irq(&chip->reg_lock);
661 }
662
663 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
664 {
665 if (request_irq(chip->pci->irq, azx_interrupt,
666 chip->msi ? 0 : IRQF_SHARED,
667 KBUILD_MODNAME, chip)) {
668 dev_err(chip->card->dev,
669 "unable to grab IRQ %d, disabling device\n",
670 chip->pci->irq);
671 if (do_disconnect)
672 snd_card_disconnect(chip->card);
673 return -1;
674 }
675 chip->irq = chip->pci->irq;
676 pci_intx(chip->pci, !chip->msi);
677 return 0;
678 }
679
680 /* get the current DMA position with correction on VIA chips */
681 static unsigned int azx_via_get_position(struct azx *chip,
682 struct azx_dev *azx_dev)
683 {
684 unsigned int link_pos, mini_pos, bound_pos;
685 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
686 unsigned int fifo_size;
687
688 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
689 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
690 /* Playback, no problem using link position */
691 return link_pos;
692 }
693
694 /* Capture */
695 /* For new chipset,
696 * use mod to get the DMA position just like old chipset
697 */
698 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
699 mod_dma_pos %= azx_dev->period_bytes;
700
701 /* azx_dev->fifo_size can't get FIFO size of in stream.
702 * Get from base address + offset.
703 */
704 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
705
706 if (azx_dev->insufficient) {
707 /* Link position never gather than FIFO size */
708 if (link_pos <= fifo_size)
709 return 0;
710
711 azx_dev->insufficient = 0;
712 }
713
714 if (link_pos <= fifo_size)
715 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
716 else
717 mini_pos = link_pos - fifo_size;
718
719 /* Find nearest previous boudary */
720 mod_mini_pos = mini_pos % azx_dev->period_bytes;
721 mod_link_pos = link_pos % azx_dev->period_bytes;
722 if (mod_link_pos >= fifo_size)
723 bound_pos = link_pos - mod_link_pos;
724 else if (mod_dma_pos >= mod_mini_pos)
725 bound_pos = mini_pos - mod_mini_pos;
726 else {
727 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
728 if (bound_pos >= azx_dev->bufsize)
729 bound_pos = 0;
730 }
731
732 /* Calculate real DMA position we want */
733 return bound_pos + mod_dma_pos;
734 }
735
736 #ifdef CONFIG_PM
737 static DEFINE_MUTEX(card_list_lock);
738 static LIST_HEAD(card_list);
739
740 static void azx_add_card_list(struct azx *chip)
741 {
742 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
743 mutex_lock(&card_list_lock);
744 list_add(&hda->list, &card_list);
745 mutex_unlock(&card_list_lock);
746 }
747
748 static void azx_del_card_list(struct azx *chip)
749 {
750 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
751 mutex_lock(&card_list_lock);
752 list_del_init(&hda->list);
753 mutex_unlock(&card_list_lock);
754 }
755
756 /* trigger power-save check at writing parameter */
757 static int param_set_xint(const char *val, const struct kernel_param *kp)
758 {
759 struct hda_intel *hda;
760 struct azx *chip;
761 struct hda_codec *c;
762 int prev = power_save;
763 int ret = param_set_int(val, kp);
764
765 if (ret || prev == power_save)
766 return ret;
767
768 mutex_lock(&card_list_lock);
769 list_for_each_entry(hda, &card_list, list) {
770 chip = &hda->chip;
771 if (!chip->bus || chip->disabled)
772 continue;
773 list_for_each_entry(c, &chip->bus->codec_list, list)
774 snd_hda_power_sync(c);
775 }
776 mutex_unlock(&card_list_lock);
777 return 0;
778 }
779 #else
780 #define azx_add_card_list(chip) /* NOP */
781 #define azx_del_card_list(chip) /* NOP */
782 #endif /* CONFIG_PM */
783
784 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
785 /*
786 * power management
787 */
788 static int azx_suspend(struct device *dev)
789 {
790 struct pci_dev *pci = to_pci_dev(dev);
791 struct snd_card *card = dev_get_drvdata(dev);
792 struct azx *chip;
793 struct hda_intel *hda;
794 struct azx_pcm *p;
795
796 if (!card)
797 return 0;
798
799 chip = card->private_data;
800 hda = container_of(chip, struct hda_intel, chip);
801 if (chip->disabled || hda->init_failed)
802 return 0;
803
804 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
805 azx_clear_irq_pending(chip);
806 list_for_each_entry(p, &chip->pcm_list, list)
807 snd_pcm_suspend_all(p->pcm);
808 if (chip->initialized)
809 snd_hda_suspend(chip->bus);
810 azx_stop_chip(chip);
811 azx_enter_link_reset(chip);
812 if (chip->irq >= 0) {
813 free_irq(chip->irq, chip);
814 chip->irq = -1;
815 }
816
817 if (chip->msi)
818 pci_disable_msi(chip->pci);
819 pci_disable_device(pci);
820 pci_save_state(pci);
821 pci_set_power_state(pci, PCI_D3hot);
822 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
823 hda_display_power(false);
824 return 0;
825 }
826
827 static int azx_resume(struct device *dev)
828 {
829 struct pci_dev *pci = to_pci_dev(dev);
830 struct snd_card *card = dev_get_drvdata(dev);
831 struct azx *chip;
832 struct hda_intel *hda;
833
834 if (!card)
835 return 0;
836
837 chip = card->private_data;
838 hda = container_of(chip, struct hda_intel, chip);
839 if (chip->disabled || hda->init_failed)
840 return 0;
841
842 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
843 hda_display_power(true);
844 haswell_set_bclk(chip);
845 }
846 pci_set_power_state(pci, PCI_D0);
847 pci_restore_state(pci);
848 if (pci_enable_device(pci) < 0) {
849 dev_err(chip->card->dev,
850 "pci_enable_device failed, disabling device\n");
851 snd_card_disconnect(card);
852 return -EIO;
853 }
854 pci_set_master(pci);
855 if (chip->msi)
856 if (pci_enable_msi(pci) < 0)
857 chip->msi = 0;
858 if (azx_acquire_irq(chip, 1) < 0)
859 return -EIO;
860 azx_init_pci(chip);
861
862 azx_init_chip(chip, true);
863
864 snd_hda_resume(chip->bus);
865 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
866 return 0;
867 }
868 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
869
870 #ifdef CONFIG_PM_RUNTIME
871 static int azx_runtime_suspend(struct device *dev)
872 {
873 struct snd_card *card = dev_get_drvdata(dev);
874 struct azx *chip;
875 struct hda_intel *hda;
876
877 if (!card)
878 return 0;
879
880 chip = card->private_data;
881 hda = container_of(chip, struct hda_intel, chip);
882 if (chip->disabled || hda->init_failed)
883 return 0;
884
885 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
886 return 0;
887
888 /* enable controller wake up event */
889 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
890 STATESTS_INT_MASK);
891
892 azx_stop_chip(chip);
893 azx_enter_link_reset(chip);
894 azx_clear_irq_pending(chip);
895 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
896 hda_display_power(false);
897
898 return 0;
899 }
900
901 static int azx_runtime_resume(struct device *dev)
902 {
903 struct snd_card *card = dev_get_drvdata(dev);
904 struct azx *chip;
905 struct hda_intel *hda;
906 struct hda_bus *bus;
907 struct hda_codec *codec;
908 int status;
909
910 if (!card)
911 return 0;
912
913 chip = card->private_data;
914 hda = container_of(chip, struct hda_intel, chip);
915 if (chip->disabled || hda->init_failed)
916 return 0;
917
918 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
919 return 0;
920
921 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
922 hda_display_power(true);
923 haswell_set_bclk(chip);
924 }
925
926 /* Read STATESTS before controller reset */
927 status = azx_readw(chip, STATESTS);
928
929 azx_init_pci(chip);
930 azx_init_chip(chip, true);
931
932 bus = chip->bus;
933 if (status && bus) {
934 list_for_each_entry(codec, &bus->codec_list, list)
935 if (status & (1 << codec->addr))
936 queue_delayed_work(codec->bus->workq,
937 &codec->jackpoll_work, codec->jackpoll_interval);
938 }
939
940 /* disable controller Wake Up event*/
941 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
942 ~STATESTS_INT_MASK);
943
944 return 0;
945 }
946
947 static int azx_runtime_idle(struct device *dev)
948 {
949 struct snd_card *card = dev_get_drvdata(dev);
950 struct azx *chip;
951 struct hda_intel *hda;
952
953 if (!card)
954 return 0;
955
956 chip = card->private_data;
957 hda = container_of(chip, struct hda_intel, chip);
958 if (chip->disabled || hda->init_failed)
959 return 0;
960
961 if (!power_save_controller ||
962 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
963 return -EBUSY;
964
965 return 0;
966 }
967
968 #endif /* CONFIG_PM_RUNTIME */
969
970 #ifdef CONFIG_PM
971 static const struct dev_pm_ops azx_pm = {
972 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
973 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
974 };
975
976 #define AZX_PM_OPS &azx_pm
977 #else
978 #define AZX_PM_OPS NULL
979 #endif /* CONFIG_PM */
980
981
982 static int azx_probe_continue(struct azx *chip);
983
984 #ifdef SUPPORT_VGA_SWITCHEROO
985 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
986
987 static void azx_vs_set_state(struct pci_dev *pci,
988 enum vga_switcheroo_state state)
989 {
990 struct snd_card *card = pci_get_drvdata(pci);
991 struct azx *chip = card->private_data;
992 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
993 bool disabled;
994
995 wait_for_completion(&hda->probe_wait);
996 if (hda->init_failed)
997 return;
998
999 disabled = (state == VGA_SWITCHEROO_OFF);
1000 if (chip->disabled == disabled)
1001 return;
1002
1003 if (!chip->bus) {
1004 chip->disabled = disabled;
1005 if (!disabled) {
1006 dev_info(chip->card->dev,
1007 "Start delayed initialization\n");
1008 if (azx_probe_continue(chip) < 0) {
1009 dev_err(chip->card->dev, "initialization error\n");
1010 hda->init_failed = true;
1011 }
1012 }
1013 } else {
1014 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1015 disabled ? "Disabling" : "Enabling");
1016 if (disabled) {
1017 pm_runtime_put_sync_suspend(card->dev);
1018 azx_suspend(card->dev);
1019 /* when we get suspended by vga switcheroo we end up in D3cold,
1020 * however we have no ACPI handle, so pci/acpi can't put us there,
1021 * put ourselves there */
1022 pci->current_state = PCI_D3cold;
1023 chip->disabled = true;
1024 if (snd_hda_lock_devices(chip->bus))
1025 dev_warn(chip->card->dev,
1026 "Cannot lock devices!\n");
1027 } else {
1028 snd_hda_unlock_devices(chip->bus);
1029 pm_runtime_get_noresume(card->dev);
1030 chip->disabled = false;
1031 azx_resume(card->dev);
1032 }
1033 }
1034 }
1035
1036 static bool azx_vs_can_switch(struct pci_dev *pci)
1037 {
1038 struct snd_card *card = pci_get_drvdata(pci);
1039 struct azx *chip = card->private_data;
1040 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1041
1042 wait_for_completion(&hda->probe_wait);
1043 if (hda->init_failed)
1044 return false;
1045 if (chip->disabled || !chip->bus)
1046 return true;
1047 if (snd_hda_lock_devices(chip->bus))
1048 return false;
1049 snd_hda_unlock_devices(chip->bus);
1050 return true;
1051 }
1052
1053 static void init_vga_switcheroo(struct azx *chip)
1054 {
1055 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1056 struct pci_dev *p = get_bound_vga(chip->pci);
1057 if (p) {
1058 dev_info(chip->card->dev,
1059 "Handle VGA-switcheroo audio client\n");
1060 hda->use_vga_switcheroo = 1;
1061 pci_dev_put(p);
1062 }
1063 }
1064
1065 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1066 .set_gpu_state = azx_vs_set_state,
1067 .can_switch = azx_vs_can_switch,
1068 };
1069
1070 static int register_vga_switcheroo(struct azx *chip)
1071 {
1072 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1073 int err;
1074
1075 if (!hda->use_vga_switcheroo)
1076 return 0;
1077 /* FIXME: currently only handling DIS controller
1078 * is there any machine with two switchable HDMI audio controllers?
1079 */
1080 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1081 VGA_SWITCHEROO_DIS,
1082 chip->bus != NULL);
1083 if (err < 0)
1084 return err;
1085 hda->vga_switcheroo_registered = 1;
1086
1087 /* register as an optimus hdmi audio power domain */
1088 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1089 &hda->hdmi_pm_domain);
1090 return 0;
1091 }
1092 #else
1093 #define init_vga_switcheroo(chip) /* NOP */
1094 #define register_vga_switcheroo(chip) 0
1095 #define check_hdmi_disabled(pci) false
1096 #endif /* SUPPORT_VGA_SWITCHER */
1097
1098 /*
1099 * destructor
1100 */
1101 static int azx_free(struct azx *chip)
1102 {
1103 struct pci_dev *pci = chip->pci;
1104 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1105 int i;
1106
1107 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1108 && chip->running)
1109 pm_runtime_get_noresume(&pci->dev);
1110
1111 azx_del_card_list(chip);
1112
1113 azx_notifier_unregister(chip);
1114
1115 hda->init_failed = 1; /* to be sure */
1116 complete_all(&hda->probe_wait);
1117
1118 if (use_vga_switcheroo(hda)) {
1119 if (chip->disabled && chip->bus)
1120 snd_hda_unlock_devices(chip->bus);
1121 if (hda->vga_switcheroo_registered)
1122 vga_switcheroo_unregister_client(chip->pci);
1123 }
1124
1125 if (chip->initialized) {
1126 azx_clear_irq_pending(chip);
1127 for (i = 0; i < chip->num_streams; i++)
1128 azx_stream_stop(chip, &chip->azx_dev[i]);
1129 azx_stop_chip(chip);
1130 }
1131
1132 if (chip->irq >= 0)
1133 free_irq(chip->irq, (void*)chip);
1134 if (chip->msi)
1135 pci_disable_msi(chip->pci);
1136 if (chip->remap_addr)
1137 iounmap(chip->remap_addr);
1138
1139 azx_free_stream_pages(chip);
1140 if (chip->region_requested)
1141 pci_release_regions(chip->pci);
1142 pci_disable_device(chip->pci);
1143 kfree(chip->azx_dev);
1144 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1145 release_firmware(chip->fw);
1146 #endif
1147 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1148 hda_display_power(false);
1149 hda_i915_exit();
1150 }
1151 kfree(hda);
1152
1153 return 0;
1154 }
1155
1156 static int azx_dev_free(struct snd_device *device)
1157 {
1158 return azx_free(device->device_data);
1159 }
1160
1161 #ifdef SUPPORT_VGA_SWITCHEROO
1162 /*
1163 * Check of disabled HDMI controller by vga-switcheroo
1164 */
1165 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1166 {
1167 struct pci_dev *p;
1168
1169 /* check only discrete GPU */
1170 switch (pci->vendor) {
1171 case PCI_VENDOR_ID_ATI:
1172 case PCI_VENDOR_ID_AMD:
1173 case PCI_VENDOR_ID_NVIDIA:
1174 if (pci->devfn == 1) {
1175 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1176 pci->bus->number, 0);
1177 if (p) {
1178 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1179 return p;
1180 pci_dev_put(p);
1181 }
1182 }
1183 break;
1184 }
1185 return NULL;
1186 }
1187
1188 static bool check_hdmi_disabled(struct pci_dev *pci)
1189 {
1190 bool vga_inactive = false;
1191 struct pci_dev *p = get_bound_vga(pci);
1192
1193 if (p) {
1194 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1195 vga_inactive = true;
1196 pci_dev_put(p);
1197 }
1198 return vga_inactive;
1199 }
1200 #endif /* SUPPORT_VGA_SWITCHEROO */
1201
1202 /*
1203 * white/black-listing for position_fix
1204 */
1205 static struct snd_pci_quirk position_fix_list[] = {
1206 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1207 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1208 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1209 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1210 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1211 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1212 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1213 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1214 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1215 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1216 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1217 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1218 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1219 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1220 {}
1221 };
1222
1223 static int check_position_fix(struct azx *chip, int fix)
1224 {
1225 const struct snd_pci_quirk *q;
1226
1227 switch (fix) {
1228 case POS_FIX_AUTO:
1229 case POS_FIX_LPIB:
1230 case POS_FIX_POSBUF:
1231 case POS_FIX_VIACOMBO:
1232 case POS_FIX_COMBO:
1233 return fix;
1234 }
1235
1236 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1237 if (q) {
1238 dev_info(chip->card->dev,
1239 "position_fix set to %d for device %04x:%04x\n",
1240 q->value, q->subvendor, q->subdevice);
1241 return q->value;
1242 }
1243
1244 /* Check VIA/ATI HD Audio Controller exist */
1245 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1246 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1247 return POS_FIX_VIACOMBO;
1248 }
1249 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1250 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1251 return POS_FIX_LPIB;
1252 }
1253 return POS_FIX_AUTO;
1254 }
1255
1256 static void assign_position_fix(struct azx *chip, int fix)
1257 {
1258 static azx_get_pos_callback_t callbacks[] = {
1259 [POS_FIX_AUTO] = NULL,
1260 [POS_FIX_LPIB] = azx_get_pos_lpib,
1261 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1262 [POS_FIX_VIACOMBO] = azx_via_get_position,
1263 [POS_FIX_COMBO] = azx_get_pos_lpib,
1264 };
1265
1266 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1267
1268 /* combo mode uses LPIB only for playback */
1269 if (fix == POS_FIX_COMBO)
1270 chip->get_position[1] = NULL;
1271
1272 if (fix == POS_FIX_POSBUF &&
1273 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1274 chip->get_delay[0] = chip->get_delay[1] =
1275 azx_get_delay_from_lpib;
1276 }
1277
1278 }
1279
1280 /*
1281 * black-lists for probe_mask
1282 */
1283 static struct snd_pci_quirk probe_mask_list[] = {
1284 /* Thinkpad often breaks the controller communication when accessing
1285 * to the non-working (or non-existing) modem codec slot.
1286 */
1287 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1288 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1289 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1290 /* broken BIOS */
1291 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1292 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1293 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1294 /* forced codec slots */
1295 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1296 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1297 /* WinFast VP200 H (Teradici) user reported broken communication */
1298 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1299 {}
1300 };
1301
1302 #define AZX_FORCE_CODEC_MASK 0x100
1303
1304 static void check_probe_mask(struct azx *chip, int dev)
1305 {
1306 const struct snd_pci_quirk *q;
1307
1308 chip->codec_probe_mask = probe_mask[dev];
1309 if (chip->codec_probe_mask == -1) {
1310 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1311 if (q) {
1312 dev_info(chip->card->dev,
1313 "probe_mask set to 0x%x for device %04x:%04x\n",
1314 q->value, q->subvendor, q->subdevice);
1315 chip->codec_probe_mask = q->value;
1316 }
1317 }
1318
1319 /* check forced option */
1320 if (chip->codec_probe_mask != -1 &&
1321 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1322 chip->codec_mask = chip->codec_probe_mask & 0xff;
1323 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1324 chip->codec_mask);
1325 }
1326 }
1327
1328 /*
1329 * white/black-list for enable_msi
1330 */
1331 static struct snd_pci_quirk msi_black_list[] = {
1332 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1333 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1334 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1335 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1336 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1337 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1338 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1339 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1340 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1341 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1342 {}
1343 };
1344
1345 static void check_msi(struct azx *chip)
1346 {
1347 const struct snd_pci_quirk *q;
1348
1349 if (enable_msi >= 0) {
1350 chip->msi = !!enable_msi;
1351 return;
1352 }
1353 chip->msi = 1; /* enable MSI as default */
1354 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1355 if (q) {
1356 dev_info(chip->card->dev,
1357 "msi for device %04x:%04x set to %d\n",
1358 q->subvendor, q->subdevice, q->value);
1359 chip->msi = q->value;
1360 return;
1361 }
1362
1363 /* NVidia chipsets seem to cause troubles with MSI */
1364 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1365 dev_info(chip->card->dev, "Disabling MSI\n");
1366 chip->msi = 0;
1367 }
1368 }
1369
1370 /* check the snoop mode availability */
1371 static void azx_check_snoop_available(struct azx *chip)
1372 {
1373 bool snoop = chip->snoop;
1374
1375 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1376 chip->driver_type == AZX_DRIVER_VIA) {
1377 /* force to non-snoop mode for a new VIA controller
1378 * when BIOS is set
1379 */
1380 if (snoop) {
1381 u8 val;
1382 pci_read_config_byte(chip->pci, 0x42, &val);
1383 if (!(val & 0x80) && chip->pci->revision == 0x30)
1384 snoop = false;
1385 }
1386 }
1387
1388 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1389 snoop = false;
1390
1391 if (snoop != chip->snoop) {
1392 dev_info(chip->card->dev, "Force to %s mode\n",
1393 snoop ? "snoop" : "non-snoop");
1394 chip->snoop = snoop;
1395 }
1396 }
1397
1398 static void azx_probe_work(struct work_struct *work)
1399 {
1400 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1401 azx_probe_continue(&hda->chip);
1402 }
1403
1404 /*
1405 * constructor
1406 */
1407 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1408 int dev, unsigned int driver_caps,
1409 const struct hda_controller_ops *hda_ops,
1410 struct azx **rchip)
1411 {
1412 static struct snd_device_ops ops = {
1413 .dev_free = azx_dev_free,
1414 };
1415 struct hda_intel *hda;
1416 struct azx *chip;
1417 int err;
1418
1419 *rchip = NULL;
1420
1421 err = pci_enable_device(pci);
1422 if (err < 0)
1423 return err;
1424
1425 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1426 if (!hda) {
1427 dev_err(card->dev, "Cannot allocate hda\n");
1428 pci_disable_device(pci);
1429 return -ENOMEM;
1430 }
1431
1432 chip = &hda->chip;
1433 spin_lock_init(&chip->reg_lock);
1434 mutex_init(&chip->open_mutex);
1435 chip->card = card;
1436 chip->pci = pci;
1437 chip->ops = hda_ops;
1438 chip->irq = -1;
1439 chip->driver_caps = driver_caps;
1440 chip->driver_type = driver_caps & 0xff;
1441 check_msi(chip);
1442 chip->dev_index = dev;
1443 chip->jackpoll_ms = jackpoll_ms;
1444 INIT_LIST_HEAD(&chip->pcm_list);
1445 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1446 INIT_LIST_HEAD(&hda->list);
1447 init_vga_switcheroo(chip);
1448 init_completion(&hda->probe_wait);
1449
1450 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1451
1452 check_probe_mask(chip, dev);
1453
1454 chip->single_cmd = single_cmd;
1455 chip->snoop = hda_snoop;
1456 azx_check_snoop_available(chip);
1457
1458 if (bdl_pos_adj[dev] < 0) {
1459 switch (chip->driver_type) {
1460 case AZX_DRIVER_ICH:
1461 case AZX_DRIVER_PCH:
1462 bdl_pos_adj[dev] = 1;
1463 break;
1464 default:
1465 bdl_pos_adj[dev] = 32;
1466 break;
1467 }
1468 }
1469 chip->bdl_pos_adj = bdl_pos_adj;
1470
1471 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1472 if (err < 0) {
1473 dev_err(card->dev, "Error creating device [card]!\n");
1474 azx_free(chip);
1475 return err;
1476 }
1477
1478 /* continue probing in work context as may trigger request module */
1479 INIT_WORK(&hda->probe_work, azx_probe_work);
1480
1481 *rchip = chip;
1482
1483 return 0;
1484 }
1485
1486 static int azx_first_init(struct azx *chip)
1487 {
1488 int dev = chip->dev_index;
1489 struct pci_dev *pci = chip->pci;
1490 struct snd_card *card = chip->card;
1491 int err;
1492 unsigned short gcap;
1493
1494 #if BITS_PER_LONG != 64
1495 /* Fix up base address on ULI M5461 */
1496 if (chip->driver_type == AZX_DRIVER_ULI) {
1497 u16 tmp3;
1498 pci_read_config_word(pci, 0x40, &tmp3);
1499 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1500 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1501 }
1502 #endif
1503
1504 err = pci_request_regions(pci, "ICH HD audio");
1505 if (err < 0)
1506 return err;
1507 chip->region_requested = 1;
1508
1509 chip->addr = pci_resource_start(pci, 0);
1510 chip->remap_addr = pci_ioremap_bar(pci, 0);
1511 if (chip->remap_addr == NULL) {
1512 dev_err(card->dev, "ioremap error\n");
1513 return -ENXIO;
1514 }
1515
1516 if (chip->msi)
1517 if (pci_enable_msi(pci) < 0)
1518 chip->msi = 0;
1519
1520 if (azx_acquire_irq(chip, 0) < 0)
1521 return -EBUSY;
1522
1523 pci_set_master(pci);
1524 synchronize_irq(chip->irq);
1525
1526 gcap = azx_readw(chip, GCAP);
1527 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1528
1529 /* disable SB600 64bit support for safety */
1530 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1531 struct pci_dev *p_smbus;
1532 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1533 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1534 NULL);
1535 if (p_smbus) {
1536 if (p_smbus->revision < 0x30)
1537 gcap &= ~AZX_GCAP_64OK;
1538 pci_dev_put(p_smbus);
1539 }
1540 }
1541
1542 /* disable 64bit DMA address on some devices */
1543 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1544 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1545 gcap &= ~AZX_GCAP_64OK;
1546 }
1547
1548 /* disable buffer size rounding to 128-byte multiples if supported */
1549 if (align_buffer_size >= 0)
1550 chip->align_buffer_size = !!align_buffer_size;
1551 else {
1552 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
1553 chip->align_buffer_size = 0;
1554 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
1555 chip->align_buffer_size = 1;
1556 else
1557 chip->align_buffer_size = 1;
1558 }
1559
1560 /* allow 64bit DMA address if supported by H/W */
1561 if ((gcap & AZX_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
1562 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
1563 else {
1564 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1565 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
1566 }
1567
1568 /* read number of streams from GCAP register instead of using
1569 * hardcoded value
1570 */
1571 chip->capture_streams = (gcap >> 8) & 0x0f;
1572 chip->playback_streams = (gcap >> 12) & 0x0f;
1573 if (!chip->playback_streams && !chip->capture_streams) {
1574 /* gcap didn't give any info, switching to old method */
1575
1576 switch (chip->driver_type) {
1577 case AZX_DRIVER_ULI:
1578 chip->playback_streams = ULI_NUM_PLAYBACK;
1579 chip->capture_streams = ULI_NUM_CAPTURE;
1580 break;
1581 case AZX_DRIVER_ATIHDMI:
1582 case AZX_DRIVER_ATIHDMI_NS:
1583 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1584 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1585 break;
1586 case AZX_DRIVER_GENERIC:
1587 default:
1588 chip->playback_streams = ICH6_NUM_PLAYBACK;
1589 chip->capture_streams = ICH6_NUM_CAPTURE;
1590 break;
1591 }
1592 }
1593 chip->capture_index_offset = 0;
1594 chip->playback_index_offset = chip->capture_streams;
1595 chip->num_streams = chip->playback_streams + chip->capture_streams;
1596 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1597 GFP_KERNEL);
1598 if (!chip->azx_dev) {
1599 dev_err(card->dev, "cannot malloc azx_dev\n");
1600 return -ENOMEM;
1601 }
1602
1603 err = azx_alloc_stream_pages(chip);
1604 if (err < 0)
1605 return err;
1606
1607 /* initialize streams */
1608 azx_init_stream(chip);
1609
1610 /* initialize chip */
1611 azx_init_pci(chip);
1612
1613 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1614 haswell_set_bclk(chip);
1615
1616 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1617
1618 /* codec detection */
1619 if (!chip->codec_mask) {
1620 dev_err(card->dev, "no codecs found!\n");
1621 return -ENODEV;
1622 }
1623
1624 strcpy(card->driver, "HDA-Intel");
1625 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1626 sizeof(card->shortname));
1627 snprintf(card->longname, sizeof(card->longname),
1628 "%s at 0x%lx irq %i",
1629 card->shortname, chip->addr, chip->irq);
1630
1631 return 0;
1632 }
1633
1634 static void power_down_all_codecs(struct azx *chip)
1635 {
1636 #ifdef CONFIG_PM
1637 /* The codecs were powered up in snd_hda_codec_new().
1638 * Now all initialization done, so turn them down if possible
1639 */
1640 struct hda_codec *codec;
1641 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1642 snd_hda_power_down(codec);
1643 }
1644 #endif
1645 }
1646
1647 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1648 /* callback from request_firmware_nowait() */
1649 static void azx_firmware_cb(const struct firmware *fw, void *context)
1650 {
1651 struct snd_card *card = context;
1652 struct azx *chip = card->private_data;
1653 struct pci_dev *pci = chip->pci;
1654
1655 if (!fw) {
1656 dev_err(card->dev, "Cannot load firmware, aborting\n");
1657 goto error;
1658 }
1659
1660 chip->fw = fw;
1661 if (!chip->disabled) {
1662 /* continue probing */
1663 if (azx_probe_continue(chip))
1664 goto error;
1665 }
1666 return; /* OK */
1667
1668 error:
1669 snd_card_free(card);
1670 pci_set_drvdata(pci, NULL);
1671 }
1672 #endif
1673
1674 /*
1675 * HDA controller ops.
1676 */
1677
1678 /* PCI register access. */
1679 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1680 {
1681 writel(value, addr);
1682 }
1683
1684 static u32 pci_azx_readl(u32 __iomem *addr)
1685 {
1686 return readl(addr);
1687 }
1688
1689 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1690 {
1691 writew(value, addr);
1692 }
1693
1694 static u16 pci_azx_readw(u16 __iomem *addr)
1695 {
1696 return readw(addr);
1697 }
1698
1699 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1700 {
1701 writeb(value, addr);
1702 }
1703
1704 static u8 pci_azx_readb(u8 __iomem *addr)
1705 {
1706 return readb(addr);
1707 }
1708
1709 static int disable_msi_reset_irq(struct azx *chip)
1710 {
1711 int err;
1712
1713 free_irq(chip->irq, chip);
1714 chip->irq = -1;
1715 pci_disable_msi(chip->pci);
1716 chip->msi = 0;
1717 err = azx_acquire_irq(chip, 1);
1718 if (err < 0)
1719 return err;
1720
1721 return 0;
1722 }
1723
1724 /* DMA page allocation helpers. */
1725 static int dma_alloc_pages(struct azx *chip,
1726 int type,
1727 size_t size,
1728 struct snd_dma_buffer *buf)
1729 {
1730 int err;
1731
1732 err = snd_dma_alloc_pages(type,
1733 chip->card->dev,
1734 size, buf);
1735 if (err < 0)
1736 return err;
1737 mark_pages_wc(chip, buf, true);
1738 return 0;
1739 }
1740
1741 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1742 {
1743 mark_pages_wc(chip, buf, false);
1744 snd_dma_free_pages(buf);
1745 }
1746
1747 static int substream_alloc_pages(struct azx *chip,
1748 struct snd_pcm_substream *substream,
1749 size_t size)
1750 {
1751 struct azx_dev *azx_dev = get_azx_dev(substream);
1752 int ret;
1753
1754 mark_runtime_wc(chip, azx_dev, substream, false);
1755 azx_dev->bufsize = 0;
1756 azx_dev->period_bytes = 0;
1757 azx_dev->format_val = 0;
1758 ret = snd_pcm_lib_malloc_pages(substream, size);
1759 if (ret < 0)
1760 return ret;
1761 mark_runtime_wc(chip, azx_dev, substream, true);
1762 return 0;
1763 }
1764
1765 static int substream_free_pages(struct azx *chip,
1766 struct snd_pcm_substream *substream)
1767 {
1768 struct azx_dev *azx_dev = get_azx_dev(substream);
1769 mark_runtime_wc(chip, azx_dev, substream, false);
1770 return snd_pcm_lib_free_pages(substream);
1771 }
1772
1773 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1774 struct vm_area_struct *area)
1775 {
1776 #ifdef CONFIG_X86
1777 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1778 struct azx *chip = apcm->chip;
1779 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1780 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1781 #endif
1782 }
1783
1784 static const struct hda_controller_ops pci_hda_ops = {
1785 .reg_writel = pci_azx_writel,
1786 .reg_readl = pci_azx_readl,
1787 .reg_writew = pci_azx_writew,
1788 .reg_readw = pci_azx_readw,
1789 .reg_writeb = pci_azx_writeb,
1790 .reg_readb = pci_azx_readb,
1791 .disable_msi_reset_irq = disable_msi_reset_irq,
1792 .dma_alloc_pages = dma_alloc_pages,
1793 .dma_free_pages = dma_free_pages,
1794 .substream_alloc_pages = substream_alloc_pages,
1795 .substream_free_pages = substream_free_pages,
1796 .pcm_mmap_prepare = pcm_mmap_prepare,
1797 .position_check = azx_position_check,
1798 };
1799
1800 static int azx_probe(struct pci_dev *pci,
1801 const struct pci_device_id *pci_id)
1802 {
1803 static int dev;
1804 struct snd_card *card;
1805 struct hda_intel *hda;
1806 struct azx *chip;
1807 bool schedule_probe;
1808 int err;
1809
1810 if (dev >= SNDRV_CARDS)
1811 return -ENODEV;
1812 if (!enable[dev]) {
1813 dev++;
1814 return -ENOENT;
1815 }
1816
1817 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1818 0, &card);
1819 if (err < 0) {
1820 dev_err(&pci->dev, "Error creating card!\n");
1821 return err;
1822 }
1823
1824 err = azx_create(card, pci, dev, pci_id->driver_data,
1825 &pci_hda_ops, &chip);
1826 if (err < 0)
1827 goto out_free;
1828 card->private_data = chip;
1829 hda = container_of(chip, struct hda_intel, chip);
1830
1831 pci_set_drvdata(pci, card);
1832
1833 err = register_vga_switcheroo(chip);
1834 if (err < 0) {
1835 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
1836 goto out_free;
1837 }
1838
1839 if (check_hdmi_disabled(pci)) {
1840 dev_info(card->dev, "VGA controller is disabled\n");
1841 dev_info(card->dev, "Delaying initialization\n");
1842 chip->disabled = true;
1843 }
1844
1845 schedule_probe = !chip->disabled;
1846
1847 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1848 if (patch[dev] && *patch[dev]) {
1849 dev_info(card->dev, "Applying patch firmware '%s'\n",
1850 patch[dev]);
1851 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1852 &pci->dev, GFP_KERNEL, card,
1853 azx_firmware_cb);
1854 if (err < 0)
1855 goto out_free;
1856 schedule_probe = false; /* continued in azx_firmware_cb() */
1857 }
1858 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1859
1860 #ifndef CONFIG_SND_HDA_I915
1861 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1862 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1863 #endif
1864
1865 if (schedule_probe)
1866 schedule_work(&hda->probe_work);
1867
1868 dev++;
1869 if (chip->disabled)
1870 complete_all(&hda->probe_wait);
1871 return 0;
1872
1873 out_free:
1874 snd_card_free(card);
1875 return err;
1876 }
1877
1878 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1879 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1880 [AZX_DRIVER_NVIDIA] = 8,
1881 [AZX_DRIVER_TERA] = 1,
1882 };
1883
1884 static int azx_probe_continue(struct azx *chip)
1885 {
1886 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1887 struct pci_dev *pci = chip->pci;
1888 int dev = chip->dev_index;
1889 int err;
1890
1891 /* Request power well for Haswell HDA controller and codec */
1892 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1893 #ifdef CONFIG_SND_HDA_I915
1894 err = hda_i915_init();
1895 if (err < 0) {
1896 dev_err(chip->card->dev,
1897 "Error request power-well from i915\n");
1898 goto out_free;
1899 }
1900 err = hda_display_power(true);
1901 if (err < 0) {
1902 dev_err(chip->card->dev,
1903 "Cannot turn on display power on i915\n");
1904 goto out_free;
1905 }
1906 #endif
1907 }
1908
1909 err = azx_first_init(chip);
1910 if (err < 0)
1911 goto out_free;
1912
1913 #ifdef CONFIG_SND_HDA_INPUT_BEEP
1914 chip->beep_mode = beep_mode[dev];
1915 #endif
1916
1917 /* create codec instances */
1918 err = azx_codec_create(chip, model[dev],
1919 azx_max_codecs[chip->driver_type],
1920 power_save_addr);
1921
1922 if (err < 0)
1923 goto out_free;
1924 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1925 if (chip->fw) {
1926 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1927 chip->fw->data);
1928 if (err < 0)
1929 goto out_free;
1930 #ifndef CONFIG_PM
1931 release_firmware(chip->fw); /* no longer needed */
1932 chip->fw = NULL;
1933 #endif
1934 }
1935 #endif
1936 if ((probe_only[dev] & 1) == 0) {
1937 err = azx_codec_configure(chip);
1938 if (err < 0)
1939 goto out_free;
1940 }
1941
1942 /* create PCM streams */
1943 err = snd_hda_build_pcms(chip->bus);
1944 if (err < 0)
1945 goto out_free;
1946
1947 /* create mixer controls */
1948 err = azx_mixer_create(chip);
1949 if (err < 0)
1950 goto out_free;
1951
1952 err = snd_card_register(chip->card);
1953 if (err < 0)
1954 goto out_free;
1955
1956 chip->running = 1;
1957 power_down_all_codecs(chip);
1958 azx_notifier_register(chip);
1959 azx_add_card_list(chip);
1960 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || hda->use_vga_switcheroo)
1961 pm_runtime_put_noidle(&pci->dev);
1962
1963 out_free:
1964 if (err < 0)
1965 hda->init_failed = 1;
1966 complete_all(&hda->probe_wait);
1967 return err;
1968 }
1969
1970 static void azx_remove(struct pci_dev *pci)
1971 {
1972 struct snd_card *card = pci_get_drvdata(pci);
1973
1974 if (card)
1975 snd_card_free(card);
1976 }
1977
1978 /* PCI IDs */
1979 static const struct pci_device_id azx_ids[] = {
1980 /* CPT */
1981 { PCI_DEVICE(0x8086, 0x1c20),
1982 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1983 /* PBG */
1984 { PCI_DEVICE(0x8086, 0x1d20),
1985 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1986 /* Panther Point */
1987 { PCI_DEVICE(0x8086, 0x1e20),
1988 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1989 /* Lynx Point */
1990 { PCI_DEVICE(0x8086, 0x8c20),
1991 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1992 /* 9 Series */
1993 { PCI_DEVICE(0x8086, 0x8ca0),
1994 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1995 /* Wellsburg */
1996 { PCI_DEVICE(0x8086, 0x8d20),
1997 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1998 { PCI_DEVICE(0x8086, 0x8d21),
1999 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2000 /* Lynx Point-LP */
2001 { PCI_DEVICE(0x8086, 0x9c20),
2002 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2003 /* Lynx Point-LP */
2004 { PCI_DEVICE(0x8086, 0x9c21),
2005 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2006 /* Wildcat Point-LP */
2007 { PCI_DEVICE(0x8086, 0x9ca0),
2008 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2009 /* Sunrise Point */
2010 { PCI_DEVICE(0x8086, 0xa170),
2011 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2012 /* Sunrise Point-LP */
2013 { PCI_DEVICE(0x8086, 0x9d70),
2014 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2015 /* Haswell */
2016 { PCI_DEVICE(0x8086, 0x0a0c),
2017 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2018 { PCI_DEVICE(0x8086, 0x0c0c),
2019 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2020 { PCI_DEVICE(0x8086, 0x0d0c),
2021 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2022 /* Broadwell */
2023 { PCI_DEVICE(0x8086, 0x160c),
2024 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2025 /* 5 Series/3400 */
2026 { PCI_DEVICE(0x8086, 0x3b56),
2027 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2028 /* Poulsbo */
2029 { PCI_DEVICE(0x8086, 0x811b),
2030 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2031 /* Oaktrail */
2032 { PCI_DEVICE(0x8086, 0x080a),
2033 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2034 /* BayTrail */
2035 { PCI_DEVICE(0x8086, 0x0f04),
2036 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2037 /* Braswell */
2038 { PCI_DEVICE(0x8086, 0x2284),
2039 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2040 /* ICH */
2041 { PCI_DEVICE(0x8086, 0x2668),
2042 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2043 AZX_DCAPS_BUFSIZE }, /* ICH6 */
2044 { PCI_DEVICE(0x8086, 0x27d8),
2045 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2046 AZX_DCAPS_BUFSIZE }, /* ICH7 */
2047 { PCI_DEVICE(0x8086, 0x269a),
2048 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2049 AZX_DCAPS_BUFSIZE }, /* ESB2 */
2050 { PCI_DEVICE(0x8086, 0x284b),
2051 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2052 AZX_DCAPS_BUFSIZE }, /* ICH8 */
2053 { PCI_DEVICE(0x8086, 0x293e),
2054 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2055 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2056 { PCI_DEVICE(0x8086, 0x293f),
2057 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2058 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2059 { PCI_DEVICE(0x8086, 0x3a3e),
2060 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2061 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2062 { PCI_DEVICE(0x8086, 0x3a6e),
2063 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2064 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2065 /* Generic Intel */
2066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2067 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2068 .class_mask = 0xffffff,
2069 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
2070 /* ATI SB 450/600/700/800/900 */
2071 { PCI_DEVICE(0x1002, 0x437b),
2072 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2073 { PCI_DEVICE(0x1002, 0x4383),
2074 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2075 /* AMD Hudson */
2076 { PCI_DEVICE(0x1022, 0x780d),
2077 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2078 /* ATI HDMI */
2079 { PCI_DEVICE(0x1002, 0x793b),
2080 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2081 { PCI_DEVICE(0x1002, 0x7919),
2082 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2083 { PCI_DEVICE(0x1002, 0x960f),
2084 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2085 { PCI_DEVICE(0x1002, 0x970f),
2086 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2087 { PCI_DEVICE(0x1002, 0xaa00),
2088 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2089 { PCI_DEVICE(0x1002, 0xaa08),
2090 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2091 { PCI_DEVICE(0x1002, 0xaa10),
2092 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2093 { PCI_DEVICE(0x1002, 0xaa18),
2094 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2095 { PCI_DEVICE(0x1002, 0xaa20),
2096 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2097 { PCI_DEVICE(0x1002, 0xaa28),
2098 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2099 { PCI_DEVICE(0x1002, 0xaa30),
2100 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2101 { PCI_DEVICE(0x1002, 0xaa38),
2102 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2103 { PCI_DEVICE(0x1002, 0xaa40),
2104 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2105 { PCI_DEVICE(0x1002, 0xaa48),
2106 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2107 { PCI_DEVICE(0x1002, 0xaa50),
2108 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2109 { PCI_DEVICE(0x1002, 0xaa58),
2110 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2111 { PCI_DEVICE(0x1002, 0xaa60),
2112 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2113 { PCI_DEVICE(0x1002, 0xaa68),
2114 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2115 { PCI_DEVICE(0x1002, 0xaa80),
2116 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2117 { PCI_DEVICE(0x1002, 0xaa88),
2118 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2119 { PCI_DEVICE(0x1002, 0xaa90),
2120 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2121 { PCI_DEVICE(0x1002, 0xaa98),
2122 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2123 { PCI_DEVICE(0x1002, 0x9902),
2124 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2125 { PCI_DEVICE(0x1002, 0xaaa0),
2126 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2127 { PCI_DEVICE(0x1002, 0xaaa8),
2128 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2129 { PCI_DEVICE(0x1002, 0xaab0),
2130 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2131 /* VIA VT8251/VT8237A */
2132 { PCI_DEVICE(0x1106, 0x3288),
2133 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2134 /* VIA GFX VT7122/VX900 */
2135 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2136 /* VIA GFX VT6122/VX11 */
2137 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2138 /* SIS966 */
2139 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2140 /* ULI M5461 */
2141 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2142 /* NVIDIA MCP */
2143 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2144 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2145 .class_mask = 0xffffff,
2146 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2147 /* Teradici */
2148 { PCI_DEVICE(0x6549, 0x1200),
2149 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2150 { PCI_DEVICE(0x6549, 0x2200),
2151 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2152 /* Creative X-Fi (CA0110-IBG) */
2153 /* CTHDA chips */
2154 { PCI_DEVICE(0x1102, 0x0010),
2155 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2156 { PCI_DEVICE(0x1102, 0x0012),
2157 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2158 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2159 /* the following entry conflicts with snd-ctxfi driver,
2160 * as ctxfi driver mutates from HD-audio to native mode with
2161 * a special command sequence.
2162 */
2163 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2164 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2165 .class_mask = 0xffffff,
2166 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2167 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2168 #else
2169 /* this entry seems still valid -- i.e. without emu20kx chip */
2170 { PCI_DEVICE(0x1102, 0x0009),
2171 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2172 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2173 #endif
2174 /* CM8888 */
2175 { PCI_DEVICE(0x13f6, 0x5011),
2176 .driver_data = AZX_DRIVER_CMEDIA |
2177 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2178 /* Vortex86MX */
2179 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2180 /* VMware HDAudio */
2181 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2182 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2183 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2184 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2185 .class_mask = 0xffffff,
2186 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2187 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2188 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2189 .class_mask = 0xffffff,
2190 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2191 { 0, }
2192 };
2193 MODULE_DEVICE_TABLE(pci, azx_ids);
2194
2195 /* pci_driver definition */
2196 static struct pci_driver azx_driver = {
2197 .name = KBUILD_MODNAME,
2198 .id_table = azx_ids,
2199 .probe = azx_probe,
2200 .remove = azx_remove,
2201 .driver = {
2202 .pm = AZX_PM_OPS,
2203 },
2204 };
2205
2206 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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