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propogate_mnt: Handle the first propogated copy being a slave
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <sound/hdaudio.h>
61 #include <sound/hda_i915.h>
62 #include <linux/vgaarb.h>
63 #include <linux/vga_switcheroo.h>
64 #include <linux/firmware.h>
65 #include "hda_codec.h"
66 #include "hda_controller.h"
67 #include "hda_intel.h"
68
69 #define CREATE_TRACE_POINTS
70 #include "hda_intel_trace.h"
71
72 /* position fix mode */
73 enum {
74 POS_FIX_AUTO,
75 POS_FIX_LPIB,
76 POS_FIX_POSBUF,
77 POS_FIX_VIACOMBO,
78 POS_FIX_COMBO,
79 };
80
81 /* Defines for ATI HD Audio support in SB450 south bridge */
82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
84
85 /* Defines for Nvidia HDA support */
86 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
87 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
88 #define NVIDIA_HDA_ISTRM_COH 0x4d
89 #define NVIDIA_HDA_OSTRM_COH 0x4c
90 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
91
92 /* Defines for Intel SCH HDA snoop control */
93 #define INTEL_HDA_CGCTL 0x48
94 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
95 #define INTEL_SCH_HDA_DEVC 0x78
96 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
97
98 /* Define IN stream 0 FIFO size offset in VIA controller */
99 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
100 /* Define VIA HD Audio Device ID*/
101 #define VIA_HDAC_DEVICE_ID 0x3288
102
103 /* max number of SDs */
104 /* ICH, ATI and VIA have 4 playback and 4 capture */
105 #define ICH6_NUM_CAPTURE 4
106 #define ICH6_NUM_PLAYBACK 4
107
108 /* ULI has 6 playback and 5 capture */
109 #define ULI_NUM_CAPTURE 5
110 #define ULI_NUM_PLAYBACK 6
111
112 /* ATI HDMI may have up to 8 playbacks and 0 capture */
113 #define ATIHDMI_NUM_CAPTURE 0
114 #define ATIHDMI_NUM_PLAYBACK 8
115
116 /* TERA has 4 playback and 3 capture */
117 #define TERA_NUM_CAPTURE 3
118 #define TERA_NUM_PLAYBACK 4
119
120
121 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
122 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
123 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
124 static char *model[SNDRV_CARDS];
125 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
126 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
127 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
128 static int probe_only[SNDRV_CARDS];
129 static int jackpoll_ms[SNDRV_CARDS];
130 static bool single_cmd;
131 static int enable_msi = -1;
132 #ifdef CONFIG_SND_HDA_PATCH_LOADER
133 static char *patch[SNDRV_CARDS];
134 #endif
135 #ifdef CONFIG_SND_HDA_INPUT_BEEP
136 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
137 CONFIG_SND_HDA_INPUT_BEEP_MODE};
138 #endif
139
140 module_param_array(index, int, NULL, 0444);
141 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
142 module_param_array(id, charp, NULL, 0444);
143 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
144 module_param_array(enable, bool, NULL, 0444);
145 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
146 module_param_array(model, charp, NULL, 0444);
147 MODULE_PARM_DESC(model, "Use the given board model.");
148 module_param_array(position_fix, int, NULL, 0444);
149 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
150 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
151 module_param_array(bdl_pos_adj, int, NULL, 0644);
152 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
153 module_param_array(probe_mask, int, NULL, 0444);
154 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
155 module_param_array(probe_only, int, NULL, 0444);
156 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
157 module_param_array(jackpoll_ms, int, NULL, 0444);
158 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
159 module_param(single_cmd, bool, 0444);
160 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
161 "(for debugging only).");
162 module_param(enable_msi, bint, 0444);
163 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
164 #ifdef CONFIG_SND_HDA_PATCH_LOADER
165 module_param_array(patch, charp, NULL, 0444);
166 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
167 #endif
168 #ifdef CONFIG_SND_HDA_INPUT_BEEP
169 module_param_array(beep_mode, bool, NULL, 0444);
170 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
171 "(0=off, 1=on) (default=1).");
172 #endif
173
174 #ifdef CONFIG_PM
175 static int param_set_xint(const char *val, const struct kernel_param *kp);
176 static const struct kernel_param_ops param_ops_xint = {
177 .set = param_set_xint,
178 .get = param_get_int,
179 };
180 #define param_check_xint param_check_int
181
182 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
183 module_param(power_save, xint, 0644);
184 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
185 "(in second, 0 = disable).");
186
187 /* reset the HD-audio controller in power save mode.
188 * this may give more power-saving, but will take longer time to
189 * wake up.
190 */
191 static bool power_save_controller = 1;
192 module_param(power_save_controller, bool, 0644);
193 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
194 #else
195 #define power_save 0
196 #endif /* CONFIG_PM */
197
198 static int align_buffer_size = -1;
199 module_param(align_buffer_size, bint, 0644);
200 MODULE_PARM_DESC(align_buffer_size,
201 "Force buffer and period sizes to be multiple of 128 bytes.");
202
203 #ifdef CONFIG_X86
204 static int hda_snoop = -1;
205 module_param_named(snoop, hda_snoop, bint, 0444);
206 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
207 #else
208 #define hda_snoop true
209 #endif
210
211
212 MODULE_LICENSE("GPL");
213 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
214 "{Intel, ICH6M},"
215 "{Intel, ICH7},"
216 "{Intel, ESB2},"
217 "{Intel, ICH8},"
218 "{Intel, ICH9},"
219 "{Intel, ICH10},"
220 "{Intel, PCH},"
221 "{Intel, CPT},"
222 "{Intel, PPT},"
223 "{Intel, LPT},"
224 "{Intel, LPT_LP},"
225 "{Intel, WPT_LP},"
226 "{Intel, SPT},"
227 "{Intel, SPT_LP},"
228 "{Intel, HPT},"
229 "{Intel, PBG},"
230 "{Intel, SCH},"
231 "{ATI, SB450},"
232 "{ATI, SB600},"
233 "{ATI, RS600},"
234 "{ATI, RS690},"
235 "{ATI, RS780},"
236 "{ATI, R600},"
237 "{ATI, RV630},"
238 "{ATI, RV610},"
239 "{ATI, RV670},"
240 "{ATI, RV635},"
241 "{ATI, RV620},"
242 "{ATI, RV770},"
243 "{VIA, VT8251},"
244 "{VIA, VT8237A},"
245 "{SiS, SIS966},"
246 "{ULI, M5461}}");
247 MODULE_DESCRIPTION("Intel HDA driver");
248
249 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
250 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
251 #define SUPPORT_VGA_SWITCHEROO
252 #endif
253 #endif
254
255
256 /*
257 */
258
259 /* driver types */
260 enum {
261 AZX_DRIVER_ICH,
262 AZX_DRIVER_PCH,
263 AZX_DRIVER_SCH,
264 AZX_DRIVER_HDMI,
265 AZX_DRIVER_ATI,
266 AZX_DRIVER_ATIHDMI,
267 AZX_DRIVER_ATIHDMI_NS,
268 AZX_DRIVER_VIA,
269 AZX_DRIVER_SIS,
270 AZX_DRIVER_ULI,
271 AZX_DRIVER_NVIDIA,
272 AZX_DRIVER_TERA,
273 AZX_DRIVER_CTX,
274 AZX_DRIVER_CTHDA,
275 AZX_DRIVER_CMEDIA,
276 AZX_DRIVER_GENERIC,
277 AZX_NUM_DRIVERS, /* keep this as last entry */
278 };
279
280 #define azx_get_snoop_type(chip) \
281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
283
284 /* quirks for old Intel chipsets */
285 #define AZX_DCAPS_INTEL_ICH \
286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
287
288 /* quirks for Intel PCH */
289 #define AZX_DCAPS_INTEL_PCH_BASE \
290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
291 AZX_DCAPS_SNOOP_TYPE(SCH))
292
293 /* PCH up to IVB; no runtime PM */
294 #define AZX_DCAPS_INTEL_PCH_NOPM \
295 (AZX_DCAPS_INTEL_PCH_BASE)
296
297 /* PCH for HSW/BDW; with runtime PM */
298 #define AZX_DCAPS_INTEL_PCH \
299 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
300
301 /* HSW HDMI */
302 #define AZX_DCAPS_INTEL_HASWELL \
303 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
304 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
305 AZX_DCAPS_SNOOP_TYPE(SCH))
306
307 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
308 #define AZX_DCAPS_INTEL_BROADWELL \
309 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
310 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
311 AZX_DCAPS_SNOOP_TYPE(SCH))
312
313 #define AZX_DCAPS_INTEL_BAYTRAIL \
314 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
315
316 #define AZX_DCAPS_INTEL_BRASWELL \
317 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
318
319 #define AZX_DCAPS_INTEL_SKYLAKE \
320 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
321 AZX_DCAPS_I915_POWERWELL)
322
323 #define AZX_DCAPS_INTEL_BROXTON \
324 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
325 AZX_DCAPS_I915_POWERWELL)
326
327 /* quirks for ATI SB / AMD Hudson */
328 #define AZX_DCAPS_PRESET_ATI_SB \
329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
330 AZX_DCAPS_SNOOP_TYPE(ATI))
331
332 /* quirks for ATI/AMD HDMI */
333 #define AZX_DCAPS_PRESET_ATI_HDMI \
334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
335 AZX_DCAPS_NO_MSI64)
336
337 /* quirks for ATI HDMI with snoop off */
338 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
339 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
340
341 /* quirks for Nvidia */
342 #define AZX_DCAPS_PRESET_NVIDIA \
343 (AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
344 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
345 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
346
347 #define AZX_DCAPS_PRESET_CTHDA \
348 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
349 AZX_DCAPS_NO_64BIT |\
350 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
351
352 /*
353 * vga_switcheroo support
354 */
355 #ifdef SUPPORT_VGA_SWITCHEROO
356 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
357 #else
358 #define use_vga_switcheroo(chip) 0
359 #endif
360
361 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
362 ((pci)->device == 0x0c0c) || \
363 ((pci)->device == 0x0d0c) || \
364 ((pci)->device == 0x160c))
365
366 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
367 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
368 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
369 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci))
370
371 static char *driver_short_names[] = {
372 [AZX_DRIVER_ICH] = "HDA Intel",
373 [AZX_DRIVER_PCH] = "HDA Intel PCH",
374 [AZX_DRIVER_SCH] = "HDA Intel MID",
375 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
376 [AZX_DRIVER_ATI] = "HDA ATI SB",
377 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
378 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
379 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
380 [AZX_DRIVER_SIS] = "HDA SIS966",
381 [AZX_DRIVER_ULI] = "HDA ULI M5461",
382 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
383 [AZX_DRIVER_TERA] = "HDA Teradici",
384 [AZX_DRIVER_CTX] = "HDA Creative",
385 [AZX_DRIVER_CTHDA] = "HDA Creative",
386 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
387 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
388 };
389
390 #ifdef CONFIG_X86
391 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
392 {
393 int pages;
394
395 if (azx_snoop(chip))
396 return;
397 if (!dmab || !dmab->area || !dmab->bytes)
398 return;
399
400 #ifdef CONFIG_SND_DMA_SGBUF
401 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
402 struct snd_sg_buf *sgbuf = dmab->private_data;
403 if (chip->driver_type == AZX_DRIVER_CMEDIA)
404 return; /* deal with only CORB/RIRB buffers */
405 if (on)
406 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
407 else
408 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
409 return;
410 }
411 #endif
412
413 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
414 if (on)
415 set_memory_wc((unsigned long)dmab->area, pages);
416 else
417 set_memory_wb((unsigned long)dmab->area, pages);
418 }
419
420 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
421 bool on)
422 {
423 __mark_pages_wc(chip, buf, on);
424 }
425 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
426 struct snd_pcm_substream *substream, bool on)
427 {
428 if (azx_dev->wc_marked != on) {
429 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
430 azx_dev->wc_marked = on;
431 }
432 }
433 #else
434 /* NOP for other archs */
435 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
436 bool on)
437 {
438 }
439 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
440 struct snd_pcm_substream *substream, bool on)
441 {
442 }
443 #endif
444
445 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
446
447 /*
448 * initialize the PCI registers
449 */
450 /* update bits in a PCI register byte */
451 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
452 unsigned char mask, unsigned char val)
453 {
454 unsigned char data;
455
456 pci_read_config_byte(pci, reg, &data);
457 data &= ~mask;
458 data |= (val & mask);
459 pci_write_config_byte(pci, reg, data);
460 }
461
462 static void azx_init_pci(struct azx *chip)
463 {
464 int snoop_type = azx_get_snoop_type(chip);
465
466 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
467 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
468 * Ensuring these bits are 0 clears playback static on some HD Audio
469 * codecs.
470 * The PCI register TCSEL is defined in the Intel manuals.
471 */
472 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
473 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
474 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
475 }
476
477 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
478 * we need to enable snoop.
479 */
480 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
481 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
482 azx_snoop(chip));
483 update_pci_byte(chip->pci,
484 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
485 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
486 }
487
488 /* For NVIDIA HDA, enable snoop */
489 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
490 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
491 azx_snoop(chip));
492 update_pci_byte(chip->pci,
493 NVIDIA_HDA_TRANSREG_ADDR,
494 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
495 update_pci_byte(chip->pci,
496 NVIDIA_HDA_ISTRM_COH,
497 0x01, NVIDIA_HDA_ENABLE_COHBIT);
498 update_pci_byte(chip->pci,
499 NVIDIA_HDA_OSTRM_COH,
500 0x01, NVIDIA_HDA_ENABLE_COHBIT);
501 }
502
503 /* Enable SCH/PCH snoop if needed */
504 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
505 unsigned short snoop;
506 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
507 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
508 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
509 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
510 if (!azx_snoop(chip))
511 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
512 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
513 pci_read_config_word(chip->pci,
514 INTEL_SCH_HDA_DEVC, &snoop);
515 }
516 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
517 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
518 "Disabled" : "Enabled");
519 }
520 }
521
522 /*
523 * In BXT-P A0, HD-Audio DMA requests is later than expected,
524 * and makes an audio stream sensitive to system latencies when
525 * 24/32 bits are playing.
526 * Adjusting threshold of DMA fifo to force the DMA request
527 * sooner to improve latency tolerance at the expense of power.
528 */
529 static void bxt_reduce_dma_latency(struct azx *chip)
530 {
531 u32 val;
532
533 val = azx_readl(chip, SKL_EM4L);
534 val &= (0x3 << 20);
535 azx_writel(chip, SKL_EM4L, val);
536 }
537
538 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
539 {
540 struct hdac_bus *bus = azx_bus(chip);
541 struct pci_dev *pci = chip->pci;
542 u32 val;
543
544 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
545 snd_hdac_set_codec_wakeup(bus, true);
546 if (IS_SKL_PLUS(pci)) {
547 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
548 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
549 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
550 }
551 azx_init_chip(chip, full_reset);
552 if (IS_SKL_PLUS(pci)) {
553 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
554 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
555 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
556 }
557 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
558 snd_hdac_set_codec_wakeup(bus, false);
559
560 /* reduce dma latency to avoid noise */
561 if (IS_BXT(pci))
562 bxt_reduce_dma_latency(chip);
563 }
564
565 /* calculate runtime delay from LPIB */
566 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
567 unsigned int pos)
568 {
569 struct snd_pcm_substream *substream = azx_dev->core.substream;
570 int stream = substream->stream;
571 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
572 int delay;
573
574 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
575 delay = pos - lpib_pos;
576 else
577 delay = lpib_pos - pos;
578 if (delay < 0) {
579 if (delay >= azx_dev->core.delay_negative_threshold)
580 delay = 0;
581 else
582 delay += azx_dev->core.bufsize;
583 }
584
585 if (delay >= azx_dev->core.period_bytes) {
586 dev_info(chip->card->dev,
587 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
588 delay, azx_dev->core.period_bytes);
589 delay = 0;
590 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
591 chip->get_delay[stream] = NULL;
592 }
593
594 return bytes_to_frames(substream->runtime, delay);
595 }
596
597 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
598
599 /* called from IRQ */
600 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
601 {
602 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
603 int ok;
604
605 ok = azx_position_ok(chip, azx_dev);
606 if (ok == 1) {
607 azx_dev->irq_pending = 0;
608 return ok;
609 } else if (ok == 0) {
610 /* bogus IRQ, process it later */
611 azx_dev->irq_pending = 1;
612 schedule_work(&hda->irq_pending_work);
613 }
614 return 0;
615 }
616
617 /* Enable/disable i915 display power for the link */
618 static int azx_intel_link_power(struct azx *chip, bool enable)
619 {
620 struct hdac_bus *bus = azx_bus(chip);
621
622 return snd_hdac_display_power(bus, enable);
623 }
624
625 /*
626 * Check whether the current DMA position is acceptable for updating
627 * periods. Returns non-zero if it's OK.
628 *
629 * Many HD-audio controllers appear pretty inaccurate about
630 * the update-IRQ timing. The IRQ is issued before actually the
631 * data is processed. So, we need to process it afterwords in a
632 * workqueue.
633 */
634 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
635 {
636 struct snd_pcm_substream *substream = azx_dev->core.substream;
637 int stream = substream->stream;
638 u32 wallclk;
639 unsigned int pos;
640
641 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
642 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
643 return -1; /* bogus (too early) interrupt */
644
645 if (chip->get_position[stream])
646 pos = chip->get_position[stream](chip, azx_dev);
647 else { /* use the position buffer as default */
648 pos = azx_get_pos_posbuf(chip, azx_dev);
649 if (!pos || pos == (u32)-1) {
650 dev_info(chip->card->dev,
651 "Invalid position buffer, using LPIB read method instead.\n");
652 chip->get_position[stream] = azx_get_pos_lpib;
653 if (chip->get_position[0] == azx_get_pos_lpib &&
654 chip->get_position[1] == azx_get_pos_lpib)
655 azx_bus(chip)->use_posbuf = false;
656 pos = azx_get_pos_lpib(chip, azx_dev);
657 chip->get_delay[stream] = NULL;
658 } else {
659 chip->get_position[stream] = azx_get_pos_posbuf;
660 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
661 chip->get_delay[stream] = azx_get_delay_from_lpib;
662 }
663 }
664
665 if (pos >= azx_dev->core.bufsize)
666 pos = 0;
667
668 if (WARN_ONCE(!azx_dev->core.period_bytes,
669 "hda-intel: zero azx_dev->period_bytes"))
670 return -1; /* this shouldn't happen! */
671 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
672 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
673 /* NG - it's below the first next period boundary */
674 return chip->bdl_pos_adj ? 0 : -1;
675 azx_dev->core.start_wallclk += wallclk;
676 return 1; /* OK, it's fine */
677 }
678
679 /*
680 * The work for pending PCM period updates.
681 */
682 static void azx_irq_pending_work(struct work_struct *work)
683 {
684 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
685 struct azx *chip = &hda->chip;
686 struct hdac_bus *bus = azx_bus(chip);
687 struct hdac_stream *s;
688 int pending, ok;
689
690 if (!hda->irq_pending_warned) {
691 dev_info(chip->card->dev,
692 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
693 chip->card->number);
694 hda->irq_pending_warned = 1;
695 }
696
697 for (;;) {
698 pending = 0;
699 spin_lock_irq(&bus->reg_lock);
700 list_for_each_entry(s, &bus->stream_list, list) {
701 struct azx_dev *azx_dev = stream_to_azx_dev(s);
702 if (!azx_dev->irq_pending ||
703 !s->substream ||
704 !s->running)
705 continue;
706 ok = azx_position_ok(chip, azx_dev);
707 if (ok > 0) {
708 azx_dev->irq_pending = 0;
709 spin_unlock(&bus->reg_lock);
710 snd_pcm_period_elapsed(s->substream);
711 spin_lock(&bus->reg_lock);
712 } else if (ok < 0) {
713 pending = 0; /* too early */
714 } else
715 pending++;
716 }
717 spin_unlock_irq(&bus->reg_lock);
718 if (!pending)
719 return;
720 msleep(1);
721 }
722 }
723
724 /* clear irq_pending flags and assure no on-going workq */
725 static void azx_clear_irq_pending(struct azx *chip)
726 {
727 struct hdac_bus *bus = azx_bus(chip);
728 struct hdac_stream *s;
729
730 spin_lock_irq(&bus->reg_lock);
731 list_for_each_entry(s, &bus->stream_list, list) {
732 struct azx_dev *azx_dev = stream_to_azx_dev(s);
733 azx_dev->irq_pending = 0;
734 }
735 spin_unlock_irq(&bus->reg_lock);
736 }
737
738 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
739 {
740 struct hdac_bus *bus = azx_bus(chip);
741
742 if (request_irq(chip->pci->irq, azx_interrupt,
743 chip->msi ? 0 : IRQF_SHARED,
744 chip->card->irq_descr, chip)) {
745 dev_err(chip->card->dev,
746 "unable to grab IRQ %d, disabling device\n",
747 chip->pci->irq);
748 if (do_disconnect)
749 snd_card_disconnect(chip->card);
750 return -1;
751 }
752 bus->irq = chip->pci->irq;
753 pci_intx(chip->pci, !chip->msi);
754 return 0;
755 }
756
757 /* get the current DMA position with correction on VIA chips */
758 static unsigned int azx_via_get_position(struct azx *chip,
759 struct azx_dev *azx_dev)
760 {
761 unsigned int link_pos, mini_pos, bound_pos;
762 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
763 unsigned int fifo_size;
764
765 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
766 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
767 /* Playback, no problem using link position */
768 return link_pos;
769 }
770
771 /* Capture */
772 /* For new chipset,
773 * use mod to get the DMA position just like old chipset
774 */
775 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
776 mod_dma_pos %= azx_dev->core.period_bytes;
777
778 /* azx_dev->fifo_size can't get FIFO size of in stream.
779 * Get from base address + offset.
780 */
781 fifo_size = readw(azx_bus(chip)->remap_addr +
782 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
783
784 if (azx_dev->insufficient) {
785 /* Link position never gather than FIFO size */
786 if (link_pos <= fifo_size)
787 return 0;
788
789 azx_dev->insufficient = 0;
790 }
791
792 if (link_pos <= fifo_size)
793 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
794 else
795 mini_pos = link_pos - fifo_size;
796
797 /* Find nearest previous boudary */
798 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
799 mod_link_pos = link_pos % azx_dev->core.period_bytes;
800 if (mod_link_pos >= fifo_size)
801 bound_pos = link_pos - mod_link_pos;
802 else if (mod_dma_pos >= mod_mini_pos)
803 bound_pos = mini_pos - mod_mini_pos;
804 else {
805 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
806 if (bound_pos >= azx_dev->core.bufsize)
807 bound_pos = 0;
808 }
809
810 /* Calculate real DMA position we want */
811 return bound_pos + mod_dma_pos;
812 }
813
814 #ifdef CONFIG_PM
815 static DEFINE_MUTEX(card_list_lock);
816 static LIST_HEAD(card_list);
817
818 static void azx_add_card_list(struct azx *chip)
819 {
820 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
821 mutex_lock(&card_list_lock);
822 list_add(&hda->list, &card_list);
823 mutex_unlock(&card_list_lock);
824 }
825
826 static void azx_del_card_list(struct azx *chip)
827 {
828 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
829 mutex_lock(&card_list_lock);
830 list_del_init(&hda->list);
831 mutex_unlock(&card_list_lock);
832 }
833
834 /* trigger power-save check at writing parameter */
835 static int param_set_xint(const char *val, const struct kernel_param *kp)
836 {
837 struct hda_intel *hda;
838 struct azx *chip;
839 int prev = power_save;
840 int ret = param_set_int(val, kp);
841
842 if (ret || prev == power_save)
843 return ret;
844
845 mutex_lock(&card_list_lock);
846 list_for_each_entry(hda, &card_list, list) {
847 chip = &hda->chip;
848 if (!hda->probe_continued || chip->disabled)
849 continue;
850 snd_hda_set_power_save(&chip->bus, power_save * 1000);
851 }
852 mutex_unlock(&card_list_lock);
853 return 0;
854 }
855 #else
856 #define azx_add_card_list(chip) /* NOP */
857 #define azx_del_card_list(chip) /* NOP */
858 #endif /* CONFIG_PM */
859
860 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
861 * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
862 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
863 * BCLK = CDCLK * M / N
864 * The values will be lost when the display power well is disabled and need to
865 * be restored to avoid abnormal playback speed.
866 */
867 static void haswell_set_bclk(struct hda_intel *hda)
868 {
869 struct azx *chip = &hda->chip;
870 int cdclk_freq;
871 unsigned int bclk_m, bclk_n;
872
873 if (!hda->need_i915_power)
874 return;
875
876 cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
877 switch (cdclk_freq) {
878 case 337500:
879 bclk_m = 16;
880 bclk_n = 225;
881 break;
882
883 case 450000:
884 default: /* default CDCLK 450MHz */
885 bclk_m = 4;
886 bclk_n = 75;
887 break;
888
889 case 540000:
890 bclk_m = 4;
891 bclk_n = 90;
892 break;
893
894 case 675000:
895 bclk_m = 8;
896 bclk_n = 225;
897 break;
898 }
899
900 azx_writew(chip, HSW_EM4, bclk_m);
901 azx_writew(chip, HSW_EM5, bclk_n);
902 }
903
904 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
905 /*
906 * power management
907 */
908 static int azx_suspend(struct device *dev)
909 {
910 struct snd_card *card = dev_get_drvdata(dev);
911 struct azx *chip;
912 struct hda_intel *hda;
913 struct hdac_bus *bus;
914
915 if (!card)
916 return 0;
917
918 chip = card->private_data;
919 hda = container_of(chip, struct hda_intel, chip);
920 if (chip->disabled || hda->init_failed || !chip->running)
921 return 0;
922
923 bus = azx_bus(chip);
924 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
925 azx_clear_irq_pending(chip);
926 azx_stop_chip(chip);
927 azx_enter_link_reset(chip);
928 if (bus->irq >= 0) {
929 free_irq(bus->irq, chip);
930 bus->irq = -1;
931 }
932
933 if (chip->msi)
934 pci_disable_msi(chip->pci);
935 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
936 && hda->need_i915_power)
937 snd_hdac_display_power(bus, false);
938
939 trace_azx_suspend(chip);
940 return 0;
941 }
942
943 static int azx_resume(struct device *dev)
944 {
945 struct pci_dev *pci = to_pci_dev(dev);
946 struct snd_card *card = dev_get_drvdata(dev);
947 struct azx *chip;
948 struct hda_intel *hda;
949
950 if (!card)
951 return 0;
952
953 chip = card->private_data;
954 hda = container_of(chip, struct hda_intel, chip);
955 if (chip->disabled || hda->init_failed || !chip->running)
956 return 0;
957
958 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
959 && hda->need_i915_power) {
960 snd_hdac_display_power(azx_bus(chip), true);
961 haswell_set_bclk(hda);
962 }
963 if (chip->msi)
964 if (pci_enable_msi(pci) < 0)
965 chip->msi = 0;
966 if (azx_acquire_irq(chip, 1) < 0)
967 return -EIO;
968 azx_init_pci(chip);
969
970 hda_intel_init_chip(chip, true);
971
972 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
973
974 trace_azx_resume(chip);
975 return 0;
976 }
977 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
978
979 #ifdef CONFIG_PM_SLEEP
980 /* put codec down to D3 at hibernation for Intel SKL+;
981 * otherwise BIOS may still access the codec and screw up the driver
982 */
983 static int azx_freeze_noirq(struct device *dev)
984 {
985 struct pci_dev *pci = to_pci_dev(dev);
986
987 if (IS_SKL_PLUS(pci))
988 pci_set_power_state(pci, PCI_D3hot);
989
990 return 0;
991 }
992
993 static int azx_thaw_noirq(struct device *dev)
994 {
995 struct pci_dev *pci = to_pci_dev(dev);
996
997 if (IS_SKL_PLUS(pci))
998 pci_set_power_state(pci, PCI_D0);
999
1000 return 0;
1001 }
1002 #endif /* CONFIG_PM_SLEEP */
1003
1004 #ifdef CONFIG_PM
1005 static int azx_runtime_suspend(struct device *dev)
1006 {
1007 struct snd_card *card = dev_get_drvdata(dev);
1008 struct azx *chip;
1009 struct hda_intel *hda;
1010
1011 if (!card)
1012 return 0;
1013
1014 chip = card->private_data;
1015 hda = container_of(chip, struct hda_intel, chip);
1016 if (chip->disabled || hda->init_failed)
1017 return 0;
1018
1019 if (!azx_has_pm_runtime(chip))
1020 return 0;
1021
1022 /* enable controller wake up event */
1023 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1024 STATESTS_INT_MASK);
1025
1026 azx_stop_chip(chip);
1027 azx_enter_link_reset(chip);
1028 azx_clear_irq_pending(chip);
1029 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1030 && hda->need_i915_power)
1031 snd_hdac_display_power(azx_bus(chip), false);
1032
1033 trace_azx_runtime_suspend(chip);
1034 return 0;
1035 }
1036
1037 static int azx_runtime_resume(struct device *dev)
1038 {
1039 struct snd_card *card = dev_get_drvdata(dev);
1040 struct azx *chip;
1041 struct hda_intel *hda;
1042 struct hdac_bus *bus;
1043 struct hda_codec *codec;
1044 int status;
1045
1046 if (!card)
1047 return 0;
1048
1049 chip = card->private_data;
1050 hda = container_of(chip, struct hda_intel, chip);
1051 if (chip->disabled || hda->init_failed)
1052 return 0;
1053
1054 if (!azx_has_pm_runtime(chip))
1055 return 0;
1056
1057 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1058 bus = azx_bus(chip);
1059 if (hda->need_i915_power) {
1060 snd_hdac_display_power(bus, true);
1061 haswell_set_bclk(hda);
1062 } else {
1063 /* toggle codec wakeup bit for STATESTS read */
1064 snd_hdac_set_codec_wakeup(bus, true);
1065 snd_hdac_set_codec_wakeup(bus, false);
1066 }
1067 }
1068
1069 /* Read STATESTS before controller reset */
1070 status = azx_readw(chip, STATESTS);
1071
1072 azx_init_pci(chip);
1073 hda_intel_init_chip(chip, true);
1074
1075 if (status) {
1076 list_for_each_codec(codec, &chip->bus)
1077 if (status & (1 << codec->addr))
1078 schedule_delayed_work(&codec->jackpoll_work,
1079 codec->jackpoll_interval);
1080 }
1081
1082 /* disable controller Wake Up event*/
1083 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1084 ~STATESTS_INT_MASK);
1085
1086 trace_azx_runtime_resume(chip);
1087 return 0;
1088 }
1089
1090 static int azx_runtime_idle(struct device *dev)
1091 {
1092 struct snd_card *card = dev_get_drvdata(dev);
1093 struct azx *chip;
1094 struct hda_intel *hda;
1095
1096 if (!card)
1097 return 0;
1098
1099 chip = card->private_data;
1100 hda = container_of(chip, struct hda_intel, chip);
1101 if (chip->disabled || hda->init_failed)
1102 return 0;
1103
1104 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1105 azx_bus(chip)->codec_powered || !chip->running)
1106 return -EBUSY;
1107
1108 return 0;
1109 }
1110
1111 static const struct dev_pm_ops azx_pm = {
1112 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1113 #ifdef CONFIG_PM_SLEEP
1114 .freeze_noirq = azx_freeze_noirq,
1115 .thaw_noirq = azx_thaw_noirq,
1116 #endif
1117 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1118 };
1119
1120 #define AZX_PM_OPS &azx_pm
1121 #else
1122 #define AZX_PM_OPS NULL
1123 #endif /* CONFIG_PM */
1124
1125
1126 static int azx_probe_continue(struct azx *chip);
1127
1128 #ifdef SUPPORT_VGA_SWITCHEROO
1129 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1130
1131 static void azx_vs_set_state(struct pci_dev *pci,
1132 enum vga_switcheroo_state state)
1133 {
1134 struct snd_card *card = pci_get_drvdata(pci);
1135 struct azx *chip = card->private_data;
1136 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1137 bool disabled;
1138
1139 wait_for_completion(&hda->probe_wait);
1140 if (hda->init_failed)
1141 return;
1142
1143 disabled = (state == VGA_SWITCHEROO_OFF);
1144 if (chip->disabled == disabled)
1145 return;
1146
1147 if (!hda->probe_continued) {
1148 chip->disabled = disabled;
1149 if (!disabled) {
1150 dev_info(chip->card->dev,
1151 "Start delayed initialization\n");
1152 if (azx_probe_continue(chip) < 0) {
1153 dev_err(chip->card->dev, "initialization error\n");
1154 hda->init_failed = true;
1155 }
1156 }
1157 } else {
1158 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1159 disabled ? "Disabling" : "Enabling");
1160 if (disabled) {
1161 pm_runtime_put_sync_suspend(card->dev);
1162 azx_suspend(card->dev);
1163 /* when we get suspended by vga_switcheroo we end up in D3cold,
1164 * however we have no ACPI handle, so pci/acpi can't put us there,
1165 * put ourselves there */
1166 pci->current_state = PCI_D3cold;
1167 chip->disabled = true;
1168 if (snd_hda_lock_devices(&chip->bus))
1169 dev_warn(chip->card->dev,
1170 "Cannot lock devices!\n");
1171 } else {
1172 snd_hda_unlock_devices(&chip->bus);
1173 pm_runtime_get_noresume(card->dev);
1174 chip->disabled = false;
1175 azx_resume(card->dev);
1176 }
1177 }
1178 }
1179
1180 static bool azx_vs_can_switch(struct pci_dev *pci)
1181 {
1182 struct snd_card *card = pci_get_drvdata(pci);
1183 struct azx *chip = card->private_data;
1184 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1185
1186 wait_for_completion(&hda->probe_wait);
1187 if (hda->init_failed)
1188 return false;
1189 if (chip->disabled || !hda->probe_continued)
1190 return true;
1191 if (snd_hda_lock_devices(&chip->bus))
1192 return false;
1193 snd_hda_unlock_devices(&chip->bus);
1194 return true;
1195 }
1196
1197 static void init_vga_switcheroo(struct azx *chip)
1198 {
1199 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1200 struct pci_dev *p = get_bound_vga(chip->pci);
1201 if (p) {
1202 dev_info(chip->card->dev,
1203 "Handle vga_switcheroo audio client\n");
1204 hda->use_vga_switcheroo = 1;
1205 pci_dev_put(p);
1206 }
1207 }
1208
1209 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1210 .set_gpu_state = azx_vs_set_state,
1211 .can_switch = azx_vs_can_switch,
1212 };
1213
1214 static int register_vga_switcheroo(struct azx *chip)
1215 {
1216 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1217 int err;
1218
1219 if (!hda->use_vga_switcheroo)
1220 return 0;
1221 /* FIXME: currently only handling DIS controller
1222 * is there any machine with two switchable HDMI audio controllers?
1223 */
1224 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1225 VGA_SWITCHEROO_DIS);
1226 if (err < 0)
1227 return err;
1228 hda->vga_switcheroo_registered = 1;
1229
1230 /* register as an optimus hdmi audio power domain */
1231 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1232 &hda->hdmi_pm_domain);
1233 return 0;
1234 }
1235 #else
1236 #define init_vga_switcheroo(chip) /* NOP */
1237 #define register_vga_switcheroo(chip) 0
1238 #define check_hdmi_disabled(pci) false
1239 #endif /* SUPPORT_VGA_SWITCHER */
1240
1241 /*
1242 * destructor
1243 */
1244 static int azx_free(struct azx *chip)
1245 {
1246 struct pci_dev *pci = chip->pci;
1247 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1248 struct hdac_bus *bus = azx_bus(chip);
1249
1250 if (azx_has_pm_runtime(chip) && chip->running)
1251 pm_runtime_get_noresume(&pci->dev);
1252
1253 azx_del_card_list(chip);
1254
1255 hda->init_failed = 1; /* to be sure */
1256 complete_all(&hda->probe_wait);
1257
1258 if (use_vga_switcheroo(hda)) {
1259 if (chip->disabled && hda->probe_continued)
1260 snd_hda_unlock_devices(&chip->bus);
1261 if (hda->vga_switcheroo_registered)
1262 vga_switcheroo_unregister_client(chip->pci);
1263 }
1264
1265 if (bus->chip_init) {
1266 azx_clear_irq_pending(chip);
1267 azx_stop_all_streams(chip);
1268 azx_stop_chip(chip);
1269 }
1270
1271 if (bus->irq >= 0)
1272 free_irq(bus->irq, (void*)chip);
1273 if (chip->msi)
1274 pci_disable_msi(chip->pci);
1275 iounmap(bus->remap_addr);
1276
1277 azx_free_stream_pages(chip);
1278 azx_free_streams(chip);
1279 snd_hdac_bus_exit(bus);
1280
1281 if (chip->region_requested)
1282 pci_release_regions(chip->pci);
1283
1284 pci_disable_device(chip->pci);
1285 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1286 release_firmware(chip->fw);
1287 #endif
1288
1289 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1290 if (hda->need_i915_power)
1291 snd_hdac_display_power(bus, false);
1292 snd_hdac_i915_exit(bus);
1293 }
1294 kfree(hda);
1295
1296 return 0;
1297 }
1298
1299 static int azx_dev_disconnect(struct snd_device *device)
1300 {
1301 struct azx *chip = device->device_data;
1302
1303 chip->bus.shutdown = 1;
1304 return 0;
1305 }
1306
1307 static int azx_dev_free(struct snd_device *device)
1308 {
1309 return azx_free(device->device_data);
1310 }
1311
1312 #ifdef SUPPORT_VGA_SWITCHEROO
1313 /*
1314 * Check of disabled HDMI controller by vga_switcheroo
1315 */
1316 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1317 {
1318 struct pci_dev *p;
1319
1320 /* check only discrete GPU */
1321 switch (pci->vendor) {
1322 case PCI_VENDOR_ID_ATI:
1323 case PCI_VENDOR_ID_AMD:
1324 case PCI_VENDOR_ID_NVIDIA:
1325 if (pci->devfn == 1) {
1326 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1327 pci->bus->number, 0);
1328 if (p) {
1329 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1330 return p;
1331 pci_dev_put(p);
1332 }
1333 }
1334 break;
1335 }
1336 return NULL;
1337 }
1338
1339 static bool check_hdmi_disabled(struct pci_dev *pci)
1340 {
1341 bool vga_inactive = false;
1342 struct pci_dev *p = get_bound_vga(pci);
1343
1344 if (p) {
1345 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1346 vga_inactive = true;
1347 pci_dev_put(p);
1348 }
1349 return vga_inactive;
1350 }
1351 #endif /* SUPPORT_VGA_SWITCHEROO */
1352
1353 /*
1354 * white/black-listing for position_fix
1355 */
1356 static struct snd_pci_quirk position_fix_list[] = {
1357 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1358 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1359 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1360 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1361 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1362 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1363 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1364 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1365 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1366 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1367 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1368 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1369 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1370 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1371 {}
1372 };
1373
1374 static int check_position_fix(struct azx *chip, int fix)
1375 {
1376 const struct snd_pci_quirk *q;
1377
1378 switch (fix) {
1379 case POS_FIX_AUTO:
1380 case POS_FIX_LPIB:
1381 case POS_FIX_POSBUF:
1382 case POS_FIX_VIACOMBO:
1383 case POS_FIX_COMBO:
1384 return fix;
1385 }
1386
1387 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1388 if (q) {
1389 dev_info(chip->card->dev,
1390 "position_fix set to %d for device %04x:%04x\n",
1391 q->value, q->subvendor, q->subdevice);
1392 return q->value;
1393 }
1394
1395 /* Check VIA/ATI HD Audio Controller exist */
1396 if (chip->driver_type == AZX_DRIVER_VIA) {
1397 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1398 return POS_FIX_VIACOMBO;
1399 }
1400 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1401 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1402 return POS_FIX_LPIB;
1403 }
1404 return POS_FIX_AUTO;
1405 }
1406
1407 static void assign_position_fix(struct azx *chip, int fix)
1408 {
1409 static azx_get_pos_callback_t callbacks[] = {
1410 [POS_FIX_AUTO] = NULL,
1411 [POS_FIX_LPIB] = azx_get_pos_lpib,
1412 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1413 [POS_FIX_VIACOMBO] = azx_via_get_position,
1414 [POS_FIX_COMBO] = azx_get_pos_lpib,
1415 };
1416
1417 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1418
1419 /* combo mode uses LPIB only for playback */
1420 if (fix == POS_FIX_COMBO)
1421 chip->get_position[1] = NULL;
1422
1423 if (fix == POS_FIX_POSBUF &&
1424 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1425 chip->get_delay[0] = chip->get_delay[1] =
1426 azx_get_delay_from_lpib;
1427 }
1428
1429 }
1430
1431 /*
1432 * black-lists for probe_mask
1433 */
1434 static struct snd_pci_quirk probe_mask_list[] = {
1435 /* Thinkpad often breaks the controller communication when accessing
1436 * to the non-working (or non-existing) modem codec slot.
1437 */
1438 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1439 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1440 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1441 /* broken BIOS */
1442 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1443 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1444 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1445 /* forced codec slots */
1446 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1447 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1448 /* WinFast VP200 H (Teradici) user reported broken communication */
1449 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1450 {}
1451 };
1452
1453 #define AZX_FORCE_CODEC_MASK 0x100
1454
1455 static void check_probe_mask(struct azx *chip, int dev)
1456 {
1457 const struct snd_pci_quirk *q;
1458
1459 chip->codec_probe_mask = probe_mask[dev];
1460 if (chip->codec_probe_mask == -1) {
1461 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1462 if (q) {
1463 dev_info(chip->card->dev,
1464 "probe_mask set to 0x%x for device %04x:%04x\n",
1465 q->value, q->subvendor, q->subdevice);
1466 chip->codec_probe_mask = q->value;
1467 }
1468 }
1469
1470 /* check forced option */
1471 if (chip->codec_probe_mask != -1 &&
1472 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1473 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1474 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1475 (int)azx_bus(chip)->codec_mask);
1476 }
1477 }
1478
1479 /*
1480 * white/black-list for enable_msi
1481 */
1482 static struct snd_pci_quirk msi_black_list[] = {
1483 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1484 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1485 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1486 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1487 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1488 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1489 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1490 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1491 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1492 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1493 {}
1494 };
1495
1496 static void check_msi(struct azx *chip)
1497 {
1498 const struct snd_pci_quirk *q;
1499
1500 if (enable_msi >= 0) {
1501 chip->msi = !!enable_msi;
1502 return;
1503 }
1504 chip->msi = 1; /* enable MSI as default */
1505 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1506 if (q) {
1507 dev_info(chip->card->dev,
1508 "msi for device %04x:%04x set to %d\n",
1509 q->subvendor, q->subdevice, q->value);
1510 chip->msi = q->value;
1511 return;
1512 }
1513
1514 /* NVidia chipsets seem to cause troubles with MSI */
1515 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1516 dev_info(chip->card->dev, "Disabling MSI\n");
1517 chip->msi = 0;
1518 }
1519 }
1520
1521 /* check the snoop mode availability */
1522 static void azx_check_snoop_available(struct azx *chip)
1523 {
1524 int snoop = hda_snoop;
1525
1526 if (snoop >= 0) {
1527 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1528 snoop ? "snoop" : "non-snoop");
1529 chip->snoop = snoop;
1530 return;
1531 }
1532
1533 snoop = true;
1534 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1535 chip->driver_type == AZX_DRIVER_VIA) {
1536 /* force to non-snoop mode for a new VIA controller
1537 * when BIOS is set
1538 */
1539 u8 val;
1540 pci_read_config_byte(chip->pci, 0x42, &val);
1541 if (!(val & 0x80) && chip->pci->revision == 0x30)
1542 snoop = false;
1543 }
1544
1545 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1546 snoop = false;
1547
1548 chip->snoop = snoop;
1549 if (!snoop)
1550 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1551 }
1552
1553 static void azx_probe_work(struct work_struct *work)
1554 {
1555 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1556 azx_probe_continue(&hda->chip);
1557 }
1558
1559 static int default_bdl_pos_adj(struct azx *chip)
1560 {
1561 /* some exceptions: Atoms seem problematic with value 1 */
1562 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1563 switch (chip->pci->device) {
1564 case 0x0f04: /* Baytrail */
1565 case 0x2284: /* Braswell */
1566 return 32;
1567 }
1568 }
1569
1570 switch (chip->driver_type) {
1571 case AZX_DRIVER_ICH:
1572 case AZX_DRIVER_PCH:
1573 return 1;
1574 default:
1575 return 32;
1576 }
1577 }
1578
1579 /*
1580 * constructor
1581 */
1582 static const struct hdac_io_ops pci_hda_io_ops;
1583 static const struct hda_controller_ops pci_hda_ops;
1584
1585 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1586 int dev, unsigned int driver_caps,
1587 struct azx **rchip)
1588 {
1589 static struct snd_device_ops ops = {
1590 .dev_disconnect = azx_dev_disconnect,
1591 .dev_free = azx_dev_free,
1592 };
1593 struct hda_intel *hda;
1594 struct azx *chip;
1595 int err;
1596
1597 *rchip = NULL;
1598
1599 err = pci_enable_device(pci);
1600 if (err < 0)
1601 return err;
1602
1603 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1604 if (!hda) {
1605 pci_disable_device(pci);
1606 return -ENOMEM;
1607 }
1608
1609 chip = &hda->chip;
1610 mutex_init(&chip->open_mutex);
1611 chip->card = card;
1612 chip->pci = pci;
1613 chip->ops = &pci_hda_ops;
1614 chip->driver_caps = driver_caps;
1615 chip->driver_type = driver_caps & 0xff;
1616 check_msi(chip);
1617 chip->dev_index = dev;
1618 chip->jackpoll_ms = jackpoll_ms;
1619 INIT_LIST_HEAD(&chip->pcm_list);
1620 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1621 INIT_LIST_HEAD(&hda->list);
1622 init_vga_switcheroo(chip);
1623 init_completion(&hda->probe_wait);
1624
1625 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1626
1627 check_probe_mask(chip, dev);
1628
1629 chip->single_cmd = single_cmd;
1630 azx_check_snoop_available(chip);
1631
1632 if (bdl_pos_adj[dev] < 0)
1633 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1634 else
1635 chip->bdl_pos_adj = bdl_pos_adj[dev];
1636
1637 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1638 if (err < 0) {
1639 kfree(hda);
1640 pci_disable_device(pci);
1641 return err;
1642 }
1643
1644 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1645 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1646 chip->bus.needs_damn_long_delay = 1;
1647 }
1648
1649 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1650 if (err < 0) {
1651 dev_err(card->dev, "Error creating device [card]!\n");
1652 azx_free(chip);
1653 return err;
1654 }
1655
1656 /* continue probing in work context as may trigger request module */
1657 INIT_WORK(&hda->probe_work, azx_probe_work);
1658
1659 *rchip = chip;
1660
1661 return 0;
1662 }
1663
1664 static int azx_first_init(struct azx *chip)
1665 {
1666 int dev = chip->dev_index;
1667 struct pci_dev *pci = chip->pci;
1668 struct snd_card *card = chip->card;
1669 struct hdac_bus *bus = azx_bus(chip);
1670 int err;
1671 unsigned short gcap;
1672 unsigned int dma_bits = 64;
1673
1674 #if BITS_PER_LONG != 64
1675 /* Fix up base address on ULI M5461 */
1676 if (chip->driver_type == AZX_DRIVER_ULI) {
1677 u16 tmp3;
1678 pci_read_config_word(pci, 0x40, &tmp3);
1679 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1680 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1681 }
1682 #endif
1683
1684 err = pci_request_regions(pci, "ICH HD audio");
1685 if (err < 0)
1686 return err;
1687 chip->region_requested = 1;
1688
1689 bus->addr = pci_resource_start(pci, 0);
1690 bus->remap_addr = pci_ioremap_bar(pci, 0);
1691 if (bus->remap_addr == NULL) {
1692 dev_err(card->dev, "ioremap error\n");
1693 return -ENXIO;
1694 }
1695
1696 if (chip->msi) {
1697 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1698 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1699 pci->no_64bit_msi = true;
1700 }
1701 if (pci_enable_msi(pci) < 0)
1702 chip->msi = 0;
1703 }
1704
1705 if (azx_acquire_irq(chip, 0) < 0)
1706 return -EBUSY;
1707
1708 pci_set_master(pci);
1709 synchronize_irq(bus->irq);
1710
1711 gcap = azx_readw(chip, GCAP);
1712 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1713
1714 /* AMD devices support 40 or 48bit DMA, take the safe one */
1715 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1716 dma_bits = 40;
1717
1718 /* disable SB600 64bit support for safety */
1719 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1720 struct pci_dev *p_smbus;
1721 dma_bits = 40;
1722 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1723 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1724 NULL);
1725 if (p_smbus) {
1726 if (p_smbus->revision < 0x30)
1727 gcap &= ~AZX_GCAP_64OK;
1728 pci_dev_put(p_smbus);
1729 }
1730 }
1731
1732 /* disable 64bit DMA address on some devices */
1733 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1734 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1735 gcap &= ~AZX_GCAP_64OK;
1736 }
1737
1738 /* disable buffer size rounding to 128-byte multiples if supported */
1739 if (align_buffer_size >= 0)
1740 chip->align_buffer_size = !!align_buffer_size;
1741 else {
1742 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1743 chip->align_buffer_size = 0;
1744 else
1745 chip->align_buffer_size = 1;
1746 }
1747
1748 /* allow 64bit DMA address if supported by H/W */
1749 if (!(gcap & AZX_GCAP_64OK))
1750 dma_bits = 32;
1751 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1752 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1753 } else {
1754 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1755 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1756 }
1757
1758 /* read number of streams from GCAP register instead of using
1759 * hardcoded value
1760 */
1761 chip->capture_streams = (gcap >> 8) & 0x0f;
1762 chip->playback_streams = (gcap >> 12) & 0x0f;
1763 if (!chip->playback_streams && !chip->capture_streams) {
1764 /* gcap didn't give any info, switching to old method */
1765
1766 switch (chip->driver_type) {
1767 case AZX_DRIVER_ULI:
1768 chip->playback_streams = ULI_NUM_PLAYBACK;
1769 chip->capture_streams = ULI_NUM_CAPTURE;
1770 break;
1771 case AZX_DRIVER_ATIHDMI:
1772 case AZX_DRIVER_ATIHDMI_NS:
1773 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1774 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1775 break;
1776 case AZX_DRIVER_GENERIC:
1777 default:
1778 chip->playback_streams = ICH6_NUM_PLAYBACK;
1779 chip->capture_streams = ICH6_NUM_CAPTURE;
1780 break;
1781 }
1782 }
1783 chip->capture_index_offset = 0;
1784 chip->playback_index_offset = chip->capture_streams;
1785 chip->num_streams = chip->playback_streams + chip->capture_streams;
1786
1787 /* initialize streams */
1788 err = azx_init_streams(chip);
1789 if (err < 0)
1790 return err;
1791
1792 err = azx_alloc_stream_pages(chip);
1793 if (err < 0)
1794 return err;
1795
1796 /* initialize chip */
1797 azx_init_pci(chip);
1798
1799 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1800 struct hda_intel *hda;
1801
1802 hda = container_of(chip, struct hda_intel, chip);
1803 haswell_set_bclk(hda);
1804 }
1805
1806 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1807
1808 /* codec detection */
1809 if (!azx_bus(chip)->codec_mask) {
1810 dev_err(card->dev, "no codecs found!\n");
1811 return -ENODEV;
1812 }
1813
1814 strcpy(card->driver, "HDA-Intel");
1815 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1816 sizeof(card->shortname));
1817 snprintf(card->longname, sizeof(card->longname),
1818 "%s at 0x%lx irq %i",
1819 card->shortname, bus->addr, bus->irq);
1820
1821 return 0;
1822 }
1823
1824 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1825 /* callback from request_firmware_nowait() */
1826 static void azx_firmware_cb(const struct firmware *fw, void *context)
1827 {
1828 struct snd_card *card = context;
1829 struct azx *chip = card->private_data;
1830 struct pci_dev *pci = chip->pci;
1831
1832 if (!fw) {
1833 dev_err(card->dev, "Cannot load firmware, aborting\n");
1834 goto error;
1835 }
1836
1837 chip->fw = fw;
1838 if (!chip->disabled) {
1839 /* continue probing */
1840 if (azx_probe_continue(chip))
1841 goto error;
1842 }
1843 return; /* OK */
1844
1845 error:
1846 snd_card_free(card);
1847 pci_set_drvdata(pci, NULL);
1848 }
1849 #endif
1850
1851 /*
1852 * HDA controller ops.
1853 */
1854
1855 /* PCI register access. */
1856 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1857 {
1858 writel(value, addr);
1859 }
1860
1861 static u32 pci_azx_readl(u32 __iomem *addr)
1862 {
1863 return readl(addr);
1864 }
1865
1866 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1867 {
1868 writew(value, addr);
1869 }
1870
1871 static u16 pci_azx_readw(u16 __iomem *addr)
1872 {
1873 return readw(addr);
1874 }
1875
1876 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1877 {
1878 writeb(value, addr);
1879 }
1880
1881 static u8 pci_azx_readb(u8 __iomem *addr)
1882 {
1883 return readb(addr);
1884 }
1885
1886 static int disable_msi_reset_irq(struct azx *chip)
1887 {
1888 struct hdac_bus *bus = azx_bus(chip);
1889 int err;
1890
1891 free_irq(bus->irq, chip);
1892 bus->irq = -1;
1893 pci_disable_msi(chip->pci);
1894 chip->msi = 0;
1895 err = azx_acquire_irq(chip, 1);
1896 if (err < 0)
1897 return err;
1898
1899 return 0;
1900 }
1901
1902 /* DMA page allocation helpers. */
1903 static int dma_alloc_pages(struct hdac_bus *bus,
1904 int type,
1905 size_t size,
1906 struct snd_dma_buffer *buf)
1907 {
1908 struct azx *chip = bus_to_azx(bus);
1909 int err;
1910
1911 err = snd_dma_alloc_pages(type,
1912 bus->dev,
1913 size, buf);
1914 if (err < 0)
1915 return err;
1916 mark_pages_wc(chip, buf, true);
1917 return 0;
1918 }
1919
1920 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1921 {
1922 struct azx *chip = bus_to_azx(bus);
1923
1924 mark_pages_wc(chip, buf, false);
1925 snd_dma_free_pages(buf);
1926 }
1927
1928 static int substream_alloc_pages(struct azx *chip,
1929 struct snd_pcm_substream *substream,
1930 size_t size)
1931 {
1932 struct azx_dev *azx_dev = get_azx_dev(substream);
1933 int ret;
1934
1935 mark_runtime_wc(chip, azx_dev, substream, false);
1936 ret = snd_pcm_lib_malloc_pages(substream, size);
1937 if (ret < 0)
1938 return ret;
1939 mark_runtime_wc(chip, azx_dev, substream, true);
1940 return 0;
1941 }
1942
1943 static int substream_free_pages(struct azx *chip,
1944 struct snd_pcm_substream *substream)
1945 {
1946 struct azx_dev *azx_dev = get_azx_dev(substream);
1947 mark_runtime_wc(chip, azx_dev, substream, false);
1948 return snd_pcm_lib_free_pages(substream);
1949 }
1950
1951 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1952 struct vm_area_struct *area)
1953 {
1954 #ifdef CONFIG_X86
1955 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1956 struct azx *chip = apcm->chip;
1957 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1958 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1959 #endif
1960 }
1961
1962 static const struct hdac_io_ops pci_hda_io_ops = {
1963 .reg_writel = pci_azx_writel,
1964 .reg_readl = pci_azx_readl,
1965 .reg_writew = pci_azx_writew,
1966 .reg_readw = pci_azx_readw,
1967 .reg_writeb = pci_azx_writeb,
1968 .reg_readb = pci_azx_readb,
1969 .dma_alloc_pages = dma_alloc_pages,
1970 .dma_free_pages = dma_free_pages,
1971 };
1972
1973 static const struct hda_controller_ops pci_hda_ops = {
1974 .disable_msi_reset_irq = disable_msi_reset_irq,
1975 .substream_alloc_pages = substream_alloc_pages,
1976 .substream_free_pages = substream_free_pages,
1977 .pcm_mmap_prepare = pcm_mmap_prepare,
1978 .position_check = azx_position_check,
1979 .link_power = azx_intel_link_power,
1980 };
1981
1982 static int azx_probe(struct pci_dev *pci,
1983 const struct pci_device_id *pci_id)
1984 {
1985 static int dev;
1986 struct snd_card *card;
1987 struct hda_intel *hda;
1988 struct azx *chip;
1989 bool schedule_probe;
1990 int err;
1991
1992 if (dev >= SNDRV_CARDS)
1993 return -ENODEV;
1994 if (!enable[dev]) {
1995 dev++;
1996 return -ENOENT;
1997 }
1998
1999 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2000 0, &card);
2001 if (err < 0) {
2002 dev_err(&pci->dev, "Error creating card!\n");
2003 return err;
2004 }
2005
2006 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2007 if (err < 0)
2008 goto out_free;
2009 card->private_data = chip;
2010 hda = container_of(chip, struct hda_intel, chip);
2011
2012 pci_set_drvdata(pci, card);
2013
2014 err = register_vga_switcheroo(chip);
2015 if (err < 0) {
2016 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2017 goto out_free;
2018 }
2019
2020 if (check_hdmi_disabled(pci)) {
2021 dev_info(card->dev, "VGA controller is disabled\n");
2022 dev_info(card->dev, "Delaying initialization\n");
2023 chip->disabled = true;
2024 }
2025
2026 schedule_probe = !chip->disabled;
2027
2028 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2029 if (patch[dev] && *patch[dev]) {
2030 dev_info(card->dev, "Applying patch firmware '%s'\n",
2031 patch[dev]);
2032 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2033 &pci->dev, GFP_KERNEL, card,
2034 azx_firmware_cb);
2035 if (err < 0)
2036 goto out_free;
2037 schedule_probe = false; /* continued in azx_firmware_cb() */
2038 }
2039 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2040
2041 #ifndef CONFIG_SND_HDA_I915
2042 if (CONTROLLER_IN_GPU(pci))
2043 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2044 #endif
2045
2046 if (schedule_probe)
2047 schedule_work(&hda->probe_work);
2048
2049 dev++;
2050 if (chip->disabled)
2051 complete_all(&hda->probe_wait);
2052 return 0;
2053
2054 out_free:
2055 snd_card_free(card);
2056 return err;
2057 }
2058
2059 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2060 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2061 [AZX_DRIVER_NVIDIA] = 8,
2062 [AZX_DRIVER_TERA] = 1,
2063 };
2064
2065 static int azx_probe_continue(struct azx *chip)
2066 {
2067 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2068 struct hdac_bus *bus = azx_bus(chip);
2069 struct pci_dev *pci = chip->pci;
2070 int dev = chip->dev_index;
2071 int err;
2072
2073 hda->probe_continued = 1;
2074
2075 /* Request display power well for the HDA controller or codec. For
2076 * Haswell/Broadwell, both the display HDA controller and codec need
2077 * this power. For other platforms, like Baytrail/Braswell, only the
2078 * display codec needs the power and it can be released after probe.
2079 */
2080 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2081 /* HSW/BDW controllers need this power */
2082 if (CONTROLLER_IN_GPU(pci))
2083 hda->need_i915_power = 1;
2084
2085 err = snd_hdac_i915_init(bus);
2086 if (err < 0) {
2087 /* if the controller is bound only with HDMI/DP
2088 * (for HSW and BDW), we need to abort the probe;
2089 * for other chips, still continue probing as other
2090 * codecs can be on the same link.
2091 */
2092 if (CONTROLLER_IN_GPU(pci)) {
2093 dev_err(chip->card->dev,
2094 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2095 goto out_free;
2096 } else
2097 goto skip_i915;
2098 }
2099
2100 err = snd_hdac_display_power(bus, true);
2101 if (err < 0) {
2102 dev_err(chip->card->dev,
2103 "Cannot turn on display power on i915\n");
2104 goto i915_power_fail;
2105 }
2106 }
2107
2108 skip_i915:
2109 err = azx_first_init(chip);
2110 if (err < 0)
2111 goto out_free;
2112
2113 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2114 chip->beep_mode = beep_mode[dev];
2115 #endif
2116
2117 /* create codec instances */
2118 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2119 if (err < 0)
2120 goto out_free;
2121
2122 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2123 if (chip->fw) {
2124 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2125 chip->fw->data);
2126 if (err < 0)
2127 goto out_free;
2128 #ifndef CONFIG_PM
2129 release_firmware(chip->fw); /* no longer needed */
2130 chip->fw = NULL;
2131 #endif
2132 }
2133 #endif
2134 if ((probe_only[dev] & 1) == 0) {
2135 err = azx_codec_configure(chip);
2136 if (err < 0)
2137 goto out_free;
2138 }
2139
2140 err = snd_card_register(chip->card);
2141 if (err < 0)
2142 goto out_free;
2143
2144 chip->running = 1;
2145 azx_add_card_list(chip);
2146 snd_hda_set_power_save(&chip->bus, power_save * 1000);
2147 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2148 pm_runtime_put_autosuspend(&pci->dev);
2149
2150 out_free:
2151 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2152 && !hda->need_i915_power)
2153 snd_hdac_display_power(bus, false);
2154
2155 i915_power_fail:
2156 if (err < 0)
2157 hda->init_failed = 1;
2158 complete_all(&hda->probe_wait);
2159 return err;
2160 }
2161
2162 static void azx_remove(struct pci_dev *pci)
2163 {
2164 struct snd_card *card = pci_get_drvdata(pci);
2165 struct azx *chip;
2166 struct hda_intel *hda;
2167
2168 if (card) {
2169 /* cancel the pending probing work */
2170 chip = card->private_data;
2171 hda = container_of(chip, struct hda_intel, chip);
2172 cancel_work_sync(&hda->probe_work);
2173
2174 snd_card_free(card);
2175 }
2176 }
2177
2178 static void azx_shutdown(struct pci_dev *pci)
2179 {
2180 struct snd_card *card = pci_get_drvdata(pci);
2181 struct azx *chip;
2182
2183 if (!card)
2184 return;
2185 chip = card->private_data;
2186 if (chip && chip->running)
2187 azx_stop_chip(chip);
2188 }
2189
2190 /* PCI IDs */
2191 static const struct pci_device_id azx_ids[] = {
2192 /* CPT */
2193 { PCI_DEVICE(0x8086, 0x1c20),
2194 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2195 /* PBG */
2196 { PCI_DEVICE(0x8086, 0x1d20),
2197 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2198 /* Panther Point */
2199 { PCI_DEVICE(0x8086, 0x1e20),
2200 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2201 /* Lynx Point */
2202 { PCI_DEVICE(0x8086, 0x8c20),
2203 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2204 /* 9 Series */
2205 { PCI_DEVICE(0x8086, 0x8ca0),
2206 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2207 /* Wellsburg */
2208 { PCI_DEVICE(0x8086, 0x8d20),
2209 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2210 { PCI_DEVICE(0x8086, 0x8d21),
2211 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2212 /* Lewisburg */
2213 { PCI_DEVICE(0x8086, 0xa1f0),
2214 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2215 { PCI_DEVICE(0x8086, 0xa270),
2216 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2217 /* Lynx Point-LP */
2218 { PCI_DEVICE(0x8086, 0x9c20),
2219 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2220 /* Lynx Point-LP */
2221 { PCI_DEVICE(0x8086, 0x9c21),
2222 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2223 /* Wildcat Point-LP */
2224 { PCI_DEVICE(0x8086, 0x9ca0),
2225 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2226 /* Sunrise Point */
2227 { PCI_DEVICE(0x8086, 0xa170),
2228 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2229 /* Sunrise Point-LP */
2230 { PCI_DEVICE(0x8086, 0x9d70),
2231 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2232 /* Broxton-P(Apollolake) */
2233 { PCI_DEVICE(0x8086, 0x5a98),
2234 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2235 /* Broxton-T */
2236 { PCI_DEVICE(0x8086, 0x1a98),
2237 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2238 /* Haswell */
2239 { PCI_DEVICE(0x8086, 0x0a0c),
2240 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2241 { PCI_DEVICE(0x8086, 0x0c0c),
2242 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2243 { PCI_DEVICE(0x8086, 0x0d0c),
2244 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2245 /* Broadwell */
2246 { PCI_DEVICE(0x8086, 0x160c),
2247 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2248 /* 5 Series/3400 */
2249 { PCI_DEVICE(0x8086, 0x3b56),
2250 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2251 /* Poulsbo */
2252 { PCI_DEVICE(0x8086, 0x811b),
2253 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2254 /* Oaktrail */
2255 { PCI_DEVICE(0x8086, 0x080a),
2256 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2257 /* BayTrail */
2258 { PCI_DEVICE(0x8086, 0x0f04),
2259 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2260 /* Braswell */
2261 { PCI_DEVICE(0x8086, 0x2284),
2262 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2263 /* ICH6 */
2264 { PCI_DEVICE(0x8086, 0x2668),
2265 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2266 /* ICH7 */
2267 { PCI_DEVICE(0x8086, 0x27d8),
2268 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2269 /* ESB2 */
2270 { PCI_DEVICE(0x8086, 0x269a),
2271 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2272 /* ICH8 */
2273 { PCI_DEVICE(0x8086, 0x284b),
2274 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2275 /* ICH9 */
2276 { PCI_DEVICE(0x8086, 0x293e),
2277 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2278 /* ICH9 */
2279 { PCI_DEVICE(0x8086, 0x293f),
2280 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2281 /* ICH10 */
2282 { PCI_DEVICE(0x8086, 0x3a3e),
2283 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2284 /* ICH10 */
2285 { PCI_DEVICE(0x8086, 0x3a6e),
2286 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2287 /* Generic Intel */
2288 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2289 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2290 .class_mask = 0xffffff,
2291 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2292 /* ATI SB 450/600/700/800/900 */
2293 { PCI_DEVICE(0x1002, 0x437b),
2294 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2295 { PCI_DEVICE(0x1002, 0x4383),
2296 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2297 /* AMD Hudson */
2298 { PCI_DEVICE(0x1022, 0x780d),
2299 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2300 /* ATI HDMI */
2301 { PCI_DEVICE(0x1002, 0x1308),
2302 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2303 { PCI_DEVICE(0x1002, 0x157a),
2304 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2305 { PCI_DEVICE(0x1002, 0x793b),
2306 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2307 { PCI_DEVICE(0x1002, 0x7919),
2308 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2309 { PCI_DEVICE(0x1002, 0x960f),
2310 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2311 { PCI_DEVICE(0x1002, 0x970f),
2312 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2313 { PCI_DEVICE(0x1002, 0x9840),
2314 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2315 { PCI_DEVICE(0x1002, 0xaa00),
2316 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2317 { PCI_DEVICE(0x1002, 0xaa08),
2318 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2319 { PCI_DEVICE(0x1002, 0xaa10),
2320 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2321 { PCI_DEVICE(0x1002, 0xaa18),
2322 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2323 { PCI_DEVICE(0x1002, 0xaa20),
2324 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2325 { PCI_DEVICE(0x1002, 0xaa28),
2326 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2327 { PCI_DEVICE(0x1002, 0xaa30),
2328 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2329 { PCI_DEVICE(0x1002, 0xaa38),
2330 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2331 { PCI_DEVICE(0x1002, 0xaa40),
2332 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2333 { PCI_DEVICE(0x1002, 0xaa48),
2334 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2335 { PCI_DEVICE(0x1002, 0xaa50),
2336 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2337 { PCI_DEVICE(0x1002, 0xaa58),
2338 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2339 { PCI_DEVICE(0x1002, 0xaa60),
2340 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2341 { PCI_DEVICE(0x1002, 0xaa68),
2342 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2343 { PCI_DEVICE(0x1002, 0xaa80),
2344 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2345 { PCI_DEVICE(0x1002, 0xaa88),
2346 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2347 { PCI_DEVICE(0x1002, 0xaa90),
2348 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2349 { PCI_DEVICE(0x1002, 0xaa98),
2350 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2351 { PCI_DEVICE(0x1002, 0x9902),
2352 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2353 { PCI_DEVICE(0x1002, 0xaaa0),
2354 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2355 { PCI_DEVICE(0x1002, 0xaaa8),
2356 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2357 { PCI_DEVICE(0x1002, 0xaab0),
2358 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2359 { PCI_DEVICE(0x1002, 0xaac0),
2360 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2361 { PCI_DEVICE(0x1002, 0xaac8),
2362 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2363 { PCI_DEVICE(0x1002, 0xaad8),
2364 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2365 { PCI_DEVICE(0x1002, 0xaae8),
2366 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2367 { PCI_DEVICE(0x1002, 0xaae0),
2368 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2369 { PCI_DEVICE(0x1002, 0xaaf0),
2370 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2371 /* VIA VT8251/VT8237A */
2372 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2373 /* VIA GFX VT7122/VX900 */
2374 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2375 /* VIA GFX VT6122/VX11 */
2376 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2377 /* SIS966 */
2378 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2379 /* ULI M5461 */
2380 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2381 /* NVIDIA MCP */
2382 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2383 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2384 .class_mask = 0xffffff,
2385 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2386 /* Teradici */
2387 { PCI_DEVICE(0x6549, 0x1200),
2388 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2389 { PCI_DEVICE(0x6549, 0x2200),
2390 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2391 /* Creative X-Fi (CA0110-IBG) */
2392 /* CTHDA chips */
2393 { PCI_DEVICE(0x1102, 0x0010),
2394 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2395 { PCI_DEVICE(0x1102, 0x0012),
2396 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2397 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2398 /* the following entry conflicts with snd-ctxfi driver,
2399 * as ctxfi driver mutates from HD-audio to native mode with
2400 * a special command sequence.
2401 */
2402 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2403 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2404 .class_mask = 0xffffff,
2405 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2406 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2407 #else
2408 /* this entry seems still valid -- i.e. without emu20kx chip */
2409 { PCI_DEVICE(0x1102, 0x0009),
2410 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2411 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2412 #endif
2413 /* CM8888 */
2414 { PCI_DEVICE(0x13f6, 0x5011),
2415 .driver_data = AZX_DRIVER_CMEDIA |
2416 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2417 /* Vortex86MX */
2418 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2419 /* VMware HDAudio */
2420 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2421 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2422 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2423 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2424 .class_mask = 0xffffff,
2425 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2426 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2427 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2428 .class_mask = 0xffffff,
2429 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2430 { 0, }
2431 };
2432 MODULE_DEVICE_TABLE(pci, azx_ids);
2433
2434 /* pci_driver definition */
2435 static struct pci_driver azx_driver = {
2436 .name = KBUILD_MODNAME,
2437 .id_table = azx_ids,
2438 .probe = azx_probe,
2439 .remove = azx_remove,
2440 .shutdown = azx_shutdown,
2441 .driver = {
2442 .pm = AZX_PM_OPS,
2443 },
2444 };
2445
2446 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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