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706879a97608a236bd7a7031f87acd3d5c39c15e
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <linux/vgaarb.h>
61 #include <linux/vga_switcheroo.h>
62 #include <linux/firmware.h>
63 #include "hda_codec.h"
64 #include "hda_controller.h"
65 #include "hda_intel.h"
66
67 /* position fix mode */
68 enum {
69 POS_FIX_AUTO,
70 POS_FIX_LPIB,
71 POS_FIX_POSBUF,
72 POS_FIX_VIACOMBO,
73 POS_FIX_COMBO,
74 };
75
76 /* Defines for ATI HD Audio support in SB450 south bridge */
77 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
78 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
79
80 /* Defines for Nvidia HDA support */
81 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
82 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
83 #define NVIDIA_HDA_ISTRM_COH 0x4d
84 #define NVIDIA_HDA_OSTRM_COH 0x4c
85 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
86
87 /* Defines for Intel SCH HDA snoop control */
88 #define INTEL_SCH_HDA_DEVC 0x78
89 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
90
91 /* Define IN stream 0 FIFO size offset in VIA controller */
92 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
93 /* Define VIA HD Audio Device ID*/
94 #define VIA_HDAC_DEVICE_ID 0x3288
95
96 /* max number of SDs */
97 /* ICH, ATI and VIA have 4 playback and 4 capture */
98 #define ICH6_NUM_CAPTURE 4
99 #define ICH6_NUM_PLAYBACK 4
100
101 /* ULI has 6 playback and 5 capture */
102 #define ULI_NUM_CAPTURE 5
103 #define ULI_NUM_PLAYBACK 6
104
105 /* ATI HDMI may have up to 8 playbacks and 0 capture */
106 #define ATIHDMI_NUM_CAPTURE 0
107 #define ATIHDMI_NUM_PLAYBACK 8
108
109 /* TERA has 4 playback and 3 capture */
110 #define TERA_NUM_CAPTURE 3
111 #define TERA_NUM_PLAYBACK 4
112
113
114 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
115 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
116 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
117 static char *model[SNDRV_CARDS];
118 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
119 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
120 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
121 static int probe_only[SNDRV_CARDS];
122 static int jackpoll_ms[SNDRV_CARDS];
123 static bool single_cmd;
124 static int enable_msi = -1;
125 #ifdef CONFIG_SND_HDA_PATCH_LOADER
126 static char *patch[SNDRV_CARDS];
127 #endif
128 #ifdef CONFIG_SND_HDA_INPUT_BEEP
129 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
130 CONFIG_SND_HDA_INPUT_BEEP_MODE};
131 #endif
132
133 module_param_array(index, int, NULL, 0444);
134 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
135 module_param_array(id, charp, NULL, 0444);
136 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
137 module_param_array(enable, bool, NULL, 0444);
138 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
139 module_param_array(model, charp, NULL, 0444);
140 MODULE_PARM_DESC(model, "Use the given board model.");
141 module_param_array(position_fix, int, NULL, 0444);
142 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
143 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
144 module_param_array(bdl_pos_adj, int, NULL, 0644);
145 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
146 module_param_array(probe_mask, int, NULL, 0444);
147 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
148 module_param_array(probe_only, int, NULL, 0444);
149 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
150 module_param_array(jackpoll_ms, int, NULL, 0444);
151 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
152 module_param(single_cmd, bool, 0444);
153 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
154 "(for debugging only).");
155 module_param(enable_msi, bint, 0444);
156 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
157 #ifdef CONFIG_SND_HDA_PATCH_LOADER
158 module_param_array(patch, charp, NULL, 0444);
159 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
160 #endif
161 #ifdef CONFIG_SND_HDA_INPUT_BEEP
162 module_param_array(beep_mode, bool, NULL, 0444);
163 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
164 "(0=off, 1=on) (default=1).");
165 #endif
166
167 #ifdef CONFIG_PM
168 static int param_set_xint(const char *val, const struct kernel_param *kp);
169 static struct kernel_param_ops param_ops_xint = {
170 .set = param_set_xint,
171 .get = param_get_int,
172 };
173 #define param_check_xint param_check_int
174
175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
176 module_param(power_save, xint, 0644);
177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
178 "(in second, 0 = disable).");
179
180 /* reset the HD-audio controller in power save mode.
181 * this may give more power-saving, but will take longer time to
182 * wake up.
183 */
184 static bool power_save_controller = 1;
185 module_param(power_save_controller, bool, 0644);
186 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
187 #else
188 #define power_save 0
189 #endif /* CONFIG_PM */
190
191 static int align_buffer_size = -1;
192 module_param(align_buffer_size, bint, 0644);
193 MODULE_PARM_DESC(align_buffer_size,
194 "Force buffer and period sizes to be multiple of 128 bytes.");
195
196 #ifdef CONFIG_X86
197 static int hda_snoop = -1;
198 module_param_named(snoop, hda_snoop, bint, 0444);
199 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
200 #else
201 #define hda_snoop true
202 #endif
203
204
205 MODULE_LICENSE("GPL");
206 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
207 "{Intel, ICH6M},"
208 "{Intel, ICH7},"
209 "{Intel, ESB2},"
210 "{Intel, ICH8},"
211 "{Intel, ICH9},"
212 "{Intel, ICH10},"
213 "{Intel, PCH},"
214 "{Intel, CPT},"
215 "{Intel, PPT},"
216 "{Intel, LPT},"
217 "{Intel, LPT_LP},"
218 "{Intel, WPT_LP},"
219 "{Intel, SPT},"
220 "{Intel, SPT_LP},"
221 "{Intel, HPT},"
222 "{Intel, PBG},"
223 "{Intel, SCH},"
224 "{ATI, SB450},"
225 "{ATI, SB600},"
226 "{ATI, RS600},"
227 "{ATI, RS690},"
228 "{ATI, RS780},"
229 "{ATI, R600},"
230 "{ATI, RV630},"
231 "{ATI, RV610},"
232 "{ATI, RV670},"
233 "{ATI, RV635},"
234 "{ATI, RV620},"
235 "{ATI, RV770},"
236 "{VIA, VT8251},"
237 "{VIA, VT8237A},"
238 "{SiS, SIS966},"
239 "{ULI, M5461}}");
240 MODULE_DESCRIPTION("Intel HDA driver");
241
242 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
243 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
244 #define SUPPORT_VGA_SWITCHEROO
245 #endif
246 #endif
247
248
249 /*
250 */
251
252 /* driver types */
253 enum {
254 AZX_DRIVER_ICH,
255 AZX_DRIVER_PCH,
256 AZX_DRIVER_SCH,
257 AZX_DRIVER_HDMI,
258 AZX_DRIVER_ATI,
259 AZX_DRIVER_ATIHDMI,
260 AZX_DRIVER_ATIHDMI_NS,
261 AZX_DRIVER_VIA,
262 AZX_DRIVER_SIS,
263 AZX_DRIVER_ULI,
264 AZX_DRIVER_NVIDIA,
265 AZX_DRIVER_TERA,
266 AZX_DRIVER_CTX,
267 AZX_DRIVER_CTHDA,
268 AZX_DRIVER_CMEDIA,
269 AZX_DRIVER_GENERIC,
270 AZX_NUM_DRIVERS, /* keep this as last entry */
271 };
272
273 #define azx_get_snoop_type(chip) \
274 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
275 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
276
277 /* quirks for old Intel chipsets */
278 #define AZX_DCAPS_INTEL_ICH \
279 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
280
281 /* quirks for Intel PCH */
282 #define AZX_DCAPS_INTEL_PCH_NOPM \
283 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
284 AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
285
286 #define AZX_DCAPS_INTEL_PCH \
287 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
288
289 #define AZX_DCAPS_INTEL_HASWELL \
290 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
291 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
292 AZX_DCAPS_SNOOP_TYPE(SCH))
293
294 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
295 #define AZX_DCAPS_INTEL_BROADWELL \
296 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
297 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
298 AZX_DCAPS_SNOOP_TYPE(SCH))
299
300 #define AZX_DCAPS_INTEL_BAYTRAIL \
301 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
302
303 #define AZX_DCAPS_INTEL_BRASWELL \
304 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
305
306 #define AZX_DCAPS_INTEL_SKYLAKE \
307 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
308 AZX_DCAPS_I915_POWERWELL)
309
310 /* quirks for ATI SB / AMD Hudson */
311 #define AZX_DCAPS_PRESET_ATI_SB \
312 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
313 AZX_DCAPS_SNOOP_TYPE(ATI))
314
315 /* quirks for ATI/AMD HDMI */
316 #define AZX_DCAPS_PRESET_ATI_HDMI \
317 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
318 AZX_DCAPS_NO_MSI64)
319
320 /* quirks for ATI HDMI with snoop off */
321 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
322 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
323
324 /* quirks for Nvidia */
325 #define AZX_DCAPS_PRESET_NVIDIA \
326 (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
327 AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
328 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
329
330 #define AZX_DCAPS_PRESET_CTHDA \
331 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
332 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
333
334 /*
335 * VGA-switcher support
336 */
337 #ifdef SUPPORT_VGA_SWITCHEROO
338 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
339 #else
340 #define use_vga_switcheroo(chip) 0
341 #endif
342
343 static char *driver_short_names[] = {
344 [AZX_DRIVER_ICH] = "HDA Intel",
345 [AZX_DRIVER_PCH] = "HDA Intel PCH",
346 [AZX_DRIVER_SCH] = "HDA Intel MID",
347 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
348 [AZX_DRIVER_ATI] = "HDA ATI SB",
349 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
350 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
351 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
352 [AZX_DRIVER_SIS] = "HDA SIS966",
353 [AZX_DRIVER_ULI] = "HDA ULI M5461",
354 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
355 [AZX_DRIVER_TERA] = "HDA Teradici",
356 [AZX_DRIVER_CTX] = "HDA Creative",
357 [AZX_DRIVER_CTHDA] = "HDA Creative",
358 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
359 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
360 };
361
362 #ifdef CONFIG_X86
363 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
364 {
365 int pages;
366
367 if (azx_snoop(chip))
368 return;
369 if (!dmab || !dmab->area || !dmab->bytes)
370 return;
371
372 #ifdef CONFIG_SND_DMA_SGBUF
373 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
374 struct snd_sg_buf *sgbuf = dmab->private_data;
375 if (chip->driver_type == AZX_DRIVER_CMEDIA)
376 return; /* deal with only CORB/RIRB buffers */
377 if (on)
378 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
379 else
380 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
381 return;
382 }
383 #endif
384
385 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
386 if (on)
387 set_memory_wc((unsigned long)dmab->area, pages);
388 else
389 set_memory_wb((unsigned long)dmab->area, pages);
390 }
391
392 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
393 bool on)
394 {
395 __mark_pages_wc(chip, buf, on);
396 }
397 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
398 struct snd_pcm_substream *substream, bool on)
399 {
400 if (azx_dev->wc_marked != on) {
401 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
402 azx_dev->wc_marked = on;
403 }
404 }
405 #else
406 /* NOP for other archs */
407 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
408 bool on)
409 {
410 }
411 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
412 struct snd_pcm_substream *substream, bool on)
413 {
414 }
415 #endif
416
417 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
418
419 /*
420 * initialize the PCI registers
421 */
422 /* update bits in a PCI register byte */
423 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
424 unsigned char mask, unsigned char val)
425 {
426 unsigned char data;
427
428 pci_read_config_byte(pci, reg, &data);
429 data &= ~mask;
430 data |= (val & mask);
431 pci_write_config_byte(pci, reg, data);
432 }
433
434 static void azx_init_pci(struct azx *chip)
435 {
436 int snoop_type = azx_get_snoop_type(chip);
437
438 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
439 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
440 * Ensuring these bits are 0 clears playback static on some HD Audio
441 * codecs.
442 * The PCI register TCSEL is defined in the Intel manuals.
443 */
444 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
445 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
446 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
447 }
448
449 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
450 * we need to enable snoop.
451 */
452 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
453 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
454 azx_snoop(chip));
455 update_pci_byte(chip->pci,
456 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
457 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
458 }
459
460 /* For NVIDIA HDA, enable snoop */
461 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
462 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
463 azx_snoop(chip));
464 update_pci_byte(chip->pci,
465 NVIDIA_HDA_TRANSREG_ADDR,
466 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
467 update_pci_byte(chip->pci,
468 NVIDIA_HDA_ISTRM_COH,
469 0x01, NVIDIA_HDA_ENABLE_COHBIT);
470 update_pci_byte(chip->pci,
471 NVIDIA_HDA_OSTRM_COH,
472 0x01, NVIDIA_HDA_ENABLE_COHBIT);
473 }
474
475 /* Enable SCH/PCH snoop if needed */
476 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
477 unsigned short snoop;
478 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
479 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
480 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
481 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
482 if (!azx_snoop(chip))
483 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
484 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
485 pci_read_config_word(chip->pci,
486 INTEL_SCH_HDA_DEVC, &snoop);
487 }
488 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
489 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
490 "Disabled" : "Enabled");
491 }
492 }
493
494 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
495 {
496 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
497
498 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
499 hda_set_codec_wakeup(hda, true);
500 azx_init_chip(chip, full_reset);
501 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
502 hda_set_codec_wakeup(hda, false);
503 }
504
505 /* calculate runtime delay from LPIB */
506 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
507 unsigned int pos)
508 {
509 struct snd_pcm_substream *substream = azx_dev->core.substream;
510 int stream = substream->stream;
511 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
512 int delay;
513
514 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
515 delay = pos - lpib_pos;
516 else
517 delay = lpib_pos - pos;
518 if (delay < 0) {
519 if (delay >= azx_dev->core.delay_negative_threshold)
520 delay = 0;
521 else
522 delay += azx_dev->core.bufsize;
523 }
524
525 if (delay >= azx_dev->core.period_bytes) {
526 dev_info(chip->card->dev,
527 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
528 delay, azx_dev->core.period_bytes);
529 delay = 0;
530 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
531 chip->get_delay[stream] = NULL;
532 }
533
534 return bytes_to_frames(substream->runtime, delay);
535 }
536
537 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
538
539 /* called from IRQ */
540 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
541 {
542 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
543 int ok;
544
545 ok = azx_position_ok(chip, azx_dev);
546 if (ok == 1) {
547 azx_dev->irq_pending = 0;
548 return ok;
549 } else if (ok == 0) {
550 /* bogus IRQ, process it later */
551 azx_dev->irq_pending = 1;
552 schedule_work(&hda->irq_pending_work);
553 }
554 return 0;
555 }
556
557 /* Enable/disable i915 display power for the link */
558 static int azx_intel_link_power(struct azx *chip, bool enable)
559 {
560 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
561
562 return hda_display_power(hda, enable);
563 }
564
565 /*
566 * Check whether the current DMA position is acceptable for updating
567 * periods. Returns non-zero if it's OK.
568 *
569 * Many HD-audio controllers appear pretty inaccurate about
570 * the update-IRQ timing. The IRQ is issued before actually the
571 * data is processed. So, we need to process it afterwords in a
572 * workqueue.
573 */
574 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
575 {
576 struct snd_pcm_substream *substream = azx_dev->core.substream;
577 int stream = substream->stream;
578 u32 wallclk;
579 unsigned int pos;
580
581 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
582 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
583 return -1; /* bogus (too early) interrupt */
584
585 if (chip->get_position[stream])
586 pos = chip->get_position[stream](chip, azx_dev);
587 else { /* use the position buffer as default */
588 pos = azx_get_pos_posbuf(chip, azx_dev);
589 if (!pos || pos == (u32)-1) {
590 dev_info(chip->card->dev,
591 "Invalid position buffer, using LPIB read method instead.\n");
592 chip->get_position[stream] = azx_get_pos_lpib;
593 if (chip->get_position[0] == azx_get_pos_lpib &&
594 chip->get_position[1] == azx_get_pos_lpib)
595 azx_bus(chip)->use_posbuf = false;
596 pos = azx_get_pos_lpib(chip, azx_dev);
597 chip->get_delay[stream] = NULL;
598 } else {
599 chip->get_position[stream] = azx_get_pos_posbuf;
600 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
601 chip->get_delay[stream] = azx_get_delay_from_lpib;
602 }
603 }
604
605 if (pos >= azx_dev->core.bufsize)
606 pos = 0;
607
608 if (WARN_ONCE(!azx_dev->core.period_bytes,
609 "hda-intel: zero azx_dev->period_bytes"))
610 return -1; /* this shouldn't happen! */
611 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
612 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
613 /* NG - it's below the first next period boundary */
614 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
615 azx_dev->core.start_wallclk += wallclk;
616 return 1; /* OK, it's fine */
617 }
618
619 /*
620 * The work for pending PCM period updates.
621 */
622 static void azx_irq_pending_work(struct work_struct *work)
623 {
624 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
625 struct azx *chip = &hda->chip;
626 struct hdac_bus *bus = azx_bus(chip);
627 struct hdac_stream *s;
628 int pending, ok;
629
630 if (!hda->irq_pending_warned) {
631 dev_info(chip->card->dev,
632 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
633 chip->card->number);
634 hda->irq_pending_warned = 1;
635 }
636
637 for (;;) {
638 pending = 0;
639 spin_lock_irq(&bus->reg_lock);
640 list_for_each_entry(s, &bus->stream_list, list) {
641 struct azx_dev *azx_dev = stream_to_azx_dev(s);
642 if (!azx_dev->irq_pending ||
643 !s->substream ||
644 !s->running)
645 continue;
646 ok = azx_position_ok(chip, azx_dev);
647 if (ok > 0) {
648 azx_dev->irq_pending = 0;
649 spin_unlock(&bus->reg_lock);
650 snd_pcm_period_elapsed(s->substream);
651 spin_lock(&bus->reg_lock);
652 } else if (ok < 0) {
653 pending = 0; /* too early */
654 } else
655 pending++;
656 }
657 spin_unlock_irq(&bus->reg_lock);
658 if (!pending)
659 return;
660 msleep(1);
661 }
662 }
663
664 /* clear irq_pending flags and assure no on-going workq */
665 static void azx_clear_irq_pending(struct azx *chip)
666 {
667 struct hdac_bus *bus = azx_bus(chip);
668 struct hdac_stream *s;
669
670 spin_lock_irq(&bus->reg_lock);
671 list_for_each_entry(s, &bus->stream_list, list) {
672 struct azx_dev *azx_dev = stream_to_azx_dev(s);
673 azx_dev->irq_pending = 0;
674 }
675 spin_unlock_irq(&bus->reg_lock);
676 }
677
678 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
679 {
680 struct hdac_bus *bus = azx_bus(chip);
681
682 if (request_irq(chip->pci->irq, azx_interrupt,
683 chip->msi ? 0 : IRQF_SHARED,
684 KBUILD_MODNAME, chip)) {
685 dev_err(chip->card->dev,
686 "unable to grab IRQ %d, disabling device\n",
687 chip->pci->irq);
688 if (do_disconnect)
689 snd_card_disconnect(chip->card);
690 return -1;
691 }
692 bus->irq = chip->pci->irq;
693 pci_intx(chip->pci, !chip->msi);
694 return 0;
695 }
696
697 /* get the current DMA position with correction on VIA chips */
698 static unsigned int azx_via_get_position(struct azx *chip,
699 struct azx_dev *azx_dev)
700 {
701 unsigned int link_pos, mini_pos, bound_pos;
702 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
703 unsigned int fifo_size;
704
705 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
706 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
707 /* Playback, no problem using link position */
708 return link_pos;
709 }
710
711 /* Capture */
712 /* For new chipset,
713 * use mod to get the DMA position just like old chipset
714 */
715 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
716 mod_dma_pos %= azx_dev->core.period_bytes;
717
718 /* azx_dev->fifo_size can't get FIFO size of in stream.
719 * Get from base address + offset.
720 */
721 fifo_size = readw(azx_bus(chip)->remap_addr +
722 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
723
724 if (azx_dev->insufficient) {
725 /* Link position never gather than FIFO size */
726 if (link_pos <= fifo_size)
727 return 0;
728
729 azx_dev->insufficient = 0;
730 }
731
732 if (link_pos <= fifo_size)
733 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
734 else
735 mini_pos = link_pos - fifo_size;
736
737 /* Find nearest previous boudary */
738 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
739 mod_link_pos = link_pos % azx_dev->core.period_bytes;
740 if (mod_link_pos >= fifo_size)
741 bound_pos = link_pos - mod_link_pos;
742 else if (mod_dma_pos >= mod_mini_pos)
743 bound_pos = mini_pos - mod_mini_pos;
744 else {
745 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
746 if (bound_pos >= azx_dev->core.bufsize)
747 bound_pos = 0;
748 }
749
750 /* Calculate real DMA position we want */
751 return bound_pos + mod_dma_pos;
752 }
753
754 #ifdef CONFIG_PM
755 static DEFINE_MUTEX(card_list_lock);
756 static LIST_HEAD(card_list);
757
758 static void azx_add_card_list(struct azx *chip)
759 {
760 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
761 mutex_lock(&card_list_lock);
762 list_add(&hda->list, &card_list);
763 mutex_unlock(&card_list_lock);
764 }
765
766 static void azx_del_card_list(struct azx *chip)
767 {
768 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
769 mutex_lock(&card_list_lock);
770 list_del_init(&hda->list);
771 mutex_unlock(&card_list_lock);
772 }
773
774 /* trigger power-save check at writing parameter */
775 static int param_set_xint(const char *val, const struct kernel_param *kp)
776 {
777 struct hda_intel *hda;
778 struct azx *chip;
779 int prev = power_save;
780 int ret = param_set_int(val, kp);
781
782 if (ret || prev == power_save)
783 return ret;
784
785 mutex_lock(&card_list_lock);
786 list_for_each_entry(hda, &card_list, list) {
787 chip = &hda->chip;
788 if (!hda->probe_continued || chip->disabled)
789 continue;
790 snd_hda_set_power_save(&chip->bus, power_save * 1000);
791 }
792 mutex_unlock(&card_list_lock);
793 return 0;
794 }
795 #else
796 #define azx_add_card_list(chip) /* NOP */
797 #define azx_del_card_list(chip) /* NOP */
798 #endif /* CONFIG_PM */
799
800 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
801 /*
802 * power management
803 */
804 static int azx_suspend(struct device *dev)
805 {
806 struct snd_card *card = dev_get_drvdata(dev);
807 struct azx *chip;
808 struct hda_intel *hda;
809 struct hdac_bus *bus;
810
811 if (!card)
812 return 0;
813
814 chip = card->private_data;
815 hda = container_of(chip, struct hda_intel, chip);
816 if (chip->disabled || hda->init_failed)
817 return 0;
818
819 bus = azx_bus(chip);
820 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
821 azx_clear_irq_pending(chip);
822 azx_stop_chip(chip);
823 azx_enter_link_reset(chip);
824 if (bus->irq >= 0) {
825 free_irq(bus->irq, chip);
826 bus->irq = -1;
827 }
828
829 if (chip->msi)
830 pci_disable_msi(chip->pci);
831 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
832 && hda->need_i915_power)
833 hda_display_power(hda, false);
834 return 0;
835 }
836
837 static int azx_resume(struct device *dev)
838 {
839 struct pci_dev *pci = to_pci_dev(dev);
840 struct snd_card *card = dev_get_drvdata(dev);
841 struct azx *chip;
842 struct hda_intel *hda;
843
844 if (!card)
845 return 0;
846
847 chip = card->private_data;
848 hda = container_of(chip, struct hda_intel, chip);
849 if (chip->disabled || hda->init_failed)
850 return 0;
851
852 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
853 && hda->need_i915_power) {
854 hda_display_power(hda, true);
855 haswell_set_bclk(hda);
856 }
857 if (chip->msi)
858 if (pci_enable_msi(pci) < 0)
859 chip->msi = 0;
860 if (azx_acquire_irq(chip, 1) < 0)
861 return -EIO;
862 azx_init_pci(chip);
863
864 hda_intel_init_chip(chip, true);
865
866 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
867 return 0;
868 }
869 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
870
871 #ifdef CONFIG_PM
872 static int azx_runtime_suspend(struct device *dev)
873 {
874 struct snd_card *card = dev_get_drvdata(dev);
875 struct azx *chip;
876 struct hda_intel *hda;
877
878 if (!card)
879 return 0;
880
881 chip = card->private_data;
882 hda = container_of(chip, struct hda_intel, chip);
883 if (chip->disabled || hda->init_failed)
884 return 0;
885
886 if (!azx_has_pm_runtime(chip))
887 return 0;
888
889 /* enable controller wake up event */
890 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
891 STATESTS_INT_MASK);
892
893 azx_stop_chip(chip);
894 azx_enter_link_reset(chip);
895 azx_clear_irq_pending(chip);
896 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
897 && hda->need_i915_power)
898 hda_display_power(hda, false);
899
900 return 0;
901 }
902
903 static int azx_runtime_resume(struct device *dev)
904 {
905 struct snd_card *card = dev_get_drvdata(dev);
906 struct azx *chip;
907 struct hda_intel *hda;
908 struct hda_codec *codec;
909 int status;
910
911 if (!card)
912 return 0;
913
914 chip = card->private_data;
915 hda = container_of(chip, struct hda_intel, chip);
916 if (chip->disabled || hda->init_failed)
917 return 0;
918
919 if (!azx_has_pm_runtime(chip))
920 return 0;
921
922 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
923 && hda->need_i915_power) {
924 hda_display_power(hda, true);
925 haswell_set_bclk(hda);
926 /* toggle codec wakeup bit for STATESTS read */
927 hda_set_codec_wakeup(hda, true);
928 hda_set_codec_wakeup(hda, false);
929 }
930
931 /* Read STATESTS before controller reset */
932 status = azx_readw(chip, STATESTS);
933
934 azx_init_pci(chip);
935 hda_intel_init_chip(chip, true);
936
937 if (status) {
938 list_for_each_codec(codec, &chip->bus)
939 if (status & (1 << codec->addr))
940 schedule_delayed_work(&codec->jackpoll_work,
941 codec->jackpoll_interval);
942 }
943
944 /* disable controller Wake Up event*/
945 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
946 ~STATESTS_INT_MASK);
947
948 return 0;
949 }
950
951 static int azx_runtime_idle(struct device *dev)
952 {
953 struct snd_card *card = dev_get_drvdata(dev);
954 struct azx *chip;
955 struct hda_intel *hda;
956
957 if (!card)
958 return 0;
959
960 chip = card->private_data;
961 hda = container_of(chip, struct hda_intel, chip);
962 if (chip->disabled || hda->init_failed)
963 return 0;
964
965 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
966 azx_bus(chip)->codec_powered)
967 return -EBUSY;
968
969 return 0;
970 }
971
972 static const struct dev_pm_ops azx_pm = {
973 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
974 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
975 };
976
977 #define AZX_PM_OPS &azx_pm
978 #else
979 #define AZX_PM_OPS NULL
980 #endif /* CONFIG_PM */
981
982
983 static int azx_probe_continue(struct azx *chip);
984
985 #ifdef SUPPORT_VGA_SWITCHEROO
986 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
987
988 static void azx_vs_set_state(struct pci_dev *pci,
989 enum vga_switcheroo_state state)
990 {
991 struct snd_card *card = pci_get_drvdata(pci);
992 struct azx *chip = card->private_data;
993 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
994 bool disabled;
995
996 wait_for_completion(&hda->probe_wait);
997 if (hda->init_failed)
998 return;
999
1000 disabled = (state == VGA_SWITCHEROO_OFF);
1001 if (chip->disabled == disabled)
1002 return;
1003
1004 if (!hda->probe_continued) {
1005 chip->disabled = disabled;
1006 if (!disabled) {
1007 dev_info(chip->card->dev,
1008 "Start delayed initialization\n");
1009 if (azx_probe_continue(chip) < 0) {
1010 dev_err(chip->card->dev, "initialization error\n");
1011 hda->init_failed = true;
1012 }
1013 }
1014 } else {
1015 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1016 disabled ? "Disabling" : "Enabling");
1017 if (disabled) {
1018 pm_runtime_put_sync_suspend(card->dev);
1019 azx_suspend(card->dev);
1020 /* when we get suspended by vga switcheroo we end up in D3cold,
1021 * however we have no ACPI handle, so pci/acpi can't put us there,
1022 * put ourselves there */
1023 pci->current_state = PCI_D3cold;
1024 chip->disabled = true;
1025 if (snd_hda_lock_devices(&chip->bus))
1026 dev_warn(chip->card->dev,
1027 "Cannot lock devices!\n");
1028 } else {
1029 snd_hda_unlock_devices(&chip->bus);
1030 pm_runtime_get_noresume(card->dev);
1031 chip->disabled = false;
1032 azx_resume(card->dev);
1033 }
1034 }
1035 }
1036
1037 static bool azx_vs_can_switch(struct pci_dev *pci)
1038 {
1039 struct snd_card *card = pci_get_drvdata(pci);
1040 struct azx *chip = card->private_data;
1041 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1042
1043 wait_for_completion(&hda->probe_wait);
1044 if (hda->init_failed)
1045 return false;
1046 if (chip->disabled || !hda->probe_continued)
1047 return true;
1048 if (snd_hda_lock_devices(&chip->bus))
1049 return false;
1050 snd_hda_unlock_devices(&chip->bus);
1051 return true;
1052 }
1053
1054 static void init_vga_switcheroo(struct azx *chip)
1055 {
1056 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1057 struct pci_dev *p = get_bound_vga(chip->pci);
1058 if (p) {
1059 dev_info(chip->card->dev,
1060 "Handle VGA-switcheroo audio client\n");
1061 hda->use_vga_switcheroo = 1;
1062 pci_dev_put(p);
1063 }
1064 }
1065
1066 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1067 .set_gpu_state = azx_vs_set_state,
1068 .can_switch = azx_vs_can_switch,
1069 };
1070
1071 static int register_vga_switcheroo(struct azx *chip)
1072 {
1073 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1074 int err;
1075
1076 if (!hda->use_vga_switcheroo)
1077 return 0;
1078 /* FIXME: currently only handling DIS controller
1079 * is there any machine with two switchable HDMI audio controllers?
1080 */
1081 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1082 VGA_SWITCHEROO_DIS,
1083 hda->probe_continued);
1084 if (err < 0)
1085 return err;
1086 hda->vga_switcheroo_registered = 1;
1087
1088 /* register as an optimus hdmi audio power domain */
1089 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1090 &hda->hdmi_pm_domain);
1091 return 0;
1092 }
1093 #else
1094 #define init_vga_switcheroo(chip) /* NOP */
1095 #define register_vga_switcheroo(chip) 0
1096 #define check_hdmi_disabled(pci) false
1097 #endif /* SUPPORT_VGA_SWITCHER */
1098
1099 /*
1100 * destructor
1101 */
1102 static int azx_free(struct azx *chip)
1103 {
1104 struct pci_dev *pci = chip->pci;
1105 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1106 struct hdac_bus *bus = azx_bus(chip);
1107
1108 if (azx_has_pm_runtime(chip) && chip->running)
1109 pm_runtime_get_noresume(&pci->dev);
1110
1111 azx_del_card_list(chip);
1112
1113 hda->init_failed = 1; /* to be sure */
1114 complete_all(&hda->probe_wait);
1115
1116 if (use_vga_switcheroo(hda)) {
1117 if (chip->disabled && hda->probe_continued)
1118 snd_hda_unlock_devices(&chip->bus);
1119 if (hda->vga_switcheroo_registered)
1120 vga_switcheroo_unregister_client(chip->pci);
1121 }
1122
1123 if (bus->chip_init) {
1124 azx_clear_irq_pending(chip);
1125 azx_stop_all_streams(chip);
1126 azx_stop_chip(chip);
1127 }
1128
1129 if (bus->irq >= 0)
1130 free_irq(bus->irq, (void*)chip);
1131 if (chip->msi)
1132 pci_disable_msi(chip->pci);
1133 iounmap(bus->remap_addr);
1134
1135 azx_free_stream_pages(chip);
1136 azx_free_streams(chip);
1137 snd_hdac_bus_exit(bus);
1138
1139 if (chip->region_requested)
1140 pci_release_regions(chip->pci);
1141
1142 pci_disable_device(chip->pci);
1143 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1144 release_firmware(chip->fw);
1145 #endif
1146 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1147 if (hda->need_i915_power)
1148 hda_display_power(hda, false);
1149 hda_i915_exit(hda);
1150 }
1151 kfree(hda);
1152
1153 return 0;
1154 }
1155
1156 static int azx_dev_disconnect(struct snd_device *device)
1157 {
1158 struct azx *chip = device->device_data;
1159
1160 chip->bus.shutdown = 1;
1161 return 0;
1162 }
1163
1164 static int azx_dev_free(struct snd_device *device)
1165 {
1166 return azx_free(device->device_data);
1167 }
1168
1169 #ifdef SUPPORT_VGA_SWITCHEROO
1170 /*
1171 * Check of disabled HDMI controller by vga-switcheroo
1172 */
1173 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1174 {
1175 struct pci_dev *p;
1176
1177 /* check only discrete GPU */
1178 switch (pci->vendor) {
1179 case PCI_VENDOR_ID_ATI:
1180 case PCI_VENDOR_ID_AMD:
1181 case PCI_VENDOR_ID_NVIDIA:
1182 if (pci->devfn == 1) {
1183 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1184 pci->bus->number, 0);
1185 if (p) {
1186 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1187 return p;
1188 pci_dev_put(p);
1189 }
1190 }
1191 break;
1192 }
1193 return NULL;
1194 }
1195
1196 static bool check_hdmi_disabled(struct pci_dev *pci)
1197 {
1198 bool vga_inactive = false;
1199 struct pci_dev *p = get_bound_vga(pci);
1200
1201 if (p) {
1202 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1203 vga_inactive = true;
1204 pci_dev_put(p);
1205 }
1206 return vga_inactive;
1207 }
1208 #endif /* SUPPORT_VGA_SWITCHEROO */
1209
1210 /*
1211 * white/black-listing for position_fix
1212 */
1213 static struct snd_pci_quirk position_fix_list[] = {
1214 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1215 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1216 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1217 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1218 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1219 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1220 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1221 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1222 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1223 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1224 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1225 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1226 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1227 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1228 {}
1229 };
1230
1231 static int check_position_fix(struct azx *chip, int fix)
1232 {
1233 const struct snd_pci_quirk *q;
1234
1235 switch (fix) {
1236 case POS_FIX_AUTO:
1237 case POS_FIX_LPIB:
1238 case POS_FIX_POSBUF:
1239 case POS_FIX_VIACOMBO:
1240 case POS_FIX_COMBO:
1241 return fix;
1242 }
1243
1244 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1245 if (q) {
1246 dev_info(chip->card->dev,
1247 "position_fix set to %d for device %04x:%04x\n",
1248 q->value, q->subvendor, q->subdevice);
1249 return q->value;
1250 }
1251
1252 /* Check VIA/ATI HD Audio Controller exist */
1253 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1254 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1255 return POS_FIX_VIACOMBO;
1256 }
1257 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1258 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1259 return POS_FIX_LPIB;
1260 }
1261 return POS_FIX_AUTO;
1262 }
1263
1264 static void assign_position_fix(struct azx *chip, int fix)
1265 {
1266 static azx_get_pos_callback_t callbacks[] = {
1267 [POS_FIX_AUTO] = NULL,
1268 [POS_FIX_LPIB] = azx_get_pos_lpib,
1269 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1270 [POS_FIX_VIACOMBO] = azx_via_get_position,
1271 [POS_FIX_COMBO] = azx_get_pos_lpib,
1272 };
1273
1274 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1275
1276 /* combo mode uses LPIB only for playback */
1277 if (fix == POS_FIX_COMBO)
1278 chip->get_position[1] = NULL;
1279
1280 if (fix == POS_FIX_POSBUF &&
1281 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1282 chip->get_delay[0] = chip->get_delay[1] =
1283 azx_get_delay_from_lpib;
1284 }
1285
1286 }
1287
1288 /*
1289 * black-lists for probe_mask
1290 */
1291 static struct snd_pci_quirk probe_mask_list[] = {
1292 /* Thinkpad often breaks the controller communication when accessing
1293 * to the non-working (or non-existing) modem codec slot.
1294 */
1295 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1296 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1297 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1298 /* broken BIOS */
1299 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1300 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1301 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1302 /* forced codec slots */
1303 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1304 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1305 /* WinFast VP200 H (Teradici) user reported broken communication */
1306 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1307 {}
1308 };
1309
1310 #define AZX_FORCE_CODEC_MASK 0x100
1311
1312 static void check_probe_mask(struct azx *chip, int dev)
1313 {
1314 const struct snd_pci_quirk *q;
1315
1316 chip->codec_probe_mask = probe_mask[dev];
1317 if (chip->codec_probe_mask == -1) {
1318 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1319 if (q) {
1320 dev_info(chip->card->dev,
1321 "probe_mask set to 0x%x for device %04x:%04x\n",
1322 q->value, q->subvendor, q->subdevice);
1323 chip->codec_probe_mask = q->value;
1324 }
1325 }
1326
1327 /* check forced option */
1328 if (chip->codec_probe_mask != -1 &&
1329 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1330 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1331 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1332 (int)azx_bus(chip)->codec_mask);
1333 }
1334 }
1335
1336 /*
1337 * white/black-list for enable_msi
1338 */
1339 static struct snd_pci_quirk msi_black_list[] = {
1340 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1341 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1342 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1343 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1344 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1345 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1346 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1347 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1348 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1349 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1350 {}
1351 };
1352
1353 static void check_msi(struct azx *chip)
1354 {
1355 const struct snd_pci_quirk *q;
1356
1357 if (enable_msi >= 0) {
1358 chip->msi = !!enable_msi;
1359 return;
1360 }
1361 chip->msi = 1; /* enable MSI as default */
1362 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1363 if (q) {
1364 dev_info(chip->card->dev,
1365 "msi for device %04x:%04x set to %d\n",
1366 q->subvendor, q->subdevice, q->value);
1367 chip->msi = q->value;
1368 return;
1369 }
1370
1371 /* NVidia chipsets seem to cause troubles with MSI */
1372 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1373 dev_info(chip->card->dev, "Disabling MSI\n");
1374 chip->msi = 0;
1375 }
1376 }
1377
1378 /* check the snoop mode availability */
1379 static void azx_check_snoop_available(struct azx *chip)
1380 {
1381 int snoop = hda_snoop;
1382
1383 if (snoop >= 0) {
1384 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1385 snoop ? "snoop" : "non-snoop");
1386 chip->snoop = snoop;
1387 return;
1388 }
1389
1390 snoop = true;
1391 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1392 chip->driver_type == AZX_DRIVER_VIA) {
1393 /* force to non-snoop mode for a new VIA controller
1394 * when BIOS is set
1395 */
1396 u8 val;
1397 pci_read_config_byte(chip->pci, 0x42, &val);
1398 if (!(val & 0x80) && chip->pci->revision == 0x30)
1399 snoop = false;
1400 }
1401
1402 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1403 snoop = false;
1404
1405 chip->snoop = snoop;
1406 if (!snoop)
1407 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1408 }
1409
1410 static void azx_probe_work(struct work_struct *work)
1411 {
1412 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1413 azx_probe_continue(&hda->chip);
1414 }
1415
1416 /*
1417 * constructor
1418 */
1419 static const struct hdac_io_ops pci_hda_io_ops;
1420 static const struct hda_controller_ops pci_hda_ops;
1421
1422 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1423 int dev, unsigned int driver_caps,
1424 struct azx **rchip)
1425 {
1426 static struct snd_device_ops ops = {
1427 .dev_disconnect = azx_dev_disconnect,
1428 .dev_free = azx_dev_free,
1429 };
1430 struct hda_intel *hda;
1431 struct azx *chip;
1432 int err;
1433
1434 *rchip = NULL;
1435
1436 err = pci_enable_device(pci);
1437 if (err < 0)
1438 return err;
1439
1440 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1441 if (!hda) {
1442 pci_disable_device(pci);
1443 return -ENOMEM;
1444 }
1445
1446 chip = &hda->chip;
1447 mutex_init(&chip->open_mutex);
1448 chip->card = card;
1449 chip->pci = pci;
1450 chip->ops = &pci_hda_ops;
1451 chip->driver_caps = driver_caps;
1452 chip->driver_type = driver_caps & 0xff;
1453 check_msi(chip);
1454 chip->dev_index = dev;
1455 chip->jackpoll_ms = jackpoll_ms;
1456 INIT_LIST_HEAD(&chip->pcm_list);
1457 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1458 INIT_LIST_HEAD(&hda->list);
1459 init_vga_switcheroo(chip);
1460 init_completion(&hda->probe_wait);
1461
1462 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1463
1464 check_probe_mask(chip, dev);
1465
1466 chip->single_cmd = single_cmd;
1467 azx_check_snoop_available(chip);
1468
1469 if (bdl_pos_adj[dev] < 0) {
1470 switch (chip->driver_type) {
1471 case AZX_DRIVER_ICH:
1472 case AZX_DRIVER_PCH:
1473 bdl_pos_adj[dev] = 1;
1474 break;
1475 default:
1476 bdl_pos_adj[dev] = 32;
1477 break;
1478 }
1479 }
1480 chip->bdl_pos_adj = bdl_pos_adj;
1481
1482 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1483 if (err < 0) {
1484 kfree(hda);
1485 pci_disable_device(pci);
1486 return err;
1487 }
1488
1489 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1490 if (err < 0) {
1491 dev_err(card->dev, "Error creating device [card]!\n");
1492 azx_free(chip);
1493 return err;
1494 }
1495
1496 /* continue probing in work context as may trigger request module */
1497 INIT_WORK(&hda->probe_work, azx_probe_work);
1498
1499 *rchip = chip;
1500
1501 return 0;
1502 }
1503
1504 static int azx_first_init(struct azx *chip)
1505 {
1506 int dev = chip->dev_index;
1507 struct pci_dev *pci = chip->pci;
1508 struct snd_card *card = chip->card;
1509 struct hdac_bus *bus = azx_bus(chip);
1510 int err;
1511 unsigned short gcap;
1512 unsigned int dma_bits = 64;
1513
1514 #if BITS_PER_LONG != 64
1515 /* Fix up base address on ULI M5461 */
1516 if (chip->driver_type == AZX_DRIVER_ULI) {
1517 u16 tmp3;
1518 pci_read_config_word(pci, 0x40, &tmp3);
1519 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1520 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1521 }
1522 #endif
1523
1524 err = pci_request_regions(pci, "ICH HD audio");
1525 if (err < 0)
1526 return err;
1527 chip->region_requested = 1;
1528
1529 bus->addr = pci_resource_start(pci, 0);
1530 bus->remap_addr = pci_ioremap_bar(pci, 0);
1531 if (bus->remap_addr == NULL) {
1532 dev_err(card->dev, "ioremap error\n");
1533 return -ENXIO;
1534 }
1535
1536 if (chip->msi) {
1537 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1538 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1539 pci->no_64bit_msi = true;
1540 }
1541 if (pci_enable_msi(pci) < 0)
1542 chip->msi = 0;
1543 }
1544
1545 if (azx_acquire_irq(chip, 0) < 0)
1546 return -EBUSY;
1547
1548 pci_set_master(pci);
1549 synchronize_irq(bus->irq);
1550
1551 gcap = azx_readw(chip, GCAP);
1552 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1553
1554 /* AMD devices support 40 or 48bit DMA, take the safe one */
1555 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1556 dma_bits = 40;
1557
1558 /* disable SB600 64bit support for safety */
1559 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1560 struct pci_dev *p_smbus;
1561 dma_bits = 40;
1562 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1563 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1564 NULL);
1565 if (p_smbus) {
1566 if (p_smbus->revision < 0x30)
1567 gcap &= ~AZX_GCAP_64OK;
1568 pci_dev_put(p_smbus);
1569 }
1570 }
1571
1572 /* disable 64bit DMA address on some devices */
1573 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1574 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1575 gcap &= ~AZX_GCAP_64OK;
1576 }
1577
1578 /* disable buffer size rounding to 128-byte multiples if supported */
1579 if (align_buffer_size >= 0)
1580 chip->align_buffer_size = !!align_buffer_size;
1581 else {
1582 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1583 chip->align_buffer_size = 0;
1584 else
1585 chip->align_buffer_size = 1;
1586 }
1587
1588 /* allow 64bit DMA address if supported by H/W */
1589 if (!(gcap & AZX_GCAP_64OK))
1590 dma_bits = 32;
1591 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1592 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1593 } else {
1594 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1595 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1596 }
1597
1598 /* read number of streams from GCAP register instead of using
1599 * hardcoded value
1600 */
1601 chip->capture_streams = (gcap >> 8) & 0x0f;
1602 chip->playback_streams = (gcap >> 12) & 0x0f;
1603 if (!chip->playback_streams && !chip->capture_streams) {
1604 /* gcap didn't give any info, switching to old method */
1605
1606 switch (chip->driver_type) {
1607 case AZX_DRIVER_ULI:
1608 chip->playback_streams = ULI_NUM_PLAYBACK;
1609 chip->capture_streams = ULI_NUM_CAPTURE;
1610 break;
1611 case AZX_DRIVER_ATIHDMI:
1612 case AZX_DRIVER_ATIHDMI_NS:
1613 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1614 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1615 break;
1616 case AZX_DRIVER_GENERIC:
1617 default:
1618 chip->playback_streams = ICH6_NUM_PLAYBACK;
1619 chip->capture_streams = ICH6_NUM_CAPTURE;
1620 break;
1621 }
1622 }
1623 chip->capture_index_offset = 0;
1624 chip->playback_index_offset = chip->capture_streams;
1625 chip->num_streams = chip->playback_streams + chip->capture_streams;
1626
1627 /* initialize streams */
1628 err = azx_init_streams(chip);
1629 if (err < 0)
1630 return err;
1631
1632 err = azx_alloc_stream_pages(chip);
1633 if (err < 0)
1634 return err;
1635
1636 /* initialize chip */
1637 azx_init_pci(chip);
1638
1639 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1640 struct hda_intel *hda;
1641
1642 hda = container_of(chip, struct hda_intel, chip);
1643 haswell_set_bclk(hda);
1644 }
1645
1646 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1647
1648 /* codec detection */
1649 if (!azx_bus(chip)->codec_mask) {
1650 dev_err(card->dev, "no codecs found!\n");
1651 return -ENODEV;
1652 }
1653
1654 strcpy(card->driver, "HDA-Intel");
1655 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1656 sizeof(card->shortname));
1657 snprintf(card->longname, sizeof(card->longname),
1658 "%s at 0x%lx irq %i",
1659 card->shortname, bus->addr, bus->irq);
1660
1661 return 0;
1662 }
1663
1664 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1665 /* callback from request_firmware_nowait() */
1666 static void azx_firmware_cb(const struct firmware *fw, void *context)
1667 {
1668 struct snd_card *card = context;
1669 struct azx *chip = card->private_data;
1670 struct pci_dev *pci = chip->pci;
1671
1672 if (!fw) {
1673 dev_err(card->dev, "Cannot load firmware, aborting\n");
1674 goto error;
1675 }
1676
1677 chip->fw = fw;
1678 if (!chip->disabled) {
1679 /* continue probing */
1680 if (azx_probe_continue(chip))
1681 goto error;
1682 }
1683 return; /* OK */
1684
1685 error:
1686 snd_card_free(card);
1687 pci_set_drvdata(pci, NULL);
1688 }
1689 #endif
1690
1691 /*
1692 * HDA controller ops.
1693 */
1694
1695 /* PCI register access. */
1696 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1697 {
1698 writel(value, addr);
1699 }
1700
1701 static u32 pci_azx_readl(u32 __iomem *addr)
1702 {
1703 return readl(addr);
1704 }
1705
1706 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1707 {
1708 writew(value, addr);
1709 }
1710
1711 static u16 pci_azx_readw(u16 __iomem *addr)
1712 {
1713 return readw(addr);
1714 }
1715
1716 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1717 {
1718 writeb(value, addr);
1719 }
1720
1721 static u8 pci_azx_readb(u8 __iomem *addr)
1722 {
1723 return readb(addr);
1724 }
1725
1726 static int disable_msi_reset_irq(struct azx *chip)
1727 {
1728 struct hdac_bus *bus = azx_bus(chip);
1729 int err;
1730
1731 free_irq(bus->irq, chip);
1732 bus->irq = -1;
1733 pci_disable_msi(chip->pci);
1734 chip->msi = 0;
1735 err = azx_acquire_irq(chip, 1);
1736 if (err < 0)
1737 return err;
1738
1739 return 0;
1740 }
1741
1742 /* DMA page allocation helpers. */
1743 static int dma_alloc_pages(struct hdac_bus *bus,
1744 int type,
1745 size_t size,
1746 struct snd_dma_buffer *buf)
1747 {
1748 struct azx *chip = bus_to_azx(bus);
1749 int err;
1750
1751 err = snd_dma_alloc_pages(type,
1752 bus->dev,
1753 size, buf);
1754 if (err < 0)
1755 return err;
1756 mark_pages_wc(chip, buf, true);
1757 return 0;
1758 }
1759
1760 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1761 {
1762 struct azx *chip = bus_to_azx(bus);
1763
1764 mark_pages_wc(chip, buf, false);
1765 snd_dma_free_pages(buf);
1766 }
1767
1768 static int substream_alloc_pages(struct azx *chip,
1769 struct snd_pcm_substream *substream,
1770 size_t size)
1771 {
1772 struct azx_dev *azx_dev = get_azx_dev(substream);
1773 int ret;
1774
1775 mark_runtime_wc(chip, azx_dev, substream, false);
1776 ret = snd_pcm_lib_malloc_pages(substream, size);
1777 if (ret < 0)
1778 return ret;
1779 mark_runtime_wc(chip, azx_dev, substream, true);
1780 return 0;
1781 }
1782
1783 static int substream_free_pages(struct azx *chip,
1784 struct snd_pcm_substream *substream)
1785 {
1786 struct azx_dev *azx_dev = get_azx_dev(substream);
1787 mark_runtime_wc(chip, azx_dev, substream, false);
1788 return snd_pcm_lib_free_pages(substream);
1789 }
1790
1791 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1792 struct vm_area_struct *area)
1793 {
1794 #ifdef CONFIG_X86
1795 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1796 struct azx *chip = apcm->chip;
1797 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1798 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1799 #endif
1800 }
1801
1802 static const struct hdac_io_ops pci_hda_io_ops = {
1803 .reg_writel = pci_azx_writel,
1804 .reg_readl = pci_azx_readl,
1805 .reg_writew = pci_azx_writew,
1806 .reg_readw = pci_azx_readw,
1807 .reg_writeb = pci_azx_writeb,
1808 .reg_readb = pci_azx_readb,
1809 .dma_alloc_pages = dma_alloc_pages,
1810 .dma_free_pages = dma_free_pages,
1811 };
1812
1813 static const struct hda_controller_ops pci_hda_ops = {
1814 .disable_msi_reset_irq = disable_msi_reset_irq,
1815 .substream_alloc_pages = substream_alloc_pages,
1816 .substream_free_pages = substream_free_pages,
1817 .pcm_mmap_prepare = pcm_mmap_prepare,
1818 .position_check = azx_position_check,
1819 .link_power = azx_intel_link_power,
1820 };
1821
1822 static int azx_probe(struct pci_dev *pci,
1823 const struct pci_device_id *pci_id)
1824 {
1825 static int dev;
1826 struct snd_card *card;
1827 struct hda_intel *hda;
1828 struct azx *chip;
1829 bool schedule_probe;
1830 int err;
1831
1832 if (dev >= SNDRV_CARDS)
1833 return -ENODEV;
1834 if (!enable[dev]) {
1835 dev++;
1836 return -ENOENT;
1837 }
1838
1839 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1840 0, &card);
1841 if (err < 0) {
1842 dev_err(&pci->dev, "Error creating card!\n");
1843 return err;
1844 }
1845
1846 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1847 if (err < 0)
1848 goto out_free;
1849 card->private_data = chip;
1850 hda = container_of(chip, struct hda_intel, chip);
1851
1852 pci_set_drvdata(pci, card);
1853
1854 err = register_vga_switcheroo(chip);
1855 if (err < 0) {
1856 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
1857 goto out_free;
1858 }
1859
1860 if (check_hdmi_disabled(pci)) {
1861 dev_info(card->dev, "VGA controller is disabled\n");
1862 dev_info(card->dev, "Delaying initialization\n");
1863 chip->disabled = true;
1864 }
1865
1866 schedule_probe = !chip->disabled;
1867
1868 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1869 if (patch[dev] && *patch[dev]) {
1870 dev_info(card->dev, "Applying patch firmware '%s'\n",
1871 patch[dev]);
1872 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1873 &pci->dev, GFP_KERNEL, card,
1874 azx_firmware_cb);
1875 if (err < 0)
1876 goto out_free;
1877 schedule_probe = false; /* continued in azx_firmware_cb() */
1878 }
1879 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1880
1881 #ifndef CONFIG_SND_HDA_I915
1882 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1883 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1884 #endif
1885
1886 if (schedule_probe)
1887 schedule_work(&hda->probe_work);
1888
1889 dev++;
1890 if (chip->disabled)
1891 complete_all(&hda->probe_wait);
1892 return 0;
1893
1894 out_free:
1895 snd_card_free(card);
1896 return err;
1897 }
1898
1899 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1900 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1901 [AZX_DRIVER_NVIDIA] = 8,
1902 [AZX_DRIVER_TERA] = 1,
1903 };
1904
1905 static int azx_probe_continue(struct azx *chip)
1906 {
1907 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1908 struct pci_dev *pci = chip->pci;
1909 int dev = chip->dev_index;
1910 int err;
1911
1912 hda->probe_continued = 1;
1913
1914 /* Request display power well for the HDA controller or codec. For
1915 * Haswell/Broadwell, both the display HDA controller and codec need
1916 * this power. For other platforms, like Baytrail/Braswell, only the
1917 * display codec needs the power and it can be released after probe.
1918 */
1919 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1920 /* Baytral/Braswell controllers don't need this power */
1921 if (pci->device != 0x0f04 && pci->device != 0x2284)
1922 hda->need_i915_power = 1;
1923
1924 err = hda_i915_init(hda);
1925 if (err < 0)
1926 goto i915_power_fail;
1927
1928 err = hda_display_power(hda, true);
1929 if (err < 0) {
1930 dev_err(chip->card->dev,
1931 "Cannot turn on display power on i915\n");
1932 goto i915_power_fail;
1933 }
1934 }
1935
1936 err = azx_first_init(chip);
1937 if (err < 0)
1938 goto out_free;
1939
1940 #ifdef CONFIG_SND_HDA_INPUT_BEEP
1941 chip->beep_mode = beep_mode[dev];
1942 #endif
1943
1944 /* create codec instances */
1945 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
1946 if (err < 0)
1947 goto out_free;
1948
1949 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1950 if (chip->fw) {
1951 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
1952 chip->fw->data);
1953 if (err < 0)
1954 goto out_free;
1955 #ifndef CONFIG_PM
1956 release_firmware(chip->fw); /* no longer needed */
1957 chip->fw = NULL;
1958 #endif
1959 }
1960 #endif
1961 if ((probe_only[dev] & 1) == 0) {
1962 err = azx_codec_configure(chip);
1963 if (err < 0)
1964 goto out_free;
1965 }
1966
1967 err = snd_card_register(chip->card);
1968 if (err < 0)
1969 goto out_free;
1970
1971 chip->running = 1;
1972 azx_add_card_list(chip);
1973 snd_hda_set_power_save(&chip->bus, power_save * 1000);
1974 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
1975 pm_runtime_put_noidle(&pci->dev);
1976
1977 out_free:
1978 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1979 && !hda->need_i915_power)
1980 hda_display_power(hda, false);
1981
1982 i915_power_fail:
1983 if (err < 0)
1984 hda->init_failed = 1;
1985 complete_all(&hda->probe_wait);
1986 return err;
1987 }
1988
1989 static void azx_remove(struct pci_dev *pci)
1990 {
1991 struct snd_card *card = pci_get_drvdata(pci);
1992
1993 if (card)
1994 snd_card_free(card);
1995 }
1996
1997 static void azx_shutdown(struct pci_dev *pci)
1998 {
1999 struct snd_card *card = pci_get_drvdata(pci);
2000 struct azx *chip;
2001
2002 if (!card)
2003 return;
2004 chip = card->private_data;
2005 if (chip && chip->running)
2006 azx_stop_chip(chip);
2007 }
2008
2009 /* PCI IDs */
2010 static const struct pci_device_id azx_ids[] = {
2011 /* CPT */
2012 { PCI_DEVICE(0x8086, 0x1c20),
2013 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2014 /* PBG */
2015 { PCI_DEVICE(0x8086, 0x1d20),
2016 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2017 /* Panther Point */
2018 { PCI_DEVICE(0x8086, 0x1e20),
2019 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2020 /* Lynx Point */
2021 { PCI_DEVICE(0x8086, 0x8c20),
2022 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2023 /* 9 Series */
2024 { PCI_DEVICE(0x8086, 0x8ca0),
2025 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2026 /* Wellsburg */
2027 { PCI_DEVICE(0x8086, 0x8d20),
2028 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2029 { PCI_DEVICE(0x8086, 0x8d21),
2030 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2031 /* Lynx Point-LP */
2032 { PCI_DEVICE(0x8086, 0x9c20),
2033 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2034 /* Lynx Point-LP */
2035 { PCI_DEVICE(0x8086, 0x9c21),
2036 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2037 /* Wildcat Point-LP */
2038 { PCI_DEVICE(0x8086, 0x9ca0),
2039 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2040 /* Sunrise Point */
2041 { PCI_DEVICE(0x8086, 0xa170),
2042 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2043 /* Sunrise Point-LP */
2044 { PCI_DEVICE(0x8086, 0x9d70),
2045 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2046 /* Haswell */
2047 { PCI_DEVICE(0x8086, 0x0a0c),
2048 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2049 { PCI_DEVICE(0x8086, 0x0c0c),
2050 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2051 { PCI_DEVICE(0x8086, 0x0d0c),
2052 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2053 /* Broadwell */
2054 { PCI_DEVICE(0x8086, 0x160c),
2055 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2056 /* 5 Series/3400 */
2057 { PCI_DEVICE(0x8086, 0x3b56),
2058 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2059 /* Poulsbo */
2060 { PCI_DEVICE(0x8086, 0x811b),
2061 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2062 /* Oaktrail */
2063 { PCI_DEVICE(0x8086, 0x080a),
2064 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2065 /* BayTrail */
2066 { PCI_DEVICE(0x8086, 0x0f04),
2067 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2068 /* Braswell */
2069 { PCI_DEVICE(0x8086, 0x2284),
2070 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2071 /* ICH6 */
2072 { PCI_DEVICE(0x8086, 0x2668),
2073 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2074 /* ICH7 */
2075 { PCI_DEVICE(0x8086, 0x27d8),
2076 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2077 /* ESB2 */
2078 { PCI_DEVICE(0x8086, 0x269a),
2079 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2080 /* ICH8 */
2081 { PCI_DEVICE(0x8086, 0x284b),
2082 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2083 /* ICH9 */
2084 { PCI_DEVICE(0x8086, 0x293e),
2085 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2086 /* ICH9 */
2087 { PCI_DEVICE(0x8086, 0x293f),
2088 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2089 /* ICH10 */
2090 { PCI_DEVICE(0x8086, 0x3a3e),
2091 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2092 /* ICH10 */
2093 { PCI_DEVICE(0x8086, 0x3a6e),
2094 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2095 /* Generic Intel */
2096 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2097 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2098 .class_mask = 0xffffff,
2099 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2100 /* ATI SB 450/600/700/800/900 */
2101 { PCI_DEVICE(0x1002, 0x437b),
2102 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2103 { PCI_DEVICE(0x1002, 0x4383),
2104 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2105 /* AMD Hudson */
2106 { PCI_DEVICE(0x1022, 0x780d),
2107 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2108 /* ATI HDMI */
2109 { PCI_DEVICE(0x1002, 0x793b),
2110 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2111 { PCI_DEVICE(0x1002, 0x7919),
2112 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2113 { PCI_DEVICE(0x1002, 0x960f),
2114 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2115 { PCI_DEVICE(0x1002, 0x970f),
2116 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2117 { PCI_DEVICE(0x1002, 0xaa00),
2118 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2119 { PCI_DEVICE(0x1002, 0xaa08),
2120 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2121 { PCI_DEVICE(0x1002, 0xaa10),
2122 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2123 { PCI_DEVICE(0x1002, 0xaa18),
2124 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2125 { PCI_DEVICE(0x1002, 0xaa20),
2126 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2127 { PCI_DEVICE(0x1002, 0xaa28),
2128 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2129 { PCI_DEVICE(0x1002, 0xaa30),
2130 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2131 { PCI_DEVICE(0x1002, 0xaa38),
2132 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2133 { PCI_DEVICE(0x1002, 0xaa40),
2134 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2135 { PCI_DEVICE(0x1002, 0xaa48),
2136 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2137 { PCI_DEVICE(0x1002, 0xaa50),
2138 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2139 { PCI_DEVICE(0x1002, 0xaa58),
2140 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2141 { PCI_DEVICE(0x1002, 0xaa60),
2142 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2143 { PCI_DEVICE(0x1002, 0xaa68),
2144 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2145 { PCI_DEVICE(0x1002, 0xaa80),
2146 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2147 { PCI_DEVICE(0x1002, 0xaa88),
2148 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2149 { PCI_DEVICE(0x1002, 0xaa90),
2150 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2151 { PCI_DEVICE(0x1002, 0xaa98),
2152 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2153 { PCI_DEVICE(0x1002, 0x9902),
2154 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2155 { PCI_DEVICE(0x1002, 0xaaa0),
2156 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2157 { PCI_DEVICE(0x1002, 0xaaa8),
2158 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2159 { PCI_DEVICE(0x1002, 0xaab0),
2160 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2161 /* VIA VT8251/VT8237A */
2162 { PCI_DEVICE(0x1106, 0x3288),
2163 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2164 /* VIA GFX VT7122/VX900 */
2165 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2166 /* VIA GFX VT6122/VX11 */
2167 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2168 /* SIS966 */
2169 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2170 /* ULI M5461 */
2171 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2172 /* NVIDIA MCP */
2173 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2174 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2175 .class_mask = 0xffffff,
2176 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2177 /* Teradici */
2178 { PCI_DEVICE(0x6549, 0x1200),
2179 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2180 { PCI_DEVICE(0x6549, 0x2200),
2181 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2182 /* Creative X-Fi (CA0110-IBG) */
2183 /* CTHDA chips */
2184 { PCI_DEVICE(0x1102, 0x0010),
2185 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2186 { PCI_DEVICE(0x1102, 0x0012),
2187 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2188 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2189 /* the following entry conflicts with snd-ctxfi driver,
2190 * as ctxfi driver mutates from HD-audio to native mode with
2191 * a special command sequence.
2192 */
2193 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2194 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2195 .class_mask = 0xffffff,
2196 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2197 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2198 #else
2199 /* this entry seems still valid -- i.e. without emu20kx chip */
2200 { PCI_DEVICE(0x1102, 0x0009),
2201 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2202 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2203 #endif
2204 /* CM8888 */
2205 { PCI_DEVICE(0x13f6, 0x5011),
2206 .driver_data = AZX_DRIVER_CMEDIA |
2207 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2208 /* Vortex86MX */
2209 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2210 /* VMware HDAudio */
2211 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2212 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2213 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2214 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2215 .class_mask = 0xffffff,
2216 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2217 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2218 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2219 .class_mask = 0xffffff,
2220 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2221 { 0, }
2222 };
2223 MODULE_DEVICE_TABLE(pci, azx_ids);
2224
2225 /* pci_driver definition */
2226 static struct pci_driver azx_driver = {
2227 .name = KBUILD_MODNAME,
2228 .id_table = azx_ids,
2229 .probe = azx_probe,
2230 .remove = azx_remove,
2231 .shutdown = azx_shutdown,
2232 .driver = {
2233 .pm = AZX_PM_OPS,
2234 },
2235 };
2236
2237 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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