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76ec2421fae19655a4558870f93617a0d480b759
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #ifdef CONFIG_X86
51 /* for snoop control */
52 #include <asm/pgtable.h>
53 #include <asm/cacheflush.h>
54 #endif
55 #include <sound/core.h>
56 #include <sound/initval.h>
57 #include <linux/vgaarb.h>
58 #include <linux/vga_switcheroo.h>
59 #include <linux/firmware.h>
60 #include "hda_codec.h"
61
62
63 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
64 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
65 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
66 static char *model[SNDRV_CARDS];
67 static int position_fix[SNDRV_CARDS];
68 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
69 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
70 static int probe_only[SNDRV_CARDS];
71 static bool single_cmd;
72 static int enable_msi = -1;
73 #ifdef CONFIG_SND_HDA_PATCH_LOADER
74 static char *patch[SNDRV_CARDS];
75 #endif
76 #ifdef CONFIG_SND_HDA_INPUT_BEEP
77 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
78 CONFIG_SND_HDA_INPUT_BEEP_MODE};
79 #endif
80
81 module_param_array(index, int, NULL, 0444);
82 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
83 module_param_array(id, charp, NULL, 0444);
84 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
85 module_param_array(enable, bool, NULL, 0444);
86 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
87 module_param_array(model, charp, NULL, 0444);
88 MODULE_PARM_DESC(model, "Use the given board model.");
89 module_param_array(position_fix, int, NULL, 0444);
90 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
91 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
92 module_param_array(bdl_pos_adj, int, NULL, 0644);
93 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
94 module_param_array(probe_mask, int, NULL, 0444);
95 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
96 module_param_array(probe_only, int, NULL, 0444);
97 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
98 module_param(single_cmd, bool, 0444);
99 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
100 "(for debugging only).");
101 module_param(enable_msi, bint, 0444);
102 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
103 #ifdef CONFIG_SND_HDA_PATCH_LOADER
104 module_param_array(patch, charp, NULL, 0444);
105 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
106 #endif
107 #ifdef CONFIG_SND_HDA_INPUT_BEEP
108 module_param_array(beep_mode, bool, NULL, 0444);
109 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
110 "(0=off, 1=on) (default=1).");
111 #endif
112
113 #ifdef CONFIG_PM
114 static int param_set_xint(const char *val, const struct kernel_param *kp);
115 static struct kernel_param_ops param_ops_xint = {
116 .set = param_set_xint,
117 .get = param_get_int,
118 };
119 #define param_check_xint param_check_int
120
121 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
122 module_param(power_save, xint, 0644);
123 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
124 "(in second, 0 = disable).");
125
126 /* reset the HD-audio controller in power save mode.
127 * this may give more power-saving, but will take longer time to
128 * wake up.
129 */
130 static bool power_save_controller = 1;
131 module_param(power_save_controller, bool, 0644);
132 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
133 #endif /* CONFIG_PM */
134
135 static int align_buffer_size = -1;
136 module_param(align_buffer_size, bint, 0644);
137 MODULE_PARM_DESC(align_buffer_size,
138 "Force buffer and period sizes to be multiple of 128 bytes.");
139
140 #ifdef CONFIG_X86
141 static bool hda_snoop = true;
142 module_param_named(snoop, hda_snoop, bool, 0444);
143 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
144 #define azx_snoop(chip) (chip)->snoop
145 #else
146 #define hda_snoop true
147 #define azx_snoop(chip) true
148 #endif
149
150
151 MODULE_LICENSE("GPL");
152 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
153 "{Intel, ICH6M},"
154 "{Intel, ICH7},"
155 "{Intel, ESB2},"
156 "{Intel, ICH8},"
157 "{Intel, ICH9},"
158 "{Intel, ICH10},"
159 "{Intel, PCH},"
160 "{Intel, CPT},"
161 "{Intel, PPT},"
162 "{Intel, LPT},"
163 "{Intel, LPT_LP},"
164 "{Intel, HPT},"
165 "{Intel, PBG},"
166 "{Intel, SCH},"
167 "{ATI, SB450},"
168 "{ATI, SB600},"
169 "{ATI, RS600},"
170 "{ATI, RS690},"
171 "{ATI, RS780},"
172 "{ATI, R600},"
173 "{ATI, RV630},"
174 "{ATI, RV610},"
175 "{ATI, RV670},"
176 "{ATI, RV635},"
177 "{ATI, RV620},"
178 "{ATI, RV770},"
179 "{VIA, VT8251},"
180 "{VIA, VT8237A},"
181 "{SiS, SIS966},"
182 "{ULI, M5461}}");
183 MODULE_DESCRIPTION("Intel HDA driver");
184
185 #ifdef CONFIG_SND_VERBOSE_PRINTK
186 #define SFX /* nop */
187 #else
188 #define SFX "hda-intel: "
189 #endif
190
191 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
192 #ifdef CONFIG_SND_HDA_CODEC_HDMI
193 #define SUPPORT_VGA_SWITCHEROO
194 #endif
195 #endif
196
197
198 /*
199 * registers
200 */
201 #define ICH6_REG_GCAP 0x00
202 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
203 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
204 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
205 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
206 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
207 #define ICH6_REG_VMIN 0x02
208 #define ICH6_REG_VMAJ 0x03
209 #define ICH6_REG_OUTPAY 0x04
210 #define ICH6_REG_INPAY 0x06
211 #define ICH6_REG_GCTL 0x08
212 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
213 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
214 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
215 #define ICH6_REG_WAKEEN 0x0c
216 #define ICH6_REG_STATESTS 0x0e
217 #define ICH6_REG_GSTS 0x10
218 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
219 #define ICH6_REG_INTCTL 0x20
220 #define ICH6_REG_INTSTS 0x24
221 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
222 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
223 #define ICH6_REG_SSYNC 0x38
224 #define ICH6_REG_CORBLBASE 0x40
225 #define ICH6_REG_CORBUBASE 0x44
226 #define ICH6_REG_CORBWP 0x48
227 #define ICH6_REG_CORBRP 0x4a
228 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
229 #define ICH6_REG_CORBCTL 0x4c
230 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
231 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
232 #define ICH6_REG_CORBSTS 0x4d
233 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
234 #define ICH6_REG_CORBSIZE 0x4e
235
236 #define ICH6_REG_RIRBLBASE 0x50
237 #define ICH6_REG_RIRBUBASE 0x54
238 #define ICH6_REG_RIRBWP 0x58
239 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
240 #define ICH6_REG_RINTCNT 0x5a
241 #define ICH6_REG_RIRBCTL 0x5c
242 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
243 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
244 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
245 #define ICH6_REG_RIRBSTS 0x5d
246 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
247 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
248 #define ICH6_REG_RIRBSIZE 0x5e
249
250 #define ICH6_REG_IC 0x60
251 #define ICH6_REG_IR 0x64
252 #define ICH6_REG_IRS 0x68
253 #define ICH6_IRS_VALID (1<<1)
254 #define ICH6_IRS_BUSY (1<<0)
255
256 #define ICH6_REG_DPLBASE 0x70
257 #define ICH6_REG_DPUBASE 0x74
258 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
259
260 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
261 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
262
263 /* stream register offsets from stream base */
264 #define ICH6_REG_SD_CTL 0x00
265 #define ICH6_REG_SD_STS 0x03
266 #define ICH6_REG_SD_LPIB 0x04
267 #define ICH6_REG_SD_CBL 0x08
268 #define ICH6_REG_SD_LVI 0x0c
269 #define ICH6_REG_SD_FIFOW 0x0e
270 #define ICH6_REG_SD_FIFOSIZE 0x10
271 #define ICH6_REG_SD_FORMAT 0x12
272 #define ICH6_REG_SD_BDLPL 0x18
273 #define ICH6_REG_SD_BDLPU 0x1c
274
275 /* PCI space */
276 #define ICH6_PCIREG_TCSEL 0x44
277
278 /*
279 * other constants
280 */
281
282 /* max number of SDs */
283 /* ICH, ATI and VIA have 4 playback and 4 capture */
284 #define ICH6_NUM_CAPTURE 4
285 #define ICH6_NUM_PLAYBACK 4
286
287 /* ULI has 6 playback and 5 capture */
288 #define ULI_NUM_CAPTURE 5
289 #define ULI_NUM_PLAYBACK 6
290
291 /* ATI HDMI has 1 playback and 0 capture */
292 #define ATIHDMI_NUM_CAPTURE 0
293 #define ATIHDMI_NUM_PLAYBACK 1
294
295 /* TERA has 4 playback and 3 capture */
296 #define TERA_NUM_CAPTURE 3
297 #define TERA_NUM_PLAYBACK 4
298
299 /* this number is statically defined for simplicity */
300 #define MAX_AZX_DEV 16
301
302 /* max number of fragments - we may use more if allocating more pages for BDL */
303 #define BDL_SIZE 4096
304 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
305 #define AZX_MAX_FRAG 32
306 /* max buffer size - no h/w limit, you can increase as you like */
307 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
308
309 /* RIRB int mask: overrun[2], response[0] */
310 #define RIRB_INT_RESPONSE 0x01
311 #define RIRB_INT_OVERRUN 0x04
312 #define RIRB_INT_MASK 0x05
313
314 /* STATESTS int mask: S3,SD2,SD1,SD0 */
315 #define AZX_MAX_CODECS 8
316 #define AZX_DEFAULT_CODECS 4
317 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
318
319 /* SD_CTL bits */
320 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
321 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
322 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
323 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
324 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
325 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
326 #define SD_CTL_STREAM_TAG_SHIFT 20
327
328 /* SD_CTL and SD_STS */
329 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
330 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
331 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
332 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
333 SD_INT_COMPLETE)
334
335 /* SD_STS */
336 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
337
338 /* INTCTL and INTSTS */
339 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
340 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
341 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
342
343 /* below are so far hardcoded - should read registers in future */
344 #define ICH6_MAX_CORB_ENTRIES 256
345 #define ICH6_MAX_RIRB_ENTRIES 256
346
347 /* position fix mode */
348 enum {
349 POS_FIX_AUTO,
350 POS_FIX_LPIB,
351 POS_FIX_POSBUF,
352 POS_FIX_VIACOMBO,
353 POS_FIX_COMBO,
354 };
355
356 /* Defines for ATI HD Audio support in SB450 south bridge */
357 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
358 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
359
360 /* Defines for Nvidia HDA support */
361 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
362 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
363 #define NVIDIA_HDA_ISTRM_COH 0x4d
364 #define NVIDIA_HDA_OSTRM_COH 0x4c
365 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
366
367 /* Defines for Intel SCH HDA snoop control */
368 #define INTEL_SCH_HDA_DEVC 0x78
369 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
370
371 /* Define IN stream 0 FIFO size offset in VIA controller */
372 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
373 /* Define VIA HD Audio Device ID*/
374 #define VIA_HDAC_DEVICE_ID 0x3288
375
376 /* HD Audio class code */
377 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
378
379 /*
380 */
381
382 struct azx_dev {
383 struct snd_dma_buffer bdl; /* BDL buffer */
384 u32 *posbuf; /* position buffer pointer */
385
386 unsigned int bufsize; /* size of the play buffer in bytes */
387 unsigned int period_bytes; /* size of the period in bytes */
388 unsigned int frags; /* number for period in the play buffer */
389 unsigned int fifo_size; /* FIFO size */
390 unsigned long start_wallclk; /* start + minimum wallclk */
391 unsigned long period_wallclk; /* wallclk for period */
392
393 void __iomem *sd_addr; /* stream descriptor pointer */
394
395 u32 sd_int_sta_mask; /* stream int status mask */
396
397 /* pcm support */
398 struct snd_pcm_substream *substream; /* assigned substream,
399 * set in PCM open
400 */
401 unsigned int format_val; /* format value to be set in the
402 * controller and the codec
403 */
404 unsigned char stream_tag; /* assigned stream */
405 unsigned char index; /* stream index */
406 int assigned_key; /* last device# key assigned to */
407
408 unsigned int opened :1;
409 unsigned int running :1;
410 unsigned int irq_pending :1;
411 /*
412 * For VIA:
413 * A flag to ensure DMA position is 0
414 * when link position is not greater than FIFO size
415 */
416 unsigned int insufficient :1;
417 unsigned int wc_marked:1;
418 unsigned int no_period_wakeup:1;
419 };
420
421 /* CORB/RIRB */
422 struct azx_rb {
423 u32 *buf; /* CORB/RIRB buffer
424 * Each CORB entry is 4byte, RIRB is 8byte
425 */
426 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
427 /* for RIRB */
428 unsigned short rp, wp; /* read/write pointers */
429 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
430 u32 res[AZX_MAX_CODECS]; /* last read value */
431 };
432
433 struct azx_pcm {
434 struct azx *chip;
435 struct snd_pcm *pcm;
436 struct hda_codec *codec;
437 struct hda_pcm_stream *hinfo[2];
438 struct list_head list;
439 };
440
441 struct azx {
442 struct snd_card *card;
443 struct pci_dev *pci;
444 int dev_index;
445
446 /* chip type specific */
447 int driver_type;
448 unsigned int driver_caps;
449 int playback_streams;
450 int playback_index_offset;
451 int capture_streams;
452 int capture_index_offset;
453 int num_streams;
454
455 /* pci resources */
456 unsigned long addr;
457 void __iomem *remap_addr;
458 int irq;
459
460 /* locks */
461 spinlock_t reg_lock;
462 struct mutex open_mutex;
463
464 /* streams (x num_streams) */
465 struct azx_dev *azx_dev;
466
467 /* PCM */
468 struct list_head pcm_list; /* azx_pcm list */
469
470 /* HD codec */
471 unsigned short codec_mask;
472 int codec_probe_mask; /* copied from probe_mask option */
473 struct hda_bus *bus;
474 unsigned int beep_mode;
475
476 /* CORB/RIRB */
477 struct azx_rb corb;
478 struct azx_rb rirb;
479
480 /* CORB/RIRB and position buffers */
481 struct snd_dma_buffer rb;
482 struct snd_dma_buffer posbuf;
483
484 #ifdef CONFIG_SND_HDA_PATCH_LOADER
485 const struct firmware *fw;
486 #endif
487
488 /* flags */
489 int position_fix[2]; /* for both playback/capture streams */
490 int poll_count;
491 unsigned int running :1;
492 unsigned int initialized :1;
493 unsigned int single_cmd :1;
494 unsigned int polling_mode :1;
495 unsigned int msi :1;
496 unsigned int irq_pending_warned :1;
497 unsigned int probing :1; /* codec probing phase */
498 unsigned int snoop:1;
499 unsigned int align_buffer_size:1;
500 unsigned int region_requested:1;
501
502 /* VGA-switcheroo setup */
503 unsigned int use_vga_switcheroo:1;
504 unsigned int init_failed:1; /* delayed init failed */
505 unsigned int disabled:1; /* disabled by VGA-switcher */
506
507 /* for debugging */
508 unsigned int last_cmd[AZX_MAX_CODECS];
509
510 /* for pending irqs */
511 struct work_struct irq_pending_work;
512
513 /* reboot notifier (for mysterious hangup problem at power-down) */
514 struct notifier_block reboot_notifier;
515
516 /* card list (for power_save trigger) */
517 struct list_head list;
518 };
519
520 /* driver types */
521 enum {
522 AZX_DRIVER_ICH,
523 AZX_DRIVER_PCH,
524 AZX_DRIVER_SCH,
525 AZX_DRIVER_ATI,
526 AZX_DRIVER_ATIHDMI,
527 AZX_DRIVER_ATIHDMI_NS,
528 AZX_DRIVER_VIA,
529 AZX_DRIVER_SIS,
530 AZX_DRIVER_ULI,
531 AZX_DRIVER_NVIDIA,
532 AZX_DRIVER_TERA,
533 AZX_DRIVER_CTX,
534 AZX_DRIVER_CTHDA,
535 AZX_DRIVER_GENERIC,
536 AZX_NUM_DRIVERS, /* keep this as last entry */
537 };
538
539 /* driver quirks (capabilities) */
540 /* bits 0-7 are used for indicating driver type */
541 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
542 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
543 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
544 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
545 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
546 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
547 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
548 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
549 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
550 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
551 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
552 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
553 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
554 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
555 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
556 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
557 #define AZX_DCAPS_POSFIX_COMBO (1 << 24) /* Use COMBO as default */
558
559 /* quirks for ATI SB / AMD Hudson */
560 #define AZX_DCAPS_PRESET_ATI_SB \
561 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
562 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
563
564 /* quirks for ATI/AMD HDMI */
565 #define AZX_DCAPS_PRESET_ATI_HDMI \
566 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
567
568 /* quirks for Nvidia */
569 #define AZX_DCAPS_PRESET_NVIDIA \
570 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
571 AZX_DCAPS_ALIGN_BUFSIZE)
572
573 #define AZX_DCAPS_PRESET_CTHDA \
574 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
575
576 /*
577 * VGA-switcher support
578 */
579 #ifdef SUPPORT_VGA_SWITCHEROO
580 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
581 #else
582 #define use_vga_switcheroo(chip) 0
583 #endif
584
585 #if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
586 #define DELAYED_INIT_MARK
587 #define DELAYED_INITDATA_MARK
588 #else
589 #define DELAYED_INIT_MARK __devinit
590 #define DELAYED_INITDATA_MARK __devinitdata
591 #endif
592
593 static char *driver_short_names[] DELAYED_INITDATA_MARK = {
594 [AZX_DRIVER_ICH] = "HDA Intel",
595 [AZX_DRIVER_PCH] = "HDA Intel PCH",
596 [AZX_DRIVER_SCH] = "HDA Intel MID",
597 [AZX_DRIVER_ATI] = "HDA ATI SB",
598 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
599 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
600 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
601 [AZX_DRIVER_SIS] = "HDA SIS966",
602 [AZX_DRIVER_ULI] = "HDA ULI M5461",
603 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
604 [AZX_DRIVER_TERA] = "HDA Teradici",
605 [AZX_DRIVER_CTX] = "HDA Creative",
606 [AZX_DRIVER_CTHDA] = "HDA Creative",
607 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
608 };
609
610 /*
611 * macros for easy use
612 */
613 #define azx_writel(chip,reg,value) \
614 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
615 #define azx_readl(chip,reg) \
616 readl((chip)->remap_addr + ICH6_REG_##reg)
617 #define azx_writew(chip,reg,value) \
618 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
619 #define azx_readw(chip,reg) \
620 readw((chip)->remap_addr + ICH6_REG_##reg)
621 #define azx_writeb(chip,reg,value) \
622 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
623 #define azx_readb(chip,reg) \
624 readb((chip)->remap_addr + ICH6_REG_##reg)
625
626 #define azx_sd_writel(dev,reg,value) \
627 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
628 #define azx_sd_readl(dev,reg) \
629 readl((dev)->sd_addr + ICH6_REG_##reg)
630 #define azx_sd_writew(dev,reg,value) \
631 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
632 #define azx_sd_readw(dev,reg) \
633 readw((dev)->sd_addr + ICH6_REG_##reg)
634 #define azx_sd_writeb(dev,reg,value) \
635 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
636 #define azx_sd_readb(dev,reg) \
637 readb((dev)->sd_addr + ICH6_REG_##reg)
638
639 /* for pcm support */
640 #define get_azx_dev(substream) (substream->runtime->private_data)
641
642 #ifdef CONFIG_X86
643 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
644 {
645 if (azx_snoop(chip))
646 return;
647 if (addr && size) {
648 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
649 if (on)
650 set_memory_wc((unsigned long)addr, pages);
651 else
652 set_memory_wb((unsigned long)addr, pages);
653 }
654 }
655
656 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
657 bool on)
658 {
659 __mark_pages_wc(chip, buf->area, buf->bytes, on);
660 }
661 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
662 struct snd_pcm_runtime *runtime, bool on)
663 {
664 if (azx_dev->wc_marked != on) {
665 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
666 azx_dev->wc_marked = on;
667 }
668 }
669 #else
670 /* NOP for other archs */
671 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
672 bool on)
673 {
674 }
675 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
676 struct snd_pcm_runtime *runtime, bool on)
677 {
678 }
679 #endif
680
681 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
682 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
683 /*
684 * Interface for HD codec
685 */
686
687 /*
688 * CORB / RIRB interface
689 */
690 static int azx_alloc_cmd_io(struct azx *chip)
691 {
692 int err;
693
694 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
695 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
696 snd_dma_pci_data(chip->pci),
697 PAGE_SIZE, &chip->rb);
698 if (err < 0) {
699 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
700 return err;
701 }
702 mark_pages_wc(chip, &chip->rb, true);
703 return 0;
704 }
705
706 static void azx_init_cmd_io(struct azx *chip)
707 {
708 spin_lock_irq(&chip->reg_lock);
709 /* CORB set up */
710 chip->corb.addr = chip->rb.addr;
711 chip->corb.buf = (u32 *)chip->rb.area;
712 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
713 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
714
715 /* set the corb size to 256 entries (ULI requires explicitly) */
716 azx_writeb(chip, CORBSIZE, 0x02);
717 /* set the corb write pointer to 0 */
718 azx_writew(chip, CORBWP, 0);
719 /* reset the corb hw read pointer */
720 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
721 /* enable corb dma */
722 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
723
724 /* RIRB set up */
725 chip->rirb.addr = chip->rb.addr + 2048;
726 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
727 chip->rirb.wp = chip->rirb.rp = 0;
728 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
729 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
730 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
731
732 /* set the rirb size to 256 entries (ULI requires explicitly) */
733 azx_writeb(chip, RIRBSIZE, 0x02);
734 /* reset the rirb hw write pointer */
735 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
736 /* set N=1, get RIRB response interrupt for new entry */
737 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
738 azx_writew(chip, RINTCNT, 0xc0);
739 else
740 azx_writew(chip, RINTCNT, 1);
741 /* enable rirb dma and response irq */
742 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
743 spin_unlock_irq(&chip->reg_lock);
744 }
745
746 static void azx_free_cmd_io(struct azx *chip)
747 {
748 spin_lock_irq(&chip->reg_lock);
749 /* disable ringbuffer DMAs */
750 azx_writeb(chip, RIRBCTL, 0);
751 azx_writeb(chip, CORBCTL, 0);
752 spin_unlock_irq(&chip->reg_lock);
753 }
754
755 static unsigned int azx_command_addr(u32 cmd)
756 {
757 unsigned int addr = cmd >> 28;
758
759 if (addr >= AZX_MAX_CODECS) {
760 snd_BUG();
761 addr = 0;
762 }
763
764 return addr;
765 }
766
767 static unsigned int azx_response_addr(u32 res)
768 {
769 unsigned int addr = res & 0xf;
770
771 if (addr >= AZX_MAX_CODECS) {
772 snd_BUG();
773 addr = 0;
774 }
775
776 return addr;
777 }
778
779 /* send a command */
780 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
781 {
782 struct azx *chip = bus->private_data;
783 unsigned int addr = azx_command_addr(val);
784 unsigned int wp;
785
786 spin_lock_irq(&chip->reg_lock);
787
788 /* add command to corb */
789 wp = azx_readb(chip, CORBWP);
790 wp++;
791 wp %= ICH6_MAX_CORB_ENTRIES;
792
793 chip->rirb.cmds[addr]++;
794 chip->corb.buf[wp] = cpu_to_le32(val);
795 azx_writel(chip, CORBWP, wp);
796
797 spin_unlock_irq(&chip->reg_lock);
798
799 return 0;
800 }
801
802 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
803
804 /* retrieve RIRB entry - called from interrupt handler */
805 static void azx_update_rirb(struct azx *chip)
806 {
807 unsigned int rp, wp;
808 unsigned int addr;
809 u32 res, res_ex;
810
811 wp = azx_readb(chip, RIRBWP);
812 if (wp == chip->rirb.wp)
813 return;
814 chip->rirb.wp = wp;
815
816 while (chip->rirb.rp != wp) {
817 chip->rirb.rp++;
818 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
819
820 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
821 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
822 res = le32_to_cpu(chip->rirb.buf[rp]);
823 addr = azx_response_addr(res_ex);
824 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
825 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
826 else if (chip->rirb.cmds[addr]) {
827 chip->rirb.res[addr] = res;
828 smp_wmb();
829 chip->rirb.cmds[addr]--;
830 } else
831 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
832 "last cmd=%#08x\n",
833 res, res_ex,
834 chip->last_cmd[addr]);
835 }
836 }
837
838 /* receive a response */
839 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
840 unsigned int addr)
841 {
842 struct azx *chip = bus->private_data;
843 unsigned long timeout;
844 unsigned long loopcounter;
845 int do_poll = 0;
846
847 again:
848 timeout = jiffies + msecs_to_jiffies(1000);
849
850 for (loopcounter = 0;; loopcounter++) {
851 if (chip->polling_mode || do_poll) {
852 spin_lock_irq(&chip->reg_lock);
853 azx_update_rirb(chip);
854 spin_unlock_irq(&chip->reg_lock);
855 }
856 if (!chip->rirb.cmds[addr]) {
857 smp_rmb();
858 bus->rirb_error = 0;
859
860 if (!do_poll)
861 chip->poll_count = 0;
862 return chip->rirb.res[addr]; /* the last value */
863 }
864 if (time_after(jiffies, timeout))
865 break;
866 if (bus->needs_damn_long_delay || loopcounter > 3000)
867 msleep(2); /* temporary workaround */
868 else {
869 udelay(10);
870 cond_resched();
871 }
872 }
873
874 if (!chip->polling_mode && chip->poll_count < 2) {
875 snd_printdd(SFX "azx_get_response timeout, "
876 "polling the codec once: last cmd=0x%08x\n",
877 chip->last_cmd[addr]);
878 do_poll = 1;
879 chip->poll_count++;
880 goto again;
881 }
882
883
884 if (!chip->polling_mode) {
885 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
886 "switching to polling mode: last cmd=0x%08x\n",
887 chip->last_cmd[addr]);
888 chip->polling_mode = 1;
889 goto again;
890 }
891
892 if (chip->msi) {
893 snd_printk(KERN_WARNING SFX "No response from codec, "
894 "disabling MSI: last cmd=0x%08x\n",
895 chip->last_cmd[addr]);
896 free_irq(chip->irq, chip);
897 chip->irq = -1;
898 pci_disable_msi(chip->pci);
899 chip->msi = 0;
900 if (azx_acquire_irq(chip, 1) < 0) {
901 bus->rirb_error = 1;
902 return -1;
903 }
904 goto again;
905 }
906
907 if (chip->probing) {
908 /* If this critical timeout happens during the codec probing
909 * phase, this is likely an access to a non-existing codec
910 * slot. Better to return an error and reset the system.
911 */
912 return -1;
913 }
914
915 /* a fatal communication error; need either to reset or to fallback
916 * to the single_cmd mode
917 */
918 bus->rirb_error = 1;
919 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
920 bus->response_reset = 1;
921 return -1; /* give a chance to retry */
922 }
923
924 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
925 "switching to single_cmd mode: last cmd=0x%08x\n",
926 chip->last_cmd[addr]);
927 chip->single_cmd = 1;
928 bus->response_reset = 0;
929 /* release CORB/RIRB */
930 azx_free_cmd_io(chip);
931 /* disable unsolicited responses */
932 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
933 return -1;
934 }
935
936 /*
937 * Use the single immediate command instead of CORB/RIRB for simplicity
938 *
939 * Note: according to Intel, this is not preferred use. The command was
940 * intended for the BIOS only, and may get confused with unsolicited
941 * responses. So, we shouldn't use it for normal operation from the
942 * driver.
943 * I left the codes, however, for debugging/testing purposes.
944 */
945
946 /* receive a response */
947 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
948 {
949 int timeout = 50;
950
951 while (timeout--) {
952 /* check IRV busy bit */
953 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
954 /* reuse rirb.res as the response return value */
955 chip->rirb.res[addr] = azx_readl(chip, IR);
956 return 0;
957 }
958 udelay(1);
959 }
960 if (printk_ratelimit())
961 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
962 azx_readw(chip, IRS));
963 chip->rirb.res[addr] = -1;
964 return -EIO;
965 }
966
967 /* send a command */
968 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
969 {
970 struct azx *chip = bus->private_data;
971 unsigned int addr = azx_command_addr(val);
972 int timeout = 50;
973
974 bus->rirb_error = 0;
975 while (timeout--) {
976 /* check ICB busy bit */
977 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
978 /* Clear IRV valid bit */
979 azx_writew(chip, IRS, azx_readw(chip, IRS) |
980 ICH6_IRS_VALID);
981 azx_writel(chip, IC, val);
982 azx_writew(chip, IRS, azx_readw(chip, IRS) |
983 ICH6_IRS_BUSY);
984 return azx_single_wait_for_response(chip, addr);
985 }
986 udelay(1);
987 }
988 if (printk_ratelimit())
989 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
990 azx_readw(chip, IRS), val);
991 return -EIO;
992 }
993
994 /* receive a response */
995 static unsigned int azx_single_get_response(struct hda_bus *bus,
996 unsigned int addr)
997 {
998 struct azx *chip = bus->private_data;
999 return chip->rirb.res[addr];
1000 }
1001
1002 /*
1003 * The below are the main callbacks from hda_codec.
1004 *
1005 * They are just the skeleton to call sub-callbacks according to the
1006 * current setting of chip->single_cmd.
1007 */
1008
1009 /* send a command */
1010 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1011 {
1012 struct azx *chip = bus->private_data;
1013
1014 if (chip->disabled)
1015 return 0;
1016 chip->last_cmd[azx_command_addr(val)] = val;
1017 if (chip->single_cmd)
1018 return azx_single_send_cmd(bus, val);
1019 else
1020 return azx_corb_send_cmd(bus, val);
1021 }
1022
1023 /* get a response */
1024 static unsigned int azx_get_response(struct hda_bus *bus,
1025 unsigned int addr)
1026 {
1027 struct azx *chip = bus->private_data;
1028 if (chip->disabled)
1029 return 0;
1030 if (chip->single_cmd)
1031 return azx_single_get_response(bus, addr);
1032 else
1033 return azx_rirb_get_response(bus, addr);
1034 }
1035
1036 #ifdef CONFIG_PM
1037 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1038 #endif
1039
1040 /* reset codec link */
1041 static int azx_reset(struct azx *chip, int full_reset)
1042 {
1043 int count;
1044
1045 if (!full_reset)
1046 goto __skip;
1047
1048 /* clear STATESTS */
1049 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1050
1051 /* reset controller */
1052 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1053
1054 count = 50;
1055 while (azx_readb(chip, GCTL) && --count)
1056 msleep(1);
1057
1058 /* delay for >= 100us for codec PLL to settle per spec
1059 * Rev 0.9 section 5.5.1
1060 */
1061 msleep(1);
1062
1063 /* Bring controller out of reset */
1064 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1065
1066 count = 50;
1067 while (!azx_readb(chip, GCTL) && --count)
1068 msleep(1);
1069
1070 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1071 msleep(1);
1072
1073 __skip:
1074 /* check to see if controller is ready */
1075 if (!azx_readb(chip, GCTL)) {
1076 snd_printd(SFX "azx_reset: controller not ready!\n");
1077 return -EBUSY;
1078 }
1079
1080 /* Accept unsolicited responses */
1081 if (!chip->single_cmd)
1082 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1083 ICH6_GCTL_UNSOL);
1084
1085 /* detect codecs */
1086 if (!chip->codec_mask) {
1087 chip->codec_mask = azx_readw(chip, STATESTS);
1088 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1089 }
1090
1091 return 0;
1092 }
1093
1094
1095 /*
1096 * Lowlevel interface
1097 */
1098
1099 /* enable interrupts */
1100 static void azx_int_enable(struct azx *chip)
1101 {
1102 /* enable controller CIE and GIE */
1103 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1104 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1105 }
1106
1107 /* disable interrupts */
1108 static void azx_int_disable(struct azx *chip)
1109 {
1110 int i;
1111
1112 /* disable interrupts in stream descriptor */
1113 for (i = 0; i < chip->num_streams; i++) {
1114 struct azx_dev *azx_dev = &chip->azx_dev[i];
1115 azx_sd_writeb(azx_dev, SD_CTL,
1116 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1117 }
1118
1119 /* disable SIE for all streams */
1120 azx_writeb(chip, INTCTL, 0);
1121
1122 /* disable controller CIE and GIE */
1123 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1124 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1125 }
1126
1127 /* clear interrupts */
1128 static void azx_int_clear(struct azx *chip)
1129 {
1130 int i;
1131
1132 /* clear stream status */
1133 for (i = 0; i < chip->num_streams; i++) {
1134 struct azx_dev *azx_dev = &chip->azx_dev[i];
1135 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1136 }
1137
1138 /* clear STATESTS */
1139 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1140
1141 /* clear rirb status */
1142 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1143
1144 /* clear int status */
1145 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1146 }
1147
1148 /* start a stream */
1149 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1150 {
1151 /*
1152 * Before stream start, initialize parameter
1153 */
1154 azx_dev->insufficient = 1;
1155
1156 /* enable SIE */
1157 azx_writel(chip, INTCTL,
1158 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1159 /* set DMA start and interrupt mask */
1160 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1161 SD_CTL_DMA_START | SD_INT_MASK);
1162 }
1163
1164 /* stop DMA */
1165 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1166 {
1167 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1168 ~(SD_CTL_DMA_START | SD_INT_MASK));
1169 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1170 }
1171
1172 /* stop a stream */
1173 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1174 {
1175 azx_stream_clear(chip, azx_dev);
1176 /* disable SIE */
1177 azx_writel(chip, INTCTL,
1178 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1179 }
1180
1181
1182 /*
1183 * reset and start the controller registers
1184 */
1185 static void azx_init_chip(struct azx *chip, int full_reset)
1186 {
1187 if (chip->initialized)
1188 return;
1189
1190 /* reset controller */
1191 azx_reset(chip, full_reset);
1192
1193 /* initialize interrupts */
1194 azx_int_clear(chip);
1195 azx_int_enable(chip);
1196
1197 /* initialize the codec command I/O */
1198 if (!chip->single_cmd)
1199 azx_init_cmd_io(chip);
1200
1201 /* program the position buffer */
1202 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1203 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1204
1205 chip->initialized = 1;
1206 }
1207
1208 /*
1209 * initialize the PCI registers
1210 */
1211 /* update bits in a PCI register byte */
1212 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1213 unsigned char mask, unsigned char val)
1214 {
1215 unsigned char data;
1216
1217 pci_read_config_byte(pci, reg, &data);
1218 data &= ~mask;
1219 data |= (val & mask);
1220 pci_write_config_byte(pci, reg, data);
1221 }
1222
1223 static void azx_init_pci(struct azx *chip)
1224 {
1225 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1226 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1227 * Ensuring these bits are 0 clears playback static on some HD Audio
1228 * codecs.
1229 * The PCI register TCSEL is defined in the Intel manuals.
1230 */
1231 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1232 snd_printdd(SFX "Clearing TCSEL\n");
1233 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1234 }
1235
1236 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1237 * we need to enable snoop.
1238 */
1239 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1240 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1241 update_pci_byte(chip->pci,
1242 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1243 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1244 }
1245
1246 /* For NVIDIA HDA, enable snoop */
1247 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1248 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1249 update_pci_byte(chip->pci,
1250 NVIDIA_HDA_TRANSREG_ADDR,
1251 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1252 update_pci_byte(chip->pci,
1253 NVIDIA_HDA_ISTRM_COH,
1254 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1255 update_pci_byte(chip->pci,
1256 NVIDIA_HDA_OSTRM_COH,
1257 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1258 }
1259
1260 /* Enable SCH/PCH snoop if needed */
1261 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1262 unsigned short snoop;
1263 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1264 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1265 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1266 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1267 if (!azx_snoop(chip))
1268 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1269 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1270 pci_read_config_word(chip->pci,
1271 INTEL_SCH_HDA_DEVC, &snoop);
1272 }
1273 snd_printdd(SFX "SCH snoop: %s\n",
1274 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1275 ? "Disabled" : "Enabled");
1276 }
1277 }
1278
1279
1280 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1281
1282 /*
1283 * interrupt handler
1284 */
1285 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1286 {
1287 struct azx *chip = dev_id;
1288 struct azx_dev *azx_dev;
1289 u32 status;
1290 u8 sd_status;
1291 int i, ok;
1292
1293 #ifdef CONFIG_PM_RUNTIME
1294 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1295 return IRQ_NONE;
1296 #endif
1297
1298 spin_lock(&chip->reg_lock);
1299
1300 if (chip->disabled) {
1301 spin_unlock(&chip->reg_lock);
1302 return IRQ_NONE;
1303 }
1304
1305 status = azx_readl(chip, INTSTS);
1306 if (status == 0) {
1307 spin_unlock(&chip->reg_lock);
1308 return IRQ_NONE;
1309 }
1310
1311 for (i = 0; i < chip->num_streams; i++) {
1312 azx_dev = &chip->azx_dev[i];
1313 if (status & azx_dev->sd_int_sta_mask) {
1314 sd_status = azx_sd_readb(azx_dev, SD_STS);
1315 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1316 if (!azx_dev->substream || !azx_dev->running ||
1317 !(sd_status & SD_INT_COMPLETE))
1318 continue;
1319 /* check whether this IRQ is really acceptable */
1320 ok = azx_position_ok(chip, azx_dev);
1321 if (ok == 1) {
1322 azx_dev->irq_pending = 0;
1323 spin_unlock(&chip->reg_lock);
1324 snd_pcm_period_elapsed(azx_dev->substream);
1325 spin_lock(&chip->reg_lock);
1326 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1327 /* bogus IRQ, process it later */
1328 azx_dev->irq_pending = 1;
1329 queue_work(chip->bus->workq,
1330 &chip->irq_pending_work);
1331 }
1332 }
1333 }
1334
1335 /* clear rirb int */
1336 status = azx_readb(chip, RIRBSTS);
1337 if (status & RIRB_INT_MASK) {
1338 if (status & RIRB_INT_RESPONSE) {
1339 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1340 udelay(80);
1341 azx_update_rirb(chip);
1342 }
1343 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1344 }
1345
1346 #if 0
1347 /* clear state status int */
1348 if (azx_readb(chip, STATESTS) & 0x04)
1349 azx_writeb(chip, STATESTS, 0x04);
1350 #endif
1351 spin_unlock(&chip->reg_lock);
1352
1353 return IRQ_HANDLED;
1354 }
1355
1356
1357 /*
1358 * set up a BDL entry
1359 */
1360 static int setup_bdle(struct azx *chip,
1361 struct snd_pcm_substream *substream,
1362 struct azx_dev *azx_dev, u32 **bdlp,
1363 int ofs, int size, int with_ioc)
1364 {
1365 u32 *bdl = *bdlp;
1366
1367 while (size > 0) {
1368 dma_addr_t addr;
1369 int chunk;
1370
1371 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1372 return -EINVAL;
1373
1374 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1375 /* program the address field of the BDL entry */
1376 bdl[0] = cpu_to_le32((u32)addr);
1377 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1378 /* program the size field of the BDL entry */
1379 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1380 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1381 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1382 u32 remain = 0x1000 - (ofs & 0xfff);
1383 if (chunk > remain)
1384 chunk = remain;
1385 }
1386 bdl[2] = cpu_to_le32(chunk);
1387 /* program the IOC to enable interrupt
1388 * only when the whole fragment is processed
1389 */
1390 size -= chunk;
1391 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1392 bdl += 4;
1393 azx_dev->frags++;
1394 ofs += chunk;
1395 }
1396 *bdlp = bdl;
1397 return ofs;
1398 }
1399
1400 /*
1401 * set up BDL entries
1402 */
1403 static int azx_setup_periods(struct azx *chip,
1404 struct snd_pcm_substream *substream,
1405 struct azx_dev *azx_dev)
1406 {
1407 u32 *bdl;
1408 int i, ofs, periods, period_bytes;
1409 int pos_adj;
1410
1411 /* reset BDL address */
1412 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1413 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1414
1415 period_bytes = azx_dev->period_bytes;
1416 periods = azx_dev->bufsize / period_bytes;
1417
1418 /* program the initial BDL entries */
1419 bdl = (u32 *)azx_dev->bdl.area;
1420 ofs = 0;
1421 azx_dev->frags = 0;
1422 pos_adj = bdl_pos_adj[chip->dev_index];
1423 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1424 struct snd_pcm_runtime *runtime = substream->runtime;
1425 int pos_align = pos_adj;
1426 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1427 if (!pos_adj)
1428 pos_adj = pos_align;
1429 else
1430 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1431 pos_align;
1432 pos_adj = frames_to_bytes(runtime, pos_adj);
1433 if (pos_adj >= period_bytes) {
1434 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1435 bdl_pos_adj[chip->dev_index]);
1436 pos_adj = 0;
1437 } else {
1438 ofs = setup_bdle(chip, substream, azx_dev,
1439 &bdl, ofs, pos_adj, true);
1440 if (ofs < 0)
1441 goto error;
1442 }
1443 } else
1444 pos_adj = 0;
1445 for (i = 0; i < periods; i++) {
1446 if (i == periods - 1 && pos_adj)
1447 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1448 period_bytes - pos_adj, 0);
1449 else
1450 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1451 period_bytes,
1452 !azx_dev->no_period_wakeup);
1453 if (ofs < 0)
1454 goto error;
1455 }
1456 return 0;
1457
1458 error:
1459 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1460 azx_dev->bufsize, period_bytes);
1461 return -EINVAL;
1462 }
1463
1464 /* reset stream */
1465 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1466 {
1467 unsigned char val;
1468 int timeout;
1469
1470 azx_stream_clear(chip, azx_dev);
1471
1472 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1473 SD_CTL_STREAM_RESET);
1474 udelay(3);
1475 timeout = 300;
1476 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1477 --timeout)
1478 ;
1479 val &= ~SD_CTL_STREAM_RESET;
1480 azx_sd_writeb(azx_dev, SD_CTL, val);
1481 udelay(3);
1482
1483 timeout = 300;
1484 /* waiting for hardware to report that the stream is out of reset */
1485 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1486 --timeout)
1487 ;
1488
1489 /* reset first position - may not be synced with hw at this time */
1490 *azx_dev->posbuf = 0;
1491 }
1492
1493 /*
1494 * set up the SD for streaming
1495 */
1496 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1497 {
1498 unsigned int val;
1499 /* make sure the run bit is zero for SD */
1500 azx_stream_clear(chip, azx_dev);
1501 /* program the stream_tag */
1502 val = azx_sd_readl(azx_dev, SD_CTL);
1503 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1504 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1505 if (!azx_snoop(chip))
1506 val |= SD_CTL_TRAFFIC_PRIO;
1507 azx_sd_writel(azx_dev, SD_CTL, val);
1508
1509 /* program the length of samples in cyclic buffer */
1510 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1511
1512 /* program the stream format */
1513 /* this value needs to be the same as the one programmed */
1514 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1515
1516 /* program the stream LVI (last valid index) of the BDL */
1517 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1518
1519 /* program the BDL address */
1520 /* lower BDL address */
1521 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1522 /* upper BDL address */
1523 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1524
1525 /* enable the position buffer */
1526 if (chip->position_fix[0] != POS_FIX_LPIB ||
1527 chip->position_fix[1] != POS_FIX_LPIB) {
1528 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1529 azx_writel(chip, DPLBASE,
1530 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1531 }
1532
1533 /* set the interrupt enable bits in the descriptor control register */
1534 azx_sd_writel(azx_dev, SD_CTL,
1535 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1536
1537 return 0;
1538 }
1539
1540 /*
1541 * Probe the given codec address
1542 */
1543 static int probe_codec(struct azx *chip, int addr)
1544 {
1545 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1546 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1547 unsigned int res;
1548
1549 mutex_lock(&chip->bus->cmd_mutex);
1550 chip->probing = 1;
1551 azx_send_cmd(chip->bus, cmd);
1552 res = azx_get_response(chip->bus, addr);
1553 chip->probing = 0;
1554 mutex_unlock(&chip->bus->cmd_mutex);
1555 if (res == -1)
1556 return -EIO;
1557 snd_printdd(SFX "codec #%d probed OK\n", addr);
1558 return 0;
1559 }
1560
1561 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1562 struct hda_pcm *cpcm);
1563 static void azx_stop_chip(struct azx *chip);
1564
1565 static void azx_bus_reset(struct hda_bus *bus)
1566 {
1567 struct azx *chip = bus->private_data;
1568
1569 bus->in_reset = 1;
1570 azx_stop_chip(chip);
1571 azx_init_chip(chip, 1);
1572 #ifdef CONFIG_PM
1573 if (chip->initialized) {
1574 struct azx_pcm *p;
1575 list_for_each_entry(p, &chip->pcm_list, list)
1576 snd_pcm_suspend_all(p->pcm);
1577 snd_hda_suspend(chip->bus);
1578 snd_hda_resume(chip->bus);
1579 }
1580 #endif
1581 bus->in_reset = 0;
1582 }
1583
1584 /*
1585 * Codec initialization
1586 */
1587
1588 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1589 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
1590 [AZX_DRIVER_NVIDIA] = 8,
1591 [AZX_DRIVER_TERA] = 1,
1592 };
1593
1594 static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1595 {
1596 struct hda_bus_template bus_temp;
1597 int c, codecs, err;
1598 int max_slots;
1599
1600 memset(&bus_temp, 0, sizeof(bus_temp));
1601 bus_temp.private_data = chip;
1602 bus_temp.modelname = model;
1603 bus_temp.pci = chip->pci;
1604 bus_temp.ops.command = azx_send_cmd;
1605 bus_temp.ops.get_response = azx_get_response;
1606 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1607 bus_temp.ops.bus_reset = azx_bus_reset;
1608 #ifdef CONFIG_PM
1609 bus_temp.power_save = &power_save;
1610 bus_temp.ops.pm_notify = azx_power_notify;
1611 #endif
1612
1613 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1614 if (err < 0)
1615 return err;
1616
1617 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1618 snd_printd(SFX "Enable delay in RIRB handling\n");
1619 chip->bus->needs_damn_long_delay = 1;
1620 }
1621
1622 codecs = 0;
1623 max_slots = azx_max_codecs[chip->driver_type];
1624 if (!max_slots)
1625 max_slots = AZX_DEFAULT_CODECS;
1626
1627 /* First try to probe all given codec slots */
1628 for (c = 0; c < max_slots; c++) {
1629 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1630 if (probe_codec(chip, c) < 0) {
1631 /* Some BIOSen give you wrong codec addresses
1632 * that don't exist
1633 */
1634 snd_printk(KERN_WARNING SFX
1635 "Codec #%d probe error; "
1636 "disabling it...\n", c);
1637 chip->codec_mask &= ~(1 << c);
1638 /* More badly, accessing to a non-existing
1639 * codec often screws up the controller chip,
1640 * and disturbs the further communications.
1641 * Thus if an error occurs during probing,
1642 * better to reset the controller chip to
1643 * get back to the sanity state.
1644 */
1645 azx_stop_chip(chip);
1646 azx_init_chip(chip, 1);
1647 }
1648 }
1649 }
1650
1651 /* AMD chipsets often cause the communication stalls upon certain
1652 * sequence like the pin-detection. It seems that forcing the synced
1653 * access works around the stall. Grrr...
1654 */
1655 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1656 snd_printd(SFX "Enable sync_write for stable communication\n");
1657 chip->bus->sync_write = 1;
1658 chip->bus->allow_bus_reset = 1;
1659 }
1660
1661 /* Then create codec instances */
1662 for (c = 0; c < max_slots; c++) {
1663 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1664 struct hda_codec *codec;
1665 err = snd_hda_codec_new(chip->bus, c, &codec);
1666 if (err < 0)
1667 continue;
1668 codec->beep_mode = chip->beep_mode;
1669 codecs++;
1670 }
1671 }
1672 if (!codecs) {
1673 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1674 return -ENXIO;
1675 }
1676 return 0;
1677 }
1678
1679 /* configure each codec instance */
1680 static int __devinit azx_codec_configure(struct azx *chip)
1681 {
1682 struct hda_codec *codec;
1683 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1684 snd_hda_codec_configure(codec);
1685 }
1686 return 0;
1687 }
1688
1689
1690 /*
1691 * PCM support
1692 */
1693
1694 /* assign a stream for the PCM */
1695 static inline struct azx_dev *
1696 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1697 {
1698 int dev, i, nums;
1699 struct azx_dev *res = NULL;
1700 /* make a non-zero unique key for the substream */
1701 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1702 (substream->stream + 1);
1703
1704 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1705 dev = chip->playback_index_offset;
1706 nums = chip->playback_streams;
1707 } else {
1708 dev = chip->capture_index_offset;
1709 nums = chip->capture_streams;
1710 }
1711 for (i = 0; i < nums; i++, dev++)
1712 if (!chip->azx_dev[dev].opened) {
1713 res = &chip->azx_dev[dev];
1714 if (res->assigned_key == key)
1715 break;
1716 }
1717 if (res) {
1718 res->opened = 1;
1719 res->assigned_key = key;
1720 }
1721 return res;
1722 }
1723
1724 /* release the assigned stream */
1725 static inline void azx_release_device(struct azx_dev *azx_dev)
1726 {
1727 azx_dev->opened = 0;
1728 }
1729
1730 static struct snd_pcm_hardware azx_pcm_hw = {
1731 .info = (SNDRV_PCM_INFO_MMAP |
1732 SNDRV_PCM_INFO_INTERLEAVED |
1733 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1734 SNDRV_PCM_INFO_MMAP_VALID |
1735 /* No full-resume yet implemented */
1736 /* SNDRV_PCM_INFO_RESUME |*/
1737 SNDRV_PCM_INFO_PAUSE |
1738 SNDRV_PCM_INFO_SYNC_START |
1739 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1740 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1741 .rates = SNDRV_PCM_RATE_48000,
1742 .rate_min = 48000,
1743 .rate_max = 48000,
1744 .channels_min = 2,
1745 .channels_max = 2,
1746 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1747 .period_bytes_min = 128,
1748 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1749 .periods_min = 2,
1750 .periods_max = AZX_MAX_FRAG,
1751 .fifo_size = 0,
1752 };
1753
1754 static int azx_pcm_open(struct snd_pcm_substream *substream)
1755 {
1756 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1757 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1758 struct azx *chip = apcm->chip;
1759 struct azx_dev *azx_dev;
1760 struct snd_pcm_runtime *runtime = substream->runtime;
1761 unsigned long flags;
1762 int err;
1763 int buff_step;
1764
1765 mutex_lock(&chip->open_mutex);
1766 azx_dev = azx_assign_device(chip, substream);
1767 if (azx_dev == NULL) {
1768 mutex_unlock(&chip->open_mutex);
1769 return -EBUSY;
1770 }
1771 runtime->hw = azx_pcm_hw;
1772 runtime->hw.channels_min = hinfo->channels_min;
1773 runtime->hw.channels_max = hinfo->channels_max;
1774 runtime->hw.formats = hinfo->formats;
1775 runtime->hw.rates = hinfo->rates;
1776 snd_pcm_limit_hw_rates(runtime);
1777 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1778 if (chip->align_buffer_size)
1779 /* constrain buffer sizes to be multiple of 128
1780 bytes. This is more efficient in terms of memory
1781 access but isn't required by the HDA spec and
1782 prevents users from specifying exact period/buffer
1783 sizes. For example for 44.1kHz, a period size set
1784 to 20ms will be rounded to 19.59ms. */
1785 buff_step = 128;
1786 else
1787 /* Don't enforce steps on buffer sizes, still need to
1788 be multiple of 4 bytes (HDA spec). Tested on Intel
1789 HDA controllers, may not work on all devices where
1790 option needs to be disabled */
1791 buff_step = 4;
1792
1793 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1794 buff_step);
1795 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1796 buff_step);
1797 snd_hda_power_up_d3wait(apcm->codec);
1798 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1799 if (err < 0) {
1800 azx_release_device(azx_dev);
1801 snd_hda_power_down(apcm->codec);
1802 mutex_unlock(&chip->open_mutex);
1803 return err;
1804 }
1805 snd_pcm_limit_hw_rates(runtime);
1806 /* sanity check */
1807 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1808 snd_BUG_ON(!runtime->hw.channels_max) ||
1809 snd_BUG_ON(!runtime->hw.formats) ||
1810 snd_BUG_ON(!runtime->hw.rates)) {
1811 azx_release_device(azx_dev);
1812 hinfo->ops.close(hinfo, apcm->codec, substream);
1813 snd_hda_power_down(apcm->codec);
1814 mutex_unlock(&chip->open_mutex);
1815 return -EINVAL;
1816 }
1817 spin_lock_irqsave(&chip->reg_lock, flags);
1818 azx_dev->substream = substream;
1819 azx_dev->running = 0;
1820 spin_unlock_irqrestore(&chip->reg_lock, flags);
1821
1822 runtime->private_data = azx_dev;
1823 snd_pcm_set_sync(substream);
1824 mutex_unlock(&chip->open_mutex);
1825 return 0;
1826 }
1827
1828 static int azx_pcm_close(struct snd_pcm_substream *substream)
1829 {
1830 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1831 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1832 struct azx *chip = apcm->chip;
1833 struct azx_dev *azx_dev = get_azx_dev(substream);
1834 unsigned long flags;
1835
1836 mutex_lock(&chip->open_mutex);
1837 spin_lock_irqsave(&chip->reg_lock, flags);
1838 azx_dev->substream = NULL;
1839 azx_dev->running = 0;
1840 spin_unlock_irqrestore(&chip->reg_lock, flags);
1841 azx_release_device(azx_dev);
1842 hinfo->ops.close(hinfo, apcm->codec, substream);
1843 snd_hda_power_down(apcm->codec);
1844 mutex_unlock(&chip->open_mutex);
1845 return 0;
1846 }
1847
1848 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1849 struct snd_pcm_hw_params *hw_params)
1850 {
1851 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1852 struct azx *chip = apcm->chip;
1853 struct snd_pcm_runtime *runtime = substream->runtime;
1854 struct azx_dev *azx_dev = get_azx_dev(substream);
1855 int ret;
1856
1857 mark_runtime_wc(chip, azx_dev, runtime, false);
1858 azx_dev->bufsize = 0;
1859 azx_dev->period_bytes = 0;
1860 azx_dev->format_val = 0;
1861 ret = snd_pcm_lib_malloc_pages(substream,
1862 params_buffer_bytes(hw_params));
1863 if (ret < 0)
1864 return ret;
1865 mark_runtime_wc(chip, azx_dev, runtime, true);
1866 return ret;
1867 }
1868
1869 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1870 {
1871 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1872 struct azx_dev *azx_dev = get_azx_dev(substream);
1873 struct azx *chip = apcm->chip;
1874 struct snd_pcm_runtime *runtime = substream->runtime;
1875 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1876
1877 /* reset BDL address */
1878 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1879 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1880 azx_sd_writel(azx_dev, SD_CTL, 0);
1881 azx_dev->bufsize = 0;
1882 azx_dev->period_bytes = 0;
1883 azx_dev->format_val = 0;
1884
1885 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1886
1887 mark_runtime_wc(chip, azx_dev, runtime, false);
1888 return snd_pcm_lib_free_pages(substream);
1889 }
1890
1891 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1892 {
1893 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1894 struct azx *chip = apcm->chip;
1895 struct azx_dev *azx_dev = get_azx_dev(substream);
1896 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1897 struct snd_pcm_runtime *runtime = substream->runtime;
1898 unsigned int bufsize, period_bytes, format_val, stream_tag;
1899 int err;
1900 struct hda_spdif_out *spdif =
1901 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1902 unsigned short ctls = spdif ? spdif->ctls : 0;
1903
1904 azx_stream_reset(chip, azx_dev);
1905 format_val = snd_hda_calc_stream_format(runtime->rate,
1906 runtime->channels,
1907 runtime->format,
1908 hinfo->maxbps,
1909 ctls);
1910 if (!format_val) {
1911 snd_printk(KERN_ERR SFX
1912 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1913 runtime->rate, runtime->channels, runtime->format);
1914 return -EINVAL;
1915 }
1916
1917 bufsize = snd_pcm_lib_buffer_bytes(substream);
1918 period_bytes = snd_pcm_lib_period_bytes(substream);
1919
1920 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1921 bufsize, format_val);
1922
1923 if (bufsize != azx_dev->bufsize ||
1924 period_bytes != azx_dev->period_bytes ||
1925 format_val != azx_dev->format_val ||
1926 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
1927 azx_dev->bufsize = bufsize;
1928 azx_dev->period_bytes = period_bytes;
1929 azx_dev->format_val = format_val;
1930 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
1931 err = azx_setup_periods(chip, substream, azx_dev);
1932 if (err < 0)
1933 return err;
1934 }
1935
1936 /* wallclk has 24Mhz clock source */
1937 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1938 runtime->rate) * 1000);
1939 azx_setup_controller(chip, azx_dev);
1940 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1941 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1942 else
1943 azx_dev->fifo_size = 0;
1944
1945 stream_tag = azx_dev->stream_tag;
1946 /* CA-IBG chips need the playback stream starting from 1 */
1947 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1948 stream_tag > chip->capture_streams)
1949 stream_tag -= chip->capture_streams;
1950 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1951 azx_dev->format_val, substream);
1952 }
1953
1954 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1955 {
1956 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1957 struct azx *chip = apcm->chip;
1958 struct azx_dev *azx_dev;
1959 struct snd_pcm_substream *s;
1960 int rstart = 0, start, nsync = 0, sbits = 0;
1961 int nwait, timeout;
1962
1963 switch (cmd) {
1964 case SNDRV_PCM_TRIGGER_START:
1965 rstart = 1;
1966 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1967 case SNDRV_PCM_TRIGGER_RESUME:
1968 start = 1;
1969 break;
1970 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1971 case SNDRV_PCM_TRIGGER_SUSPEND:
1972 case SNDRV_PCM_TRIGGER_STOP:
1973 start = 0;
1974 break;
1975 default:
1976 return -EINVAL;
1977 }
1978
1979 snd_pcm_group_for_each_entry(s, substream) {
1980 if (s->pcm->card != substream->pcm->card)
1981 continue;
1982 azx_dev = get_azx_dev(s);
1983 sbits |= 1 << azx_dev->index;
1984 nsync++;
1985 snd_pcm_trigger_done(s, substream);
1986 }
1987
1988 spin_lock(&chip->reg_lock);
1989 if (nsync > 1) {
1990 /* first, set SYNC bits of corresponding streams */
1991 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1992 azx_writel(chip, OLD_SSYNC,
1993 azx_readl(chip, OLD_SSYNC) | sbits);
1994 else
1995 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1996 }
1997 snd_pcm_group_for_each_entry(s, substream) {
1998 if (s->pcm->card != substream->pcm->card)
1999 continue;
2000 azx_dev = get_azx_dev(s);
2001 if (start) {
2002 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2003 if (!rstart)
2004 azx_dev->start_wallclk -=
2005 azx_dev->period_wallclk;
2006 azx_stream_start(chip, azx_dev);
2007 } else {
2008 azx_stream_stop(chip, azx_dev);
2009 }
2010 azx_dev->running = start;
2011 }
2012 spin_unlock(&chip->reg_lock);
2013 if (start) {
2014 if (nsync == 1)
2015 return 0;
2016 /* wait until all FIFOs get ready */
2017 for (timeout = 5000; timeout; timeout--) {
2018 nwait = 0;
2019 snd_pcm_group_for_each_entry(s, substream) {
2020 if (s->pcm->card != substream->pcm->card)
2021 continue;
2022 azx_dev = get_azx_dev(s);
2023 if (!(azx_sd_readb(azx_dev, SD_STS) &
2024 SD_STS_FIFO_READY))
2025 nwait++;
2026 }
2027 if (!nwait)
2028 break;
2029 cpu_relax();
2030 }
2031 } else {
2032 /* wait until all RUN bits are cleared */
2033 for (timeout = 5000; timeout; timeout--) {
2034 nwait = 0;
2035 snd_pcm_group_for_each_entry(s, substream) {
2036 if (s->pcm->card != substream->pcm->card)
2037 continue;
2038 azx_dev = get_azx_dev(s);
2039 if (azx_sd_readb(azx_dev, SD_CTL) &
2040 SD_CTL_DMA_START)
2041 nwait++;
2042 }
2043 if (!nwait)
2044 break;
2045 cpu_relax();
2046 }
2047 }
2048 if (nsync > 1) {
2049 spin_lock(&chip->reg_lock);
2050 /* reset SYNC bits */
2051 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2052 azx_writel(chip, OLD_SSYNC,
2053 azx_readl(chip, OLD_SSYNC) & ~sbits);
2054 else
2055 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2056 spin_unlock(&chip->reg_lock);
2057 }
2058 return 0;
2059 }
2060
2061 /* get the current DMA position with correction on VIA chips */
2062 static unsigned int azx_via_get_position(struct azx *chip,
2063 struct azx_dev *azx_dev)
2064 {
2065 unsigned int link_pos, mini_pos, bound_pos;
2066 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2067 unsigned int fifo_size;
2068
2069 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2070 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2071 /* Playback, no problem using link position */
2072 return link_pos;
2073 }
2074
2075 /* Capture */
2076 /* For new chipset,
2077 * use mod to get the DMA position just like old chipset
2078 */
2079 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2080 mod_dma_pos %= azx_dev->period_bytes;
2081
2082 /* azx_dev->fifo_size can't get FIFO size of in stream.
2083 * Get from base address + offset.
2084 */
2085 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2086
2087 if (azx_dev->insufficient) {
2088 /* Link position never gather than FIFO size */
2089 if (link_pos <= fifo_size)
2090 return 0;
2091
2092 azx_dev->insufficient = 0;
2093 }
2094
2095 if (link_pos <= fifo_size)
2096 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2097 else
2098 mini_pos = link_pos - fifo_size;
2099
2100 /* Find nearest previous boudary */
2101 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2102 mod_link_pos = link_pos % azx_dev->period_bytes;
2103 if (mod_link_pos >= fifo_size)
2104 bound_pos = link_pos - mod_link_pos;
2105 else if (mod_dma_pos >= mod_mini_pos)
2106 bound_pos = mini_pos - mod_mini_pos;
2107 else {
2108 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2109 if (bound_pos >= azx_dev->bufsize)
2110 bound_pos = 0;
2111 }
2112
2113 /* Calculate real DMA position we want */
2114 return bound_pos + mod_dma_pos;
2115 }
2116
2117 static unsigned int azx_get_position(struct azx *chip,
2118 struct azx_dev *azx_dev,
2119 bool with_check)
2120 {
2121 unsigned int pos;
2122 int stream = azx_dev->substream->stream;
2123
2124 switch (chip->position_fix[stream]) {
2125 case POS_FIX_LPIB:
2126 /* read LPIB */
2127 pos = azx_sd_readl(azx_dev, SD_LPIB);
2128 break;
2129 case POS_FIX_VIACOMBO:
2130 pos = azx_via_get_position(chip, azx_dev);
2131 break;
2132 default:
2133 /* use the position buffer */
2134 pos = le32_to_cpu(*azx_dev->posbuf);
2135 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2136 if (!pos || pos == (u32)-1) {
2137 printk(KERN_WARNING
2138 "hda-intel: Invalid position buffer, "
2139 "using LPIB read method instead.\n");
2140 chip->position_fix[stream] = POS_FIX_LPIB;
2141 pos = azx_sd_readl(azx_dev, SD_LPIB);
2142 } else
2143 chip->position_fix[stream] = POS_FIX_POSBUF;
2144 }
2145 break;
2146 }
2147
2148 if (pos >= azx_dev->bufsize)
2149 pos = 0;
2150 return pos;
2151 }
2152
2153 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2154 {
2155 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2156 struct azx *chip = apcm->chip;
2157 struct azx_dev *azx_dev = get_azx_dev(substream);
2158 return bytes_to_frames(substream->runtime,
2159 azx_get_position(chip, azx_dev, false));
2160 }
2161
2162 /*
2163 * Check whether the current DMA position is acceptable for updating
2164 * periods. Returns non-zero if it's OK.
2165 *
2166 * Many HD-audio controllers appear pretty inaccurate about
2167 * the update-IRQ timing. The IRQ is issued before actually the
2168 * data is processed. So, we need to process it afterwords in a
2169 * workqueue.
2170 */
2171 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2172 {
2173 u32 wallclk;
2174 unsigned int pos;
2175 int stream;
2176
2177 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2178 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2179 return -1; /* bogus (too early) interrupt */
2180
2181 stream = azx_dev->substream->stream;
2182 pos = azx_get_position(chip, azx_dev, true);
2183
2184 if (WARN_ONCE(!azx_dev->period_bytes,
2185 "hda-intel: zero azx_dev->period_bytes"))
2186 return -1; /* this shouldn't happen! */
2187 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2188 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2189 /* NG - it's below the first next period boundary */
2190 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2191 azx_dev->start_wallclk += wallclk;
2192 return 1; /* OK, it's fine */
2193 }
2194
2195 /*
2196 * The work for pending PCM period updates.
2197 */
2198 static void azx_irq_pending_work(struct work_struct *work)
2199 {
2200 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2201 int i, pending, ok;
2202
2203 if (!chip->irq_pending_warned) {
2204 printk(KERN_WARNING
2205 "hda-intel: IRQ timing workaround is activated "
2206 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2207 chip->card->number);
2208 chip->irq_pending_warned = 1;
2209 }
2210
2211 for (;;) {
2212 pending = 0;
2213 spin_lock_irq(&chip->reg_lock);
2214 for (i = 0; i < chip->num_streams; i++) {
2215 struct azx_dev *azx_dev = &chip->azx_dev[i];
2216 if (!azx_dev->irq_pending ||
2217 !azx_dev->substream ||
2218 !azx_dev->running)
2219 continue;
2220 ok = azx_position_ok(chip, azx_dev);
2221 if (ok > 0) {
2222 azx_dev->irq_pending = 0;
2223 spin_unlock(&chip->reg_lock);
2224 snd_pcm_period_elapsed(azx_dev->substream);
2225 spin_lock(&chip->reg_lock);
2226 } else if (ok < 0) {
2227 pending = 0; /* too early */
2228 } else
2229 pending++;
2230 }
2231 spin_unlock_irq(&chip->reg_lock);
2232 if (!pending)
2233 return;
2234 msleep(1);
2235 }
2236 }
2237
2238 /* clear irq_pending flags and assure no on-going workq */
2239 static void azx_clear_irq_pending(struct azx *chip)
2240 {
2241 int i;
2242
2243 spin_lock_irq(&chip->reg_lock);
2244 for (i = 0; i < chip->num_streams; i++)
2245 chip->azx_dev[i].irq_pending = 0;
2246 spin_unlock_irq(&chip->reg_lock);
2247 }
2248
2249 #ifdef CONFIG_X86
2250 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2251 struct vm_area_struct *area)
2252 {
2253 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2254 struct azx *chip = apcm->chip;
2255 if (!azx_snoop(chip))
2256 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2257 return snd_pcm_lib_default_mmap(substream, area);
2258 }
2259 #else
2260 #define azx_pcm_mmap NULL
2261 #endif
2262
2263 static struct snd_pcm_ops azx_pcm_ops = {
2264 .open = azx_pcm_open,
2265 .close = azx_pcm_close,
2266 .ioctl = snd_pcm_lib_ioctl,
2267 .hw_params = azx_pcm_hw_params,
2268 .hw_free = azx_pcm_hw_free,
2269 .prepare = azx_pcm_prepare,
2270 .trigger = azx_pcm_trigger,
2271 .pointer = azx_pcm_pointer,
2272 .mmap = azx_pcm_mmap,
2273 .page = snd_pcm_sgbuf_ops_page,
2274 };
2275
2276 static void azx_pcm_free(struct snd_pcm *pcm)
2277 {
2278 struct azx_pcm *apcm = pcm->private_data;
2279 if (apcm) {
2280 list_del(&apcm->list);
2281 kfree(apcm);
2282 }
2283 }
2284
2285 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2286
2287 static int
2288 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2289 struct hda_pcm *cpcm)
2290 {
2291 struct azx *chip = bus->private_data;
2292 struct snd_pcm *pcm;
2293 struct azx_pcm *apcm;
2294 int pcm_dev = cpcm->device;
2295 unsigned int size;
2296 int s, err;
2297
2298 list_for_each_entry(apcm, &chip->pcm_list, list) {
2299 if (apcm->pcm->device == pcm_dev) {
2300 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2301 return -EBUSY;
2302 }
2303 }
2304 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2305 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2306 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2307 &pcm);
2308 if (err < 0)
2309 return err;
2310 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2311 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2312 if (apcm == NULL)
2313 return -ENOMEM;
2314 apcm->chip = chip;
2315 apcm->pcm = pcm;
2316 apcm->codec = codec;
2317 pcm->private_data = apcm;
2318 pcm->private_free = azx_pcm_free;
2319 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2320 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2321 list_add_tail(&apcm->list, &chip->pcm_list);
2322 cpcm->pcm = pcm;
2323 for (s = 0; s < 2; s++) {
2324 apcm->hinfo[s] = &cpcm->stream[s];
2325 if (cpcm->stream[s].substreams)
2326 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2327 }
2328 /* buffer pre-allocation */
2329 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2330 if (size > MAX_PREALLOC_SIZE)
2331 size = MAX_PREALLOC_SIZE;
2332 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2333 snd_dma_pci_data(chip->pci),
2334 size, MAX_PREALLOC_SIZE);
2335 return 0;
2336 }
2337
2338 /*
2339 * mixer creation - all stuff is implemented in hda module
2340 */
2341 static int __devinit azx_mixer_create(struct azx *chip)
2342 {
2343 return snd_hda_build_controls(chip->bus);
2344 }
2345
2346
2347 /*
2348 * initialize SD streams
2349 */
2350 static int __devinit azx_init_stream(struct azx *chip)
2351 {
2352 int i;
2353
2354 /* initialize each stream (aka device)
2355 * assign the starting bdl address to each stream (device)
2356 * and initialize
2357 */
2358 for (i = 0; i < chip->num_streams; i++) {
2359 struct azx_dev *azx_dev = &chip->azx_dev[i];
2360 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2361 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2362 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2363 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2364 azx_dev->sd_int_sta_mask = 1 << i;
2365 /* stream tag: must be non-zero and unique */
2366 azx_dev->index = i;
2367 azx_dev->stream_tag = i + 1;
2368 }
2369
2370 return 0;
2371 }
2372
2373 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2374 {
2375 if (request_irq(chip->pci->irq, azx_interrupt,
2376 chip->msi ? 0 : IRQF_SHARED,
2377 KBUILD_MODNAME, chip)) {
2378 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2379 "disabling device\n", chip->pci->irq);
2380 if (do_disconnect)
2381 snd_card_disconnect(chip->card);
2382 return -1;
2383 }
2384 chip->irq = chip->pci->irq;
2385 pci_intx(chip->pci, !chip->msi);
2386 return 0;
2387 }
2388
2389
2390 static void azx_stop_chip(struct azx *chip)
2391 {
2392 if (!chip->initialized)
2393 return;
2394
2395 /* disable interrupts */
2396 azx_int_disable(chip);
2397 azx_int_clear(chip);
2398
2399 /* disable CORB/RIRB */
2400 azx_free_cmd_io(chip);
2401
2402 /* disable position buffer */
2403 azx_writel(chip, DPLBASE, 0);
2404 azx_writel(chip, DPUBASE, 0);
2405
2406 chip->initialized = 0;
2407 }
2408
2409 #ifdef CONFIG_PM
2410 /* power-up/down the controller */
2411 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2412 {
2413 struct azx *chip = bus->private_data;
2414
2415 if (power_up)
2416 pm_runtime_get_sync(&chip->pci->dev);
2417 else
2418 pm_runtime_put_sync(&chip->pci->dev);
2419 }
2420
2421 static DEFINE_MUTEX(card_list_lock);
2422 static LIST_HEAD(card_list);
2423
2424 static void azx_add_card_list(struct azx *chip)
2425 {
2426 mutex_lock(&card_list_lock);
2427 list_add(&chip->list, &card_list);
2428 mutex_unlock(&card_list_lock);
2429 }
2430
2431 static void azx_del_card_list(struct azx *chip)
2432 {
2433 mutex_lock(&card_list_lock);
2434 list_del_init(&chip->list);
2435 mutex_unlock(&card_list_lock);
2436 }
2437
2438 /* trigger power-save check at writing parameter */
2439 static int param_set_xint(const char *val, const struct kernel_param *kp)
2440 {
2441 struct azx *chip;
2442 struct hda_codec *c;
2443 int prev = power_save;
2444 int ret = param_set_int(val, kp);
2445
2446 if (ret || prev == power_save)
2447 return ret;
2448
2449 mutex_lock(&card_list_lock);
2450 list_for_each_entry(chip, &card_list, list) {
2451 if (!chip->bus || chip->disabled)
2452 continue;
2453 list_for_each_entry(c, &chip->bus->codec_list, list)
2454 snd_hda_power_sync(c);
2455 }
2456 mutex_unlock(&card_list_lock);
2457 return 0;
2458 }
2459 #else
2460 #define azx_add_card_list(chip) /* NOP */
2461 #define azx_del_card_list(chip) /* NOP */
2462 #endif /* CONFIG_PM */
2463
2464 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2465 /*
2466 * power management
2467 */
2468 static int azx_suspend(struct device *dev)
2469 {
2470 struct pci_dev *pci = to_pci_dev(dev);
2471 struct snd_card *card = dev_get_drvdata(dev);
2472 struct azx *chip = card->private_data;
2473 struct azx_pcm *p;
2474
2475 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2476 azx_clear_irq_pending(chip);
2477 list_for_each_entry(p, &chip->pcm_list, list)
2478 snd_pcm_suspend_all(p->pcm);
2479 if (chip->initialized)
2480 snd_hda_suspend(chip->bus);
2481 azx_stop_chip(chip);
2482 if (chip->irq >= 0) {
2483 free_irq(chip->irq, chip);
2484 chip->irq = -1;
2485 }
2486 if (chip->msi)
2487 pci_disable_msi(chip->pci);
2488 pci_disable_device(pci);
2489 pci_save_state(pci);
2490 pci_set_power_state(pci, PCI_D3hot);
2491 return 0;
2492 }
2493
2494 static int azx_resume(struct device *dev)
2495 {
2496 struct pci_dev *pci = to_pci_dev(dev);
2497 struct snd_card *card = dev_get_drvdata(dev);
2498 struct azx *chip = card->private_data;
2499
2500 pci_set_power_state(pci, PCI_D0);
2501 pci_restore_state(pci);
2502 if (pci_enable_device(pci) < 0) {
2503 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2504 "disabling device\n");
2505 snd_card_disconnect(card);
2506 return -EIO;
2507 }
2508 pci_set_master(pci);
2509 if (chip->msi)
2510 if (pci_enable_msi(pci) < 0)
2511 chip->msi = 0;
2512 if (azx_acquire_irq(chip, 1) < 0)
2513 return -EIO;
2514 azx_init_pci(chip);
2515
2516 azx_init_chip(chip, 1);
2517
2518 snd_hda_resume(chip->bus);
2519 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2520 return 0;
2521 }
2522 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2523
2524 #ifdef CONFIG_PM_RUNTIME
2525 static int azx_runtime_suspend(struct device *dev)
2526 {
2527 struct snd_card *card = dev_get_drvdata(dev);
2528 struct azx *chip = card->private_data;
2529
2530 if (!power_save_controller)
2531 return -EAGAIN;
2532
2533 azx_stop_chip(chip);
2534 azx_clear_irq_pending(chip);
2535 return 0;
2536 }
2537
2538 static int azx_runtime_resume(struct device *dev)
2539 {
2540 struct snd_card *card = dev_get_drvdata(dev);
2541 struct azx *chip = card->private_data;
2542
2543 azx_init_pci(chip);
2544 azx_init_chip(chip, 1);
2545 return 0;
2546 }
2547 #endif /* CONFIG_PM_RUNTIME */
2548
2549 #ifdef CONFIG_PM
2550 static const struct dev_pm_ops azx_pm = {
2551 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2552 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2553 };
2554
2555 #define AZX_PM_OPS &azx_pm
2556 #else
2557 #define AZX_PM_OPS NULL
2558 #endif /* CONFIG_PM */
2559
2560
2561 /*
2562 * reboot notifier for hang-up problem at power-down
2563 */
2564 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2565 {
2566 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2567 snd_hda_bus_reboot_notify(chip->bus);
2568 azx_stop_chip(chip);
2569 return NOTIFY_OK;
2570 }
2571
2572 static void azx_notifier_register(struct azx *chip)
2573 {
2574 chip->reboot_notifier.notifier_call = azx_halt;
2575 register_reboot_notifier(&chip->reboot_notifier);
2576 }
2577
2578 static void azx_notifier_unregister(struct azx *chip)
2579 {
2580 if (chip->reboot_notifier.notifier_call)
2581 unregister_reboot_notifier(&chip->reboot_notifier);
2582 }
2583
2584 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2585 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2586
2587 #ifdef SUPPORT_VGA_SWITCHEROO
2588 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2589
2590 static void azx_vs_set_state(struct pci_dev *pci,
2591 enum vga_switcheroo_state state)
2592 {
2593 struct snd_card *card = pci_get_drvdata(pci);
2594 struct azx *chip = card->private_data;
2595 bool disabled;
2596
2597 if (chip->init_failed)
2598 return;
2599
2600 disabled = (state == VGA_SWITCHEROO_OFF);
2601 if (chip->disabled == disabled)
2602 return;
2603
2604 if (!chip->bus) {
2605 chip->disabled = disabled;
2606 if (!disabled) {
2607 snd_printk(KERN_INFO SFX
2608 "%s: Start delayed initialization\n",
2609 pci_name(chip->pci));
2610 if (azx_first_init(chip) < 0 ||
2611 azx_probe_continue(chip) < 0) {
2612 snd_printk(KERN_ERR SFX
2613 "%s: initialization error\n",
2614 pci_name(chip->pci));
2615 chip->init_failed = true;
2616 }
2617 }
2618 } else {
2619 snd_printk(KERN_INFO SFX
2620 "%s %s via VGA-switcheroo\n",
2621 disabled ? "Disabling" : "Enabling",
2622 pci_name(chip->pci));
2623 if (disabled) {
2624 azx_suspend(&pci->dev);
2625 chip->disabled = true;
2626 snd_hda_lock_devices(chip->bus);
2627 } else {
2628 snd_hda_unlock_devices(chip->bus);
2629 chip->disabled = false;
2630 azx_resume(&pci->dev);
2631 }
2632 }
2633 }
2634
2635 static bool azx_vs_can_switch(struct pci_dev *pci)
2636 {
2637 struct snd_card *card = pci_get_drvdata(pci);
2638 struct azx *chip = card->private_data;
2639
2640 if (chip->init_failed)
2641 return false;
2642 if (chip->disabled || !chip->bus)
2643 return true;
2644 if (snd_hda_lock_devices(chip->bus))
2645 return false;
2646 snd_hda_unlock_devices(chip->bus);
2647 return true;
2648 }
2649
2650 static void __devinit init_vga_switcheroo(struct azx *chip)
2651 {
2652 struct pci_dev *p = get_bound_vga(chip->pci);
2653 if (p) {
2654 snd_printk(KERN_INFO SFX
2655 "%s: Handle VGA-switcheroo audio client\n",
2656 pci_name(chip->pci));
2657 chip->use_vga_switcheroo = 1;
2658 pci_dev_put(p);
2659 }
2660 }
2661
2662 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2663 .set_gpu_state = azx_vs_set_state,
2664 .can_switch = azx_vs_can_switch,
2665 };
2666
2667 static int __devinit register_vga_switcheroo(struct azx *chip)
2668 {
2669 if (!chip->use_vga_switcheroo)
2670 return 0;
2671 /* FIXME: currently only handling DIS controller
2672 * is there any machine with two switchable HDMI audio controllers?
2673 */
2674 return vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2675 VGA_SWITCHEROO_DIS,
2676 chip->bus != NULL);
2677 }
2678 #else
2679 #define init_vga_switcheroo(chip) /* NOP */
2680 #define register_vga_switcheroo(chip) 0
2681 #define check_hdmi_disabled(pci) false
2682 #endif /* SUPPORT_VGA_SWITCHER */
2683
2684 /*
2685 * destructor
2686 */
2687 static int azx_free(struct azx *chip)
2688 {
2689 int i;
2690
2691 azx_del_card_list(chip);
2692
2693 azx_notifier_unregister(chip);
2694
2695 if (use_vga_switcheroo(chip)) {
2696 if (chip->disabled && chip->bus)
2697 snd_hda_unlock_devices(chip->bus);
2698 vga_switcheroo_unregister_client(chip->pci);
2699 }
2700
2701 if (chip->initialized) {
2702 azx_clear_irq_pending(chip);
2703 for (i = 0; i < chip->num_streams; i++)
2704 azx_stream_stop(chip, &chip->azx_dev[i]);
2705 azx_stop_chip(chip);
2706 }
2707
2708 if (chip->irq >= 0)
2709 free_irq(chip->irq, (void*)chip);
2710 if (chip->msi)
2711 pci_disable_msi(chip->pci);
2712 if (chip->remap_addr)
2713 iounmap(chip->remap_addr);
2714
2715 if (chip->azx_dev) {
2716 for (i = 0; i < chip->num_streams; i++)
2717 if (chip->azx_dev[i].bdl.area) {
2718 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2719 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2720 }
2721 }
2722 if (chip->rb.area) {
2723 mark_pages_wc(chip, &chip->rb, false);
2724 snd_dma_free_pages(&chip->rb);
2725 }
2726 if (chip->posbuf.area) {
2727 mark_pages_wc(chip, &chip->posbuf, false);
2728 snd_dma_free_pages(&chip->posbuf);
2729 }
2730 if (chip->region_requested)
2731 pci_release_regions(chip->pci);
2732 pci_disable_device(chip->pci);
2733 kfree(chip->azx_dev);
2734 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2735 if (chip->fw)
2736 release_firmware(chip->fw);
2737 #endif
2738 kfree(chip);
2739
2740 return 0;
2741 }
2742
2743 static int azx_dev_free(struct snd_device *device)
2744 {
2745 return azx_free(device->device_data);
2746 }
2747
2748 #ifdef SUPPORT_VGA_SWITCHEROO
2749 /*
2750 * Check of disabled HDMI controller by vga-switcheroo
2751 */
2752 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2753 {
2754 struct pci_dev *p;
2755
2756 /* check only discrete GPU */
2757 switch (pci->vendor) {
2758 case PCI_VENDOR_ID_ATI:
2759 case PCI_VENDOR_ID_AMD:
2760 case PCI_VENDOR_ID_NVIDIA:
2761 if (pci->devfn == 1) {
2762 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2763 pci->bus->number, 0);
2764 if (p) {
2765 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2766 return p;
2767 pci_dev_put(p);
2768 }
2769 }
2770 break;
2771 }
2772 return NULL;
2773 }
2774
2775 static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2776 {
2777 bool vga_inactive = false;
2778 struct pci_dev *p = get_bound_vga(pci);
2779
2780 if (p) {
2781 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2782 vga_inactive = true;
2783 pci_dev_put(p);
2784 }
2785 return vga_inactive;
2786 }
2787 #endif /* SUPPORT_VGA_SWITCHEROO */
2788
2789 /*
2790 * white/black-listing for position_fix
2791 */
2792 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2793 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2794 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2795 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2796 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2797 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2798 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2799 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2800 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2801 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2802 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2803 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2804 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2805 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2806 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2807 {}
2808 };
2809
2810 static int __devinit check_position_fix(struct azx *chip, int fix)
2811 {
2812 const struct snd_pci_quirk *q;
2813
2814 switch (fix) {
2815 case POS_FIX_LPIB:
2816 case POS_FIX_POSBUF:
2817 case POS_FIX_VIACOMBO:
2818 case POS_FIX_COMBO:
2819 return fix;
2820 }
2821
2822 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2823 if (q) {
2824 printk(KERN_INFO
2825 "hda_intel: position_fix set to %d "
2826 "for device %04x:%04x\n",
2827 q->value, q->subvendor, q->subdevice);
2828 return q->value;
2829 }
2830
2831 /* Check VIA/ATI HD Audio Controller exist */
2832 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2833 snd_printd(SFX "Using VIACOMBO position fix\n");
2834 return POS_FIX_VIACOMBO;
2835 }
2836 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2837 snd_printd(SFX "Using LPIB position fix\n");
2838 return POS_FIX_LPIB;
2839 }
2840 if (chip->driver_caps & AZX_DCAPS_POSFIX_COMBO) {
2841 snd_printd(SFX "Using COMBO position fix\n");
2842 return POS_FIX_COMBO;
2843 }
2844 return POS_FIX_AUTO;
2845 }
2846
2847 /*
2848 * black-lists for probe_mask
2849 */
2850 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2851 /* Thinkpad often breaks the controller communication when accessing
2852 * to the non-working (or non-existing) modem codec slot.
2853 */
2854 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2855 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2856 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2857 /* broken BIOS */
2858 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2859 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2860 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2861 /* forced codec slots */
2862 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2863 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2864 /* WinFast VP200 H (Teradici) user reported broken communication */
2865 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
2866 {}
2867 };
2868
2869 #define AZX_FORCE_CODEC_MASK 0x100
2870
2871 static void __devinit check_probe_mask(struct azx *chip, int dev)
2872 {
2873 const struct snd_pci_quirk *q;
2874
2875 chip->codec_probe_mask = probe_mask[dev];
2876 if (chip->codec_probe_mask == -1) {
2877 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2878 if (q) {
2879 printk(KERN_INFO
2880 "hda_intel: probe_mask set to 0x%x "
2881 "for device %04x:%04x\n",
2882 q->value, q->subvendor, q->subdevice);
2883 chip->codec_probe_mask = q->value;
2884 }
2885 }
2886
2887 /* check forced option */
2888 if (chip->codec_probe_mask != -1 &&
2889 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2890 chip->codec_mask = chip->codec_probe_mask & 0xff;
2891 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2892 chip->codec_mask);
2893 }
2894 }
2895
2896 /*
2897 * white/black-list for enable_msi
2898 */
2899 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2900 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2901 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2902 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2903 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2904 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2905 {}
2906 };
2907
2908 static void __devinit check_msi(struct azx *chip)
2909 {
2910 const struct snd_pci_quirk *q;
2911
2912 if (enable_msi >= 0) {
2913 chip->msi = !!enable_msi;
2914 return;
2915 }
2916 chip->msi = 1; /* enable MSI as default */
2917 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2918 if (q) {
2919 printk(KERN_INFO
2920 "hda_intel: msi for device %04x:%04x set to %d\n",
2921 q->subvendor, q->subdevice, q->value);
2922 chip->msi = q->value;
2923 return;
2924 }
2925
2926 /* NVidia chipsets seem to cause troubles with MSI */
2927 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2928 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2929 chip->msi = 0;
2930 }
2931 }
2932
2933 /* check the snoop mode availability */
2934 static void __devinit azx_check_snoop_available(struct azx *chip)
2935 {
2936 bool snoop = chip->snoop;
2937
2938 switch (chip->driver_type) {
2939 case AZX_DRIVER_VIA:
2940 /* force to non-snoop mode for a new VIA controller
2941 * when BIOS is set
2942 */
2943 if (snoop) {
2944 u8 val;
2945 pci_read_config_byte(chip->pci, 0x42, &val);
2946 if (!(val & 0x80) && chip->pci->revision == 0x30)
2947 snoop = false;
2948 }
2949 break;
2950 case AZX_DRIVER_ATIHDMI_NS:
2951 /* new ATI HDMI requires non-snoop */
2952 snoop = false;
2953 break;
2954 }
2955
2956 if (snoop != chip->snoop) {
2957 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2958 snoop ? "snoop" : "non-snoop");
2959 chip->snoop = snoop;
2960 }
2961 }
2962
2963 /*
2964 * constructor
2965 */
2966 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2967 int dev, unsigned int driver_caps,
2968 struct azx **rchip)
2969 {
2970 static struct snd_device_ops ops = {
2971 .dev_free = azx_dev_free,
2972 };
2973 struct azx *chip;
2974 int err;
2975
2976 *rchip = NULL;
2977
2978 err = pci_enable_device(pci);
2979 if (err < 0)
2980 return err;
2981
2982 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2983 if (!chip) {
2984 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2985 pci_disable_device(pci);
2986 return -ENOMEM;
2987 }
2988
2989 spin_lock_init(&chip->reg_lock);
2990 mutex_init(&chip->open_mutex);
2991 chip->card = card;
2992 chip->pci = pci;
2993 chip->irq = -1;
2994 chip->driver_caps = driver_caps;
2995 chip->driver_type = driver_caps & 0xff;
2996 check_msi(chip);
2997 chip->dev_index = dev;
2998 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2999 INIT_LIST_HEAD(&chip->pcm_list);
3000 INIT_LIST_HEAD(&chip->list);
3001 init_vga_switcheroo(chip);
3002
3003 chip->position_fix[0] = chip->position_fix[1] =
3004 check_position_fix(chip, position_fix[dev]);
3005 /* combo mode uses LPIB for playback */
3006 if (chip->position_fix[0] == POS_FIX_COMBO) {
3007 chip->position_fix[0] = POS_FIX_LPIB;
3008 chip->position_fix[1] = POS_FIX_AUTO;
3009 }
3010
3011 check_probe_mask(chip, dev);
3012
3013 chip->single_cmd = single_cmd;
3014 chip->snoop = hda_snoop;
3015 azx_check_snoop_available(chip);
3016
3017 if (bdl_pos_adj[dev] < 0) {
3018 switch (chip->driver_type) {
3019 case AZX_DRIVER_ICH:
3020 case AZX_DRIVER_PCH:
3021 bdl_pos_adj[dev] = 1;
3022 break;
3023 default:
3024 bdl_pos_adj[dev] = 32;
3025 break;
3026 }
3027 }
3028
3029 if (check_hdmi_disabled(pci)) {
3030 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
3031 pci_name(pci));
3032 if (use_vga_switcheroo(chip)) {
3033 snd_printk(KERN_INFO SFX "Delaying initialization\n");
3034 chip->disabled = true;
3035 goto ok;
3036 }
3037 kfree(chip);
3038 pci_disable_device(pci);
3039 return -ENXIO;
3040 }
3041
3042 err = azx_first_init(chip);
3043 if (err < 0) {
3044 azx_free(chip);
3045 return err;
3046 }
3047
3048 ok:
3049 err = register_vga_switcheroo(chip);
3050 if (err < 0) {
3051 snd_printk(KERN_ERR SFX
3052 "Error registering VGA-switcheroo client\n");
3053 azx_free(chip);
3054 return err;
3055 }
3056
3057 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3058 if (err < 0) {
3059 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3060 azx_free(chip);
3061 return err;
3062 }
3063
3064 *rchip = chip;
3065 return 0;
3066 }
3067
3068 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3069 {
3070 int dev = chip->dev_index;
3071 struct pci_dev *pci = chip->pci;
3072 struct snd_card *card = chip->card;
3073 int i, err;
3074 unsigned short gcap;
3075
3076 #if BITS_PER_LONG != 64
3077 /* Fix up base address on ULI M5461 */
3078 if (chip->driver_type == AZX_DRIVER_ULI) {
3079 u16 tmp3;
3080 pci_read_config_word(pci, 0x40, &tmp3);
3081 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3082 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3083 }
3084 #endif
3085
3086 err = pci_request_regions(pci, "ICH HD audio");
3087 if (err < 0)
3088 return err;
3089 chip->region_requested = 1;
3090
3091 chip->addr = pci_resource_start(pci, 0);
3092 chip->remap_addr = pci_ioremap_bar(pci, 0);
3093 if (chip->remap_addr == NULL) {
3094 snd_printk(KERN_ERR SFX "ioremap error\n");
3095 return -ENXIO;
3096 }
3097
3098 if (chip->msi)
3099 if (pci_enable_msi(pci) < 0)
3100 chip->msi = 0;
3101
3102 if (azx_acquire_irq(chip, 0) < 0)
3103 return -EBUSY;
3104
3105 pci_set_master(pci);
3106 synchronize_irq(chip->irq);
3107
3108 gcap = azx_readw(chip, GCAP);
3109 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
3110
3111 /* disable SB600 64bit support for safety */
3112 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3113 struct pci_dev *p_smbus;
3114 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3115 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3116 NULL);
3117 if (p_smbus) {
3118 if (p_smbus->revision < 0x30)
3119 gcap &= ~ICH6_GCAP_64OK;
3120 pci_dev_put(p_smbus);
3121 }
3122 }
3123
3124 /* disable 64bit DMA address on some devices */
3125 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3126 snd_printd(SFX "Disabling 64bit DMA\n");
3127 gcap &= ~ICH6_GCAP_64OK;
3128 }
3129
3130 /* disable buffer size rounding to 128-byte multiples if supported */
3131 if (align_buffer_size >= 0)
3132 chip->align_buffer_size = !!align_buffer_size;
3133 else {
3134 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3135 chip->align_buffer_size = 0;
3136 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3137 chip->align_buffer_size = 1;
3138 else
3139 chip->align_buffer_size = 1;
3140 }
3141
3142 /* allow 64bit DMA address if supported by H/W */
3143 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3144 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3145 else {
3146 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3147 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3148 }
3149
3150 /* read number of streams from GCAP register instead of using
3151 * hardcoded value
3152 */
3153 chip->capture_streams = (gcap >> 8) & 0x0f;
3154 chip->playback_streams = (gcap >> 12) & 0x0f;
3155 if (!chip->playback_streams && !chip->capture_streams) {
3156 /* gcap didn't give any info, switching to old method */
3157
3158 switch (chip->driver_type) {
3159 case AZX_DRIVER_ULI:
3160 chip->playback_streams = ULI_NUM_PLAYBACK;
3161 chip->capture_streams = ULI_NUM_CAPTURE;
3162 break;
3163 case AZX_DRIVER_ATIHDMI:
3164 case AZX_DRIVER_ATIHDMI_NS:
3165 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3166 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3167 break;
3168 case AZX_DRIVER_GENERIC:
3169 default:
3170 chip->playback_streams = ICH6_NUM_PLAYBACK;
3171 chip->capture_streams = ICH6_NUM_CAPTURE;
3172 break;
3173 }
3174 }
3175 chip->capture_index_offset = 0;
3176 chip->playback_index_offset = chip->capture_streams;
3177 chip->num_streams = chip->playback_streams + chip->capture_streams;
3178 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3179 GFP_KERNEL);
3180 if (!chip->azx_dev) {
3181 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3182 return -ENOMEM;
3183 }
3184
3185 for (i = 0; i < chip->num_streams; i++) {
3186 /* allocate memory for the BDL for each stream */
3187 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3188 snd_dma_pci_data(chip->pci),
3189 BDL_SIZE, &chip->azx_dev[i].bdl);
3190 if (err < 0) {
3191 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3192 return -ENOMEM;
3193 }
3194 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3195 }
3196 /* allocate memory for the position buffer */
3197 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3198 snd_dma_pci_data(chip->pci),
3199 chip->num_streams * 8, &chip->posbuf);
3200 if (err < 0) {
3201 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3202 return -ENOMEM;
3203 }
3204 mark_pages_wc(chip, &chip->posbuf, true);
3205 /* allocate CORB/RIRB */
3206 err = azx_alloc_cmd_io(chip);
3207 if (err < 0)
3208 return err;
3209
3210 /* initialize streams */
3211 azx_init_stream(chip);
3212
3213 /* initialize chip */
3214 azx_init_pci(chip);
3215 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3216
3217 /* codec detection */
3218 if (!chip->codec_mask) {
3219 snd_printk(KERN_ERR SFX "no codecs found!\n");
3220 return -ENODEV;
3221 }
3222
3223 strcpy(card->driver, "HDA-Intel");
3224 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3225 sizeof(card->shortname));
3226 snprintf(card->longname, sizeof(card->longname),
3227 "%s at 0x%lx irq %i",
3228 card->shortname, chip->addr, chip->irq);
3229
3230 return 0;
3231 }
3232
3233 static void power_down_all_codecs(struct azx *chip)
3234 {
3235 #ifdef CONFIG_PM
3236 /* The codecs were powered up in snd_hda_codec_new().
3237 * Now all initialization done, so turn them down if possible
3238 */
3239 struct hda_codec *codec;
3240 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3241 snd_hda_power_down(codec);
3242 }
3243 #endif
3244 }
3245
3246 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3247 /* callback from request_firmware_nowait() */
3248 static void azx_firmware_cb(const struct firmware *fw, void *context)
3249 {
3250 struct snd_card *card = context;
3251 struct azx *chip = card->private_data;
3252 struct pci_dev *pci = chip->pci;
3253
3254 if (!fw) {
3255 snd_printk(KERN_ERR SFX "Cannot load firmware, aborting\n");
3256 goto error;
3257 }
3258
3259 chip->fw = fw;
3260 if (!chip->disabled) {
3261 /* continue probing */
3262 if (azx_probe_continue(chip))
3263 goto error;
3264 }
3265 return; /* OK */
3266
3267 error:
3268 snd_card_free(card);
3269 pci_set_drvdata(pci, NULL);
3270 }
3271 #endif
3272
3273 static int __devinit azx_probe(struct pci_dev *pci,
3274 const struct pci_device_id *pci_id)
3275 {
3276 static int dev;
3277 struct snd_card *card;
3278 struct azx *chip;
3279 bool probe_now;
3280 int err;
3281
3282 if (dev >= SNDRV_CARDS)
3283 return -ENODEV;
3284 if (!enable[dev]) {
3285 dev++;
3286 return -ENOENT;
3287 }
3288
3289 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3290 if (err < 0) {
3291 snd_printk(KERN_ERR SFX "Error creating card!\n");
3292 return err;
3293 }
3294
3295 snd_card_set_dev(card, &pci->dev);
3296
3297 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3298 if (err < 0)
3299 goto out_free;
3300 card->private_data = chip;
3301 probe_now = !chip->disabled;
3302
3303 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3304 if (patch[dev] && *patch[dev]) {
3305 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3306 patch[dev]);
3307 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3308 &pci->dev, GFP_KERNEL, card,
3309 azx_firmware_cb);
3310 if (err < 0)
3311 goto out_free;
3312 probe_now = false; /* continued in azx_firmware_cb() */
3313 }
3314 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3315
3316 if (probe_now) {
3317 err = azx_probe_continue(chip);
3318 if (err < 0)
3319 goto out_free;
3320 }
3321
3322 pci_set_drvdata(pci, card);
3323
3324 if (pci_dev_run_wake(pci))
3325 pm_runtime_put_noidle(&pci->dev);
3326
3327 dev++;
3328 return 0;
3329
3330 out_free:
3331 snd_card_free(card);
3332 return err;
3333 }
3334
3335 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3336 {
3337 int dev = chip->dev_index;
3338 int err;
3339
3340 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3341 chip->beep_mode = beep_mode[dev];
3342 #endif
3343
3344 /* create codec instances */
3345 err = azx_codec_create(chip, model[dev]);
3346 if (err < 0)
3347 goto out_free;
3348 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3349 if (chip->fw) {
3350 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3351 chip->fw->data);
3352 if (err < 0)
3353 goto out_free;
3354 release_firmware(chip->fw); /* no longer needed */
3355 chip->fw = NULL;
3356 }
3357 #endif
3358 if ((probe_only[dev] & 1) == 0) {
3359 err = azx_codec_configure(chip);
3360 if (err < 0)
3361 goto out_free;
3362 }
3363
3364 /* create PCM streams */
3365 err = snd_hda_build_pcms(chip->bus);
3366 if (err < 0)
3367 goto out_free;
3368
3369 /* create mixer controls */
3370 err = azx_mixer_create(chip);
3371 if (err < 0)
3372 goto out_free;
3373
3374 err = snd_card_register(chip->card);
3375 if (err < 0)
3376 goto out_free;
3377
3378 chip->running = 1;
3379 power_down_all_codecs(chip);
3380 azx_notifier_register(chip);
3381 azx_add_card_list(chip);
3382
3383 return 0;
3384
3385 out_free:
3386 chip->init_failed = 1;
3387 return err;
3388 }
3389
3390 static void __devexit azx_remove(struct pci_dev *pci)
3391 {
3392 struct snd_card *card = pci_get_drvdata(pci);
3393
3394 if (pci_dev_run_wake(pci))
3395 pm_runtime_get_noresume(&pci->dev);
3396
3397 if (card)
3398 snd_card_free(card);
3399 pci_set_drvdata(pci, NULL);
3400 }
3401
3402 /* PCI IDs */
3403 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3404 /* CPT */
3405 { PCI_DEVICE(0x8086, 0x1c20),
3406 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3407 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3408 /* PBG */
3409 { PCI_DEVICE(0x8086, 0x1d20),
3410 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3411 AZX_DCAPS_BUFSIZE},
3412 /* Panther Point */
3413 { PCI_DEVICE(0x8086, 0x1e20),
3414 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3415 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3416 /* Lynx Point */
3417 { PCI_DEVICE(0x8086, 0x8c20),
3418 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3419 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3420 /* Lynx Point-LP */
3421 { PCI_DEVICE(0x8086, 0x9c20),
3422 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3423 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3424 /* Lynx Point-LP */
3425 { PCI_DEVICE(0x8086, 0x9c21),
3426 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3427 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3428 /* Haswell */
3429 { PCI_DEVICE(0x8086, 0x0c0c),
3430 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3431 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3432 /* SCH */
3433 { PCI_DEVICE(0x8086, 0x811b),
3434 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3435 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3436 { PCI_DEVICE(0x8086, 0x080a),
3437 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3438 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3439 /* ICH */
3440 { PCI_DEVICE(0x8086, 0x2668),
3441 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3442 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3443 { PCI_DEVICE(0x8086, 0x27d8),
3444 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3445 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3446 { PCI_DEVICE(0x8086, 0x269a),
3447 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3448 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3449 { PCI_DEVICE(0x8086, 0x284b),
3450 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3451 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3452 { PCI_DEVICE(0x8086, 0x293e),
3453 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3454 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3455 { PCI_DEVICE(0x8086, 0x293f),
3456 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3457 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3458 { PCI_DEVICE(0x8086, 0x3a3e),
3459 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3460 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3461 { PCI_DEVICE(0x8086, 0x3a6e),
3462 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3463 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3464 /* Generic Intel */
3465 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3466 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3467 .class_mask = 0xffffff,
3468 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3469 /* ATI SB 450/600/700/800/900 */
3470 { PCI_DEVICE(0x1002, 0x437b),
3471 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3472 { PCI_DEVICE(0x1002, 0x4383),
3473 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3474 /* AMD Hudson */
3475 { PCI_DEVICE(0x1022, 0x780d),
3476 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3477 /* ATI HDMI */
3478 { PCI_DEVICE(0x1002, 0x793b),
3479 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3480 { PCI_DEVICE(0x1002, 0x7919),
3481 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3482 { PCI_DEVICE(0x1002, 0x960f),
3483 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3484 { PCI_DEVICE(0x1002, 0x970f),
3485 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3486 { PCI_DEVICE(0x1002, 0xaa00),
3487 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3488 { PCI_DEVICE(0x1002, 0xaa08),
3489 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3490 { PCI_DEVICE(0x1002, 0xaa10),
3491 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3492 { PCI_DEVICE(0x1002, 0xaa18),
3493 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3494 { PCI_DEVICE(0x1002, 0xaa20),
3495 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3496 { PCI_DEVICE(0x1002, 0xaa28),
3497 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3498 { PCI_DEVICE(0x1002, 0xaa30),
3499 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3500 { PCI_DEVICE(0x1002, 0xaa38),
3501 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3502 { PCI_DEVICE(0x1002, 0xaa40),
3503 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3504 { PCI_DEVICE(0x1002, 0xaa48),
3505 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3506 { PCI_DEVICE(0x1002, 0x9902),
3507 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3508 { PCI_DEVICE(0x1002, 0xaaa0),
3509 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3510 { PCI_DEVICE(0x1002, 0xaaa8),
3511 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3512 { PCI_DEVICE(0x1002, 0xaab0),
3513 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3514 /* VIA VT8251/VT8237A */
3515 { PCI_DEVICE(0x1106, 0x3288),
3516 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3517 /* VIA GFX VT7122/VX900 */
3518 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3519 /* VIA GFX VT6122/VX11 */
3520 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3521 /* SIS966 */
3522 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3523 /* ULI M5461 */
3524 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3525 /* NVIDIA MCP */
3526 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3527 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3528 .class_mask = 0xffffff,
3529 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3530 /* Teradici */
3531 { PCI_DEVICE(0x6549, 0x1200),
3532 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3533 /* Creative X-Fi (CA0110-IBG) */
3534 /* CTHDA chips */
3535 { PCI_DEVICE(0x1102, 0x0010),
3536 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3537 { PCI_DEVICE(0x1102, 0x0012),
3538 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3539 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3540 /* the following entry conflicts with snd-ctxfi driver,
3541 * as ctxfi driver mutates from HD-audio to native mode with
3542 * a special command sequence.
3543 */
3544 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3545 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3546 .class_mask = 0xffffff,
3547 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3548 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3549 #else
3550 /* this entry seems still valid -- i.e. without emu20kx chip */
3551 { PCI_DEVICE(0x1102, 0x0009),
3552 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3553 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3554 #endif
3555 /* Vortex86MX */
3556 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3557 /* VMware HDAudio */
3558 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3559 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3560 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3561 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3562 .class_mask = 0xffffff,
3563 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3564 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3565 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3566 .class_mask = 0xffffff,
3567 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3568 { 0, }
3569 };
3570 MODULE_DEVICE_TABLE(pci, azx_ids);
3571
3572 /* pci_driver definition */
3573 static struct pci_driver azx_driver = {
3574 .name = KBUILD_MODNAME,
3575 .id_table = azx_ids,
3576 .probe = azx_probe,
3577 .remove = __devexit_p(azx_remove),
3578 .driver = {
3579 .pm = AZX_PM_OPS,
3580 },
3581 };
3582
3583 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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