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[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65 #include "hda_i915.h"
66 #include "hda_priv.h"
67
68
69 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
70 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
71 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
72 static char *model[SNDRV_CARDS];
73 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
75 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
76 static int probe_only[SNDRV_CARDS];
77 static int jackpoll_ms[SNDRV_CARDS];
78 static bool single_cmd;
79 static int enable_msi = -1;
80 #ifdef CONFIG_SND_HDA_PATCH_LOADER
81 static char *patch[SNDRV_CARDS];
82 #endif
83 #ifdef CONFIG_SND_HDA_INPUT_BEEP
84 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
85 CONFIG_SND_HDA_INPUT_BEEP_MODE};
86 #endif
87
88 module_param_array(index, int, NULL, 0444);
89 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
90 module_param_array(id, charp, NULL, 0444);
91 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
92 module_param_array(enable, bool, NULL, 0444);
93 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
94 module_param_array(model, charp, NULL, 0444);
95 MODULE_PARM_DESC(model, "Use the given board model.");
96 module_param_array(position_fix, int, NULL, 0444);
97 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
98 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
99 module_param_array(bdl_pos_adj, int, NULL, 0644);
100 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
101 module_param_array(probe_mask, int, NULL, 0444);
102 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
103 module_param_array(probe_only, int, NULL, 0444);
104 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
105 module_param_array(jackpoll_ms, int, NULL, 0444);
106 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
107 module_param(single_cmd, bool, 0444);
108 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
109 "(for debugging only).");
110 module_param(enable_msi, bint, 0444);
111 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
112 #ifdef CONFIG_SND_HDA_PATCH_LOADER
113 module_param_array(patch, charp, NULL, 0444);
114 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
115 #endif
116 #ifdef CONFIG_SND_HDA_INPUT_BEEP
117 module_param_array(beep_mode, bool, NULL, 0444);
118 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
119 "(0=off, 1=on) (default=1).");
120 #endif
121
122 #ifdef CONFIG_PM
123 static int param_set_xint(const char *val, const struct kernel_param *kp);
124 static struct kernel_param_ops param_ops_xint = {
125 .set = param_set_xint,
126 .get = param_get_int,
127 };
128 #define param_check_xint param_check_int
129
130 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
131 module_param(power_save, xint, 0644);
132 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
133 "(in second, 0 = disable).");
134
135 /* reset the HD-audio controller in power save mode.
136 * this may give more power-saving, but will take longer time to
137 * wake up.
138 */
139 static bool power_save_controller = 1;
140 module_param(power_save_controller, bool, 0644);
141 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
142 #endif /* CONFIG_PM */
143
144 static int align_buffer_size = -1;
145 module_param(align_buffer_size, bint, 0644);
146 MODULE_PARM_DESC(align_buffer_size,
147 "Force buffer and period sizes to be multiple of 128 bytes.");
148
149 #ifdef CONFIG_X86
150 static bool hda_snoop = true;
151 module_param_named(snoop, hda_snoop, bool, 0444);
152 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
153 #else
154 #define hda_snoop true
155 #endif
156
157
158 MODULE_LICENSE("GPL");
159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160 "{Intel, ICH6M},"
161 "{Intel, ICH7},"
162 "{Intel, ESB2},"
163 "{Intel, ICH8},"
164 "{Intel, ICH9},"
165 "{Intel, ICH10},"
166 "{Intel, PCH},"
167 "{Intel, CPT},"
168 "{Intel, PPT},"
169 "{Intel, LPT},"
170 "{Intel, LPT_LP},"
171 "{Intel, WPT_LP},"
172 "{Intel, HPT},"
173 "{Intel, PBG},"
174 "{Intel, SCH},"
175 "{ATI, SB450},"
176 "{ATI, SB600},"
177 "{ATI, RS600},"
178 "{ATI, RS690},"
179 "{ATI, RS780},"
180 "{ATI, R600},"
181 "{ATI, RV630},"
182 "{ATI, RV610},"
183 "{ATI, RV670},"
184 "{ATI, RV635},"
185 "{ATI, RV620},"
186 "{ATI, RV770},"
187 "{VIA, VT8251},"
188 "{VIA, VT8237A},"
189 "{SiS, SIS966},"
190 "{ULI, M5461}}");
191 MODULE_DESCRIPTION("Intel HDA driver");
192
193 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
194 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
195 #define SUPPORT_VGA_SWITCHEROO
196 #endif
197 #endif
198
199
200 /*
201 */
202
203 /* DSP lock helpers */
204 #ifdef CONFIG_SND_HDA_DSP_LOADER
205 #define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
206 #define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
207 #define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
208 #define dsp_is_locked(dev) ((dev)->locked)
209 #else
210 #define dsp_lock_init(dev) do {} while (0)
211 #define dsp_lock(dev) do {} while (0)
212 #define dsp_unlock(dev) do {} while (0)
213 #define dsp_is_locked(dev) 0
214 #endif
215
216 #define CREATE_TRACE_POINTS
217 #include "hda_intel_trace.h"
218
219 /* driver types */
220 enum {
221 AZX_DRIVER_ICH,
222 AZX_DRIVER_PCH,
223 AZX_DRIVER_SCH,
224 AZX_DRIVER_HDMI,
225 AZX_DRIVER_ATI,
226 AZX_DRIVER_ATIHDMI,
227 AZX_DRIVER_ATIHDMI_NS,
228 AZX_DRIVER_VIA,
229 AZX_DRIVER_SIS,
230 AZX_DRIVER_ULI,
231 AZX_DRIVER_NVIDIA,
232 AZX_DRIVER_TERA,
233 AZX_DRIVER_CTX,
234 AZX_DRIVER_CTHDA,
235 AZX_DRIVER_GENERIC,
236 AZX_NUM_DRIVERS, /* keep this as last entry */
237 };
238
239 /* quirks for Intel PCH */
240 #define AZX_DCAPS_INTEL_PCH_NOPM \
241 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
242 AZX_DCAPS_COUNT_LPIB_DELAY)
243
244 #define AZX_DCAPS_INTEL_PCH \
245 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
246
247 #define AZX_DCAPS_INTEL_HASWELL \
248 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
249 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
250 AZX_DCAPS_I915_POWERWELL)
251
252 /* quirks for ATI SB / AMD Hudson */
253 #define AZX_DCAPS_PRESET_ATI_SB \
254 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
255 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
256
257 /* quirks for ATI/AMD HDMI */
258 #define AZX_DCAPS_PRESET_ATI_HDMI \
259 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
260
261 /* quirks for Nvidia */
262 #define AZX_DCAPS_PRESET_NVIDIA \
263 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
264 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
265
266 #define AZX_DCAPS_PRESET_CTHDA \
267 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
268
269 /*
270 * VGA-switcher support
271 */
272 #ifdef SUPPORT_VGA_SWITCHEROO
273 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
274 #else
275 #define use_vga_switcheroo(chip) 0
276 #endif
277
278 static char *driver_short_names[] = {
279 [AZX_DRIVER_ICH] = "HDA Intel",
280 [AZX_DRIVER_PCH] = "HDA Intel PCH",
281 [AZX_DRIVER_SCH] = "HDA Intel MID",
282 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
283 [AZX_DRIVER_ATI] = "HDA ATI SB",
284 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
285 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
286 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
287 [AZX_DRIVER_SIS] = "HDA SIS966",
288 [AZX_DRIVER_ULI] = "HDA ULI M5461",
289 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
290 [AZX_DRIVER_TERA] = "HDA Teradici",
291 [AZX_DRIVER_CTX] = "HDA Creative",
292 [AZX_DRIVER_CTHDA] = "HDA Creative",
293 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
294 };
295
296 /* for pcm support */
297 #define get_azx_dev(substream) (substream->runtime->private_data)
298
299 #ifdef CONFIG_X86
300 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
301 {
302 int pages;
303
304 if (azx_snoop(chip))
305 return;
306 if (!dmab || !dmab->area || !dmab->bytes)
307 return;
308
309 #ifdef CONFIG_SND_DMA_SGBUF
310 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
311 struct snd_sg_buf *sgbuf = dmab->private_data;
312 if (on)
313 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
314 else
315 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
316 return;
317 }
318 #endif
319
320 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
321 if (on)
322 set_memory_wc((unsigned long)dmab->area, pages);
323 else
324 set_memory_wb((unsigned long)dmab->area, pages);
325 }
326
327 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
328 bool on)
329 {
330 __mark_pages_wc(chip, buf, on);
331 }
332 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
333 struct snd_pcm_substream *substream, bool on)
334 {
335 if (azx_dev->wc_marked != on) {
336 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
337 azx_dev->wc_marked = on;
338 }
339 }
340 #else
341 /* NOP for other archs */
342 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
343 bool on)
344 {
345 }
346 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
347 struct snd_pcm_substream *substream, bool on)
348 {
349 }
350 #endif
351
352 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
353 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
354 /*
355 * Interface for HD codec
356 */
357
358 /*
359 * CORB / RIRB interface
360 */
361 static int azx_alloc_cmd_io(struct azx *chip)
362 {
363 int err;
364
365 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
366 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
367 chip->card->dev,
368 PAGE_SIZE, &chip->rb);
369 if (err < 0) {
370 dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n");
371 return err;
372 }
373 mark_pages_wc(chip, &chip->rb, true);
374 return 0;
375 }
376
377 static void azx_init_cmd_io(struct azx *chip)
378 {
379 int timeout;
380
381 spin_lock_irq(&chip->reg_lock);
382 /* CORB set up */
383 chip->corb.addr = chip->rb.addr;
384 chip->corb.buf = (u32 *)chip->rb.area;
385 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
386 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
387
388 /* set the corb size to 256 entries (ULI requires explicitly) */
389 azx_writeb(chip, CORBSIZE, 0x02);
390 /* set the corb write pointer to 0 */
391 azx_writew(chip, CORBWP, 0);
392
393 /* reset the corb hw read pointer */
394 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
395 for (timeout = 1000; timeout > 0; timeout--) {
396 if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST)
397 break;
398 udelay(1);
399 }
400 if (timeout <= 0)
401 dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n",
402 azx_readw(chip, CORBRP));
403
404 azx_writew(chip, CORBRP, 0);
405 for (timeout = 1000; timeout > 0; timeout--) {
406 if (azx_readw(chip, CORBRP) == 0)
407 break;
408 udelay(1);
409 }
410 if (timeout <= 0)
411 dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n",
412 azx_readw(chip, CORBRP));
413
414 /* enable corb dma */
415 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
416
417 /* RIRB set up */
418 chip->rirb.addr = chip->rb.addr + 2048;
419 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
420 chip->rirb.wp = chip->rirb.rp = 0;
421 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
422 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
423 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
424
425 /* set the rirb size to 256 entries (ULI requires explicitly) */
426 azx_writeb(chip, RIRBSIZE, 0x02);
427 /* reset the rirb hw write pointer */
428 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
429 /* set N=1, get RIRB response interrupt for new entry */
430 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
431 azx_writew(chip, RINTCNT, 0xc0);
432 else
433 azx_writew(chip, RINTCNT, 1);
434 /* enable rirb dma and response irq */
435 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
436 spin_unlock_irq(&chip->reg_lock);
437 }
438
439 static void azx_free_cmd_io(struct azx *chip)
440 {
441 spin_lock_irq(&chip->reg_lock);
442 /* disable ringbuffer DMAs */
443 azx_writeb(chip, RIRBCTL, 0);
444 azx_writeb(chip, CORBCTL, 0);
445 spin_unlock_irq(&chip->reg_lock);
446 }
447
448 static unsigned int azx_command_addr(u32 cmd)
449 {
450 unsigned int addr = cmd >> 28;
451
452 if (addr >= AZX_MAX_CODECS) {
453 snd_BUG();
454 addr = 0;
455 }
456
457 return addr;
458 }
459
460 /* send a command */
461 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
462 {
463 struct azx *chip = bus->private_data;
464 unsigned int addr = azx_command_addr(val);
465 unsigned int wp, rp;
466
467 spin_lock_irq(&chip->reg_lock);
468
469 /* add command to corb */
470 wp = azx_readw(chip, CORBWP);
471 if (wp == 0xffff) {
472 /* something wrong, controller likely turned to D3 */
473 spin_unlock_irq(&chip->reg_lock);
474 return -EIO;
475 }
476 wp++;
477 wp %= ICH6_MAX_CORB_ENTRIES;
478
479 rp = azx_readw(chip, CORBRP);
480 if (wp == rp) {
481 /* oops, it's full */
482 spin_unlock_irq(&chip->reg_lock);
483 return -EAGAIN;
484 }
485
486 chip->rirb.cmds[addr]++;
487 chip->corb.buf[wp] = cpu_to_le32(val);
488 azx_writew(chip, CORBWP, wp);
489
490 spin_unlock_irq(&chip->reg_lock);
491
492 return 0;
493 }
494
495 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
496
497 /* retrieve RIRB entry - called from interrupt handler */
498 static void azx_update_rirb(struct azx *chip)
499 {
500 unsigned int rp, wp;
501 unsigned int addr;
502 u32 res, res_ex;
503
504 wp = azx_readw(chip, RIRBWP);
505 if (wp == 0xffff) {
506 /* something wrong, controller likely turned to D3 */
507 return;
508 }
509
510 if (wp == chip->rirb.wp)
511 return;
512 chip->rirb.wp = wp;
513
514 while (chip->rirb.rp != wp) {
515 chip->rirb.rp++;
516 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
517
518 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
519 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
520 res = le32_to_cpu(chip->rirb.buf[rp]);
521 addr = res_ex & 0xf;
522 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
523 dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
524 res, res_ex,
525 chip->rirb.rp, wp);
526 snd_BUG();
527 }
528 else if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
529 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
530 else if (chip->rirb.cmds[addr]) {
531 chip->rirb.res[addr] = res;
532 smp_wmb();
533 chip->rirb.cmds[addr]--;
534 } else if (printk_ratelimit()) {
535 dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
536 res, res_ex,
537 chip->last_cmd[addr]);
538 }
539 }
540 }
541
542 /* receive a response */
543 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
544 unsigned int addr)
545 {
546 struct azx *chip = bus->private_data;
547 unsigned long timeout;
548 unsigned long loopcounter;
549 int do_poll = 0;
550
551 again:
552 timeout = jiffies + msecs_to_jiffies(1000);
553
554 for (loopcounter = 0;; loopcounter++) {
555 if (chip->polling_mode || do_poll) {
556 spin_lock_irq(&chip->reg_lock);
557 azx_update_rirb(chip);
558 spin_unlock_irq(&chip->reg_lock);
559 }
560 if (!chip->rirb.cmds[addr]) {
561 smp_rmb();
562 bus->rirb_error = 0;
563
564 if (!do_poll)
565 chip->poll_count = 0;
566 return chip->rirb.res[addr]; /* the last value */
567 }
568 if (time_after(jiffies, timeout))
569 break;
570 if (bus->needs_damn_long_delay || loopcounter > 3000)
571 msleep(2); /* temporary workaround */
572 else {
573 udelay(10);
574 cond_resched();
575 }
576 }
577
578 if (!bus->no_response_fallback)
579 return -1;
580
581 if (!chip->polling_mode && chip->poll_count < 2) {
582 dev_dbg(chip->card->dev,
583 "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
584 chip->last_cmd[addr]);
585 do_poll = 1;
586 chip->poll_count++;
587 goto again;
588 }
589
590
591 if (!chip->polling_mode) {
592 dev_warn(chip->card->dev,
593 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
594 chip->last_cmd[addr]);
595 chip->polling_mode = 1;
596 goto again;
597 }
598
599 if (chip->msi) {
600 dev_warn(chip->card->dev,
601 "No response from codec, disabling MSI: last cmd=0x%08x\n",
602 chip->last_cmd[addr]);
603 if (chip->ops->disable_msi_reset_irq &&
604 chip->ops->disable_msi_reset_irq(chip) < 0) {
605 bus->rirb_error = 1;
606 return -1;
607 }
608 goto again;
609 }
610
611 if (chip->probing) {
612 /* If this critical timeout happens during the codec probing
613 * phase, this is likely an access to a non-existing codec
614 * slot. Better to return an error and reset the system.
615 */
616 return -1;
617 }
618
619 /* a fatal communication error; need either to reset or to fallback
620 * to the single_cmd mode
621 */
622 bus->rirb_error = 1;
623 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
624 bus->response_reset = 1;
625 return -1; /* give a chance to retry */
626 }
627
628 dev_err(chip->card->dev,
629 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
630 chip->last_cmd[addr]);
631 chip->single_cmd = 1;
632 bus->response_reset = 0;
633 /* release CORB/RIRB */
634 azx_free_cmd_io(chip);
635 /* disable unsolicited responses */
636 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
637 return -1;
638 }
639
640 /*
641 * Use the single immediate command instead of CORB/RIRB for simplicity
642 *
643 * Note: according to Intel, this is not preferred use. The command was
644 * intended for the BIOS only, and may get confused with unsolicited
645 * responses. So, we shouldn't use it for normal operation from the
646 * driver.
647 * I left the codes, however, for debugging/testing purposes.
648 */
649
650 /* receive a response */
651 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
652 {
653 int timeout = 50;
654
655 while (timeout--) {
656 /* check IRV busy bit */
657 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
658 /* reuse rirb.res as the response return value */
659 chip->rirb.res[addr] = azx_readl(chip, IR);
660 return 0;
661 }
662 udelay(1);
663 }
664 if (printk_ratelimit())
665 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
666 azx_readw(chip, IRS));
667 chip->rirb.res[addr] = -1;
668 return -EIO;
669 }
670
671 /* send a command */
672 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
673 {
674 struct azx *chip = bus->private_data;
675 unsigned int addr = azx_command_addr(val);
676 int timeout = 50;
677
678 bus->rirb_error = 0;
679 while (timeout--) {
680 /* check ICB busy bit */
681 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
682 /* Clear IRV valid bit */
683 azx_writew(chip, IRS, azx_readw(chip, IRS) |
684 ICH6_IRS_VALID);
685 azx_writel(chip, IC, val);
686 azx_writew(chip, IRS, azx_readw(chip, IRS) |
687 ICH6_IRS_BUSY);
688 return azx_single_wait_for_response(chip, addr);
689 }
690 udelay(1);
691 }
692 if (printk_ratelimit())
693 dev_dbg(chip->card->dev,
694 "send_cmd timeout: IRS=0x%x, val=0x%x\n",
695 azx_readw(chip, IRS), val);
696 return -EIO;
697 }
698
699 /* receive a response */
700 static unsigned int azx_single_get_response(struct hda_bus *bus,
701 unsigned int addr)
702 {
703 struct azx *chip = bus->private_data;
704 return chip->rirb.res[addr];
705 }
706
707 /*
708 * The below are the main callbacks from hda_codec.
709 *
710 * They are just the skeleton to call sub-callbacks according to the
711 * current setting of chip->single_cmd.
712 */
713
714 /* send a command */
715 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
716 {
717 struct azx *chip = bus->private_data;
718
719 if (chip->disabled)
720 return 0;
721 chip->last_cmd[azx_command_addr(val)] = val;
722 if (chip->single_cmd)
723 return azx_single_send_cmd(bus, val);
724 else
725 return azx_corb_send_cmd(bus, val);
726 }
727
728 /* get a response */
729 static unsigned int azx_get_response(struct hda_bus *bus,
730 unsigned int addr)
731 {
732 struct azx *chip = bus->private_data;
733 if (chip->disabled)
734 return 0;
735 if (chip->single_cmd)
736 return azx_single_get_response(bus, addr);
737 else
738 return azx_rirb_get_response(bus, addr);
739 }
740
741 #ifdef CONFIG_PM
742 static void azx_power_notify(struct hda_bus *bus, bool power_up);
743 #endif
744
745 #ifdef CONFIG_SND_HDA_DSP_LOADER
746 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
747 unsigned int byte_size,
748 struct snd_dma_buffer *bufp);
749 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
750 static void azx_load_dsp_cleanup(struct hda_bus *bus,
751 struct snd_dma_buffer *dmab);
752 #endif
753
754 /* enter link reset */
755 static void azx_enter_link_reset(struct azx *chip)
756 {
757 unsigned long timeout;
758
759 /* reset controller */
760 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
761
762 timeout = jiffies + msecs_to_jiffies(100);
763 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
764 time_before(jiffies, timeout))
765 usleep_range(500, 1000);
766 }
767
768 /* exit link reset */
769 static void azx_exit_link_reset(struct azx *chip)
770 {
771 unsigned long timeout;
772
773 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
774
775 timeout = jiffies + msecs_to_jiffies(100);
776 while (!azx_readb(chip, GCTL) &&
777 time_before(jiffies, timeout))
778 usleep_range(500, 1000);
779 }
780
781 /* reset codec link */
782 static int azx_reset(struct azx *chip, int full_reset)
783 {
784 if (!full_reset)
785 goto __skip;
786
787 /* clear STATESTS */
788 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
789
790 /* reset controller */
791 azx_enter_link_reset(chip);
792
793 /* delay for >= 100us for codec PLL to settle per spec
794 * Rev 0.9 section 5.5.1
795 */
796 usleep_range(500, 1000);
797
798 /* Bring controller out of reset */
799 azx_exit_link_reset(chip);
800
801 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
802 usleep_range(1000, 1200);
803
804 __skip:
805 /* check to see if controller is ready */
806 if (!azx_readb(chip, GCTL)) {
807 dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
808 return -EBUSY;
809 }
810
811 /* Accept unsolicited responses */
812 if (!chip->single_cmd)
813 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
814 ICH6_GCTL_UNSOL);
815
816 /* detect codecs */
817 if (!chip->codec_mask) {
818 chip->codec_mask = azx_readw(chip, STATESTS);
819 dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
820 chip->codec_mask);
821 }
822
823 return 0;
824 }
825
826
827 /*
828 * Lowlevel interface
829 */
830
831 /* enable interrupts */
832 static void azx_int_enable(struct azx *chip)
833 {
834 /* enable controller CIE and GIE */
835 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
836 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
837 }
838
839 /* disable interrupts */
840 static void azx_int_disable(struct azx *chip)
841 {
842 int i;
843
844 /* disable interrupts in stream descriptor */
845 for (i = 0; i < chip->num_streams; i++) {
846 struct azx_dev *azx_dev = &chip->azx_dev[i];
847 azx_sd_writeb(chip, azx_dev, SD_CTL,
848 azx_sd_readb(chip, azx_dev, SD_CTL) &
849 ~SD_INT_MASK);
850 }
851
852 /* disable SIE for all streams */
853 azx_writeb(chip, INTCTL, 0);
854
855 /* disable controller CIE and GIE */
856 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
857 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
858 }
859
860 /* clear interrupts */
861 static void azx_int_clear(struct azx *chip)
862 {
863 int i;
864
865 /* clear stream status */
866 for (i = 0; i < chip->num_streams; i++) {
867 struct azx_dev *azx_dev = &chip->azx_dev[i];
868 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
869 }
870
871 /* clear STATESTS */
872 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
873
874 /* clear rirb status */
875 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
876
877 /* clear int status */
878 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
879 }
880
881 /* start a stream */
882 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
883 {
884 /*
885 * Before stream start, initialize parameter
886 */
887 azx_dev->insufficient = 1;
888
889 /* enable SIE */
890 azx_writel(chip, INTCTL,
891 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
892 /* set DMA start and interrupt mask */
893 azx_sd_writeb(chip, azx_dev, SD_CTL,
894 azx_sd_readb(chip, azx_dev, SD_CTL) |
895 SD_CTL_DMA_START | SD_INT_MASK);
896 }
897
898 /* stop DMA */
899 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
900 {
901 azx_sd_writeb(chip, azx_dev, SD_CTL,
902 azx_sd_readb(chip, azx_dev, SD_CTL) &
903 ~(SD_CTL_DMA_START | SD_INT_MASK));
904 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
905 }
906
907 /* stop a stream */
908 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
909 {
910 azx_stream_clear(chip, azx_dev);
911 /* disable SIE */
912 azx_writel(chip, INTCTL,
913 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
914 }
915
916
917 /*
918 * reset and start the controller registers
919 */
920 static void azx_init_chip(struct azx *chip, int full_reset)
921 {
922 if (chip->initialized)
923 return;
924
925 /* reset controller */
926 azx_reset(chip, full_reset);
927
928 /* initialize interrupts */
929 azx_int_clear(chip);
930 azx_int_enable(chip);
931
932 /* initialize the codec command I/O */
933 if (!chip->single_cmd)
934 azx_init_cmd_io(chip);
935
936 /* program the position buffer */
937 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
938 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
939
940 chip->initialized = 1;
941 }
942
943 /*
944 * initialize the PCI registers
945 */
946 /* update bits in a PCI register byte */
947 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
948 unsigned char mask, unsigned char val)
949 {
950 unsigned char data;
951
952 pci_read_config_byte(pci, reg, &data);
953 data &= ~mask;
954 data |= (val & mask);
955 pci_write_config_byte(pci, reg, data);
956 }
957
958 static void azx_init_pci(struct azx *chip)
959 {
960 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
961 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
962 * Ensuring these bits are 0 clears playback static on some HD Audio
963 * codecs.
964 * The PCI register TCSEL is defined in the Intel manuals.
965 */
966 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
967 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
968 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
969 }
970
971 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
972 * we need to enable snoop.
973 */
974 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
975 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
976 azx_snoop(chip));
977 update_pci_byte(chip->pci,
978 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
979 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
980 }
981
982 /* For NVIDIA HDA, enable snoop */
983 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
984 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
985 azx_snoop(chip));
986 update_pci_byte(chip->pci,
987 NVIDIA_HDA_TRANSREG_ADDR,
988 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
989 update_pci_byte(chip->pci,
990 NVIDIA_HDA_ISTRM_COH,
991 0x01, NVIDIA_HDA_ENABLE_COHBIT);
992 update_pci_byte(chip->pci,
993 NVIDIA_HDA_OSTRM_COH,
994 0x01, NVIDIA_HDA_ENABLE_COHBIT);
995 }
996
997 /* Enable SCH/PCH snoop if needed */
998 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
999 unsigned short snoop;
1000 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1001 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1002 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1003 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1004 if (!azx_snoop(chip))
1005 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1006 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1007 pci_read_config_word(chip->pci,
1008 INTEL_SCH_HDA_DEVC, &snoop);
1009 }
1010 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
1011 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
1012 "Disabled" : "Enabled");
1013 }
1014 }
1015
1016
1017 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1018
1019 /*
1020 * interrupt handler
1021 */
1022 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1023 {
1024 struct azx *chip = dev_id;
1025 struct azx_dev *azx_dev;
1026 u32 status;
1027 u8 sd_status;
1028 int i, ok;
1029
1030 #ifdef CONFIG_PM_RUNTIME
1031 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1032 if (chip->card->dev->power.runtime_status != RPM_ACTIVE)
1033 return IRQ_NONE;
1034 #endif
1035
1036 spin_lock(&chip->reg_lock);
1037
1038 if (chip->disabled) {
1039 spin_unlock(&chip->reg_lock);
1040 return IRQ_NONE;
1041 }
1042
1043 status = azx_readl(chip, INTSTS);
1044 if (status == 0 || status == 0xffffffff) {
1045 spin_unlock(&chip->reg_lock);
1046 return IRQ_NONE;
1047 }
1048
1049 for (i = 0; i < chip->num_streams; i++) {
1050 azx_dev = &chip->azx_dev[i];
1051 if (status & azx_dev->sd_int_sta_mask) {
1052 sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
1053 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
1054 if (!azx_dev->substream || !azx_dev->running ||
1055 !(sd_status & SD_INT_COMPLETE))
1056 continue;
1057 /* check whether this IRQ is really acceptable */
1058 ok = azx_position_ok(chip, azx_dev);
1059 if (ok == 1) {
1060 azx_dev->irq_pending = 0;
1061 spin_unlock(&chip->reg_lock);
1062 snd_pcm_period_elapsed(azx_dev->substream);
1063 spin_lock(&chip->reg_lock);
1064 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1065 /* bogus IRQ, process it later */
1066 azx_dev->irq_pending = 1;
1067 queue_work(chip->bus->workq,
1068 &chip->irq_pending_work);
1069 }
1070 }
1071 }
1072
1073 /* clear rirb int */
1074 status = azx_readb(chip, RIRBSTS);
1075 if (status & RIRB_INT_MASK) {
1076 if (status & RIRB_INT_RESPONSE) {
1077 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1078 udelay(80);
1079 azx_update_rirb(chip);
1080 }
1081 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1082 }
1083
1084 spin_unlock(&chip->reg_lock);
1085
1086 return IRQ_HANDLED;
1087 }
1088
1089
1090 /*
1091 * set up a BDL entry
1092 */
1093 static int setup_bdle(struct azx *chip,
1094 struct snd_dma_buffer *dmab,
1095 struct azx_dev *azx_dev, u32 **bdlp,
1096 int ofs, int size, int with_ioc)
1097 {
1098 u32 *bdl = *bdlp;
1099
1100 while (size > 0) {
1101 dma_addr_t addr;
1102 int chunk;
1103
1104 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1105 return -EINVAL;
1106
1107 addr = snd_sgbuf_get_addr(dmab, ofs);
1108 /* program the address field of the BDL entry */
1109 bdl[0] = cpu_to_le32((u32)addr);
1110 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1111 /* program the size field of the BDL entry */
1112 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1113 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1114 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1115 u32 remain = 0x1000 - (ofs & 0xfff);
1116 if (chunk > remain)
1117 chunk = remain;
1118 }
1119 bdl[2] = cpu_to_le32(chunk);
1120 /* program the IOC to enable interrupt
1121 * only when the whole fragment is processed
1122 */
1123 size -= chunk;
1124 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1125 bdl += 4;
1126 azx_dev->frags++;
1127 ofs += chunk;
1128 }
1129 *bdlp = bdl;
1130 return ofs;
1131 }
1132
1133 /*
1134 * set up BDL entries
1135 */
1136 static int azx_setup_periods(struct azx *chip,
1137 struct snd_pcm_substream *substream,
1138 struct azx_dev *azx_dev)
1139 {
1140 u32 *bdl;
1141 int i, ofs, periods, period_bytes;
1142 int pos_adj = 0;
1143
1144 /* reset BDL address */
1145 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1146 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1147
1148 period_bytes = azx_dev->period_bytes;
1149 periods = azx_dev->bufsize / period_bytes;
1150
1151 /* program the initial BDL entries */
1152 bdl = (u32 *)azx_dev->bdl.area;
1153 ofs = 0;
1154 azx_dev->frags = 0;
1155
1156 if (chip->bdl_pos_adj)
1157 pos_adj = chip->bdl_pos_adj[chip->dev_index];
1158 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1159 struct snd_pcm_runtime *runtime = substream->runtime;
1160 int pos_align = pos_adj;
1161 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1162 if (!pos_adj)
1163 pos_adj = pos_align;
1164 else
1165 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1166 pos_align;
1167 pos_adj = frames_to_bytes(runtime, pos_adj);
1168 if (pos_adj >= period_bytes) {
1169 dev_warn(chip->card->dev,"Too big adjustment %d\n",
1170 pos_adj);
1171 pos_adj = 0;
1172 } else {
1173 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1174 azx_dev,
1175 &bdl, ofs, pos_adj, true);
1176 if (ofs < 0)
1177 goto error;
1178 }
1179 } else
1180 pos_adj = 0;
1181
1182 for (i = 0; i < periods; i++) {
1183 if (i == periods - 1 && pos_adj)
1184 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1185 azx_dev, &bdl, ofs,
1186 period_bytes - pos_adj, 0);
1187 else
1188 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1189 azx_dev, &bdl, ofs,
1190 period_bytes,
1191 !azx_dev->no_period_wakeup);
1192 if (ofs < 0)
1193 goto error;
1194 }
1195 return 0;
1196
1197 error:
1198 dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
1199 azx_dev->bufsize, period_bytes);
1200 return -EINVAL;
1201 }
1202
1203 /* reset stream */
1204 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1205 {
1206 unsigned char val;
1207 int timeout;
1208
1209 azx_stream_clear(chip, azx_dev);
1210
1211 azx_sd_writeb(chip, azx_dev, SD_CTL,
1212 azx_sd_readb(chip, azx_dev, SD_CTL) |
1213 SD_CTL_STREAM_RESET);
1214 udelay(3);
1215 timeout = 300;
1216 while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
1217 SD_CTL_STREAM_RESET) && --timeout)
1218 ;
1219 val &= ~SD_CTL_STREAM_RESET;
1220 azx_sd_writeb(chip, azx_dev, SD_CTL, val);
1221 udelay(3);
1222
1223 timeout = 300;
1224 /* waiting for hardware to report that the stream is out of reset */
1225 while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
1226 SD_CTL_STREAM_RESET) && --timeout)
1227 ;
1228
1229 /* reset first position - may not be synced with hw at this time */
1230 *azx_dev->posbuf = 0;
1231 }
1232
1233 /*
1234 * set up the SD for streaming
1235 */
1236 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1237 {
1238 unsigned int val;
1239 /* make sure the run bit is zero for SD */
1240 azx_stream_clear(chip, azx_dev);
1241 /* program the stream_tag */
1242 val = azx_sd_readl(chip, azx_dev, SD_CTL);
1243 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1244 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1245 if (!azx_snoop(chip))
1246 val |= SD_CTL_TRAFFIC_PRIO;
1247 azx_sd_writel(chip, azx_dev, SD_CTL, val);
1248
1249 /* program the length of samples in cyclic buffer */
1250 azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize);
1251
1252 /* program the stream format */
1253 /* this value needs to be the same as the one programmed */
1254 azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val);
1255
1256 /* program the stream LVI (last valid index) of the BDL */
1257 azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1);
1258
1259 /* program the BDL address */
1260 /* lower BDL address */
1261 azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1262 /* upper BDL address */
1263 azx_sd_writel(chip, azx_dev, SD_BDLPU,
1264 upper_32_bits(azx_dev->bdl.addr));
1265
1266 /* enable the position buffer */
1267 if (chip->position_fix[0] != POS_FIX_LPIB ||
1268 chip->position_fix[1] != POS_FIX_LPIB) {
1269 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1270 azx_writel(chip, DPLBASE,
1271 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1272 }
1273
1274 /* set the interrupt enable bits in the descriptor control register */
1275 azx_sd_writel(chip, azx_dev, SD_CTL,
1276 azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK);
1277
1278 return 0;
1279 }
1280
1281 /*
1282 * Probe the given codec address
1283 */
1284 static int probe_codec(struct azx *chip, int addr)
1285 {
1286 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1287 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1288 unsigned int res;
1289
1290 mutex_lock(&chip->bus->cmd_mutex);
1291 chip->probing = 1;
1292 azx_send_cmd(chip->bus, cmd);
1293 res = azx_get_response(chip->bus, addr);
1294 chip->probing = 0;
1295 mutex_unlock(&chip->bus->cmd_mutex);
1296 if (res == -1)
1297 return -EIO;
1298 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1299 return 0;
1300 }
1301
1302 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1303 struct hda_pcm *cpcm);
1304 static void azx_stop_chip(struct azx *chip);
1305
1306 static void azx_bus_reset(struct hda_bus *bus)
1307 {
1308 struct azx *chip = bus->private_data;
1309
1310 bus->in_reset = 1;
1311 azx_stop_chip(chip);
1312 azx_init_chip(chip, 1);
1313 #ifdef CONFIG_PM
1314 if (chip->initialized) {
1315 struct azx_pcm *p;
1316 list_for_each_entry(p, &chip->pcm_list, list)
1317 snd_pcm_suspend_all(p->pcm);
1318 snd_hda_suspend(chip->bus);
1319 snd_hda_resume(chip->bus);
1320 }
1321 #endif
1322 bus->in_reset = 0;
1323 }
1324
1325 static int get_jackpoll_interval(struct azx *chip)
1326 {
1327 int i = jackpoll_ms[chip->dev_index];
1328 unsigned int j;
1329 if (i == 0)
1330 return 0;
1331 if (i < 50 || i > 60000)
1332 j = 0;
1333 else
1334 j = msecs_to_jiffies(i);
1335 if (j == 0)
1336 dev_warn(chip->card->dev,
1337 "jackpoll_ms value out of range: %d\n", i);
1338 return j;
1339 }
1340
1341 /*
1342 * Codec initialization
1343 */
1344
1345 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1346 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1347 [AZX_DRIVER_NVIDIA] = 8,
1348 [AZX_DRIVER_TERA] = 1,
1349 };
1350
1351 static int azx_codec_create(struct azx *chip, const char *model)
1352 {
1353 struct hda_bus_template bus_temp;
1354 int c, codecs, err;
1355 int max_slots;
1356
1357 memset(&bus_temp, 0, sizeof(bus_temp));
1358 bus_temp.private_data = chip;
1359 bus_temp.modelname = model;
1360 bus_temp.pci = chip->pci;
1361 bus_temp.ops.command = azx_send_cmd;
1362 bus_temp.ops.get_response = azx_get_response;
1363 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1364 bus_temp.ops.bus_reset = azx_bus_reset;
1365 #ifdef CONFIG_PM
1366 bus_temp.power_save = &power_save;
1367 bus_temp.ops.pm_notify = azx_power_notify;
1368 #endif
1369 #ifdef CONFIG_SND_HDA_DSP_LOADER
1370 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1371 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1372 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1373 #endif
1374
1375 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1376 if (err < 0)
1377 return err;
1378
1379 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1380 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1381 chip->bus->needs_damn_long_delay = 1;
1382 }
1383
1384 codecs = 0;
1385 max_slots = azx_max_codecs[chip->driver_type];
1386 if (!max_slots)
1387 max_slots = AZX_DEFAULT_CODECS;
1388
1389 /* First try to probe all given codec slots */
1390 for (c = 0; c < max_slots; c++) {
1391 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1392 if (probe_codec(chip, c) < 0) {
1393 /* Some BIOSen give you wrong codec addresses
1394 * that don't exist
1395 */
1396 dev_warn(chip->card->dev,
1397 "Codec #%d probe error; disabling it...\n", c);
1398 chip->codec_mask &= ~(1 << c);
1399 /* More badly, accessing to a non-existing
1400 * codec often screws up the controller chip,
1401 * and disturbs the further communications.
1402 * Thus if an error occurs during probing,
1403 * better to reset the controller chip to
1404 * get back to the sanity state.
1405 */
1406 azx_stop_chip(chip);
1407 azx_init_chip(chip, 1);
1408 }
1409 }
1410 }
1411
1412 /* AMD chipsets often cause the communication stalls upon certain
1413 * sequence like the pin-detection. It seems that forcing the synced
1414 * access works around the stall. Grrr...
1415 */
1416 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1417 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1418 chip->bus->sync_write = 1;
1419 chip->bus->allow_bus_reset = 1;
1420 }
1421
1422 /* Then create codec instances */
1423 for (c = 0; c < max_slots; c++) {
1424 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1425 struct hda_codec *codec;
1426 err = snd_hda_codec_new(chip->bus, c, &codec);
1427 if (err < 0)
1428 continue;
1429 codec->jackpoll_interval = get_jackpoll_interval(chip);
1430 codec->beep_mode = chip->beep_mode;
1431 codecs++;
1432 }
1433 }
1434 if (!codecs) {
1435 dev_err(chip->card->dev, "no codecs initialized\n");
1436 return -ENXIO;
1437 }
1438 return 0;
1439 }
1440
1441 /* configure each codec instance */
1442 static int azx_codec_configure(struct azx *chip)
1443 {
1444 struct hda_codec *codec;
1445 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1446 snd_hda_codec_configure(codec);
1447 }
1448 return 0;
1449 }
1450
1451
1452 /*
1453 * PCM support
1454 */
1455
1456 /* assign a stream for the PCM */
1457 static inline struct azx_dev *
1458 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1459 {
1460 int dev, i, nums;
1461 struct azx_dev *res = NULL;
1462 /* make a non-zero unique key for the substream */
1463 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1464 (substream->stream + 1);
1465
1466 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1467 dev = chip->playback_index_offset;
1468 nums = chip->playback_streams;
1469 } else {
1470 dev = chip->capture_index_offset;
1471 nums = chip->capture_streams;
1472 }
1473 for (i = 0; i < nums; i++, dev++) {
1474 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1475 dsp_lock(azx_dev);
1476 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1477 res = azx_dev;
1478 if (res->assigned_key == key) {
1479 res->opened = 1;
1480 res->assigned_key = key;
1481 dsp_unlock(azx_dev);
1482 return azx_dev;
1483 }
1484 }
1485 dsp_unlock(azx_dev);
1486 }
1487 if (res) {
1488 dsp_lock(res);
1489 res->opened = 1;
1490 res->assigned_key = key;
1491 dsp_unlock(res);
1492 }
1493 return res;
1494 }
1495
1496 /* release the assigned stream */
1497 static inline void azx_release_device(struct azx_dev *azx_dev)
1498 {
1499 azx_dev->opened = 0;
1500 }
1501
1502 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1503 {
1504 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1505 struct snd_pcm_substream *substream = azx_dev->substream;
1506 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1507 struct azx *chip = apcm->chip;
1508
1509 return azx_readl(chip, WALLCLK);
1510 }
1511
1512 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1513 bool force, cycle_t last)
1514 {
1515 struct azx_dev *azx_dev = get_azx_dev(substream);
1516 struct timecounter *tc = &azx_dev->azx_tc;
1517 struct cyclecounter *cc = &azx_dev->azx_cc;
1518 u64 nsec;
1519
1520 cc->read = azx_cc_read;
1521 cc->mask = CLOCKSOURCE_MASK(32);
1522
1523 /*
1524 * Converting from 24 MHz to ns means applying a 125/3 factor.
1525 * To avoid any saturation issues in intermediate operations,
1526 * the 125 factor is applied first. The division is applied
1527 * last after reading the timecounter value.
1528 * Applying the 1/3 factor as part of the multiplication
1529 * requires at least 20 bits for a decent precision, however
1530 * overflows occur after about 4 hours or less, not a option.
1531 */
1532
1533 cc->mult = 125; /* saturation after 195 years */
1534 cc->shift = 0;
1535
1536 nsec = 0; /* audio time is elapsed time since trigger */
1537 timecounter_init(tc, cc, nsec);
1538 if (force)
1539 /*
1540 * force timecounter to use predefined value,
1541 * used for synchronized starts
1542 */
1543 tc->cycle_last = last;
1544 }
1545
1546 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
1547 u64 nsec)
1548 {
1549 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1550 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1551 u64 codec_frames, codec_nsecs;
1552
1553 if (!hinfo->ops.get_delay)
1554 return nsec;
1555
1556 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1557 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1558 substream->runtime->rate);
1559
1560 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1561 return nsec + codec_nsecs;
1562
1563 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1564 }
1565
1566 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1567 struct timespec *ts)
1568 {
1569 struct azx_dev *azx_dev = get_azx_dev(substream);
1570 u64 nsec;
1571
1572 nsec = timecounter_read(&azx_dev->azx_tc);
1573 nsec = div_u64(nsec, 3); /* can be optimized */
1574 nsec = azx_adjust_codec_delay(substream, nsec);
1575
1576 *ts = ns_to_timespec(nsec);
1577
1578 return 0;
1579 }
1580
1581 static struct snd_pcm_hardware azx_pcm_hw = {
1582 .info = (SNDRV_PCM_INFO_MMAP |
1583 SNDRV_PCM_INFO_INTERLEAVED |
1584 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1585 SNDRV_PCM_INFO_MMAP_VALID |
1586 /* No full-resume yet implemented */
1587 /* SNDRV_PCM_INFO_RESUME |*/
1588 SNDRV_PCM_INFO_PAUSE |
1589 SNDRV_PCM_INFO_SYNC_START |
1590 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1591 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1592 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1593 .rates = SNDRV_PCM_RATE_48000,
1594 .rate_min = 48000,
1595 .rate_max = 48000,
1596 .channels_min = 2,
1597 .channels_max = 2,
1598 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1599 .period_bytes_min = 128,
1600 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1601 .periods_min = 2,
1602 .periods_max = AZX_MAX_FRAG,
1603 .fifo_size = 0,
1604 };
1605
1606 static int azx_pcm_open(struct snd_pcm_substream *substream)
1607 {
1608 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1609 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1610 struct azx *chip = apcm->chip;
1611 struct azx_dev *azx_dev;
1612 struct snd_pcm_runtime *runtime = substream->runtime;
1613 unsigned long flags;
1614 int err;
1615 int buff_step;
1616
1617 mutex_lock(&chip->open_mutex);
1618 azx_dev = azx_assign_device(chip, substream);
1619 if (azx_dev == NULL) {
1620 mutex_unlock(&chip->open_mutex);
1621 return -EBUSY;
1622 }
1623 runtime->hw = azx_pcm_hw;
1624 runtime->hw.channels_min = hinfo->channels_min;
1625 runtime->hw.channels_max = hinfo->channels_max;
1626 runtime->hw.formats = hinfo->formats;
1627 runtime->hw.rates = hinfo->rates;
1628 snd_pcm_limit_hw_rates(runtime);
1629 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1630
1631 /* avoid wrap-around with wall-clock */
1632 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1633 20,
1634 178000000);
1635
1636 if (chip->align_buffer_size)
1637 /* constrain buffer sizes to be multiple of 128
1638 bytes. This is more efficient in terms of memory
1639 access but isn't required by the HDA spec and
1640 prevents users from specifying exact period/buffer
1641 sizes. For example for 44.1kHz, a period size set
1642 to 20ms will be rounded to 19.59ms. */
1643 buff_step = 128;
1644 else
1645 /* Don't enforce steps on buffer sizes, still need to
1646 be multiple of 4 bytes (HDA spec). Tested on Intel
1647 HDA controllers, may not work on all devices where
1648 option needs to be disabled */
1649 buff_step = 4;
1650
1651 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1652 buff_step);
1653 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1654 buff_step);
1655 snd_hda_power_up_d3wait(apcm->codec);
1656 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1657 if (err < 0) {
1658 azx_release_device(azx_dev);
1659 snd_hda_power_down(apcm->codec);
1660 mutex_unlock(&chip->open_mutex);
1661 return err;
1662 }
1663 snd_pcm_limit_hw_rates(runtime);
1664 /* sanity check */
1665 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1666 snd_BUG_ON(!runtime->hw.channels_max) ||
1667 snd_BUG_ON(!runtime->hw.formats) ||
1668 snd_BUG_ON(!runtime->hw.rates)) {
1669 azx_release_device(azx_dev);
1670 hinfo->ops.close(hinfo, apcm->codec, substream);
1671 snd_hda_power_down(apcm->codec);
1672 mutex_unlock(&chip->open_mutex);
1673 return -EINVAL;
1674 }
1675
1676 /* disable WALLCLOCK timestamps for capture streams
1677 until we figure out how to handle digital inputs */
1678 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1679 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1680
1681 spin_lock_irqsave(&chip->reg_lock, flags);
1682 azx_dev->substream = substream;
1683 azx_dev->running = 0;
1684 spin_unlock_irqrestore(&chip->reg_lock, flags);
1685
1686 runtime->private_data = azx_dev;
1687 snd_pcm_set_sync(substream);
1688 mutex_unlock(&chip->open_mutex);
1689 return 0;
1690 }
1691
1692 static int azx_pcm_close(struct snd_pcm_substream *substream)
1693 {
1694 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1695 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1696 struct azx *chip = apcm->chip;
1697 struct azx_dev *azx_dev = get_azx_dev(substream);
1698 unsigned long flags;
1699
1700 mutex_lock(&chip->open_mutex);
1701 spin_lock_irqsave(&chip->reg_lock, flags);
1702 azx_dev->substream = NULL;
1703 azx_dev->running = 0;
1704 spin_unlock_irqrestore(&chip->reg_lock, flags);
1705 azx_release_device(azx_dev);
1706 hinfo->ops.close(hinfo, apcm->codec, substream);
1707 snd_hda_power_down(apcm->codec);
1708 mutex_unlock(&chip->open_mutex);
1709 return 0;
1710 }
1711
1712 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1713 struct snd_pcm_hw_params *hw_params)
1714 {
1715 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1716 struct azx *chip = apcm->chip;
1717 struct azx_dev *azx_dev = get_azx_dev(substream);
1718 int ret;
1719
1720 dsp_lock(azx_dev);
1721 if (dsp_is_locked(azx_dev)) {
1722 ret = -EBUSY;
1723 goto unlock;
1724 }
1725
1726 mark_runtime_wc(chip, azx_dev, substream, false);
1727 azx_dev->bufsize = 0;
1728 azx_dev->period_bytes = 0;
1729 azx_dev->format_val = 0;
1730 ret = snd_pcm_lib_malloc_pages(substream,
1731 params_buffer_bytes(hw_params));
1732 if (ret < 0)
1733 goto unlock;
1734 mark_runtime_wc(chip, azx_dev, substream, true);
1735 unlock:
1736 dsp_unlock(azx_dev);
1737 return ret;
1738 }
1739
1740 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1741 {
1742 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1743 struct azx_dev *azx_dev = get_azx_dev(substream);
1744 struct azx *chip = apcm->chip;
1745 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1746
1747 /* reset BDL address */
1748 dsp_lock(azx_dev);
1749 if (!dsp_is_locked(azx_dev)) {
1750 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1751 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1752 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
1753 azx_dev->bufsize = 0;
1754 azx_dev->period_bytes = 0;
1755 azx_dev->format_val = 0;
1756 }
1757
1758 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1759
1760 mark_runtime_wc(chip, azx_dev, substream, false);
1761 azx_dev->prepared = 0;
1762 dsp_unlock(azx_dev);
1763 return snd_pcm_lib_free_pages(substream);
1764 }
1765
1766 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1767 {
1768 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1769 struct azx *chip = apcm->chip;
1770 struct azx_dev *azx_dev = get_azx_dev(substream);
1771 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1772 struct snd_pcm_runtime *runtime = substream->runtime;
1773 unsigned int bufsize, period_bytes, format_val, stream_tag;
1774 int err;
1775 struct hda_spdif_out *spdif =
1776 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1777 unsigned short ctls = spdif ? spdif->ctls : 0;
1778
1779 dsp_lock(azx_dev);
1780 if (dsp_is_locked(azx_dev)) {
1781 err = -EBUSY;
1782 goto unlock;
1783 }
1784
1785 azx_stream_reset(chip, azx_dev);
1786 format_val = snd_hda_calc_stream_format(runtime->rate,
1787 runtime->channels,
1788 runtime->format,
1789 hinfo->maxbps,
1790 ctls);
1791 if (!format_val) {
1792 dev_err(chip->card->dev,
1793 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1794 runtime->rate, runtime->channels, runtime->format);
1795 err = -EINVAL;
1796 goto unlock;
1797 }
1798
1799 bufsize = snd_pcm_lib_buffer_bytes(substream);
1800 period_bytes = snd_pcm_lib_period_bytes(substream);
1801
1802 dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1803 bufsize, format_val);
1804
1805 if (bufsize != azx_dev->bufsize ||
1806 period_bytes != azx_dev->period_bytes ||
1807 format_val != azx_dev->format_val ||
1808 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
1809 azx_dev->bufsize = bufsize;
1810 azx_dev->period_bytes = period_bytes;
1811 azx_dev->format_val = format_val;
1812 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
1813 err = azx_setup_periods(chip, substream, azx_dev);
1814 if (err < 0)
1815 goto unlock;
1816 }
1817
1818 /* when LPIB delay correction gives a small negative value,
1819 * we ignore it; currently set the threshold statically to
1820 * 64 frames
1821 */
1822 if (runtime->period_size > 64)
1823 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
1824 else
1825 azx_dev->delay_negative_threshold = 0;
1826
1827 /* wallclk has 24Mhz clock source */
1828 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1829 runtime->rate) * 1000);
1830 azx_setup_controller(chip, azx_dev);
1831 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1832 azx_dev->fifo_size =
1833 azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
1834 else
1835 azx_dev->fifo_size = 0;
1836
1837 stream_tag = azx_dev->stream_tag;
1838 /* CA-IBG chips need the playback stream starting from 1 */
1839 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1840 stream_tag > chip->capture_streams)
1841 stream_tag -= chip->capture_streams;
1842 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1843 azx_dev->format_val, substream);
1844
1845 unlock:
1846 if (!err)
1847 azx_dev->prepared = 1;
1848 dsp_unlock(azx_dev);
1849 return err;
1850 }
1851
1852 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1853 {
1854 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1855 struct azx *chip = apcm->chip;
1856 struct azx_dev *azx_dev;
1857 struct snd_pcm_substream *s;
1858 int rstart = 0, start, nsync = 0, sbits = 0;
1859 int nwait, timeout;
1860
1861 azx_dev = get_azx_dev(substream);
1862 trace_azx_pcm_trigger(chip, azx_dev, cmd);
1863
1864 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
1865 return -EPIPE;
1866
1867 switch (cmd) {
1868 case SNDRV_PCM_TRIGGER_START:
1869 rstart = 1;
1870 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1871 case SNDRV_PCM_TRIGGER_RESUME:
1872 start = 1;
1873 break;
1874 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1875 case SNDRV_PCM_TRIGGER_SUSPEND:
1876 case SNDRV_PCM_TRIGGER_STOP:
1877 start = 0;
1878 break;
1879 default:
1880 return -EINVAL;
1881 }
1882
1883 snd_pcm_group_for_each_entry(s, substream) {
1884 if (s->pcm->card != substream->pcm->card)
1885 continue;
1886 azx_dev = get_azx_dev(s);
1887 sbits |= 1 << azx_dev->index;
1888 nsync++;
1889 snd_pcm_trigger_done(s, substream);
1890 }
1891
1892 spin_lock(&chip->reg_lock);
1893
1894 /* first, set SYNC bits of corresponding streams */
1895 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1896 azx_writel(chip, OLD_SSYNC,
1897 azx_readl(chip, OLD_SSYNC) | sbits);
1898 else
1899 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1900
1901 snd_pcm_group_for_each_entry(s, substream) {
1902 if (s->pcm->card != substream->pcm->card)
1903 continue;
1904 azx_dev = get_azx_dev(s);
1905 if (start) {
1906 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1907 if (!rstart)
1908 azx_dev->start_wallclk -=
1909 azx_dev->period_wallclk;
1910 azx_stream_start(chip, azx_dev);
1911 } else {
1912 azx_stream_stop(chip, azx_dev);
1913 }
1914 azx_dev->running = start;
1915 }
1916 spin_unlock(&chip->reg_lock);
1917 if (start) {
1918 /* wait until all FIFOs get ready */
1919 for (timeout = 5000; timeout; timeout--) {
1920 nwait = 0;
1921 snd_pcm_group_for_each_entry(s, substream) {
1922 if (s->pcm->card != substream->pcm->card)
1923 continue;
1924 azx_dev = get_azx_dev(s);
1925 if (!(azx_sd_readb(chip, azx_dev, SD_STS) &
1926 SD_STS_FIFO_READY))
1927 nwait++;
1928 }
1929 if (!nwait)
1930 break;
1931 cpu_relax();
1932 }
1933 } else {
1934 /* wait until all RUN bits are cleared */
1935 for (timeout = 5000; timeout; timeout--) {
1936 nwait = 0;
1937 snd_pcm_group_for_each_entry(s, substream) {
1938 if (s->pcm->card != substream->pcm->card)
1939 continue;
1940 azx_dev = get_azx_dev(s);
1941 if (azx_sd_readb(chip, azx_dev, SD_CTL) &
1942 SD_CTL_DMA_START)
1943 nwait++;
1944 }
1945 if (!nwait)
1946 break;
1947 cpu_relax();
1948 }
1949 }
1950 spin_lock(&chip->reg_lock);
1951 /* reset SYNC bits */
1952 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1953 azx_writel(chip, OLD_SSYNC,
1954 azx_readl(chip, OLD_SSYNC) & ~sbits);
1955 else
1956 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1957 if (start) {
1958 azx_timecounter_init(substream, 0, 0);
1959 if (nsync > 1) {
1960 cycle_t cycle_last;
1961
1962 /* same start cycle for master and group */
1963 azx_dev = get_azx_dev(substream);
1964 cycle_last = azx_dev->azx_tc.cycle_last;
1965
1966 snd_pcm_group_for_each_entry(s, substream) {
1967 if (s->pcm->card != substream->pcm->card)
1968 continue;
1969 azx_timecounter_init(s, 1, cycle_last);
1970 }
1971 }
1972 }
1973 spin_unlock(&chip->reg_lock);
1974 return 0;
1975 }
1976
1977 /* get the current DMA position with correction on VIA chips */
1978 static unsigned int azx_via_get_position(struct azx *chip,
1979 struct azx_dev *azx_dev)
1980 {
1981 unsigned int link_pos, mini_pos, bound_pos;
1982 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1983 unsigned int fifo_size;
1984
1985 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
1986 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1987 /* Playback, no problem using link position */
1988 return link_pos;
1989 }
1990
1991 /* Capture */
1992 /* For new chipset,
1993 * use mod to get the DMA position just like old chipset
1994 */
1995 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1996 mod_dma_pos %= azx_dev->period_bytes;
1997
1998 /* azx_dev->fifo_size can't get FIFO size of in stream.
1999 * Get from base address + offset.
2000 */
2001 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2002
2003 if (azx_dev->insufficient) {
2004 /* Link position never gather than FIFO size */
2005 if (link_pos <= fifo_size)
2006 return 0;
2007
2008 azx_dev->insufficient = 0;
2009 }
2010
2011 if (link_pos <= fifo_size)
2012 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2013 else
2014 mini_pos = link_pos - fifo_size;
2015
2016 /* Find nearest previous boudary */
2017 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2018 mod_link_pos = link_pos % azx_dev->period_bytes;
2019 if (mod_link_pos >= fifo_size)
2020 bound_pos = link_pos - mod_link_pos;
2021 else if (mod_dma_pos >= mod_mini_pos)
2022 bound_pos = mini_pos - mod_mini_pos;
2023 else {
2024 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2025 if (bound_pos >= azx_dev->bufsize)
2026 bound_pos = 0;
2027 }
2028
2029 /* Calculate real DMA position we want */
2030 return bound_pos + mod_dma_pos;
2031 }
2032
2033 static unsigned int azx_get_position(struct azx *chip,
2034 struct azx_dev *azx_dev,
2035 bool with_check)
2036 {
2037 struct snd_pcm_substream *substream = azx_dev->substream;
2038 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2039 unsigned int pos;
2040 int stream = substream->stream;
2041 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2042 int delay = 0;
2043
2044 switch (chip->position_fix[stream]) {
2045 case POS_FIX_LPIB:
2046 /* read LPIB */
2047 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
2048 break;
2049 case POS_FIX_VIACOMBO:
2050 pos = azx_via_get_position(chip, azx_dev);
2051 break;
2052 default:
2053 /* use the position buffer */
2054 pos = le32_to_cpu(*azx_dev->posbuf);
2055 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2056 if (!pos || pos == (u32)-1) {
2057 dev_info(chip->card->dev,
2058 "Invalid position buffer, using LPIB read method instead.\n");
2059 chip->position_fix[stream] = POS_FIX_LPIB;
2060 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
2061 } else
2062 chip->position_fix[stream] = POS_FIX_POSBUF;
2063 }
2064 break;
2065 }
2066
2067 if (pos >= azx_dev->bufsize)
2068 pos = 0;
2069
2070 /* calculate runtime delay from LPIB */
2071 if (substream->runtime &&
2072 chip->position_fix[stream] == POS_FIX_POSBUF &&
2073 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2074 unsigned int lpib_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
2075 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2076 delay = pos - lpib_pos;
2077 else
2078 delay = lpib_pos - pos;
2079 if (delay < 0) {
2080 if (delay >= azx_dev->delay_negative_threshold)
2081 delay = 0;
2082 else
2083 delay += azx_dev->bufsize;
2084 }
2085 if (delay >= azx_dev->period_bytes) {
2086 dev_info(chip->card->dev,
2087 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
2088 delay, azx_dev->period_bytes);
2089 delay = 0;
2090 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2091 }
2092 delay = bytes_to_frames(substream->runtime, delay);
2093 }
2094
2095 if (substream->runtime) {
2096 if (hinfo->ops.get_delay)
2097 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2098 substream);
2099 substream->runtime->delay = delay;
2100 }
2101
2102 trace_azx_get_position(chip, azx_dev, pos, delay);
2103 return pos;
2104 }
2105
2106 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2107 {
2108 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2109 struct azx *chip = apcm->chip;
2110 struct azx_dev *azx_dev = get_azx_dev(substream);
2111 return bytes_to_frames(substream->runtime,
2112 azx_get_position(chip, azx_dev, false));
2113 }
2114
2115 /*
2116 * Check whether the current DMA position is acceptable for updating
2117 * periods. Returns non-zero if it's OK.
2118 *
2119 * Many HD-audio controllers appear pretty inaccurate about
2120 * the update-IRQ timing. The IRQ is issued before actually the
2121 * data is processed. So, we need to process it afterwords in a
2122 * workqueue.
2123 */
2124 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2125 {
2126 u32 wallclk;
2127 unsigned int pos;
2128
2129 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2130 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2131 return -1; /* bogus (too early) interrupt */
2132
2133 pos = azx_get_position(chip, azx_dev, true);
2134
2135 if (WARN_ONCE(!azx_dev->period_bytes,
2136 "hda-intel: zero azx_dev->period_bytes"))
2137 return -1; /* this shouldn't happen! */
2138 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2139 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2140 /* NG - it's below the first next period boundary */
2141 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
2142 azx_dev->start_wallclk += wallclk;
2143 return 1; /* OK, it's fine */
2144 }
2145
2146 /*
2147 * The work for pending PCM period updates.
2148 */
2149 static void azx_irq_pending_work(struct work_struct *work)
2150 {
2151 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2152 int i, pending, ok;
2153
2154 if (!chip->irq_pending_warned) {
2155 dev_info(chip->card->dev,
2156 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
2157 chip->card->number);
2158 chip->irq_pending_warned = 1;
2159 }
2160
2161 for (;;) {
2162 pending = 0;
2163 spin_lock_irq(&chip->reg_lock);
2164 for (i = 0; i < chip->num_streams; i++) {
2165 struct azx_dev *azx_dev = &chip->azx_dev[i];
2166 if (!azx_dev->irq_pending ||
2167 !azx_dev->substream ||
2168 !azx_dev->running)
2169 continue;
2170 ok = azx_position_ok(chip, azx_dev);
2171 if (ok > 0) {
2172 azx_dev->irq_pending = 0;
2173 spin_unlock(&chip->reg_lock);
2174 snd_pcm_period_elapsed(azx_dev->substream);
2175 spin_lock(&chip->reg_lock);
2176 } else if (ok < 0) {
2177 pending = 0; /* too early */
2178 } else
2179 pending++;
2180 }
2181 spin_unlock_irq(&chip->reg_lock);
2182 if (!pending)
2183 return;
2184 msleep(1);
2185 }
2186 }
2187
2188 /* clear irq_pending flags and assure no on-going workq */
2189 static void azx_clear_irq_pending(struct azx *chip)
2190 {
2191 int i;
2192
2193 spin_lock_irq(&chip->reg_lock);
2194 for (i = 0; i < chip->num_streams; i++)
2195 chip->azx_dev[i].irq_pending = 0;
2196 spin_unlock_irq(&chip->reg_lock);
2197 }
2198
2199 #ifdef CONFIG_X86
2200 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2201 struct vm_area_struct *area)
2202 {
2203 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2204 struct azx *chip = apcm->chip;
2205 if (!azx_snoop(chip))
2206 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2207 return snd_pcm_lib_default_mmap(substream, area);
2208 }
2209 #else
2210 #define azx_pcm_mmap NULL
2211 #endif
2212
2213 static struct snd_pcm_ops azx_pcm_ops = {
2214 .open = azx_pcm_open,
2215 .close = azx_pcm_close,
2216 .ioctl = snd_pcm_lib_ioctl,
2217 .hw_params = azx_pcm_hw_params,
2218 .hw_free = azx_pcm_hw_free,
2219 .prepare = azx_pcm_prepare,
2220 .trigger = azx_pcm_trigger,
2221 .pointer = azx_pcm_pointer,
2222 .wall_clock = azx_get_wallclock_tstamp,
2223 .mmap = azx_pcm_mmap,
2224 .page = snd_pcm_sgbuf_ops_page,
2225 };
2226
2227 static void azx_pcm_free(struct snd_pcm *pcm)
2228 {
2229 struct azx_pcm *apcm = pcm->private_data;
2230 if (apcm) {
2231 list_del(&apcm->list);
2232 kfree(apcm);
2233 }
2234 }
2235
2236 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2237
2238 static int
2239 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2240 struct hda_pcm *cpcm)
2241 {
2242 struct azx *chip = bus->private_data;
2243 struct snd_pcm *pcm;
2244 struct azx_pcm *apcm;
2245 int pcm_dev = cpcm->device;
2246 unsigned int size;
2247 int s, err;
2248
2249 list_for_each_entry(apcm, &chip->pcm_list, list) {
2250 if (apcm->pcm->device == pcm_dev) {
2251 dev_err(chip->card->dev, "PCM %d already exists\n",
2252 pcm_dev);
2253 return -EBUSY;
2254 }
2255 }
2256 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2257 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2258 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2259 &pcm);
2260 if (err < 0)
2261 return err;
2262 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2263 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2264 if (apcm == NULL)
2265 return -ENOMEM;
2266 apcm->chip = chip;
2267 apcm->pcm = pcm;
2268 apcm->codec = codec;
2269 pcm->private_data = apcm;
2270 pcm->private_free = azx_pcm_free;
2271 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2272 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2273 list_add_tail(&apcm->list, &chip->pcm_list);
2274 cpcm->pcm = pcm;
2275 for (s = 0; s < 2; s++) {
2276 apcm->hinfo[s] = &cpcm->stream[s];
2277 if (cpcm->stream[s].substreams)
2278 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2279 }
2280 /* buffer pre-allocation */
2281 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2282 if (size > MAX_PREALLOC_SIZE)
2283 size = MAX_PREALLOC_SIZE;
2284 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2285 chip->card->dev,
2286 size, MAX_PREALLOC_SIZE);
2287 /* link to codec */
2288 pcm->dev = &codec->dev;
2289 return 0;
2290 }
2291
2292 /*
2293 * mixer creation - all stuff is implemented in hda module
2294 */
2295 static int azx_mixer_create(struct azx *chip)
2296 {
2297 return snd_hda_build_controls(chip->bus);
2298 }
2299
2300
2301 /*
2302 * initialize SD streams
2303 */
2304 static int azx_init_stream(struct azx *chip)
2305 {
2306 int i;
2307
2308 /* initialize each stream (aka device)
2309 * assign the starting bdl address to each stream (device)
2310 * and initialize
2311 */
2312 for (i = 0; i < chip->num_streams; i++) {
2313 struct azx_dev *azx_dev = &chip->azx_dev[i];
2314 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2315 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2316 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2317 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2318 azx_dev->sd_int_sta_mask = 1 << i;
2319 /* stream tag: must be non-zero and unique */
2320 azx_dev->index = i;
2321 azx_dev->stream_tag = i + 1;
2322 }
2323
2324 return 0;
2325 }
2326
2327 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2328 {
2329 if (request_irq(chip->pci->irq, azx_interrupt,
2330 chip->msi ? 0 : IRQF_SHARED,
2331 KBUILD_MODNAME, chip)) {
2332 dev_err(chip->card->dev,
2333 "unable to grab IRQ %d, disabling device\n",
2334 chip->pci->irq);
2335 if (do_disconnect)
2336 snd_card_disconnect(chip->card);
2337 return -1;
2338 }
2339 chip->irq = chip->pci->irq;
2340 pci_intx(chip->pci, !chip->msi);
2341 return 0;
2342 }
2343
2344
2345 static void azx_stop_chip(struct azx *chip)
2346 {
2347 if (!chip->initialized)
2348 return;
2349
2350 /* disable interrupts */
2351 azx_int_disable(chip);
2352 azx_int_clear(chip);
2353
2354 /* disable CORB/RIRB */
2355 azx_free_cmd_io(chip);
2356
2357 /* disable position buffer */
2358 azx_writel(chip, DPLBASE, 0);
2359 azx_writel(chip, DPUBASE, 0);
2360
2361 chip->initialized = 0;
2362 }
2363
2364 #ifdef CONFIG_SND_HDA_DSP_LOADER
2365 /*
2366 * DSP loading code (e.g. for CA0132)
2367 */
2368
2369 /* use the first stream for loading DSP */
2370 static struct azx_dev *
2371 azx_get_dsp_loader_dev(struct azx *chip)
2372 {
2373 return &chip->azx_dev[chip->playback_index_offset];
2374 }
2375
2376 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2377 unsigned int byte_size,
2378 struct snd_dma_buffer *bufp)
2379 {
2380 u32 *bdl;
2381 struct azx *chip = bus->private_data;
2382 struct azx_dev *azx_dev;
2383 int err;
2384
2385 azx_dev = azx_get_dsp_loader_dev(chip);
2386
2387 dsp_lock(azx_dev);
2388 spin_lock_irq(&chip->reg_lock);
2389 if (azx_dev->running || azx_dev->locked) {
2390 spin_unlock_irq(&chip->reg_lock);
2391 err = -EBUSY;
2392 goto unlock;
2393 }
2394 azx_dev->prepared = 0;
2395 chip->saved_azx_dev = *azx_dev;
2396 azx_dev->locked = 1;
2397 spin_unlock_irq(&chip->reg_lock);
2398
2399 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2400 chip->card->dev,
2401 byte_size, bufp);
2402 if (err < 0)
2403 goto err_alloc;
2404
2405 mark_pages_wc(chip, bufp, true);
2406 azx_dev->bufsize = byte_size;
2407 azx_dev->period_bytes = byte_size;
2408 azx_dev->format_val = format;
2409
2410 azx_stream_reset(chip, azx_dev);
2411
2412 /* reset BDL address */
2413 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
2414 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
2415
2416 azx_dev->frags = 0;
2417 bdl = (u32 *)azx_dev->bdl.area;
2418 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2419 if (err < 0)
2420 goto error;
2421
2422 azx_setup_controller(chip, azx_dev);
2423 dsp_unlock(azx_dev);
2424 return azx_dev->stream_tag;
2425
2426 error:
2427 mark_pages_wc(chip, bufp, false);
2428 snd_dma_free_pages(bufp);
2429 err_alloc:
2430 spin_lock_irq(&chip->reg_lock);
2431 if (azx_dev->opened)
2432 *azx_dev = chip->saved_azx_dev;
2433 azx_dev->locked = 0;
2434 spin_unlock_irq(&chip->reg_lock);
2435 unlock:
2436 dsp_unlock(azx_dev);
2437 return err;
2438 }
2439
2440 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2441 {
2442 struct azx *chip = bus->private_data;
2443 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2444
2445 if (start)
2446 azx_stream_start(chip, azx_dev);
2447 else
2448 azx_stream_stop(chip, azx_dev);
2449 azx_dev->running = start;
2450 }
2451
2452 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2453 struct snd_dma_buffer *dmab)
2454 {
2455 struct azx *chip = bus->private_data;
2456 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2457
2458 if (!dmab->area || !azx_dev->locked)
2459 return;
2460
2461 dsp_lock(azx_dev);
2462 /* reset BDL address */
2463 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
2464 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
2465 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
2466 azx_dev->bufsize = 0;
2467 azx_dev->period_bytes = 0;
2468 azx_dev->format_val = 0;
2469
2470 mark_pages_wc(chip, dmab, false);
2471 snd_dma_free_pages(dmab);
2472 dmab->area = NULL;
2473
2474 spin_lock_irq(&chip->reg_lock);
2475 if (azx_dev->opened)
2476 *azx_dev = chip->saved_azx_dev;
2477 azx_dev->locked = 0;
2478 spin_unlock_irq(&chip->reg_lock);
2479 dsp_unlock(azx_dev);
2480 }
2481 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2482
2483 #ifdef CONFIG_PM
2484 /* power-up/down the controller */
2485 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2486 {
2487 struct azx *chip = bus->private_data;
2488
2489 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2490 return;
2491
2492 if (power_up)
2493 pm_runtime_get_sync(chip->card->dev);
2494 else
2495 pm_runtime_put_sync(chip->card->dev);
2496 }
2497
2498 static DEFINE_MUTEX(card_list_lock);
2499 static LIST_HEAD(card_list);
2500
2501 static void azx_add_card_list(struct azx *chip)
2502 {
2503 mutex_lock(&card_list_lock);
2504 list_add(&chip->list, &card_list);
2505 mutex_unlock(&card_list_lock);
2506 }
2507
2508 static void azx_del_card_list(struct azx *chip)
2509 {
2510 mutex_lock(&card_list_lock);
2511 list_del_init(&chip->list);
2512 mutex_unlock(&card_list_lock);
2513 }
2514
2515 /* trigger power-save check at writing parameter */
2516 static int param_set_xint(const char *val, const struct kernel_param *kp)
2517 {
2518 struct azx *chip;
2519 struct hda_codec *c;
2520 int prev = power_save;
2521 int ret = param_set_int(val, kp);
2522
2523 if (ret || prev == power_save)
2524 return ret;
2525
2526 mutex_lock(&card_list_lock);
2527 list_for_each_entry(chip, &card_list, list) {
2528 if (!chip->bus || chip->disabled)
2529 continue;
2530 list_for_each_entry(c, &chip->bus->codec_list, list)
2531 snd_hda_power_sync(c);
2532 }
2533 mutex_unlock(&card_list_lock);
2534 return 0;
2535 }
2536 #else
2537 #define azx_add_card_list(chip) /* NOP */
2538 #define azx_del_card_list(chip) /* NOP */
2539 #endif /* CONFIG_PM */
2540
2541 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2542 /*
2543 * power management
2544 */
2545 static int azx_suspend(struct device *dev)
2546 {
2547 struct pci_dev *pci = to_pci_dev(dev);
2548 struct snd_card *card = dev_get_drvdata(dev);
2549 struct azx *chip = card->private_data;
2550 struct azx_pcm *p;
2551
2552 if (chip->disabled)
2553 return 0;
2554
2555 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2556 azx_clear_irq_pending(chip);
2557 list_for_each_entry(p, &chip->pcm_list, list)
2558 snd_pcm_suspend_all(p->pcm);
2559 if (chip->initialized)
2560 snd_hda_suspend(chip->bus);
2561 azx_stop_chip(chip);
2562 azx_enter_link_reset(chip);
2563 if (chip->irq >= 0) {
2564 free_irq(chip->irq, chip);
2565 chip->irq = -1;
2566 }
2567 if (chip->msi)
2568 pci_disable_msi(chip->pci);
2569 pci_disable_device(pci);
2570 pci_save_state(pci);
2571 pci_set_power_state(pci, PCI_D3hot);
2572 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2573 hda_display_power(false);
2574 return 0;
2575 }
2576
2577 static int azx_resume(struct device *dev)
2578 {
2579 struct pci_dev *pci = to_pci_dev(dev);
2580 struct snd_card *card = dev_get_drvdata(dev);
2581 struct azx *chip = card->private_data;
2582
2583 if (chip->disabled)
2584 return 0;
2585
2586 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2587 hda_display_power(true);
2588 pci_set_power_state(pci, PCI_D0);
2589 pci_restore_state(pci);
2590 if (pci_enable_device(pci) < 0) {
2591 dev_err(chip->card->dev,
2592 "pci_enable_device failed, disabling device\n");
2593 snd_card_disconnect(card);
2594 return -EIO;
2595 }
2596 pci_set_master(pci);
2597 if (chip->msi)
2598 if (pci_enable_msi(pci) < 0)
2599 chip->msi = 0;
2600 if (azx_acquire_irq(chip, 1) < 0)
2601 return -EIO;
2602 azx_init_pci(chip);
2603
2604 azx_init_chip(chip, 1);
2605
2606 snd_hda_resume(chip->bus);
2607 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2608 return 0;
2609 }
2610 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2611
2612 #ifdef CONFIG_PM_RUNTIME
2613 static int azx_runtime_suspend(struct device *dev)
2614 {
2615 struct snd_card *card = dev_get_drvdata(dev);
2616 struct azx *chip = card->private_data;
2617
2618 if (chip->disabled)
2619 return 0;
2620
2621 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2622 return 0;
2623
2624 /* enable controller wake up event */
2625 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
2626 STATESTS_INT_MASK);
2627
2628 azx_stop_chip(chip);
2629 azx_enter_link_reset(chip);
2630 azx_clear_irq_pending(chip);
2631 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2632 hda_display_power(false);
2633 return 0;
2634 }
2635
2636 static int azx_runtime_resume(struct device *dev)
2637 {
2638 struct snd_card *card = dev_get_drvdata(dev);
2639 struct azx *chip = card->private_data;
2640 struct hda_bus *bus;
2641 struct hda_codec *codec;
2642 int status;
2643
2644 if (chip->disabled)
2645 return 0;
2646
2647 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2648 return 0;
2649
2650 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2651 hda_display_power(true);
2652
2653 /* Read STATESTS before controller reset */
2654 status = azx_readw(chip, STATESTS);
2655
2656 azx_init_pci(chip);
2657 azx_init_chip(chip, 1);
2658
2659 bus = chip->bus;
2660 if (status && bus) {
2661 list_for_each_entry(codec, &bus->codec_list, list)
2662 if (status & (1 << codec->addr))
2663 queue_delayed_work(codec->bus->workq,
2664 &codec->jackpoll_work, codec->jackpoll_interval);
2665 }
2666
2667 /* disable controller Wake Up event*/
2668 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
2669 ~STATESTS_INT_MASK);
2670
2671 return 0;
2672 }
2673
2674 static int azx_runtime_idle(struct device *dev)
2675 {
2676 struct snd_card *card = dev_get_drvdata(dev);
2677 struct azx *chip = card->private_data;
2678
2679 if (chip->disabled)
2680 return 0;
2681
2682 if (!power_save_controller ||
2683 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2684 return -EBUSY;
2685
2686 return 0;
2687 }
2688
2689 #endif /* CONFIG_PM_RUNTIME */
2690
2691 #ifdef CONFIG_PM
2692 static const struct dev_pm_ops azx_pm = {
2693 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2694 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
2695 };
2696
2697 #define AZX_PM_OPS &azx_pm
2698 #else
2699 #define AZX_PM_OPS NULL
2700 #endif /* CONFIG_PM */
2701
2702
2703 /*
2704 * reboot notifier for hang-up problem at power-down
2705 */
2706 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2707 {
2708 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2709 snd_hda_bus_reboot_notify(chip->bus);
2710 azx_stop_chip(chip);
2711 return NOTIFY_OK;
2712 }
2713
2714 static void azx_notifier_register(struct azx *chip)
2715 {
2716 chip->reboot_notifier.notifier_call = azx_halt;
2717 register_reboot_notifier(&chip->reboot_notifier);
2718 }
2719
2720 static void azx_notifier_unregister(struct azx *chip)
2721 {
2722 if (chip->reboot_notifier.notifier_call)
2723 unregister_reboot_notifier(&chip->reboot_notifier);
2724 }
2725
2726 static int azx_probe_continue(struct azx *chip);
2727
2728 #ifdef SUPPORT_VGA_SWITCHEROO
2729 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
2730
2731 static void azx_vs_set_state(struct pci_dev *pci,
2732 enum vga_switcheroo_state state)
2733 {
2734 struct snd_card *card = pci_get_drvdata(pci);
2735 struct azx *chip = card->private_data;
2736 bool disabled;
2737
2738 wait_for_completion(&chip->probe_wait);
2739 if (chip->init_failed)
2740 return;
2741
2742 disabled = (state == VGA_SWITCHEROO_OFF);
2743 if (chip->disabled == disabled)
2744 return;
2745
2746 if (!chip->bus) {
2747 chip->disabled = disabled;
2748 if (!disabled) {
2749 dev_info(chip->card->dev,
2750 "Start delayed initialization\n");
2751 if (azx_probe_continue(chip) < 0) {
2752 dev_err(chip->card->dev, "initialization error\n");
2753 chip->init_failed = true;
2754 }
2755 }
2756 } else {
2757 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
2758 disabled ? "Disabling" : "Enabling");
2759 if (disabled) {
2760 pm_runtime_put_sync_suspend(card->dev);
2761 azx_suspend(card->dev);
2762 /* when we get suspended by vga switcheroo we end up in D3cold,
2763 * however we have no ACPI handle, so pci/acpi can't put us there,
2764 * put ourselves there */
2765 pci->current_state = PCI_D3cold;
2766 chip->disabled = true;
2767 if (snd_hda_lock_devices(chip->bus))
2768 dev_warn(chip->card->dev,
2769 "Cannot lock devices!\n");
2770 } else {
2771 snd_hda_unlock_devices(chip->bus);
2772 pm_runtime_get_noresume(card->dev);
2773 chip->disabled = false;
2774 azx_resume(card->dev);
2775 }
2776 }
2777 }
2778
2779 static bool azx_vs_can_switch(struct pci_dev *pci)
2780 {
2781 struct snd_card *card = pci_get_drvdata(pci);
2782 struct azx *chip = card->private_data;
2783
2784 wait_for_completion(&chip->probe_wait);
2785 if (chip->init_failed)
2786 return false;
2787 if (chip->disabled || !chip->bus)
2788 return true;
2789 if (snd_hda_lock_devices(chip->bus))
2790 return false;
2791 snd_hda_unlock_devices(chip->bus);
2792 return true;
2793 }
2794
2795 static void init_vga_switcheroo(struct azx *chip)
2796 {
2797 struct pci_dev *p = get_bound_vga(chip->pci);
2798 if (p) {
2799 dev_info(chip->card->dev,
2800 "Handle VGA-switcheroo audio client\n");
2801 chip->use_vga_switcheroo = 1;
2802 pci_dev_put(p);
2803 }
2804 }
2805
2806 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2807 .set_gpu_state = azx_vs_set_state,
2808 .can_switch = azx_vs_can_switch,
2809 };
2810
2811 static int register_vga_switcheroo(struct azx *chip)
2812 {
2813 int err;
2814
2815 if (!chip->use_vga_switcheroo)
2816 return 0;
2817 /* FIXME: currently only handling DIS controller
2818 * is there any machine with two switchable HDMI audio controllers?
2819 */
2820 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2821 VGA_SWITCHEROO_DIS,
2822 chip->bus != NULL);
2823 if (err < 0)
2824 return err;
2825 chip->vga_switcheroo_registered = 1;
2826
2827 /* register as an optimus hdmi audio power domain */
2828 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
2829 &chip->hdmi_pm_domain);
2830 return 0;
2831 }
2832 #else
2833 #define init_vga_switcheroo(chip) /* NOP */
2834 #define register_vga_switcheroo(chip) 0
2835 #define check_hdmi_disabled(pci) false
2836 #endif /* SUPPORT_VGA_SWITCHER */
2837
2838 /*
2839 * destructor
2840 */
2841 static int azx_free(struct azx *chip)
2842 {
2843 struct pci_dev *pci = chip->pci;
2844 int i;
2845
2846 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
2847 && chip->running)
2848 pm_runtime_get_noresume(&pci->dev);
2849
2850 azx_del_card_list(chip);
2851
2852 azx_notifier_unregister(chip);
2853
2854 chip->init_failed = 1; /* to be sure */
2855 complete_all(&chip->probe_wait);
2856
2857 if (use_vga_switcheroo(chip)) {
2858 if (chip->disabled && chip->bus)
2859 snd_hda_unlock_devices(chip->bus);
2860 if (chip->vga_switcheroo_registered)
2861 vga_switcheroo_unregister_client(chip->pci);
2862 }
2863
2864 if (chip->initialized) {
2865 azx_clear_irq_pending(chip);
2866 for (i = 0; i < chip->num_streams; i++)
2867 azx_stream_stop(chip, &chip->azx_dev[i]);
2868 azx_stop_chip(chip);
2869 }
2870
2871 if (chip->irq >= 0)
2872 free_irq(chip->irq, (void*)chip);
2873 if (chip->msi)
2874 pci_disable_msi(chip->pci);
2875 if (chip->remap_addr)
2876 iounmap(chip->remap_addr);
2877
2878 if (chip->azx_dev) {
2879 for (i = 0; i < chip->num_streams; i++)
2880 if (chip->azx_dev[i].bdl.area) {
2881 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2882 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2883 }
2884 }
2885 if (chip->rb.area) {
2886 mark_pages_wc(chip, &chip->rb, false);
2887 snd_dma_free_pages(&chip->rb);
2888 }
2889 if (chip->posbuf.area) {
2890 mark_pages_wc(chip, &chip->posbuf, false);
2891 snd_dma_free_pages(&chip->posbuf);
2892 }
2893 if (chip->region_requested)
2894 pci_release_regions(chip->pci);
2895 pci_disable_device(chip->pci);
2896 kfree(chip->azx_dev);
2897 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2898 if (chip->fw)
2899 release_firmware(chip->fw);
2900 #endif
2901 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2902 hda_display_power(false);
2903 hda_i915_exit();
2904 }
2905 kfree(chip);
2906
2907 return 0;
2908 }
2909
2910 static int azx_dev_free(struct snd_device *device)
2911 {
2912 return azx_free(device->device_data);
2913 }
2914
2915 #ifdef SUPPORT_VGA_SWITCHEROO
2916 /*
2917 * Check of disabled HDMI controller by vga-switcheroo
2918 */
2919 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
2920 {
2921 struct pci_dev *p;
2922
2923 /* check only discrete GPU */
2924 switch (pci->vendor) {
2925 case PCI_VENDOR_ID_ATI:
2926 case PCI_VENDOR_ID_AMD:
2927 case PCI_VENDOR_ID_NVIDIA:
2928 if (pci->devfn == 1) {
2929 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2930 pci->bus->number, 0);
2931 if (p) {
2932 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2933 return p;
2934 pci_dev_put(p);
2935 }
2936 }
2937 break;
2938 }
2939 return NULL;
2940 }
2941
2942 static bool check_hdmi_disabled(struct pci_dev *pci)
2943 {
2944 bool vga_inactive = false;
2945 struct pci_dev *p = get_bound_vga(pci);
2946
2947 if (p) {
2948 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2949 vga_inactive = true;
2950 pci_dev_put(p);
2951 }
2952 return vga_inactive;
2953 }
2954 #endif /* SUPPORT_VGA_SWITCHEROO */
2955
2956 /*
2957 * white/black-listing for position_fix
2958 */
2959 static struct snd_pci_quirk position_fix_list[] = {
2960 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2961 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2962 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2963 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2964 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2965 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2966 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2967 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2968 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2969 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2970 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2971 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2972 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2973 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2974 {}
2975 };
2976
2977 static int check_position_fix(struct azx *chip, int fix)
2978 {
2979 const struct snd_pci_quirk *q;
2980
2981 switch (fix) {
2982 case POS_FIX_AUTO:
2983 case POS_FIX_LPIB:
2984 case POS_FIX_POSBUF:
2985 case POS_FIX_VIACOMBO:
2986 case POS_FIX_COMBO:
2987 return fix;
2988 }
2989
2990 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2991 if (q) {
2992 dev_info(chip->card->dev,
2993 "position_fix set to %d for device %04x:%04x\n",
2994 q->value, q->subvendor, q->subdevice);
2995 return q->value;
2996 }
2997
2998 /* Check VIA/ATI HD Audio Controller exist */
2999 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3000 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
3001 return POS_FIX_VIACOMBO;
3002 }
3003 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3004 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
3005 return POS_FIX_LPIB;
3006 }
3007 return POS_FIX_AUTO;
3008 }
3009
3010 /*
3011 * black-lists for probe_mask
3012 */
3013 static struct snd_pci_quirk probe_mask_list[] = {
3014 /* Thinkpad often breaks the controller communication when accessing
3015 * to the non-working (or non-existing) modem codec slot.
3016 */
3017 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3018 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3019 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3020 /* broken BIOS */
3021 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3022 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3023 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3024 /* forced codec slots */
3025 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3026 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3027 /* WinFast VP200 H (Teradici) user reported broken communication */
3028 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3029 {}
3030 };
3031
3032 #define AZX_FORCE_CODEC_MASK 0x100
3033
3034 static void check_probe_mask(struct azx *chip, int dev)
3035 {
3036 const struct snd_pci_quirk *q;
3037
3038 chip->codec_probe_mask = probe_mask[dev];
3039 if (chip->codec_probe_mask == -1) {
3040 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3041 if (q) {
3042 dev_info(chip->card->dev,
3043 "probe_mask set to 0x%x for device %04x:%04x\n",
3044 q->value, q->subvendor, q->subdevice);
3045 chip->codec_probe_mask = q->value;
3046 }
3047 }
3048
3049 /* check forced option */
3050 if (chip->codec_probe_mask != -1 &&
3051 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3052 chip->codec_mask = chip->codec_probe_mask & 0xff;
3053 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
3054 chip->codec_mask);
3055 }
3056 }
3057
3058 /*
3059 * white/black-list for enable_msi
3060 */
3061 static struct snd_pci_quirk msi_black_list[] = {
3062 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
3063 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
3064 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
3065 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
3066 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3067 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3068 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3069 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
3070 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3071 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3072 {}
3073 };
3074
3075 static void check_msi(struct azx *chip)
3076 {
3077 const struct snd_pci_quirk *q;
3078
3079 if (enable_msi >= 0) {
3080 chip->msi = !!enable_msi;
3081 return;
3082 }
3083 chip->msi = 1; /* enable MSI as default */
3084 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3085 if (q) {
3086 dev_info(chip->card->dev,
3087 "msi for device %04x:%04x set to %d\n",
3088 q->subvendor, q->subdevice, q->value);
3089 chip->msi = q->value;
3090 return;
3091 }
3092
3093 /* NVidia chipsets seem to cause troubles with MSI */
3094 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3095 dev_info(chip->card->dev, "Disabling MSI\n");
3096 chip->msi = 0;
3097 }
3098 }
3099
3100 /* check the snoop mode availability */
3101 static void azx_check_snoop_available(struct azx *chip)
3102 {
3103 bool snoop = chip->snoop;
3104
3105 switch (chip->driver_type) {
3106 case AZX_DRIVER_VIA:
3107 /* force to non-snoop mode for a new VIA controller
3108 * when BIOS is set
3109 */
3110 if (snoop) {
3111 u8 val;
3112 pci_read_config_byte(chip->pci, 0x42, &val);
3113 if (!(val & 0x80) && chip->pci->revision == 0x30)
3114 snoop = false;
3115 }
3116 break;
3117 case AZX_DRIVER_ATIHDMI_NS:
3118 /* new ATI HDMI requires non-snoop */
3119 snoop = false;
3120 break;
3121 case AZX_DRIVER_CTHDA:
3122 snoop = false;
3123 break;
3124 }
3125
3126 if (snoop != chip->snoop) {
3127 dev_info(chip->card->dev, "Force to %s mode\n",
3128 snoop ? "snoop" : "non-snoop");
3129 chip->snoop = snoop;
3130 }
3131 }
3132
3133 static void azx_probe_work(struct work_struct *work)
3134 {
3135 azx_probe_continue(container_of(work, struct azx, probe_work));
3136 }
3137
3138 /*
3139 * constructor
3140 */
3141 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3142 int dev, unsigned int driver_caps,
3143 const struct hda_controller_ops *hda_ops,
3144 struct azx **rchip)
3145 {
3146 static struct snd_device_ops ops = {
3147 .dev_free = azx_dev_free,
3148 };
3149 struct azx *chip;
3150 int err;
3151
3152 *rchip = NULL;
3153
3154 err = pci_enable_device(pci);
3155 if (err < 0)
3156 return err;
3157
3158 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3159 if (!chip) {
3160 dev_err(card->dev, "Cannot allocate chip\n");
3161 pci_disable_device(pci);
3162 return -ENOMEM;
3163 }
3164
3165 spin_lock_init(&chip->reg_lock);
3166 mutex_init(&chip->open_mutex);
3167 chip->card = card;
3168 chip->pci = pci;
3169 chip->ops = hda_ops;
3170 chip->irq = -1;
3171 chip->driver_caps = driver_caps;
3172 chip->driver_type = driver_caps & 0xff;
3173 check_msi(chip);
3174 chip->dev_index = dev;
3175 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3176 INIT_LIST_HEAD(&chip->pcm_list);
3177 INIT_LIST_HEAD(&chip->list);
3178 init_vga_switcheroo(chip);
3179 init_completion(&chip->probe_wait);
3180
3181 chip->position_fix[0] = chip->position_fix[1] =
3182 check_position_fix(chip, position_fix[dev]);
3183 /* combo mode uses LPIB for playback */
3184 if (chip->position_fix[0] == POS_FIX_COMBO) {
3185 chip->position_fix[0] = POS_FIX_LPIB;
3186 chip->position_fix[1] = POS_FIX_AUTO;
3187 }
3188
3189 check_probe_mask(chip, dev);
3190
3191 chip->single_cmd = single_cmd;
3192 chip->snoop = hda_snoop;
3193 azx_check_snoop_available(chip);
3194
3195 if (bdl_pos_adj[dev] < 0) {
3196 switch (chip->driver_type) {
3197 case AZX_DRIVER_ICH:
3198 case AZX_DRIVER_PCH:
3199 bdl_pos_adj[dev] = 1;
3200 break;
3201 default:
3202 bdl_pos_adj[dev] = 32;
3203 break;
3204 }
3205 }
3206 chip->bdl_pos_adj = bdl_pos_adj;
3207
3208 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3209 if (err < 0) {
3210 dev_err(card->dev, "Error creating device [card]!\n");
3211 azx_free(chip);
3212 return err;
3213 }
3214
3215 /* continue probing in work context as may trigger request module */
3216 INIT_WORK(&chip->probe_work, azx_probe_work);
3217
3218 *rchip = chip;
3219
3220 return 0;
3221 }
3222
3223 static int azx_first_init(struct azx *chip)
3224 {
3225 int dev = chip->dev_index;
3226 struct pci_dev *pci = chip->pci;
3227 struct snd_card *card = chip->card;
3228 int i, err;
3229 unsigned short gcap;
3230
3231 #if BITS_PER_LONG != 64
3232 /* Fix up base address on ULI M5461 */
3233 if (chip->driver_type == AZX_DRIVER_ULI) {
3234 u16 tmp3;
3235 pci_read_config_word(pci, 0x40, &tmp3);
3236 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3237 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3238 }
3239 #endif
3240
3241 err = pci_request_regions(pci, "ICH HD audio");
3242 if (err < 0)
3243 return err;
3244 chip->region_requested = 1;
3245
3246 chip->addr = pci_resource_start(pci, 0);
3247 chip->remap_addr = pci_ioremap_bar(pci, 0);
3248 if (chip->remap_addr == NULL) {
3249 dev_err(card->dev, "ioremap error\n");
3250 return -ENXIO;
3251 }
3252
3253 if (chip->msi)
3254 if (pci_enable_msi(pci) < 0)
3255 chip->msi = 0;
3256
3257 if (azx_acquire_irq(chip, 0) < 0)
3258 return -EBUSY;
3259
3260 pci_set_master(pci);
3261 synchronize_irq(chip->irq);
3262
3263 gcap = azx_readw(chip, GCAP);
3264 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
3265
3266 /* disable SB600 64bit support for safety */
3267 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3268 struct pci_dev *p_smbus;
3269 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3270 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3271 NULL);
3272 if (p_smbus) {
3273 if (p_smbus->revision < 0x30)
3274 gcap &= ~ICH6_GCAP_64OK;
3275 pci_dev_put(p_smbus);
3276 }
3277 }
3278
3279 /* disable 64bit DMA address on some devices */
3280 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3281 dev_dbg(card->dev, "Disabling 64bit DMA\n");
3282 gcap &= ~ICH6_GCAP_64OK;
3283 }
3284
3285 /* disable buffer size rounding to 128-byte multiples if supported */
3286 if (align_buffer_size >= 0)
3287 chip->align_buffer_size = !!align_buffer_size;
3288 else {
3289 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3290 chip->align_buffer_size = 0;
3291 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3292 chip->align_buffer_size = 1;
3293 else
3294 chip->align_buffer_size = 1;
3295 }
3296
3297 /* allow 64bit DMA address if supported by H/W */
3298 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3299 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3300 else {
3301 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3302 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3303 }
3304
3305 /* read number of streams from GCAP register instead of using
3306 * hardcoded value
3307 */
3308 chip->capture_streams = (gcap >> 8) & 0x0f;
3309 chip->playback_streams = (gcap >> 12) & 0x0f;
3310 if (!chip->playback_streams && !chip->capture_streams) {
3311 /* gcap didn't give any info, switching to old method */
3312
3313 switch (chip->driver_type) {
3314 case AZX_DRIVER_ULI:
3315 chip->playback_streams = ULI_NUM_PLAYBACK;
3316 chip->capture_streams = ULI_NUM_CAPTURE;
3317 break;
3318 case AZX_DRIVER_ATIHDMI:
3319 case AZX_DRIVER_ATIHDMI_NS:
3320 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3321 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3322 break;
3323 case AZX_DRIVER_GENERIC:
3324 default:
3325 chip->playback_streams = ICH6_NUM_PLAYBACK;
3326 chip->capture_streams = ICH6_NUM_CAPTURE;
3327 break;
3328 }
3329 }
3330 chip->capture_index_offset = 0;
3331 chip->playback_index_offset = chip->capture_streams;
3332 chip->num_streams = chip->playback_streams + chip->capture_streams;
3333 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3334 GFP_KERNEL);
3335 if (!chip->azx_dev) {
3336 dev_err(card->dev, "cannot malloc azx_dev\n");
3337 return -ENOMEM;
3338 }
3339
3340 for (i = 0; i < chip->num_streams; i++) {
3341 dsp_lock_init(&chip->azx_dev[i]);
3342 /* allocate memory for the BDL for each stream */
3343 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3344 chip->card->dev,
3345 BDL_SIZE, &chip->azx_dev[i].bdl);
3346 if (err < 0) {
3347 dev_err(card->dev, "cannot allocate BDL\n");
3348 return -ENOMEM;
3349 }
3350 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3351 }
3352 /* allocate memory for the position buffer */
3353 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3354 chip->card->dev,
3355 chip->num_streams * 8, &chip->posbuf);
3356 if (err < 0) {
3357 dev_err(card->dev, "cannot allocate posbuf\n");
3358 return -ENOMEM;
3359 }
3360 mark_pages_wc(chip, &chip->posbuf, true);
3361 /* allocate CORB/RIRB */
3362 err = azx_alloc_cmd_io(chip);
3363 if (err < 0)
3364 return err;
3365
3366 /* initialize streams */
3367 azx_init_stream(chip);
3368
3369 /* initialize chip */
3370 azx_init_pci(chip);
3371 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3372
3373 /* codec detection */
3374 if (!chip->codec_mask) {
3375 dev_err(card->dev, "no codecs found!\n");
3376 return -ENODEV;
3377 }
3378
3379 strcpy(card->driver, "HDA-Intel");
3380 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3381 sizeof(card->shortname));
3382 snprintf(card->longname, sizeof(card->longname),
3383 "%s at 0x%lx irq %i",
3384 card->shortname, chip->addr, chip->irq);
3385
3386 return 0;
3387 }
3388
3389 static void power_down_all_codecs(struct azx *chip)
3390 {
3391 #ifdef CONFIG_PM
3392 /* The codecs were powered up in snd_hda_codec_new().
3393 * Now all initialization done, so turn them down if possible
3394 */
3395 struct hda_codec *codec;
3396 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3397 snd_hda_power_down(codec);
3398 }
3399 #endif
3400 }
3401
3402 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3403 /* callback from request_firmware_nowait() */
3404 static void azx_firmware_cb(const struct firmware *fw, void *context)
3405 {
3406 struct snd_card *card = context;
3407 struct azx *chip = card->private_data;
3408 struct pci_dev *pci = chip->pci;
3409
3410 if (!fw) {
3411 dev_err(card->dev, "Cannot load firmware, aborting\n");
3412 goto error;
3413 }
3414
3415 chip->fw = fw;
3416 if (!chip->disabled) {
3417 /* continue probing */
3418 if (azx_probe_continue(chip))
3419 goto error;
3420 }
3421 return; /* OK */
3422
3423 error:
3424 snd_card_free(card);
3425 pci_set_drvdata(pci, NULL);
3426 }
3427 #endif
3428
3429 /*
3430 * HDA controller ops.
3431 */
3432
3433 /* PCI register access. */
3434 static void pci_azx_writel(u32 value, u32 *addr)
3435 {
3436 writel(value, addr);
3437 }
3438
3439 static u32 pci_azx_readl(u32 *addr)
3440 {
3441 return readl(addr);
3442 }
3443
3444 static void pci_azx_writew(u16 value, u16 *addr)
3445 {
3446 writew(value, addr);
3447 }
3448
3449 static u16 pci_azx_readw(u16 *addr)
3450 {
3451 return readw(addr);
3452 }
3453
3454 static void pci_azx_writeb(u8 value, u8 *addr)
3455 {
3456 writeb(value, addr);
3457 }
3458
3459 static u8 pci_azx_readb(u8 *addr)
3460 {
3461 return readb(addr);
3462 }
3463
3464 static int disable_msi_reset_irq(struct azx *chip)
3465 {
3466 int err;
3467
3468 free_irq(chip->irq, chip);
3469 chip->irq = -1;
3470 pci_disable_msi(chip->pci);
3471 chip->msi = 0;
3472 err = azx_acquire_irq(chip, 1);
3473 if (err < 0)
3474 return err;
3475
3476 return 0;
3477 }
3478
3479 static const struct hda_controller_ops pci_hda_ops = {
3480 .writel = pci_azx_writel,
3481 .readl = pci_azx_readl,
3482 .writew = pci_azx_writew,
3483 .readw = pci_azx_readw,
3484 .writeb = pci_azx_writeb,
3485 .readb = pci_azx_readb,
3486 .disable_msi_reset_irq = disable_msi_reset_irq,
3487 };
3488
3489 static int azx_probe(struct pci_dev *pci,
3490 const struct pci_device_id *pci_id)
3491 {
3492 static int dev;
3493 struct snd_card *card;
3494 struct azx *chip;
3495 bool schedule_probe;
3496 int err;
3497
3498 if (dev >= SNDRV_CARDS)
3499 return -ENODEV;
3500 if (!enable[dev]) {
3501 dev++;
3502 return -ENOENT;
3503 }
3504
3505 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3506 0, &card);
3507 if (err < 0) {
3508 dev_err(&pci->dev, "Error creating card!\n");
3509 return err;
3510 }
3511
3512 err = azx_create(card, pci, dev, pci_id->driver_data,
3513 &pci_hda_ops, &chip);
3514 if (err < 0)
3515 goto out_free;
3516 card->private_data = chip;
3517
3518 pci_set_drvdata(pci, card);
3519
3520 err = register_vga_switcheroo(chip);
3521 if (err < 0) {
3522 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
3523 goto out_free;
3524 }
3525
3526 if (check_hdmi_disabled(pci)) {
3527 dev_info(card->dev, "VGA controller is disabled\n");
3528 dev_info(card->dev, "Delaying initialization\n");
3529 chip->disabled = true;
3530 }
3531
3532 schedule_probe = !chip->disabled;
3533
3534 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3535 if (patch[dev] && *patch[dev]) {
3536 dev_info(card->dev, "Applying patch firmware '%s'\n",
3537 patch[dev]);
3538 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3539 &pci->dev, GFP_KERNEL, card,
3540 azx_firmware_cb);
3541 if (err < 0)
3542 goto out_free;
3543 schedule_probe = false; /* continued in azx_firmware_cb() */
3544 }
3545 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3546
3547 #ifndef CONFIG_SND_HDA_I915
3548 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3549 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
3550 #endif
3551
3552 if (schedule_probe)
3553 schedule_work(&chip->probe_work);
3554
3555 dev++;
3556 if (chip->disabled)
3557 complete_all(&chip->probe_wait);
3558 return 0;
3559
3560 out_free:
3561 snd_card_free(card);
3562 return err;
3563 }
3564
3565 static int azx_probe_continue(struct azx *chip)
3566 {
3567 struct pci_dev *pci = chip->pci;
3568 int dev = chip->dev_index;
3569 int err;
3570
3571 /* Request power well for Haswell HDA controller and codec */
3572 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3573 #ifdef CONFIG_SND_HDA_I915
3574 err = hda_i915_init();
3575 if (err < 0) {
3576 dev_err(chip->card->dev,
3577 "Error request power-well from i915\n");
3578 goto out_free;
3579 }
3580 #endif
3581 hda_display_power(true);
3582 }
3583
3584 err = azx_first_init(chip);
3585 if (err < 0)
3586 goto out_free;
3587
3588 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3589 chip->beep_mode = beep_mode[dev];
3590 #endif
3591
3592 /* create codec instances */
3593 err = azx_codec_create(chip, model[dev]);
3594 if (err < 0)
3595 goto out_free;
3596 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3597 if (chip->fw) {
3598 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3599 chip->fw->data);
3600 if (err < 0)
3601 goto out_free;
3602 #ifndef CONFIG_PM
3603 release_firmware(chip->fw); /* no longer needed */
3604 chip->fw = NULL;
3605 #endif
3606 }
3607 #endif
3608 if ((probe_only[dev] & 1) == 0) {
3609 err = azx_codec_configure(chip);
3610 if (err < 0)
3611 goto out_free;
3612 }
3613
3614 /* create PCM streams */
3615 err = snd_hda_build_pcms(chip->bus);
3616 if (err < 0)
3617 goto out_free;
3618
3619 /* create mixer controls */
3620 err = azx_mixer_create(chip);
3621 if (err < 0)
3622 goto out_free;
3623
3624 err = snd_card_register(chip->card);
3625 if (err < 0)
3626 goto out_free;
3627
3628 chip->running = 1;
3629 power_down_all_codecs(chip);
3630 azx_notifier_register(chip);
3631 azx_add_card_list(chip);
3632 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
3633 pm_runtime_put_noidle(&pci->dev);
3634
3635 out_free:
3636 if (err < 0)
3637 chip->init_failed = 1;
3638 complete_all(&chip->probe_wait);
3639 return err;
3640 }
3641
3642 static void azx_remove(struct pci_dev *pci)
3643 {
3644 struct snd_card *card = pci_get_drvdata(pci);
3645
3646 if (card)
3647 snd_card_free(card);
3648 }
3649
3650 /* PCI IDs */
3651 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3652 /* CPT */
3653 { PCI_DEVICE(0x8086, 0x1c20),
3654 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3655 /* PBG */
3656 { PCI_DEVICE(0x8086, 0x1d20),
3657 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3658 /* Panther Point */
3659 { PCI_DEVICE(0x8086, 0x1e20),
3660 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3661 /* Lynx Point */
3662 { PCI_DEVICE(0x8086, 0x8c20),
3663 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3664 /* Wellsburg */
3665 { PCI_DEVICE(0x8086, 0x8d20),
3666 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3667 { PCI_DEVICE(0x8086, 0x8d21),
3668 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3669 /* Lynx Point-LP */
3670 { PCI_DEVICE(0x8086, 0x9c20),
3671 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3672 /* Lynx Point-LP */
3673 { PCI_DEVICE(0x8086, 0x9c21),
3674 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3675 /* Wildcat Point-LP */
3676 { PCI_DEVICE(0x8086, 0x9ca0),
3677 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3678 /* Haswell */
3679 { PCI_DEVICE(0x8086, 0x0a0c),
3680 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3681 { PCI_DEVICE(0x8086, 0x0c0c),
3682 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3683 { PCI_DEVICE(0x8086, 0x0d0c),
3684 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3685 /* Broadwell */
3686 { PCI_DEVICE(0x8086, 0x160c),
3687 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3688 /* 5 Series/3400 */
3689 { PCI_DEVICE(0x8086, 0x3b56),
3690 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3691 /* Poulsbo */
3692 { PCI_DEVICE(0x8086, 0x811b),
3693 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3694 /* Oaktrail */
3695 { PCI_DEVICE(0x8086, 0x080a),
3696 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3697 /* BayTrail */
3698 { PCI_DEVICE(0x8086, 0x0f04),
3699 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3700 /* ICH */
3701 { PCI_DEVICE(0x8086, 0x2668),
3702 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3703 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3704 { PCI_DEVICE(0x8086, 0x27d8),
3705 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3706 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3707 { PCI_DEVICE(0x8086, 0x269a),
3708 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3709 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3710 { PCI_DEVICE(0x8086, 0x284b),
3711 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3712 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3713 { PCI_DEVICE(0x8086, 0x293e),
3714 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3715 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3716 { PCI_DEVICE(0x8086, 0x293f),
3717 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3718 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3719 { PCI_DEVICE(0x8086, 0x3a3e),
3720 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3721 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3722 { PCI_DEVICE(0x8086, 0x3a6e),
3723 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3724 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3725 /* Generic Intel */
3726 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3727 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3728 .class_mask = 0xffffff,
3729 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3730 /* ATI SB 450/600/700/800/900 */
3731 { PCI_DEVICE(0x1002, 0x437b),
3732 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3733 { PCI_DEVICE(0x1002, 0x4383),
3734 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3735 /* AMD Hudson */
3736 { PCI_DEVICE(0x1022, 0x780d),
3737 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3738 /* ATI HDMI */
3739 { PCI_DEVICE(0x1002, 0x793b),
3740 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3741 { PCI_DEVICE(0x1002, 0x7919),
3742 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3743 { PCI_DEVICE(0x1002, 0x960f),
3744 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3745 { PCI_DEVICE(0x1002, 0x970f),
3746 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3747 { PCI_DEVICE(0x1002, 0xaa00),
3748 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3749 { PCI_DEVICE(0x1002, 0xaa08),
3750 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3751 { PCI_DEVICE(0x1002, 0xaa10),
3752 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3753 { PCI_DEVICE(0x1002, 0xaa18),
3754 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3755 { PCI_DEVICE(0x1002, 0xaa20),
3756 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3757 { PCI_DEVICE(0x1002, 0xaa28),
3758 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3759 { PCI_DEVICE(0x1002, 0xaa30),
3760 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3761 { PCI_DEVICE(0x1002, 0xaa38),
3762 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3763 { PCI_DEVICE(0x1002, 0xaa40),
3764 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3765 { PCI_DEVICE(0x1002, 0xaa48),
3766 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3767 { PCI_DEVICE(0x1002, 0xaa50),
3768 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3769 { PCI_DEVICE(0x1002, 0xaa58),
3770 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3771 { PCI_DEVICE(0x1002, 0xaa60),
3772 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3773 { PCI_DEVICE(0x1002, 0xaa68),
3774 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3775 { PCI_DEVICE(0x1002, 0xaa80),
3776 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3777 { PCI_DEVICE(0x1002, 0xaa88),
3778 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3779 { PCI_DEVICE(0x1002, 0xaa90),
3780 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3781 { PCI_DEVICE(0x1002, 0xaa98),
3782 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3783 { PCI_DEVICE(0x1002, 0x9902),
3784 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3785 { PCI_DEVICE(0x1002, 0xaaa0),
3786 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3787 { PCI_DEVICE(0x1002, 0xaaa8),
3788 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3789 { PCI_DEVICE(0x1002, 0xaab0),
3790 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3791 /* VIA VT8251/VT8237A */
3792 { PCI_DEVICE(0x1106, 0x3288),
3793 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3794 /* VIA GFX VT7122/VX900 */
3795 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3796 /* VIA GFX VT6122/VX11 */
3797 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3798 /* SIS966 */
3799 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3800 /* ULI M5461 */
3801 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3802 /* NVIDIA MCP */
3803 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3804 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3805 .class_mask = 0xffffff,
3806 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3807 /* Teradici */
3808 { PCI_DEVICE(0x6549, 0x1200),
3809 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3810 { PCI_DEVICE(0x6549, 0x2200),
3811 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3812 /* Creative X-Fi (CA0110-IBG) */
3813 /* CTHDA chips */
3814 { PCI_DEVICE(0x1102, 0x0010),
3815 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3816 { PCI_DEVICE(0x1102, 0x0012),
3817 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3818 #if !IS_ENABLED(CONFIG_SND_CTXFI)
3819 /* the following entry conflicts with snd-ctxfi driver,
3820 * as ctxfi driver mutates from HD-audio to native mode with
3821 * a special command sequence.
3822 */
3823 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3824 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3825 .class_mask = 0xffffff,
3826 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3827 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3828 #else
3829 /* this entry seems still valid -- i.e. without emu20kx chip */
3830 { PCI_DEVICE(0x1102, 0x0009),
3831 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3832 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3833 #endif
3834 /* Vortex86MX */
3835 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3836 /* VMware HDAudio */
3837 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3838 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3839 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3840 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3841 .class_mask = 0xffffff,
3842 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3843 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3844 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3845 .class_mask = 0xffffff,
3846 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3847 { 0, }
3848 };
3849 MODULE_DEVICE_TABLE(pci, azx_ids);
3850
3851 /* pci_driver definition */
3852 static struct pci_driver azx_driver = {
3853 .name = KBUILD_MODNAME,
3854 .id_table = azx_ids,
3855 .probe = azx_probe,
3856 .remove = azx_remove,
3857 .driver = {
3858 .pm = AZX_PM_OPS,
3859 },
3860 };
3861
3862 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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