3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
54 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
;
55 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
;
56 static int enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
;
57 static char *model
[SNDRV_CARDS
];
58 static int position_fix
[SNDRV_CARDS
];
59 static int bdl_pos_adj
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
60 static int probe_mask
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
61 static int probe_only
[SNDRV_CARDS
];
62 static int single_cmd
;
63 static int enable_msi
;
65 module_param_array(index
, int, NULL
, 0444);
66 MODULE_PARM_DESC(index
, "Index value for Intel HD audio interface.");
67 module_param_array(id
, charp
, NULL
, 0444);
68 MODULE_PARM_DESC(id
, "ID string for Intel HD audio interface.");
69 module_param_array(enable
, bool, NULL
, 0444);
70 MODULE_PARM_DESC(enable
, "Enable Intel HD audio interface.");
71 module_param_array(model
, charp
, NULL
, 0444);
72 MODULE_PARM_DESC(model
, "Use the given board model.");
73 module_param_array(position_fix
, int, NULL
, 0444);
74 MODULE_PARM_DESC(position_fix
, "Fix DMA pointer "
75 "(0 = auto, 1 = none, 2 = POSBUF).");
76 module_param_array(bdl_pos_adj
, int, NULL
, 0644);
77 MODULE_PARM_DESC(bdl_pos_adj
, "BDL position adjustment offset.");
78 module_param_array(probe_mask
, int, NULL
, 0444);
79 MODULE_PARM_DESC(probe_mask
, "Bitmask to probe codecs (default = -1).");
80 module_param_array(probe_only
, bool, NULL
, 0444);
81 MODULE_PARM_DESC(probe_only
, "Only probing and no codec initialization.");
82 module_param(single_cmd
, bool, 0444);
83 MODULE_PARM_DESC(single_cmd
, "Use single command to communicate with codecs "
84 "(for debugging only).");
85 module_param(enable_msi
, int, 0444);
86 MODULE_PARM_DESC(enable_msi
, "Enable Message Signaled Interrupt (MSI)");
88 #ifdef CONFIG_SND_HDA_POWER_SAVE
89 static int power_save
= CONFIG_SND_HDA_POWER_SAVE_DEFAULT
;
90 module_param(power_save
, int, 0644);
91 MODULE_PARM_DESC(power_save
, "Automatic power-saving timeout "
92 "(in second, 0 = disable).");
94 /* reset the HD-audio controller in power save mode.
95 * this may give more power-saving, but will take longer time to
98 static int power_save_controller
= 1;
99 module_param(power_save_controller
, bool, 0644);
100 MODULE_PARM_DESC(power_save_controller
, "Reset controller in power save mode.");
103 MODULE_LICENSE("GPL");
104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
129 MODULE_DESCRIPTION("Intel HDA driver");
131 #define SFX "hda-intel: "
137 #define ICH6_REG_GCAP 0x00
138 #define ICH6_REG_VMIN 0x02
139 #define ICH6_REG_VMAJ 0x03
140 #define ICH6_REG_OUTPAY 0x04
141 #define ICH6_REG_INPAY 0x06
142 #define ICH6_REG_GCTL 0x08
143 #define ICH6_REG_WAKEEN 0x0c
144 #define ICH6_REG_STATESTS 0x0e
145 #define ICH6_REG_GSTS 0x10
146 #define ICH6_REG_INTCTL 0x20
147 #define ICH6_REG_INTSTS 0x24
148 #define ICH6_REG_WALCLK 0x30
149 #define ICH6_REG_SYNC 0x34
150 #define ICH6_REG_CORBLBASE 0x40
151 #define ICH6_REG_CORBUBASE 0x44
152 #define ICH6_REG_CORBWP 0x48
153 #define ICH6_REG_CORBRP 0x4A
154 #define ICH6_REG_CORBCTL 0x4c
155 #define ICH6_REG_CORBSTS 0x4d
156 #define ICH6_REG_CORBSIZE 0x4e
158 #define ICH6_REG_RIRBLBASE 0x50
159 #define ICH6_REG_RIRBUBASE 0x54
160 #define ICH6_REG_RIRBWP 0x58
161 #define ICH6_REG_RINTCNT 0x5a
162 #define ICH6_REG_RIRBCTL 0x5c
163 #define ICH6_REG_RIRBSTS 0x5d
164 #define ICH6_REG_RIRBSIZE 0x5e
166 #define ICH6_REG_IC 0x60
167 #define ICH6_REG_IR 0x64
168 #define ICH6_REG_IRS 0x68
169 #define ICH6_IRS_VALID (1<<1)
170 #define ICH6_IRS_BUSY (1<<0)
172 #define ICH6_REG_DPLBASE 0x70
173 #define ICH6_REG_DPUBASE 0x74
174 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
176 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
177 enum { SDI0
, SDI1
, SDI2
, SDI3
, SDO0
, SDO1
, SDO2
, SDO3
};
179 /* stream register offsets from stream base */
180 #define ICH6_REG_SD_CTL 0x00
181 #define ICH6_REG_SD_STS 0x03
182 #define ICH6_REG_SD_LPIB 0x04
183 #define ICH6_REG_SD_CBL 0x08
184 #define ICH6_REG_SD_LVI 0x0c
185 #define ICH6_REG_SD_FIFOW 0x0e
186 #define ICH6_REG_SD_FIFOSIZE 0x10
187 #define ICH6_REG_SD_FORMAT 0x12
188 #define ICH6_REG_SD_BDLPL 0x18
189 #define ICH6_REG_SD_BDLPU 0x1c
192 #define ICH6_PCIREG_TCSEL 0x44
198 /* max number of SDs */
199 /* ICH, ATI and VIA have 4 playback and 4 capture */
200 #define ICH6_NUM_CAPTURE 4
201 #define ICH6_NUM_PLAYBACK 4
203 /* ULI has 6 playback and 5 capture */
204 #define ULI_NUM_CAPTURE 5
205 #define ULI_NUM_PLAYBACK 6
207 /* ATI HDMI has 1 playback and 0 capture */
208 #define ATIHDMI_NUM_CAPTURE 0
209 #define ATIHDMI_NUM_PLAYBACK 1
211 /* TERA has 4 playback and 3 capture */
212 #define TERA_NUM_CAPTURE 3
213 #define TERA_NUM_PLAYBACK 4
215 /* this number is statically defined for simplicity */
216 #define MAX_AZX_DEV 16
218 /* max number of fragments - we may use more if allocating more pages for BDL */
219 #define BDL_SIZE 4096
220 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
221 #define AZX_MAX_FRAG 32
222 /* max buffer size - no h/w limit, you can increase as you like */
223 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
224 /* max number of PCM devics per card */
225 #define AZX_MAX_PCMS 8
227 /* RIRB int mask: overrun[2], response[0] */
228 #define RIRB_INT_RESPONSE 0x01
229 #define RIRB_INT_OVERRUN 0x04
230 #define RIRB_INT_MASK 0x05
232 /* STATESTS int mask: S3,SD2,SD1,SD0 */
233 #define AZX_MAX_CODECS 4
234 #define STATESTS_INT_MASK 0x0f
237 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
238 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
239 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
240 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
241 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
242 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
243 #define SD_CTL_STREAM_TAG_SHIFT 20
245 /* SD_CTL and SD_STS */
246 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
247 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
248 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
249 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
253 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
255 /* INTCTL and INTSTS */
256 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
257 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
258 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
260 /* GCTL unsolicited response enable bit */
261 #define ICH6_GCTL_UREN (1<<8)
264 #define ICH6_GCTL_RESET (1<<0)
266 /* CORB/RIRB control, read/write pointer */
267 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
268 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
269 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
270 /* below are so far hardcoded - should read registers in future */
271 #define ICH6_MAX_CORB_ENTRIES 256
272 #define ICH6_MAX_RIRB_ENTRIES 256
274 /* position fix mode */
281 /* Defines for ATI HD Audio support in SB450 south bridge */
282 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
283 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
285 /* Defines for Nvidia HDA support */
286 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
287 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
288 #define NVIDIA_HDA_ISTRM_COH 0x4d
289 #define NVIDIA_HDA_OSTRM_COH 0x4c
290 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
292 /* Defines for Intel SCH HDA snoop control */
293 #define INTEL_SCH_HDA_DEVC 0x78
294 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
296 /* Define IN stream 0 FIFO size offset in VIA controller */
297 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
298 /* Define VIA HD Audio Device ID*/
299 #define VIA_HDAC_DEVICE_ID 0x3288
301 /* HD Audio class code */
302 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
308 struct snd_dma_buffer bdl
; /* BDL buffer */
309 u32
*posbuf
; /* position buffer pointer */
311 unsigned int bufsize
; /* size of the play buffer in bytes */
312 unsigned int period_bytes
; /* size of the period in bytes */
313 unsigned int frags
; /* number for period in the play buffer */
314 unsigned int fifo_size
; /* FIFO size */
316 void __iomem
*sd_addr
; /* stream descriptor pointer */
318 u32 sd_int_sta_mask
; /* stream int status mask */
321 struct snd_pcm_substream
*substream
; /* assigned substream,
324 unsigned int format_val
; /* format value to be set in the
325 * controller and the codec
327 unsigned char stream_tag
; /* assigned stream */
328 unsigned char index
; /* stream index */
330 unsigned int opened
:1;
331 unsigned int running
:1;
332 unsigned int irq_pending
:1;
333 unsigned int irq_ignore
:1;
336 * A flag to ensure DMA position is 0
337 * when link position is not greater than FIFO size
339 unsigned int insufficient
:1;
344 u32
*buf
; /* CORB/RIRB buffer
345 * Each CORB entry is 4byte, RIRB is 8byte
347 dma_addr_t addr
; /* physical address of CORB/RIRB buffer */
349 unsigned short rp
, wp
; /* read/write pointers */
350 int cmds
; /* number of pending requests */
351 u32 res
; /* last read value */
355 struct snd_card
*card
;
359 /* chip type specific */
361 int playback_streams
;
362 int playback_index_offset
;
364 int capture_index_offset
;
369 void __iomem
*remap_addr
;
374 struct mutex open_mutex
;
376 /* streams (x num_streams) */
377 struct azx_dev
*azx_dev
;
380 struct snd_pcm
*pcm
[AZX_MAX_PCMS
];
383 unsigned short codec_mask
;
384 int codec_probe_mask
; /* copied from probe_mask option */
391 /* CORB/RIRB and position buffers */
392 struct snd_dma_buffer rb
;
393 struct snd_dma_buffer posbuf
;
397 unsigned int running
:1;
398 unsigned int initialized
:1;
399 unsigned int single_cmd
:1;
400 unsigned int polling_mode
:1;
402 unsigned int irq_pending_warned
:1;
403 unsigned int via_dmapos_patch
:1; /* enable DMA-position fix for VIA */
404 unsigned int probing
:1; /* codec probing phase */
407 unsigned int last_cmd
; /* last issued command (to sync) */
409 /* for pending irqs */
410 struct work_struct irq_pending_work
;
412 /* reboot notifier (for mysterious hangup problem at power-down) */
413 struct notifier_block reboot_notifier
;
428 AZX_NUM_DRIVERS
, /* keep this as last entry */
431 static char *driver_short_names
[] __devinitdata
= {
432 [AZX_DRIVER_ICH
] = "HDA Intel",
433 [AZX_DRIVER_SCH
] = "HDA Intel MID",
434 [AZX_DRIVER_ATI
] = "HDA ATI SB",
435 [AZX_DRIVER_ATIHDMI
] = "HDA ATI HDMI",
436 [AZX_DRIVER_VIA
] = "HDA VIA VT82xx",
437 [AZX_DRIVER_SIS
] = "HDA SIS966",
438 [AZX_DRIVER_ULI
] = "HDA ULI M5461",
439 [AZX_DRIVER_NVIDIA
] = "HDA NVidia",
440 [AZX_DRIVER_TERA
] = "HDA Teradici",
441 [AZX_DRIVER_GENERIC
] = "HD-Audio Generic",
445 * macros for easy use
447 #define azx_writel(chip,reg,value) \
448 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
449 #define azx_readl(chip,reg) \
450 readl((chip)->remap_addr + ICH6_REG_##reg)
451 #define azx_writew(chip,reg,value) \
452 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
453 #define azx_readw(chip,reg) \
454 readw((chip)->remap_addr + ICH6_REG_##reg)
455 #define azx_writeb(chip,reg,value) \
456 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
457 #define azx_readb(chip,reg) \
458 readb((chip)->remap_addr + ICH6_REG_##reg)
460 #define azx_sd_writel(dev,reg,value) \
461 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
462 #define azx_sd_readl(dev,reg) \
463 readl((dev)->sd_addr + ICH6_REG_##reg)
464 #define azx_sd_writew(dev,reg,value) \
465 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
466 #define azx_sd_readw(dev,reg) \
467 readw((dev)->sd_addr + ICH6_REG_##reg)
468 #define azx_sd_writeb(dev,reg,value) \
469 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
470 #define azx_sd_readb(dev,reg) \
471 readb((dev)->sd_addr + ICH6_REG_##reg)
473 /* for pcm support */
474 #define get_azx_dev(substream) (substream->runtime->private_data)
476 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
);
479 * Interface for HD codec
483 * CORB / RIRB interface
485 static int azx_alloc_cmd_io(struct azx
*chip
)
489 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
490 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
491 snd_dma_pci_data(chip
->pci
),
492 PAGE_SIZE
, &chip
->rb
);
494 snd_printk(KERN_ERR SFX
"cannot allocate CORB/RIRB\n");
500 static void azx_init_cmd_io(struct azx
*chip
)
503 chip
->corb
.addr
= chip
->rb
.addr
;
504 chip
->corb
.buf
= (u32
*)chip
->rb
.area
;
505 azx_writel(chip
, CORBLBASE
, (u32
)chip
->corb
.addr
);
506 azx_writel(chip
, CORBUBASE
, upper_32_bits(chip
->corb
.addr
));
508 /* set the corb size to 256 entries (ULI requires explicitly) */
509 azx_writeb(chip
, CORBSIZE
, 0x02);
510 /* set the corb write pointer to 0 */
511 azx_writew(chip
, CORBWP
, 0);
512 /* reset the corb hw read pointer */
513 azx_writew(chip
, CORBRP
, ICH6_RBRWP_CLR
);
514 /* enable corb dma */
515 azx_writeb(chip
, CORBCTL
, ICH6_RBCTL_DMA_EN
);
518 chip
->rirb
.addr
= chip
->rb
.addr
+ 2048;
519 chip
->rirb
.buf
= (u32
*)(chip
->rb
.area
+ 2048);
520 azx_writel(chip
, RIRBLBASE
, (u32
)chip
->rirb
.addr
);
521 azx_writel(chip
, RIRBUBASE
, upper_32_bits(chip
->rirb
.addr
));
523 /* set the rirb size to 256 entries (ULI requires explicitly) */
524 azx_writeb(chip
, RIRBSIZE
, 0x02);
525 /* reset the rirb hw write pointer */
526 azx_writew(chip
, RIRBWP
, ICH6_RBRWP_CLR
);
527 /* set N=1, get RIRB response interrupt for new entry */
528 azx_writew(chip
, RINTCNT
, 1);
529 /* enable rirb dma and response irq */
530 azx_writeb(chip
, RIRBCTL
, ICH6_RBCTL_DMA_EN
| ICH6_RBCTL_IRQ_EN
);
531 chip
->rirb
.rp
= chip
->rirb
.cmds
= 0;
534 static void azx_free_cmd_io(struct azx
*chip
)
536 /* disable ringbuffer DMAs */
537 azx_writeb(chip
, RIRBCTL
, 0);
538 azx_writeb(chip
, CORBCTL
, 0);
542 static int azx_corb_send_cmd(struct hda_bus
*bus
, u32 val
)
544 struct azx
*chip
= bus
->private_data
;
547 /* add command to corb */
548 wp
= azx_readb(chip
, CORBWP
);
550 wp
%= ICH6_MAX_CORB_ENTRIES
;
552 spin_lock_irq(&chip
->reg_lock
);
554 chip
->corb
.buf
[wp
] = cpu_to_le32(val
);
555 azx_writel(chip
, CORBWP
, wp
);
556 spin_unlock_irq(&chip
->reg_lock
);
561 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
563 /* retrieve RIRB entry - called from interrupt handler */
564 static void azx_update_rirb(struct azx
*chip
)
569 wp
= azx_readb(chip
, RIRBWP
);
570 if (wp
== chip
->rirb
.wp
)
574 while (chip
->rirb
.rp
!= wp
) {
576 chip
->rirb
.rp
%= ICH6_MAX_RIRB_ENTRIES
;
578 rp
= chip
->rirb
.rp
<< 1; /* an RIRB entry is 8-bytes */
579 res_ex
= le32_to_cpu(chip
->rirb
.buf
[rp
+ 1]);
580 res
= le32_to_cpu(chip
->rirb
.buf
[rp
]);
581 if (res_ex
& ICH6_RIRB_EX_UNSOL_EV
)
582 snd_hda_queue_unsol_event(chip
->bus
, res
, res_ex
);
583 else if (chip
->rirb
.cmds
) {
584 chip
->rirb
.res
= res
;
591 /* receive a response */
592 static unsigned int azx_rirb_get_response(struct hda_bus
*bus
)
594 struct azx
*chip
= bus
->private_data
;
595 unsigned long timeout
;
598 timeout
= jiffies
+ msecs_to_jiffies(1000);
600 if (chip
->polling_mode
) {
601 spin_lock_irq(&chip
->reg_lock
);
602 azx_update_rirb(chip
);
603 spin_unlock_irq(&chip
->reg_lock
);
605 if (!chip
->rirb
.cmds
) {
607 return chip
->rirb
.res
; /* the last value */
609 if (time_after(jiffies
, timeout
))
611 if (bus
->needs_damn_long_delay
)
612 msleep(2); /* temporary workaround */
620 snd_printk(KERN_WARNING
"hda_intel: No response from codec, "
621 "disabling MSI: last cmd=0x%08x\n", chip
->last_cmd
);
622 free_irq(chip
->irq
, chip
);
624 pci_disable_msi(chip
->pci
);
626 if (azx_acquire_irq(chip
, 1) < 0)
631 if (!chip
->polling_mode
) {
632 snd_printk(KERN_WARNING
"hda_intel: azx_get_response timeout, "
633 "switching to polling mode: last cmd=0x%08x\n",
635 chip
->polling_mode
= 1;
640 /* If this critical timeout happens during the codec probing
641 * phase, this is likely an access to a non-existing codec
642 * slot. Better to return an error and reset the system.
647 snd_printk(KERN_ERR
"hda_intel: azx_get_response timeout, "
648 "switching to single_cmd mode: last cmd=0x%08x\n",
650 chip
->rirb
.rp
= azx_readb(chip
, RIRBWP
);
652 /* switch to single_cmd mode */
653 chip
->single_cmd
= 1;
654 azx_free_cmd_io(chip
);
659 * Use the single immediate command instead of CORB/RIRB for simplicity
661 * Note: according to Intel, this is not preferred use. The command was
662 * intended for the BIOS only, and may get confused with unsolicited
663 * responses. So, we shouldn't use it for normal operation from the
665 * I left the codes, however, for debugging/testing purposes.
669 static int azx_single_send_cmd(struct hda_bus
*bus
, u32 val
)
671 struct azx
*chip
= bus
->private_data
;
675 /* check ICB busy bit */
676 if (!((azx_readw(chip
, IRS
) & ICH6_IRS_BUSY
))) {
677 /* Clear IRV valid bit */
678 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
680 azx_writel(chip
, IC
, val
);
681 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
687 if (printk_ratelimit())
688 snd_printd(SFX
"send_cmd timeout: IRS=0x%x, val=0x%x\n",
689 azx_readw(chip
, IRS
), val
);
693 /* receive a response */
694 static unsigned int azx_single_get_response(struct hda_bus
*bus
)
696 struct azx
*chip
= bus
->private_data
;
700 /* check IRV busy bit */
701 if (azx_readw(chip
, IRS
) & ICH6_IRS_VALID
)
702 return azx_readl(chip
, IR
);
705 if (printk_ratelimit())
706 snd_printd(SFX
"get_response timeout: IRS=0x%x\n",
707 azx_readw(chip
, IRS
));
708 return (unsigned int)-1;
712 * The below are the main callbacks from hda_codec.
714 * They are just the skeleton to call sub-callbacks according to the
715 * current setting of chip->single_cmd.
719 static int azx_send_cmd(struct hda_bus
*bus
, unsigned int val
)
721 struct azx
*chip
= bus
->private_data
;
723 chip
->last_cmd
= val
;
724 if (chip
->single_cmd
)
725 return azx_single_send_cmd(bus
, val
);
727 return azx_corb_send_cmd(bus
, val
);
731 static unsigned int azx_get_response(struct hda_bus
*bus
)
733 struct azx
*chip
= bus
->private_data
;
734 if (chip
->single_cmd
)
735 return azx_single_get_response(bus
);
737 return azx_rirb_get_response(bus
);
740 #ifdef CONFIG_SND_HDA_POWER_SAVE
741 static void azx_power_notify(struct hda_bus
*bus
);
744 /* reset codec link */
745 static int azx_reset(struct azx
*chip
)
750 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
752 /* reset controller */
753 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) & ~ICH6_GCTL_RESET
);
756 while (azx_readb(chip
, GCTL
) && --count
)
759 /* delay for >= 100us for codec PLL to settle per spec
760 * Rev 0.9 section 5.5.1
764 /* Bring controller out of reset */
765 azx_writeb(chip
, GCTL
, azx_readb(chip
, GCTL
) | ICH6_GCTL_RESET
);
768 while (!azx_readb(chip
, GCTL
) && --count
)
771 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
774 /* check to see if controller is ready */
775 if (!azx_readb(chip
, GCTL
)) {
776 snd_printd("azx_reset: controller not ready!\n");
780 /* Accept unsolicited responses */
781 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) | ICH6_GCTL_UREN
);
784 if (!chip
->codec_mask
) {
785 chip
->codec_mask
= azx_readw(chip
, STATESTS
);
786 snd_printdd("codec_mask = 0x%x\n", chip
->codec_mask
);
797 /* enable interrupts */
798 static void azx_int_enable(struct azx
*chip
)
800 /* enable controller CIE and GIE */
801 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) |
802 ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
);
805 /* disable interrupts */
806 static void azx_int_disable(struct azx
*chip
)
810 /* disable interrupts in stream descriptor */
811 for (i
= 0; i
< chip
->num_streams
; i
++) {
812 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
813 azx_sd_writeb(azx_dev
, SD_CTL
,
814 azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_INT_MASK
);
817 /* disable SIE for all streams */
818 azx_writeb(chip
, INTCTL
, 0);
820 /* disable controller CIE and GIE */
821 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) &
822 ~(ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
));
825 /* clear interrupts */
826 static void azx_int_clear(struct azx
*chip
)
830 /* clear stream status */
831 for (i
= 0; i
< chip
->num_streams
; i
++) {
832 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
833 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
837 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
839 /* clear rirb status */
840 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
842 /* clear int status */
843 azx_writel(chip
, INTSTS
, ICH6_INT_CTRL_EN
| ICH6_INT_ALL_STREAM
);
847 static void azx_stream_start(struct azx
*chip
, struct azx_dev
*azx_dev
)
850 * Before stream start, initialize parameter
852 azx_dev
->insufficient
= 1;
855 azx_writeb(chip
, INTCTL
,
856 azx_readb(chip
, INTCTL
) | (1 << azx_dev
->index
));
857 /* set DMA start and interrupt mask */
858 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
859 SD_CTL_DMA_START
| SD_INT_MASK
);
863 static void azx_stream_clear(struct azx
*chip
, struct azx_dev
*azx_dev
)
865 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) &
866 ~(SD_CTL_DMA_START
| SD_INT_MASK
));
867 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
); /* to be sure */
871 static void azx_stream_stop(struct azx
*chip
, struct azx_dev
*azx_dev
)
873 azx_stream_clear(chip
, azx_dev
);
875 azx_writeb(chip
, INTCTL
,
876 azx_readb(chip
, INTCTL
) & ~(1 << azx_dev
->index
));
881 * reset and start the controller registers
883 static void azx_init_chip(struct azx
*chip
)
885 if (chip
->initialized
)
888 /* reset controller */
891 /* initialize interrupts */
893 azx_int_enable(chip
);
895 /* initialize the codec command I/O */
896 if (!chip
->single_cmd
)
897 azx_init_cmd_io(chip
);
899 /* program the position buffer */
900 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
);
901 azx_writel(chip
, DPUBASE
, upper_32_bits(chip
->posbuf
.addr
));
903 chip
->initialized
= 1;
907 * initialize the PCI registers
909 /* update bits in a PCI register byte */
910 static void update_pci_byte(struct pci_dev
*pci
, unsigned int reg
,
911 unsigned char mask
, unsigned char val
)
915 pci_read_config_byte(pci
, reg
, &data
);
917 data
|= (val
& mask
);
918 pci_write_config_byte(pci
, reg
, data
);
921 static void azx_init_pci(struct azx
*chip
)
923 unsigned short snoop
;
925 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
926 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
927 * Ensuring these bits are 0 clears playback static on some HD Audio
930 update_pci_byte(chip
->pci
, ICH6_PCIREG_TCSEL
, 0x07, 0);
932 switch (chip
->driver_type
) {
934 /* For ATI SB450 azalia HD audio, we need to enable snoop */
935 update_pci_byte(chip
->pci
,
936 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
,
937 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP
);
939 case AZX_DRIVER_NVIDIA
:
940 /* For NVIDIA HDA, enable snoop */
941 update_pci_byte(chip
->pci
,
942 NVIDIA_HDA_TRANSREG_ADDR
,
943 0x0f, NVIDIA_HDA_ENABLE_COHBITS
);
944 update_pci_byte(chip
->pci
,
945 NVIDIA_HDA_ISTRM_COH
,
946 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
947 update_pci_byte(chip
->pci
,
948 NVIDIA_HDA_OSTRM_COH
,
949 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
952 pci_read_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
, &snoop
);
953 if (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
) {
954 pci_write_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
, \
955 snoop
& (~INTEL_SCH_HDA_DEVC_NOSNOOP
));
956 pci_read_config_word(chip
->pci
,
957 INTEL_SCH_HDA_DEVC
, &snoop
);
958 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
959 (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
) \
968 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
);
973 static irqreturn_t
azx_interrupt(int irq
, void *dev_id
)
975 struct azx
*chip
= dev_id
;
976 struct azx_dev
*azx_dev
;
980 spin_lock(&chip
->reg_lock
);
982 status
= azx_readl(chip
, INTSTS
);
984 spin_unlock(&chip
->reg_lock
);
988 for (i
= 0; i
< chip
->num_streams
; i
++) {
989 azx_dev
= &chip
->azx_dev
[i
];
990 if (status
& azx_dev
->sd_int_sta_mask
) {
991 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
992 if (!azx_dev
->substream
|| !azx_dev
->running
)
994 /* ignore the first dummy IRQ (due to pos_adj) */
995 if (azx_dev
->irq_ignore
) {
996 azx_dev
->irq_ignore
= 0;
999 /* check whether this IRQ is really acceptable */
1000 if (azx_position_ok(chip
, azx_dev
)) {
1001 azx_dev
->irq_pending
= 0;
1002 spin_unlock(&chip
->reg_lock
);
1003 snd_pcm_period_elapsed(azx_dev
->substream
);
1004 spin_lock(&chip
->reg_lock
);
1005 } else if (chip
->bus
&& chip
->bus
->workq
) {
1006 /* bogus IRQ, process it later */
1007 azx_dev
->irq_pending
= 1;
1008 queue_work(chip
->bus
->workq
,
1009 &chip
->irq_pending_work
);
1014 /* clear rirb int */
1015 status
= azx_readb(chip
, RIRBSTS
);
1016 if (status
& RIRB_INT_MASK
) {
1017 if (!chip
->single_cmd
&& (status
& RIRB_INT_RESPONSE
))
1018 azx_update_rirb(chip
);
1019 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
1023 /* clear state status int */
1024 if (azx_readb(chip
, STATESTS
) & 0x04)
1025 azx_writeb(chip
, STATESTS
, 0x04);
1027 spin_unlock(&chip
->reg_lock
);
1034 * set up a BDL entry
1036 static int setup_bdle(struct snd_pcm_substream
*substream
,
1037 struct azx_dev
*azx_dev
, u32
**bdlp
,
1038 int ofs
, int size
, int with_ioc
)
1046 if (azx_dev
->frags
>= AZX_MAX_BDL_ENTRIES
)
1049 addr
= snd_pcm_sgbuf_get_addr(substream
, ofs
);
1050 /* program the address field of the BDL entry */
1051 bdl
[0] = cpu_to_le32((u32
)addr
);
1052 bdl
[1] = cpu_to_le32(upper_32_bits(addr
));
1053 /* program the size field of the BDL entry */
1054 chunk
= snd_pcm_sgbuf_get_chunk_size(substream
, ofs
, size
);
1055 bdl
[2] = cpu_to_le32(chunk
);
1056 /* program the IOC to enable interrupt
1057 * only when the whole fragment is processed
1060 bdl
[3] = (size
|| !with_ioc
) ? 0 : cpu_to_le32(0x01);
1070 * set up BDL entries
1072 static int azx_setup_periods(struct azx
*chip
,
1073 struct snd_pcm_substream
*substream
,
1074 struct azx_dev
*azx_dev
)
1077 int i
, ofs
, periods
, period_bytes
;
1080 /* reset BDL address */
1081 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1082 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1084 period_bytes
= azx_dev
->period_bytes
;
1085 periods
= azx_dev
->bufsize
/ period_bytes
;
1087 /* program the initial BDL entries */
1088 bdl
= (u32
*)azx_dev
->bdl
.area
;
1091 azx_dev
->irq_ignore
= 0;
1092 pos_adj
= bdl_pos_adj
[chip
->dev_index
];
1094 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1095 int pos_align
= pos_adj
;
1096 pos_adj
= (pos_adj
* runtime
->rate
+ 47999) / 48000;
1098 pos_adj
= pos_align
;
1100 pos_adj
= ((pos_adj
+ pos_align
- 1) / pos_align
) *
1102 pos_adj
= frames_to_bytes(runtime
, pos_adj
);
1103 if (pos_adj
>= period_bytes
) {
1104 snd_printk(KERN_WARNING
"Too big adjustment %d\n",
1105 bdl_pos_adj
[chip
->dev_index
]);
1108 ofs
= setup_bdle(substream
, azx_dev
,
1109 &bdl
, ofs
, pos_adj
, 1);
1112 azx_dev
->irq_ignore
= 1;
1116 for (i
= 0; i
< periods
; i
++) {
1117 if (i
== periods
- 1 && pos_adj
)
1118 ofs
= setup_bdle(substream
, azx_dev
, &bdl
, ofs
,
1119 period_bytes
- pos_adj
, 0);
1121 ofs
= setup_bdle(substream
, azx_dev
, &bdl
, ofs
,
1129 snd_printk(KERN_ERR
"Too many BDL entries: buffer=%d, period=%d\n",
1130 azx_dev
->bufsize
, period_bytes
);
1135 static void azx_stream_reset(struct azx
*chip
, struct azx_dev
*azx_dev
)
1140 azx_stream_clear(chip
, azx_dev
);
1142 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
1143 SD_CTL_STREAM_RESET
);
1146 while (!((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
1149 val
&= ~SD_CTL_STREAM_RESET
;
1150 azx_sd_writeb(azx_dev
, SD_CTL
, val
);
1154 /* waiting for hardware to report that the stream is out of reset */
1155 while (((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
1161 * set up the SD for streaming
1163 static int azx_setup_controller(struct azx
*chip
, struct azx_dev
*azx_dev
)
1165 /* make sure the run bit is zero for SD */
1166 azx_stream_clear(chip
, azx_dev
);
1167 /* program the stream_tag */
1168 azx_sd_writel(azx_dev
, SD_CTL
,
1169 (azx_sd_readl(azx_dev
, SD_CTL
) & ~SD_CTL_STREAM_TAG_MASK
)|
1170 (azx_dev
->stream_tag
<< SD_CTL_STREAM_TAG_SHIFT
));
1172 /* program the length of samples in cyclic buffer */
1173 azx_sd_writel(azx_dev
, SD_CBL
, azx_dev
->bufsize
);
1175 /* program the stream format */
1176 /* this value needs to be the same as the one programmed */
1177 azx_sd_writew(azx_dev
, SD_FORMAT
, azx_dev
->format_val
);
1179 /* program the stream LVI (last valid index) of the BDL */
1180 azx_sd_writew(azx_dev
, SD_LVI
, azx_dev
->frags
- 1);
1182 /* program the BDL address */
1183 /* lower BDL address */
1184 azx_sd_writel(azx_dev
, SD_BDLPL
, (u32
)azx_dev
->bdl
.addr
);
1185 /* upper BDL address */
1186 azx_sd_writel(azx_dev
, SD_BDLPU
, upper_32_bits(azx_dev
->bdl
.addr
));
1188 /* enable the position buffer */
1189 if (chip
->position_fix
== POS_FIX_POSBUF
||
1190 chip
->position_fix
== POS_FIX_AUTO
||
1191 chip
->via_dmapos_patch
) {
1192 if (!(azx_readl(chip
, DPLBASE
) & ICH6_DPLBASE_ENABLE
))
1193 azx_writel(chip
, DPLBASE
,
1194 (u32
)chip
->posbuf
.addr
| ICH6_DPLBASE_ENABLE
);
1197 /* set the interrupt enable bits in the descriptor control register */
1198 azx_sd_writel(azx_dev
, SD_CTL
,
1199 azx_sd_readl(azx_dev
, SD_CTL
) | SD_INT_MASK
);
1205 * Probe the given codec address
1207 static int probe_codec(struct azx
*chip
, int addr
)
1209 unsigned int cmd
= (addr
<< 28) | (AC_NODE_ROOT
<< 20) |
1210 (AC_VERB_PARAMETERS
<< 8) | AC_PAR_VENDOR_ID
;
1214 azx_send_cmd(chip
->bus
, cmd
);
1215 res
= azx_get_response(chip
->bus
);
1219 snd_printdd("hda_intel: codec #%d probed OK\n", addr
);
1223 static int azx_attach_pcm_stream(struct hda_bus
*bus
, struct hda_codec
*codec
,
1224 struct hda_pcm
*cpcm
);
1225 static void azx_stop_chip(struct azx
*chip
);
1228 * Codec initialization
1231 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1232 static unsigned int azx_max_codecs
[AZX_NUM_DRIVERS
] __devinitdata
= {
1233 [AZX_DRIVER_TERA
] = 1,
1236 static int __devinit
azx_codec_create(struct azx
*chip
, const char *model
,
1239 struct hda_bus_template bus_temp
;
1243 memset(&bus_temp
, 0, sizeof(bus_temp
));
1244 bus_temp
.private_data
= chip
;
1245 bus_temp
.modelname
= model
;
1246 bus_temp
.pci
= chip
->pci
;
1247 bus_temp
.ops
.command
= azx_send_cmd
;
1248 bus_temp
.ops
.get_response
= azx_get_response
;
1249 bus_temp
.ops
.attach_pcm
= azx_attach_pcm_stream
;
1250 #ifdef CONFIG_SND_HDA_POWER_SAVE
1251 bus_temp
.power_save
= &power_save
;
1252 bus_temp
.ops
.pm_notify
= azx_power_notify
;
1255 err
= snd_hda_bus_new(chip
->card
, &bus_temp
, &chip
->bus
);
1259 if (chip
->driver_type
== AZX_DRIVER_NVIDIA
)
1260 chip
->bus
->needs_damn_long_delay
= 1;
1263 max_slots
= azx_max_codecs
[chip
->driver_type
];
1265 max_slots
= AZX_MAX_CODECS
;
1267 /* First try to probe all given codec slots */
1268 for (c
= 0; c
< max_slots
; c
++) {
1269 if ((chip
->codec_mask
& (1 << c
)) & chip
->codec_probe_mask
) {
1270 if (probe_codec(chip
, c
) < 0) {
1271 /* Some BIOSen give you wrong codec addresses
1274 snd_printk(KERN_WARNING
1275 "hda_intel: Codec #%d probe error; "
1276 "disabling it...\n", c
);
1277 chip
->codec_mask
&= ~(1 << c
);
1278 /* More badly, accessing to a non-existing
1279 * codec often screws up the controller chip,
1280 * and distrubs the further communications.
1281 * Thus if an error occurs during probing,
1282 * better to reset the controller chip to
1283 * get back to the sanity state.
1285 azx_stop_chip(chip
);
1286 azx_init_chip(chip
);
1291 /* Then create codec instances */
1292 for (c
= 0; c
< max_slots
; c
++) {
1293 if ((chip
->codec_mask
& (1 << c
)) & chip
->codec_probe_mask
) {
1294 struct hda_codec
*codec
;
1295 err
= snd_hda_codec_new(chip
->bus
, c
, !no_init
, &codec
);
1302 snd_printk(KERN_ERR SFX
"no codecs initialized\n");
1314 /* assign a stream for the PCM */
1315 static inline struct azx_dev
*azx_assign_device(struct azx
*chip
, int stream
)
1318 if (stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
1319 dev
= chip
->playback_index_offset
;
1320 nums
= chip
->playback_streams
;
1322 dev
= chip
->capture_index_offset
;
1323 nums
= chip
->capture_streams
;
1325 for (i
= 0; i
< nums
; i
++, dev
++)
1326 if (!chip
->azx_dev
[dev
].opened
) {
1327 chip
->azx_dev
[dev
].opened
= 1;
1328 return &chip
->azx_dev
[dev
];
1333 /* release the assigned stream */
1334 static inline void azx_release_device(struct azx_dev
*azx_dev
)
1336 azx_dev
->opened
= 0;
1339 static struct snd_pcm_hardware azx_pcm_hw
= {
1340 .info
= (SNDRV_PCM_INFO_MMAP
|
1341 SNDRV_PCM_INFO_INTERLEAVED
|
1342 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1343 SNDRV_PCM_INFO_MMAP_VALID
|
1344 /* No full-resume yet implemented */
1345 /* SNDRV_PCM_INFO_RESUME |*/
1346 SNDRV_PCM_INFO_PAUSE
|
1347 SNDRV_PCM_INFO_SYNC_START
),
1348 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1349 .rates
= SNDRV_PCM_RATE_48000
,
1354 .buffer_bytes_max
= AZX_MAX_BUF_SIZE
,
1355 .period_bytes_min
= 128,
1356 .period_bytes_max
= AZX_MAX_BUF_SIZE
/ 2,
1358 .periods_max
= AZX_MAX_FRAG
,
1364 struct hda_codec
*codec
;
1365 struct hda_pcm_stream
*hinfo
[2];
1368 static int azx_pcm_open(struct snd_pcm_substream
*substream
)
1370 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1371 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1372 struct azx
*chip
= apcm
->chip
;
1373 struct azx_dev
*azx_dev
;
1374 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1375 unsigned long flags
;
1378 mutex_lock(&chip
->open_mutex
);
1379 azx_dev
= azx_assign_device(chip
, substream
->stream
);
1380 if (azx_dev
== NULL
) {
1381 mutex_unlock(&chip
->open_mutex
);
1384 runtime
->hw
= azx_pcm_hw
;
1385 runtime
->hw
.channels_min
= hinfo
->channels_min
;
1386 runtime
->hw
.channels_max
= hinfo
->channels_max
;
1387 runtime
->hw
.formats
= hinfo
->formats
;
1388 runtime
->hw
.rates
= hinfo
->rates
;
1389 snd_pcm_limit_hw_rates(runtime
);
1390 snd_pcm_hw_constraint_integer(runtime
, SNDRV_PCM_HW_PARAM_PERIODS
);
1391 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES
,
1393 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1395 snd_hda_power_up(apcm
->codec
);
1396 err
= hinfo
->ops
.open(hinfo
, apcm
->codec
, substream
);
1398 azx_release_device(azx_dev
);
1399 snd_hda_power_down(apcm
->codec
);
1400 mutex_unlock(&chip
->open_mutex
);
1403 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1404 azx_dev
->substream
= substream
;
1405 azx_dev
->running
= 0;
1406 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1408 runtime
->private_data
= azx_dev
;
1409 snd_pcm_set_sync(substream
);
1410 mutex_unlock(&chip
->open_mutex
);
1412 azx_stream_reset(chip
, azx_dev
);
1416 static int azx_pcm_close(struct snd_pcm_substream
*substream
)
1418 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1419 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1420 struct azx
*chip
= apcm
->chip
;
1421 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1422 unsigned long flags
;
1424 mutex_lock(&chip
->open_mutex
);
1425 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1426 azx_dev
->substream
= NULL
;
1427 azx_dev
->running
= 0;
1428 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1429 azx_release_device(azx_dev
);
1430 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1431 snd_hda_power_down(apcm
->codec
);
1432 mutex_unlock(&chip
->open_mutex
);
1436 static int azx_pcm_hw_params(struct snd_pcm_substream
*substream
,
1437 struct snd_pcm_hw_params
*hw_params
)
1439 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1441 azx_dev
->bufsize
= 0;
1442 azx_dev
->period_bytes
= 0;
1443 azx_dev
->format_val
= 0;
1444 return snd_pcm_lib_malloc_pages(substream
,
1445 params_buffer_bytes(hw_params
));
1448 static int azx_pcm_hw_free(struct snd_pcm_substream
*substream
)
1450 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1451 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1452 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1454 /* reset BDL address */
1455 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1456 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1457 azx_sd_writel(azx_dev
, SD_CTL
, 0);
1458 azx_dev
->bufsize
= 0;
1459 azx_dev
->period_bytes
= 0;
1460 azx_dev
->format_val
= 0;
1462 hinfo
->ops
.cleanup(hinfo
, apcm
->codec
, substream
);
1464 return snd_pcm_lib_free_pages(substream
);
1467 static int azx_pcm_prepare(struct snd_pcm_substream
*substream
)
1469 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1470 struct azx
*chip
= apcm
->chip
;
1471 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1472 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1473 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1474 unsigned int bufsize
, period_bytes
, format_val
;
1477 format_val
= snd_hda_calc_stream_format(runtime
->rate
,
1482 snd_printk(KERN_ERR SFX
1483 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1484 runtime
->rate
, runtime
->channels
, runtime
->format
);
1488 bufsize
= snd_pcm_lib_buffer_bytes(substream
);
1489 period_bytes
= snd_pcm_lib_period_bytes(substream
);
1491 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1492 bufsize
, format_val
);
1494 if (bufsize
!= azx_dev
->bufsize
||
1495 period_bytes
!= azx_dev
->period_bytes
||
1496 format_val
!= azx_dev
->format_val
) {
1497 azx_dev
->bufsize
= bufsize
;
1498 azx_dev
->period_bytes
= period_bytes
;
1499 azx_dev
->format_val
= format_val
;
1500 err
= azx_setup_periods(chip
, substream
, azx_dev
);
1505 azx_setup_controller(chip
, azx_dev
);
1506 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1507 azx_dev
->fifo_size
= azx_sd_readw(azx_dev
, SD_FIFOSIZE
) + 1;
1509 azx_dev
->fifo_size
= 0;
1511 return hinfo
->ops
.prepare(hinfo
, apcm
->codec
, azx_dev
->stream_tag
,
1512 azx_dev
->format_val
, substream
);
1515 static int azx_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
)
1517 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1518 struct azx
*chip
= apcm
->chip
;
1519 struct azx_dev
*azx_dev
;
1520 struct snd_pcm_substream
*s
;
1521 int start
, nsync
= 0, sbits
= 0;
1525 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1526 case SNDRV_PCM_TRIGGER_RESUME
:
1527 case SNDRV_PCM_TRIGGER_START
:
1530 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1531 case SNDRV_PCM_TRIGGER_SUSPEND
:
1532 case SNDRV_PCM_TRIGGER_STOP
:
1539 snd_pcm_group_for_each_entry(s
, substream
) {
1540 if (s
->pcm
->card
!= substream
->pcm
->card
)
1542 azx_dev
= get_azx_dev(s
);
1543 sbits
|= 1 << azx_dev
->index
;
1545 snd_pcm_trigger_done(s
, substream
);
1548 spin_lock(&chip
->reg_lock
);
1550 /* first, set SYNC bits of corresponding streams */
1551 azx_writel(chip
, SYNC
, azx_readl(chip
, SYNC
) | sbits
);
1553 snd_pcm_group_for_each_entry(s
, substream
) {
1554 if (s
->pcm
->card
!= substream
->pcm
->card
)
1556 azx_dev
= get_azx_dev(s
);
1558 azx_stream_start(chip
, azx_dev
);
1560 azx_stream_stop(chip
, azx_dev
);
1561 azx_dev
->running
= start
;
1563 spin_unlock(&chip
->reg_lock
);
1567 /* wait until all FIFOs get ready */
1568 for (timeout
= 5000; timeout
; timeout
--) {
1570 snd_pcm_group_for_each_entry(s
, substream
) {
1571 if (s
->pcm
->card
!= substream
->pcm
->card
)
1573 azx_dev
= get_azx_dev(s
);
1574 if (!(azx_sd_readb(azx_dev
, SD_STS
) &
1583 /* wait until all RUN bits are cleared */
1584 for (timeout
= 5000; timeout
; timeout
--) {
1586 snd_pcm_group_for_each_entry(s
, substream
) {
1587 if (s
->pcm
->card
!= substream
->pcm
->card
)
1589 azx_dev
= get_azx_dev(s
);
1590 if (azx_sd_readb(azx_dev
, SD_CTL
) &
1600 spin_lock(&chip
->reg_lock
);
1601 /* reset SYNC bits */
1602 azx_writel(chip
, SYNC
, azx_readl(chip
, SYNC
) & ~sbits
);
1603 spin_unlock(&chip
->reg_lock
);
1608 /* get the current DMA position with correction on VIA chips */
1609 static unsigned int azx_via_get_position(struct azx
*chip
,
1610 struct azx_dev
*azx_dev
)
1612 unsigned int link_pos
, mini_pos
, bound_pos
;
1613 unsigned int mod_link_pos
, mod_dma_pos
, mod_mini_pos
;
1614 unsigned int fifo_size
;
1616 link_pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1617 if (azx_dev
->index
>= 4) {
1618 /* Playback, no problem using link position */
1624 * use mod to get the DMA position just like old chipset
1626 mod_dma_pos
= le32_to_cpu(*azx_dev
->posbuf
);
1627 mod_dma_pos
%= azx_dev
->period_bytes
;
1629 /* azx_dev->fifo_size can't get FIFO size of in stream.
1630 * Get from base address + offset.
1632 fifo_size
= readw(chip
->remap_addr
+ VIA_IN_STREAM0_FIFO_SIZE_OFFSET
);
1634 if (azx_dev
->insufficient
) {
1635 /* Link position never gather than FIFO size */
1636 if (link_pos
<= fifo_size
)
1639 azx_dev
->insufficient
= 0;
1642 if (link_pos
<= fifo_size
)
1643 mini_pos
= azx_dev
->bufsize
+ link_pos
- fifo_size
;
1645 mini_pos
= link_pos
- fifo_size
;
1647 /* Find nearest previous boudary */
1648 mod_mini_pos
= mini_pos
% azx_dev
->period_bytes
;
1649 mod_link_pos
= link_pos
% azx_dev
->period_bytes
;
1650 if (mod_link_pos
>= fifo_size
)
1651 bound_pos
= link_pos
- mod_link_pos
;
1652 else if (mod_dma_pos
>= mod_mini_pos
)
1653 bound_pos
= mini_pos
- mod_mini_pos
;
1655 bound_pos
= mini_pos
- mod_mini_pos
+ azx_dev
->period_bytes
;
1656 if (bound_pos
>= azx_dev
->bufsize
)
1660 /* Calculate real DMA position we want */
1661 return bound_pos
+ mod_dma_pos
;
1664 static unsigned int azx_get_position(struct azx
*chip
,
1665 struct azx_dev
*azx_dev
)
1669 if (chip
->via_dmapos_patch
)
1670 pos
= azx_via_get_position(chip
, azx_dev
);
1671 else if (chip
->position_fix
== POS_FIX_POSBUF
||
1672 chip
->position_fix
== POS_FIX_AUTO
) {
1673 /* use the position buffer */
1674 pos
= le32_to_cpu(*azx_dev
->posbuf
);
1677 pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1679 if (pos
>= azx_dev
->bufsize
)
1684 static snd_pcm_uframes_t
azx_pcm_pointer(struct snd_pcm_substream
*substream
)
1686 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1687 struct azx
*chip
= apcm
->chip
;
1688 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1689 return bytes_to_frames(substream
->runtime
,
1690 azx_get_position(chip
, azx_dev
));
1694 * Check whether the current DMA position is acceptable for updating
1695 * periods. Returns non-zero if it's OK.
1697 * Many HD-audio controllers appear pretty inaccurate about
1698 * the update-IRQ timing. The IRQ is issued before actually the
1699 * data is processed. So, we need to process it afterwords in a
1702 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
)
1706 pos
= azx_get_position(chip
, azx_dev
);
1707 if (chip
->position_fix
== POS_FIX_AUTO
) {
1710 "hda-intel: Invalid position buffer, "
1711 "using LPIB read method instead.\n");
1712 chip
->position_fix
= POS_FIX_LPIB
;
1713 pos
= azx_get_position(chip
, azx_dev
);
1715 chip
->position_fix
= POS_FIX_POSBUF
;
1718 if (!bdl_pos_adj
[chip
->dev_index
])
1719 return 1; /* no delayed ack */
1720 if (pos
% azx_dev
->period_bytes
> azx_dev
->period_bytes
/ 2)
1721 return 0; /* NG - it's below the period boundary */
1722 return 1; /* OK, it's fine */
1726 * The work for pending PCM period updates.
1728 static void azx_irq_pending_work(struct work_struct
*work
)
1730 struct azx
*chip
= container_of(work
, struct azx
, irq_pending_work
);
1733 if (!chip
->irq_pending_warned
) {
1735 "hda-intel: IRQ timing workaround is activated "
1736 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1737 chip
->card
->number
);
1738 chip
->irq_pending_warned
= 1;
1743 spin_lock_irq(&chip
->reg_lock
);
1744 for (i
= 0; i
< chip
->num_streams
; i
++) {
1745 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
1746 if (!azx_dev
->irq_pending
||
1747 !azx_dev
->substream
||
1750 if (azx_position_ok(chip
, azx_dev
)) {
1751 azx_dev
->irq_pending
= 0;
1752 spin_unlock(&chip
->reg_lock
);
1753 snd_pcm_period_elapsed(azx_dev
->substream
);
1754 spin_lock(&chip
->reg_lock
);
1758 spin_unlock_irq(&chip
->reg_lock
);
1765 /* clear irq_pending flags and assure no on-going workq */
1766 static void azx_clear_irq_pending(struct azx
*chip
)
1770 spin_lock_irq(&chip
->reg_lock
);
1771 for (i
= 0; i
< chip
->num_streams
; i
++)
1772 chip
->azx_dev
[i
].irq_pending
= 0;
1773 spin_unlock_irq(&chip
->reg_lock
);
1776 static struct snd_pcm_ops azx_pcm_ops
= {
1777 .open
= azx_pcm_open
,
1778 .close
= azx_pcm_close
,
1779 .ioctl
= snd_pcm_lib_ioctl
,
1780 .hw_params
= azx_pcm_hw_params
,
1781 .hw_free
= azx_pcm_hw_free
,
1782 .prepare
= azx_pcm_prepare
,
1783 .trigger
= azx_pcm_trigger
,
1784 .pointer
= azx_pcm_pointer
,
1785 .page
= snd_pcm_sgbuf_ops_page
,
1788 static void azx_pcm_free(struct snd_pcm
*pcm
)
1790 struct azx_pcm
*apcm
= pcm
->private_data
;
1792 apcm
->chip
->pcm
[pcm
->device
] = NULL
;
1798 azx_attach_pcm_stream(struct hda_bus
*bus
, struct hda_codec
*codec
,
1799 struct hda_pcm
*cpcm
)
1801 struct azx
*chip
= bus
->private_data
;
1802 struct snd_pcm
*pcm
;
1803 struct azx_pcm
*apcm
;
1804 int pcm_dev
= cpcm
->device
;
1807 if (pcm_dev
>= AZX_MAX_PCMS
) {
1808 snd_printk(KERN_ERR SFX
"Invalid PCM device number %d\n",
1812 if (chip
->pcm
[pcm_dev
]) {
1813 snd_printk(KERN_ERR SFX
"PCM %d already exists\n", pcm_dev
);
1816 err
= snd_pcm_new(chip
->card
, cpcm
->name
, pcm_dev
,
1817 cpcm
->stream
[SNDRV_PCM_STREAM_PLAYBACK
].substreams
,
1818 cpcm
->stream
[SNDRV_PCM_STREAM_CAPTURE
].substreams
,
1822 strcpy(pcm
->name
, cpcm
->name
);
1823 apcm
= kzalloc(sizeof(*apcm
), GFP_KERNEL
);
1827 apcm
->codec
= codec
;
1828 pcm
->private_data
= apcm
;
1829 pcm
->private_free
= azx_pcm_free
;
1830 if (cpcm
->pcm_type
== HDA_PCM_TYPE_MODEM
)
1831 pcm
->dev_class
= SNDRV_PCM_CLASS_MODEM
;
1832 chip
->pcm
[pcm_dev
] = pcm
;
1834 for (s
= 0; s
< 2; s
++) {
1835 apcm
->hinfo
[s
] = &cpcm
->stream
[s
];
1836 if (cpcm
->stream
[s
].substreams
)
1837 snd_pcm_set_ops(pcm
, s
, &azx_pcm_ops
);
1839 /* buffer pre-allocation */
1840 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV_SG
,
1841 snd_dma_pci_data(chip
->pci
),
1842 1024 * 64, 32 * 1024 * 1024);
1847 * mixer creation - all stuff is implemented in hda module
1849 static int __devinit
azx_mixer_create(struct azx
*chip
)
1851 return snd_hda_build_controls(chip
->bus
);
1856 * initialize SD streams
1858 static int __devinit
azx_init_stream(struct azx
*chip
)
1862 /* initialize each stream (aka device)
1863 * assign the starting bdl address to each stream (device)
1866 for (i
= 0; i
< chip
->num_streams
; i
++) {
1867 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
1868 azx_dev
->posbuf
= (u32 __iomem
*)(chip
->posbuf
.area
+ i
* 8);
1869 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1870 azx_dev
->sd_addr
= chip
->remap_addr
+ (0x20 * i
+ 0x80);
1871 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1872 azx_dev
->sd_int_sta_mask
= 1 << i
;
1873 /* stream tag: must be non-zero and unique */
1875 azx_dev
->stream_tag
= i
+ 1;
1881 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
)
1883 if (request_irq(chip
->pci
->irq
, azx_interrupt
,
1884 chip
->msi
? 0 : IRQF_SHARED
,
1885 "HDA Intel", chip
)) {
1886 printk(KERN_ERR
"hda-intel: unable to grab IRQ %d, "
1887 "disabling device\n", chip
->pci
->irq
);
1889 snd_card_disconnect(chip
->card
);
1892 chip
->irq
= chip
->pci
->irq
;
1893 pci_intx(chip
->pci
, !chip
->msi
);
1898 static void azx_stop_chip(struct azx
*chip
)
1900 if (!chip
->initialized
)
1903 /* disable interrupts */
1904 azx_int_disable(chip
);
1905 azx_int_clear(chip
);
1907 /* disable CORB/RIRB */
1908 azx_free_cmd_io(chip
);
1910 /* disable position buffer */
1911 azx_writel(chip
, DPLBASE
, 0);
1912 azx_writel(chip
, DPUBASE
, 0);
1914 chip
->initialized
= 0;
1917 #ifdef CONFIG_SND_HDA_POWER_SAVE
1918 /* power-up/down the controller */
1919 static void azx_power_notify(struct hda_bus
*bus
)
1921 struct azx
*chip
= bus
->private_data
;
1922 struct hda_codec
*c
;
1925 list_for_each_entry(c
, &bus
->codec_list
, list
) {
1932 azx_init_chip(chip
);
1933 else if (chip
->running
&& power_save_controller
)
1934 azx_stop_chip(chip
);
1936 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1943 static int snd_hda_codecs_inuse(struct hda_bus
*bus
)
1945 struct hda_codec
*codec
;
1947 list_for_each_entry(codec
, &bus
->codec_list
, list
) {
1948 if (snd_hda_codec_needs_resume(codec
))
1954 static int azx_suspend(struct pci_dev
*pci
, pm_message_t state
)
1956 struct snd_card
*card
= pci_get_drvdata(pci
);
1957 struct azx
*chip
= card
->private_data
;
1960 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
1961 azx_clear_irq_pending(chip
);
1962 for (i
= 0; i
< AZX_MAX_PCMS
; i
++)
1963 snd_pcm_suspend_all(chip
->pcm
[i
]);
1964 if (chip
->initialized
)
1965 snd_hda_suspend(chip
->bus
, state
);
1966 azx_stop_chip(chip
);
1967 if (chip
->irq
>= 0) {
1968 free_irq(chip
->irq
, chip
);
1972 pci_disable_msi(chip
->pci
);
1973 pci_disable_device(pci
);
1974 pci_save_state(pci
);
1975 pci_set_power_state(pci
, pci_choose_state(pci
, state
));
1979 static int azx_resume(struct pci_dev
*pci
)
1981 struct snd_card
*card
= pci_get_drvdata(pci
);
1982 struct azx
*chip
= card
->private_data
;
1984 pci_set_power_state(pci
, PCI_D0
);
1985 pci_restore_state(pci
);
1986 if (pci_enable_device(pci
) < 0) {
1987 printk(KERN_ERR
"hda-intel: pci_enable_device failed, "
1988 "disabling device\n");
1989 snd_card_disconnect(card
);
1992 pci_set_master(pci
);
1994 if (pci_enable_msi(pci
) < 0)
1996 if (azx_acquire_irq(chip
, 1) < 0)
2000 if (snd_hda_codecs_inuse(chip
->bus
))
2001 azx_init_chip(chip
);
2003 snd_hda_resume(chip
->bus
);
2004 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
2007 #endif /* CONFIG_PM */
2011 * reboot notifier for hang-up problem at power-down
2013 static int azx_halt(struct notifier_block
*nb
, unsigned long event
, void *buf
)
2015 struct azx
*chip
= container_of(nb
, struct azx
, reboot_notifier
);
2016 azx_stop_chip(chip
);
2020 static void azx_notifier_register(struct azx
*chip
)
2022 chip
->reboot_notifier
.notifier_call
= azx_halt
;
2023 register_reboot_notifier(&chip
->reboot_notifier
);
2026 static void azx_notifier_unregister(struct azx
*chip
)
2028 if (chip
->reboot_notifier
.notifier_call
)
2029 unregister_reboot_notifier(&chip
->reboot_notifier
);
2035 static int azx_free(struct azx
*chip
)
2039 azx_notifier_unregister(chip
);
2041 if (chip
->initialized
) {
2042 azx_clear_irq_pending(chip
);
2043 for (i
= 0; i
< chip
->num_streams
; i
++)
2044 azx_stream_stop(chip
, &chip
->azx_dev
[i
]);
2045 azx_stop_chip(chip
);
2049 free_irq(chip
->irq
, (void*)chip
);
2051 pci_disable_msi(chip
->pci
);
2052 if (chip
->remap_addr
)
2053 iounmap(chip
->remap_addr
);
2055 if (chip
->azx_dev
) {
2056 for (i
= 0; i
< chip
->num_streams
; i
++)
2057 if (chip
->azx_dev
[i
].bdl
.area
)
2058 snd_dma_free_pages(&chip
->azx_dev
[i
].bdl
);
2061 snd_dma_free_pages(&chip
->rb
);
2062 if (chip
->posbuf
.area
)
2063 snd_dma_free_pages(&chip
->posbuf
);
2064 pci_release_regions(chip
->pci
);
2065 pci_disable_device(chip
->pci
);
2066 kfree(chip
->azx_dev
);
2072 static int azx_dev_free(struct snd_device
*device
)
2074 return azx_free(device
->device_data
);
2078 * white/black-listing for position_fix
2080 static struct snd_pci_quirk position_fix_list
[] __devinitdata
= {
2081 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB
),
2082 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB
),
2083 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB
),
2087 static int __devinit
check_position_fix(struct azx
*chip
, int fix
)
2089 const struct snd_pci_quirk
*q
;
2093 case POS_FIX_POSBUF
:
2097 /* Check VIA/ATI HD Audio Controller exist */
2098 switch (chip
->driver_type
) {
2099 case AZX_DRIVER_VIA
:
2100 case AZX_DRIVER_ATI
:
2101 chip
->via_dmapos_patch
= 1;
2102 /* Use link position directly, avoid any transfer problem. */
2103 return POS_FIX_LPIB
;
2105 chip
->via_dmapos_patch
= 0;
2107 q
= snd_pci_quirk_lookup(chip
->pci
, position_fix_list
);
2110 "hda_intel: position_fix set to %d "
2111 "for device %04x:%04x\n",
2112 q
->value
, q
->subvendor
, q
->subdevice
);
2115 return POS_FIX_AUTO
;
2119 * black-lists for probe_mask
2121 static struct snd_pci_quirk probe_mask_list
[] __devinitdata
= {
2122 /* Thinkpad often breaks the controller communication when accessing
2123 * to the non-working (or non-existing) modem codec slot.
2125 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2126 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2127 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2129 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2130 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2131 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2132 /* forced codec slots */
2133 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2137 #define AZX_FORCE_CODEC_MASK 0x100
2139 static void __devinit
check_probe_mask(struct azx
*chip
, int dev
)
2141 const struct snd_pci_quirk
*q
;
2143 chip
->codec_probe_mask
= probe_mask
[dev
];
2144 if (chip
->codec_probe_mask
== -1) {
2145 q
= snd_pci_quirk_lookup(chip
->pci
, probe_mask_list
);
2148 "hda_intel: probe_mask set to 0x%x "
2149 "for device %04x:%04x\n",
2150 q
->value
, q
->subvendor
, q
->subdevice
);
2151 chip
->codec_probe_mask
= q
->value
;
2155 /* check forced option */
2156 if (chip
->codec_probe_mask
!= -1 &&
2157 (chip
->codec_probe_mask
& AZX_FORCE_CODEC_MASK
)) {
2158 chip
->codec_mask
= chip
->codec_probe_mask
& 0xff;
2159 printk(KERN_INFO
"hda_intel: codec_mask forced to 0x%x\n",
2168 static int __devinit
azx_create(struct snd_card
*card
, struct pci_dev
*pci
,
2169 int dev
, int driver_type
,
2174 unsigned short gcap
;
2175 static struct snd_device_ops ops
= {
2176 .dev_free
= azx_dev_free
,
2181 err
= pci_enable_device(pci
);
2185 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
2187 snd_printk(KERN_ERR SFX
"cannot allocate chip\n");
2188 pci_disable_device(pci
);
2192 spin_lock_init(&chip
->reg_lock
);
2193 mutex_init(&chip
->open_mutex
);
2197 chip
->driver_type
= driver_type
;
2198 chip
->msi
= enable_msi
;
2199 chip
->dev_index
= dev
;
2200 INIT_WORK(&chip
->irq_pending_work
, azx_irq_pending_work
);
2202 chip
->position_fix
= check_position_fix(chip
, position_fix
[dev
]);
2203 check_probe_mask(chip
, dev
);
2205 chip
->single_cmd
= single_cmd
;
2207 if (bdl_pos_adj
[dev
] < 0) {
2208 switch (chip
->driver_type
) {
2209 case AZX_DRIVER_ICH
:
2210 bdl_pos_adj
[dev
] = 1;
2213 bdl_pos_adj
[dev
] = 32;
2218 #if BITS_PER_LONG != 64
2219 /* Fix up base address on ULI M5461 */
2220 if (chip
->driver_type
== AZX_DRIVER_ULI
) {
2222 pci_read_config_word(pci
, 0x40, &tmp3
);
2223 pci_write_config_word(pci
, 0x40, tmp3
| 0x10);
2224 pci_write_config_dword(pci
, PCI_BASE_ADDRESS_1
, 0);
2228 err
= pci_request_regions(pci
, "ICH HD audio");
2231 pci_disable_device(pci
);
2235 chip
->addr
= pci_resource_start(pci
, 0);
2236 chip
->remap_addr
= pci_ioremap_bar(pci
, 0);
2237 if (chip
->remap_addr
== NULL
) {
2238 snd_printk(KERN_ERR SFX
"ioremap error\n");
2244 if (pci_enable_msi(pci
) < 0)
2247 if (azx_acquire_irq(chip
, 0) < 0) {
2252 pci_set_master(pci
);
2253 synchronize_irq(chip
->irq
);
2255 gcap
= azx_readw(chip
, GCAP
);
2256 snd_printdd("chipset global capabilities = 0x%x\n", gcap
);
2258 /* ATI chips seems buggy about 64bit DMA addresses */
2259 if (chip
->driver_type
== AZX_DRIVER_ATI
)
2262 /* allow 64bit DMA address if supported by H/W */
2263 if ((gcap
& 0x01) && !pci_set_dma_mask(pci
, DMA_64BIT_MASK
))
2264 pci_set_consistent_dma_mask(pci
, DMA_64BIT_MASK
);
2266 pci_set_dma_mask(pci
, DMA_32BIT_MASK
);
2267 pci_set_consistent_dma_mask(pci
, DMA_32BIT_MASK
);
2270 /* read number of streams from GCAP register instead of using
2273 chip
->capture_streams
= (gcap
>> 8) & 0x0f;
2274 chip
->playback_streams
= (gcap
>> 12) & 0x0f;
2275 if (!chip
->playback_streams
&& !chip
->capture_streams
) {
2276 /* gcap didn't give any info, switching to old method */
2278 switch (chip
->driver_type
) {
2279 case AZX_DRIVER_ULI
:
2280 chip
->playback_streams
= ULI_NUM_PLAYBACK
;
2281 chip
->capture_streams
= ULI_NUM_CAPTURE
;
2283 case AZX_DRIVER_ATIHDMI
:
2284 chip
->playback_streams
= ATIHDMI_NUM_PLAYBACK
;
2285 chip
->capture_streams
= ATIHDMI_NUM_CAPTURE
;
2287 case AZX_DRIVER_GENERIC
:
2289 chip
->playback_streams
= ICH6_NUM_PLAYBACK
;
2290 chip
->capture_streams
= ICH6_NUM_CAPTURE
;
2294 chip
->capture_index_offset
= 0;
2295 chip
->playback_index_offset
= chip
->capture_streams
;
2296 chip
->num_streams
= chip
->playback_streams
+ chip
->capture_streams
;
2297 chip
->azx_dev
= kcalloc(chip
->num_streams
, sizeof(*chip
->azx_dev
),
2299 if (!chip
->azx_dev
) {
2300 snd_printk(KERN_ERR
"cannot malloc azx_dev\n");
2304 for (i
= 0; i
< chip
->num_streams
; i
++) {
2305 /* allocate memory for the BDL for each stream */
2306 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
2307 snd_dma_pci_data(chip
->pci
),
2308 BDL_SIZE
, &chip
->azx_dev
[i
].bdl
);
2310 snd_printk(KERN_ERR SFX
"cannot allocate BDL\n");
2314 /* allocate memory for the position buffer */
2315 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
2316 snd_dma_pci_data(chip
->pci
),
2317 chip
->num_streams
* 8, &chip
->posbuf
);
2319 snd_printk(KERN_ERR SFX
"cannot allocate posbuf\n");
2322 /* allocate CORB/RIRB */
2323 if (!chip
->single_cmd
) {
2324 err
= azx_alloc_cmd_io(chip
);
2329 /* initialize streams */
2330 azx_init_stream(chip
);
2332 /* initialize chip */
2334 azx_init_chip(chip
);
2336 /* codec detection */
2337 if (!chip
->codec_mask
) {
2338 snd_printk(KERN_ERR SFX
"no codecs found!\n");
2343 err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
);
2345 snd_printk(KERN_ERR SFX
"Error creating device [card]!\n");
2349 strcpy(card
->driver
, "HDA-Intel");
2350 strcpy(card
->shortname
, driver_short_names
[chip
->driver_type
]);
2351 sprintf(card
->longname
, "%s at 0x%lx irq %i",
2352 card
->shortname
, chip
->addr
, chip
->irq
);
2362 static void power_down_all_codecs(struct azx
*chip
)
2364 #ifdef CONFIG_SND_HDA_POWER_SAVE
2365 /* The codecs were powered up in snd_hda_codec_new().
2366 * Now all initialization done, so turn them down if possible
2368 struct hda_codec
*codec
;
2369 list_for_each_entry(codec
, &chip
->bus
->codec_list
, list
) {
2370 snd_hda_power_down(codec
);
2375 static int __devinit
azx_probe(struct pci_dev
*pci
,
2376 const struct pci_device_id
*pci_id
)
2379 struct snd_card
*card
;
2383 if (dev
>= SNDRV_CARDS
)
2390 card
= snd_card_new(index
[dev
], id
[dev
], THIS_MODULE
, 0);
2392 snd_printk(KERN_ERR SFX
"Error creating card!\n");
2396 err
= azx_create(card
, pci
, dev
, pci_id
->driver_data
, &chip
);
2399 card
->private_data
= chip
;
2401 /* create codec instances */
2402 err
= azx_codec_create(chip
, model
[dev
], probe_only
[dev
]);
2406 /* create PCM streams */
2407 err
= snd_hda_build_pcms(chip
->bus
);
2411 /* create mixer controls */
2412 err
= azx_mixer_create(chip
);
2416 snd_card_set_dev(card
, &pci
->dev
);
2418 err
= snd_card_register(card
);
2422 pci_set_drvdata(pci
, card
);
2424 power_down_all_codecs(chip
);
2425 azx_notifier_register(chip
);
2430 snd_card_free(card
);
2434 static void __devexit
azx_remove(struct pci_dev
*pci
)
2436 snd_card_free(pci_get_drvdata(pci
));
2437 pci_set_drvdata(pci
, NULL
);
2441 static struct pci_device_id azx_ids
[] = {
2443 { PCI_DEVICE(0x8086, 0x2668), .driver_data
= AZX_DRIVER_ICH
},
2444 { PCI_DEVICE(0x8086, 0x27d8), .driver_data
= AZX_DRIVER_ICH
},
2445 { PCI_DEVICE(0x8086, 0x269a), .driver_data
= AZX_DRIVER_ICH
},
2446 { PCI_DEVICE(0x8086, 0x284b), .driver_data
= AZX_DRIVER_ICH
},
2447 { PCI_DEVICE(0x8086, 0x2911), .driver_data
= AZX_DRIVER_ICH
},
2448 { PCI_DEVICE(0x8086, 0x293e), .driver_data
= AZX_DRIVER_ICH
},
2449 { PCI_DEVICE(0x8086, 0x293f), .driver_data
= AZX_DRIVER_ICH
},
2450 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data
= AZX_DRIVER_ICH
},
2451 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data
= AZX_DRIVER_ICH
},
2453 { PCI_DEVICE(0x8086, 0x3b56), .driver_data
= AZX_DRIVER_ICH
},
2455 { PCI_DEVICE(0x8086, 0x811b), .driver_data
= AZX_DRIVER_SCH
},
2456 /* ATI SB 450/600 */
2457 { PCI_DEVICE(0x1002, 0x437b), .driver_data
= AZX_DRIVER_ATI
},
2458 { PCI_DEVICE(0x1002, 0x4383), .driver_data
= AZX_DRIVER_ATI
},
2460 { PCI_DEVICE(0x1002, 0x793b), .driver_data
= AZX_DRIVER_ATIHDMI
},
2461 { PCI_DEVICE(0x1002, 0x7919), .driver_data
= AZX_DRIVER_ATIHDMI
},
2462 { PCI_DEVICE(0x1002, 0x960f), .driver_data
= AZX_DRIVER_ATIHDMI
},
2463 { PCI_DEVICE(0x1002, 0x970f), .driver_data
= AZX_DRIVER_ATIHDMI
},
2464 { PCI_DEVICE(0x1002, 0xaa00), .driver_data
= AZX_DRIVER_ATIHDMI
},
2465 { PCI_DEVICE(0x1002, 0xaa08), .driver_data
= AZX_DRIVER_ATIHDMI
},
2466 { PCI_DEVICE(0x1002, 0xaa10), .driver_data
= AZX_DRIVER_ATIHDMI
},
2467 { PCI_DEVICE(0x1002, 0xaa18), .driver_data
= AZX_DRIVER_ATIHDMI
},
2468 { PCI_DEVICE(0x1002, 0xaa20), .driver_data
= AZX_DRIVER_ATIHDMI
},
2469 { PCI_DEVICE(0x1002, 0xaa28), .driver_data
= AZX_DRIVER_ATIHDMI
},
2470 { PCI_DEVICE(0x1002, 0xaa30), .driver_data
= AZX_DRIVER_ATIHDMI
},
2471 { PCI_DEVICE(0x1002, 0xaa38), .driver_data
= AZX_DRIVER_ATIHDMI
},
2472 { PCI_DEVICE(0x1002, 0xaa40), .driver_data
= AZX_DRIVER_ATIHDMI
},
2473 { PCI_DEVICE(0x1002, 0xaa48), .driver_data
= AZX_DRIVER_ATIHDMI
},
2474 /* VIA VT8251/VT8237A */
2475 { PCI_DEVICE(0x1106, 0x3288), .driver_data
= AZX_DRIVER_VIA
},
2477 { PCI_DEVICE(0x1039, 0x7502), .driver_data
= AZX_DRIVER_SIS
},
2479 { PCI_DEVICE(0x10b9, 0x5461), .driver_data
= AZX_DRIVER_ULI
},
2481 { PCI_DEVICE(0x10de, 0x026c), .driver_data
= AZX_DRIVER_NVIDIA
},
2482 { PCI_DEVICE(0x10de, 0x0371), .driver_data
= AZX_DRIVER_NVIDIA
},
2483 { PCI_DEVICE(0x10de, 0x03e4), .driver_data
= AZX_DRIVER_NVIDIA
},
2484 { PCI_DEVICE(0x10de, 0x03f0), .driver_data
= AZX_DRIVER_NVIDIA
},
2485 { PCI_DEVICE(0x10de, 0x044a), .driver_data
= AZX_DRIVER_NVIDIA
},
2486 { PCI_DEVICE(0x10de, 0x044b), .driver_data
= AZX_DRIVER_NVIDIA
},
2487 { PCI_DEVICE(0x10de, 0x055c), .driver_data
= AZX_DRIVER_NVIDIA
},
2488 { PCI_DEVICE(0x10de, 0x055d), .driver_data
= AZX_DRIVER_NVIDIA
},
2489 { PCI_DEVICE(0x10de, 0x0774), .driver_data
= AZX_DRIVER_NVIDIA
},
2490 { PCI_DEVICE(0x10de, 0x0775), .driver_data
= AZX_DRIVER_NVIDIA
},
2491 { PCI_DEVICE(0x10de, 0x0776), .driver_data
= AZX_DRIVER_NVIDIA
},
2492 { PCI_DEVICE(0x10de, 0x0777), .driver_data
= AZX_DRIVER_NVIDIA
},
2493 { PCI_DEVICE(0x10de, 0x07fc), .driver_data
= AZX_DRIVER_NVIDIA
},
2494 { PCI_DEVICE(0x10de, 0x07fd), .driver_data
= AZX_DRIVER_NVIDIA
},
2495 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data
= AZX_DRIVER_NVIDIA
},
2496 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data
= AZX_DRIVER_NVIDIA
},
2497 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data
= AZX_DRIVER_NVIDIA
},
2498 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data
= AZX_DRIVER_NVIDIA
},
2499 { PCI_DEVICE(0x10de, 0x0d94), .driver_data
= AZX_DRIVER_NVIDIA
},
2500 { PCI_DEVICE(0x10de, 0x0d95), .driver_data
= AZX_DRIVER_NVIDIA
},
2501 { PCI_DEVICE(0x10de, 0x0d96), .driver_data
= AZX_DRIVER_NVIDIA
},
2502 { PCI_DEVICE(0x10de, 0x0d97), .driver_data
= AZX_DRIVER_NVIDIA
},
2504 { PCI_DEVICE(0x6549, 0x1200), .driver_data
= AZX_DRIVER_TERA
},
2505 /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2506 { PCI_DEVICE(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
),
2507 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
2508 .class_mask
= 0xffffff,
2509 .driver_data
= AZX_DRIVER_GENERIC
},
2512 MODULE_DEVICE_TABLE(pci
, azx_ids
);
2514 /* pci_driver definition */
2515 static struct pci_driver driver
= {
2516 .name
= "HDA Intel",
2517 .id_table
= azx_ids
,
2519 .remove
= __devexit_p(azx_remove
),
2521 .suspend
= azx_suspend
,
2522 .resume
= azx_resume
,
2526 static int __init
alsa_card_azx_init(void)
2528 return pci_register_driver(&driver
);
2531 static void __exit
alsa_card_azx_exit(void)
2533 pci_unregister_driver(&driver
);
2536 module_init(alsa_card_azx_init
)
2537 module_exit(alsa_card_azx_exit
)