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ALSA: hda - Remove superfluous DELAYED_INIT*_MARK
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65
66
67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
70 static char *model[SNDRV_CARDS];
71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int probe_only[SNDRV_CARDS];
75 static int jackpoll_ms[SNDRV_CARDS];
76 static bool single_cmd;
77 static int enable_msi = -1;
78 #ifdef CONFIG_SND_HDA_PATCH_LOADER
79 static char *patch[SNDRV_CARDS];
80 #endif
81 #ifdef CONFIG_SND_HDA_INPUT_BEEP
82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
83 CONFIG_SND_HDA_INPUT_BEEP_MODE};
84 #endif
85
86 module_param_array(index, int, NULL, 0444);
87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
88 module_param_array(id, charp, NULL, 0444);
89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
90 module_param_array(enable, bool, NULL, 0444);
91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
92 module_param_array(model, charp, NULL, 0444);
93 MODULE_PARM_DESC(model, "Use the given board model.");
94 module_param_array(position_fix, int, NULL, 0444);
95 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
96 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
97 module_param_array(bdl_pos_adj, int, NULL, 0644);
98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
99 module_param_array(probe_mask, int, NULL, 0444);
100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
101 module_param_array(probe_only, int, NULL, 0444);
102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
103 module_param_array(jackpoll_ms, int, NULL, 0444);
104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
105 module_param(single_cmd, bool, 0444);
106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
107 "(for debugging only).");
108 module_param(enable_msi, bint, 0444);
109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
111 module_param_array(patch, charp, NULL, 0444);
112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
113 #endif
114 #ifdef CONFIG_SND_HDA_INPUT_BEEP
115 module_param_array(beep_mode, bool, NULL, 0444);
116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
117 "(0=off, 1=on) (default=1).");
118 #endif
119
120 #ifdef CONFIG_PM
121 static int param_set_xint(const char *val, const struct kernel_param *kp);
122 static struct kernel_param_ops param_ops_xint = {
123 .set = param_set_xint,
124 .get = param_get_int,
125 };
126 #define param_check_xint param_check_int
127
128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
129 module_param(power_save, xint, 0644);
130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
131 "(in second, 0 = disable).");
132
133 /* reset the HD-audio controller in power save mode.
134 * this may give more power-saving, but will take longer time to
135 * wake up.
136 */
137 static bool power_save_controller = 1;
138 module_param(power_save_controller, bool, 0644);
139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
140 #endif /* CONFIG_PM */
141
142 static int align_buffer_size = -1;
143 module_param(align_buffer_size, bint, 0644);
144 MODULE_PARM_DESC(align_buffer_size,
145 "Force buffer and period sizes to be multiple of 128 bytes.");
146
147 #ifdef CONFIG_X86
148 static bool hda_snoop = true;
149 module_param_named(snoop, hda_snoop, bool, 0444);
150 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
151 #define azx_snoop(chip) (chip)->snoop
152 #else
153 #define hda_snoop true
154 #define azx_snoop(chip) true
155 #endif
156
157
158 MODULE_LICENSE("GPL");
159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160 "{Intel, ICH6M},"
161 "{Intel, ICH7},"
162 "{Intel, ESB2},"
163 "{Intel, ICH8},"
164 "{Intel, ICH9},"
165 "{Intel, ICH10},"
166 "{Intel, PCH},"
167 "{Intel, CPT},"
168 "{Intel, PPT},"
169 "{Intel, LPT},"
170 "{Intel, LPT_LP},"
171 "{Intel, HPT},"
172 "{Intel, PBG},"
173 "{Intel, SCH},"
174 "{ATI, SB450},"
175 "{ATI, SB600},"
176 "{ATI, RS600},"
177 "{ATI, RS690},"
178 "{ATI, RS780},"
179 "{ATI, R600},"
180 "{ATI, RV630},"
181 "{ATI, RV610},"
182 "{ATI, RV670},"
183 "{ATI, RV635},"
184 "{ATI, RV620},"
185 "{ATI, RV770},"
186 "{VIA, VT8251},"
187 "{VIA, VT8237A},"
188 "{SiS, SIS966},"
189 "{ULI, M5461}}");
190 MODULE_DESCRIPTION("Intel HDA driver");
191
192 #ifdef CONFIG_SND_VERBOSE_PRINTK
193 #define SFX /* nop */
194 #else
195 #define SFX "hda-intel "
196 #endif
197
198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
199 #ifdef CONFIG_SND_HDA_CODEC_HDMI
200 #define SUPPORT_VGA_SWITCHEROO
201 #endif
202 #endif
203
204
205 /*
206 * registers
207 */
208 #define ICH6_REG_GCAP 0x00
209 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
210 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
211 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
212 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
213 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
214 #define ICH6_REG_VMIN 0x02
215 #define ICH6_REG_VMAJ 0x03
216 #define ICH6_REG_OUTPAY 0x04
217 #define ICH6_REG_INPAY 0x06
218 #define ICH6_REG_GCTL 0x08
219 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
220 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
221 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
222 #define ICH6_REG_WAKEEN 0x0c
223 #define ICH6_REG_STATESTS 0x0e
224 #define ICH6_REG_GSTS 0x10
225 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
226 #define ICH6_REG_INTCTL 0x20
227 #define ICH6_REG_INTSTS 0x24
228 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
229 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
230 #define ICH6_REG_SSYNC 0x38
231 #define ICH6_REG_CORBLBASE 0x40
232 #define ICH6_REG_CORBUBASE 0x44
233 #define ICH6_REG_CORBWP 0x48
234 #define ICH6_REG_CORBRP 0x4a
235 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
236 #define ICH6_REG_CORBCTL 0x4c
237 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
238 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
239 #define ICH6_REG_CORBSTS 0x4d
240 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
241 #define ICH6_REG_CORBSIZE 0x4e
242
243 #define ICH6_REG_RIRBLBASE 0x50
244 #define ICH6_REG_RIRBUBASE 0x54
245 #define ICH6_REG_RIRBWP 0x58
246 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
247 #define ICH6_REG_RINTCNT 0x5a
248 #define ICH6_REG_RIRBCTL 0x5c
249 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
250 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
251 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
252 #define ICH6_REG_RIRBSTS 0x5d
253 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
254 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
255 #define ICH6_REG_RIRBSIZE 0x5e
256
257 #define ICH6_REG_IC 0x60
258 #define ICH6_REG_IR 0x64
259 #define ICH6_REG_IRS 0x68
260 #define ICH6_IRS_VALID (1<<1)
261 #define ICH6_IRS_BUSY (1<<0)
262
263 #define ICH6_REG_DPLBASE 0x70
264 #define ICH6_REG_DPUBASE 0x74
265 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
266
267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
269
270 /* stream register offsets from stream base */
271 #define ICH6_REG_SD_CTL 0x00
272 #define ICH6_REG_SD_STS 0x03
273 #define ICH6_REG_SD_LPIB 0x04
274 #define ICH6_REG_SD_CBL 0x08
275 #define ICH6_REG_SD_LVI 0x0c
276 #define ICH6_REG_SD_FIFOW 0x0e
277 #define ICH6_REG_SD_FIFOSIZE 0x10
278 #define ICH6_REG_SD_FORMAT 0x12
279 #define ICH6_REG_SD_BDLPL 0x18
280 #define ICH6_REG_SD_BDLPU 0x1c
281
282 /* PCI space */
283 #define ICH6_PCIREG_TCSEL 0x44
284
285 /*
286 * other constants
287 */
288
289 /* max number of SDs */
290 /* ICH, ATI and VIA have 4 playback and 4 capture */
291 #define ICH6_NUM_CAPTURE 4
292 #define ICH6_NUM_PLAYBACK 4
293
294 /* ULI has 6 playback and 5 capture */
295 #define ULI_NUM_CAPTURE 5
296 #define ULI_NUM_PLAYBACK 6
297
298 /* ATI HDMI has 1 playback and 0 capture */
299 #define ATIHDMI_NUM_CAPTURE 0
300 #define ATIHDMI_NUM_PLAYBACK 1
301
302 /* TERA has 4 playback and 3 capture */
303 #define TERA_NUM_CAPTURE 3
304 #define TERA_NUM_PLAYBACK 4
305
306 /* this number is statically defined for simplicity */
307 #define MAX_AZX_DEV 16
308
309 /* max number of fragments - we may use more if allocating more pages for BDL */
310 #define BDL_SIZE 4096
311 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
312 #define AZX_MAX_FRAG 32
313 /* max buffer size - no h/w limit, you can increase as you like */
314 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
315
316 /* RIRB int mask: overrun[2], response[0] */
317 #define RIRB_INT_RESPONSE 0x01
318 #define RIRB_INT_OVERRUN 0x04
319 #define RIRB_INT_MASK 0x05
320
321 /* STATESTS int mask: S3,SD2,SD1,SD0 */
322 #define AZX_MAX_CODECS 8
323 #define AZX_DEFAULT_CODECS 4
324 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
325
326 /* SD_CTL bits */
327 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
328 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
329 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
330 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
331 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
332 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
333 #define SD_CTL_STREAM_TAG_SHIFT 20
334
335 /* SD_CTL and SD_STS */
336 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
337 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
338 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
339 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
340 SD_INT_COMPLETE)
341
342 /* SD_STS */
343 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
344
345 /* INTCTL and INTSTS */
346 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
347 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
348 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
349
350 /* below are so far hardcoded - should read registers in future */
351 #define ICH6_MAX_CORB_ENTRIES 256
352 #define ICH6_MAX_RIRB_ENTRIES 256
353
354 /* position fix mode */
355 enum {
356 POS_FIX_AUTO,
357 POS_FIX_LPIB,
358 POS_FIX_POSBUF,
359 POS_FIX_VIACOMBO,
360 POS_FIX_COMBO,
361 };
362
363 /* Defines for ATI HD Audio support in SB450 south bridge */
364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
366
367 /* Defines for Nvidia HDA support */
368 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
369 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
370 #define NVIDIA_HDA_ISTRM_COH 0x4d
371 #define NVIDIA_HDA_OSTRM_COH 0x4c
372 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
373
374 /* Defines for Intel SCH HDA snoop control */
375 #define INTEL_SCH_HDA_DEVC 0x78
376 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
377
378 /* Define IN stream 0 FIFO size offset in VIA controller */
379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
380 /* Define VIA HD Audio Device ID*/
381 #define VIA_HDAC_DEVICE_ID 0x3288
382
383 /* HD Audio class code */
384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
385
386 /*
387 */
388
389 struct azx_dev {
390 struct snd_dma_buffer bdl; /* BDL buffer */
391 u32 *posbuf; /* position buffer pointer */
392
393 unsigned int bufsize; /* size of the play buffer in bytes */
394 unsigned int period_bytes; /* size of the period in bytes */
395 unsigned int frags; /* number for period in the play buffer */
396 unsigned int fifo_size; /* FIFO size */
397 unsigned long start_wallclk; /* start + minimum wallclk */
398 unsigned long period_wallclk; /* wallclk for period */
399
400 void __iomem *sd_addr; /* stream descriptor pointer */
401
402 u32 sd_int_sta_mask; /* stream int status mask */
403
404 /* pcm support */
405 struct snd_pcm_substream *substream; /* assigned substream,
406 * set in PCM open
407 */
408 unsigned int format_val; /* format value to be set in the
409 * controller and the codec
410 */
411 unsigned char stream_tag; /* assigned stream */
412 unsigned char index; /* stream index */
413 int assigned_key; /* last device# key assigned to */
414
415 unsigned int opened :1;
416 unsigned int running :1;
417 unsigned int irq_pending :1;
418 /*
419 * For VIA:
420 * A flag to ensure DMA position is 0
421 * when link position is not greater than FIFO size
422 */
423 unsigned int insufficient :1;
424 unsigned int wc_marked:1;
425 unsigned int no_period_wakeup:1;
426
427 struct timecounter azx_tc;
428 struct cyclecounter azx_cc;
429 };
430
431 /* CORB/RIRB */
432 struct azx_rb {
433 u32 *buf; /* CORB/RIRB buffer
434 * Each CORB entry is 4byte, RIRB is 8byte
435 */
436 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
437 /* for RIRB */
438 unsigned short rp, wp; /* read/write pointers */
439 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
440 u32 res[AZX_MAX_CODECS]; /* last read value */
441 };
442
443 struct azx_pcm {
444 struct azx *chip;
445 struct snd_pcm *pcm;
446 struct hda_codec *codec;
447 struct hda_pcm_stream *hinfo[2];
448 struct list_head list;
449 };
450
451 struct azx {
452 struct snd_card *card;
453 struct pci_dev *pci;
454 int dev_index;
455
456 /* chip type specific */
457 int driver_type;
458 unsigned int driver_caps;
459 int playback_streams;
460 int playback_index_offset;
461 int capture_streams;
462 int capture_index_offset;
463 int num_streams;
464
465 /* pci resources */
466 unsigned long addr;
467 void __iomem *remap_addr;
468 int irq;
469
470 /* locks */
471 spinlock_t reg_lock;
472 struct mutex open_mutex;
473 struct completion probe_wait;
474
475 /* streams (x num_streams) */
476 struct azx_dev *azx_dev;
477
478 /* PCM */
479 struct list_head pcm_list; /* azx_pcm list */
480
481 /* HD codec */
482 unsigned short codec_mask;
483 int codec_probe_mask; /* copied from probe_mask option */
484 struct hda_bus *bus;
485 unsigned int beep_mode;
486
487 /* CORB/RIRB */
488 struct azx_rb corb;
489 struct azx_rb rirb;
490
491 /* CORB/RIRB and position buffers */
492 struct snd_dma_buffer rb;
493 struct snd_dma_buffer posbuf;
494
495 #ifdef CONFIG_SND_HDA_PATCH_LOADER
496 const struct firmware *fw;
497 #endif
498
499 /* flags */
500 int position_fix[2]; /* for both playback/capture streams */
501 int poll_count;
502 unsigned int running :1;
503 unsigned int initialized :1;
504 unsigned int single_cmd :1;
505 unsigned int polling_mode :1;
506 unsigned int msi :1;
507 unsigned int irq_pending_warned :1;
508 unsigned int probing :1; /* codec probing phase */
509 unsigned int snoop:1;
510 unsigned int align_buffer_size:1;
511 unsigned int region_requested:1;
512
513 /* VGA-switcheroo setup */
514 unsigned int use_vga_switcheroo:1;
515 unsigned int vga_switcheroo_registered:1;
516 unsigned int init_failed:1; /* delayed init failed */
517 unsigned int disabled:1; /* disabled by VGA-switcher */
518
519 /* for debugging */
520 unsigned int last_cmd[AZX_MAX_CODECS];
521
522 /* for pending irqs */
523 struct work_struct irq_pending_work;
524
525 /* reboot notifier (for mysterious hangup problem at power-down) */
526 struct notifier_block reboot_notifier;
527
528 /* card list (for power_save trigger) */
529 struct list_head list;
530 };
531
532 #define CREATE_TRACE_POINTS
533 #include "hda_intel_trace.h"
534
535 /* driver types */
536 enum {
537 AZX_DRIVER_ICH,
538 AZX_DRIVER_PCH,
539 AZX_DRIVER_SCH,
540 AZX_DRIVER_ATI,
541 AZX_DRIVER_ATIHDMI,
542 AZX_DRIVER_ATIHDMI_NS,
543 AZX_DRIVER_VIA,
544 AZX_DRIVER_SIS,
545 AZX_DRIVER_ULI,
546 AZX_DRIVER_NVIDIA,
547 AZX_DRIVER_TERA,
548 AZX_DRIVER_CTX,
549 AZX_DRIVER_CTHDA,
550 AZX_DRIVER_GENERIC,
551 AZX_NUM_DRIVERS, /* keep this as last entry */
552 };
553
554 /* driver quirks (capabilities) */
555 /* bits 0-7 are used for indicating driver type */
556 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
557 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
558 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
559 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
560 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
561 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
562 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
563 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
564 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
565 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
566 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
567 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
568 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
569 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
570 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
571 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
572 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
573 #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
574
575 /* quirks for Intel PCH */
576 #define AZX_DCAPS_INTEL_PCH \
577 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
578 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME)
579
580 /* quirks for ATI SB / AMD Hudson */
581 #define AZX_DCAPS_PRESET_ATI_SB \
582 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
583 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
584
585 /* quirks for ATI/AMD HDMI */
586 #define AZX_DCAPS_PRESET_ATI_HDMI \
587 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
588
589 /* quirks for Nvidia */
590 #define AZX_DCAPS_PRESET_NVIDIA \
591 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
592 AZX_DCAPS_ALIGN_BUFSIZE)
593
594 #define AZX_DCAPS_PRESET_CTHDA \
595 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
596
597 /*
598 * VGA-switcher support
599 */
600 #ifdef SUPPORT_VGA_SWITCHEROO
601 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
602 #else
603 #define use_vga_switcheroo(chip) 0
604 #endif
605
606 static char *driver_short_names[] = {
607 [AZX_DRIVER_ICH] = "HDA Intel",
608 [AZX_DRIVER_PCH] = "HDA Intel PCH",
609 [AZX_DRIVER_SCH] = "HDA Intel MID",
610 [AZX_DRIVER_ATI] = "HDA ATI SB",
611 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
612 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
613 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
614 [AZX_DRIVER_SIS] = "HDA SIS966",
615 [AZX_DRIVER_ULI] = "HDA ULI M5461",
616 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
617 [AZX_DRIVER_TERA] = "HDA Teradici",
618 [AZX_DRIVER_CTX] = "HDA Creative",
619 [AZX_DRIVER_CTHDA] = "HDA Creative",
620 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
621 };
622
623 /*
624 * macros for easy use
625 */
626 #define azx_writel(chip,reg,value) \
627 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
628 #define azx_readl(chip,reg) \
629 readl((chip)->remap_addr + ICH6_REG_##reg)
630 #define azx_writew(chip,reg,value) \
631 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
632 #define azx_readw(chip,reg) \
633 readw((chip)->remap_addr + ICH6_REG_##reg)
634 #define azx_writeb(chip,reg,value) \
635 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
636 #define azx_readb(chip,reg) \
637 readb((chip)->remap_addr + ICH6_REG_##reg)
638
639 #define azx_sd_writel(dev,reg,value) \
640 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
641 #define azx_sd_readl(dev,reg) \
642 readl((dev)->sd_addr + ICH6_REG_##reg)
643 #define azx_sd_writew(dev,reg,value) \
644 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
645 #define azx_sd_readw(dev,reg) \
646 readw((dev)->sd_addr + ICH6_REG_##reg)
647 #define azx_sd_writeb(dev,reg,value) \
648 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
649 #define azx_sd_readb(dev,reg) \
650 readb((dev)->sd_addr + ICH6_REG_##reg)
651
652 /* for pcm support */
653 #define get_azx_dev(substream) (substream->runtime->private_data)
654
655 #ifdef CONFIG_X86
656 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
657 {
658 if (azx_snoop(chip))
659 return;
660 if (addr && size) {
661 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
662 if (on)
663 set_memory_wc((unsigned long)addr, pages);
664 else
665 set_memory_wb((unsigned long)addr, pages);
666 }
667 }
668
669 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
670 bool on)
671 {
672 __mark_pages_wc(chip, buf->area, buf->bytes, on);
673 }
674 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
675 struct snd_pcm_runtime *runtime, bool on)
676 {
677 if (azx_dev->wc_marked != on) {
678 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
679 azx_dev->wc_marked = on;
680 }
681 }
682 #else
683 /* NOP for other archs */
684 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
685 bool on)
686 {
687 }
688 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
689 struct snd_pcm_runtime *runtime, bool on)
690 {
691 }
692 #endif
693
694 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
695 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
696 /*
697 * Interface for HD codec
698 */
699
700 /*
701 * CORB / RIRB interface
702 */
703 static int azx_alloc_cmd_io(struct azx *chip)
704 {
705 int err;
706
707 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
708 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
709 snd_dma_pci_data(chip->pci),
710 PAGE_SIZE, &chip->rb);
711 if (err < 0) {
712 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
713 return err;
714 }
715 mark_pages_wc(chip, &chip->rb, true);
716 return 0;
717 }
718
719 static void azx_init_cmd_io(struct azx *chip)
720 {
721 spin_lock_irq(&chip->reg_lock);
722 /* CORB set up */
723 chip->corb.addr = chip->rb.addr;
724 chip->corb.buf = (u32 *)chip->rb.area;
725 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
726 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
727
728 /* set the corb size to 256 entries (ULI requires explicitly) */
729 azx_writeb(chip, CORBSIZE, 0x02);
730 /* set the corb write pointer to 0 */
731 azx_writew(chip, CORBWP, 0);
732 /* reset the corb hw read pointer */
733 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
734 /* enable corb dma */
735 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
736
737 /* RIRB set up */
738 chip->rirb.addr = chip->rb.addr + 2048;
739 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
740 chip->rirb.wp = chip->rirb.rp = 0;
741 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
742 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
743 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
744
745 /* set the rirb size to 256 entries (ULI requires explicitly) */
746 azx_writeb(chip, RIRBSIZE, 0x02);
747 /* reset the rirb hw write pointer */
748 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
749 /* set N=1, get RIRB response interrupt for new entry */
750 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
751 azx_writew(chip, RINTCNT, 0xc0);
752 else
753 azx_writew(chip, RINTCNT, 1);
754 /* enable rirb dma and response irq */
755 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
756 spin_unlock_irq(&chip->reg_lock);
757 }
758
759 static void azx_free_cmd_io(struct azx *chip)
760 {
761 spin_lock_irq(&chip->reg_lock);
762 /* disable ringbuffer DMAs */
763 azx_writeb(chip, RIRBCTL, 0);
764 azx_writeb(chip, CORBCTL, 0);
765 spin_unlock_irq(&chip->reg_lock);
766 }
767
768 static unsigned int azx_command_addr(u32 cmd)
769 {
770 unsigned int addr = cmd >> 28;
771
772 if (addr >= AZX_MAX_CODECS) {
773 snd_BUG();
774 addr = 0;
775 }
776
777 return addr;
778 }
779
780 static unsigned int azx_response_addr(u32 res)
781 {
782 unsigned int addr = res & 0xf;
783
784 if (addr >= AZX_MAX_CODECS) {
785 snd_BUG();
786 addr = 0;
787 }
788
789 return addr;
790 }
791
792 /* send a command */
793 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
794 {
795 struct azx *chip = bus->private_data;
796 unsigned int addr = azx_command_addr(val);
797 unsigned int wp;
798
799 spin_lock_irq(&chip->reg_lock);
800
801 /* add command to corb */
802 wp = azx_readb(chip, CORBWP);
803 wp++;
804 wp %= ICH6_MAX_CORB_ENTRIES;
805
806 chip->rirb.cmds[addr]++;
807 chip->corb.buf[wp] = cpu_to_le32(val);
808 azx_writel(chip, CORBWP, wp);
809
810 spin_unlock_irq(&chip->reg_lock);
811
812 return 0;
813 }
814
815 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
816
817 /* retrieve RIRB entry - called from interrupt handler */
818 static void azx_update_rirb(struct azx *chip)
819 {
820 unsigned int rp, wp;
821 unsigned int addr;
822 u32 res, res_ex;
823
824 wp = azx_readb(chip, RIRBWP);
825 if (wp == chip->rirb.wp)
826 return;
827 chip->rirb.wp = wp;
828
829 while (chip->rirb.rp != wp) {
830 chip->rirb.rp++;
831 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
832
833 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
834 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
835 res = le32_to_cpu(chip->rirb.buf[rp]);
836 addr = azx_response_addr(res_ex);
837 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
838 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
839 else if (chip->rirb.cmds[addr]) {
840 chip->rirb.res[addr] = res;
841 smp_wmb();
842 chip->rirb.cmds[addr]--;
843 } else
844 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
845 "last cmd=%#08x\n",
846 pci_name(chip->pci),
847 res, res_ex,
848 chip->last_cmd[addr]);
849 }
850 }
851
852 /* receive a response */
853 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
854 unsigned int addr)
855 {
856 struct azx *chip = bus->private_data;
857 unsigned long timeout;
858 unsigned long loopcounter;
859 int do_poll = 0;
860
861 again:
862 timeout = jiffies + msecs_to_jiffies(1000);
863
864 for (loopcounter = 0;; loopcounter++) {
865 if (chip->polling_mode || do_poll) {
866 spin_lock_irq(&chip->reg_lock);
867 azx_update_rirb(chip);
868 spin_unlock_irq(&chip->reg_lock);
869 }
870 if (!chip->rirb.cmds[addr]) {
871 smp_rmb();
872 bus->rirb_error = 0;
873
874 if (!do_poll)
875 chip->poll_count = 0;
876 return chip->rirb.res[addr]; /* the last value */
877 }
878 if (time_after(jiffies, timeout))
879 break;
880 if (bus->needs_damn_long_delay || loopcounter > 3000)
881 msleep(2); /* temporary workaround */
882 else {
883 udelay(10);
884 cond_resched();
885 }
886 }
887
888 if (!chip->polling_mode && chip->poll_count < 2) {
889 snd_printdd(SFX "%s: azx_get_response timeout, "
890 "polling the codec once: last cmd=0x%08x\n",
891 pci_name(chip->pci), chip->last_cmd[addr]);
892 do_poll = 1;
893 chip->poll_count++;
894 goto again;
895 }
896
897
898 if (!chip->polling_mode) {
899 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
900 "switching to polling mode: last cmd=0x%08x\n",
901 pci_name(chip->pci), chip->last_cmd[addr]);
902 chip->polling_mode = 1;
903 goto again;
904 }
905
906 if (chip->msi) {
907 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
908 "disabling MSI: last cmd=0x%08x\n",
909 pci_name(chip->pci), chip->last_cmd[addr]);
910 free_irq(chip->irq, chip);
911 chip->irq = -1;
912 pci_disable_msi(chip->pci);
913 chip->msi = 0;
914 if (azx_acquire_irq(chip, 1) < 0) {
915 bus->rirb_error = 1;
916 return -1;
917 }
918 goto again;
919 }
920
921 if (chip->probing) {
922 /* If this critical timeout happens during the codec probing
923 * phase, this is likely an access to a non-existing codec
924 * slot. Better to return an error and reset the system.
925 */
926 return -1;
927 }
928
929 /* a fatal communication error; need either to reset or to fallback
930 * to the single_cmd mode
931 */
932 bus->rirb_error = 1;
933 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
934 bus->response_reset = 1;
935 return -1; /* give a chance to retry */
936 }
937
938 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
939 "switching to single_cmd mode: last cmd=0x%08x\n",
940 chip->last_cmd[addr]);
941 chip->single_cmd = 1;
942 bus->response_reset = 0;
943 /* release CORB/RIRB */
944 azx_free_cmd_io(chip);
945 /* disable unsolicited responses */
946 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
947 return -1;
948 }
949
950 /*
951 * Use the single immediate command instead of CORB/RIRB for simplicity
952 *
953 * Note: according to Intel, this is not preferred use. The command was
954 * intended for the BIOS only, and may get confused with unsolicited
955 * responses. So, we shouldn't use it for normal operation from the
956 * driver.
957 * I left the codes, however, for debugging/testing purposes.
958 */
959
960 /* receive a response */
961 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
962 {
963 int timeout = 50;
964
965 while (timeout--) {
966 /* check IRV busy bit */
967 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
968 /* reuse rirb.res as the response return value */
969 chip->rirb.res[addr] = azx_readl(chip, IR);
970 return 0;
971 }
972 udelay(1);
973 }
974 if (printk_ratelimit())
975 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
976 pci_name(chip->pci), azx_readw(chip, IRS));
977 chip->rirb.res[addr] = -1;
978 return -EIO;
979 }
980
981 /* send a command */
982 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
983 {
984 struct azx *chip = bus->private_data;
985 unsigned int addr = azx_command_addr(val);
986 int timeout = 50;
987
988 bus->rirb_error = 0;
989 while (timeout--) {
990 /* check ICB busy bit */
991 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
992 /* Clear IRV valid bit */
993 azx_writew(chip, IRS, azx_readw(chip, IRS) |
994 ICH6_IRS_VALID);
995 azx_writel(chip, IC, val);
996 azx_writew(chip, IRS, azx_readw(chip, IRS) |
997 ICH6_IRS_BUSY);
998 return azx_single_wait_for_response(chip, addr);
999 }
1000 udelay(1);
1001 }
1002 if (printk_ratelimit())
1003 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1004 pci_name(chip->pci), azx_readw(chip, IRS), val);
1005 return -EIO;
1006 }
1007
1008 /* receive a response */
1009 static unsigned int azx_single_get_response(struct hda_bus *bus,
1010 unsigned int addr)
1011 {
1012 struct azx *chip = bus->private_data;
1013 return chip->rirb.res[addr];
1014 }
1015
1016 /*
1017 * The below are the main callbacks from hda_codec.
1018 *
1019 * They are just the skeleton to call sub-callbacks according to the
1020 * current setting of chip->single_cmd.
1021 */
1022
1023 /* send a command */
1024 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1025 {
1026 struct azx *chip = bus->private_data;
1027
1028 if (chip->disabled)
1029 return 0;
1030 chip->last_cmd[azx_command_addr(val)] = val;
1031 if (chip->single_cmd)
1032 return azx_single_send_cmd(bus, val);
1033 else
1034 return azx_corb_send_cmd(bus, val);
1035 }
1036
1037 /* get a response */
1038 static unsigned int azx_get_response(struct hda_bus *bus,
1039 unsigned int addr)
1040 {
1041 struct azx *chip = bus->private_data;
1042 if (chip->disabled)
1043 return 0;
1044 if (chip->single_cmd)
1045 return azx_single_get_response(bus, addr);
1046 else
1047 return azx_rirb_get_response(bus, addr);
1048 }
1049
1050 #ifdef CONFIG_PM
1051 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1052 #endif
1053
1054 /* reset codec link */
1055 static int azx_reset(struct azx *chip, int full_reset)
1056 {
1057 int count;
1058
1059 if (!full_reset)
1060 goto __skip;
1061
1062 /* clear STATESTS */
1063 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1064
1065 /* reset controller */
1066 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1067
1068 count = 50;
1069 while (azx_readb(chip, GCTL) && --count)
1070 msleep(1);
1071
1072 /* delay for >= 100us for codec PLL to settle per spec
1073 * Rev 0.9 section 5.5.1
1074 */
1075 msleep(1);
1076
1077 /* Bring controller out of reset */
1078 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1079
1080 count = 50;
1081 while (!azx_readb(chip, GCTL) && --count)
1082 msleep(1);
1083
1084 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1085 msleep(1);
1086
1087 __skip:
1088 /* check to see if controller is ready */
1089 if (!azx_readb(chip, GCTL)) {
1090 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1091 return -EBUSY;
1092 }
1093
1094 /* Accept unsolicited responses */
1095 if (!chip->single_cmd)
1096 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1097 ICH6_GCTL_UNSOL);
1098
1099 /* detect codecs */
1100 if (!chip->codec_mask) {
1101 chip->codec_mask = azx_readw(chip, STATESTS);
1102 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1103 }
1104
1105 return 0;
1106 }
1107
1108
1109 /*
1110 * Lowlevel interface
1111 */
1112
1113 /* enable interrupts */
1114 static void azx_int_enable(struct azx *chip)
1115 {
1116 /* enable controller CIE and GIE */
1117 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1118 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1119 }
1120
1121 /* disable interrupts */
1122 static void azx_int_disable(struct azx *chip)
1123 {
1124 int i;
1125
1126 /* disable interrupts in stream descriptor */
1127 for (i = 0; i < chip->num_streams; i++) {
1128 struct azx_dev *azx_dev = &chip->azx_dev[i];
1129 azx_sd_writeb(azx_dev, SD_CTL,
1130 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1131 }
1132
1133 /* disable SIE for all streams */
1134 azx_writeb(chip, INTCTL, 0);
1135
1136 /* disable controller CIE and GIE */
1137 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1138 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1139 }
1140
1141 /* clear interrupts */
1142 static void azx_int_clear(struct azx *chip)
1143 {
1144 int i;
1145
1146 /* clear stream status */
1147 for (i = 0; i < chip->num_streams; i++) {
1148 struct azx_dev *azx_dev = &chip->azx_dev[i];
1149 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1150 }
1151
1152 /* clear STATESTS */
1153 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1154
1155 /* clear rirb status */
1156 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1157
1158 /* clear int status */
1159 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1160 }
1161
1162 /* start a stream */
1163 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1164 {
1165 /*
1166 * Before stream start, initialize parameter
1167 */
1168 azx_dev->insufficient = 1;
1169
1170 /* enable SIE */
1171 azx_writel(chip, INTCTL,
1172 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1173 /* set DMA start and interrupt mask */
1174 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1175 SD_CTL_DMA_START | SD_INT_MASK);
1176 }
1177
1178 /* stop DMA */
1179 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1180 {
1181 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1182 ~(SD_CTL_DMA_START | SD_INT_MASK));
1183 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1184 }
1185
1186 /* stop a stream */
1187 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1188 {
1189 azx_stream_clear(chip, azx_dev);
1190 /* disable SIE */
1191 azx_writel(chip, INTCTL,
1192 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1193 }
1194
1195
1196 /*
1197 * reset and start the controller registers
1198 */
1199 static void azx_init_chip(struct azx *chip, int full_reset)
1200 {
1201 if (chip->initialized)
1202 return;
1203
1204 /* reset controller */
1205 azx_reset(chip, full_reset);
1206
1207 /* initialize interrupts */
1208 azx_int_clear(chip);
1209 azx_int_enable(chip);
1210
1211 /* initialize the codec command I/O */
1212 if (!chip->single_cmd)
1213 azx_init_cmd_io(chip);
1214
1215 /* program the position buffer */
1216 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1217 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1218
1219 chip->initialized = 1;
1220 }
1221
1222 /*
1223 * initialize the PCI registers
1224 */
1225 /* update bits in a PCI register byte */
1226 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1227 unsigned char mask, unsigned char val)
1228 {
1229 unsigned char data;
1230
1231 pci_read_config_byte(pci, reg, &data);
1232 data &= ~mask;
1233 data |= (val & mask);
1234 pci_write_config_byte(pci, reg, data);
1235 }
1236
1237 static void azx_init_pci(struct azx *chip)
1238 {
1239 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1240 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1241 * Ensuring these bits are 0 clears playback static on some HD Audio
1242 * codecs.
1243 * The PCI register TCSEL is defined in the Intel manuals.
1244 */
1245 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1246 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1247 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1248 }
1249
1250 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1251 * we need to enable snoop.
1252 */
1253 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1254 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1255 update_pci_byte(chip->pci,
1256 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1257 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1258 }
1259
1260 /* For NVIDIA HDA, enable snoop */
1261 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1262 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1263 update_pci_byte(chip->pci,
1264 NVIDIA_HDA_TRANSREG_ADDR,
1265 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1266 update_pci_byte(chip->pci,
1267 NVIDIA_HDA_ISTRM_COH,
1268 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1269 update_pci_byte(chip->pci,
1270 NVIDIA_HDA_OSTRM_COH,
1271 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1272 }
1273
1274 /* Enable SCH/PCH snoop if needed */
1275 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1276 unsigned short snoop;
1277 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1278 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1279 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1280 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1281 if (!azx_snoop(chip))
1282 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1283 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1284 pci_read_config_word(chip->pci,
1285 INTEL_SCH_HDA_DEVC, &snoop);
1286 }
1287 snd_printdd(SFX "%s: SCH snoop: %s\n",
1288 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1289 ? "Disabled" : "Enabled");
1290 }
1291 }
1292
1293
1294 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1295
1296 /*
1297 * interrupt handler
1298 */
1299 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1300 {
1301 struct azx *chip = dev_id;
1302 struct azx_dev *azx_dev;
1303 u32 status;
1304 u8 sd_status;
1305 int i, ok;
1306
1307 #ifdef CONFIG_PM_RUNTIME
1308 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1309 return IRQ_NONE;
1310 #endif
1311
1312 spin_lock(&chip->reg_lock);
1313
1314 if (chip->disabled) {
1315 spin_unlock(&chip->reg_lock);
1316 return IRQ_NONE;
1317 }
1318
1319 status = azx_readl(chip, INTSTS);
1320 if (status == 0) {
1321 spin_unlock(&chip->reg_lock);
1322 return IRQ_NONE;
1323 }
1324
1325 for (i = 0; i < chip->num_streams; i++) {
1326 azx_dev = &chip->azx_dev[i];
1327 if (status & azx_dev->sd_int_sta_mask) {
1328 sd_status = azx_sd_readb(azx_dev, SD_STS);
1329 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1330 if (!azx_dev->substream || !azx_dev->running ||
1331 !(sd_status & SD_INT_COMPLETE))
1332 continue;
1333 /* check whether this IRQ is really acceptable */
1334 ok = azx_position_ok(chip, azx_dev);
1335 if (ok == 1) {
1336 azx_dev->irq_pending = 0;
1337 spin_unlock(&chip->reg_lock);
1338 snd_pcm_period_elapsed(azx_dev->substream);
1339 spin_lock(&chip->reg_lock);
1340 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1341 /* bogus IRQ, process it later */
1342 azx_dev->irq_pending = 1;
1343 queue_work(chip->bus->workq,
1344 &chip->irq_pending_work);
1345 }
1346 }
1347 }
1348
1349 /* clear rirb int */
1350 status = azx_readb(chip, RIRBSTS);
1351 if (status & RIRB_INT_MASK) {
1352 if (status & RIRB_INT_RESPONSE) {
1353 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1354 udelay(80);
1355 azx_update_rirb(chip);
1356 }
1357 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1358 }
1359
1360 #if 0
1361 /* clear state status int */
1362 if (azx_readb(chip, STATESTS) & 0x04)
1363 azx_writeb(chip, STATESTS, 0x04);
1364 #endif
1365 spin_unlock(&chip->reg_lock);
1366
1367 return IRQ_HANDLED;
1368 }
1369
1370
1371 /*
1372 * set up a BDL entry
1373 */
1374 static int setup_bdle(struct azx *chip,
1375 struct snd_pcm_substream *substream,
1376 struct azx_dev *azx_dev, u32 **bdlp,
1377 int ofs, int size, int with_ioc)
1378 {
1379 u32 *bdl = *bdlp;
1380
1381 while (size > 0) {
1382 dma_addr_t addr;
1383 int chunk;
1384
1385 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1386 return -EINVAL;
1387
1388 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1389 /* program the address field of the BDL entry */
1390 bdl[0] = cpu_to_le32((u32)addr);
1391 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1392 /* program the size field of the BDL entry */
1393 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1394 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1395 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1396 u32 remain = 0x1000 - (ofs & 0xfff);
1397 if (chunk > remain)
1398 chunk = remain;
1399 }
1400 bdl[2] = cpu_to_le32(chunk);
1401 /* program the IOC to enable interrupt
1402 * only when the whole fragment is processed
1403 */
1404 size -= chunk;
1405 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1406 bdl += 4;
1407 azx_dev->frags++;
1408 ofs += chunk;
1409 }
1410 *bdlp = bdl;
1411 return ofs;
1412 }
1413
1414 /*
1415 * set up BDL entries
1416 */
1417 static int azx_setup_periods(struct azx *chip,
1418 struct snd_pcm_substream *substream,
1419 struct azx_dev *azx_dev)
1420 {
1421 u32 *bdl;
1422 int i, ofs, periods, period_bytes;
1423 int pos_adj;
1424
1425 /* reset BDL address */
1426 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1427 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1428
1429 period_bytes = azx_dev->period_bytes;
1430 periods = azx_dev->bufsize / period_bytes;
1431
1432 /* program the initial BDL entries */
1433 bdl = (u32 *)azx_dev->bdl.area;
1434 ofs = 0;
1435 azx_dev->frags = 0;
1436 pos_adj = bdl_pos_adj[chip->dev_index];
1437 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1438 struct snd_pcm_runtime *runtime = substream->runtime;
1439 int pos_align = pos_adj;
1440 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1441 if (!pos_adj)
1442 pos_adj = pos_align;
1443 else
1444 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1445 pos_align;
1446 pos_adj = frames_to_bytes(runtime, pos_adj);
1447 if (pos_adj >= period_bytes) {
1448 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1449 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1450 pos_adj = 0;
1451 } else {
1452 ofs = setup_bdle(chip, substream, azx_dev,
1453 &bdl, ofs, pos_adj, true);
1454 if (ofs < 0)
1455 goto error;
1456 }
1457 } else
1458 pos_adj = 0;
1459 for (i = 0; i < periods; i++) {
1460 if (i == periods - 1 && pos_adj)
1461 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1462 period_bytes - pos_adj, 0);
1463 else
1464 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1465 period_bytes,
1466 !azx_dev->no_period_wakeup);
1467 if (ofs < 0)
1468 goto error;
1469 }
1470 return 0;
1471
1472 error:
1473 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1474 pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1475 return -EINVAL;
1476 }
1477
1478 /* reset stream */
1479 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1480 {
1481 unsigned char val;
1482 int timeout;
1483
1484 azx_stream_clear(chip, azx_dev);
1485
1486 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1487 SD_CTL_STREAM_RESET);
1488 udelay(3);
1489 timeout = 300;
1490 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1491 --timeout)
1492 ;
1493 val &= ~SD_CTL_STREAM_RESET;
1494 azx_sd_writeb(azx_dev, SD_CTL, val);
1495 udelay(3);
1496
1497 timeout = 300;
1498 /* waiting for hardware to report that the stream is out of reset */
1499 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1500 --timeout)
1501 ;
1502
1503 /* reset first position - may not be synced with hw at this time */
1504 *azx_dev->posbuf = 0;
1505 }
1506
1507 /*
1508 * set up the SD for streaming
1509 */
1510 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1511 {
1512 unsigned int val;
1513 /* make sure the run bit is zero for SD */
1514 azx_stream_clear(chip, azx_dev);
1515 /* program the stream_tag */
1516 val = azx_sd_readl(azx_dev, SD_CTL);
1517 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1518 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1519 if (!azx_snoop(chip))
1520 val |= SD_CTL_TRAFFIC_PRIO;
1521 azx_sd_writel(azx_dev, SD_CTL, val);
1522
1523 /* program the length of samples in cyclic buffer */
1524 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1525
1526 /* program the stream format */
1527 /* this value needs to be the same as the one programmed */
1528 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1529
1530 /* program the stream LVI (last valid index) of the BDL */
1531 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1532
1533 /* program the BDL address */
1534 /* lower BDL address */
1535 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1536 /* upper BDL address */
1537 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1538
1539 /* enable the position buffer */
1540 if (chip->position_fix[0] != POS_FIX_LPIB ||
1541 chip->position_fix[1] != POS_FIX_LPIB) {
1542 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1543 azx_writel(chip, DPLBASE,
1544 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1545 }
1546
1547 /* set the interrupt enable bits in the descriptor control register */
1548 azx_sd_writel(azx_dev, SD_CTL,
1549 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1550
1551 return 0;
1552 }
1553
1554 /*
1555 * Probe the given codec address
1556 */
1557 static int probe_codec(struct azx *chip, int addr)
1558 {
1559 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1560 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1561 unsigned int res;
1562
1563 mutex_lock(&chip->bus->cmd_mutex);
1564 chip->probing = 1;
1565 azx_send_cmd(chip->bus, cmd);
1566 res = azx_get_response(chip->bus, addr);
1567 chip->probing = 0;
1568 mutex_unlock(&chip->bus->cmd_mutex);
1569 if (res == -1)
1570 return -EIO;
1571 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1572 return 0;
1573 }
1574
1575 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1576 struct hda_pcm *cpcm);
1577 static void azx_stop_chip(struct azx *chip);
1578
1579 static void azx_bus_reset(struct hda_bus *bus)
1580 {
1581 struct azx *chip = bus->private_data;
1582
1583 bus->in_reset = 1;
1584 azx_stop_chip(chip);
1585 azx_init_chip(chip, 1);
1586 #ifdef CONFIG_PM
1587 if (chip->initialized) {
1588 struct azx_pcm *p;
1589 list_for_each_entry(p, &chip->pcm_list, list)
1590 snd_pcm_suspend_all(p->pcm);
1591 snd_hda_suspend(chip->bus);
1592 snd_hda_resume(chip->bus);
1593 }
1594 #endif
1595 bus->in_reset = 0;
1596 }
1597
1598 static int get_jackpoll_interval(struct azx *chip)
1599 {
1600 int i = jackpoll_ms[chip->dev_index];
1601 unsigned int j;
1602 if (i == 0)
1603 return 0;
1604 if (i < 50 || i > 60000)
1605 j = 0;
1606 else
1607 j = msecs_to_jiffies(i);
1608 if (j == 0)
1609 snd_printk(KERN_WARNING SFX
1610 "jackpoll_ms value out of range: %d\n", i);
1611 return j;
1612 }
1613
1614 /*
1615 * Codec initialization
1616 */
1617
1618 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1619 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1620 [AZX_DRIVER_NVIDIA] = 8,
1621 [AZX_DRIVER_TERA] = 1,
1622 };
1623
1624 static int azx_codec_create(struct azx *chip, const char *model)
1625 {
1626 struct hda_bus_template bus_temp;
1627 int c, codecs, err;
1628 int max_slots;
1629
1630 memset(&bus_temp, 0, sizeof(bus_temp));
1631 bus_temp.private_data = chip;
1632 bus_temp.modelname = model;
1633 bus_temp.pci = chip->pci;
1634 bus_temp.ops.command = azx_send_cmd;
1635 bus_temp.ops.get_response = azx_get_response;
1636 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1637 bus_temp.ops.bus_reset = azx_bus_reset;
1638 #ifdef CONFIG_PM
1639 bus_temp.power_save = &power_save;
1640 bus_temp.ops.pm_notify = azx_power_notify;
1641 #endif
1642
1643 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1644 if (err < 0)
1645 return err;
1646
1647 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1648 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1649 chip->bus->needs_damn_long_delay = 1;
1650 }
1651
1652 codecs = 0;
1653 max_slots = azx_max_codecs[chip->driver_type];
1654 if (!max_slots)
1655 max_slots = AZX_DEFAULT_CODECS;
1656
1657 /* First try to probe all given codec slots */
1658 for (c = 0; c < max_slots; c++) {
1659 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1660 if (probe_codec(chip, c) < 0) {
1661 /* Some BIOSen give you wrong codec addresses
1662 * that don't exist
1663 */
1664 snd_printk(KERN_WARNING SFX
1665 "%s: Codec #%d probe error; "
1666 "disabling it...\n", pci_name(chip->pci), c);
1667 chip->codec_mask &= ~(1 << c);
1668 /* More badly, accessing to a non-existing
1669 * codec often screws up the controller chip,
1670 * and disturbs the further communications.
1671 * Thus if an error occurs during probing,
1672 * better to reset the controller chip to
1673 * get back to the sanity state.
1674 */
1675 azx_stop_chip(chip);
1676 azx_init_chip(chip, 1);
1677 }
1678 }
1679 }
1680
1681 /* AMD chipsets often cause the communication stalls upon certain
1682 * sequence like the pin-detection. It seems that forcing the synced
1683 * access works around the stall. Grrr...
1684 */
1685 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1686 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1687 pci_name(chip->pci));
1688 chip->bus->sync_write = 1;
1689 chip->bus->allow_bus_reset = 1;
1690 }
1691
1692 /* Then create codec instances */
1693 for (c = 0; c < max_slots; c++) {
1694 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1695 struct hda_codec *codec;
1696 err = snd_hda_codec_new(chip->bus, c, &codec);
1697 if (err < 0)
1698 continue;
1699 codec->jackpoll_interval = get_jackpoll_interval(chip);
1700 codec->beep_mode = chip->beep_mode;
1701 codecs++;
1702 }
1703 }
1704 if (!codecs) {
1705 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1706 return -ENXIO;
1707 }
1708 return 0;
1709 }
1710
1711 /* configure each codec instance */
1712 static int azx_codec_configure(struct azx *chip)
1713 {
1714 struct hda_codec *codec;
1715 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1716 snd_hda_codec_configure(codec);
1717 }
1718 return 0;
1719 }
1720
1721
1722 /*
1723 * PCM support
1724 */
1725
1726 /* assign a stream for the PCM */
1727 static inline struct azx_dev *
1728 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1729 {
1730 int dev, i, nums;
1731 struct azx_dev *res = NULL;
1732 /* make a non-zero unique key for the substream */
1733 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1734 (substream->stream + 1);
1735
1736 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1737 dev = chip->playback_index_offset;
1738 nums = chip->playback_streams;
1739 } else {
1740 dev = chip->capture_index_offset;
1741 nums = chip->capture_streams;
1742 }
1743 for (i = 0; i < nums; i++, dev++)
1744 if (!chip->azx_dev[dev].opened) {
1745 res = &chip->azx_dev[dev];
1746 if (res->assigned_key == key)
1747 break;
1748 }
1749 if (res) {
1750 res->opened = 1;
1751 res->assigned_key = key;
1752 }
1753 return res;
1754 }
1755
1756 /* release the assigned stream */
1757 static inline void azx_release_device(struct azx_dev *azx_dev)
1758 {
1759 azx_dev->opened = 0;
1760 }
1761
1762 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1763 {
1764 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1765 struct snd_pcm_substream *substream = azx_dev->substream;
1766 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1767 struct azx *chip = apcm->chip;
1768
1769 return azx_readl(chip, WALLCLK);
1770 }
1771
1772 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1773 bool force, cycle_t last)
1774 {
1775 struct azx_dev *azx_dev = get_azx_dev(substream);
1776 struct timecounter *tc = &azx_dev->azx_tc;
1777 struct cyclecounter *cc = &azx_dev->azx_cc;
1778 u64 nsec;
1779
1780 cc->read = azx_cc_read;
1781 cc->mask = CLOCKSOURCE_MASK(32);
1782
1783 /*
1784 * Converting from 24 MHz to ns means applying a 125/3 factor.
1785 * To avoid any saturation issues in intermediate operations,
1786 * the 125 factor is applied first. The division is applied
1787 * last after reading the timecounter value.
1788 * Applying the 1/3 factor as part of the multiplication
1789 * requires at least 20 bits for a decent precision, however
1790 * overflows occur after about 4 hours or less, not a option.
1791 */
1792
1793 cc->mult = 125; /* saturation after 195 years */
1794 cc->shift = 0;
1795
1796 nsec = 0; /* audio time is elapsed time since trigger */
1797 timecounter_init(tc, cc, nsec);
1798 if (force)
1799 /*
1800 * force timecounter to use predefined value,
1801 * used for synchronized starts
1802 */
1803 tc->cycle_last = last;
1804 }
1805
1806 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1807 struct timespec *ts)
1808 {
1809 struct azx_dev *azx_dev = get_azx_dev(substream);
1810 u64 nsec;
1811
1812 nsec = timecounter_read(&azx_dev->azx_tc);
1813 nsec = div_u64(nsec, 3); /* can be optimized */
1814
1815 *ts = ns_to_timespec(nsec);
1816
1817 return 0;
1818 }
1819
1820 static struct snd_pcm_hardware azx_pcm_hw = {
1821 .info = (SNDRV_PCM_INFO_MMAP |
1822 SNDRV_PCM_INFO_INTERLEAVED |
1823 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1824 SNDRV_PCM_INFO_MMAP_VALID |
1825 /* No full-resume yet implemented */
1826 /* SNDRV_PCM_INFO_RESUME |*/
1827 SNDRV_PCM_INFO_PAUSE |
1828 SNDRV_PCM_INFO_SYNC_START |
1829 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1830 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1831 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1832 .rates = SNDRV_PCM_RATE_48000,
1833 .rate_min = 48000,
1834 .rate_max = 48000,
1835 .channels_min = 2,
1836 .channels_max = 2,
1837 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1838 .period_bytes_min = 128,
1839 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1840 .periods_min = 2,
1841 .periods_max = AZX_MAX_FRAG,
1842 .fifo_size = 0,
1843 };
1844
1845 static int azx_pcm_open(struct snd_pcm_substream *substream)
1846 {
1847 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1848 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1849 struct azx *chip = apcm->chip;
1850 struct azx_dev *azx_dev;
1851 struct snd_pcm_runtime *runtime = substream->runtime;
1852 unsigned long flags;
1853 int err;
1854 int buff_step;
1855
1856 mutex_lock(&chip->open_mutex);
1857 azx_dev = azx_assign_device(chip, substream);
1858 if (azx_dev == NULL) {
1859 mutex_unlock(&chip->open_mutex);
1860 return -EBUSY;
1861 }
1862 runtime->hw = azx_pcm_hw;
1863 runtime->hw.channels_min = hinfo->channels_min;
1864 runtime->hw.channels_max = hinfo->channels_max;
1865 runtime->hw.formats = hinfo->formats;
1866 runtime->hw.rates = hinfo->rates;
1867 snd_pcm_limit_hw_rates(runtime);
1868 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1869
1870 /* avoid wrap-around with wall-clock */
1871 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1872 20,
1873 178000000);
1874
1875 if (chip->align_buffer_size)
1876 /* constrain buffer sizes to be multiple of 128
1877 bytes. This is more efficient in terms of memory
1878 access but isn't required by the HDA spec and
1879 prevents users from specifying exact period/buffer
1880 sizes. For example for 44.1kHz, a period size set
1881 to 20ms will be rounded to 19.59ms. */
1882 buff_step = 128;
1883 else
1884 /* Don't enforce steps on buffer sizes, still need to
1885 be multiple of 4 bytes (HDA spec). Tested on Intel
1886 HDA controllers, may not work on all devices where
1887 option needs to be disabled */
1888 buff_step = 4;
1889
1890 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1891 buff_step);
1892 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1893 buff_step);
1894 snd_hda_power_up_d3wait(apcm->codec);
1895 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1896 if (err < 0) {
1897 azx_release_device(azx_dev);
1898 snd_hda_power_down(apcm->codec);
1899 mutex_unlock(&chip->open_mutex);
1900 return err;
1901 }
1902 snd_pcm_limit_hw_rates(runtime);
1903 /* sanity check */
1904 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1905 snd_BUG_ON(!runtime->hw.channels_max) ||
1906 snd_BUG_ON(!runtime->hw.formats) ||
1907 snd_BUG_ON(!runtime->hw.rates)) {
1908 azx_release_device(azx_dev);
1909 hinfo->ops.close(hinfo, apcm->codec, substream);
1910 snd_hda_power_down(apcm->codec);
1911 mutex_unlock(&chip->open_mutex);
1912 return -EINVAL;
1913 }
1914
1915 /* disable WALLCLOCK timestamps for capture streams
1916 until we figure out how to handle digital inputs */
1917 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1918 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1919
1920 spin_lock_irqsave(&chip->reg_lock, flags);
1921 azx_dev->substream = substream;
1922 azx_dev->running = 0;
1923 spin_unlock_irqrestore(&chip->reg_lock, flags);
1924
1925 runtime->private_data = azx_dev;
1926 snd_pcm_set_sync(substream);
1927 mutex_unlock(&chip->open_mutex);
1928 return 0;
1929 }
1930
1931 static int azx_pcm_close(struct snd_pcm_substream *substream)
1932 {
1933 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1934 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1935 struct azx *chip = apcm->chip;
1936 struct azx_dev *azx_dev = get_azx_dev(substream);
1937 unsigned long flags;
1938
1939 mutex_lock(&chip->open_mutex);
1940 spin_lock_irqsave(&chip->reg_lock, flags);
1941 azx_dev->substream = NULL;
1942 azx_dev->running = 0;
1943 spin_unlock_irqrestore(&chip->reg_lock, flags);
1944 azx_release_device(azx_dev);
1945 hinfo->ops.close(hinfo, apcm->codec, substream);
1946 snd_hda_power_down(apcm->codec);
1947 mutex_unlock(&chip->open_mutex);
1948 return 0;
1949 }
1950
1951 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1952 struct snd_pcm_hw_params *hw_params)
1953 {
1954 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1955 struct azx *chip = apcm->chip;
1956 struct snd_pcm_runtime *runtime = substream->runtime;
1957 struct azx_dev *azx_dev = get_azx_dev(substream);
1958 int ret;
1959
1960 mark_runtime_wc(chip, azx_dev, runtime, false);
1961 azx_dev->bufsize = 0;
1962 azx_dev->period_bytes = 0;
1963 azx_dev->format_val = 0;
1964 ret = snd_pcm_lib_malloc_pages(substream,
1965 params_buffer_bytes(hw_params));
1966 if (ret < 0)
1967 return ret;
1968 mark_runtime_wc(chip, azx_dev, runtime, true);
1969 return ret;
1970 }
1971
1972 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1973 {
1974 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1975 struct azx_dev *azx_dev = get_azx_dev(substream);
1976 struct azx *chip = apcm->chip;
1977 struct snd_pcm_runtime *runtime = substream->runtime;
1978 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1979
1980 /* reset BDL address */
1981 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1982 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1983 azx_sd_writel(azx_dev, SD_CTL, 0);
1984 azx_dev->bufsize = 0;
1985 azx_dev->period_bytes = 0;
1986 azx_dev->format_val = 0;
1987
1988 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1989
1990 mark_runtime_wc(chip, azx_dev, runtime, false);
1991 return snd_pcm_lib_free_pages(substream);
1992 }
1993
1994 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1995 {
1996 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1997 struct azx *chip = apcm->chip;
1998 struct azx_dev *azx_dev = get_azx_dev(substream);
1999 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2000 struct snd_pcm_runtime *runtime = substream->runtime;
2001 unsigned int bufsize, period_bytes, format_val, stream_tag;
2002 int err;
2003 struct hda_spdif_out *spdif =
2004 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2005 unsigned short ctls = spdif ? spdif->ctls : 0;
2006
2007 azx_stream_reset(chip, azx_dev);
2008 format_val = snd_hda_calc_stream_format(runtime->rate,
2009 runtime->channels,
2010 runtime->format,
2011 hinfo->maxbps,
2012 ctls);
2013 if (!format_val) {
2014 snd_printk(KERN_ERR SFX
2015 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2016 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2017 return -EINVAL;
2018 }
2019
2020 bufsize = snd_pcm_lib_buffer_bytes(substream);
2021 period_bytes = snd_pcm_lib_period_bytes(substream);
2022
2023 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2024 pci_name(chip->pci), bufsize, format_val);
2025
2026 if (bufsize != azx_dev->bufsize ||
2027 period_bytes != azx_dev->period_bytes ||
2028 format_val != azx_dev->format_val ||
2029 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2030 azx_dev->bufsize = bufsize;
2031 azx_dev->period_bytes = period_bytes;
2032 azx_dev->format_val = format_val;
2033 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2034 err = azx_setup_periods(chip, substream, azx_dev);
2035 if (err < 0)
2036 return err;
2037 }
2038
2039 /* wallclk has 24Mhz clock source */
2040 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2041 runtime->rate) * 1000);
2042 azx_setup_controller(chip, azx_dev);
2043 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2044 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2045 else
2046 azx_dev->fifo_size = 0;
2047
2048 stream_tag = azx_dev->stream_tag;
2049 /* CA-IBG chips need the playback stream starting from 1 */
2050 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2051 stream_tag > chip->capture_streams)
2052 stream_tag -= chip->capture_streams;
2053 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2054 azx_dev->format_val, substream);
2055 }
2056
2057 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2058 {
2059 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2060 struct azx *chip = apcm->chip;
2061 struct azx_dev *azx_dev;
2062 struct snd_pcm_substream *s;
2063 int rstart = 0, start, nsync = 0, sbits = 0;
2064 int nwait, timeout;
2065
2066 azx_dev = get_azx_dev(substream);
2067 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2068
2069 switch (cmd) {
2070 case SNDRV_PCM_TRIGGER_START:
2071 rstart = 1;
2072 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2073 case SNDRV_PCM_TRIGGER_RESUME:
2074 start = 1;
2075 break;
2076 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2077 case SNDRV_PCM_TRIGGER_SUSPEND:
2078 case SNDRV_PCM_TRIGGER_STOP:
2079 start = 0;
2080 break;
2081 default:
2082 return -EINVAL;
2083 }
2084
2085 snd_pcm_group_for_each_entry(s, substream) {
2086 if (s->pcm->card != substream->pcm->card)
2087 continue;
2088 azx_dev = get_azx_dev(s);
2089 sbits |= 1 << azx_dev->index;
2090 nsync++;
2091 snd_pcm_trigger_done(s, substream);
2092 }
2093
2094 spin_lock(&chip->reg_lock);
2095
2096 /* first, set SYNC bits of corresponding streams */
2097 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2098 azx_writel(chip, OLD_SSYNC,
2099 azx_readl(chip, OLD_SSYNC) | sbits);
2100 else
2101 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2102
2103 snd_pcm_group_for_each_entry(s, substream) {
2104 if (s->pcm->card != substream->pcm->card)
2105 continue;
2106 azx_dev = get_azx_dev(s);
2107 if (start) {
2108 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2109 if (!rstart)
2110 azx_dev->start_wallclk -=
2111 azx_dev->period_wallclk;
2112 azx_stream_start(chip, azx_dev);
2113 } else {
2114 azx_stream_stop(chip, azx_dev);
2115 }
2116 azx_dev->running = start;
2117 }
2118 spin_unlock(&chip->reg_lock);
2119 if (start) {
2120 /* wait until all FIFOs get ready */
2121 for (timeout = 5000; timeout; timeout--) {
2122 nwait = 0;
2123 snd_pcm_group_for_each_entry(s, substream) {
2124 if (s->pcm->card != substream->pcm->card)
2125 continue;
2126 azx_dev = get_azx_dev(s);
2127 if (!(azx_sd_readb(azx_dev, SD_STS) &
2128 SD_STS_FIFO_READY))
2129 nwait++;
2130 }
2131 if (!nwait)
2132 break;
2133 cpu_relax();
2134 }
2135 } else {
2136 /* wait until all RUN bits are cleared */
2137 for (timeout = 5000; timeout; timeout--) {
2138 nwait = 0;
2139 snd_pcm_group_for_each_entry(s, substream) {
2140 if (s->pcm->card != substream->pcm->card)
2141 continue;
2142 azx_dev = get_azx_dev(s);
2143 if (azx_sd_readb(azx_dev, SD_CTL) &
2144 SD_CTL_DMA_START)
2145 nwait++;
2146 }
2147 if (!nwait)
2148 break;
2149 cpu_relax();
2150 }
2151 }
2152 spin_lock(&chip->reg_lock);
2153 /* reset SYNC bits */
2154 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2155 azx_writel(chip, OLD_SSYNC,
2156 azx_readl(chip, OLD_SSYNC) & ~sbits);
2157 else
2158 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2159 if (start) {
2160 azx_timecounter_init(substream, 0, 0);
2161 if (nsync > 1) {
2162 cycle_t cycle_last;
2163
2164 /* same start cycle for master and group */
2165 azx_dev = get_azx_dev(substream);
2166 cycle_last = azx_dev->azx_tc.cycle_last;
2167
2168 snd_pcm_group_for_each_entry(s, substream) {
2169 if (s->pcm->card != substream->pcm->card)
2170 continue;
2171 azx_timecounter_init(s, 1, cycle_last);
2172 }
2173 }
2174 }
2175 spin_unlock(&chip->reg_lock);
2176 return 0;
2177 }
2178
2179 /* get the current DMA position with correction on VIA chips */
2180 static unsigned int azx_via_get_position(struct azx *chip,
2181 struct azx_dev *azx_dev)
2182 {
2183 unsigned int link_pos, mini_pos, bound_pos;
2184 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2185 unsigned int fifo_size;
2186
2187 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2188 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2189 /* Playback, no problem using link position */
2190 return link_pos;
2191 }
2192
2193 /* Capture */
2194 /* For new chipset,
2195 * use mod to get the DMA position just like old chipset
2196 */
2197 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2198 mod_dma_pos %= azx_dev->period_bytes;
2199
2200 /* azx_dev->fifo_size can't get FIFO size of in stream.
2201 * Get from base address + offset.
2202 */
2203 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2204
2205 if (azx_dev->insufficient) {
2206 /* Link position never gather than FIFO size */
2207 if (link_pos <= fifo_size)
2208 return 0;
2209
2210 azx_dev->insufficient = 0;
2211 }
2212
2213 if (link_pos <= fifo_size)
2214 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2215 else
2216 mini_pos = link_pos - fifo_size;
2217
2218 /* Find nearest previous boudary */
2219 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2220 mod_link_pos = link_pos % azx_dev->period_bytes;
2221 if (mod_link_pos >= fifo_size)
2222 bound_pos = link_pos - mod_link_pos;
2223 else if (mod_dma_pos >= mod_mini_pos)
2224 bound_pos = mini_pos - mod_mini_pos;
2225 else {
2226 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2227 if (bound_pos >= azx_dev->bufsize)
2228 bound_pos = 0;
2229 }
2230
2231 /* Calculate real DMA position we want */
2232 return bound_pos + mod_dma_pos;
2233 }
2234
2235 static unsigned int azx_get_position(struct azx *chip,
2236 struct azx_dev *azx_dev,
2237 bool with_check)
2238 {
2239 unsigned int pos;
2240 int stream = azx_dev->substream->stream;
2241 int delay = 0;
2242
2243 switch (chip->position_fix[stream]) {
2244 case POS_FIX_LPIB:
2245 /* read LPIB */
2246 pos = azx_sd_readl(azx_dev, SD_LPIB);
2247 break;
2248 case POS_FIX_VIACOMBO:
2249 pos = azx_via_get_position(chip, azx_dev);
2250 break;
2251 default:
2252 /* use the position buffer */
2253 pos = le32_to_cpu(*azx_dev->posbuf);
2254 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2255 if (!pos || pos == (u32)-1) {
2256 printk(KERN_WARNING
2257 "hda-intel: Invalid position buffer, "
2258 "using LPIB read method instead.\n");
2259 chip->position_fix[stream] = POS_FIX_LPIB;
2260 pos = azx_sd_readl(azx_dev, SD_LPIB);
2261 } else
2262 chip->position_fix[stream] = POS_FIX_POSBUF;
2263 }
2264 break;
2265 }
2266
2267 if (pos >= azx_dev->bufsize)
2268 pos = 0;
2269
2270 /* calculate runtime delay from LPIB */
2271 if (azx_dev->substream->runtime &&
2272 chip->position_fix[stream] == POS_FIX_POSBUF &&
2273 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2274 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2275 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2276 delay = pos - lpib_pos;
2277 else
2278 delay = lpib_pos - pos;
2279 if (delay < 0)
2280 delay += azx_dev->bufsize;
2281 if (delay >= azx_dev->period_bytes) {
2282 snd_printk(KERN_WARNING SFX
2283 "%s: Unstable LPIB (%d >= %d); "
2284 "disabling LPIB delay counting\n",
2285 pci_name(chip->pci), delay, azx_dev->period_bytes);
2286 delay = 0;
2287 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2288 }
2289 azx_dev->substream->runtime->delay =
2290 bytes_to_frames(azx_dev->substream->runtime, delay);
2291 }
2292 trace_azx_get_position(chip, azx_dev, pos, delay);
2293 return pos;
2294 }
2295
2296 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2297 {
2298 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2299 struct azx *chip = apcm->chip;
2300 struct azx_dev *azx_dev = get_azx_dev(substream);
2301 return bytes_to_frames(substream->runtime,
2302 azx_get_position(chip, azx_dev, false));
2303 }
2304
2305 /*
2306 * Check whether the current DMA position is acceptable for updating
2307 * periods. Returns non-zero if it's OK.
2308 *
2309 * Many HD-audio controllers appear pretty inaccurate about
2310 * the update-IRQ timing. The IRQ is issued before actually the
2311 * data is processed. So, we need to process it afterwords in a
2312 * workqueue.
2313 */
2314 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2315 {
2316 u32 wallclk;
2317 unsigned int pos;
2318
2319 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2320 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2321 return -1; /* bogus (too early) interrupt */
2322
2323 pos = azx_get_position(chip, azx_dev, true);
2324
2325 if (WARN_ONCE(!azx_dev->period_bytes,
2326 "hda-intel: zero azx_dev->period_bytes"))
2327 return -1; /* this shouldn't happen! */
2328 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2329 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2330 /* NG - it's below the first next period boundary */
2331 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2332 azx_dev->start_wallclk += wallclk;
2333 return 1; /* OK, it's fine */
2334 }
2335
2336 /*
2337 * The work for pending PCM period updates.
2338 */
2339 static void azx_irq_pending_work(struct work_struct *work)
2340 {
2341 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2342 int i, pending, ok;
2343
2344 if (!chip->irq_pending_warned) {
2345 printk(KERN_WARNING
2346 "hda-intel: IRQ timing workaround is activated "
2347 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2348 chip->card->number);
2349 chip->irq_pending_warned = 1;
2350 }
2351
2352 for (;;) {
2353 pending = 0;
2354 spin_lock_irq(&chip->reg_lock);
2355 for (i = 0; i < chip->num_streams; i++) {
2356 struct azx_dev *azx_dev = &chip->azx_dev[i];
2357 if (!azx_dev->irq_pending ||
2358 !azx_dev->substream ||
2359 !azx_dev->running)
2360 continue;
2361 ok = azx_position_ok(chip, azx_dev);
2362 if (ok > 0) {
2363 azx_dev->irq_pending = 0;
2364 spin_unlock(&chip->reg_lock);
2365 snd_pcm_period_elapsed(azx_dev->substream);
2366 spin_lock(&chip->reg_lock);
2367 } else if (ok < 0) {
2368 pending = 0; /* too early */
2369 } else
2370 pending++;
2371 }
2372 spin_unlock_irq(&chip->reg_lock);
2373 if (!pending)
2374 return;
2375 msleep(1);
2376 }
2377 }
2378
2379 /* clear irq_pending flags and assure no on-going workq */
2380 static void azx_clear_irq_pending(struct azx *chip)
2381 {
2382 int i;
2383
2384 spin_lock_irq(&chip->reg_lock);
2385 for (i = 0; i < chip->num_streams; i++)
2386 chip->azx_dev[i].irq_pending = 0;
2387 spin_unlock_irq(&chip->reg_lock);
2388 }
2389
2390 #ifdef CONFIG_X86
2391 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2392 struct vm_area_struct *area)
2393 {
2394 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2395 struct azx *chip = apcm->chip;
2396 if (!azx_snoop(chip))
2397 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2398 return snd_pcm_lib_default_mmap(substream, area);
2399 }
2400 #else
2401 #define azx_pcm_mmap NULL
2402 #endif
2403
2404 static struct snd_pcm_ops azx_pcm_ops = {
2405 .open = azx_pcm_open,
2406 .close = azx_pcm_close,
2407 .ioctl = snd_pcm_lib_ioctl,
2408 .hw_params = azx_pcm_hw_params,
2409 .hw_free = azx_pcm_hw_free,
2410 .prepare = azx_pcm_prepare,
2411 .trigger = azx_pcm_trigger,
2412 .pointer = azx_pcm_pointer,
2413 .wall_clock = azx_get_wallclock_tstamp,
2414 .mmap = azx_pcm_mmap,
2415 .page = snd_pcm_sgbuf_ops_page,
2416 };
2417
2418 static void azx_pcm_free(struct snd_pcm *pcm)
2419 {
2420 struct azx_pcm *apcm = pcm->private_data;
2421 if (apcm) {
2422 list_del(&apcm->list);
2423 kfree(apcm);
2424 }
2425 }
2426
2427 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2428
2429 static int
2430 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2431 struct hda_pcm *cpcm)
2432 {
2433 struct azx *chip = bus->private_data;
2434 struct snd_pcm *pcm;
2435 struct azx_pcm *apcm;
2436 int pcm_dev = cpcm->device;
2437 unsigned int size;
2438 int s, err;
2439
2440 list_for_each_entry(apcm, &chip->pcm_list, list) {
2441 if (apcm->pcm->device == pcm_dev) {
2442 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2443 pci_name(chip->pci), pcm_dev);
2444 return -EBUSY;
2445 }
2446 }
2447 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2448 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2449 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2450 &pcm);
2451 if (err < 0)
2452 return err;
2453 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2454 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2455 if (apcm == NULL)
2456 return -ENOMEM;
2457 apcm->chip = chip;
2458 apcm->pcm = pcm;
2459 apcm->codec = codec;
2460 pcm->private_data = apcm;
2461 pcm->private_free = azx_pcm_free;
2462 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2463 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2464 list_add_tail(&apcm->list, &chip->pcm_list);
2465 cpcm->pcm = pcm;
2466 for (s = 0; s < 2; s++) {
2467 apcm->hinfo[s] = &cpcm->stream[s];
2468 if (cpcm->stream[s].substreams)
2469 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2470 }
2471 /* buffer pre-allocation */
2472 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2473 if (size > MAX_PREALLOC_SIZE)
2474 size = MAX_PREALLOC_SIZE;
2475 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2476 snd_dma_pci_data(chip->pci),
2477 size, MAX_PREALLOC_SIZE);
2478 return 0;
2479 }
2480
2481 /*
2482 * mixer creation - all stuff is implemented in hda module
2483 */
2484 static int azx_mixer_create(struct azx *chip)
2485 {
2486 return snd_hda_build_controls(chip->bus);
2487 }
2488
2489
2490 /*
2491 * initialize SD streams
2492 */
2493 static int azx_init_stream(struct azx *chip)
2494 {
2495 int i;
2496
2497 /* initialize each stream (aka device)
2498 * assign the starting bdl address to each stream (device)
2499 * and initialize
2500 */
2501 for (i = 0; i < chip->num_streams; i++) {
2502 struct azx_dev *azx_dev = &chip->azx_dev[i];
2503 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2504 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2505 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2506 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2507 azx_dev->sd_int_sta_mask = 1 << i;
2508 /* stream tag: must be non-zero and unique */
2509 azx_dev->index = i;
2510 azx_dev->stream_tag = i + 1;
2511 }
2512
2513 return 0;
2514 }
2515
2516 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2517 {
2518 if (request_irq(chip->pci->irq, azx_interrupt,
2519 chip->msi ? 0 : IRQF_SHARED,
2520 KBUILD_MODNAME, chip)) {
2521 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2522 "disabling device\n", chip->pci->irq);
2523 if (do_disconnect)
2524 snd_card_disconnect(chip->card);
2525 return -1;
2526 }
2527 chip->irq = chip->pci->irq;
2528 pci_intx(chip->pci, !chip->msi);
2529 return 0;
2530 }
2531
2532
2533 static void azx_stop_chip(struct azx *chip)
2534 {
2535 if (!chip->initialized)
2536 return;
2537
2538 /* disable interrupts */
2539 azx_int_disable(chip);
2540 azx_int_clear(chip);
2541
2542 /* disable CORB/RIRB */
2543 azx_free_cmd_io(chip);
2544
2545 /* disable position buffer */
2546 azx_writel(chip, DPLBASE, 0);
2547 azx_writel(chip, DPUBASE, 0);
2548
2549 chip->initialized = 0;
2550 }
2551
2552 #ifdef CONFIG_PM
2553 /* power-up/down the controller */
2554 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2555 {
2556 struct azx *chip = bus->private_data;
2557
2558 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2559 return;
2560
2561 if (power_up)
2562 pm_runtime_get_sync(&chip->pci->dev);
2563 else
2564 pm_runtime_put_sync(&chip->pci->dev);
2565 }
2566
2567 static DEFINE_MUTEX(card_list_lock);
2568 static LIST_HEAD(card_list);
2569
2570 static void azx_add_card_list(struct azx *chip)
2571 {
2572 mutex_lock(&card_list_lock);
2573 list_add(&chip->list, &card_list);
2574 mutex_unlock(&card_list_lock);
2575 }
2576
2577 static void azx_del_card_list(struct azx *chip)
2578 {
2579 mutex_lock(&card_list_lock);
2580 list_del_init(&chip->list);
2581 mutex_unlock(&card_list_lock);
2582 }
2583
2584 /* trigger power-save check at writing parameter */
2585 static int param_set_xint(const char *val, const struct kernel_param *kp)
2586 {
2587 struct azx *chip;
2588 struct hda_codec *c;
2589 int prev = power_save;
2590 int ret = param_set_int(val, kp);
2591
2592 if (ret || prev == power_save)
2593 return ret;
2594
2595 mutex_lock(&card_list_lock);
2596 list_for_each_entry(chip, &card_list, list) {
2597 if (!chip->bus || chip->disabled)
2598 continue;
2599 list_for_each_entry(c, &chip->bus->codec_list, list)
2600 snd_hda_power_sync(c);
2601 }
2602 mutex_unlock(&card_list_lock);
2603 return 0;
2604 }
2605 #else
2606 #define azx_add_card_list(chip) /* NOP */
2607 #define azx_del_card_list(chip) /* NOP */
2608 #endif /* CONFIG_PM */
2609
2610 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2611 /*
2612 * power management
2613 */
2614 static int azx_suspend(struct device *dev)
2615 {
2616 struct pci_dev *pci = to_pci_dev(dev);
2617 struct snd_card *card = dev_get_drvdata(dev);
2618 struct azx *chip = card->private_data;
2619 struct azx_pcm *p;
2620
2621 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2622 azx_clear_irq_pending(chip);
2623 list_for_each_entry(p, &chip->pcm_list, list)
2624 snd_pcm_suspend_all(p->pcm);
2625 if (chip->initialized)
2626 snd_hda_suspend(chip->bus);
2627 azx_stop_chip(chip);
2628 if (chip->irq >= 0) {
2629 free_irq(chip->irq, chip);
2630 chip->irq = -1;
2631 }
2632 if (chip->msi)
2633 pci_disable_msi(chip->pci);
2634 pci_disable_device(pci);
2635 pci_save_state(pci);
2636 pci_set_power_state(pci, PCI_D3hot);
2637 return 0;
2638 }
2639
2640 static int azx_resume(struct device *dev)
2641 {
2642 struct pci_dev *pci = to_pci_dev(dev);
2643 struct snd_card *card = dev_get_drvdata(dev);
2644 struct azx *chip = card->private_data;
2645
2646 pci_set_power_state(pci, PCI_D0);
2647 pci_restore_state(pci);
2648 if (pci_enable_device(pci) < 0) {
2649 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2650 "disabling device\n");
2651 snd_card_disconnect(card);
2652 return -EIO;
2653 }
2654 pci_set_master(pci);
2655 if (chip->msi)
2656 if (pci_enable_msi(pci) < 0)
2657 chip->msi = 0;
2658 if (azx_acquire_irq(chip, 1) < 0)
2659 return -EIO;
2660 azx_init_pci(chip);
2661
2662 azx_init_chip(chip, 1);
2663
2664 snd_hda_resume(chip->bus);
2665 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2666 return 0;
2667 }
2668 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2669
2670 #ifdef CONFIG_PM_RUNTIME
2671 static int azx_runtime_suspend(struct device *dev)
2672 {
2673 struct snd_card *card = dev_get_drvdata(dev);
2674 struct azx *chip = card->private_data;
2675
2676 if (!power_save_controller ||
2677 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2678 return -EAGAIN;
2679
2680 azx_stop_chip(chip);
2681 azx_clear_irq_pending(chip);
2682 return 0;
2683 }
2684
2685 static int azx_runtime_resume(struct device *dev)
2686 {
2687 struct snd_card *card = dev_get_drvdata(dev);
2688 struct azx *chip = card->private_data;
2689
2690 azx_init_pci(chip);
2691 azx_init_chip(chip, 1);
2692 return 0;
2693 }
2694 #endif /* CONFIG_PM_RUNTIME */
2695
2696 #ifdef CONFIG_PM
2697 static const struct dev_pm_ops azx_pm = {
2698 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2699 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2700 };
2701
2702 #define AZX_PM_OPS &azx_pm
2703 #else
2704 #define AZX_PM_OPS NULL
2705 #endif /* CONFIG_PM */
2706
2707
2708 /*
2709 * reboot notifier for hang-up problem at power-down
2710 */
2711 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2712 {
2713 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2714 snd_hda_bus_reboot_notify(chip->bus);
2715 azx_stop_chip(chip);
2716 return NOTIFY_OK;
2717 }
2718
2719 static void azx_notifier_register(struct azx *chip)
2720 {
2721 chip->reboot_notifier.notifier_call = azx_halt;
2722 register_reboot_notifier(&chip->reboot_notifier);
2723 }
2724
2725 static void azx_notifier_unregister(struct azx *chip)
2726 {
2727 if (chip->reboot_notifier.notifier_call)
2728 unregister_reboot_notifier(&chip->reboot_notifier);
2729 }
2730
2731 static int azx_first_init(struct azx *chip);
2732 static int azx_probe_continue(struct azx *chip);
2733
2734 #ifdef SUPPORT_VGA_SWITCHEROO
2735 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
2736
2737 static void azx_vs_set_state(struct pci_dev *pci,
2738 enum vga_switcheroo_state state)
2739 {
2740 struct snd_card *card = pci_get_drvdata(pci);
2741 struct azx *chip = card->private_data;
2742 bool disabled;
2743
2744 wait_for_completion(&chip->probe_wait);
2745 if (chip->init_failed)
2746 return;
2747
2748 disabled = (state == VGA_SWITCHEROO_OFF);
2749 if (chip->disabled == disabled)
2750 return;
2751
2752 if (!chip->bus) {
2753 chip->disabled = disabled;
2754 if (!disabled) {
2755 snd_printk(KERN_INFO SFX
2756 "%s: Start delayed initialization\n",
2757 pci_name(chip->pci));
2758 if (azx_first_init(chip) < 0 ||
2759 azx_probe_continue(chip) < 0) {
2760 snd_printk(KERN_ERR SFX
2761 "%s: initialization error\n",
2762 pci_name(chip->pci));
2763 chip->init_failed = true;
2764 }
2765 }
2766 } else {
2767 snd_printk(KERN_INFO SFX
2768 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
2769 disabled ? "Disabling" : "Enabling");
2770 if (disabled) {
2771 azx_suspend(&pci->dev);
2772 chip->disabled = true;
2773 if (snd_hda_lock_devices(chip->bus))
2774 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
2775 pci_name(chip->pci));
2776 } else {
2777 snd_hda_unlock_devices(chip->bus);
2778 chip->disabled = false;
2779 azx_resume(&pci->dev);
2780 }
2781 }
2782 }
2783
2784 static bool azx_vs_can_switch(struct pci_dev *pci)
2785 {
2786 struct snd_card *card = pci_get_drvdata(pci);
2787 struct azx *chip = card->private_data;
2788
2789 wait_for_completion(&chip->probe_wait);
2790 if (chip->init_failed)
2791 return false;
2792 if (chip->disabled || !chip->bus)
2793 return true;
2794 if (snd_hda_lock_devices(chip->bus))
2795 return false;
2796 snd_hda_unlock_devices(chip->bus);
2797 return true;
2798 }
2799
2800 static void init_vga_switcheroo(struct azx *chip)
2801 {
2802 struct pci_dev *p = get_bound_vga(chip->pci);
2803 if (p) {
2804 snd_printk(KERN_INFO SFX
2805 "%s: Handle VGA-switcheroo audio client\n",
2806 pci_name(chip->pci));
2807 chip->use_vga_switcheroo = 1;
2808 pci_dev_put(p);
2809 }
2810 }
2811
2812 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2813 .set_gpu_state = azx_vs_set_state,
2814 .can_switch = azx_vs_can_switch,
2815 };
2816
2817 static int register_vga_switcheroo(struct azx *chip)
2818 {
2819 int err;
2820
2821 if (!chip->use_vga_switcheroo)
2822 return 0;
2823 /* FIXME: currently only handling DIS controller
2824 * is there any machine with two switchable HDMI audio controllers?
2825 */
2826 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2827 VGA_SWITCHEROO_DIS,
2828 chip->bus != NULL);
2829 if (err < 0)
2830 return err;
2831 chip->vga_switcheroo_registered = 1;
2832 return 0;
2833 }
2834 #else
2835 #define init_vga_switcheroo(chip) /* NOP */
2836 #define register_vga_switcheroo(chip) 0
2837 #define check_hdmi_disabled(pci) false
2838 #endif /* SUPPORT_VGA_SWITCHER */
2839
2840 /*
2841 * destructor
2842 */
2843 static int azx_free(struct azx *chip)
2844 {
2845 int i;
2846
2847 azx_del_card_list(chip);
2848
2849 azx_notifier_unregister(chip);
2850
2851 chip->init_failed = 1; /* to be sure */
2852 complete(&chip->probe_wait);
2853
2854 if (use_vga_switcheroo(chip)) {
2855 if (chip->disabled && chip->bus)
2856 snd_hda_unlock_devices(chip->bus);
2857 if (chip->vga_switcheroo_registered)
2858 vga_switcheroo_unregister_client(chip->pci);
2859 }
2860
2861 if (chip->initialized) {
2862 azx_clear_irq_pending(chip);
2863 for (i = 0; i < chip->num_streams; i++)
2864 azx_stream_stop(chip, &chip->azx_dev[i]);
2865 azx_stop_chip(chip);
2866 }
2867
2868 if (chip->irq >= 0)
2869 free_irq(chip->irq, (void*)chip);
2870 if (chip->msi)
2871 pci_disable_msi(chip->pci);
2872 if (chip->remap_addr)
2873 iounmap(chip->remap_addr);
2874
2875 if (chip->azx_dev) {
2876 for (i = 0; i < chip->num_streams; i++)
2877 if (chip->azx_dev[i].bdl.area) {
2878 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2879 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2880 }
2881 }
2882 if (chip->rb.area) {
2883 mark_pages_wc(chip, &chip->rb, false);
2884 snd_dma_free_pages(&chip->rb);
2885 }
2886 if (chip->posbuf.area) {
2887 mark_pages_wc(chip, &chip->posbuf, false);
2888 snd_dma_free_pages(&chip->posbuf);
2889 }
2890 if (chip->region_requested)
2891 pci_release_regions(chip->pci);
2892 pci_disable_device(chip->pci);
2893 kfree(chip->azx_dev);
2894 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2895 if (chip->fw)
2896 release_firmware(chip->fw);
2897 #endif
2898 kfree(chip);
2899
2900 return 0;
2901 }
2902
2903 static int azx_dev_free(struct snd_device *device)
2904 {
2905 return azx_free(device->device_data);
2906 }
2907
2908 #ifdef SUPPORT_VGA_SWITCHEROO
2909 /*
2910 * Check of disabled HDMI controller by vga-switcheroo
2911 */
2912 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
2913 {
2914 struct pci_dev *p;
2915
2916 /* check only discrete GPU */
2917 switch (pci->vendor) {
2918 case PCI_VENDOR_ID_ATI:
2919 case PCI_VENDOR_ID_AMD:
2920 case PCI_VENDOR_ID_NVIDIA:
2921 if (pci->devfn == 1) {
2922 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2923 pci->bus->number, 0);
2924 if (p) {
2925 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2926 return p;
2927 pci_dev_put(p);
2928 }
2929 }
2930 break;
2931 }
2932 return NULL;
2933 }
2934
2935 static bool check_hdmi_disabled(struct pci_dev *pci)
2936 {
2937 bool vga_inactive = false;
2938 struct pci_dev *p = get_bound_vga(pci);
2939
2940 if (p) {
2941 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2942 vga_inactive = true;
2943 pci_dev_put(p);
2944 }
2945 return vga_inactive;
2946 }
2947 #endif /* SUPPORT_VGA_SWITCHEROO */
2948
2949 /*
2950 * white/black-listing for position_fix
2951 */
2952 static struct snd_pci_quirk position_fix_list[] = {
2953 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2954 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2955 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2956 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2957 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2958 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2959 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2960 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2961 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2962 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2963 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2964 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2965 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2966 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2967 {}
2968 };
2969
2970 static int check_position_fix(struct azx *chip, int fix)
2971 {
2972 const struct snd_pci_quirk *q;
2973
2974 switch (fix) {
2975 case POS_FIX_AUTO:
2976 case POS_FIX_LPIB:
2977 case POS_FIX_POSBUF:
2978 case POS_FIX_VIACOMBO:
2979 case POS_FIX_COMBO:
2980 return fix;
2981 }
2982
2983 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2984 if (q) {
2985 printk(KERN_INFO
2986 "hda_intel: position_fix set to %d "
2987 "for device %04x:%04x\n",
2988 q->value, q->subvendor, q->subdevice);
2989 return q->value;
2990 }
2991
2992 /* Check VIA/ATI HD Audio Controller exist */
2993 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2994 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
2995 return POS_FIX_VIACOMBO;
2996 }
2997 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2998 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
2999 return POS_FIX_LPIB;
3000 }
3001 return POS_FIX_AUTO;
3002 }
3003
3004 /*
3005 * black-lists for probe_mask
3006 */
3007 static struct snd_pci_quirk probe_mask_list[] = {
3008 /* Thinkpad often breaks the controller communication when accessing
3009 * to the non-working (or non-existing) modem codec slot.
3010 */
3011 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3012 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3013 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3014 /* broken BIOS */
3015 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3016 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3017 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3018 /* forced codec slots */
3019 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3020 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3021 /* WinFast VP200 H (Teradici) user reported broken communication */
3022 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3023 {}
3024 };
3025
3026 #define AZX_FORCE_CODEC_MASK 0x100
3027
3028 static void check_probe_mask(struct azx *chip, int dev)
3029 {
3030 const struct snd_pci_quirk *q;
3031
3032 chip->codec_probe_mask = probe_mask[dev];
3033 if (chip->codec_probe_mask == -1) {
3034 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3035 if (q) {
3036 printk(KERN_INFO
3037 "hda_intel: probe_mask set to 0x%x "
3038 "for device %04x:%04x\n",
3039 q->value, q->subvendor, q->subdevice);
3040 chip->codec_probe_mask = q->value;
3041 }
3042 }
3043
3044 /* check forced option */
3045 if (chip->codec_probe_mask != -1 &&
3046 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3047 chip->codec_mask = chip->codec_probe_mask & 0xff;
3048 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3049 chip->codec_mask);
3050 }
3051 }
3052
3053 /*
3054 * white/black-list for enable_msi
3055 */
3056 static struct snd_pci_quirk msi_black_list[] = {
3057 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3058 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3059 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3060 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3061 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3062 {}
3063 };
3064
3065 static void check_msi(struct azx *chip)
3066 {
3067 const struct snd_pci_quirk *q;
3068
3069 if (enable_msi >= 0) {
3070 chip->msi = !!enable_msi;
3071 return;
3072 }
3073 chip->msi = 1; /* enable MSI as default */
3074 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3075 if (q) {
3076 printk(KERN_INFO
3077 "hda_intel: msi for device %04x:%04x set to %d\n",
3078 q->subvendor, q->subdevice, q->value);
3079 chip->msi = q->value;
3080 return;
3081 }
3082
3083 /* NVidia chipsets seem to cause troubles with MSI */
3084 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3085 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3086 chip->msi = 0;
3087 }
3088 }
3089
3090 /* check the snoop mode availability */
3091 static void azx_check_snoop_available(struct azx *chip)
3092 {
3093 bool snoop = chip->snoop;
3094
3095 switch (chip->driver_type) {
3096 case AZX_DRIVER_VIA:
3097 /* force to non-snoop mode for a new VIA controller
3098 * when BIOS is set
3099 */
3100 if (snoop) {
3101 u8 val;
3102 pci_read_config_byte(chip->pci, 0x42, &val);
3103 if (!(val & 0x80) && chip->pci->revision == 0x30)
3104 snoop = false;
3105 }
3106 break;
3107 case AZX_DRIVER_ATIHDMI_NS:
3108 /* new ATI HDMI requires non-snoop */
3109 snoop = false;
3110 break;
3111 }
3112
3113 if (snoop != chip->snoop) {
3114 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3115 pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3116 chip->snoop = snoop;
3117 }
3118 }
3119
3120 /*
3121 * constructor
3122 */
3123 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3124 int dev, unsigned int driver_caps,
3125 struct azx **rchip)
3126 {
3127 static struct snd_device_ops ops = {
3128 .dev_free = azx_dev_free,
3129 };
3130 struct azx *chip;
3131 int err;
3132
3133 *rchip = NULL;
3134
3135 err = pci_enable_device(pci);
3136 if (err < 0)
3137 return err;
3138
3139 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3140 if (!chip) {
3141 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3142 pci_disable_device(pci);
3143 return -ENOMEM;
3144 }
3145
3146 spin_lock_init(&chip->reg_lock);
3147 mutex_init(&chip->open_mutex);
3148 chip->card = card;
3149 chip->pci = pci;
3150 chip->irq = -1;
3151 chip->driver_caps = driver_caps;
3152 chip->driver_type = driver_caps & 0xff;
3153 check_msi(chip);
3154 chip->dev_index = dev;
3155 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3156 INIT_LIST_HEAD(&chip->pcm_list);
3157 INIT_LIST_HEAD(&chip->list);
3158 init_vga_switcheroo(chip);
3159 init_completion(&chip->probe_wait);
3160
3161 chip->position_fix[0] = chip->position_fix[1] =
3162 check_position_fix(chip, position_fix[dev]);
3163 /* combo mode uses LPIB for playback */
3164 if (chip->position_fix[0] == POS_FIX_COMBO) {
3165 chip->position_fix[0] = POS_FIX_LPIB;
3166 chip->position_fix[1] = POS_FIX_AUTO;
3167 }
3168
3169 check_probe_mask(chip, dev);
3170
3171 chip->single_cmd = single_cmd;
3172 chip->snoop = hda_snoop;
3173 azx_check_snoop_available(chip);
3174
3175 if (bdl_pos_adj[dev] < 0) {
3176 switch (chip->driver_type) {
3177 case AZX_DRIVER_ICH:
3178 case AZX_DRIVER_PCH:
3179 bdl_pos_adj[dev] = 1;
3180 break;
3181 default:
3182 bdl_pos_adj[dev] = 32;
3183 break;
3184 }
3185 }
3186
3187 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3188 if (err < 0) {
3189 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3190 pci_name(chip->pci));
3191 azx_free(chip);
3192 return err;
3193 }
3194
3195 *rchip = chip;
3196 return 0;
3197 }
3198
3199 static int azx_first_init(struct azx *chip)
3200 {
3201 int dev = chip->dev_index;
3202 struct pci_dev *pci = chip->pci;
3203 struct snd_card *card = chip->card;
3204 int i, err;
3205 unsigned short gcap;
3206
3207 #if BITS_PER_LONG != 64
3208 /* Fix up base address on ULI M5461 */
3209 if (chip->driver_type == AZX_DRIVER_ULI) {
3210 u16 tmp3;
3211 pci_read_config_word(pci, 0x40, &tmp3);
3212 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3213 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3214 }
3215 #endif
3216
3217 err = pci_request_regions(pci, "ICH HD audio");
3218 if (err < 0)
3219 return err;
3220 chip->region_requested = 1;
3221
3222 chip->addr = pci_resource_start(pci, 0);
3223 chip->remap_addr = pci_ioremap_bar(pci, 0);
3224 if (chip->remap_addr == NULL) {
3225 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3226 return -ENXIO;
3227 }
3228
3229 if (chip->msi)
3230 if (pci_enable_msi(pci) < 0)
3231 chip->msi = 0;
3232
3233 if (azx_acquire_irq(chip, 0) < 0)
3234 return -EBUSY;
3235
3236 pci_set_master(pci);
3237 synchronize_irq(chip->irq);
3238
3239 gcap = azx_readw(chip, GCAP);
3240 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3241
3242 /* disable SB600 64bit support for safety */
3243 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3244 struct pci_dev *p_smbus;
3245 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3246 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3247 NULL);
3248 if (p_smbus) {
3249 if (p_smbus->revision < 0x30)
3250 gcap &= ~ICH6_GCAP_64OK;
3251 pci_dev_put(p_smbus);
3252 }
3253 }
3254
3255 /* disable 64bit DMA address on some devices */
3256 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3257 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3258 gcap &= ~ICH6_GCAP_64OK;
3259 }
3260
3261 /* disable buffer size rounding to 128-byte multiples if supported */
3262 if (align_buffer_size >= 0)
3263 chip->align_buffer_size = !!align_buffer_size;
3264 else {
3265 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3266 chip->align_buffer_size = 0;
3267 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3268 chip->align_buffer_size = 1;
3269 else
3270 chip->align_buffer_size = 1;
3271 }
3272
3273 /* allow 64bit DMA address if supported by H/W */
3274 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3275 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3276 else {
3277 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3278 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3279 }
3280
3281 /* read number of streams from GCAP register instead of using
3282 * hardcoded value
3283 */
3284 chip->capture_streams = (gcap >> 8) & 0x0f;
3285 chip->playback_streams = (gcap >> 12) & 0x0f;
3286 if (!chip->playback_streams && !chip->capture_streams) {
3287 /* gcap didn't give any info, switching to old method */
3288
3289 switch (chip->driver_type) {
3290 case AZX_DRIVER_ULI:
3291 chip->playback_streams = ULI_NUM_PLAYBACK;
3292 chip->capture_streams = ULI_NUM_CAPTURE;
3293 break;
3294 case AZX_DRIVER_ATIHDMI:
3295 case AZX_DRIVER_ATIHDMI_NS:
3296 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3297 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3298 break;
3299 case AZX_DRIVER_GENERIC:
3300 default:
3301 chip->playback_streams = ICH6_NUM_PLAYBACK;
3302 chip->capture_streams = ICH6_NUM_CAPTURE;
3303 break;
3304 }
3305 }
3306 chip->capture_index_offset = 0;
3307 chip->playback_index_offset = chip->capture_streams;
3308 chip->num_streams = chip->playback_streams + chip->capture_streams;
3309 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3310 GFP_KERNEL);
3311 if (!chip->azx_dev) {
3312 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
3313 return -ENOMEM;
3314 }
3315
3316 for (i = 0; i < chip->num_streams; i++) {
3317 /* allocate memory for the BDL for each stream */
3318 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3319 snd_dma_pci_data(chip->pci),
3320 BDL_SIZE, &chip->azx_dev[i].bdl);
3321 if (err < 0) {
3322 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
3323 return -ENOMEM;
3324 }
3325 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3326 }
3327 /* allocate memory for the position buffer */
3328 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3329 snd_dma_pci_data(chip->pci),
3330 chip->num_streams * 8, &chip->posbuf);
3331 if (err < 0) {
3332 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
3333 return -ENOMEM;
3334 }
3335 mark_pages_wc(chip, &chip->posbuf, true);
3336 /* allocate CORB/RIRB */
3337 err = azx_alloc_cmd_io(chip);
3338 if (err < 0)
3339 return err;
3340
3341 /* initialize streams */
3342 azx_init_stream(chip);
3343
3344 /* initialize chip */
3345 azx_init_pci(chip);
3346 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3347
3348 /* codec detection */
3349 if (!chip->codec_mask) {
3350 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
3351 return -ENODEV;
3352 }
3353
3354 strcpy(card->driver, "HDA-Intel");
3355 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3356 sizeof(card->shortname));
3357 snprintf(card->longname, sizeof(card->longname),
3358 "%s at 0x%lx irq %i",
3359 card->shortname, chip->addr, chip->irq);
3360
3361 return 0;
3362 }
3363
3364 static void power_down_all_codecs(struct azx *chip)
3365 {
3366 #ifdef CONFIG_PM
3367 /* The codecs were powered up in snd_hda_codec_new().
3368 * Now all initialization done, so turn them down if possible
3369 */
3370 struct hda_codec *codec;
3371 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3372 snd_hda_power_down(codec);
3373 }
3374 #endif
3375 }
3376
3377 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3378 /* callback from request_firmware_nowait() */
3379 static void azx_firmware_cb(const struct firmware *fw, void *context)
3380 {
3381 struct snd_card *card = context;
3382 struct azx *chip = card->private_data;
3383 struct pci_dev *pci = chip->pci;
3384
3385 if (!fw) {
3386 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3387 pci_name(chip->pci));
3388 goto error;
3389 }
3390
3391 chip->fw = fw;
3392 if (!chip->disabled) {
3393 /* continue probing */
3394 if (azx_probe_continue(chip))
3395 goto error;
3396 }
3397 return; /* OK */
3398
3399 error:
3400 snd_card_free(card);
3401 pci_set_drvdata(pci, NULL);
3402 }
3403 #endif
3404
3405 static int azx_probe(struct pci_dev *pci,
3406 const struct pci_device_id *pci_id)
3407 {
3408 static int dev;
3409 struct snd_card *card;
3410 struct azx *chip;
3411 bool probe_now;
3412 int err;
3413
3414 if (dev >= SNDRV_CARDS)
3415 return -ENODEV;
3416 if (!enable[dev]) {
3417 dev++;
3418 return -ENOENT;
3419 }
3420
3421 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3422 if (err < 0) {
3423 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
3424 return err;
3425 }
3426
3427 snd_card_set_dev(card, &pci->dev);
3428
3429 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3430 if (err < 0)
3431 goto out_free;
3432 card->private_data = chip;
3433
3434 pci_set_drvdata(pci, card);
3435
3436 err = register_vga_switcheroo(chip);
3437 if (err < 0) {
3438 snd_printk(KERN_ERR SFX
3439 "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
3440 goto out_free;
3441 }
3442
3443 if (check_hdmi_disabled(pci)) {
3444 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
3445 pci_name(pci));
3446 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
3447 chip->disabled = true;
3448 }
3449
3450 probe_now = !chip->disabled;
3451 if (probe_now) {
3452 err = azx_first_init(chip);
3453 if (err < 0)
3454 goto out_free;
3455 }
3456
3457 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3458 if (patch[dev] && *patch[dev]) {
3459 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3460 pci_name(pci), patch[dev]);
3461 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3462 &pci->dev, GFP_KERNEL, card,
3463 azx_firmware_cb);
3464 if (err < 0)
3465 goto out_free;
3466 probe_now = false; /* continued in azx_firmware_cb() */
3467 }
3468 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3469
3470 if (probe_now) {
3471 err = azx_probe_continue(chip);
3472 if (err < 0)
3473 goto out_free;
3474 }
3475
3476 if (pci_dev_run_wake(pci))
3477 pm_runtime_put_noidle(&pci->dev);
3478
3479 dev++;
3480 complete(&chip->probe_wait);
3481 return 0;
3482
3483 out_free:
3484 snd_card_free(card);
3485 pci_set_drvdata(pci, NULL);
3486 return err;
3487 }
3488
3489 static int azx_probe_continue(struct azx *chip)
3490 {
3491 int dev = chip->dev_index;
3492 int err;
3493
3494 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3495 chip->beep_mode = beep_mode[dev];
3496 #endif
3497
3498 /* create codec instances */
3499 err = azx_codec_create(chip, model[dev]);
3500 if (err < 0)
3501 goto out_free;
3502 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3503 if (chip->fw) {
3504 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3505 chip->fw->data);
3506 if (err < 0)
3507 goto out_free;
3508 #ifndef CONFIG_PM
3509 release_firmware(chip->fw); /* no longer needed */
3510 chip->fw = NULL;
3511 #endif
3512 }
3513 #endif
3514 if ((probe_only[dev] & 1) == 0) {
3515 err = azx_codec_configure(chip);
3516 if (err < 0)
3517 goto out_free;
3518 }
3519
3520 /* create PCM streams */
3521 err = snd_hda_build_pcms(chip->bus);
3522 if (err < 0)
3523 goto out_free;
3524
3525 /* create mixer controls */
3526 err = azx_mixer_create(chip);
3527 if (err < 0)
3528 goto out_free;
3529
3530 err = snd_card_register(chip->card);
3531 if (err < 0)
3532 goto out_free;
3533
3534 chip->running = 1;
3535 power_down_all_codecs(chip);
3536 azx_notifier_register(chip);
3537 azx_add_card_list(chip);
3538
3539 return 0;
3540
3541 out_free:
3542 chip->init_failed = 1;
3543 return err;
3544 }
3545
3546 static void azx_remove(struct pci_dev *pci)
3547 {
3548 struct snd_card *card = pci_get_drvdata(pci);
3549
3550 if (pci_dev_run_wake(pci))
3551 pm_runtime_get_noresume(&pci->dev);
3552
3553 if (card)
3554 snd_card_free(card);
3555 pci_set_drvdata(pci, NULL);
3556 }
3557
3558 /* PCI IDs */
3559 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3560 /* CPT */
3561 { PCI_DEVICE(0x8086, 0x1c20),
3562 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3563 /* PBG */
3564 { PCI_DEVICE(0x8086, 0x1d20),
3565 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3566 /* Panther Point */
3567 { PCI_DEVICE(0x8086, 0x1e20),
3568 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3569 /* Lynx Point */
3570 { PCI_DEVICE(0x8086, 0x8c20),
3571 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3572 /* Lynx Point-LP */
3573 { PCI_DEVICE(0x8086, 0x9c20),
3574 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3575 /* Lynx Point-LP */
3576 { PCI_DEVICE(0x8086, 0x9c21),
3577 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3578 /* Haswell */
3579 { PCI_DEVICE(0x8086, 0x0c0c),
3580 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3581 { PCI_DEVICE(0x8086, 0x0d0c),
3582 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3583 /* 5 Series/3400 */
3584 { PCI_DEVICE(0x8086, 0x3b56),
3585 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3586 /* SCH */
3587 { PCI_DEVICE(0x8086, 0x811b),
3588 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3589 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3590 { PCI_DEVICE(0x8086, 0x080a),
3591 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3592 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3593 /* ICH */
3594 { PCI_DEVICE(0x8086, 0x2668),
3595 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3596 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3597 { PCI_DEVICE(0x8086, 0x27d8),
3598 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3599 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3600 { PCI_DEVICE(0x8086, 0x269a),
3601 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3602 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3603 { PCI_DEVICE(0x8086, 0x284b),
3604 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3605 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3606 { PCI_DEVICE(0x8086, 0x293e),
3607 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3608 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3609 { PCI_DEVICE(0x8086, 0x293f),
3610 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3611 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3612 { PCI_DEVICE(0x8086, 0x3a3e),
3613 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3614 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3615 { PCI_DEVICE(0x8086, 0x3a6e),
3616 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3617 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3618 /* Generic Intel */
3619 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3620 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3621 .class_mask = 0xffffff,
3622 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3623 /* ATI SB 450/600/700/800/900 */
3624 { PCI_DEVICE(0x1002, 0x437b),
3625 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3626 { PCI_DEVICE(0x1002, 0x4383),
3627 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3628 /* AMD Hudson */
3629 { PCI_DEVICE(0x1022, 0x780d),
3630 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3631 /* ATI HDMI */
3632 { PCI_DEVICE(0x1002, 0x793b),
3633 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3634 { PCI_DEVICE(0x1002, 0x7919),
3635 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3636 { PCI_DEVICE(0x1002, 0x960f),
3637 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3638 { PCI_DEVICE(0x1002, 0x970f),
3639 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3640 { PCI_DEVICE(0x1002, 0xaa00),
3641 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3642 { PCI_DEVICE(0x1002, 0xaa08),
3643 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3644 { PCI_DEVICE(0x1002, 0xaa10),
3645 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3646 { PCI_DEVICE(0x1002, 0xaa18),
3647 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3648 { PCI_DEVICE(0x1002, 0xaa20),
3649 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3650 { PCI_DEVICE(0x1002, 0xaa28),
3651 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3652 { PCI_DEVICE(0x1002, 0xaa30),
3653 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3654 { PCI_DEVICE(0x1002, 0xaa38),
3655 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3656 { PCI_DEVICE(0x1002, 0xaa40),
3657 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3658 { PCI_DEVICE(0x1002, 0xaa48),
3659 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3660 { PCI_DEVICE(0x1002, 0x9902),
3661 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3662 { PCI_DEVICE(0x1002, 0xaaa0),
3663 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3664 { PCI_DEVICE(0x1002, 0xaaa8),
3665 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3666 { PCI_DEVICE(0x1002, 0xaab0),
3667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3668 /* VIA VT8251/VT8237A */
3669 { PCI_DEVICE(0x1106, 0x3288),
3670 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3671 /* VIA GFX VT7122/VX900 */
3672 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3673 /* VIA GFX VT6122/VX11 */
3674 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3675 /* SIS966 */
3676 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3677 /* ULI M5461 */
3678 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3679 /* NVIDIA MCP */
3680 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3681 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3682 .class_mask = 0xffffff,
3683 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3684 /* Teradici */
3685 { PCI_DEVICE(0x6549, 0x1200),
3686 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3687 { PCI_DEVICE(0x6549, 0x2200),
3688 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3689 /* Creative X-Fi (CA0110-IBG) */
3690 /* CTHDA chips */
3691 { PCI_DEVICE(0x1102, 0x0010),
3692 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3693 { PCI_DEVICE(0x1102, 0x0012),
3694 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3695 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3696 /* the following entry conflicts with snd-ctxfi driver,
3697 * as ctxfi driver mutates from HD-audio to native mode with
3698 * a special command sequence.
3699 */
3700 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3701 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3702 .class_mask = 0xffffff,
3703 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3704 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3705 #else
3706 /* this entry seems still valid -- i.e. without emu20kx chip */
3707 { PCI_DEVICE(0x1102, 0x0009),
3708 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3709 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3710 #endif
3711 /* Vortex86MX */
3712 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3713 /* VMware HDAudio */
3714 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3715 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3716 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3717 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3718 .class_mask = 0xffffff,
3719 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3720 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3721 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3722 .class_mask = 0xffffff,
3723 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3724 { 0, }
3725 };
3726 MODULE_DEVICE_TABLE(pci, azx_ids);
3727
3728 /* pci_driver definition */
3729 static struct pci_driver azx_driver = {
3730 .name = KBUILD_MODNAME,
3731 .id_table = azx_ids,
3732 .probe = azx_probe,
3733 .remove = azx_remove,
3734 .driver = {
3735 .pm = AZX_PM_OPS,
3736 },
3737 };
3738
3739 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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