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ALSA: hda - Limit 40bit DMA for AMD HDMI controllers
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/io.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
52
53 #ifdef CONFIG_X86
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #endif
58 #include <sound/core.h>
59 #include <sound/initval.h>
60 #include <linux/vgaarb.h>
61 #include <linux/vga_switcheroo.h>
62 #include <linux/firmware.h>
63 #include "hda_codec.h"
64 #include "hda_controller.h"
65 #include "hda_priv.h"
66 #include "hda_i915.h"
67
68 /* position fix mode */
69 enum {
70 POS_FIX_AUTO,
71 POS_FIX_LPIB,
72 POS_FIX_POSBUF,
73 POS_FIX_VIACOMBO,
74 POS_FIX_COMBO,
75 };
76
77 /* Defines for ATI HD Audio support in SB450 south bridge */
78 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
79 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
80
81 /* Defines for Nvidia HDA support */
82 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
83 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
84 #define NVIDIA_HDA_ISTRM_COH 0x4d
85 #define NVIDIA_HDA_OSTRM_COH 0x4c
86 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
87
88 /* Defines for Intel SCH HDA snoop control */
89 #define INTEL_SCH_HDA_DEVC 0x78
90 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
91
92 /* Define IN stream 0 FIFO size offset in VIA controller */
93 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
94 /* Define VIA HD Audio Device ID*/
95 #define VIA_HDAC_DEVICE_ID 0x3288
96
97 /* max number of SDs */
98 /* ICH, ATI and VIA have 4 playback and 4 capture */
99 #define ICH6_NUM_CAPTURE 4
100 #define ICH6_NUM_PLAYBACK 4
101
102 /* ULI has 6 playback and 5 capture */
103 #define ULI_NUM_CAPTURE 5
104 #define ULI_NUM_PLAYBACK 6
105
106 /* ATI HDMI may have up to 8 playbacks and 0 capture */
107 #define ATIHDMI_NUM_CAPTURE 0
108 #define ATIHDMI_NUM_PLAYBACK 8
109
110 /* TERA has 4 playback and 3 capture */
111 #define TERA_NUM_CAPTURE 3
112 #define TERA_NUM_PLAYBACK 4
113
114
115 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
116 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
117 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
118 static char *model[SNDRV_CARDS];
119 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
120 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
121 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
122 static int probe_only[SNDRV_CARDS];
123 static int jackpoll_ms[SNDRV_CARDS];
124 static bool single_cmd;
125 static int enable_msi = -1;
126 #ifdef CONFIG_SND_HDA_PATCH_LOADER
127 static char *patch[SNDRV_CARDS];
128 #endif
129 #ifdef CONFIG_SND_HDA_INPUT_BEEP
130 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
131 CONFIG_SND_HDA_INPUT_BEEP_MODE};
132 #endif
133
134 module_param_array(index, int, NULL, 0444);
135 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
136 module_param_array(id, charp, NULL, 0444);
137 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
138 module_param_array(enable, bool, NULL, 0444);
139 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
140 module_param_array(model, charp, NULL, 0444);
141 MODULE_PARM_DESC(model, "Use the given board model.");
142 module_param_array(position_fix, int, NULL, 0444);
143 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
144 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
145 module_param_array(bdl_pos_adj, int, NULL, 0644);
146 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
147 module_param_array(probe_mask, int, NULL, 0444);
148 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
149 module_param_array(probe_only, int, NULL, 0444);
150 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
151 module_param_array(jackpoll_ms, int, NULL, 0444);
152 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
153 module_param(single_cmd, bool, 0444);
154 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
155 "(for debugging only).");
156 module_param(enable_msi, bint, 0444);
157 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
158 #ifdef CONFIG_SND_HDA_PATCH_LOADER
159 module_param_array(patch, charp, NULL, 0444);
160 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
161 #endif
162 #ifdef CONFIG_SND_HDA_INPUT_BEEP
163 module_param_array(beep_mode, bool, NULL, 0444);
164 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
165 "(0=off, 1=on) (default=1).");
166 #endif
167
168 #ifdef CONFIG_PM
169 static int param_set_xint(const char *val, const struct kernel_param *kp);
170 static struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173 };
174 #define param_check_xint param_check_int
175
176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
177 static int *power_save_addr = &power_save;
178 module_param(power_save, xint, 0644);
179 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
180 "(in second, 0 = disable).");
181
182 /* reset the HD-audio controller in power save mode.
183 * this may give more power-saving, but will take longer time to
184 * wake up.
185 */
186 static bool power_save_controller = 1;
187 module_param(power_save_controller, bool, 0644);
188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
189 #else
190 static int *power_save_addr;
191 #endif /* CONFIG_PM */
192
193 static int align_buffer_size = -1;
194 module_param(align_buffer_size, bint, 0644);
195 MODULE_PARM_DESC(align_buffer_size,
196 "Force buffer and period sizes to be multiple of 128 bytes.");
197
198 #ifdef CONFIG_X86
199 static bool hda_snoop = true;
200 module_param_named(snoop, hda_snoop, bool, 0444);
201 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
202 #else
203 #define hda_snoop true
204 #endif
205
206
207 MODULE_LICENSE("GPL");
208 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
209 "{Intel, ICH6M},"
210 "{Intel, ICH7},"
211 "{Intel, ESB2},"
212 "{Intel, ICH8},"
213 "{Intel, ICH9},"
214 "{Intel, ICH10},"
215 "{Intel, PCH},"
216 "{Intel, CPT},"
217 "{Intel, PPT},"
218 "{Intel, LPT},"
219 "{Intel, LPT_LP},"
220 "{Intel, WPT_LP},"
221 "{Intel, SPT},"
222 "{Intel, SPT_LP},"
223 "{Intel, HPT},"
224 "{Intel, PBG},"
225 "{Intel, SCH},"
226 "{ATI, SB450},"
227 "{ATI, SB600},"
228 "{ATI, RS600},"
229 "{ATI, RS690},"
230 "{ATI, RS780},"
231 "{ATI, R600},"
232 "{ATI, RV630},"
233 "{ATI, RV610},"
234 "{ATI, RV670},"
235 "{ATI, RV635},"
236 "{ATI, RV620},"
237 "{ATI, RV770},"
238 "{VIA, VT8251},"
239 "{VIA, VT8237A},"
240 "{SiS, SIS966},"
241 "{ULI, M5461}}");
242 MODULE_DESCRIPTION("Intel HDA driver");
243
244 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
245 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
246 #define SUPPORT_VGA_SWITCHEROO
247 #endif
248 #endif
249
250
251 /*
252 */
253
254 /* driver types */
255 enum {
256 AZX_DRIVER_ICH,
257 AZX_DRIVER_PCH,
258 AZX_DRIVER_SCH,
259 AZX_DRIVER_HDMI,
260 AZX_DRIVER_ATI,
261 AZX_DRIVER_ATIHDMI,
262 AZX_DRIVER_ATIHDMI_NS,
263 AZX_DRIVER_VIA,
264 AZX_DRIVER_SIS,
265 AZX_DRIVER_ULI,
266 AZX_DRIVER_NVIDIA,
267 AZX_DRIVER_TERA,
268 AZX_DRIVER_CTX,
269 AZX_DRIVER_CTHDA,
270 AZX_DRIVER_CMEDIA,
271 AZX_DRIVER_GENERIC,
272 AZX_NUM_DRIVERS, /* keep this as last entry */
273 };
274
275 /* quirks for Intel PCH */
276 #define AZX_DCAPS_INTEL_PCH_NOPM \
277 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
278 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_REVERSE_ASSIGN)
279
280 #define AZX_DCAPS_INTEL_PCH \
281 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
282
283 #define AZX_DCAPS_INTEL_HASWELL \
284 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
285 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
286 AZX_DCAPS_I915_POWERWELL)
287
288 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
289 #define AZX_DCAPS_INTEL_BROADWELL \
290 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
291 AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_PM_RUNTIME | \
292 AZX_DCAPS_I915_POWERWELL)
293
294 /* quirks for ATI SB / AMD Hudson */
295 #define AZX_DCAPS_PRESET_ATI_SB \
296 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
297 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
298
299 /* quirks for ATI/AMD HDMI */
300 #define AZX_DCAPS_PRESET_ATI_HDMI \
301 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
302
303 /* quirks for Nvidia */
304 #define AZX_DCAPS_PRESET_NVIDIA \
305 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
306 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT |\
307 AZX_DCAPS_CORBRP_SELF_CLEAR)
308
309 #define AZX_DCAPS_PRESET_CTHDA \
310 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
311
312 /*
313 * VGA-switcher support
314 */
315 #ifdef SUPPORT_VGA_SWITCHEROO
316 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
317 #else
318 #define use_vga_switcheroo(chip) 0
319 #endif
320
321 static char *driver_short_names[] = {
322 [AZX_DRIVER_ICH] = "HDA Intel",
323 [AZX_DRIVER_PCH] = "HDA Intel PCH",
324 [AZX_DRIVER_SCH] = "HDA Intel MID",
325 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
326 [AZX_DRIVER_ATI] = "HDA ATI SB",
327 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
328 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
329 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
330 [AZX_DRIVER_SIS] = "HDA SIS966",
331 [AZX_DRIVER_ULI] = "HDA ULI M5461",
332 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
333 [AZX_DRIVER_TERA] = "HDA Teradici",
334 [AZX_DRIVER_CTX] = "HDA Creative",
335 [AZX_DRIVER_CTHDA] = "HDA Creative",
336 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
337 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
338 };
339
340 struct hda_intel {
341 struct azx chip;
342
343 /* for pending irqs */
344 struct work_struct irq_pending_work;
345
346 /* sync probing */
347 struct completion probe_wait;
348 struct work_struct probe_work;
349
350 /* card list (for power_save trigger) */
351 struct list_head list;
352
353 /* extra flags */
354 unsigned int irq_pending_warned:1;
355
356 /* VGA-switcheroo setup */
357 unsigned int use_vga_switcheroo:1;
358 unsigned int vga_switcheroo_registered:1;
359 unsigned int init_failed:1; /* delayed init failed */
360
361 /* secondary power domain for hdmi audio under vga device */
362 struct dev_pm_domain hdmi_pm_domain;
363 };
364
365 #ifdef CONFIG_X86
366 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
367 {
368 int pages;
369
370 if (azx_snoop(chip))
371 return;
372 if (!dmab || !dmab->area || !dmab->bytes)
373 return;
374
375 #ifdef CONFIG_SND_DMA_SGBUF
376 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
377 struct snd_sg_buf *sgbuf = dmab->private_data;
378 if (chip->driver_type == AZX_DRIVER_CMEDIA)
379 return; /* deal with only CORB/RIRB buffers */
380 if (on)
381 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
382 else
383 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
384 return;
385 }
386 #endif
387
388 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
389 if (on)
390 set_memory_wc((unsigned long)dmab->area, pages);
391 else
392 set_memory_wb((unsigned long)dmab->area, pages);
393 }
394
395 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
396 bool on)
397 {
398 __mark_pages_wc(chip, buf, on);
399 }
400 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
401 struct snd_pcm_substream *substream, bool on)
402 {
403 if (azx_dev->wc_marked != on) {
404 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
405 azx_dev->wc_marked = on;
406 }
407 }
408 #else
409 /* NOP for other archs */
410 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
411 bool on)
412 {
413 }
414 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
415 struct snd_pcm_substream *substream, bool on)
416 {
417 }
418 #endif
419
420 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
421
422 /*
423 * initialize the PCI registers
424 */
425 /* update bits in a PCI register byte */
426 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
427 unsigned char mask, unsigned char val)
428 {
429 unsigned char data;
430
431 pci_read_config_byte(pci, reg, &data);
432 data &= ~mask;
433 data |= (val & mask);
434 pci_write_config_byte(pci, reg, data);
435 }
436
437 static void azx_init_pci(struct azx *chip)
438 {
439 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
440 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
441 * Ensuring these bits are 0 clears playback static on some HD Audio
442 * codecs.
443 * The PCI register TCSEL is defined in the Intel manuals.
444 */
445 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
446 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
447 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
448 }
449
450 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
451 * we need to enable snoop.
452 */
453 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
454 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
455 azx_snoop(chip));
456 update_pci_byte(chip->pci,
457 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
458 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
459 }
460
461 /* For NVIDIA HDA, enable snoop */
462 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
463 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
464 azx_snoop(chip));
465 update_pci_byte(chip->pci,
466 NVIDIA_HDA_TRANSREG_ADDR,
467 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
468 update_pci_byte(chip->pci,
469 NVIDIA_HDA_ISTRM_COH,
470 0x01, NVIDIA_HDA_ENABLE_COHBIT);
471 update_pci_byte(chip->pci,
472 NVIDIA_HDA_OSTRM_COH,
473 0x01, NVIDIA_HDA_ENABLE_COHBIT);
474 }
475
476 /* Enable SCH/PCH snoop if needed */
477 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
478 unsigned short snoop;
479 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
480 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
481 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
482 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
483 if (!azx_snoop(chip))
484 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
485 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
486 pci_read_config_word(chip->pci,
487 INTEL_SCH_HDA_DEVC, &snoop);
488 }
489 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
490 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
491 "Disabled" : "Enabled");
492 }
493 }
494
495 /* calculate runtime delay from LPIB */
496 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
497 unsigned int pos)
498 {
499 struct snd_pcm_substream *substream = azx_dev->substream;
500 int stream = substream->stream;
501 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
502 int delay;
503
504 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
505 delay = pos - lpib_pos;
506 else
507 delay = lpib_pos - pos;
508 if (delay < 0) {
509 if (delay >= azx_dev->delay_negative_threshold)
510 delay = 0;
511 else
512 delay += azx_dev->bufsize;
513 }
514
515 if (delay >= azx_dev->period_bytes) {
516 dev_info(chip->card->dev,
517 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
518 delay, azx_dev->period_bytes);
519 delay = 0;
520 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
521 chip->get_delay[stream] = NULL;
522 }
523
524 return bytes_to_frames(substream->runtime, delay);
525 }
526
527 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
528
529 /* called from IRQ */
530 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
531 {
532 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
533 int ok;
534
535 ok = azx_position_ok(chip, azx_dev);
536 if (ok == 1) {
537 azx_dev->irq_pending = 0;
538 return ok;
539 } else if (ok == 0 && chip->bus && chip->bus->workq) {
540 /* bogus IRQ, process it later */
541 azx_dev->irq_pending = 1;
542 queue_work(chip->bus->workq, &hda->irq_pending_work);
543 }
544 return 0;
545 }
546
547 /*
548 * Check whether the current DMA position is acceptable for updating
549 * periods. Returns non-zero if it's OK.
550 *
551 * Many HD-audio controllers appear pretty inaccurate about
552 * the update-IRQ timing. The IRQ is issued before actually the
553 * data is processed. So, we need to process it afterwords in a
554 * workqueue.
555 */
556 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
557 {
558 struct snd_pcm_substream *substream = azx_dev->substream;
559 int stream = substream->stream;
560 u32 wallclk;
561 unsigned int pos;
562
563 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
564 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
565 return -1; /* bogus (too early) interrupt */
566
567 if (chip->get_position[stream])
568 pos = chip->get_position[stream](chip, azx_dev);
569 else { /* use the position buffer as default */
570 pos = azx_get_pos_posbuf(chip, azx_dev);
571 if (!pos || pos == (u32)-1) {
572 dev_info(chip->card->dev,
573 "Invalid position buffer, using LPIB read method instead.\n");
574 chip->get_position[stream] = azx_get_pos_lpib;
575 pos = azx_get_pos_lpib(chip, azx_dev);
576 chip->get_delay[stream] = NULL;
577 } else {
578 chip->get_position[stream] = azx_get_pos_posbuf;
579 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
580 chip->get_delay[stream] = azx_get_delay_from_lpib;
581 }
582 }
583
584 if (pos >= azx_dev->bufsize)
585 pos = 0;
586
587 if (WARN_ONCE(!azx_dev->period_bytes,
588 "hda-intel: zero azx_dev->period_bytes"))
589 return -1; /* this shouldn't happen! */
590 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
591 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
592 /* NG - it's below the first next period boundary */
593 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
594 azx_dev->start_wallclk += wallclk;
595 return 1; /* OK, it's fine */
596 }
597
598 /*
599 * The work for pending PCM period updates.
600 */
601 static void azx_irq_pending_work(struct work_struct *work)
602 {
603 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
604 struct azx *chip = &hda->chip;
605 int i, pending, ok;
606
607 if (!hda->irq_pending_warned) {
608 dev_info(chip->card->dev,
609 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
610 chip->card->number);
611 hda->irq_pending_warned = 1;
612 }
613
614 for (;;) {
615 pending = 0;
616 spin_lock_irq(&chip->reg_lock);
617 for (i = 0; i < chip->num_streams; i++) {
618 struct azx_dev *azx_dev = &chip->azx_dev[i];
619 if (!azx_dev->irq_pending ||
620 !azx_dev->substream ||
621 !azx_dev->running)
622 continue;
623 ok = azx_position_ok(chip, azx_dev);
624 if (ok > 0) {
625 azx_dev->irq_pending = 0;
626 spin_unlock(&chip->reg_lock);
627 snd_pcm_period_elapsed(azx_dev->substream);
628 spin_lock(&chip->reg_lock);
629 } else if (ok < 0) {
630 pending = 0; /* too early */
631 } else
632 pending++;
633 }
634 spin_unlock_irq(&chip->reg_lock);
635 if (!pending)
636 return;
637 msleep(1);
638 }
639 }
640
641 /* clear irq_pending flags and assure no on-going workq */
642 static void azx_clear_irq_pending(struct azx *chip)
643 {
644 int i;
645
646 spin_lock_irq(&chip->reg_lock);
647 for (i = 0; i < chip->num_streams; i++)
648 chip->azx_dev[i].irq_pending = 0;
649 spin_unlock_irq(&chip->reg_lock);
650 }
651
652 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
653 {
654 if (request_irq(chip->pci->irq, azx_interrupt,
655 chip->msi ? 0 : IRQF_SHARED,
656 KBUILD_MODNAME, chip)) {
657 dev_err(chip->card->dev,
658 "unable to grab IRQ %d, disabling device\n",
659 chip->pci->irq);
660 if (do_disconnect)
661 snd_card_disconnect(chip->card);
662 return -1;
663 }
664 chip->irq = chip->pci->irq;
665 pci_intx(chip->pci, !chip->msi);
666 return 0;
667 }
668
669 /* get the current DMA position with correction on VIA chips */
670 static unsigned int azx_via_get_position(struct azx *chip,
671 struct azx_dev *azx_dev)
672 {
673 unsigned int link_pos, mini_pos, bound_pos;
674 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
675 unsigned int fifo_size;
676
677 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
678 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
679 /* Playback, no problem using link position */
680 return link_pos;
681 }
682
683 /* Capture */
684 /* For new chipset,
685 * use mod to get the DMA position just like old chipset
686 */
687 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
688 mod_dma_pos %= azx_dev->period_bytes;
689
690 /* azx_dev->fifo_size can't get FIFO size of in stream.
691 * Get from base address + offset.
692 */
693 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
694
695 if (azx_dev->insufficient) {
696 /* Link position never gather than FIFO size */
697 if (link_pos <= fifo_size)
698 return 0;
699
700 azx_dev->insufficient = 0;
701 }
702
703 if (link_pos <= fifo_size)
704 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
705 else
706 mini_pos = link_pos - fifo_size;
707
708 /* Find nearest previous boudary */
709 mod_mini_pos = mini_pos % azx_dev->period_bytes;
710 mod_link_pos = link_pos % azx_dev->period_bytes;
711 if (mod_link_pos >= fifo_size)
712 bound_pos = link_pos - mod_link_pos;
713 else if (mod_dma_pos >= mod_mini_pos)
714 bound_pos = mini_pos - mod_mini_pos;
715 else {
716 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
717 if (bound_pos >= azx_dev->bufsize)
718 bound_pos = 0;
719 }
720
721 /* Calculate real DMA position we want */
722 return bound_pos + mod_dma_pos;
723 }
724
725 #ifdef CONFIG_PM
726 static DEFINE_MUTEX(card_list_lock);
727 static LIST_HEAD(card_list);
728
729 static void azx_add_card_list(struct azx *chip)
730 {
731 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
732 mutex_lock(&card_list_lock);
733 list_add(&hda->list, &card_list);
734 mutex_unlock(&card_list_lock);
735 }
736
737 static void azx_del_card_list(struct azx *chip)
738 {
739 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
740 mutex_lock(&card_list_lock);
741 list_del_init(&hda->list);
742 mutex_unlock(&card_list_lock);
743 }
744
745 /* trigger power-save check at writing parameter */
746 static int param_set_xint(const char *val, const struct kernel_param *kp)
747 {
748 struct hda_intel *hda;
749 struct azx *chip;
750 struct hda_codec *c;
751 int prev = power_save;
752 int ret = param_set_int(val, kp);
753
754 if (ret || prev == power_save)
755 return ret;
756
757 mutex_lock(&card_list_lock);
758 list_for_each_entry(hda, &card_list, list) {
759 chip = &hda->chip;
760 if (!chip->bus || chip->disabled)
761 continue;
762 list_for_each_entry(c, &chip->bus->codec_list, list)
763 snd_hda_power_sync(c);
764 }
765 mutex_unlock(&card_list_lock);
766 return 0;
767 }
768 #else
769 #define azx_add_card_list(chip) /* NOP */
770 #define azx_del_card_list(chip) /* NOP */
771 #endif /* CONFIG_PM */
772
773 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
774 /*
775 * power management
776 */
777 static int azx_suspend(struct device *dev)
778 {
779 struct pci_dev *pci = to_pci_dev(dev);
780 struct snd_card *card = dev_get_drvdata(dev);
781 struct azx *chip;
782 struct hda_intel *hda;
783 struct azx_pcm *p;
784
785 if (!card)
786 return 0;
787
788 chip = card->private_data;
789 hda = container_of(chip, struct hda_intel, chip);
790 if (chip->disabled || hda->init_failed)
791 return 0;
792
793 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
794 azx_clear_irq_pending(chip);
795 list_for_each_entry(p, &chip->pcm_list, list)
796 snd_pcm_suspend_all(p->pcm);
797 if (chip->initialized)
798 snd_hda_suspend(chip->bus);
799 azx_stop_chip(chip);
800 azx_enter_link_reset(chip);
801 if (chip->irq >= 0) {
802 free_irq(chip->irq, chip);
803 chip->irq = -1;
804 }
805
806 if (chip->msi)
807 pci_disable_msi(chip->pci);
808 pci_disable_device(pci);
809 pci_save_state(pci);
810 pci_set_power_state(pci, PCI_D3hot);
811 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
812 hda_display_power(false);
813 return 0;
814 }
815
816 static int azx_resume(struct device *dev)
817 {
818 struct pci_dev *pci = to_pci_dev(dev);
819 struct snd_card *card = dev_get_drvdata(dev);
820 struct azx *chip;
821 struct hda_intel *hda;
822
823 if (!card)
824 return 0;
825
826 chip = card->private_data;
827 hda = container_of(chip, struct hda_intel, chip);
828 if (chip->disabled || hda->init_failed)
829 return 0;
830
831 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
832 hda_display_power(true);
833 haswell_set_bclk(chip);
834 }
835 pci_set_power_state(pci, PCI_D0);
836 pci_restore_state(pci);
837 if (pci_enable_device(pci) < 0) {
838 dev_err(chip->card->dev,
839 "pci_enable_device failed, disabling device\n");
840 snd_card_disconnect(card);
841 return -EIO;
842 }
843 pci_set_master(pci);
844 if (chip->msi)
845 if (pci_enable_msi(pci) < 0)
846 chip->msi = 0;
847 if (azx_acquire_irq(chip, 1) < 0)
848 return -EIO;
849 azx_init_pci(chip);
850
851 azx_init_chip(chip, true);
852
853 snd_hda_resume(chip->bus);
854 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
855 return 0;
856 }
857 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
858
859 #ifdef CONFIG_PM_RUNTIME
860 static int azx_runtime_suspend(struct device *dev)
861 {
862 struct snd_card *card = dev_get_drvdata(dev);
863 struct azx *chip;
864 struct hda_intel *hda;
865
866 if (!card)
867 return 0;
868
869 chip = card->private_data;
870 hda = container_of(chip, struct hda_intel, chip);
871 if (chip->disabled || hda->init_failed)
872 return 0;
873
874 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
875 return 0;
876
877 /* enable controller wake up event */
878 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
879 STATESTS_INT_MASK);
880
881 azx_stop_chip(chip);
882 azx_enter_link_reset(chip);
883 azx_clear_irq_pending(chip);
884 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
885 hda_display_power(false);
886
887 return 0;
888 }
889
890 static int azx_runtime_resume(struct device *dev)
891 {
892 struct snd_card *card = dev_get_drvdata(dev);
893 struct azx *chip;
894 struct hda_intel *hda;
895 struct hda_bus *bus;
896 struct hda_codec *codec;
897 int status;
898
899 if (!card)
900 return 0;
901
902 chip = card->private_data;
903 hda = container_of(chip, struct hda_intel, chip);
904 if (chip->disabled || hda->init_failed)
905 return 0;
906
907 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
908 return 0;
909
910 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
911 hda_display_power(true);
912 haswell_set_bclk(chip);
913 }
914
915 /* Read STATESTS before controller reset */
916 status = azx_readw(chip, STATESTS);
917
918 azx_init_pci(chip);
919 azx_init_chip(chip, true);
920
921 bus = chip->bus;
922 if (status && bus) {
923 list_for_each_entry(codec, &bus->codec_list, list)
924 if (status & (1 << codec->addr))
925 queue_delayed_work(codec->bus->workq,
926 &codec->jackpoll_work, codec->jackpoll_interval);
927 }
928
929 /* disable controller Wake Up event*/
930 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
931 ~STATESTS_INT_MASK);
932
933 return 0;
934 }
935
936 static int azx_runtime_idle(struct device *dev)
937 {
938 struct snd_card *card = dev_get_drvdata(dev);
939 struct azx *chip;
940 struct hda_intel *hda;
941
942 if (!card)
943 return 0;
944
945 chip = card->private_data;
946 hda = container_of(chip, struct hda_intel, chip);
947 if (chip->disabled || hda->init_failed)
948 return 0;
949
950 if (!power_save_controller ||
951 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
952 return -EBUSY;
953
954 return 0;
955 }
956
957 #endif /* CONFIG_PM_RUNTIME */
958
959 #ifdef CONFIG_PM
960 static const struct dev_pm_ops azx_pm = {
961 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
962 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
963 };
964
965 #define AZX_PM_OPS &azx_pm
966 #else
967 #define AZX_PM_OPS NULL
968 #endif /* CONFIG_PM */
969
970
971 static int azx_probe_continue(struct azx *chip);
972
973 #ifdef SUPPORT_VGA_SWITCHEROO
974 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
975
976 static void azx_vs_set_state(struct pci_dev *pci,
977 enum vga_switcheroo_state state)
978 {
979 struct snd_card *card = pci_get_drvdata(pci);
980 struct azx *chip = card->private_data;
981 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
982 bool disabled;
983
984 wait_for_completion(&hda->probe_wait);
985 if (hda->init_failed)
986 return;
987
988 disabled = (state == VGA_SWITCHEROO_OFF);
989 if (chip->disabled == disabled)
990 return;
991
992 if (!chip->bus) {
993 chip->disabled = disabled;
994 if (!disabled) {
995 dev_info(chip->card->dev,
996 "Start delayed initialization\n");
997 if (azx_probe_continue(chip) < 0) {
998 dev_err(chip->card->dev, "initialization error\n");
999 hda->init_failed = true;
1000 }
1001 }
1002 } else {
1003 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1004 disabled ? "Disabling" : "Enabling");
1005 if (disabled) {
1006 pm_runtime_put_sync_suspend(card->dev);
1007 azx_suspend(card->dev);
1008 /* when we get suspended by vga switcheroo we end up in D3cold,
1009 * however we have no ACPI handle, so pci/acpi can't put us there,
1010 * put ourselves there */
1011 pci->current_state = PCI_D3cold;
1012 chip->disabled = true;
1013 if (snd_hda_lock_devices(chip->bus))
1014 dev_warn(chip->card->dev,
1015 "Cannot lock devices!\n");
1016 } else {
1017 snd_hda_unlock_devices(chip->bus);
1018 pm_runtime_get_noresume(card->dev);
1019 chip->disabled = false;
1020 azx_resume(card->dev);
1021 }
1022 }
1023 }
1024
1025 static bool azx_vs_can_switch(struct pci_dev *pci)
1026 {
1027 struct snd_card *card = pci_get_drvdata(pci);
1028 struct azx *chip = card->private_data;
1029 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1030
1031 wait_for_completion(&hda->probe_wait);
1032 if (hda->init_failed)
1033 return false;
1034 if (chip->disabled || !chip->bus)
1035 return true;
1036 if (snd_hda_lock_devices(chip->bus))
1037 return false;
1038 snd_hda_unlock_devices(chip->bus);
1039 return true;
1040 }
1041
1042 static void init_vga_switcheroo(struct azx *chip)
1043 {
1044 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1045 struct pci_dev *p = get_bound_vga(chip->pci);
1046 if (p) {
1047 dev_info(chip->card->dev,
1048 "Handle VGA-switcheroo audio client\n");
1049 hda->use_vga_switcheroo = 1;
1050 pci_dev_put(p);
1051 }
1052 }
1053
1054 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1055 .set_gpu_state = azx_vs_set_state,
1056 .can_switch = azx_vs_can_switch,
1057 };
1058
1059 static int register_vga_switcheroo(struct azx *chip)
1060 {
1061 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1062 int err;
1063
1064 if (!hda->use_vga_switcheroo)
1065 return 0;
1066 /* FIXME: currently only handling DIS controller
1067 * is there any machine with two switchable HDMI audio controllers?
1068 */
1069 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1070 VGA_SWITCHEROO_DIS,
1071 chip->bus != NULL);
1072 if (err < 0)
1073 return err;
1074 hda->vga_switcheroo_registered = 1;
1075
1076 /* register as an optimus hdmi audio power domain */
1077 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1078 &hda->hdmi_pm_domain);
1079 return 0;
1080 }
1081 #else
1082 #define init_vga_switcheroo(chip) /* NOP */
1083 #define register_vga_switcheroo(chip) 0
1084 #define check_hdmi_disabled(pci) false
1085 #endif /* SUPPORT_VGA_SWITCHER */
1086
1087 /*
1088 * destructor
1089 */
1090 static int azx_free(struct azx *chip)
1091 {
1092 struct pci_dev *pci = chip->pci;
1093 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1094 int i;
1095
1096 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1097 && chip->running)
1098 pm_runtime_get_noresume(&pci->dev);
1099
1100 azx_del_card_list(chip);
1101
1102 azx_notifier_unregister(chip);
1103
1104 hda->init_failed = 1; /* to be sure */
1105 complete_all(&hda->probe_wait);
1106
1107 if (use_vga_switcheroo(hda)) {
1108 if (chip->disabled && chip->bus)
1109 snd_hda_unlock_devices(chip->bus);
1110 if (hda->vga_switcheroo_registered)
1111 vga_switcheroo_unregister_client(chip->pci);
1112 }
1113
1114 if (chip->initialized) {
1115 azx_clear_irq_pending(chip);
1116 for (i = 0; i < chip->num_streams; i++)
1117 azx_stream_stop(chip, &chip->azx_dev[i]);
1118 azx_stop_chip(chip);
1119 }
1120
1121 if (chip->irq >= 0)
1122 free_irq(chip->irq, (void*)chip);
1123 if (chip->msi)
1124 pci_disable_msi(chip->pci);
1125 if (chip->remap_addr)
1126 iounmap(chip->remap_addr);
1127
1128 azx_free_stream_pages(chip);
1129 if (chip->region_requested)
1130 pci_release_regions(chip->pci);
1131 pci_disable_device(chip->pci);
1132 kfree(chip->azx_dev);
1133 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1134 if (chip->fw)
1135 release_firmware(chip->fw);
1136 #endif
1137 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1138 hda_display_power(false);
1139 hda_i915_exit();
1140 }
1141 kfree(hda);
1142
1143 return 0;
1144 }
1145
1146 static int azx_dev_free(struct snd_device *device)
1147 {
1148 return azx_free(device->device_data);
1149 }
1150
1151 #ifdef SUPPORT_VGA_SWITCHEROO
1152 /*
1153 * Check of disabled HDMI controller by vga-switcheroo
1154 */
1155 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1156 {
1157 struct pci_dev *p;
1158
1159 /* check only discrete GPU */
1160 switch (pci->vendor) {
1161 case PCI_VENDOR_ID_ATI:
1162 case PCI_VENDOR_ID_AMD:
1163 case PCI_VENDOR_ID_NVIDIA:
1164 if (pci->devfn == 1) {
1165 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1166 pci->bus->number, 0);
1167 if (p) {
1168 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1169 return p;
1170 pci_dev_put(p);
1171 }
1172 }
1173 break;
1174 }
1175 return NULL;
1176 }
1177
1178 static bool check_hdmi_disabled(struct pci_dev *pci)
1179 {
1180 bool vga_inactive = false;
1181 struct pci_dev *p = get_bound_vga(pci);
1182
1183 if (p) {
1184 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1185 vga_inactive = true;
1186 pci_dev_put(p);
1187 }
1188 return vga_inactive;
1189 }
1190 #endif /* SUPPORT_VGA_SWITCHEROO */
1191
1192 /*
1193 * white/black-listing for position_fix
1194 */
1195 static struct snd_pci_quirk position_fix_list[] = {
1196 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1197 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1198 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1199 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1200 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1201 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1202 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1203 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1204 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1205 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1206 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1207 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1208 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1209 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1210 {}
1211 };
1212
1213 static int check_position_fix(struct azx *chip, int fix)
1214 {
1215 const struct snd_pci_quirk *q;
1216
1217 switch (fix) {
1218 case POS_FIX_AUTO:
1219 case POS_FIX_LPIB:
1220 case POS_FIX_POSBUF:
1221 case POS_FIX_VIACOMBO:
1222 case POS_FIX_COMBO:
1223 return fix;
1224 }
1225
1226 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1227 if (q) {
1228 dev_info(chip->card->dev,
1229 "position_fix set to %d for device %04x:%04x\n",
1230 q->value, q->subvendor, q->subdevice);
1231 return q->value;
1232 }
1233
1234 /* Check VIA/ATI HD Audio Controller exist */
1235 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1236 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1237 return POS_FIX_VIACOMBO;
1238 }
1239 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1240 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1241 return POS_FIX_LPIB;
1242 }
1243 return POS_FIX_AUTO;
1244 }
1245
1246 static void assign_position_fix(struct azx *chip, int fix)
1247 {
1248 static azx_get_pos_callback_t callbacks[] = {
1249 [POS_FIX_AUTO] = NULL,
1250 [POS_FIX_LPIB] = azx_get_pos_lpib,
1251 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1252 [POS_FIX_VIACOMBO] = azx_via_get_position,
1253 [POS_FIX_COMBO] = azx_get_pos_lpib,
1254 };
1255
1256 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1257
1258 /* combo mode uses LPIB only for playback */
1259 if (fix == POS_FIX_COMBO)
1260 chip->get_position[1] = NULL;
1261
1262 if (fix == POS_FIX_POSBUF &&
1263 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1264 chip->get_delay[0] = chip->get_delay[1] =
1265 azx_get_delay_from_lpib;
1266 }
1267
1268 }
1269
1270 /*
1271 * black-lists for probe_mask
1272 */
1273 static struct snd_pci_quirk probe_mask_list[] = {
1274 /* Thinkpad often breaks the controller communication when accessing
1275 * to the non-working (or non-existing) modem codec slot.
1276 */
1277 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1278 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1279 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1280 /* broken BIOS */
1281 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1282 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1283 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1284 /* forced codec slots */
1285 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1286 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1287 /* WinFast VP200 H (Teradici) user reported broken communication */
1288 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1289 {}
1290 };
1291
1292 #define AZX_FORCE_CODEC_MASK 0x100
1293
1294 static void check_probe_mask(struct azx *chip, int dev)
1295 {
1296 const struct snd_pci_quirk *q;
1297
1298 chip->codec_probe_mask = probe_mask[dev];
1299 if (chip->codec_probe_mask == -1) {
1300 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1301 if (q) {
1302 dev_info(chip->card->dev,
1303 "probe_mask set to 0x%x for device %04x:%04x\n",
1304 q->value, q->subvendor, q->subdevice);
1305 chip->codec_probe_mask = q->value;
1306 }
1307 }
1308
1309 /* check forced option */
1310 if (chip->codec_probe_mask != -1 &&
1311 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1312 chip->codec_mask = chip->codec_probe_mask & 0xff;
1313 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1314 chip->codec_mask);
1315 }
1316 }
1317
1318 /*
1319 * white/black-list for enable_msi
1320 */
1321 static struct snd_pci_quirk msi_black_list[] = {
1322 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1323 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1324 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1325 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1326 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1327 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1328 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1329 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1330 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1331 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1332 {}
1333 };
1334
1335 static void check_msi(struct azx *chip)
1336 {
1337 const struct snd_pci_quirk *q;
1338
1339 if (enable_msi >= 0) {
1340 chip->msi = !!enable_msi;
1341 return;
1342 }
1343 chip->msi = 1; /* enable MSI as default */
1344 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1345 if (q) {
1346 dev_info(chip->card->dev,
1347 "msi for device %04x:%04x set to %d\n",
1348 q->subvendor, q->subdevice, q->value);
1349 chip->msi = q->value;
1350 return;
1351 }
1352
1353 /* NVidia chipsets seem to cause troubles with MSI */
1354 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1355 dev_info(chip->card->dev, "Disabling MSI\n");
1356 chip->msi = 0;
1357 }
1358 }
1359
1360 /* check the snoop mode availability */
1361 static void azx_check_snoop_available(struct azx *chip)
1362 {
1363 bool snoop = chip->snoop;
1364
1365 switch (chip->driver_type) {
1366 case AZX_DRIVER_VIA:
1367 /* force to non-snoop mode for a new VIA controller
1368 * when BIOS is set
1369 */
1370 if (snoop) {
1371 u8 val;
1372 pci_read_config_byte(chip->pci, 0x42, &val);
1373 if (!(val & 0x80) && chip->pci->revision == 0x30)
1374 snoop = false;
1375 }
1376 break;
1377 case AZX_DRIVER_ATIHDMI_NS:
1378 /* new ATI HDMI requires non-snoop */
1379 snoop = false;
1380 break;
1381 case AZX_DRIVER_CTHDA:
1382 case AZX_DRIVER_CMEDIA:
1383 snoop = false;
1384 break;
1385 }
1386
1387 if (snoop != chip->snoop) {
1388 dev_info(chip->card->dev, "Force to %s mode\n",
1389 snoop ? "snoop" : "non-snoop");
1390 chip->snoop = snoop;
1391 }
1392 }
1393
1394 static void azx_probe_work(struct work_struct *work)
1395 {
1396 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1397 azx_probe_continue(&hda->chip);
1398 }
1399
1400 /*
1401 * constructor
1402 */
1403 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1404 int dev, unsigned int driver_caps,
1405 const struct hda_controller_ops *hda_ops,
1406 struct azx **rchip)
1407 {
1408 static struct snd_device_ops ops = {
1409 .dev_free = azx_dev_free,
1410 };
1411 struct hda_intel *hda;
1412 struct azx *chip;
1413 int err;
1414
1415 *rchip = NULL;
1416
1417 err = pci_enable_device(pci);
1418 if (err < 0)
1419 return err;
1420
1421 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1422 if (!hda) {
1423 dev_err(card->dev, "Cannot allocate hda\n");
1424 pci_disable_device(pci);
1425 return -ENOMEM;
1426 }
1427
1428 chip = &hda->chip;
1429 spin_lock_init(&chip->reg_lock);
1430 mutex_init(&chip->open_mutex);
1431 chip->card = card;
1432 chip->pci = pci;
1433 chip->ops = hda_ops;
1434 chip->irq = -1;
1435 chip->driver_caps = driver_caps;
1436 chip->driver_type = driver_caps & 0xff;
1437 check_msi(chip);
1438 chip->dev_index = dev;
1439 chip->jackpoll_ms = jackpoll_ms;
1440 INIT_LIST_HEAD(&chip->pcm_list);
1441 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1442 INIT_LIST_HEAD(&hda->list);
1443 init_vga_switcheroo(chip);
1444 init_completion(&hda->probe_wait);
1445
1446 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1447
1448 check_probe_mask(chip, dev);
1449
1450 chip->single_cmd = single_cmd;
1451 chip->snoop = hda_snoop;
1452 azx_check_snoop_available(chip);
1453
1454 if (bdl_pos_adj[dev] < 0) {
1455 switch (chip->driver_type) {
1456 case AZX_DRIVER_ICH:
1457 case AZX_DRIVER_PCH:
1458 bdl_pos_adj[dev] = 1;
1459 break;
1460 default:
1461 bdl_pos_adj[dev] = 32;
1462 break;
1463 }
1464 }
1465 chip->bdl_pos_adj = bdl_pos_adj;
1466
1467 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1468 if (err < 0) {
1469 dev_err(card->dev, "Error creating device [card]!\n");
1470 azx_free(chip);
1471 return err;
1472 }
1473
1474 /* continue probing in work context as may trigger request module */
1475 INIT_WORK(&hda->probe_work, azx_probe_work);
1476
1477 *rchip = chip;
1478
1479 return 0;
1480 }
1481
1482 static int azx_first_init(struct azx *chip)
1483 {
1484 int dev = chip->dev_index;
1485 struct pci_dev *pci = chip->pci;
1486 struct snd_card *card = chip->card;
1487 int err;
1488 unsigned short gcap;
1489 unsigned int dma_bits = 64;
1490
1491 #if BITS_PER_LONG != 64
1492 /* Fix up base address on ULI M5461 */
1493 if (chip->driver_type == AZX_DRIVER_ULI) {
1494 u16 tmp3;
1495 pci_read_config_word(pci, 0x40, &tmp3);
1496 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1497 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1498 }
1499 #endif
1500
1501 err = pci_request_regions(pci, "ICH HD audio");
1502 if (err < 0)
1503 return err;
1504 chip->region_requested = 1;
1505
1506 chip->addr = pci_resource_start(pci, 0);
1507 chip->remap_addr = pci_ioremap_bar(pci, 0);
1508 if (chip->remap_addr == NULL) {
1509 dev_err(card->dev, "ioremap error\n");
1510 return -ENXIO;
1511 }
1512
1513 if (chip->msi)
1514 if (pci_enable_msi(pci) < 0)
1515 chip->msi = 0;
1516
1517 if (azx_acquire_irq(chip, 0) < 0)
1518 return -EBUSY;
1519
1520 pci_set_master(pci);
1521 synchronize_irq(chip->irq);
1522
1523 gcap = azx_readw(chip, GCAP);
1524 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1525
1526 /* AMD devices support 40 or 48bit DMA, take the safe one */
1527 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1528 dma_bits = 40;
1529
1530 /* disable SB600 64bit support for safety */
1531 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1532 struct pci_dev *p_smbus;
1533 dma_bits = 40;
1534 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1535 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1536 NULL);
1537 if (p_smbus) {
1538 if (p_smbus->revision < 0x30)
1539 gcap &= ~AZX_GCAP_64OK;
1540 pci_dev_put(p_smbus);
1541 }
1542 }
1543
1544 /* disable 64bit DMA address on some devices */
1545 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1546 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1547 gcap &= ~AZX_GCAP_64OK;
1548 }
1549
1550 /* disable buffer size rounding to 128-byte multiples if supported */
1551 if (align_buffer_size >= 0)
1552 chip->align_buffer_size = !!align_buffer_size;
1553 else {
1554 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
1555 chip->align_buffer_size = 0;
1556 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
1557 chip->align_buffer_size = 1;
1558 else
1559 chip->align_buffer_size = 1;
1560 }
1561
1562 /* allow 64bit DMA address if supported by H/W */
1563 if (!(gcap & AZX_GCAP_64OK))
1564 dma_bits = 32;
1565 if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) {
1566 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits));
1567 } else {
1568 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
1569 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
1570 }
1571
1572 /* read number of streams from GCAP register instead of using
1573 * hardcoded value
1574 */
1575 chip->capture_streams = (gcap >> 8) & 0x0f;
1576 chip->playback_streams = (gcap >> 12) & 0x0f;
1577 if (!chip->playback_streams && !chip->capture_streams) {
1578 /* gcap didn't give any info, switching to old method */
1579
1580 switch (chip->driver_type) {
1581 case AZX_DRIVER_ULI:
1582 chip->playback_streams = ULI_NUM_PLAYBACK;
1583 chip->capture_streams = ULI_NUM_CAPTURE;
1584 break;
1585 case AZX_DRIVER_ATIHDMI:
1586 case AZX_DRIVER_ATIHDMI_NS:
1587 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1588 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1589 break;
1590 case AZX_DRIVER_GENERIC:
1591 default:
1592 chip->playback_streams = ICH6_NUM_PLAYBACK;
1593 chip->capture_streams = ICH6_NUM_CAPTURE;
1594 break;
1595 }
1596 }
1597 chip->capture_index_offset = 0;
1598 chip->playback_index_offset = chip->capture_streams;
1599 chip->num_streams = chip->playback_streams + chip->capture_streams;
1600 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1601 GFP_KERNEL);
1602 if (!chip->azx_dev) {
1603 dev_err(card->dev, "cannot malloc azx_dev\n");
1604 return -ENOMEM;
1605 }
1606
1607 err = azx_alloc_stream_pages(chip);
1608 if (err < 0)
1609 return err;
1610
1611 /* initialize streams */
1612 azx_init_stream(chip);
1613
1614 /* initialize chip */
1615 azx_init_pci(chip);
1616
1617 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1618 haswell_set_bclk(chip);
1619
1620 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
1621
1622 /* codec detection */
1623 if (!chip->codec_mask) {
1624 dev_err(card->dev, "no codecs found!\n");
1625 return -ENODEV;
1626 }
1627
1628 strcpy(card->driver, "HDA-Intel");
1629 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1630 sizeof(card->shortname));
1631 snprintf(card->longname, sizeof(card->longname),
1632 "%s at 0x%lx irq %i",
1633 card->shortname, chip->addr, chip->irq);
1634
1635 return 0;
1636 }
1637
1638 static void power_down_all_codecs(struct azx *chip)
1639 {
1640 #ifdef CONFIG_PM
1641 /* The codecs were powered up in snd_hda_codec_new().
1642 * Now all initialization done, so turn them down if possible
1643 */
1644 struct hda_codec *codec;
1645 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1646 snd_hda_power_down(codec);
1647 }
1648 #endif
1649 }
1650
1651 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1652 /* callback from request_firmware_nowait() */
1653 static void azx_firmware_cb(const struct firmware *fw, void *context)
1654 {
1655 struct snd_card *card = context;
1656 struct azx *chip = card->private_data;
1657 struct pci_dev *pci = chip->pci;
1658
1659 if (!fw) {
1660 dev_err(card->dev, "Cannot load firmware, aborting\n");
1661 goto error;
1662 }
1663
1664 chip->fw = fw;
1665 if (!chip->disabled) {
1666 /* continue probing */
1667 if (azx_probe_continue(chip))
1668 goto error;
1669 }
1670 return; /* OK */
1671
1672 error:
1673 snd_card_free(card);
1674 pci_set_drvdata(pci, NULL);
1675 }
1676 #endif
1677
1678 /*
1679 * HDA controller ops.
1680 */
1681
1682 /* PCI register access. */
1683 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1684 {
1685 writel(value, addr);
1686 }
1687
1688 static u32 pci_azx_readl(u32 __iomem *addr)
1689 {
1690 return readl(addr);
1691 }
1692
1693 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1694 {
1695 writew(value, addr);
1696 }
1697
1698 static u16 pci_azx_readw(u16 __iomem *addr)
1699 {
1700 return readw(addr);
1701 }
1702
1703 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1704 {
1705 writeb(value, addr);
1706 }
1707
1708 static u8 pci_azx_readb(u8 __iomem *addr)
1709 {
1710 return readb(addr);
1711 }
1712
1713 static int disable_msi_reset_irq(struct azx *chip)
1714 {
1715 int err;
1716
1717 free_irq(chip->irq, chip);
1718 chip->irq = -1;
1719 pci_disable_msi(chip->pci);
1720 chip->msi = 0;
1721 err = azx_acquire_irq(chip, 1);
1722 if (err < 0)
1723 return err;
1724
1725 return 0;
1726 }
1727
1728 /* DMA page allocation helpers. */
1729 static int dma_alloc_pages(struct azx *chip,
1730 int type,
1731 size_t size,
1732 struct snd_dma_buffer *buf)
1733 {
1734 int err;
1735
1736 err = snd_dma_alloc_pages(type,
1737 chip->card->dev,
1738 size, buf);
1739 if (err < 0)
1740 return err;
1741 mark_pages_wc(chip, buf, true);
1742 return 0;
1743 }
1744
1745 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
1746 {
1747 mark_pages_wc(chip, buf, false);
1748 snd_dma_free_pages(buf);
1749 }
1750
1751 static int substream_alloc_pages(struct azx *chip,
1752 struct snd_pcm_substream *substream,
1753 size_t size)
1754 {
1755 struct azx_dev *azx_dev = get_azx_dev(substream);
1756 int ret;
1757
1758 mark_runtime_wc(chip, azx_dev, substream, false);
1759 azx_dev->bufsize = 0;
1760 azx_dev->period_bytes = 0;
1761 azx_dev->format_val = 0;
1762 ret = snd_pcm_lib_malloc_pages(substream, size);
1763 if (ret < 0)
1764 return ret;
1765 mark_runtime_wc(chip, azx_dev, substream, true);
1766 return 0;
1767 }
1768
1769 static int substream_free_pages(struct azx *chip,
1770 struct snd_pcm_substream *substream)
1771 {
1772 struct azx_dev *azx_dev = get_azx_dev(substream);
1773 mark_runtime_wc(chip, azx_dev, substream, false);
1774 return snd_pcm_lib_free_pages(substream);
1775 }
1776
1777 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1778 struct vm_area_struct *area)
1779 {
1780 #ifdef CONFIG_X86
1781 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1782 struct azx *chip = apcm->chip;
1783 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1784 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1785 #endif
1786 }
1787
1788 static const struct hda_controller_ops pci_hda_ops = {
1789 .reg_writel = pci_azx_writel,
1790 .reg_readl = pci_azx_readl,
1791 .reg_writew = pci_azx_writew,
1792 .reg_readw = pci_azx_readw,
1793 .reg_writeb = pci_azx_writeb,
1794 .reg_readb = pci_azx_readb,
1795 .disable_msi_reset_irq = disable_msi_reset_irq,
1796 .dma_alloc_pages = dma_alloc_pages,
1797 .dma_free_pages = dma_free_pages,
1798 .substream_alloc_pages = substream_alloc_pages,
1799 .substream_free_pages = substream_free_pages,
1800 .pcm_mmap_prepare = pcm_mmap_prepare,
1801 .position_check = azx_position_check,
1802 };
1803
1804 static int azx_probe(struct pci_dev *pci,
1805 const struct pci_device_id *pci_id)
1806 {
1807 static int dev;
1808 struct snd_card *card;
1809 struct hda_intel *hda;
1810 struct azx *chip;
1811 bool schedule_probe;
1812 int err;
1813
1814 if (dev >= SNDRV_CARDS)
1815 return -ENODEV;
1816 if (!enable[dev]) {
1817 dev++;
1818 return -ENOENT;
1819 }
1820
1821 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1822 0, &card);
1823 if (err < 0) {
1824 dev_err(&pci->dev, "Error creating card!\n");
1825 return err;
1826 }
1827
1828 err = azx_create(card, pci, dev, pci_id->driver_data,
1829 &pci_hda_ops, &chip);
1830 if (err < 0)
1831 goto out_free;
1832 card->private_data = chip;
1833 hda = container_of(chip, struct hda_intel, chip);
1834
1835 pci_set_drvdata(pci, card);
1836
1837 err = register_vga_switcheroo(chip);
1838 if (err < 0) {
1839 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
1840 goto out_free;
1841 }
1842
1843 if (check_hdmi_disabled(pci)) {
1844 dev_info(card->dev, "VGA controller is disabled\n");
1845 dev_info(card->dev, "Delaying initialization\n");
1846 chip->disabled = true;
1847 }
1848
1849 schedule_probe = !chip->disabled;
1850
1851 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1852 if (patch[dev] && *patch[dev]) {
1853 dev_info(card->dev, "Applying patch firmware '%s'\n",
1854 patch[dev]);
1855 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
1856 &pci->dev, GFP_KERNEL, card,
1857 azx_firmware_cb);
1858 if (err < 0)
1859 goto out_free;
1860 schedule_probe = false; /* continued in azx_firmware_cb() */
1861 }
1862 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
1863
1864 #ifndef CONFIG_SND_HDA_I915
1865 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1866 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
1867 #endif
1868
1869 if (schedule_probe)
1870 schedule_work(&hda->probe_work);
1871
1872 dev++;
1873 if (chip->disabled)
1874 complete_all(&hda->probe_wait);
1875 return 0;
1876
1877 out_free:
1878 snd_card_free(card);
1879 return err;
1880 }
1881
1882 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1883 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1884 [AZX_DRIVER_NVIDIA] = 8,
1885 [AZX_DRIVER_TERA] = 1,
1886 };
1887
1888 static int azx_probe_continue(struct azx *chip)
1889 {
1890 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1891 struct pci_dev *pci = chip->pci;
1892 int dev = chip->dev_index;
1893 int err;
1894
1895 /* Request power well for Haswell HDA controller and codec */
1896 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1897 #ifdef CONFIG_SND_HDA_I915
1898 err = hda_i915_init();
1899 if (err < 0) {
1900 dev_err(chip->card->dev,
1901 "Error request power-well from i915\n");
1902 goto out_free;
1903 }
1904 err = hda_display_power(true);
1905 if (err < 0) {
1906 dev_err(chip->card->dev,
1907 "Cannot turn on display power on i915\n");
1908 goto out_free;
1909 }
1910 #endif
1911 }
1912
1913 err = azx_first_init(chip);
1914 if (err < 0)
1915 goto out_free;
1916
1917 #ifdef CONFIG_SND_HDA_INPUT_BEEP
1918 chip->beep_mode = beep_mode[dev];
1919 #endif
1920
1921 /* create codec instances */
1922 err = azx_codec_create(chip, model[dev],
1923 azx_max_codecs[chip->driver_type],
1924 power_save_addr);
1925
1926 if (err < 0)
1927 goto out_free;
1928 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1929 if (chip->fw) {
1930 err = snd_hda_load_patch(chip->bus, chip->fw->size,
1931 chip->fw->data);
1932 if (err < 0)
1933 goto out_free;
1934 #ifndef CONFIG_PM
1935 release_firmware(chip->fw); /* no longer needed */
1936 chip->fw = NULL;
1937 #endif
1938 }
1939 #endif
1940 if ((probe_only[dev] & 1) == 0) {
1941 err = azx_codec_configure(chip);
1942 if (err < 0)
1943 goto out_free;
1944 }
1945
1946 /* create PCM streams */
1947 err = snd_hda_build_pcms(chip->bus);
1948 if (err < 0)
1949 goto out_free;
1950
1951 /* create mixer controls */
1952 err = azx_mixer_create(chip);
1953 if (err < 0)
1954 goto out_free;
1955
1956 err = snd_card_register(chip->card);
1957 if (err < 0)
1958 goto out_free;
1959
1960 chip->running = 1;
1961 power_down_all_codecs(chip);
1962 azx_notifier_register(chip);
1963 azx_add_card_list(chip);
1964 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || hda->use_vga_switcheroo)
1965 pm_runtime_put_noidle(&pci->dev);
1966
1967 out_free:
1968 if (err < 0)
1969 hda->init_failed = 1;
1970 complete_all(&hda->probe_wait);
1971 return err;
1972 }
1973
1974 static void azx_remove(struct pci_dev *pci)
1975 {
1976 struct snd_card *card = pci_get_drvdata(pci);
1977
1978 if (card)
1979 snd_card_free(card);
1980 }
1981
1982 /* PCI IDs */
1983 static const struct pci_device_id azx_ids[] = {
1984 /* CPT */
1985 { PCI_DEVICE(0x8086, 0x1c20),
1986 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1987 /* PBG */
1988 { PCI_DEVICE(0x8086, 0x1d20),
1989 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1990 /* Panther Point */
1991 { PCI_DEVICE(0x8086, 0x1e20),
1992 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1993 /* Lynx Point */
1994 { PCI_DEVICE(0x8086, 0x8c20),
1995 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1996 /* 9 Series */
1997 { PCI_DEVICE(0x8086, 0x8ca0),
1998 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
1999 /* Wellsburg */
2000 { PCI_DEVICE(0x8086, 0x8d20),
2001 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2002 { PCI_DEVICE(0x8086, 0x8d21),
2003 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2004 /* Lynx Point-LP */
2005 { PCI_DEVICE(0x8086, 0x9c20),
2006 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2007 /* Lynx Point-LP */
2008 { PCI_DEVICE(0x8086, 0x9c21),
2009 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2010 /* Wildcat Point-LP */
2011 { PCI_DEVICE(0x8086, 0x9ca0),
2012 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2013 /* Sunrise Point */
2014 { PCI_DEVICE(0x8086, 0xa170),
2015 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2016 /* Sunrise Point-LP */
2017 { PCI_DEVICE(0x8086, 0x9d70),
2018 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2019 /* Haswell */
2020 { PCI_DEVICE(0x8086, 0x0a0c),
2021 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2022 { PCI_DEVICE(0x8086, 0x0c0c),
2023 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2024 { PCI_DEVICE(0x8086, 0x0d0c),
2025 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2026 /* Broadwell */
2027 { PCI_DEVICE(0x8086, 0x160c),
2028 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2029 /* 5 Series/3400 */
2030 { PCI_DEVICE(0x8086, 0x3b56),
2031 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2032 /* Poulsbo */
2033 { PCI_DEVICE(0x8086, 0x811b),
2034 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2035 /* Oaktrail */
2036 { PCI_DEVICE(0x8086, 0x080a),
2037 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2038 /* BayTrail */
2039 { PCI_DEVICE(0x8086, 0x0f04),
2040 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2041 /* Braswell */
2042 { PCI_DEVICE(0x8086, 0x2284),
2043 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2044 /* ICH */
2045 { PCI_DEVICE(0x8086, 0x2668),
2046 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2047 AZX_DCAPS_BUFSIZE }, /* ICH6 */
2048 { PCI_DEVICE(0x8086, 0x27d8),
2049 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2050 AZX_DCAPS_BUFSIZE }, /* ICH7 */
2051 { PCI_DEVICE(0x8086, 0x269a),
2052 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2053 AZX_DCAPS_BUFSIZE }, /* ESB2 */
2054 { PCI_DEVICE(0x8086, 0x284b),
2055 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2056 AZX_DCAPS_BUFSIZE }, /* ICH8 */
2057 { PCI_DEVICE(0x8086, 0x293e),
2058 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2059 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2060 { PCI_DEVICE(0x8086, 0x293f),
2061 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2062 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2063 { PCI_DEVICE(0x8086, 0x3a3e),
2064 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2065 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2066 { PCI_DEVICE(0x8086, 0x3a6e),
2067 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2068 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2069 /* Generic Intel */
2070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2071 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2072 .class_mask = 0xffffff,
2073 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
2074 /* ATI SB 450/600/700/800/900 */
2075 { PCI_DEVICE(0x1002, 0x437b),
2076 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2077 { PCI_DEVICE(0x1002, 0x4383),
2078 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2079 /* AMD Hudson */
2080 { PCI_DEVICE(0x1022, 0x780d),
2081 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2082 /* ATI HDMI */
2083 { PCI_DEVICE(0x1002, 0x793b),
2084 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2085 { PCI_DEVICE(0x1002, 0x7919),
2086 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2087 { PCI_DEVICE(0x1002, 0x960f),
2088 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2089 { PCI_DEVICE(0x1002, 0x970f),
2090 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2091 { PCI_DEVICE(0x1002, 0xaa00),
2092 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2093 { PCI_DEVICE(0x1002, 0xaa08),
2094 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2095 { PCI_DEVICE(0x1002, 0xaa10),
2096 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2097 { PCI_DEVICE(0x1002, 0xaa18),
2098 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2099 { PCI_DEVICE(0x1002, 0xaa20),
2100 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2101 { PCI_DEVICE(0x1002, 0xaa28),
2102 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2103 { PCI_DEVICE(0x1002, 0xaa30),
2104 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2105 { PCI_DEVICE(0x1002, 0xaa38),
2106 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2107 { PCI_DEVICE(0x1002, 0xaa40),
2108 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2109 { PCI_DEVICE(0x1002, 0xaa48),
2110 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2111 { PCI_DEVICE(0x1002, 0xaa50),
2112 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2113 { PCI_DEVICE(0x1002, 0xaa58),
2114 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2115 { PCI_DEVICE(0x1002, 0xaa60),
2116 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2117 { PCI_DEVICE(0x1002, 0xaa68),
2118 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2119 { PCI_DEVICE(0x1002, 0xaa80),
2120 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2121 { PCI_DEVICE(0x1002, 0xaa88),
2122 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2123 { PCI_DEVICE(0x1002, 0xaa90),
2124 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2125 { PCI_DEVICE(0x1002, 0xaa98),
2126 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2127 { PCI_DEVICE(0x1002, 0x9902),
2128 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2129 { PCI_DEVICE(0x1002, 0xaaa0),
2130 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2131 { PCI_DEVICE(0x1002, 0xaaa8),
2132 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2133 { PCI_DEVICE(0x1002, 0xaab0),
2134 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2135 /* VIA VT8251/VT8237A */
2136 { PCI_DEVICE(0x1106, 0x3288),
2137 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2138 /* VIA GFX VT7122/VX900 */
2139 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2140 /* VIA GFX VT6122/VX11 */
2141 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2142 /* SIS966 */
2143 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2144 /* ULI M5461 */
2145 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2146 /* NVIDIA MCP */
2147 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2148 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2149 .class_mask = 0xffffff,
2150 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2151 /* Teradici */
2152 { PCI_DEVICE(0x6549, 0x1200),
2153 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2154 { PCI_DEVICE(0x6549, 0x2200),
2155 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2156 /* Creative X-Fi (CA0110-IBG) */
2157 /* CTHDA chips */
2158 { PCI_DEVICE(0x1102, 0x0010),
2159 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2160 { PCI_DEVICE(0x1102, 0x0012),
2161 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2162 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2163 /* the following entry conflicts with snd-ctxfi driver,
2164 * as ctxfi driver mutates from HD-audio to native mode with
2165 * a special command sequence.
2166 */
2167 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2168 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2169 .class_mask = 0xffffff,
2170 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2171 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2172 #else
2173 /* this entry seems still valid -- i.e. without emu20kx chip */
2174 { PCI_DEVICE(0x1102, 0x0009),
2175 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2176 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2177 #endif
2178 /* CM8888 */
2179 { PCI_DEVICE(0x13f6, 0x5011),
2180 .driver_data = AZX_DRIVER_CMEDIA |
2181 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB },
2182 /* Vortex86MX */
2183 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2184 /* VMware HDAudio */
2185 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2186 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2187 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2188 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2189 .class_mask = 0xffffff,
2190 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2191 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2192 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2193 .class_mask = 0xffffff,
2194 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2195 { 0, }
2196 };
2197 MODULE_DEVICE_TABLE(pci, azx_ids);
2198
2199 /* pci_driver definition */
2200 static struct pci_driver azx_driver = {
2201 .name = KBUILD_MODNAME,
2202 .id_table = azx_ids,
2203 .probe = azx_probe,
2204 .remove = azx_remove,
2205 .driver = {
2206 .pm = AZX_PM_OPS,
2207 },
2208 };
2209
2210 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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