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ALSA: hda - Add function pointer for disabling MSI
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65 #include "hda_i915.h"
66 #include "hda_priv.h"
67
68
69 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
70 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
71 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
72 static char *model[SNDRV_CARDS];
73 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
75 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
76 static int probe_only[SNDRV_CARDS];
77 static int jackpoll_ms[SNDRV_CARDS];
78 static bool single_cmd;
79 static int enable_msi = -1;
80 #ifdef CONFIG_SND_HDA_PATCH_LOADER
81 static char *patch[SNDRV_CARDS];
82 #endif
83 #ifdef CONFIG_SND_HDA_INPUT_BEEP
84 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
85 CONFIG_SND_HDA_INPUT_BEEP_MODE};
86 #endif
87
88 module_param_array(index, int, NULL, 0444);
89 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
90 module_param_array(id, charp, NULL, 0444);
91 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
92 module_param_array(enable, bool, NULL, 0444);
93 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
94 module_param_array(model, charp, NULL, 0444);
95 MODULE_PARM_DESC(model, "Use the given board model.");
96 module_param_array(position_fix, int, NULL, 0444);
97 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
98 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
99 module_param_array(bdl_pos_adj, int, NULL, 0644);
100 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
101 module_param_array(probe_mask, int, NULL, 0444);
102 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
103 module_param_array(probe_only, int, NULL, 0444);
104 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
105 module_param_array(jackpoll_ms, int, NULL, 0444);
106 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
107 module_param(single_cmd, bool, 0444);
108 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
109 "(for debugging only).");
110 module_param(enable_msi, bint, 0444);
111 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
112 #ifdef CONFIG_SND_HDA_PATCH_LOADER
113 module_param_array(patch, charp, NULL, 0444);
114 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
115 #endif
116 #ifdef CONFIG_SND_HDA_INPUT_BEEP
117 module_param_array(beep_mode, bool, NULL, 0444);
118 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
119 "(0=off, 1=on) (default=1).");
120 #endif
121
122 #ifdef CONFIG_PM
123 static int param_set_xint(const char *val, const struct kernel_param *kp);
124 static struct kernel_param_ops param_ops_xint = {
125 .set = param_set_xint,
126 .get = param_get_int,
127 };
128 #define param_check_xint param_check_int
129
130 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
131 module_param(power_save, xint, 0644);
132 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
133 "(in second, 0 = disable).");
134
135 /* reset the HD-audio controller in power save mode.
136 * this may give more power-saving, but will take longer time to
137 * wake up.
138 */
139 static bool power_save_controller = 1;
140 module_param(power_save_controller, bool, 0644);
141 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
142 #endif /* CONFIG_PM */
143
144 static int align_buffer_size = -1;
145 module_param(align_buffer_size, bint, 0644);
146 MODULE_PARM_DESC(align_buffer_size,
147 "Force buffer and period sizes to be multiple of 128 bytes.");
148
149 #ifdef CONFIG_X86
150 static bool hda_snoop = true;
151 module_param_named(snoop, hda_snoop, bool, 0444);
152 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
153 #else
154 #define hda_snoop true
155 #endif
156
157
158 MODULE_LICENSE("GPL");
159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160 "{Intel, ICH6M},"
161 "{Intel, ICH7},"
162 "{Intel, ESB2},"
163 "{Intel, ICH8},"
164 "{Intel, ICH9},"
165 "{Intel, ICH10},"
166 "{Intel, PCH},"
167 "{Intel, CPT},"
168 "{Intel, PPT},"
169 "{Intel, LPT},"
170 "{Intel, LPT_LP},"
171 "{Intel, WPT_LP},"
172 "{Intel, HPT},"
173 "{Intel, PBG},"
174 "{Intel, SCH},"
175 "{ATI, SB450},"
176 "{ATI, SB600},"
177 "{ATI, RS600},"
178 "{ATI, RS690},"
179 "{ATI, RS780},"
180 "{ATI, R600},"
181 "{ATI, RV630},"
182 "{ATI, RV610},"
183 "{ATI, RV670},"
184 "{ATI, RV635},"
185 "{ATI, RV620},"
186 "{ATI, RV770},"
187 "{VIA, VT8251},"
188 "{VIA, VT8237A},"
189 "{SiS, SIS966},"
190 "{ULI, M5461}}");
191 MODULE_DESCRIPTION("Intel HDA driver");
192
193 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
194 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
195 #define SUPPORT_VGA_SWITCHEROO
196 #endif
197 #endif
198
199
200 /*
201 */
202
203 /* DSP lock helpers */
204 #ifdef CONFIG_SND_HDA_DSP_LOADER
205 #define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
206 #define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
207 #define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
208 #define dsp_is_locked(dev) ((dev)->locked)
209 #else
210 #define dsp_lock_init(dev) do {} while (0)
211 #define dsp_lock(dev) do {} while (0)
212 #define dsp_unlock(dev) do {} while (0)
213 #define dsp_is_locked(dev) 0
214 #endif
215
216 #define CREATE_TRACE_POINTS
217 #include "hda_intel_trace.h"
218
219 /* driver types */
220 enum {
221 AZX_DRIVER_ICH,
222 AZX_DRIVER_PCH,
223 AZX_DRIVER_SCH,
224 AZX_DRIVER_HDMI,
225 AZX_DRIVER_ATI,
226 AZX_DRIVER_ATIHDMI,
227 AZX_DRIVER_ATIHDMI_NS,
228 AZX_DRIVER_VIA,
229 AZX_DRIVER_SIS,
230 AZX_DRIVER_ULI,
231 AZX_DRIVER_NVIDIA,
232 AZX_DRIVER_TERA,
233 AZX_DRIVER_CTX,
234 AZX_DRIVER_CTHDA,
235 AZX_DRIVER_GENERIC,
236 AZX_NUM_DRIVERS, /* keep this as last entry */
237 };
238
239 /* quirks for Intel PCH */
240 #define AZX_DCAPS_INTEL_PCH_NOPM \
241 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
242 AZX_DCAPS_COUNT_LPIB_DELAY)
243
244 #define AZX_DCAPS_INTEL_PCH \
245 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
246
247 #define AZX_DCAPS_INTEL_HASWELL \
248 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
249 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
250 AZX_DCAPS_I915_POWERWELL)
251
252 /* quirks for ATI SB / AMD Hudson */
253 #define AZX_DCAPS_PRESET_ATI_SB \
254 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
255 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
256
257 /* quirks for ATI/AMD HDMI */
258 #define AZX_DCAPS_PRESET_ATI_HDMI \
259 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
260
261 /* quirks for Nvidia */
262 #define AZX_DCAPS_PRESET_NVIDIA \
263 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
264 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
265
266 #define AZX_DCAPS_PRESET_CTHDA \
267 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
268
269 /*
270 * VGA-switcher support
271 */
272 #ifdef SUPPORT_VGA_SWITCHEROO
273 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
274 #else
275 #define use_vga_switcheroo(chip) 0
276 #endif
277
278 static char *driver_short_names[] = {
279 [AZX_DRIVER_ICH] = "HDA Intel",
280 [AZX_DRIVER_PCH] = "HDA Intel PCH",
281 [AZX_DRIVER_SCH] = "HDA Intel MID",
282 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
283 [AZX_DRIVER_ATI] = "HDA ATI SB",
284 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
285 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
286 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
287 [AZX_DRIVER_SIS] = "HDA SIS966",
288 [AZX_DRIVER_ULI] = "HDA ULI M5461",
289 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
290 [AZX_DRIVER_TERA] = "HDA Teradici",
291 [AZX_DRIVER_CTX] = "HDA Creative",
292 [AZX_DRIVER_CTHDA] = "HDA Creative",
293 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
294 };
295
296 /* for pcm support */
297 #define get_azx_dev(substream) (substream->runtime->private_data)
298
299 #ifdef CONFIG_X86
300 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
301 {
302 int pages;
303
304 if (azx_snoop(chip))
305 return;
306 if (!dmab || !dmab->area || !dmab->bytes)
307 return;
308
309 #ifdef CONFIG_SND_DMA_SGBUF
310 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
311 struct snd_sg_buf *sgbuf = dmab->private_data;
312 if (on)
313 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
314 else
315 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
316 return;
317 }
318 #endif
319
320 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
321 if (on)
322 set_memory_wc((unsigned long)dmab->area, pages);
323 else
324 set_memory_wb((unsigned long)dmab->area, pages);
325 }
326
327 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
328 bool on)
329 {
330 __mark_pages_wc(chip, buf, on);
331 }
332 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
333 struct snd_pcm_substream *substream, bool on)
334 {
335 if (azx_dev->wc_marked != on) {
336 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
337 azx_dev->wc_marked = on;
338 }
339 }
340 #else
341 /* NOP for other archs */
342 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
343 bool on)
344 {
345 }
346 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
347 struct snd_pcm_substream *substream, bool on)
348 {
349 }
350 #endif
351
352 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
353 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
354 /*
355 * Interface for HD codec
356 */
357
358 /*
359 * CORB / RIRB interface
360 */
361 static int azx_alloc_cmd_io(struct azx *chip)
362 {
363 int err;
364
365 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
366 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
367 chip->card->dev,
368 PAGE_SIZE, &chip->rb);
369 if (err < 0) {
370 dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n");
371 return err;
372 }
373 mark_pages_wc(chip, &chip->rb, true);
374 return 0;
375 }
376
377 static void azx_init_cmd_io(struct azx *chip)
378 {
379 int timeout;
380
381 spin_lock_irq(&chip->reg_lock);
382 /* CORB set up */
383 chip->corb.addr = chip->rb.addr;
384 chip->corb.buf = (u32 *)chip->rb.area;
385 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
386 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
387
388 /* set the corb size to 256 entries (ULI requires explicitly) */
389 azx_writeb(chip, CORBSIZE, 0x02);
390 /* set the corb write pointer to 0 */
391 azx_writew(chip, CORBWP, 0);
392
393 /* reset the corb hw read pointer */
394 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
395 for (timeout = 1000; timeout > 0; timeout--) {
396 if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST)
397 break;
398 udelay(1);
399 }
400 if (timeout <= 0)
401 dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n",
402 azx_readw(chip, CORBRP));
403
404 azx_writew(chip, CORBRP, 0);
405 for (timeout = 1000; timeout > 0; timeout--) {
406 if (azx_readw(chip, CORBRP) == 0)
407 break;
408 udelay(1);
409 }
410 if (timeout <= 0)
411 dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n",
412 azx_readw(chip, CORBRP));
413
414 /* enable corb dma */
415 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
416
417 /* RIRB set up */
418 chip->rirb.addr = chip->rb.addr + 2048;
419 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
420 chip->rirb.wp = chip->rirb.rp = 0;
421 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
422 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
423 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
424
425 /* set the rirb size to 256 entries (ULI requires explicitly) */
426 azx_writeb(chip, RIRBSIZE, 0x02);
427 /* reset the rirb hw write pointer */
428 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
429 /* set N=1, get RIRB response interrupt for new entry */
430 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
431 azx_writew(chip, RINTCNT, 0xc0);
432 else
433 azx_writew(chip, RINTCNT, 1);
434 /* enable rirb dma and response irq */
435 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
436 spin_unlock_irq(&chip->reg_lock);
437 }
438
439 static void azx_free_cmd_io(struct azx *chip)
440 {
441 spin_lock_irq(&chip->reg_lock);
442 /* disable ringbuffer DMAs */
443 azx_writeb(chip, RIRBCTL, 0);
444 azx_writeb(chip, CORBCTL, 0);
445 spin_unlock_irq(&chip->reg_lock);
446 }
447
448 static unsigned int azx_command_addr(u32 cmd)
449 {
450 unsigned int addr = cmd >> 28;
451
452 if (addr >= AZX_MAX_CODECS) {
453 snd_BUG();
454 addr = 0;
455 }
456
457 return addr;
458 }
459
460 /* send a command */
461 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
462 {
463 struct azx *chip = bus->private_data;
464 unsigned int addr = azx_command_addr(val);
465 unsigned int wp, rp;
466
467 spin_lock_irq(&chip->reg_lock);
468
469 /* add command to corb */
470 wp = azx_readw(chip, CORBWP);
471 if (wp == 0xffff) {
472 /* something wrong, controller likely turned to D3 */
473 spin_unlock_irq(&chip->reg_lock);
474 return -EIO;
475 }
476 wp++;
477 wp %= ICH6_MAX_CORB_ENTRIES;
478
479 rp = azx_readw(chip, CORBRP);
480 if (wp == rp) {
481 /* oops, it's full */
482 spin_unlock_irq(&chip->reg_lock);
483 return -EAGAIN;
484 }
485
486 chip->rirb.cmds[addr]++;
487 chip->corb.buf[wp] = cpu_to_le32(val);
488 azx_writew(chip, CORBWP, wp);
489
490 spin_unlock_irq(&chip->reg_lock);
491
492 return 0;
493 }
494
495 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
496
497 /* retrieve RIRB entry - called from interrupt handler */
498 static void azx_update_rirb(struct azx *chip)
499 {
500 unsigned int rp, wp;
501 unsigned int addr;
502 u32 res, res_ex;
503
504 wp = azx_readw(chip, RIRBWP);
505 if (wp == 0xffff) {
506 /* something wrong, controller likely turned to D3 */
507 return;
508 }
509
510 if (wp == chip->rirb.wp)
511 return;
512 chip->rirb.wp = wp;
513
514 while (chip->rirb.rp != wp) {
515 chip->rirb.rp++;
516 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
517
518 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
519 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
520 res = le32_to_cpu(chip->rirb.buf[rp]);
521 addr = res_ex & 0xf;
522 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
523 dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
524 res, res_ex,
525 chip->rirb.rp, wp);
526 snd_BUG();
527 }
528 else if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
529 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
530 else if (chip->rirb.cmds[addr]) {
531 chip->rirb.res[addr] = res;
532 smp_wmb();
533 chip->rirb.cmds[addr]--;
534 } else if (printk_ratelimit()) {
535 dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
536 res, res_ex,
537 chip->last_cmd[addr]);
538 }
539 }
540 }
541
542 /* receive a response */
543 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
544 unsigned int addr)
545 {
546 struct azx *chip = bus->private_data;
547 unsigned long timeout;
548 unsigned long loopcounter;
549 int do_poll = 0;
550
551 again:
552 timeout = jiffies + msecs_to_jiffies(1000);
553
554 for (loopcounter = 0;; loopcounter++) {
555 if (chip->polling_mode || do_poll) {
556 spin_lock_irq(&chip->reg_lock);
557 azx_update_rirb(chip);
558 spin_unlock_irq(&chip->reg_lock);
559 }
560 if (!chip->rirb.cmds[addr]) {
561 smp_rmb();
562 bus->rirb_error = 0;
563
564 if (!do_poll)
565 chip->poll_count = 0;
566 return chip->rirb.res[addr]; /* the last value */
567 }
568 if (time_after(jiffies, timeout))
569 break;
570 if (bus->needs_damn_long_delay || loopcounter > 3000)
571 msleep(2); /* temporary workaround */
572 else {
573 udelay(10);
574 cond_resched();
575 }
576 }
577
578 if (!bus->no_response_fallback)
579 return -1;
580
581 if (!chip->polling_mode && chip->poll_count < 2) {
582 dev_dbg(chip->card->dev,
583 "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
584 chip->last_cmd[addr]);
585 do_poll = 1;
586 chip->poll_count++;
587 goto again;
588 }
589
590
591 if (!chip->polling_mode) {
592 dev_warn(chip->card->dev,
593 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
594 chip->last_cmd[addr]);
595 chip->polling_mode = 1;
596 goto again;
597 }
598
599 if (chip->msi) {
600 dev_warn(chip->card->dev,
601 "No response from codec, disabling MSI: last cmd=0x%08x\n",
602 chip->last_cmd[addr]);
603 if (chip->ops->disable_msi_reset_irq &&
604 chip->ops->disable_msi_reset_irq(chip) < 0) {
605 bus->rirb_error = 1;
606 return -1;
607 }
608 goto again;
609 }
610
611 if (chip->probing) {
612 /* If this critical timeout happens during the codec probing
613 * phase, this is likely an access to a non-existing codec
614 * slot. Better to return an error and reset the system.
615 */
616 return -1;
617 }
618
619 /* a fatal communication error; need either to reset or to fallback
620 * to the single_cmd mode
621 */
622 bus->rirb_error = 1;
623 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
624 bus->response_reset = 1;
625 return -1; /* give a chance to retry */
626 }
627
628 dev_err(chip->card->dev,
629 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
630 chip->last_cmd[addr]);
631 chip->single_cmd = 1;
632 bus->response_reset = 0;
633 /* release CORB/RIRB */
634 azx_free_cmd_io(chip);
635 /* disable unsolicited responses */
636 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
637 return -1;
638 }
639
640 /*
641 * Use the single immediate command instead of CORB/RIRB for simplicity
642 *
643 * Note: according to Intel, this is not preferred use. The command was
644 * intended for the BIOS only, and may get confused with unsolicited
645 * responses. So, we shouldn't use it for normal operation from the
646 * driver.
647 * I left the codes, however, for debugging/testing purposes.
648 */
649
650 /* receive a response */
651 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
652 {
653 int timeout = 50;
654
655 while (timeout--) {
656 /* check IRV busy bit */
657 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
658 /* reuse rirb.res as the response return value */
659 chip->rirb.res[addr] = azx_readl(chip, IR);
660 return 0;
661 }
662 udelay(1);
663 }
664 if (printk_ratelimit())
665 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
666 azx_readw(chip, IRS));
667 chip->rirb.res[addr] = -1;
668 return -EIO;
669 }
670
671 /* send a command */
672 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
673 {
674 struct azx *chip = bus->private_data;
675 unsigned int addr = azx_command_addr(val);
676 int timeout = 50;
677
678 bus->rirb_error = 0;
679 while (timeout--) {
680 /* check ICB busy bit */
681 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
682 /* Clear IRV valid bit */
683 azx_writew(chip, IRS, azx_readw(chip, IRS) |
684 ICH6_IRS_VALID);
685 azx_writel(chip, IC, val);
686 azx_writew(chip, IRS, azx_readw(chip, IRS) |
687 ICH6_IRS_BUSY);
688 return azx_single_wait_for_response(chip, addr);
689 }
690 udelay(1);
691 }
692 if (printk_ratelimit())
693 dev_dbg(chip->card->dev,
694 "send_cmd timeout: IRS=0x%x, val=0x%x\n",
695 azx_readw(chip, IRS), val);
696 return -EIO;
697 }
698
699 /* receive a response */
700 static unsigned int azx_single_get_response(struct hda_bus *bus,
701 unsigned int addr)
702 {
703 struct azx *chip = bus->private_data;
704 return chip->rirb.res[addr];
705 }
706
707 /*
708 * The below are the main callbacks from hda_codec.
709 *
710 * They are just the skeleton to call sub-callbacks according to the
711 * current setting of chip->single_cmd.
712 */
713
714 /* send a command */
715 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
716 {
717 struct azx *chip = bus->private_data;
718
719 if (chip->disabled)
720 return 0;
721 chip->last_cmd[azx_command_addr(val)] = val;
722 if (chip->single_cmd)
723 return azx_single_send_cmd(bus, val);
724 else
725 return azx_corb_send_cmd(bus, val);
726 }
727
728 /* get a response */
729 static unsigned int azx_get_response(struct hda_bus *bus,
730 unsigned int addr)
731 {
732 struct azx *chip = bus->private_data;
733 if (chip->disabled)
734 return 0;
735 if (chip->single_cmd)
736 return azx_single_get_response(bus, addr);
737 else
738 return azx_rirb_get_response(bus, addr);
739 }
740
741 #ifdef CONFIG_PM
742 static void azx_power_notify(struct hda_bus *bus, bool power_up);
743 #endif
744
745 #ifdef CONFIG_SND_HDA_DSP_LOADER
746 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
747 unsigned int byte_size,
748 struct snd_dma_buffer *bufp);
749 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
750 static void azx_load_dsp_cleanup(struct hda_bus *bus,
751 struct snd_dma_buffer *dmab);
752 #endif
753
754 /* enter link reset */
755 static void azx_enter_link_reset(struct azx *chip)
756 {
757 unsigned long timeout;
758
759 /* reset controller */
760 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
761
762 timeout = jiffies + msecs_to_jiffies(100);
763 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
764 time_before(jiffies, timeout))
765 usleep_range(500, 1000);
766 }
767
768 /* exit link reset */
769 static void azx_exit_link_reset(struct azx *chip)
770 {
771 unsigned long timeout;
772
773 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
774
775 timeout = jiffies + msecs_to_jiffies(100);
776 while (!azx_readb(chip, GCTL) &&
777 time_before(jiffies, timeout))
778 usleep_range(500, 1000);
779 }
780
781 /* reset codec link */
782 static int azx_reset(struct azx *chip, int full_reset)
783 {
784 if (!full_reset)
785 goto __skip;
786
787 /* clear STATESTS */
788 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
789
790 /* reset controller */
791 azx_enter_link_reset(chip);
792
793 /* delay for >= 100us for codec PLL to settle per spec
794 * Rev 0.9 section 5.5.1
795 */
796 usleep_range(500, 1000);
797
798 /* Bring controller out of reset */
799 azx_exit_link_reset(chip);
800
801 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
802 usleep_range(1000, 1200);
803
804 __skip:
805 /* check to see if controller is ready */
806 if (!azx_readb(chip, GCTL)) {
807 dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
808 return -EBUSY;
809 }
810
811 /* Accept unsolicited responses */
812 if (!chip->single_cmd)
813 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
814 ICH6_GCTL_UNSOL);
815
816 /* detect codecs */
817 if (!chip->codec_mask) {
818 chip->codec_mask = azx_readw(chip, STATESTS);
819 dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
820 chip->codec_mask);
821 }
822
823 return 0;
824 }
825
826
827 /*
828 * Lowlevel interface
829 */
830
831 /* enable interrupts */
832 static void azx_int_enable(struct azx *chip)
833 {
834 /* enable controller CIE and GIE */
835 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
836 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
837 }
838
839 /* disable interrupts */
840 static void azx_int_disable(struct azx *chip)
841 {
842 int i;
843
844 /* disable interrupts in stream descriptor */
845 for (i = 0; i < chip->num_streams; i++) {
846 struct azx_dev *azx_dev = &chip->azx_dev[i];
847 azx_sd_writeb(chip, azx_dev, SD_CTL,
848 azx_sd_readb(chip, azx_dev, SD_CTL) &
849 ~SD_INT_MASK);
850 }
851
852 /* disable SIE for all streams */
853 azx_writeb(chip, INTCTL, 0);
854
855 /* disable controller CIE and GIE */
856 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
857 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
858 }
859
860 /* clear interrupts */
861 static void azx_int_clear(struct azx *chip)
862 {
863 int i;
864
865 /* clear stream status */
866 for (i = 0; i < chip->num_streams; i++) {
867 struct azx_dev *azx_dev = &chip->azx_dev[i];
868 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
869 }
870
871 /* clear STATESTS */
872 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
873
874 /* clear rirb status */
875 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
876
877 /* clear int status */
878 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
879 }
880
881 /* start a stream */
882 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
883 {
884 /*
885 * Before stream start, initialize parameter
886 */
887 azx_dev->insufficient = 1;
888
889 /* enable SIE */
890 azx_writel(chip, INTCTL,
891 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
892 /* set DMA start and interrupt mask */
893 azx_sd_writeb(chip, azx_dev, SD_CTL,
894 azx_sd_readb(chip, azx_dev, SD_CTL) |
895 SD_CTL_DMA_START | SD_INT_MASK);
896 }
897
898 /* stop DMA */
899 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
900 {
901 azx_sd_writeb(chip, azx_dev, SD_CTL,
902 azx_sd_readb(chip, azx_dev, SD_CTL) &
903 ~(SD_CTL_DMA_START | SD_INT_MASK));
904 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
905 }
906
907 /* stop a stream */
908 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
909 {
910 azx_stream_clear(chip, azx_dev);
911 /* disable SIE */
912 azx_writel(chip, INTCTL,
913 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
914 }
915
916
917 /*
918 * reset and start the controller registers
919 */
920 static void azx_init_chip(struct azx *chip, int full_reset)
921 {
922 if (chip->initialized)
923 return;
924
925 /* reset controller */
926 azx_reset(chip, full_reset);
927
928 /* initialize interrupts */
929 azx_int_clear(chip);
930 azx_int_enable(chip);
931
932 /* initialize the codec command I/O */
933 if (!chip->single_cmd)
934 azx_init_cmd_io(chip);
935
936 /* program the position buffer */
937 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
938 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
939
940 chip->initialized = 1;
941 }
942
943 /*
944 * initialize the PCI registers
945 */
946 /* update bits in a PCI register byte */
947 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
948 unsigned char mask, unsigned char val)
949 {
950 unsigned char data;
951
952 pci_read_config_byte(pci, reg, &data);
953 data &= ~mask;
954 data |= (val & mask);
955 pci_write_config_byte(pci, reg, data);
956 }
957
958 static void azx_init_pci(struct azx *chip)
959 {
960 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
961 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
962 * Ensuring these bits are 0 clears playback static on some HD Audio
963 * codecs.
964 * The PCI register TCSEL is defined in the Intel manuals.
965 */
966 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
967 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
968 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
969 }
970
971 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
972 * we need to enable snoop.
973 */
974 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
975 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
976 azx_snoop(chip));
977 update_pci_byte(chip->pci,
978 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
979 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
980 }
981
982 /* For NVIDIA HDA, enable snoop */
983 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
984 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
985 azx_snoop(chip));
986 update_pci_byte(chip->pci,
987 NVIDIA_HDA_TRANSREG_ADDR,
988 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
989 update_pci_byte(chip->pci,
990 NVIDIA_HDA_ISTRM_COH,
991 0x01, NVIDIA_HDA_ENABLE_COHBIT);
992 update_pci_byte(chip->pci,
993 NVIDIA_HDA_OSTRM_COH,
994 0x01, NVIDIA_HDA_ENABLE_COHBIT);
995 }
996
997 /* Enable SCH/PCH snoop if needed */
998 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
999 unsigned short snoop;
1000 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1001 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1002 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1003 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1004 if (!azx_snoop(chip))
1005 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1006 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1007 pci_read_config_word(chip->pci,
1008 INTEL_SCH_HDA_DEVC, &snoop);
1009 }
1010 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
1011 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
1012 "Disabled" : "Enabled");
1013 }
1014 }
1015
1016
1017 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1018
1019 /*
1020 * interrupt handler
1021 */
1022 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1023 {
1024 struct azx *chip = dev_id;
1025 struct azx_dev *azx_dev;
1026 u32 status;
1027 u8 sd_status;
1028 int i, ok;
1029
1030 #ifdef CONFIG_PM_RUNTIME
1031 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1032 if (chip->card->dev->power.runtime_status != RPM_ACTIVE)
1033 return IRQ_NONE;
1034 #endif
1035
1036 spin_lock(&chip->reg_lock);
1037
1038 if (chip->disabled) {
1039 spin_unlock(&chip->reg_lock);
1040 return IRQ_NONE;
1041 }
1042
1043 status = azx_readl(chip, INTSTS);
1044 if (status == 0 || status == 0xffffffff) {
1045 spin_unlock(&chip->reg_lock);
1046 return IRQ_NONE;
1047 }
1048
1049 for (i = 0; i < chip->num_streams; i++) {
1050 azx_dev = &chip->azx_dev[i];
1051 if (status & azx_dev->sd_int_sta_mask) {
1052 sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
1053 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
1054 if (!azx_dev->substream || !azx_dev->running ||
1055 !(sd_status & SD_INT_COMPLETE))
1056 continue;
1057 /* check whether this IRQ is really acceptable */
1058 ok = azx_position_ok(chip, azx_dev);
1059 if (ok == 1) {
1060 azx_dev->irq_pending = 0;
1061 spin_unlock(&chip->reg_lock);
1062 snd_pcm_period_elapsed(azx_dev->substream);
1063 spin_lock(&chip->reg_lock);
1064 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1065 /* bogus IRQ, process it later */
1066 azx_dev->irq_pending = 1;
1067 queue_work(chip->bus->workq,
1068 &chip->irq_pending_work);
1069 }
1070 }
1071 }
1072
1073 /* clear rirb int */
1074 status = azx_readb(chip, RIRBSTS);
1075 if (status & RIRB_INT_MASK) {
1076 if (status & RIRB_INT_RESPONSE) {
1077 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1078 udelay(80);
1079 azx_update_rirb(chip);
1080 }
1081 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1082 }
1083
1084 #if 0
1085 /* clear state status int */
1086 if (azx_readw(chip, STATESTS) & 0x04)
1087 azx_writew(chip, STATESTS, 0x04);
1088 #endif
1089 spin_unlock(&chip->reg_lock);
1090
1091 return IRQ_HANDLED;
1092 }
1093
1094
1095 /*
1096 * set up a BDL entry
1097 */
1098 static int setup_bdle(struct azx *chip,
1099 struct snd_dma_buffer *dmab,
1100 struct azx_dev *azx_dev, u32 **bdlp,
1101 int ofs, int size, int with_ioc)
1102 {
1103 u32 *bdl = *bdlp;
1104
1105 while (size > 0) {
1106 dma_addr_t addr;
1107 int chunk;
1108
1109 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1110 return -EINVAL;
1111
1112 addr = snd_sgbuf_get_addr(dmab, ofs);
1113 /* program the address field of the BDL entry */
1114 bdl[0] = cpu_to_le32((u32)addr);
1115 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1116 /* program the size field of the BDL entry */
1117 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1118 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1119 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1120 u32 remain = 0x1000 - (ofs & 0xfff);
1121 if (chunk > remain)
1122 chunk = remain;
1123 }
1124 bdl[2] = cpu_to_le32(chunk);
1125 /* program the IOC to enable interrupt
1126 * only when the whole fragment is processed
1127 */
1128 size -= chunk;
1129 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1130 bdl += 4;
1131 azx_dev->frags++;
1132 ofs += chunk;
1133 }
1134 *bdlp = bdl;
1135 return ofs;
1136 }
1137
1138 /*
1139 * set up BDL entries
1140 */
1141 static int azx_setup_periods(struct azx *chip,
1142 struct snd_pcm_substream *substream,
1143 struct azx_dev *azx_dev)
1144 {
1145 u32 *bdl;
1146 int i, ofs, periods, period_bytes;
1147 int pos_adj = 0;
1148
1149 /* reset BDL address */
1150 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1151 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1152
1153 period_bytes = azx_dev->period_bytes;
1154 periods = azx_dev->bufsize / period_bytes;
1155
1156 /* program the initial BDL entries */
1157 bdl = (u32 *)azx_dev->bdl.area;
1158 ofs = 0;
1159 azx_dev->frags = 0;
1160
1161 if (chip->bdl_pos_adj)
1162 pos_adj = chip->bdl_pos_adj[chip->dev_index];
1163 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1164 struct snd_pcm_runtime *runtime = substream->runtime;
1165 int pos_align = pos_adj;
1166 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1167 if (!pos_adj)
1168 pos_adj = pos_align;
1169 else
1170 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1171 pos_align;
1172 pos_adj = frames_to_bytes(runtime, pos_adj);
1173 if (pos_adj >= period_bytes) {
1174 dev_warn(chip->card->dev,"Too big adjustment %d\n",
1175 pos_adj);
1176 pos_adj = 0;
1177 } else {
1178 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1179 azx_dev,
1180 &bdl, ofs, pos_adj, true);
1181 if (ofs < 0)
1182 goto error;
1183 }
1184 } else
1185 pos_adj = 0;
1186
1187 for (i = 0; i < periods; i++) {
1188 if (i == periods - 1 && pos_adj)
1189 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1190 azx_dev, &bdl, ofs,
1191 period_bytes - pos_adj, 0);
1192 else
1193 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1194 azx_dev, &bdl, ofs,
1195 period_bytes,
1196 !azx_dev->no_period_wakeup);
1197 if (ofs < 0)
1198 goto error;
1199 }
1200 return 0;
1201
1202 error:
1203 dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
1204 azx_dev->bufsize, period_bytes);
1205 return -EINVAL;
1206 }
1207
1208 /* reset stream */
1209 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1210 {
1211 unsigned char val;
1212 int timeout;
1213
1214 azx_stream_clear(chip, azx_dev);
1215
1216 azx_sd_writeb(chip, azx_dev, SD_CTL,
1217 azx_sd_readb(chip, azx_dev, SD_CTL) |
1218 SD_CTL_STREAM_RESET);
1219 udelay(3);
1220 timeout = 300;
1221 while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
1222 SD_CTL_STREAM_RESET) && --timeout)
1223 ;
1224 val &= ~SD_CTL_STREAM_RESET;
1225 azx_sd_writeb(chip, azx_dev, SD_CTL, val);
1226 udelay(3);
1227
1228 timeout = 300;
1229 /* waiting for hardware to report that the stream is out of reset */
1230 while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
1231 SD_CTL_STREAM_RESET) && --timeout)
1232 ;
1233
1234 /* reset first position - may not be synced with hw at this time */
1235 *azx_dev->posbuf = 0;
1236 }
1237
1238 /*
1239 * set up the SD for streaming
1240 */
1241 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1242 {
1243 unsigned int val;
1244 /* make sure the run bit is zero for SD */
1245 azx_stream_clear(chip, azx_dev);
1246 /* program the stream_tag */
1247 val = azx_sd_readl(chip, azx_dev, SD_CTL);
1248 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1249 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1250 if (!azx_snoop(chip))
1251 val |= SD_CTL_TRAFFIC_PRIO;
1252 azx_sd_writel(chip, azx_dev, SD_CTL, val);
1253
1254 /* program the length of samples in cyclic buffer */
1255 azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize);
1256
1257 /* program the stream format */
1258 /* this value needs to be the same as the one programmed */
1259 azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val);
1260
1261 /* program the stream LVI (last valid index) of the BDL */
1262 azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1);
1263
1264 /* program the BDL address */
1265 /* lower BDL address */
1266 azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1267 /* upper BDL address */
1268 azx_sd_writel(chip, azx_dev, SD_BDLPU,
1269 upper_32_bits(azx_dev->bdl.addr));
1270
1271 /* enable the position buffer */
1272 if (chip->position_fix[0] != POS_FIX_LPIB ||
1273 chip->position_fix[1] != POS_FIX_LPIB) {
1274 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1275 azx_writel(chip, DPLBASE,
1276 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1277 }
1278
1279 /* set the interrupt enable bits in the descriptor control register */
1280 azx_sd_writel(chip, azx_dev, SD_CTL,
1281 azx_sd_readl(chip, azx_dev, SD_CTL) | SD_INT_MASK);
1282
1283 return 0;
1284 }
1285
1286 /*
1287 * Probe the given codec address
1288 */
1289 static int probe_codec(struct azx *chip, int addr)
1290 {
1291 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1292 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1293 unsigned int res;
1294
1295 mutex_lock(&chip->bus->cmd_mutex);
1296 chip->probing = 1;
1297 azx_send_cmd(chip->bus, cmd);
1298 res = azx_get_response(chip->bus, addr);
1299 chip->probing = 0;
1300 mutex_unlock(&chip->bus->cmd_mutex);
1301 if (res == -1)
1302 return -EIO;
1303 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1304 return 0;
1305 }
1306
1307 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1308 struct hda_pcm *cpcm);
1309 static void azx_stop_chip(struct azx *chip);
1310
1311 static void azx_bus_reset(struct hda_bus *bus)
1312 {
1313 struct azx *chip = bus->private_data;
1314
1315 bus->in_reset = 1;
1316 azx_stop_chip(chip);
1317 azx_init_chip(chip, 1);
1318 #ifdef CONFIG_PM
1319 if (chip->initialized) {
1320 struct azx_pcm *p;
1321 list_for_each_entry(p, &chip->pcm_list, list)
1322 snd_pcm_suspend_all(p->pcm);
1323 snd_hda_suspend(chip->bus);
1324 snd_hda_resume(chip->bus);
1325 }
1326 #endif
1327 bus->in_reset = 0;
1328 }
1329
1330 static int get_jackpoll_interval(struct azx *chip)
1331 {
1332 int i = jackpoll_ms[chip->dev_index];
1333 unsigned int j;
1334 if (i == 0)
1335 return 0;
1336 if (i < 50 || i > 60000)
1337 j = 0;
1338 else
1339 j = msecs_to_jiffies(i);
1340 if (j == 0)
1341 dev_warn(chip->card->dev,
1342 "jackpoll_ms value out of range: %d\n", i);
1343 return j;
1344 }
1345
1346 /*
1347 * Codec initialization
1348 */
1349
1350 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1351 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1352 [AZX_DRIVER_NVIDIA] = 8,
1353 [AZX_DRIVER_TERA] = 1,
1354 };
1355
1356 static int azx_codec_create(struct azx *chip, const char *model)
1357 {
1358 struct hda_bus_template bus_temp;
1359 int c, codecs, err;
1360 int max_slots;
1361
1362 memset(&bus_temp, 0, sizeof(bus_temp));
1363 bus_temp.private_data = chip;
1364 bus_temp.modelname = model;
1365 bus_temp.pci = chip->pci;
1366 bus_temp.ops.command = azx_send_cmd;
1367 bus_temp.ops.get_response = azx_get_response;
1368 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1369 bus_temp.ops.bus_reset = azx_bus_reset;
1370 #ifdef CONFIG_PM
1371 bus_temp.power_save = &power_save;
1372 bus_temp.ops.pm_notify = azx_power_notify;
1373 #endif
1374 #ifdef CONFIG_SND_HDA_DSP_LOADER
1375 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1376 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1377 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1378 #endif
1379
1380 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1381 if (err < 0)
1382 return err;
1383
1384 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1385 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1386 chip->bus->needs_damn_long_delay = 1;
1387 }
1388
1389 codecs = 0;
1390 max_slots = azx_max_codecs[chip->driver_type];
1391 if (!max_slots)
1392 max_slots = AZX_DEFAULT_CODECS;
1393
1394 /* First try to probe all given codec slots */
1395 for (c = 0; c < max_slots; c++) {
1396 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1397 if (probe_codec(chip, c) < 0) {
1398 /* Some BIOSen give you wrong codec addresses
1399 * that don't exist
1400 */
1401 dev_warn(chip->card->dev,
1402 "Codec #%d probe error; disabling it...\n", c);
1403 chip->codec_mask &= ~(1 << c);
1404 /* More badly, accessing to a non-existing
1405 * codec often screws up the controller chip,
1406 * and disturbs the further communications.
1407 * Thus if an error occurs during probing,
1408 * better to reset the controller chip to
1409 * get back to the sanity state.
1410 */
1411 azx_stop_chip(chip);
1412 azx_init_chip(chip, 1);
1413 }
1414 }
1415 }
1416
1417 /* AMD chipsets often cause the communication stalls upon certain
1418 * sequence like the pin-detection. It seems that forcing the synced
1419 * access works around the stall. Grrr...
1420 */
1421 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1422 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1423 chip->bus->sync_write = 1;
1424 chip->bus->allow_bus_reset = 1;
1425 }
1426
1427 /* Then create codec instances */
1428 for (c = 0; c < max_slots; c++) {
1429 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1430 struct hda_codec *codec;
1431 err = snd_hda_codec_new(chip->bus, c, &codec);
1432 if (err < 0)
1433 continue;
1434 codec->jackpoll_interval = get_jackpoll_interval(chip);
1435 codec->beep_mode = chip->beep_mode;
1436 codecs++;
1437 }
1438 }
1439 if (!codecs) {
1440 dev_err(chip->card->dev, "no codecs initialized\n");
1441 return -ENXIO;
1442 }
1443 return 0;
1444 }
1445
1446 /* configure each codec instance */
1447 static int azx_codec_configure(struct azx *chip)
1448 {
1449 struct hda_codec *codec;
1450 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1451 snd_hda_codec_configure(codec);
1452 }
1453 return 0;
1454 }
1455
1456
1457 /*
1458 * PCM support
1459 */
1460
1461 /* assign a stream for the PCM */
1462 static inline struct azx_dev *
1463 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1464 {
1465 int dev, i, nums;
1466 struct azx_dev *res = NULL;
1467 /* make a non-zero unique key for the substream */
1468 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1469 (substream->stream + 1);
1470
1471 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1472 dev = chip->playback_index_offset;
1473 nums = chip->playback_streams;
1474 } else {
1475 dev = chip->capture_index_offset;
1476 nums = chip->capture_streams;
1477 }
1478 for (i = 0; i < nums; i++, dev++) {
1479 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1480 dsp_lock(azx_dev);
1481 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1482 res = azx_dev;
1483 if (res->assigned_key == key) {
1484 res->opened = 1;
1485 res->assigned_key = key;
1486 dsp_unlock(azx_dev);
1487 return azx_dev;
1488 }
1489 }
1490 dsp_unlock(azx_dev);
1491 }
1492 if (res) {
1493 dsp_lock(res);
1494 res->opened = 1;
1495 res->assigned_key = key;
1496 dsp_unlock(res);
1497 }
1498 return res;
1499 }
1500
1501 /* release the assigned stream */
1502 static inline void azx_release_device(struct azx_dev *azx_dev)
1503 {
1504 azx_dev->opened = 0;
1505 }
1506
1507 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1508 {
1509 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1510 struct snd_pcm_substream *substream = azx_dev->substream;
1511 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1512 struct azx *chip = apcm->chip;
1513
1514 return azx_readl(chip, WALLCLK);
1515 }
1516
1517 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1518 bool force, cycle_t last)
1519 {
1520 struct azx_dev *azx_dev = get_azx_dev(substream);
1521 struct timecounter *tc = &azx_dev->azx_tc;
1522 struct cyclecounter *cc = &azx_dev->azx_cc;
1523 u64 nsec;
1524
1525 cc->read = azx_cc_read;
1526 cc->mask = CLOCKSOURCE_MASK(32);
1527
1528 /*
1529 * Converting from 24 MHz to ns means applying a 125/3 factor.
1530 * To avoid any saturation issues in intermediate operations,
1531 * the 125 factor is applied first. The division is applied
1532 * last after reading the timecounter value.
1533 * Applying the 1/3 factor as part of the multiplication
1534 * requires at least 20 bits for a decent precision, however
1535 * overflows occur after about 4 hours or less, not a option.
1536 */
1537
1538 cc->mult = 125; /* saturation after 195 years */
1539 cc->shift = 0;
1540
1541 nsec = 0; /* audio time is elapsed time since trigger */
1542 timecounter_init(tc, cc, nsec);
1543 if (force)
1544 /*
1545 * force timecounter to use predefined value,
1546 * used for synchronized starts
1547 */
1548 tc->cycle_last = last;
1549 }
1550
1551 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
1552 u64 nsec)
1553 {
1554 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1555 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1556 u64 codec_frames, codec_nsecs;
1557
1558 if (!hinfo->ops.get_delay)
1559 return nsec;
1560
1561 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1562 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1563 substream->runtime->rate);
1564
1565 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1566 return nsec + codec_nsecs;
1567
1568 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1569 }
1570
1571 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1572 struct timespec *ts)
1573 {
1574 struct azx_dev *azx_dev = get_azx_dev(substream);
1575 u64 nsec;
1576
1577 nsec = timecounter_read(&azx_dev->azx_tc);
1578 nsec = div_u64(nsec, 3); /* can be optimized */
1579 nsec = azx_adjust_codec_delay(substream, nsec);
1580
1581 *ts = ns_to_timespec(nsec);
1582
1583 return 0;
1584 }
1585
1586 static struct snd_pcm_hardware azx_pcm_hw = {
1587 .info = (SNDRV_PCM_INFO_MMAP |
1588 SNDRV_PCM_INFO_INTERLEAVED |
1589 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1590 SNDRV_PCM_INFO_MMAP_VALID |
1591 /* No full-resume yet implemented */
1592 /* SNDRV_PCM_INFO_RESUME |*/
1593 SNDRV_PCM_INFO_PAUSE |
1594 SNDRV_PCM_INFO_SYNC_START |
1595 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1596 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1597 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1598 .rates = SNDRV_PCM_RATE_48000,
1599 .rate_min = 48000,
1600 .rate_max = 48000,
1601 .channels_min = 2,
1602 .channels_max = 2,
1603 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1604 .period_bytes_min = 128,
1605 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1606 .periods_min = 2,
1607 .periods_max = AZX_MAX_FRAG,
1608 .fifo_size = 0,
1609 };
1610
1611 static int azx_pcm_open(struct snd_pcm_substream *substream)
1612 {
1613 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1614 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1615 struct azx *chip = apcm->chip;
1616 struct azx_dev *azx_dev;
1617 struct snd_pcm_runtime *runtime = substream->runtime;
1618 unsigned long flags;
1619 int err;
1620 int buff_step;
1621
1622 mutex_lock(&chip->open_mutex);
1623 azx_dev = azx_assign_device(chip, substream);
1624 if (azx_dev == NULL) {
1625 mutex_unlock(&chip->open_mutex);
1626 return -EBUSY;
1627 }
1628 runtime->hw = azx_pcm_hw;
1629 runtime->hw.channels_min = hinfo->channels_min;
1630 runtime->hw.channels_max = hinfo->channels_max;
1631 runtime->hw.formats = hinfo->formats;
1632 runtime->hw.rates = hinfo->rates;
1633 snd_pcm_limit_hw_rates(runtime);
1634 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1635
1636 /* avoid wrap-around with wall-clock */
1637 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1638 20,
1639 178000000);
1640
1641 if (chip->align_buffer_size)
1642 /* constrain buffer sizes to be multiple of 128
1643 bytes. This is more efficient in terms of memory
1644 access but isn't required by the HDA spec and
1645 prevents users from specifying exact period/buffer
1646 sizes. For example for 44.1kHz, a period size set
1647 to 20ms will be rounded to 19.59ms. */
1648 buff_step = 128;
1649 else
1650 /* Don't enforce steps on buffer sizes, still need to
1651 be multiple of 4 bytes (HDA spec). Tested on Intel
1652 HDA controllers, may not work on all devices where
1653 option needs to be disabled */
1654 buff_step = 4;
1655
1656 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1657 buff_step);
1658 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1659 buff_step);
1660 snd_hda_power_up_d3wait(apcm->codec);
1661 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1662 if (err < 0) {
1663 azx_release_device(azx_dev);
1664 snd_hda_power_down(apcm->codec);
1665 mutex_unlock(&chip->open_mutex);
1666 return err;
1667 }
1668 snd_pcm_limit_hw_rates(runtime);
1669 /* sanity check */
1670 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1671 snd_BUG_ON(!runtime->hw.channels_max) ||
1672 snd_BUG_ON(!runtime->hw.formats) ||
1673 snd_BUG_ON(!runtime->hw.rates)) {
1674 azx_release_device(azx_dev);
1675 hinfo->ops.close(hinfo, apcm->codec, substream);
1676 snd_hda_power_down(apcm->codec);
1677 mutex_unlock(&chip->open_mutex);
1678 return -EINVAL;
1679 }
1680
1681 /* disable WALLCLOCK timestamps for capture streams
1682 until we figure out how to handle digital inputs */
1683 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1684 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1685
1686 spin_lock_irqsave(&chip->reg_lock, flags);
1687 azx_dev->substream = substream;
1688 azx_dev->running = 0;
1689 spin_unlock_irqrestore(&chip->reg_lock, flags);
1690
1691 runtime->private_data = azx_dev;
1692 snd_pcm_set_sync(substream);
1693 mutex_unlock(&chip->open_mutex);
1694 return 0;
1695 }
1696
1697 static int azx_pcm_close(struct snd_pcm_substream *substream)
1698 {
1699 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1700 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1701 struct azx *chip = apcm->chip;
1702 struct azx_dev *azx_dev = get_azx_dev(substream);
1703 unsigned long flags;
1704
1705 mutex_lock(&chip->open_mutex);
1706 spin_lock_irqsave(&chip->reg_lock, flags);
1707 azx_dev->substream = NULL;
1708 azx_dev->running = 0;
1709 spin_unlock_irqrestore(&chip->reg_lock, flags);
1710 azx_release_device(azx_dev);
1711 hinfo->ops.close(hinfo, apcm->codec, substream);
1712 snd_hda_power_down(apcm->codec);
1713 mutex_unlock(&chip->open_mutex);
1714 return 0;
1715 }
1716
1717 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1718 struct snd_pcm_hw_params *hw_params)
1719 {
1720 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1721 struct azx *chip = apcm->chip;
1722 struct azx_dev *azx_dev = get_azx_dev(substream);
1723 int ret;
1724
1725 dsp_lock(azx_dev);
1726 if (dsp_is_locked(azx_dev)) {
1727 ret = -EBUSY;
1728 goto unlock;
1729 }
1730
1731 mark_runtime_wc(chip, azx_dev, substream, false);
1732 azx_dev->bufsize = 0;
1733 azx_dev->period_bytes = 0;
1734 azx_dev->format_val = 0;
1735 ret = snd_pcm_lib_malloc_pages(substream,
1736 params_buffer_bytes(hw_params));
1737 if (ret < 0)
1738 goto unlock;
1739 mark_runtime_wc(chip, azx_dev, substream, true);
1740 unlock:
1741 dsp_unlock(azx_dev);
1742 return ret;
1743 }
1744
1745 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1746 {
1747 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1748 struct azx_dev *azx_dev = get_azx_dev(substream);
1749 struct azx *chip = apcm->chip;
1750 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1751
1752 /* reset BDL address */
1753 dsp_lock(azx_dev);
1754 if (!dsp_is_locked(azx_dev)) {
1755 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1756 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1757 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
1758 azx_dev->bufsize = 0;
1759 azx_dev->period_bytes = 0;
1760 azx_dev->format_val = 0;
1761 }
1762
1763 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1764
1765 mark_runtime_wc(chip, azx_dev, substream, false);
1766 azx_dev->prepared = 0;
1767 dsp_unlock(azx_dev);
1768 return snd_pcm_lib_free_pages(substream);
1769 }
1770
1771 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1772 {
1773 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1774 struct azx *chip = apcm->chip;
1775 struct azx_dev *azx_dev = get_azx_dev(substream);
1776 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1777 struct snd_pcm_runtime *runtime = substream->runtime;
1778 unsigned int bufsize, period_bytes, format_val, stream_tag;
1779 int err;
1780 struct hda_spdif_out *spdif =
1781 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1782 unsigned short ctls = spdif ? spdif->ctls : 0;
1783
1784 dsp_lock(azx_dev);
1785 if (dsp_is_locked(azx_dev)) {
1786 err = -EBUSY;
1787 goto unlock;
1788 }
1789
1790 azx_stream_reset(chip, azx_dev);
1791 format_val = snd_hda_calc_stream_format(runtime->rate,
1792 runtime->channels,
1793 runtime->format,
1794 hinfo->maxbps,
1795 ctls);
1796 if (!format_val) {
1797 dev_err(chip->card->dev,
1798 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1799 runtime->rate, runtime->channels, runtime->format);
1800 err = -EINVAL;
1801 goto unlock;
1802 }
1803
1804 bufsize = snd_pcm_lib_buffer_bytes(substream);
1805 period_bytes = snd_pcm_lib_period_bytes(substream);
1806
1807 dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1808 bufsize, format_val);
1809
1810 if (bufsize != azx_dev->bufsize ||
1811 period_bytes != azx_dev->period_bytes ||
1812 format_val != azx_dev->format_val ||
1813 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
1814 azx_dev->bufsize = bufsize;
1815 azx_dev->period_bytes = period_bytes;
1816 azx_dev->format_val = format_val;
1817 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
1818 err = azx_setup_periods(chip, substream, azx_dev);
1819 if (err < 0)
1820 goto unlock;
1821 }
1822
1823 /* when LPIB delay correction gives a small negative value,
1824 * we ignore it; currently set the threshold statically to
1825 * 64 frames
1826 */
1827 if (runtime->period_size > 64)
1828 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
1829 else
1830 azx_dev->delay_negative_threshold = 0;
1831
1832 /* wallclk has 24Mhz clock source */
1833 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1834 runtime->rate) * 1000);
1835 azx_setup_controller(chip, azx_dev);
1836 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1837 azx_dev->fifo_size =
1838 azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
1839 else
1840 azx_dev->fifo_size = 0;
1841
1842 stream_tag = azx_dev->stream_tag;
1843 /* CA-IBG chips need the playback stream starting from 1 */
1844 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1845 stream_tag > chip->capture_streams)
1846 stream_tag -= chip->capture_streams;
1847 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1848 azx_dev->format_val, substream);
1849
1850 unlock:
1851 if (!err)
1852 azx_dev->prepared = 1;
1853 dsp_unlock(azx_dev);
1854 return err;
1855 }
1856
1857 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1858 {
1859 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1860 struct azx *chip = apcm->chip;
1861 struct azx_dev *azx_dev;
1862 struct snd_pcm_substream *s;
1863 int rstart = 0, start, nsync = 0, sbits = 0;
1864 int nwait, timeout;
1865
1866 azx_dev = get_azx_dev(substream);
1867 trace_azx_pcm_trigger(chip, azx_dev, cmd);
1868
1869 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
1870 return -EPIPE;
1871
1872 switch (cmd) {
1873 case SNDRV_PCM_TRIGGER_START:
1874 rstart = 1;
1875 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1876 case SNDRV_PCM_TRIGGER_RESUME:
1877 start = 1;
1878 break;
1879 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1880 case SNDRV_PCM_TRIGGER_SUSPEND:
1881 case SNDRV_PCM_TRIGGER_STOP:
1882 start = 0;
1883 break;
1884 default:
1885 return -EINVAL;
1886 }
1887
1888 snd_pcm_group_for_each_entry(s, substream) {
1889 if (s->pcm->card != substream->pcm->card)
1890 continue;
1891 azx_dev = get_azx_dev(s);
1892 sbits |= 1 << azx_dev->index;
1893 nsync++;
1894 snd_pcm_trigger_done(s, substream);
1895 }
1896
1897 spin_lock(&chip->reg_lock);
1898
1899 /* first, set SYNC bits of corresponding streams */
1900 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1901 azx_writel(chip, OLD_SSYNC,
1902 azx_readl(chip, OLD_SSYNC) | sbits);
1903 else
1904 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1905
1906 snd_pcm_group_for_each_entry(s, substream) {
1907 if (s->pcm->card != substream->pcm->card)
1908 continue;
1909 azx_dev = get_azx_dev(s);
1910 if (start) {
1911 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1912 if (!rstart)
1913 azx_dev->start_wallclk -=
1914 azx_dev->period_wallclk;
1915 azx_stream_start(chip, azx_dev);
1916 } else {
1917 azx_stream_stop(chip, azx_dev);
1918 }
1919 azx_dev->running = start;
1920 }
1921 spin_unlock(&chip->reg_lock);
1922 if (start) {
1923 /* wait until all FIFOs get ready */
1924 for (timeout = 5000; timeout; timeout--) {
1925 nwait = 0;
1926 snd_pcm_group_for_each_entry(s, substream) {
1927 if (s->pcm->card != substream->pcm->card)
1928 continue;
1929 azx_dev = get_azx_dev(s);
1930 if (!(azx_sd_readb(chip, azx_dev, SD_STS) &
1931 SD_STS_FIFO_READY))
1932 nwait++;
1933 }
1934 if (!nwait)
1935 break;
1936 cpu_relax();
1937 }
1938 } else {
1939 /* wait until all RUN bits are cleared */
1940 for (timeout = 5000; timeout; timeout--) {
1941 nwait = 0;
1942 snd_pcm_group_for_each_entry(s, substream) {
1943 if (s->pcm->card != substream->pcm->card)
1944 continue;
1945 azx_dev = get_azx_dev(s);
1946 if (azx_sd_readb(chip, azx_dev, SD_CTL) &
1947 SD_CTL_DMA_START)
1948 nwait++;
1949 }
1950 if (!nwait)
1951 break;
1952 cpu_relax();
1953 }
1954 }
1955 spin_lock(&chip->reg_lock);
1956 /* reset SYNC bits */
1957 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1958 azx_writel(chip, OLD_SSYNC,
1959 azx_readl(chip, OLD_SSYNC) & ~sbits);
1960 else
1961 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1962 if (start) {
1963 azx_timecounter_init(substream, 0, 0);
1964 if (nsync > 1) {
1965 cycle_t cycle_last;
1966
1967 /* same start cycle for master and group */
1968 azx_dev = get_azx_dev(substream);
1969 cycle_last = azx_dev->azx_tc.cycle_last;
1970
1971 snd_pcm_group_for_each_entry(s, substream) {
1972 if (s->pcm->card != substream->pcm->card)
1973 continue;
1974 azx_timecounter_init(s, 1, cycle_last);
1975 }
1976 }
1977 }
1978 spin_unlock(&chip->reg_lock);
1979 return 0;
1980 }
1981
1982 /* get the current DMA position with correction on VIA chips */
1983 static unsigned int azx_via_get_position(struct azx *chip,
1984 struct azx_dev *azx_dev)
1985 {
1986 unsigned int link_pos, mini_pos, bound_pos;
1987 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1988 unsigned int fifo_size;
1989
1990 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
1991 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1992 /* Playback, no problem using link position */
1993 return link_pos;
1994 }
1995
1996 /* Capture */
1997 /* For new chipset,
1998 * use mod to get the DMA position just like old chipset
1999 */
2000 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2001 mod_dma_pos %= azx_dev->period_bytes;
2002
2003 /* azx_dev->fifo_size can't get FIFO size of in stream.
2004 * Get from base address + offset.
2005 */
2006 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2007
2008 if (azx_dev->insufficient) {
2009 /* Link position never gather than FIFO size */
2010 if (link_pos <= fifo_size)
2011 return 0;
2012
2013 azx_dev->insufficient = 0;
2014 }
2015
2016 if (link_pos <= fifo_size)
2017 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2018 else
2019 mini_pos = link_pos - fifo_size;
2020
2021 /* Find nearest previous boudary */
2022 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2023 mod_link_pos = link_pos % azx_dev->period_bytes;
2024 if (mod_link_pos >= fifo_size)
2025 bound_pos = link_pos - mod_link_pos;
2026 else if (mod_dma_pos >= mod_mini_pos)
2027 bound_pos = mini_pos - mod_mini_pos;
2028 else {
2029 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2030 if (bound_pos >= azx_dev->bufsize)
2031 bound_pos = 0;
2032 }
2033
2034 /* Calculate real DMA position we want */
2035 return bound_pos + mod_dma_pos;
2036 }
2037
2038 static unsigned int azx_get_position(struct azx *chip,
2039 struct azx_dev *azx_dev,
2040 bool with_check)
2041 {
2042 struct snd_pcm_substream *substream = azx_dev->substream;
2043 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2044 unsigned int pos;
2045 int stream = substream->stream;
2046 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2047 int delay = 0;
2048
2049 switch (chip->position_fix[stream]) {
2050 case POS_FIX_LPIB:
2051 /* read LPIB */
2052 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
2053 break;
2054 case POS_FIX_VIACOMBO:
2055 pos = azx_via_get_position(chip, azx_dev);
2056 break;
2057 default:
2058 /* use the position buffer */
2059 pos = le32_to_cpu(*azx_dev->posbuf);
2060 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2061 if (!pos || pos == (u32)-1) {
2062 dev_info(chip->card->dev,
2063 "Invalid position buffer, using LPIB read method instead.\n");
2064 chip->position_fix[stream] = POS_FIX_LPIB;
2065 pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
2066 } else
2067 chip->position_fix[stream] = POS_FIX_POSBUF;
2068 }
2069 break;
2070 }
2071
2072 if (pos >= azx_dev->bufsize)
2073 pos = 0;
2074
2075 /* calculate runtime delay from LPIB */
2076 if (substream->runtime &&
2077 chip->position_fix[stream] == POS_FIX_POSBUF &&
2078 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2079 unsigned int lpib_pos = azx_sd_readl(chip, azx_dev, SD_LPIB);
2080 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2081 delay = pos - lpib_pos;
2082 else
2083 delay = lpib_pos - pos;
2084 if (delay < 0) {
2085 if (delay >= azx_dev->delay_negative_threshold)
2086 delay = 0;
2087 else
2088 delay += azx_dev->bufsize;
2089 }
2090 if (delay >= azx_dev->period_bytes) {
2091 dev_info(chip->card->dev,
2092 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
2093 delay, azx_dev->period_bytes);
2094 delay = 0;
2095 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2096 }
2097 delay = bytes_to_frames(substream->runtime, delay);
2098 }
2099
2100 if (substream->runtime) {
2101 if (hinfo->ops.get_delay)
2102 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2103 substream);
2104 substream->runtime->delay = delay;
2105 }
2106
2107 trace_azx_get_position(chip, azx_dev, pos, delay);
2108 return pos;
2109 }
2110
2111 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2112 {
2113 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2114 struct azx *chip = apcm->chip;
2115 struct azx_dev *azx_dev = get_azx_dev(substream);
2116 return bytes_to_frames(substream->runtime,
2117 azx_get_position(chip, azx_dev, false));
2118 }
2119
2120 /*
2121 * Check whether the current DMA position is acceptable for updating
2122 * periods. Returns non-zero if it's OK.
2123 *
2124 * Many HD-audio controllers appear pretty inaccurate about
2125 * the update-IRQ timing. The IRQ is issued before actually the
2126 * data is processed. So, we need to process it afterwords in a
2127 * workqueue.
2128 */
2129 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2130 {
2131 u32 wallclk;
2132 unsigned int pos;
2133
2134 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2135 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2136 return -1; /* bogus (too early) interrupt */
2137
2138 pos = azx_get_position(chip, azx_dev, true);
2139
2140 if (WARN_ONCE(!azx_dev->period_bytes,
2141 "hda-intel: zero azx_dev->period_bytes"))
2142 return -1; /* this shouldn't happen! */
2143 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2144 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2145 /* NG - it's below the first next period boundary */
2146 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
2147 azx_dev->start_wallclk += wallclk;
2148 return 1; /* OK, it's fine */
2149 }
2150
2151 /*
2152 * The work for pending PCM period updates.
2153 */
2154 static void azx_irq_pending_work(struct work_struct *work)
2155 {
2156 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2157 int i, pending, ok;
2158
2159 if (!chip->irq_pending_warned) {
2160 dev_info(chip->card->dev,
2161 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
2162 chip->card->number);
2163 chip->irq_pending_warned = 1;
2164 }
2165
2166 for (;;) {
2167 pending = 0;
2168 spin_lock_irq(&chip->reg_lock);
2169 for (i = 0; i < chip->num_streams; i++) {
2170 struct azx_dev *azx_dev = &chip->azx_dev[i];
2171 if (!azx_dev->irq_pending ||
2172 !azx_dev->substream ||
2173 !azx_dev->running)
2174 continue;
2175 ok = azx_position_ok(chip, azx_dev);
2176 if (ok > 0) {
2177 azx_dev->irq_pending = 0;
2178 spin_unlock(&chip->reg_lock);
2179 snd_pcm_period_elapsed(azx_dev->substream);
2180 spin_lock(&chip->reg_lock);
2181 } else if (ok < 0) {
2182 pending = 0; /* too early */
2183 } else
2184 pending++;
2185 }
2186 spin_unlock_irq(&chip->reg_lock);
2187 if (!pending)
2188 return;
2189 msleep(1);
2190 }
2191 }
2192
2193 /* clear irq_pending flags and assure no on-going workq */
2194 static void azx_clear_irq_pending(struct azx *chip)
2195 {
2196 int i;
2197
2198 spin_lock_irq(&chip->reg_lock);
2199 for (i = 0; i < chip->num_streams; i++)
2200 chip->azx_dev[i].irq_pending = 0;
2201 spin_unlock_irq(&chip->reg_lock);
2202 }
2203
2204 #ifdef CONFIG_X86
2205 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2206 struct vm_area_struct *area)
2207 {
2208 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2209 struct azx *chip = apcm->chip;
2210 if (!azx_snoop(chip))
2211 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2212 return snd_pcm_lib_default_mmap(substream, area);
2213 }
2214 #else
2215 #define azx_pcm_mmap NULL
2216 #endif
2217
2218 static struct snd_pcm_ops azx_pcm_ops = {
2219 .open = azx_pcm_open,
2220 .close = azx_pcm_close,
2221 .ioctl = snd_pcm_lib_ioctl,
2222 .hw_params = azx_pcm_hw_params,
2223 .hw_free = azx_pcm_hw_free,
2224 .prepare = azx_pcm_prepare,
2225 .trigger = azx_pcm_trigger,
2226 .pointer = azx_pcm_pointer,
2227 .wall_clock = azx_get_wallclock_tstamp,
2228 .mmap = azx_pcm_mmap,
2229 .page = snd_pcm_sgbuf_ops_page,
2230 };
2231
2232 static void azx_pcm_free(struct snd_pcm *pcm)
2233 {
2234 struct azx_pcm *apcm = pcm->private_data;
2235 if (apcm) {
2236 list_del(&apcm->list);
2237 kfree(apcm);
2238 }
2239 }
2240
2241 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2242
2243 static int
2244 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2245 struct hda_pcm *cpcm)
2246 {
2247 struct azx *chip = bus->private_data;
2248 struct snd_pcm *pcm;
2249 struct azx_pcm *apcm;
2250 int pcm_dev = cpcm->device;
2251 unsigned int size;
2252 int s, err;
2253
2254 list_for_each_entry(apcm, &chip->pcm_list, list) {
2255 if (apcm->pcm->device == pcm_dev) {
2256 dev_err(chip->card->dev, "PCM %d already exists\n",
2257 pcm_dev);
2258 return -EBUSY;
2259 }
2260 }
2261 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2262 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2263 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2264 &pcm);
2265 if (err < 0)
2266 return err;
2267 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2268 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2269 if (apcm == NULL)
2270 return -ENOMEM;
2271 apcm->chip = chip;
2272 apcm->pcm = pcm;
2273 apcm->codec = codec;
2274 pcm->private_data = apcm;
2275 pcm->private_free = azx_pcm_free;
2276 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2277 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2278 list_add_tail(&apcm->list, &chip->pcm_list);
2279 cpcm->pcm = pcm;
2280 for (s = 0; s < 2; s++) {
2281 apcm->hinfo[s] = &cpcm->stream[s];
2282 if (cpcm->stream[s].substreams)
2283 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2284 }
2285 /* buffer pre-allocation */
2286 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2287 if (size > MAX_PREALLOC_SIZE)
2288 size = MAX_PREALLOC_SIZE;
2289 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2290 chip->card->dev,
2291 size, MAX_PREALLOC_SIZE);
2292 /* link to codec */
2293 pcm->dev = &codec->dev;
2294 return 0;
2295 }
2296
2297 /*
2298 * mixer creation - all stuff is implemented in hda module
2299 */
2300 static int azx_mixer_create(struct azx *chip)
2301 {
2302 return snd_hda_build_controls(chip->bus);
2303 }
2304
2305
2306 /*
2307 * initialize SD streams
2308 */
2309 static int azx_init_stream(struct azx *chip)
2310 {
2311 int i;
2312
2313 /* initialize each stream (aka device)
2314 * assign the starting bdl address to each stream (device)
2315 * and initialize
2316 */
2317 for (i = 0; i < chip->num_streams; i++) {
2318 struct azx_dev *azx_dev = &chip->azx_dev[i];
2319 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2320 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2321 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2322 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2323 azx_dev->sd_int_sta_mask = 1 << i;
2324 /* stream tag: must be non-zero and unique */
2325 azx_dev->index = i;
2326 azx_dev->stream_tag = i + 1;
2327 }
2328
2329 return 0;
2330 }
2331
2332 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2333 {
2334 if (request_irq(chip->pci->irq, azx_interrupt,
2335 chip->msi ? 0 : IRQF_SHARED,
2336 KBUILD_MODNAME, chip)) {
2337 dev_err(chip->card->dev,
2338 "unable to grab IRQ %d, disabling device\n",
2339 chip->pci->irq);
2340 if (do_disconnect)
2341 snd_card_disconnect(chip->card);
2342 return -1;
2343 }
2344 chip->irq = chip->pci->irq;
2345 pci_intx(chip->pci, !chip->msi);
2346 return 0;
2347 }
2348
2349
2350 static void azx_stop_chip(struct azx *chip)
2351 {
2352 if (!chip->initialized)
2353 return;
2354
2355 /* disable interrupts */
2356 azx_int_disable(chip);
2357 azx_int_clear(chip);
2358
2359 /* disable CORB/RIRB */
2360 azx_free_cmd_io(chip);
2361
2362 /* disable position buffer */
2363 azx_writel(chip, DPLBASE, 0);
2364 azx_writel(chip, DPUBASE, 0);
2365
2366 chip->initialized = 0;
2367 }
2368
2369 #ifdef CONFIG_SND_HDA_DSP_LOADER
2370 /*
2371 * DSP loading code (e.g. for CA0132)
2372 */
2373
2374 /* use the first stream for loading DSP */
2375 static struct azx_dev *
2376 azx_get_dsp_loader_dev(struct azx *chip)
2377 {
2378 return &chip->azx_dev[chip->playback_index_offset];
2379 }
2380
2381 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2382 unsigned int byte_size,
2383 struct snd_dma_buffer *bufp)
2384 {
2385 u32 *bdl;
2386 struct azx *chip = bus->private_data;
2387 struct azx_dev *azx_dev;
2388 int err;
2389
2390 azx_dev = azx_get_dsp_loader_dev(chip);
2391
2392 dsp_lock(azx_dev);
2393 spin_lock_irq(&chip->reg_lock);
2394 if (azx_dev->running || azx_dev->locked) {
2395 spin_unlock_irq(&chip->reg_lock);
2396 err = -EBUSY;
2397 goto unlock;
2398 }
2399 azx_dev->prepared = 0;
2400 chip->saved_azx_dev = *azx_dev;
2401 azx_dev->locked = 1;
2402 spin_unlock_irq(&chip->reg_lock);
2403
2404 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2405 chip->card->dev,
2406 byte_size, bufp);
2407 if (err < 0)
2408 goto err_alloc;
2409
2410 mark_pages_wc(chip, bufp, true);
2411 azx_dev->bufsize = byte_size;
2412 azx_dev->period_bytes = byte_size;
2413 azx_dev->format_val = format;
2414
2415 azx_stream_reset(chip, azx_dev);
2416
2417 /* reset BDL address */
2418 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
2419 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
2420
2421 azx_dev->frags = 0;
2422 bdl = (u32 *)azx_dev->bdl.area;
2423 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2424 if (err < 0)
2425 goto error;
2426
2427 azx_setup_controller(chip, azx_dev);
2428 dsp_unlock(azx_dev);
2429 return azx_dev->stream_tag;
2430
2431 error:
2432 mark_pages_wc(chip, bufp, false);
2433 snd_dma_free_pages(bufp);
2434 err_alloc:
2435 spin_lock_irq(&chip->reg_lock);
2436 if (azx_dev->opened)
2437 *azx_dev = chip->saved_azx_dev;
2438 azx_dev->locked = 0;
2439 spin_unlock_irq(&chip->reg_lock);
2440 unlock:
2441 dsp_unlock(azx_dev);
2442 return err;
2443 }
2444
2445 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2446 {
2447 struct azx *chip = bus->private_data;
2448 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2449
2450 if (start)
2451 azx_stream_start(chip, azx_dev);
2452 else
2453 azx_stream_stop(chip, azx_dev);
2454 azx_dev->running = start;
2455 }
2456
2457 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2458 struct snd_dma_buffer *dmab)
2459 {
2460 struct azx *chip = bus->private_data;
2461 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2462
2463 if (!dmab->area || !azx_dev->locked)
2464 return;
2465
2466 dsp_lock(azx_dev);
2467 /* reset BDL address */
2468 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
2469 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
2470 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
2471 azx_dev->bufsize = 0;
2472 azx_dev->period_bytes = 0;
2473 azx_dev->format_val = 0;
2474
2475 mark_pages_wc(chip, dmab, false);
2476 snd_dma_free_pages(dmab);
2477 dmab->area = NULL;
2478
2479 spin_lock_irq(&chip->reg_lock);
2480 if (azx_dev->opened)
2481 *azx_dev = chip->saved_azx_dev;
2482 azx_dev->locked = 0;
2483 spin_unlock_irq(&chip->reg_lock);
2484 dsp_unlock(azx_dev);
2485 }
2486 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2487
2488 #ifdef CONFIG_PM
2489 /* power-up/down the controller */
2490 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2491 {
2492 struct azx *chip = bus->private_data;
2493
2494 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2495 return;
2496
2497 if (power_up)
2498 pm_runtime_get_sync(chip->card->dev);
2499 else
2500 pm_runtime_put_sync(chip->card->dev);
2501 }
2502
2503 static DEFINE_MUTEX(card_list_lock);
2504 static LIST_HEAD(card_list);
2505
2506 static void azx_add_card_list(struct azx *chip)
2507 {
2508 mutex_lock(&card_list_lock);
2509 list_add(&chip->list, &card_list);
2510 mutex_unlock(&card_list_lock);
2511 }
2512
2513 static void azx_del_card_list(struct azx *chip)
2514 {
2515 mutex_lock(&card_list_lock);
2516 list_del_init(&chip->list);
2517 mutex_unlock(&card_list_lock);
2518 }
2519
2520 /* trigger power-save check at writing parameter */
2521 static int param_set_xint(const char *val, const struct kernel_param *kp)
2522 {
2523 struct azx *chip;
2524 struct hda_codec *c;
2525 int prev = power_save;
2526 int ret = param_set_int(val, kp);
2527
2528 if (ret || prev == power_save)
2529 return ret;
2530
2531 mutex_lock(&card_list_lock);
2532 list_for_each_entry(chip, &card_list, list) {
2533 if (!chip->bus || chip->disabled)
2534 continue;
2535 list_for_each_entry(c, &chip->bus->codec_list, list)
2536 snd_hda_power_sync(c);
2537 }
2538 mutex_unlock(&card_list_lock);
2539 return 0;
2540 }
2541 #else
2542 #define azx_add_card_list(chip) /* NOP */
2543 #define azx_del_card_list(chip) /* NOP */
2544 #endif /* CONFIG_PM */
2545
2546 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2547 /*
2548 * power management
2549 */
2550 static int azx_suspend(struct device *dev)
2551 {
2552 struct pci_dev *pci = to_pci_dev(dev);
2553 struct snd_card *card = dev_get_drvdata(dev);
2554 struct azx *chip = card->private_data;
2555 struct azx_pcm *p;
2556
2557 if (chip->disabled)
2558 return 0;
2559
2560 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2561 azx_clear_irq_pending(chip);
2562 list_for_each_entry(p, &chip->pcm_list, list)
2563 snd_pcm_suspend_all(p->pcm);
2564 if (chip->initialized)
2565 snd_hda_suspend(chip->bus);
2566 azx_stop_chip(chip);
2567 azx_enter_link_reset(chip);
2568 if (chip->irq >= 0) {
2569 free_irq(chip->irq, chip);
2570 chip->irq = -1;
2571 }
2572 if (chip->msi)
2573 pci_disable_msi(chip->pci);
2574 pci_disable_device(pci);
2575 pci_save_state(pci);
2576 pci_set_power_state(pci, PCI_D3hot);
2577 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2578 hda_display_power(false);
2579 return 0;
2580 }
2581
2582 static int azx_resume(struct device *dev)
2583 {
2584 struct pci_dev *pci = to_pci_dev(dev);
2585 struct snd_card *card = dev_get_drvdata(dev);
2586 struct azx *chip = card->private_data;
2587
2588 if (chip->disabled)
2589 return 0;
2590
2591 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2592 hda_display_power(true);
2593 pci_set_power_state(pci, PCI_D0);
2594 pci_restore_state(pci);
2595 if (pci_enable_device(pci) < 0) {
2596 dev_err(chip->card->dev,
2597 "pci_enable_device failed, disabling device\n");
2598 snd_card_disconnect(card);
2599 return -EIO;
2600 }
2601 pci_set_master(pci);
2602 if (chip->msi)
2603 if (pci_enable_msi(pci) < 0)
2604 chip->msi = 0;
2605 if (azx_acquire_irq(chip, 1) < 0)
2606 return -EIO;
2607 azx_init_pci(chip);
2608
2609 azx_init_chip(chip, 1);
2610
2611 snd_hda_resume(chip->bus);
2612 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2613 return 0;
2614 }
2615 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2616
2617 #ifdef CONFIG_PM_RUNTIME
2618 static int azx_runtime_suspend(struct device *dev)
2619 {
2620 struct snd_card *card = dev_get_drvdata(dev);
2621 struct azx *chip = card->private_data;
2622
2623 if (chip->disabled)
2624 return 0;
2625
2626 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2627 return 0;
2628
2629 /* enable controller wake up event */
2630 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
2631 STATESTS_INT_MASK);
2632
2633 azx_stop_chip(chip);
2634 azx_enter_link_reset(chip);
2635 azx_clear_irq_pending(chip);
2636 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2637 hda_display_power(false);
2638 return 0;
2639 }
2640
2641 static int azx_runtime_resume(struct device *dev)
2642 {
2643 struct snd_card *card = dev_get_drvdata(dev);
2644 struct azx *chip = card->private_data;
2645 struct hda_bus *bus;
2646 struct hda_codec *codec;
2647 int status;
2648
2649 if (chip->disabled)
2650 return 0;
2651
2652 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2653 return 0;
2654
2655 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2656 hda_display_power(true);
2657
2658 /* Read STATESTS before controller reset */
2659 status = azx_readw(chip, STATESTS);
2660
2661 azx_init_pci(chip);
2662 azx_init_chip(chip, 1);
2663
2664 bus = chip->bus;
2665 if (status && bus) {
2666 list_for_each_entry(codec, &bus->codec_list, list)
2667 if (status & (1 << codec->addr))
2668 queue_delayed_work(codec->bus->workq,
2669 &codec->jackpoll_work, codec->jackpoll_interval);
2670 }
2671
2672 /* disable controller Wake Up event*/
2673 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
2674 ~STATESTS_INT_MASK);
2675
2676 return 0;
2677 }
2678
2679 static int azx_runtime_idle(struct device *dev)
2680 {
2681 struct snd_card *card = dev_get_drvdata(dev);
2682 struct azx *chip = card->private_data;
2683
2684 if (chip->disabled)
2685 return 0;
2686
2687 if (!power_save_controller ||
2688 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2689 return -EBUSY;
2690
2691 return 0;
2692 }
2693
2694 #endif /* CONFIG_PM_RUNTIME */
2695
2696 #ifdef CONFIG_PM
2697 static const struct dev_pm_ops azx_pm = {
2698 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2699 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
2700 };
2701
2702 #define AZX_PM_OPS &azx_pm
2703 #else
2704 #define AZX_PM_OPS NULL
2705 #endif /* CONFIG_PM */
2706
2707
2708 /*
2709 * reboot notifier for hang-up problem at power-down
2710 */
2711 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2712 {
2713 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2714 snd_hda_bus_reboot_notify(chip->bus);
2715 azx_stop_chip(chip);
2716 return NOTIFY_OK;
2717 }
2718
2719 static void azx_notifier_register(struct azx *chip)
2720 {
2721 chip->reboot_notifier.notifier_call = azx_halt;
2722 register_reboot_notifier(&chip->reboot_notifier);
2723 }
2724
2725 static void azx_notifier_unregister(struct azx *chip)
2726 {
2727 if (chip->reboot_notifier.notifier_call)
2728 unregister_reboot_notifier(&chip->reboot_notifier);
2729 }
2730
2731 static int azx_probe_continue(struct azx *chip);
2732
2733 #ifdef SUPPORT_VGA_SWITCHEROO
2734 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
2735
2736 static void azx_vs_set_state(struct pci_dev *pci,
2737 enum vga_switcheroo_state state)
2738 {
2739 struct snd_card *card = pci_get_drvdata(pci);
2740 struct azx *chip = card->private_data;
2741 bool disabled;
2742
2743 wait_for_completion(&chip->probe_wait);
2744 if (chip->init_failed)
2745 return;
2746
2747 disabled = (state == VGA_SWITCHEROO_OFF);
2748 if (chip->disabled == disabled)
2749 return;
2750
2751 if (!chip->bus) {
2752 chip->disabled = disabled;
2753 if (!disabled) {
2754 dev_info(chip->card->dev,
2755 "Start delayed initialization\n");
2756 if (azx_probe_continue(chip) < 0) {
2757 dev_err(chip->card->dev, "initialization error\n");
2758 chip->init_failed = true;
2759 }
2760 }
2761 } else {
2762 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
2763 disabled ? "Disabling" : "Enabling");
2764 if (disabled) {
2765 pm_runtime_put_sync_suspend(card->dev);
2766 azx_suspend(card->dev);
2767 /* when we get suspended by vga switcheroo we end up in D3cold,
2768 * however we have no ACPI handle, so pci/acpi can't put us there,
2769 * put ourselves there */
2770 pci->current_state = PCI_D3cold;
2771 chip->disabled = true;
2772 if (snd_hda_lock_devices(chip->bus))
2773 dev_warn(chip->card->dev,
2774 "Cannot lock devices!\n");
2775 } else {
2776 snd_hda_unlock_devices(chip->bus);
2777 pm_runtime_get_noresume(card->dev);
2778 chip->disabled = false;
2779 azx_resume(card->dev);
2780 }
2781 }
2782 }
2783
2784 static bool azx_vs_can_switch(struct pci_dev *pci)
2785 {
2786 struct snd_card *card = pci_get_drvdata(pci);
2787 struct azx *chip = card->private_data;
2788
2789 wait_for_completion(&chip->probe_wait);
2790 if (chip->init_failed)
2791 return false;
2792 if (chip->disabled || !chip->bus)
2793 return true;
2794 if (snd_hda_lock_devices(chip->bus))
2795 return false;
2796 snd_hda_unlock_devices(chip->bus);
2797 return true;
2798 }
2799
2800 static void init_vga_switcheroo(struct azx *chip)
2801 {
2802 struct pci_dev *p = get_bound_vga(chip->pci);
2803 if (p) {
2804 dev_info(chip->card->dev,
2805 "Handle VGA-switcheroo audio client\n");
2806 chip->use_vga_switcheroo = 1;
2807 pci_dev_put(p);
2808 }
2809 }
2810
2811 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2812 .set_gpu_state = azx_vs_set_state,
2813 .can_switch = azx_vs_can_switch,
2814 };
2815
2816 static int register_vga_switcheroo(struct azx *chip)
2817 {
2818 int err;
2819
2820 if (!chip->use_vga_switcheroo)
2821 return 0;
2822 /* FIXME: currently only handling DIS controller
2823 * is there any machine with two switchable HDMI audio controllers?
2824 */
2825 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2826 VGA_SWITCHEROO_DIS,
2827 chip->bus != NULL);
2828 if (err < 0)
2829 return err;
2830 chip->vga_switcheroo_registered = 1;
2831
2832 /* register as an optimus hdmi audio power domain */
2833 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
2834 &chip->hdmi_pm_domain);
2835 return 0;
2836 }
2837 #else
2838 #define init_vga_switcheroo(chip) /* NOP */
2839 #define register_vga_switcheroo(chip) 0
2840 #define check_hdmi_disabled(pci) false
2841 #endif /* SUPPORT_VGA_SWITCHER */
2842
2843 /*
2844 * destructor
2845 */
2846 static int azx_free(struct azx *chip)
2847 {
2848 struct pci_dev *pci = chip->pci;
2849 int i;
2850
2851 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
2852 && chip->running)
2853 pm_runtime_get_noresume(&pci->dev);
2854
2855 azx_del_card_list(chip);
2856
2857 azx_notifier_unregister(chip);
2858
2859 chip->init_failed = 1; /* to be sure */
2860 complete_all(&chip->probe_wait);
2861
2862 if (use_vga_switcheroo(chip)) {
2863 if (chip->disabled && chip->bus)
2864 snd_hda_unlock_devices(chip->bus);
2865 if (chip->vga_switcheroo_registered)
2866 vga_switcheroo_unregister_client(chip->pci);
2867 }
2868
2869 if (chip->initialized) {
2870 azx_clear_irq_pending(chip);
2871 for (i = 0; i < chip->num_streams; i++)
2872 azx_stream_stop(chip, &chip->azx_dev[i]);
2873 azx_stop_chip(chip);
2874 }
2875
2876 if (chip->irq >= 0)
2877 free_irq(chip->irq, (void*)chip);
2878 if (chip->msi)
2879 pci_disable_msi(chip->pci);
2880 if (chip->remap_addr)
2881 iounmap(chip->remap_addr);
2882
2883 if (chip->azx_dev) {
2884 for (i = 0; i < chip->num_streams; i++)
2885 if (chip->azx_dev[i].bdl.area) {
2886 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2887 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2888 }
2889 }
2890 if (chip->rb.area) {
2891 mark_pages_wc(chip, &chip->rb, false);
2892 snd_dma_free_pages(&chip->rb);
2893 }
2894 if (chip->posbuf.area) {
2895 mark_pages_wc(chip, &chip->posbuf, false);
2896 snd_dma_free_pages(&chip->posbuf);
2897 }
2898 if (chip->region_requested)
2899 pci_release_regions(chip->pci);
2900 pci_disable_device(chip->pci);
2901 kfree(chip->azx_dev);
2902 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2903 if (chip->fw)
2904 release_firmware(chip->fw);
2905 #endif
2906 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2907 hda_display_power(false);
2908 hda_i915_exit();
2909 }
2910 kfree(chip);
2911
2912 return 0;
2913 }
2914
2915 static int azx_dev_free(struct snd_device *device)
2916 {
2917 return azx_free(device->device_data);
2918 }
2919
2920 #ifdef SUPPORT_VGA_SWITCHEROO
2921 /*
2922 * Check of disabled HDMI controller by vga-switcheroo
2923 */
2924 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
2925 {
2926 struct pci_dev *p;
2927
2928 /* check only discrete GPU */
2929 switch (pci->vendor) {
2930 case PCI_VENDOR_ID_ATI:
2931 case PCI_VENDOR_ID_AMD:
2932 case PCI_VENDOR_ID_NVIDIA:
2933 if (pci->devfn == 1) {
2934 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2935 pci->bus->number, 0);
2936 if (p) {
2937 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2938 return p;
2939 pci_dev_put(p);
2940 }
2941 }
2942 break;
2943 }
2944 return NULL;
2945 }
2946
2947 static bool check_hdmi_disabled(struct pci_dev *pci)
2948 {
2949 bool vga_inactive = false;
2950 struct pci_dev *p = get_bound_vga(pci);
2951
2952 if (p) {
2953 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2954 vga_inactive = true;
2955 pci_dev_put(p);
2956 }
2957 return vga_inactive;
2958 }
2959 #endif /* SUPPORT_VGA_SWITCHEROO */
2960
2961 /*
2962 * white/black-listing for position_fix
2963 */
2964 static struct snd_pci_quirk position_fix_list[] = {
2965 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2966 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2967 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2968 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2969 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2970 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2971 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2972 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2973 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2974 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2975 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2976 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2977 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2978 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2979 {}
2980 };
2981
2982 static int check_position_fix(struct azx *chip, int fix)
2983 {
2984 const struct snd_pci_quirk *q;
2985
2986 switch (fix) {
2987 case POS_FIX_AUTO:
2988 case POS_FIX_LPIB:
2989 case POS_FIX_POSBUF:
2990 case POS_FIX_VIACOMBO:
2991 case POS_FIX_COMBO:
2992 return fix;
2993 }
2994
2995 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2996 if (q) {
2997 dev_info(chip->card->dev,
2998 "position_fix set to %d for device %04x:%04x\n",
2999 q->value, q->subvendor, q->subdevice);
3000 return q->value;
3001 }
3002
3003 /* Check VIA/ATI HD Audio Controller exist */
3004 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3005 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
3006 return POS_FIX_VIACOMBO;
3007 }
3008 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3009 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
3010 return POS_FIX_LPIB;
3011 }
3012 return POS_FIX_AUTO;
3013 }
3014
3015 /*
3016 * black-lists for probe_mask
3017 */
3018 static struct snd_pci_quirk probe_mask_list[] = {
3019 /* Thinkpad often breaks the controller communication when accessing
3020 * to the non-working (or non-existing) modem codec slot.
3021 */
3022 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3023 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3024 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3025 /* broken BIOS */
3026 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3027 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3028 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3029 /* forced codec slots */
3030 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3031 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3032 /* WinFast VP200 H (Teradici) user reported broken communication */
3033 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3034 {}
3035 };
3036
3037 #define AZX_FORCE_CODEC_MASK 0x100
3038
3039 static void check_probe_mask(struct azx *chip, int dev)
3040 {
3041 const struct snd_pci_quirk *q;
3042
3043 chip->codec_probe_mask = probe_mask[dev];
3044 if (chip->codec_probe_mask == -1) {
3045 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3046 if (q) {
3047 dev_info(chip->card->dev,
3048 "probe_mask set to 0x%x for device %04x:%04x\n",
3049 q->value, q->subvendor, q->subdevice);
3050 chip->codec_probe_mask = q->value;
3051 }
3052 }
3053
3054 /* check forced option */
3055 if (chip->codec_probe_mask != -1 &&
3056 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3057 chip->codec_mask = chip->codec_probe_mask & 0xff;
3058 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
3059 chip->codec_mask);
3060 }
3061 }
3062
3063 /*
3064 * white/black-list for enable_msi
3065 */
3066 static struct snd_pci_quirk msi_black_list[] = {
3067 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
3068 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
3069 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
3070 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
3071 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3072 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3073 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3074 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
3075 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3076 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3077 {}
3078 };
3079
3080 static void check_msi(struct azx *chip)
3081 {
3082 const struct snd_pci_quirk *q;
3083
3084 if (enable_msi >= 0) {
3085 chip->msi = !!enable_msi;
3086 return;
3087 }
3088 chip->msi = 1; /* enable MSI as default */
3089 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3090 if (q) {
3091 dev_info(chip->card->dev,
3092 "msi for device %04x:%04x set to %d\n",
3093 q->subvendor, q->subdevice, q->value);
3094 chip->msi = q->value;
3095 return;
3096 }
3097
3098 /* NVidia chipsets seem to cause troubles with MSI */
3099 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3100 dev_info(chip->card->dev, "Disabling MSI\n");
3101 chip->msi = 0;
3102 }
3103 }
3104
3105 /* check the snoop mode availability */
3106 static void azx_check_snoop_available(struct azx *chip)
3107 {
3108 bool snoop = chip->snoop;
3109
3110 switch (chip->driver_type) {
3111 case AZX_DRIVER_VIA:
3112 /* force to non-snoop mode for a new VIA controller
3113 * when BIOS is set
3114 */
3115 if (snoop) {
3116 u8 val;
3117 pci_read_config_byte(chip->pci, 0x42, &val);
3118 if (!(val & 0x80) && chip->pci->revision == 0x30)
3119 snoop = false;
3120 }
3121 break;
3122 case AZX_DRIVER_ATIHDMI_NS:
3123 /* new ATI HDMI requires non-snoop */
3124 snoop = false;
3125 break;
3126 case AZX_DRIVER_CTHDA:
3127 snoop = false;
3128 break;
3129 }
3130
3131 if (snoop != chip->snoop) {
3132 dev_info(chip->card->dev, "Force to %s mode\n",
3133 snoop ? "snoop" : "non-snoop");
3134 chip->snoop = snoop;
3135 }
3136 }
3137
3138 static void azx_probe_work(struct work_struct *work)
3139 {
3140 azx_probe_continue(container_of(work, struct azx, probe_work));
3141 }
3142
3143 /*
3144 * constructor
3145 */
3146 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3147 int dev, unsigned int driver_caps,
3148 const struct hda_controller_ops *hda_ops,
3149 struct azx **rchip)
3150 {
3151 static struct snd_device_ops ops = {
3152 .dev_free = azx_dev_free,
3153 };
3154 struct azx *chip;
3155 int err;
3156
3157 *rchip = NULL;
3158
3159 err = pci_enable_device(pci);
3160 if (err < 0)
3161 return err;
3162
3163 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3164 if (!chip) {
3165 dev_err(card->dev, "Cannot allocate chip\n");
3166 pci_disable_device(pci);
3167 return -ENOMEM;
3168 }
3169
3170 spin_lock_init(&chip->reg_lock);
3171 mutex_init(&chip->open_mutex);
3172 chip->card = card;
3173 chip->pci = pci;
3174 chip->ops = hda_ops;
3175 chip->irq = -1;
3176 chip->driver_caps = driver_caps;
3177 chip->driver_type = driver_caps & 0xff;
3178 check_msi(chip);
3179 chip->dev_index = dev;
3180 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3181 INIT_LIST_HEAD(&chip->pcm_list);
3182 INIT_LIST_HEAD(&chip->list);
3183 init_vga_switcheroo(chip);
3184 init_completion(&chip->probe_wait);
3185
3186 chip->position_fix[0] = chip->position_fix[1] =
3187 check_position_fix(chip, position_fix[dev]);
3188 /* combo mode uses LPIB for playback */
3189 if (chip->position_fix[0] == POS_FIX_COMBO) {
3190 chip->position_fix[0] = POS_FIX_LPIB;
3191 chip->position_fix[1] = POS_FIX_AUTO;
3192 }
3193
3194 check_probe_mask(chip, dev);
3195
3196 chip->single_cmd = single_cmd;
3197 chip->snoop = hda_snoop;
3198 azx_check_snoop_available(chip);
3199
3200 if (bdl_pos_adj[dev] < 0) {
3201 switch (chip->driver_type) {
3202 case AZX_DRIVER_ICH:
3203 case AZX_DRIVER_PCH:
3204 bdl_pos_adj[dev] = 1;
3205 break;
3206 default:
3207 bdl_pos_adj[dev] = 32;
3208 break;
3209 }
3210 }
3211 chip->bdl_pos_adj = bdl_pos_adj;
3212
3213 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3214 if (err < 0) {
3215 dev_err(card->dev, "Error creating device [card]!\n");
3216 azx_free(chip);
3217 return err;
3218 }
3219
3220 /* continue probing in work context as may trigger request module */
3221 INIT_WORK(&chip->probe_work, azx_probe_work);
3222
3223 *rchip = chip;
3224
3225 return 0;
3226 }
3227
3228 static int azx_first_init(struct azx *chip)
3229 {
3230 int dev = chip->dev_index;
3231 struct pci_dev *pci = chip->pci;
3232 struct snd_card *card = chip->card;
3233 int i, err;
3234 unsigned short gcap;
3235
3236 #if BITS_PER_LONG != 64
3237 /* Fix up base address on ULI M5461 */
3238 if (chip->driver_type == AZX_DRIVER_ULI) {
3239 u16 tmp3;
3240 pci_read_config_word(pci, 0x40, &tmp3);
3241 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3242 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3243 }
3244 #endif
3245
3246 err = pci_request_regions(pci, "ICH HD audio");
3247 if (err < 0)
3248 return err;
3249 chip->region_requested = 1;
3250
3251 chip->addr = pci_resource_start(pci, 0);
3252 chip->remap_addr = pci_ioremap_bar(pci, 0);
3253 if (chip->remap_addr == NULL) {
3254 dev_err(card->dev, "ioremap error\n");
3255 return -ENXIO;
3256 }
3257
3258 if (chip->msi)
3259 if (pci_enable_msi(pci) < 0)
3260 chip->msi = 0;
3261
3262 if (azx_acquire_irq(chip, 0) < 0)
3263 return -EBUSY;
3264
3265 pci_set_master(pci);
3266 synchronize_irq(chip->irq);
3267
3268 gcap = azx_readw(chip, GCAP);
3269 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
3270
3271 /* disable SB600 64bit support for safety */
3272 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3273 struct pci_dev *p_smbus;
3274 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3275 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3276 NULL);
3277 if (p_smbus) {
3278 if (p_smbus->revision < 0x30)
3279 gcap &= ~ICH6_GCAP_64OK;
3280 pci_dev_put(p_smbus);
3281 }
3282 }
3283
3284 /* disable 64bit DMA address on some devices */
3285 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3286 dev_dbg(card->dev, "Disabling 64bit DMA\n");
3287 gcap &= ~ICH6_GCAP_64OK;
3288 }
3289
3290 /* disable buffer size rounding to 128-byte multiples if supported */
3291 if (align_buffer_size >= 0)
3292 chip->align_buffer_size = !!align_buffer_size;
3293 else {
3294 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3295 chip->align_buffer_size = 0;
3296 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3297 chip->align_buffer_size = 1;
3298 else
3299 chip->align_buffer_size = 1;
3300 }
3301
3302 /* allow 64bit DMA address if supported by H/W */
3303 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3304 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3305 else {
3306 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3307 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3308 }
3309
3310 /* read number of streams from GCAP register instead of using
3311 * hardcoded value
3312 */
3313 chip->capture_streams = (gcap >> 8) & 0x0f;
3314 chip->playback_streams = (gcap >> 12) & 0x0f;
3315 if (!chip->playback_streams && !chip->capture_streams) {
3316 /* gcap didn't give any info, switching to old method */
3317
3318 switch (chip->driver_type) {
3319 case AZX_DRIVER_ULI:
3320 chip->playback_streams = ULI_NUM_PLAYBACK;
3321 chip->capture_streams = ULI_NUM_CAPTURE;
3322 break;
3323 case AZX_DRIVER_ATIHDMI:
3324 case AZX_DRIVER_ATIHDMI_NS:
3325 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3326 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3327 break;
3328 case AZX_DRIVER_GENERIC:
3329 default:
3330 chip->playback_streams = ICH6_NUM_PLAYBACK;
3331 chip->capture_streams = ICH6_NUM_CAPTURE;
3332 break;
3333 }
3334 }
3335 chip->capture_index_offset = 0;
3336 chip->playback_index_offset = chip->capture_streams;
3337 chip->num_streams = chip->playback_streams + chip->capture_streams;
3338 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3339 GFP_KERNEL);
3340 if (!chip->azx_dev) {
3341 dev_err(card->dev, "cannot malloc azx_dev\n");
3342 return -ENOMEM;
3343 }
3344
3345 for (i = 0; i < chip->num_streams; i++) {
3346 dsp_lock_init(&chip->azx_dev[i]);
3347 /* allocate memory for the BDL for each stream */
3348 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3349 chip->card->dev,
3350 BDL_SIZE, &chip->azx_dev[i].bdl);
3351 if (err < 0) {
3352 dev_err(card->dev, "cannot allocate BDL\n");
3353 return -ENOMEM;
3354 }
3355 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3356 }
3357 /* allocate memory for the position buffer */
3358 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3359 chip->card->dev,
3360 chip->num_streams * 8, &chip->posbuf);
3361 if (err < 0) {
3362 dev_err(card->dev, "cannot allocate posbuf\n");
3363 return -ENOMEM;
3364 }
3365 mark_pages_wc(chip, &chip->posbuf, true);
3366 /* allocate CORB/RIRB */
3367 err = azx_alloc_cmd_io(chip);
3368 if (err < 0)
3369 return err;
3370
3371 /* initialize streams */
3372 azx_init_stream(chip);
3373
3374 /* initialize chip */
3375 azx_init_pci(chip);
3376 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3377
3378 /* codec detection */
3379 if (!chip->codec_mask) {
3380 dev_err(card->dev, "no codecs found!\n");
3381 return -ENODEV;
3382 }
3383
3384 strcpy(card->driver, "HDA-Intel");
3385 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3386 sizeof(card->shortname));
3387 snprintf(card->longname, sizeof(card->longname),
3388 "%s at 0x%lx irq %i",
3389 card->shortname, chip->addr, chip->irq);
3390
3391 return 0;
3392 }
3393
3394 static void power_down_all_codecs(struct azx *chip)
3395 {
3396 #ifdef CONFIG_PM
3397 /* The codecs were powered up in snd_hda_codec_new().
3398 * Now all initialization done, so turn them down if possible
3399 */
3400 struct hda_codec *codec;
3401 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3402 snd_hda_power_down(codec);
3403 }
3404 #endif
3405 }
3406
3407 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3408 /* callback from request_firmware_nowait() */
3409 static void azx_firmware_cb(const struct firmware *fw, void *context)
3410 {
3411 struct snd_card *card = context;
3412 struct azx *chip = card->private_data;
3413 struct pci_dev *pci = chip->pci;
3414
3415 if (!fw) {
3416 dev_err(card->dev, "Cannot load firmware, aborting\n");
3417 goto error;
3418 }
3419
3420 chip->fw = fw;
3421 if (!chip->disabled) {
3422 /* continue probing */
3423 if (azx_probe_continue(chip))
3424 goto error;
3425 }
3426 return; /* OK */
3427
3428 error:
3429 snd_card_free(card);
3430 pci_set_drvdata(pci, NULL);
3431 }
3432 #endif
3433
3434 /*
3435 * HDA controller ops.
3436 */
3437
3438 /* PCI register access. */
3439 static void pci_azx_writel(u32 value, u32 *addr)
3440 {
3441 writel(value, addr);
3442 }
3443
3444 static u32 pci_azx_readl(u32 *addr)
3445 {
3446 return readl(addr);
3447 }
3448
3449 static void pci_azx_writew(u16 value, u16 *addr)
3450 {
3451 writew(value, addr);
3452 }
3453
3454 static u16 pci_azx_readw(u16 *addr)
3455 {
3456 return readw(addr);
3457 }
3458
3459 static void pci_azx_writeb(u8 value, u8 *addr)
3460 {
3461 writeb(value, addr);
3462 }
3463
3464 static u8 pci_azx_readb(u8 *addr)
3465 {
3466 return readb(addr);
3467 }
3468
3469 static int disable_msi_reset_irq(struct azx *chip)
3470 {
3471 int err;
3472
3473 free_irq(chip->irq, chip);
3474 chip->irq = -1;
3475 pci_disable_msi(chip->pci);
3476 chip->msi = 0;
3477 err = azx_acquire_irq(chip, 1);
3478 if (err < 0)
3479 return err;
3480
3481 return 0;
3482 }
3483
3484 static const struct hda_controller_ops pci_hda_ops = {
3485 .writel = pci_azx_writel,
3486 .readl = pci_azx_readl,
3487 .writew = pci_azx_writew,
3488 .readw = pci_azx_readw,
3489 .writeb = pci_azx_writeb,
3490 .readb = pci_azx_readb,
3491 .disable_msi_reset_irq = disable_msi_reset_irq,
3492 };
3493
3494 static int azx_probe(struct pci_dev *pci,
3495 const struct pci_device_id *pci_id)
3496 {
3497 static int dev;
3498 struct snd_card *card;
3499 struct azx *chip;
3500 bool schedule_probe;
3501 int err;
3502
3503 if (dev >= SNDRV_CARDS)
3504 return -ENODEV;
3505 if (!enable[dev]) {
3506 dev++;
3507 return -ENOENT;
3508 }
3509
3510 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3511 0, &card);
3512 if (err < 0) {
3513 dev_err(&pci->dev, "Error creating card!\n");
3514 return err;
3515 }
3516
3517 err = azx_create(card, pci, dev, pci_id->driver_data,
3518 &pci_hda_ops, &chip);
3519 if (err < 0)
3520 goto out_free;
3521 card->private_data = chip;
3522
3523 pci_set_drvdata(pci, card);
3524
3525 err = register_vga_switcheroo(chip);
3526 if (err < 0) {
3527 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
3528 goto out_free;
3529 }
3530
3531 if (check_hdmi_disabled(pci)) {
3532 dev_info(card->dev, "VGA controller is disabled\n");
3533 dev_info(card->dev, "Delaying initialization\n");
3534 chip->disabled = true;
3535 }
3536
3537 schedule_probe = !chip->disabled;
3538
3539 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3540 if (patch[dev] && *patch[dev]) {
3541 dev_info(card->dev, "Applying patch firmware '%s'\n",
3542 patch[dev]);
3543 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3544 &pci->dev, GFP_KERNEL, card,
3545 azx_firmware_cb);
3546 if (err < 0)
3547 goto out_free;
3548 schedule_probe = false; /* continued in azx_firmware_cb() */
3549 }
3550 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3551
3552 #ifndef CONFIG_SND_HDA_I915
3553 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
3554 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
3555 #endif
3556
3557 if (schedule_probe)
3558 schedule_work(&chip->probe_work);
3559
3560 dev++;
3561 if (chip->disabled)
3562 complete_all(&chip->probe_wait);
3563 return 0;
3564
3565 out_free:
3566 snd_card_free(card);
3567 return err;
3568 }
3569
3570 static int azx_probe_continue(struct azx *chip)
3571 {
3572 struct pci_dev *pci = chip->pci;
3573 int dev = chip->dev_index;
3574 int err;
3575
3576 /* Request power well for Haswell HDA controller and codec */
3577 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
3578 #ifdef CONFIG_SND_HDA_I915
3579 err = hda_i915_init();
3580 if (err < 0) {
3581 dev_err(chip->card->dev,
3582 "Error request power-well from i915\n");
3583 goto out_free;
3584 }
3585 #endif
3586 hda_display_power(true);
3587 }
3588
3589 err = azx_first_init(chip);
3590 if (err < 0)
3591 goto out_free;
3592
3593 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3594 chip->beep_mode = beep_mode[dev];
3595 #endif
3596
3597 /* create codec instances */
3598 err = azx_codec_create(chip, model[dev]);
3599 if (err < 0)
3600 goto out_free;
3601 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3602 if (chip->fw) {
3603 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3604 chip->fw->data);
3605 if (err < 0)
3606 goto out_free;
3607 #ifndef CONFIG_PM
3608 release_firmware(chip->fw); /* no longer needed */
3609 chip->fw = NULL;
3610 #endif
3611 }
3612 #endif
3613 if ((probe_only[dev] & 1) == 0) {
3614 err = azx_codec_configure(chip);
3615 if (err < 0)
3616 goto out_free;
3617 }
3618
3619 /* create PCM streams */
3620 err = snd_hda_build_pcms(chip->bus);
3621 if (err < 0)
3622 goto out_free;
3623
3624 /* create mixer controls */
3625 err = azx_mixer_create(chip);
3626 if (err < 0)
3627 goto out_free;
3628
3629 err = snd_card_register(chip->card);
3630 if (err < 0)
3631 goto out_free;
3632
3633 chip->running = 1;
3634 power_down_all_codecs(chip);
3635 azx_notifier_register(chip);
3636 azx_add_card_list(chip);
3637 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
3638 pm_runtime_put_noidle(&pci->dev);
3639
3640 out_free:
3641 if (err < 0)
3642 chip->init_failed = 1;
3643 complete_all(&chip->probe_wait);
3644 return err;
3645 }
3646
3647 static void azx_remove(struct pci_dev *pci)
3648 {
3649 struct snd_card *card = pci_get_drvdata(pci);
3650
3651 if (card)
3652 snd_card_free(card);
3653 }
3654
3655 /* PCI IDs */
3656 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3657 /* CPT */
3658 { PCI_DEVICE(0x8086, 0x1c20),
3659 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3660 /* PBG */
3661 { PCI_DEVICE(0x8086, 0x1d20),
3662 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3663 /* Panther Point */
3664 { PCI_DEVICE(0x8086, 0x1e20),
3665 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3666 /* Lynx Point */
3667 { PCI_DEVICE(0x8086, 0x8c20),
3668 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3669 /* Wellsburg */
3670 { PCI_DEVICE(0x8086, 0x8d20),
3671 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3672 { PCI_DEVICE(0x8086, 0x8d21),
3673 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3674 /* Lynx Point-LP */
3675 { PCI_DEVICE(0x8086, 0x9c20),
3676 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3677 /* Lynx Point-LP */
3678 { PCI_DEVICE(0x8086, 0x9c21),
3679 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3680 /* Wildcat Point-LP */
3681 { PCI_DEVICE(0x8086, 0x9ca0),
3682 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3683 /* Haswell */
3684 { PCI_DEVICE(0x8086, 0x0a0c),
3685 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3686 { PCI_DEVICE(0x8086, 0x0c0c),
3687 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3688 { PCI_DEVICE(0x8086, 0x0d0c),
3689 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3690 /* Broadwell */
3691 { PCI_DEVICE(0x8086, 0x160c),
3692 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
3693 /* 5 Series/3400 */
3694 { PCI_DEVICE(0x8086, 0x3b56),
3695 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3696 /* Poulsbo */
3697 { PCI_DEVICE(0x8086, 0x811b),
3698 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3699 /* Oaktrail */
3700 { PCI_DEVICE(0x8086, 0x080a),
3701 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3702 /* BayTrail */
3703 { PCI_DEVICE(0x8086, 0x0f04),
3704 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3705 /* ICH */
3706 { PCI_DEVICE(0x8086, 0x2668),
3707 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3708 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3709 { PCI_DEVICE(0x8086, 0x27d8),
3710 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3711 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3712 { PCI_DEVICE(0x8086, 0x269a),
3713 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3714 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3715 { PCI_DEVICE(0x8086, 0x284b),
3716 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3717 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3718 { PCI_DEVICE(0x8086, 0x293e),
3719 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3720 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3721 { PCI_DEVICE(0x8086, 0x293f),
3722 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3723 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3724 { PCI_DEVICE(0x8086, 0x3a3e),
3725 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3726 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3727 { PCI_DEVICE(0x8086, 0x3a6e),
3728 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3729 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3730 /* Generic Intel */
3731 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3732 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3733 .class_mask = 0xffffff,
3734 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3735 /* ATI SB 450/600/700/800/900 */
3736 { PCI_DEVICE(0x1002, 0x437b),
3737 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3738 { PCI_DEVICE(0x1002, 0x4383),
3739 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3740 /* AMD Hudson */
3741 { PCI_DEVICE(0x1022, 0x780d),
3742 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3743 /* ATI HDMI */
3744 { PCI_DEVICE(0x1002, 0x793b),
3745 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3746 { PCI_DEVICE(0x1002, 0x7919),
3747 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3748 { PCI_DEVICE(0x1002, 0x960f),
3749 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3750 { PCI_DEVICE(0x1002, 0x970f),
3751 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3752 { PCI_DEVICE(0x1002, 0xaa00),
3753 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3754 { PCI_DEVICE(0x1002, 0xaa08),
3755 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3756 { PCI_DEVICE(0x1002, 0xaa10),
3757 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3758 { PCI_DEVICE(0x1002, 0xaa18),
3759 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3760 { PCI_DEVICE(0x1002, 0xaa20),
3761 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3762 { PCI_DEVICE(0x1002, 0xaa28),
3763 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3764 { PCI_DEVICE(0x1002, 0xaa30),
3765 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3766 { PCI_DEVICE(0x1002, 0xaa38),
3767 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3768 { PCI_DEVICE(0x1002, 0xaa40),
3769 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3770 { PCI_DEVICE(0x1002, 0xaa48),
3771 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3772 { PCI_DEVICE(0x1002, 0xaa50),
3773 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3774 { PCI_DEVICE(0x1002, 0xaa58),
3775 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3776 { PCI_DEVICE(0x1002, 0xaa60),
3777 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3778 { PCI_DEVICE(0x1002, 0xaa68),
3779 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3780 { PCI_DEVICE(0x1002, 0xaa80),
3781 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3782 { PCI_DEVICE(0x1002, 0xaa88),
3783 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3784 { PCI_DEVICE(0x1002, 0xaa90),
3785 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3786 { PCI_DEVICE(0x1002, 0xaa98),
3787 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3788 { PCI_DEVICE(0x1002, 0x9902),
3789 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3790 { PCI_DEVICE(0x1002, 0xaaa0),
3791 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3792 { PCI_DEVICE(0x1002, 0xaaa8),
3793 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3794 { PCI_DEVICE(0x1002, 0xaab0),
3795 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3796 /* VIA VT8251/VT8237A */
3797 { PCI_DEVICE(0x1106, 0x3288),
3798 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3799 /* VIA GFX VT7122/VX900 */
3800 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3801 /* VIA GFX VT6122/VX11 */
3802 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3803 /* SIS966 */
3804 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3805 /* ULI M5461 */
3806 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3807 /* NVIDIA MCP */
3808 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3809 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3810 .class_mask = 0xffffff,
3811 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3812 /* Teradici */
3813 { PCI_DEVICE(0x6549, 0x1200),
3814 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3815 { PCI_DEVICE(0x6549, 0x2200),
3816 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3817 /* Creative X-Fi (CA0110-IBG) */
3818 /* CTHDA chips */
3819 { PCI_DEVICE(0x1102, 0x0010),
3820 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3821 { PCI_DEVICE(0x1102, 0x0012),
3822 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3823 #if !IS_ENABLED(CONFIG_SND_CTXFI)
3824 /* the following entry conflicts with snd-ctxfi driver,
3825 * as ctxfi driver mutates from HD-audio to native mode with
3826 * a special command sequence.
3827 */
3828 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3829 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3830 .class_mask = 0xffffff,
3831 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3832 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3833 #else
3834 /* this entry seems still valid -- i.e. without emu20kx chip */
3835 { PCI_DEVICE(0x1102, 0x0009),
3836 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3837 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3838 #endif
3839 /* Vortex86MX */
3840 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3841 /* VMware HDAudio */
3842 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3843 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3844 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3845 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3846 .class_mask = 0xffffff,
3847 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3848 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3849 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3850 .class_mask = 0xffffff,
3851 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3852 { 0, }
3853 };
3854 MODULE_DEVICE_TABLE(pci, azx_ids);
3855
3856 /* pci_driver definition */
3857 static struct pci_driver azx_driver = {
3858 .name = KBUILD_MODNAME,
3859 .id_table = azx_ids,
3860 .probe = azx_probe,
3861 .remove = azx_remove,
3862 .driver = {
3863 .pm = AZX_PM_OPS,
3864 },
3865 };
3866
3867 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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