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[ALSA] hda-intel - Switch to polling mode for CORB/RIRB communication
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
4 *
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
6 *
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 *
24 * CONTACTS:
25 *
26 * Matt Jared matt.jared@intel.com
27 * Andy Kopp andy.kopp@intel.com
28 * Dan Kogan dan.d.kogan@intel.com
29 *
30 * CHANGES:
31 *
32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
33 *
34 */
35
36 #include <sound/driver.h>
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
50
51
52 static int index = SNDRV_DEFAULT_IDX1;
53 static char *id = SNDRV_DEFAULT_STR1;
54 static char *model;
55 static int position_fix;
56 static int probe_mask = -1;
57 static int single_cmd;
58
59 module_param(index, int, 0444);
60 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
61 module_param(id, charp, 0444);
62 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
63 module_param(model, charp, 0444);
64 MODULE_PARM_DESC(model, "Use the given board model.");
65 module_param(position_fix, int, 0444);
66 MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
67 module_param(probe_mask, int, 0444);
68 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
69 module_param(single_cmd, bool, 0444);
70 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs (for debugging only).");
71
72
73 /* just for backward compatibility */
74 static int enable;
75 module_param(enable, bool, 0444);
76
77 MODULE_LICENSE("GPL");
78 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
79 "{Intel, ICH6M},"
80 "{Intel, ICH7},"
81 "{Intel, ESB2},"
82 "{Intel, ICH8},"
83 "{ATI, SB450},"
84 "{ATI, SB600},"
85 "{ATI, RS600},"
86 "{VIA, VT8251},"
87 "{VIA, VT8237A},"
88 "{SiS, SIS966},"
89 "{ULI, M5461}}");
90 MODULE_DESCRIPTION("Intel HDA driver");
91
92 #define SFX "hda-intel: "
93
94 /*
95 * registers
96 */
97 #define ICH6_REG_GCAP 0x00
98 #define ICH6_REG_VMIN 0x02
99 #define ICH6_REG_VMAJ 0x03
100 #define ICH6_REG_OUTPAY 0x04
101 #define ICH6_REG_INPAY 0x06
102 #define ICH6_REG_GCTL 0x08
103 #define ICH6_REG_WAKEEN 0x0c
104 #define ICH6_REG_STATESTS 0x0e
105 #define ICH6_REG_GSTS 0x10
106 #define ICH6_REG_INTCTL 0x20
107 #define ICH6_REG_INTSTS 0x24
108 #define ICH6_REG_WALCLK 0x30
109 #define ICH6_REG_SYNC 0x34
110 #define ICH6_REG_CORBLBASE 0x40
111 #define ICH6_REG_CORBUBASE 0x44
112 #define ICH6_REG_CORBWP 0x48
113 #define ICH6_REG_CORBRP 0x4A
114 #define ICH6_REG_CORBCTL 0x4c
115 #define ICH6_REG_CORBSTS 0x4d
116 #define ICH6_REG_CORBSIZE 0x4e
117
118 #define ICH6_REG_RIRBLBASE 0x50
119 #define ICH6_REG_RIRBUBASE 0x54
120 #define ICH6_REG_RIRBWP 0x58
121 #define ICH6_REG_RINTCNT 0x5a
122 #define ICH6_REG_RIRBCTL 0x5c
123 #define ICH6_REG_RIRBSTS 0x5d
124 #define ICH6_REG_RIRBSIZE 0x5e
125
126 #define ICH6_REG_IC 0x60
127 #define ICH6_REG_IR 0x64
128 #define ICH6_REG_IRS 0x68
129 #define ICH6_IRS_VALID (1<<1)
130 #define ICH6_IRS_BUSY (1<<0)
131
132 #define ICH6_REG_DPLBASE 0x70
133 #define ICH6_REG_DPUBASE 0x74
134 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
135
136 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
137 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
138
139 /* stream register offsets from stream base */
140 #define ICH6_REG_SD_CTL 0x00
141 #define ICH6_REG_SD_STS 0x03
142 #define ICH6_REG_SD_LPIB 0x04
143 #define ICH6_REG_SD_CBL 0x08
144 #define ICH6_REG_SD_LVI 0x0c
145 #define ICH6_REG_SD_FIFOW 0x0e
146 #define ICH6_REG_SD_FIFOSIZE 0x10
147 #define ICH6_REG_SD_FORMAT 0x12
148 #define ICH6_REG_SD_BDLPL 0x18
149 #define ICH6_REG_SD_BDLPU 0x1c
150
151 /* PCI space */
152 #define ICH6_PCIREG_TCSEL 0x44
153
154 /*
155 * other constants
156 */
157
158 /* max number of SDs */
159 /* ICH, ATI and VIA have 4 playback and 4 capture */
160 #define ICH6_CAPTURE_INDEX 0
161 #define ICH6_NUM_CAPTURE 4
162 #define ICH6_PLAYBACK_INDEX 4
163 #define ICH6_NUM_PLAYBACK 4
164
165 /* ULI has 6 playback and 5 capture */
166 #define ULI_CAPTURE_INDEX 0
167 #define ULI_NUM_CAPTURE 5
168 #define ULI_PLAYBACK_INDEX 5
169 #define ULI_NUM_PLAYBACK 6
170
171 /* ATI HDMI has 1 playback and 0 capture */
172 #define ATIHDMI_CAPTURE_INDEX 0
173 #define ATIHDMI_NUM_CAPTURE 0
174 #define ATIHDMI_PLAYBACK_INDEX 0
175 #define ATIHDMI_NUM_PLAYBACK 1
176
177 /* this number is statically defined for simplicity */
178 #define MAX_AZX_DEV 16
179
180 /* max number of fragments - we may use more if allocating more pages for BDL */
181 #define BDL_SIZE PAGE_ALIGN(8192)
182 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
183 /* max buffer size - no h/w limit, you can increase as you like */
184 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
185 /* max number of PCM devics per card */
186 #define AZX_MAX_AUDIO_PCMS 6
187 #define AZX_MAX_MODEM_PCMS 2
188 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
189
190 /* RIRB int mask: overrun[2], response[0] */
191 #define RIRB_INT_RESPONSE 0x01
192 #define RIRB_INT_OVERRUN 0x04
193 #define RIRB_INT_MASK 0x05
194
195 /* STATESTS int mask: SD2,SD1,SD0 */
196 #define STATESTS_INT_MASK 0x07
197 #define AZX_MAX_CODECS 4
198
199 /* SD_CTL bits */
200 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
201 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
202 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
203 #define SD_CTL_STREAM_TAG_SHIFT 20
204
205 /* SD_CTL and SD_STS */
206 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
207 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
208 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
209 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
210
211 /* SD_STS */
212 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
213
214 /* INTCTL and INTSTS */
215 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
216 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
217 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
218
219 /* GCTL unsolicited response enable bit */
220 #define ICH6_GCTL_UREN (1<<8)
221
222 /* GCTL reset bit */
223 #define ICH6_GCTL_RESET (1<<0)
224
225 /* CORB/RIRB control, read/write pointer */
226 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
227 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
228 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
229 /* below are so far hardcoded - should read registers in future */
230 #define ICH6_MAX_CORB_ENTRIES 256
231 #define ICH6_MAX_RIRB_ENTRIES 256
232
233 /* position fix mode */
234 enum {
235 POS_FIX_AUTO,
236 POS_FIX_NONE,
237 POS_FIX_POSBUF,
238 POS_FIX_FIFO,
239 };
240
241 /* Defines for ATI HD Audio support in SB450 south bridge */
242 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
243 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
244
245 /* Defines for Nvidia HDA support */
246 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
247 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
248
249 /*
250 */
251
252 struct azx_dev {
253 u32 *bdl; /* virtual address of the BDL */
254 dma_addr_t bdl_addr; /* physical address of the BDL */
255 volatile u32 *posbuf; /* position buffer pointer */
256
257 unsigned int bufsize; /* size of the play buffer in bytes */
258 unsigned int fragsize; /* size of each period in bytes */
259 unsigned int frags; /* number for period in the play buffer */
260 unsigned int fifo_size; /* FIFO size */
261
262 void __iomem *sd_addr; /* stream descriptor pointer */
263
264 u32 sd_int_sta_mask; /* stream int status mask */
265
266 /* pcm support */
267 struct snd_pcm_substream *substream; /* assigned substream, set in PCM open */
268 unsigned int format_val; /* format value to be set in the controller and the codec */
269 unsigned char stream_tag; /* assigned stream */
270 unsigned char index; /* stream index */
271 /* for sanity check of position buffer */
272 unsigned int period_intr;
273
274 unsigned int opened: 1;
275 unsigned int running: 1;
276 };
277
278 /* CORB/RIRB */
279 struct azx_rb {
280 u32 *buf; /* CORB/RIRB buffer
281 * Each CORB entry is 4byte, RIRB is 8byte
282 */
283 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
284 /* for RIRB */
285 unsigned short rp, wp; /* read/write pointers */
286 int cmds; /* number of pending requests */
287 u32 res; /* last read value */
288 };
289
290 struct azx {
291 struct snd_card *card;
292 struct pci_dev *pci;
293
294 /* chip type specific */
295 int driver_type;
296 int playback_streams;
297 int playback_index_offset;
298 int capture_streams;
299 int capture_index_offset;
300 int num_streams;
301
302 /* pci resources */
303 unsigned long addr;
304 void __iomem *remap_addr;
305 int irq;
306
307 /* locks */
308 spinlock_t reg_lock;
309 struct mutex open_mutex;
310
311 /* streams (x num_streams) */
312 struct azx_dev *azx_dev;
313
314 /* PCM */
315 unsigned int pcm_devs;
316 struct snd_pcm *pcm[AZX_MAX_PCMS];
317
318 /* HD codec */
319 unsigned short codec_mask;
320 struct hda_bus *bus;
321
322 /* CORB/RIRB */
323 struct azx_rb corb;
324 struct azx_rb rirb;
325
326 /* BDL, CORB/RIRB and position buffers */
327 struct snd_dma_buffer bdl;
328 struct snd_dma_buffer rb;
329 struct snd_dma_buffer posbuf;
330
331 /* flags */
332 int position_fix;
333 unsigned int initialized: 1;
334 unsigned int single_cmd: 1;
335 unsigned int polling_mode: 1;
336 };
337
338 /* driver types */
339 enum {
340 AZX_DRIVER_ICH,
341 AZX_DRIVER_ATI,
342 AZX_DRIVER_ATIHDMI,
343 AZX_DRIVER_VIA,
344 AZX_DRIVER_SIS,
345 AZX_DRIVER_ULI,
346 AZX_DRIVER_NVIDIA,
347 };
348
349 static char *driver_short_names[] __devinitdata = {
350 [AZX_DRIVER_ICH] = "HDA Intel",
351 [AZX_DRIVER_ATI] = "HDA ATI SB",
352 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
353 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
354 [AZX_DRIVER_SIS] = "HDA SIS966",
355 [AZX_DRIVER_ULI] = "HDA ULI M5461",
356 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
357 };
358
359 /*
360 * macros for easy use
361 */
362 #define azx_writel(chip,reg,value) \
363 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
364 #define azx_readl(chip,reg) \
365 readl((chip)->remap_addr + ICH6_REG_##reg)
366 #define azx_writew(chip,reg,value) \
367 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
368 #define azx_readw(chip,reg) \
369 readw((chip)->remap_addr + ICH6_REG_##reg)
370 #define azx_writeb(chip,reg,value) \
371 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
372 #define azx_readb(chip,reg) \
373 readb((chip)->remap_addr + ICH6_REG_##reg)
374
375 #define azx_sd_writel(dev,reg,value) \
376 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
377 #define azx_sd_readl(dev,reg) \
378 readl((dev)->sd_addr + ICH6_REG_##reg)
379 #define azx_sd_writew(dev,reg,value) \
380 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
381 #define azx_sd_readw(dev,reg) \
382 readw((dev)->sd_addr + ICH6_REG_##reg)
383 #define azx_sd_writeb(dev,reg,value) \
384 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
385 #define azx_sd_readb(dev,reg) \
386 readb((dev)->sd_addr + ICH6_REG_##reg)
387
388 /* for pcm support */
389 #define get_azx_dev(substream) (substream->runtime->private_data)
390
391 /* Get the upper 32bit of the given dma_addr_t
392 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
393 */
394 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
395
396
397 /*
398 * Interface for HD codec
399 */
400
401 /*
402 * CORB / RIRB interface
403 */
404 static int azx_alloc_cmd_io(struct azx *chip)
405 {
406 int err;
407
408 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
409 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
410 PAGE_SIZE, &chip->rb);
411 if (err < 0) {
412 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
413 return err;
414 }
415 return 0;
416 }
417
418 static void azx_init_cmd_io(struct azx *chip)
419 {
420 /* CORB set up */
421 chip->corb.addr = chip->rb.addr;
422 chip->corb.buf = (u32 *)chip->rb.area;
423 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
424 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
425
426 /* set the corb size to 256 entries (ULI requires explicitly) */
427 azx_writeb(chip, CORBSIZE, 0x02);
428 /* set the corb write pointer to 0 */
429 azx_writew(chip, CORBWP, 0);
430 /* reset the corb hw read pointer */
431 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
432 /* enable corb dma */
433 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
434
435 /* RIRB set up */
436 chip->rirb.addr = chip->rb.addr + 2048;
437 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
438 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
439 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
440
441 /* set the rirb size to 256 entries (ULI requires explicitly) */
442 azx_writeb(chip, RIRBSIZE, 0x02);
443 /* reset the rirb hw write pointer */
444 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
445 /* set N=1, get RIRB response interrupt for new entry */
446 azx_writew(chip, RINTCNT, 1);
447 /* enable rirb dma and response irq */
448 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
449 chip->rirb.rp = chip->rirb.cmds = 0;
450 }
451
452 static void azx_free_cmd_io(struct azx *chip)
453 {
454 /* disable ringbuffer DMAs */
455 azx_writeb(chip, RIRBCTL, 0);
456 azx_writeb(chip, CORBCTL, 0);
457 }
458
459 /* send a command */
460 static int azx_corb_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
461 unsigned int verb, unsigned int para)
462 {
463 struct azx *chip = codec->bus->private_data;
464 unsigned int wp;
465 u32 val;
466
467 val = (u32)(codec->addr & 0x0f) << 28;
468 val |= (u32)direct << 27;
469 val |= (u32)nid << 20;
470 val |= verb << 8;
471 val |= para;
472
473 /* add command to corb */
474 wp = azx_readb(chip, CORBWP);
475 wp++;
476 wp %= ICH6_MAX_CORB_ENTRIES;
477
478 spin_lock_irq(&chip->reg_lock);
479 chip->rirb.cmds++;
480 chip->corb.buf[wp] = cpu_to_le32(val);
481 azx_writel(chip, CORBWP, wp);
482 spin_unlock_irq(&chip->reg_lock);
483
484 return 0;
485 }
486
487 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
488
489 /* retrieve RIRB entry - called from interrupt handler */
490 static void azx_update_rirb(struct azx *chip)
491 {
492 unsigned int rp, wp;
493 u32 res, res_ex;
494
495 wp = azx_readb(chip, RIRBWP);
496 if (wp == chip->rirb.wp)
497 return;
498 chip->rirb.wp = wp;
499
500 while (chip->rirb.rp != wp) {
501 chip->rirb.rp++;
502 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
503
504 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
505 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
506 res = le32_to_cpu(chip->rirb.buf[rp]);
507 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
508 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
509 else if (chip->rirb.cmds) {
510 chip->rirb.cmds--;
511 chip->rirb.res = res;
512 }
513 }
514 }
515
516 /* receive a response */
517 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
518 {
519 struct azx *chip = codec->bus->private_data;
520 int timeout = 50;
521
522 for (;;) {
523 if (chip->polling_mode) {
524 spin_lock_irq(&chip->reg_lock);
525 azx_update_rirb(chip);
526 spin_unlock_irq(&chip->reg_lock);
527 }
528 if (! chip->rirb.cmds)
529 break;
530 if (! --timeout) {
531 if (! chip->polling_mode) {
532 snd_printk(KERN_WARNING "hda_intel: "
533 "azx_get_response timeout, "
534 "switching to polling mode...\n");
535 chip->polling_mode = 1;
536 timeout = 50;
537 continue;
538 }
539 snd_printk(KERN_ERR
540 "hda_intel: azx_get_response timeout, "
541 "switching to single_cmd mode...\n");
542 chip->rirb.rp = azx_readb(chip, RIRBWP);
543 chip->rirb.cmds = 0;
544 /* switch to single_cmd mode */
545 chip->single_cmd = 1;
546 azx_free_cmd_io(chip);
547 return -1;
548 }
549 msleep(1);
550 }
551 return chip->rirb.res; /* the last value */
552 }
553
554 /*
555 * Use the single immediate command instead of CORB/RIRB for simplicity
556 *
557 * Note: according to Intel, this is not preferred use. The command was
558 * intended for the BIOS only, and may get confused with unsolicited
559 * responses. So, we shouldn't use it for normal operation from the
560 * driver.
561 * I left the codes, however, for debugging/testing purposes.
562 */
563
564 /* send a command */
565 static int azx_single_send_cmd(struct hda_codec *codec, hda_nid_t nid,
566 int direct, unsigned int verb,
567 unsigned int para)
568 {
569 struct azx *chip = codec->bus->private_data;
570 u32 val;
571 int timeout = 50;
572
573 val = (u32)(codec->addr & 0x0f) << 28;
574 val |= (u32)direct << 27;
575 val |= (u32)nid << 20;
576 val |= verb << 8;
577 val |= para;
578
579 while (timeout--) {
580 /* check ICB busy bit */
581 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
582 /* Clear IRV valid bit */
583 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
584 azx_writel(chip, IC, val);
585 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
586 return 0;
587 }
588 udelay(1);
589 }
590 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
591 return -EIO;
592 }
593
594 /* receive a response */
595 static unsigned int azx_single_get_response(struct hda_codec *codec)
596 {
597 struct azx *chip = codec->bus->private_data;
598 int timeout = 50;
599
600 while (timeout--) {
601 /* check IRV busy bit */
602 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
603 return azx_readl(chip, IR);
604 udelay(1);
605 }
606 snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
607 return (unsigned int)-1;
608 }
609
610 /*
611 * The below are the main callbacks from hda_codec.
612 *
613 * They are just the skeleton to call sub-callbacks according to the
614 * current setting of chip->single_cmd.
615 */
616
617 /* send a command */
618 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
619 int direct, unsigned int verb,
620 unsigned int para)
621 {
622 struct azx *chip = codec->bus->private_data;
623 if (chip->single_cmd)
624 return azx_single_send_cmd(codec, nid, direct, verb, para);
625 else
626 return azx_corb_send_cmd(codec, nid, direct, verb, para);
627 }
628
629 /* get a response */
630 static unsigned int azx_get_response(struct hda_codec *codec)
631 {
632 struct azx *chip = codec->bus->private_data;
633 if (chip->single_cmd)
634 return azx_single_get_response(codec);
635 else
636 return azx_rirb_get_response(codec);
637 }
638
639
640 /* reset codec link */
641 static int azx_reset(struct azx *chip)
642 {
643 int count;
644
645 /* reset controller */
646 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
647
648 count = 50;
649 while (azx_readb(chip, GCTL) && --count)
650 msleep(1);
651
652 /* delay for >= 100us for codec PLL to settle per spec
653 * Rev 0.9 section 5.5.1
654 */
655 msleep(1);
656
657 /* Bring controller out of reset */
658 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
659
660 count = 50;
661 while (! azx_readb(chip, GCTL) && --count)
662 msleep(1);
663
664 /* Brent Chartrand said to wait >= 540us for codecs to intialize */
665 msleep(1);
666
667 /* check to see if controller is ready */
668 if (! azx_readb(chip, GCTL)) {
669 snd_printd("azx_reset: controller not ready!\n");
670 return -EBUSY;
671 }
672
673 /* Accept unsolicited responses */
674 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
675
676 /* detect codecs */
677 if (! chip->codec_mask) {
678 chip->codec_mask = azx_readw(chip, STATESTS);
679 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
680 }
681
682 return 0;
683 }
684
685
686 /*
687 * Lowlevel interface
688 */
689
690 /* enable interrupts */
691 static void azx_int_enable(struct azx *chip)
692 {
693 /* enable controller CIE and GIE */
694 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
695 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
696 }
697
698 /* disable interrupts */
699 static void azx_int_disable(struct azx *chip)
700 {
701 int i;
702
703 /* disable interrupts in stream descriptor */
704 for (i = 0; i < chip->num_streams; i++) {
705 struct azx_dev *azx_dev = &chip->azx_dev[i];
706 azx_sd_writeb(azx_dev, SD_CTL,
707 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
708 }
709
710 /* disable SIE for all streams */
711 azx_writeb(chip, INTCTL, 0);
712
713 /* disable controller CIE and GIE */
714 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
715 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
716 }
717
718 /* clear interrupts */
719 static void azx_int_clear(struct azx *chip)
720 {
721 int i;
722
723 /* clear stream status */
724 for (i = 0; i < chip->num_streams; i++) {
725 struct azx_dev *azx_dev = &chip->azx_dev[i];
726 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
727 }
728
729 /* clear STATESTS */
730 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
731
732 /* clear rirb status */
733 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
734
735 /* clear int status */
736 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
737 }
738
739 /* start a stream */
740 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
741 {
742 /* enable SIE */
743 azx_writeb(chip, INTCTL,
744 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
745 /* set DMA start and interrupt mask */
746 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
747 SD_CTL_DMA_START | SD_INT_MASK);
748 }
749
750 /* stop a stream */
751 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
752 {
753 /* stop DMA */
754 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
755 ~(SD_CTL_DMA_START | SD_INT_MASK));
756 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
757 /* disable SIE */
758 azx_writeb(chip, INTCTL,
759 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
760 }
761
762
763 /*
764 * initialize the chip
765 */
766 static void azx_init_chip(struct azx *chip)
767 {
768 unsigned char reg;
769
770 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
771 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
772 * Ensuring these bits are 0 clears playback static on some HD Audio codecs
773 */
774 pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &reg);
775 pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, reg & 0xf8);
776
777 /* reset controller */
778 azx_reset(chip);
779
780 /* initialize interrupts */
781 azx_int_clear(chip);
782 azx_int_enable(chip);
783
784 /* initialize the codec command I/O */
785 if (! chip->single_cmd)
786 azx_init_cmd_io(chip);
787
788 /* program the position buffer */
789 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
790 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
791
792 switch (chip->driver_type) {
793 case AZX_DRIVER_ATI:
794 /* For ATI SB450 azalia HD audio, we need to enable snoop */
795 pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
796 &reg);
797 pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
798 (reg & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP);
799 break;
800 case AZX_DRIVER_NVIDIA:
801 /* For NVIDIA HDA, enable snoop */
802 pci_read_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, &reg);
803 pci_write_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR,
804 (reg & 0xf0) | NVIDIA_HDA_ENABLE_COHBITS);
805 break;
806 }
807 }
808
809
810 /*
811 * interrupt handler
812 */
813 static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs)
814 {
815 struct azx *chip = dev_id;
816 struct azx_dev *azx_dev;
817 u32 status;
818 int i;
819
820 spin_lock(&chip->reg_lock);
821
822 status = azx_readl(chip, INTSTS);
823 if (status == 0) {
824 spin_unlock(&chip->reg_lock);
825 return IRQ_NONE;
826 }
827
828 for (i = 0; i < chip->num_streams; i++) {
829 azx_dev = &chip->azx_dev[i];
830 if (status & azx_dev->sd_int_sta_mask) {
831 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
832 if (azx_dev->substream && azx_dev->running) {
833 azx_dev->period_intr++;
834 spin_unlock(&chip->reg_lock);
835 snd_pcm_period_elapsed(azx_dev->substream);
836 spin_lock(&chip->reg_lock);
837 }
838 }
839 }
840
841 /* clear rirb int */
842 status = azx_readb(chip, RIRBSTS);
843 if (status & RIRB_INT_MASK) {
844 if (! chip->single_cmd && (status & RIRB_INT_RESPONSE))
845 azx_update_rirb(chip);
846 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
847 }
848
849 #if 0
850 /* clear state status int */
851 if (azx_readb(chip, STATESTS) & 0x04)
852 azx_writeb(chip, STATESTS, 0x04);
853 #endif
854 spin_unlock(&chip->reg_lock);
855
856 return IRQ_HANDLED;
857 }
858
859
860 /*
861 * set up BDL entries
862 */
863 static void azx_setup_periods(struct azx_dev *azx_dev)
864 {
865 u32 *bdl = azx_dev->bdl;
866 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
867 int idx;
868
869 /* reset BDL address */
870 azx_sd_writel(azx_dev, SD_BDLPL, 0);
871 azx_sd_writel(azx_dev, SD_BDLPU, 0);
872
873 /* program the initial BDL entries */
874 for (idx = 0; idx < azx_dev->frags; idx++) {
875 unsigned int off = idx << 2; /* 4 dword step */
876 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
877 /* program the address field of the BDL entry */
878 bdl[off] = cpu_to_le32((u32)addr);
879 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
880
881 /* program the size field of the BDL entry */
882 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
883
884 /* program the IOC to enable interrupt when buffer completes */
885 bdl[off+3] = cpu_to_le32(0x01);
886 }
887 }
888
889 /*
890 * set up the SD for streaming
891 */
892 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
893 {
894 unsigned char val;
895 int timeout;
896
897 /* make sure the run bit is zero for SD */
898 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
899 /* reset stream */
900 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
901 udelay(3);
902 timeout = 300;
903 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
904 --timeout)
905 ;
906 val &= ~SD_CTL_STREAM_RESET;
907 azx_sd_writeb(azx_dev, SD_CTL, val);
908 udelay(3);
909
910 timeout = 300;
911 /* waiting for hardware to report that the stream is out of reset */
912 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
913 --timeout)
914 ;
915
916 /* program the stream_tag */
917 azx_sd_writel(azx_dev, SD_CTL,
918 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
919 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
920
921 /* program the length of samples in cyclic buffer */
922 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
923
924 /* program the stream format */
925 /* this value needs to be the same as the one programmed */
926 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
927
928 /* program the stream LVI (last valid index) of the BDL */
929 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
930
931 /* program the BDL address */
932 /* lower BDL address */
933 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
934 /* upper BDL address */
935 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
936
937 /* enable the position buffer */
938 if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
939 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
940
941 /* set the interrupt enable bits in the descriptor control register */
942 azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
943
944 return 0;
945 }
946
947
948 /*
949 * Codec initialization
950 */
951
952 static int __devinit azx_codec_create(struct azx *chip, const char *model)
953 {
954 struct hda_bus_template bus_temp;
955 int c, codecs, err;
956
957 memset(&bus_temp, 0, sizeof(bus_temp));
958 bus_temp.private_data = chip;
959 bus_temp.modelname = model;
960 bus_temp.pci = chip->pci;
961 bus_temp.ops.command = azx_send_cmd;
962 bus_temp.ops.get_response = azx_get_response;
963
964 if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
965 return err;
966
967 codecs = 0;
968 for (c = 0; c < AZX_MAX_CODECS; c++) {
969 if ((chip->codec_mask & (1 << c)) & probe_mask) {
970 err = snd_hda_codec_new(chip->bus, c, NULL);
971 if (err < 0)
972 continue;
973 codecs++;
974 }
975 }
976 if (! codecs) {
977 snd_printk(KERN_ERR SFX "no codecs initialized\n");
978 return -ENXIO;
979 }
980
981 return 0;
982 }
983
984
985 /*
986 * PCM support
987 */
988
989 /* assign a stream for the PCM */
990 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
991 {
992 int dev, i, nums;
993 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
994 dev = chip->playback_index_offset;
995 nums = chip->playback_streams;
996 } else {
997 dev = chip->capture_index_offset;
998 nums = chip->capture_streams;
999 }
1000 for (i = 0; i < nums; i++, dev++)
1001 if (! chip->azx_dev[dev].opened) {
1002 chip->azx_dev[dev].opened = 1;
1003 return &chip->azx_dev[dev];
1004 }
1005 return NULL;
1006 }
1007
1008 /* release the assigned stream */
1009 static inline void azx_release_device(struct azx_dev *azx_dev)
1010 {
1011 azx_dev->opened = 0;
1012 }
1013
1014 static struct snd_pcm_hardware azx_pcm_hw = {
1015 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1016 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1017 SNDRV_PCM_INFO_MMAP_VALID |
1018 SNDRV_PCM_INFO_PAUSE /*|*/
1019 /*SNDRV_PCM_INFO_RESUME*/),
1020 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1021 .rates = SNDRV_PCM_RATE_48000,
1022 .rate_min = 48000,
1023 .rate_max = 48000,
1024 .channels_min = 2,
1025 .channels_max = 2,
1026 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1027 .period_bytes_min = 128,
1028 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1029 .periods_min = 2,
1030 .periods_max = AZX_MAX_FRAG,
1031 .fifo_size = 0,
1032 };
1033
1034 struct azx_pcm {
1035 struct azx *chip;
1036 struct hda_codec *codec;
1037 struct hda_pcm_stream *hinfo[2];
1038 };
1039
1040 static int azx_pcm_open(struct snd_pcm_substream *substream)
1041 {
1042 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1043 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1044 struct azx *chip = apcm->chip;
1045 struct azx_dev *azx_dev;
1046 struct snd_pcm_runtime *runtime = substream->runtime;
1047 unsigned long flags;
1048 int err;
1049
1050 mutex_lock(&chip->open_mutex);
1051 azx_dev = azx_assign_device(chip, substream->stream);
1052 if (azx_dev == NULL) {
1053 mutex_unlock(&chip->open_mutex);
1054 return -EBUSY;
1055 }
1056 runtime->hw = azx_pcm_hw;
1057 runtime->hw.channels_min = hinfo->channels_min;
1058 runtime->hw.channels_max = hinfo->channels_max;
1059 runtime->hw.formats = hinfo->formats;
1060 runtime->hw.rates = hinfo->rates;
1061 snd_pcm_limit_hw_rates(runtime);
1062 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1063 if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
1064 azx_release_device(azx_dev);
1065 mutex_unlock(&chip->open_mutex);
1066 return err;
1067 }
1068 spin_lock_irqsave(&chip->reg_lock, flags);
1069 azx_dev->substream = substream;
1070 azx_dev->running = 0;
1071 spin_unlock_irqrestore(&chip->reg_lock, flags);
1072
1073 runtime->private_data = azx_dev;
1074 mutex_unlock(&chip->open_mutex);
1075 return 0;
1076 }
1077
1078 static int azx_pcm_close(struct snd_pcm_substream *substream)
1079 {
1080 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1081 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1082 struct azx *chip = apcm->chip;
1083 struct azx_dev *azx_dev = get_azx_dev(substream);
1084 unsigned long flags;
1085
1086 mutex_lock(&chip->open_mutex);
1087 spin_lock_irqsave(&chip->reg_lock, flags);
1088 azx_dev->substream = NULL;
1089 azx_dev->running = 0;
1090 spin_unlock_irqrestore(&chip->reg_lock, flags);
1091 azx_release_device(azx_dev);
1092 hinfo->ops.close(hinfo, apcm->codec, substream);
1093 mutex_unlock(&chip->open_mutex);
1094 return 0;
1095 }
1096
1097 static int azx_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params)
1098 {
1099 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1100 }
1101
1102 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1103 {
1104 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1105 struct azx_dev *azx_dev = get_azx_dev(substream);
1106 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1107
1108 /* reset BDL address */
1109 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1110 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1111 azx_sd_writel(azx_dev, SD_CTL, 0);
1112
1113 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1114
1115 return snd_pcm_lib_free_pages(substream);
1116 }
1117
1118 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1119 {
1120 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1121 struct azx *chip = apcm->chip;
1122 struct azx_dev *azx_dev = get_azx_dev(substream);
1123 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1124 struct snd_pcm_runtime *runtime = substream->runtime;
1125
1126 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1127 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1128 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1129 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1130 runtime->channels,
1131 runtime->format,
1132 hinfo->maxbps);
1133 if (! azx_dev->format_val) {
1134 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
1135 runtime->rate, runtime->channels, runtime->format);
1136 return -EINVAL;
1137 }
1138
1139 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1140 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1141 azx_setup_periods(azx_dev);
1142 azx_setup_controller(chip, azx_dev);
1143 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1144 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1145 else
1146 azx_dev->fifo_size = 0;
1147
1148 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1149 azx_dev->format_val, substream);
1150 }
1151
1152 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1153 {
1154 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1155 struct azx_dev *azx_dev = get_azx_dev(substream);
1156 struct azx *chip = apcm->chip;
1157 int err = 0;
1158
1159 spin_lock(&chip->reg_lock);
1160 switch (cmd) {
1161 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1162 case SNDRV_PCM_TRIGGER_RESUME:
1163 case SNDRV_PCM_TRIGGER_START:
1164 azx_stream_start(chip, azx_dev);
1165 azx_dev->running = 1;
1166 break;
1167 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1168 case SNDRV_PCM_TRIGGER_SUSPEND:
1169 case SNDRV_PCM_TRIGGER_STOP:
1170 azx_stream_stop(chip, azx_dev);
1171 azx_dev->running = 0;
1172 break;
1173 default:
1174 err = -EINVAL;
1175 }
1176 spin_unlock(&chip->reg_lock);
1177 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1178 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1179 cmd == SNDRV_PCM_TRIGGER_STOP) {
1180 int timeout = 5000;
1181 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1182 ;
1183 }
1184 return err;
1185 }
1186
1187 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1188 {
1189 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1190 struct azx *chip = apcm->chip;
1191 struct azx_dev *azx_dev = get_azx_dev(substream);
1192 unsigned int pos;
1193
1194 if (chip->position_fix == POS_FIX_POSBUF ||
1195 chip->position_fix == POS_FIX_AUTO) {
1196 /* use the position buffer */
1197 pos = *azx_dev->posbuf;
1198 if (chip->position_fix == POS_FIX_AUTO &&
1199 azx_dev->period_intr == 1 && ! pos) {
1200 printk(KERN_WARNING
1201 "hda-intel: Invalid position buffer, "
1202 "using LPIB read method instead.\n");
1203 chip->position_fix = POS_FIX_NONE;
1204 goto read_lpib;
1205 }
1206 } else {
1207 read_lpib:
1208 /* read LPIB */
1209 pos = azx_sd_readl(azx_dev, SD_LPIB);
1210 if (chip->position_fix == POS_FIX_FIFO)
1211 pos += azx_dev->fifo_size;
1212 }
1213 if (pos >= azx_dev->bufsize)
1214 pos = 0;
1215 return bytes_to_frames(substream->runtime, pos);
1216 }
1217
1218 static struct snd_pcm_ops azx_pcm_ops = {
1219 .open = azx_pcm_open,
1220 .close = azx_pcm_close,
1221 .ioctl = snd_pcm_lib_ioctl,
1222 .hw_params = azx_pcm_hw_params,
1223 .hw_free = azx_pcm_hw_free,
1224 .prepare = azx_pcm_prepare,
1225 .trigger = azx_pcm_trigger,
1226 .pointer = azx_pcm_pointer,
1227 };
1228
1229 static void azx_pcm_free(struct snd_pcm *pcm)
1230 {
1231 kfree(pcm->private_data);
1232 }
1233
1234 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1235 struct hda_pcm *cpcm, int pcm_dev)
1236 {
1237 int err;
1238 struct snd_pcm *pcm;
1239 struct azx_pcm *apcm;
1240
1241 snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL);
1242 snd_assert(cpcm->name, return -EINVAL);
1243
1244 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1245 cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1246 &pcm);
1247 if (err < 0)
1248 return err;
1249 strcpy(pcm->name, cpcm->name);
1250 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1251 if (apcm == NULL)
1252 return -ENOMEM;
1253 apcm->chip = chip;
1254 apcm->codec = codec;
1255 apcm->hinfo[0] = &cpcm->stream[0];
1256 apcm->hinfo[1] = &cpcm->stream[1];
1257 pcm->private_data = apcm;
1258 pcm->private_free = azx_pcm_free;
1259 if (cpcm->stream[0].substreams)
1260 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1261 if (cpcm->stream[1].substreams)
1262 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1263 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1264 snd_dma_pci_data(chip->pci),
1265 1024 * 64, 1024 * 128);
1266 chip->pcm[pcm_dev] = pcm;
1267 chip->pcm_devs = pcm_dev + 1;
1268
1269 return 0;
1270 }
1271
1272 static int __devinit azx_pcm_create(struct azx *chip)
1273 {
1274 struct list_head *p;
1275 struct hda_codec *codec;
1276 int c, err;
1277 int pcm_dev;
1278
1279 if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1280 return err;
1281
1282 /* create audio PCMs */
1283 pcm_dev = 0;
1284 list_for_each(p, &chip->bus->codec_list) {
1285 codec = list_entry(p, struct hda_codec, list);
1286 for (c = 0; c < codec->num_pcms; c++) {
1287 if (codec->pcm_info[c].is_modem)
1288 continue; /* create later */
1289 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1290 snd_printk(KERN_ERR SFX "Too many audio PCMs\n");
1291 return -EINVAL;
1292 }
1293 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1294 if (err < 0)
1295 return err;
1296 pcm_dev++;
1297 }
1298 }
1299
1300 /* create modem PCMs */
1301 pcm_dev = AZX_MAX_AUDIO_PCMS;
1302 list_for_each(p, &chip->bus->codec_list) {
1303 codec = list_entry(p, struct hda_codec, list);
1304 for (c = 0; c < codec->num_pcms; c++) {
1305 if (! codec->pcm_info[c].is_modem)
1306 continue; /* already created */
1307 if (pcm_dev >= AZX_MAX_PCMS) {
1308 snd_printk(KERN_ERR SFX "Too many modem PCMs\n");
1309 return -EINVAL;
1310 }
1311 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1312 if (err < 0)
1313 return err;
1314 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1315 pcm_dev++;
1316 }
1317 }
1318 return 0;
1319 }
1320
1321 /*
1322 * mixer creation - all stuff is implemented in hda module
1323 */
1324 static int __devinit azx_mixer_create(struct azx *chip)
1325 {
1326 return snd_hda_build_controls(chip->bus);
1327 }
1328
1329
1330 /*
1331 * initialize SD streams
1332 */
1333 static int __devinit azx_init_stream(struct azx *chip)
1334 {
1335 int i;
1336
1337 /* initialize each stream (aka device)
1338 * assign the starting bdl address to each stream (device) and initialize
1339 */
1340 for (i = 0; i < chip->num_streams; i++) {
1341 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1342 struct azx_dev *azx_dev = &chip->azx_dev[i];
1343 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1344 azx_dev->bdl_addr = chip->bdl.addr + off;
1345 azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8);
1346 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1347 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1348 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1349 azx_dev->sd_int_sta_mask = 1 << i;
1350 /* stream tag: must be non-zero and unique */
1351 azx_dev->index = i;
1352 azx_dev->stream_tag = i + 1;
1353 }
1354
1355 return 0;
1356 }
1357
1358
1359 #ifdef CONFIG_PM
1360 /*
1361 * power management
1362 */
1363 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1364 {
1365 struct snd_card *card = pci_get_drvdata(pci);
1366 struct azx *chip = card->private_data;
1367 int i;
1368
1369 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1370 for (i = 0; i < chip->pcm_devs; i++)
1371 snd_pcm_suspend_all(chip->pcm[i]);
1372 snd_hda_suspend(chip->bus, state);
1373 azx_free_cmd_io(chip);
1374 pci_disable_device(pci);
1375 pci_save_state(pci);
1376 return 0;
1377 }
1378
1379 static int azx_resume(struct pci_dev *pci)
1380 {
1381 struct snd_card *card = pci_get_drvdata(pci);
1382 struct azx *chip = card->private_data;
1383
1384 pci_restore_state(pci);
1385 pci_enable_device(pci);
1386 pci_set_master(pci);
1387 azx_init_chip(chip);
1388 snd_hda_resume(chip->bus);
1389 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1390 return 0;
1391 }
1392 #endif /* CONFIG_PM */
1393
1394
1395 /*
1396 * destructor
1397 */
1398 static int azx_free(struct azx *chip)
1399 {
1400 if (chip->initialized) {
1401 int i;
1402
1403 for (i = 0; i < chip->num_streams; i++)
1404 azx_stream_stop(chip, &chip->azx_dev[i]);
1405
1406 /* disable interrupts */
1407 azx_int_disable(chip);
1408 azx_int_clear(chip);
1409
1410 /* disable CORB/RIRB */
1411 azx_free_cmd_io(chip);
1412
1413 /* disable position buffer */
1414 azx_writel(chip, DPLBASE, 0);
1415 azx_writel(chip, DPUBASE, 0);
1416
1417 /* wait a little for interrupts to finish */
1418 msleep(1);
1419 }
1420
1421 if (chip->irq >= 0)
1422 free_irq(chip->irq, (void*)chip);
1423 if (chip->remap_addr)
1424 iounmap(chip->remap_addr);
1425
1426 if (chip->bdl.area)
1427 snd_dma_free_pages(&chip->bdl);
1428 if (chip->rb.area)
1429 snd_dma_free_pages(&chip->rb);
1430 if (chip->posbuf.area)
1431 snd_dma_free_pages(&chip->posbuf);
1432 pci_release_regions(chip->pci);
1433 pci_disable_device(chip->pci);
1434 kfree(chip->azx_dev);
1435 kfree(chip);
1436
1437 return 0;
1438 }
1439
1440 static int azx_dev_free(struct snd_device *device)
1441 {
1442 return azx_free(device->device_data);
1443 }
1444
1445 /*
1446 * constructor
1447 */
1448 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1449 int driver_type,
1450 struct azx **rchip)
1451 {
1452 struct azx *chip;
1453 int err = 0;
1454 static struct snd_device_ops ops = {
1455 .dev_free = azx_dev_free,
1456 };
1457
1458 *rchip = NULL;
1459
1460 if ((err = pci_enable_device(pci)) < 0)
1461 return err;
1462
1463 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1464
1465 if (NULL == chip) {
1466 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1467 pci_disable_device(pci);
1468 return -ENOMEM;
1469 }
1470
1471 spin_lock_init(&chip->reg_lock);
1472 mutex_init(&chip->open_mutex);
1473 chip->card = card;
1474 chip->pci = pci;
1475 chip->irq = -1;
1476 chip->driver_type = driver_type;
1477
1478 chip->position_fix = position_fix;
1479 chip->single_cmd = single_cmd;
1480
1481 #if BITS_PER_LONG != 64
1482 /* Fix up base address on ULI M5461 */
1483 if (chip->driver_type == AZX_DRIVER_ULI) {
1484 u16 tmp3;
1485 pci_read_config_word(pci, 0x40, &tmp3);
1486 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1487 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1488 }
1489 #endif
1490
1491 if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) {
1492 kfree(chip);
1493 pci_disable_device(pci);
1494 return err;
1495 }
1496
1497 chip->addr = pci_resource_start(pci,0);
1498 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1499 if (chip->remap_addr == NULL) {
1500 snd_printk(KERN_ERR SFX "ioremap error\n");
1501 err = -ENXIO;
1502 goto errout;
1503 }
1504
1505 if (request_irq(pci->irq, azx_interrupt, IRQF_DISABLED|IRQF_SHARED,
1506 "HDA Intel", (void*)chip)) {
1507 snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
1508 err = -EBUSY;
1509 goto errout;
1510 }
1511 chip->irq = pci->irq;
1512
1513 pci_set_master(pci);
1514 synchronize_irq(chip->irq);
1515
1516 switch (chip->driver_type) {
1517 case AZX_DRIVER_ULI:
1518 chip->playback_streams = ULI_NUM_PLAYBACK;
1519 chip->capture_streams = ULI_NUM_CAPTURE;
1520 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1521 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1522 break;
1523 case AZX_DRIVER_ATIHDMI:
1524 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1525 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1526 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1527 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1528 break;
1529 default:
1530 chip->playback_streams = ICH6_NUM_PLAYBACK;
1531 chip->capture_streams = ICH6_NUM_CAPTURE;
1532 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1533 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1534 break;
1535 }
1536 chip->num_streams = chip->playback_streams + chip->capture_streams;
1537 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL);
1538 if (! chip->azx_dev) {
1539 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1540 goto errout;
1541 }
1542
1543 /* allocate memory for the BDL for each stream */
1544 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1545 BDL_SIZE, &chip->bdl)) < 0) {
1546 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1547 goto errout;
1548 }
1549 /* allocate memory for the position buffer */
1550 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1551 chip->num_streams * 8, &chip->posbuf)) < 0) {
1552 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1553 goto errout;
1554 }
1555 /* allocate CORB/RIRB */
1556 if (! chip->single_cmd)
1557 if ((err = azx_alloc_cmd_io(chip)) < 0)
1558 goto errout;
1559
1560 /* initialize streams */
1561 azx_init_stream(chip);
1562
1563 /* initialize chip */
1564 azx_init_chip(chip);
1565
1566 chip->initialized = 1;
1567
1568 /* codec detection */
1569 if (! chip->codec_mask) {
1570 snd_printk(KERN_ERR SFX "no codecs found!\n");
1571 err = -ENODEV;
1572 goto errout;
1573 }
1574
1575 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1576 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1577 goto errout;
1578 }
1579
1580 strcpy(card->driver, "HDA-Intel");
1581 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1582 sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1583
1584 *rchip = chip;
1585 return 0;
1586
1587 errout:
1588 azx_free(chip);
1589 return err;
1590 }
1591
1592 static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1593 {
1594 struct snd_card *card;
1595 struct azx *chip;
1596 int err = 0;
1597
1598 card = snd_card_new(index, id, THIS_MODULE, 0);
1599 if (NULL == card) {
1600 snd_printk(KERN_ERR SFX "Error creating card!\n");
1601 return -ENOMEM;
1602 }
1603
1604 if ((err = azx_create(card, pci, pci_id->driver_data,
1605 &chip)) < 0) {
1606 snd_card_free(card);
1607 return err;
1608 }
1609 card->private_data = chip;
1610
1611 /* create codec instances */
1612 if ((err = azx_codec_create(chip, model)) < 0) {
1613 snd_card_free(card);
1614 return err;
1615 }
1616
1617 /* create PCM streams */
1618 if ((err = azx_pcm_create(chip)) < 0) {
1619 snd_card_free(card);
1620 return err;
1621 }
1622
1623 /* create mixer controls */
1624 if ((err = azx_mixer_create(chip)) < 0) {
1625 snd_card_free(card);
1626 return err;
1627 }
1628
1629 snd_card_set_dev(card, &pci->dev);
1630
1631 if ((err = snd_card_register(card)) < 0) {
1632 snd_card_free(card);
1633 return err;
1634 }
1635
1636 pci_set_drvdata(pci, card);
1637
1638 return err;
1639 }
1640
1641 static void __devexit azx_remove(struct pci_dev *pci)
1642 {
1643 snd_card_free(pci_get_drvdata(pci));
1644 pci_set_drvdata(pci, NULL);
1645 }
1646
1647 /* PCI IDs */
1648 static struct pci_device_id azx_ids[] = {
1649 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1650 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1651 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
1652 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
1653 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
1654 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
1655 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
1656 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1657 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1658 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
1659 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA 026c */
1660 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA 0371 */
1661 { 0, }
1662 };
1663 MODULE_DEVICE_TABLE(pci, azx_ids);
1664
1665 /* pci_driver definition */
1666 static struct pci_driver driver = {
1667 .name = "HDA Intel",
1668 .id_table = azx_ids,
1669 .probe = azx_probe,
1670 .remove = __devexit_p(azx_remove),
1671 #ifdef CONFIG_PM
1672 .suspend = azx_suspend,
1673 .resume = azx_resume,
1674 #endif
1675 };
1676
1677 static int __init alsa_card_azx_init(void)
1678 {
1679 return pci_register_driver(&driver);
1680 }
1681
1682 static void __exit alsa_card_azx_exit(void)
1683 {
1684 pci_unregister_driver(&driver);
1685 }
1686
1687 module_init(alsa_card_azx_init)
1688 module_exit(alsa_card_azx_exit)
Linux kernel - Deliverables
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