projects / deliverable / linux.git / blob
? search:


eb88c528e120f5dee71146c3df25f1290e202b98
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65
66
67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
70 static char *model[SNDRV_CARDS];
71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int probe_only[SNDRV_CARDS];
75 static int jackpoll_ms[SNDRV_CARDS];
76 static bool single_cmd;
77 static int enable_msi = -1;
78 #ifdef CONFIG_SND_HDA_PATCH_LOADER
79 static char *patch[SNDRV_CARDS];
80 #endif
81 #ifdef CONFIG_SND_HDA_INPUT_BEEP
82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
83 CONFIG_SND_HDA_INPUT_BEEP_MODE};
84 #endif
85
86 module_param_array(index, int, NULL, 0444);
87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
88 module_param_array(id, charp, NULL, 0444);
89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
90 module_param_array(enable, bool, NULL, 0444);
91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
92 module_param_array(model, charp, NULL, 0444);
93 MODULE_PARM_DESC(model, "Use the given board model.");
94 module_param_array(position_fix, int, NULL, 0444);
95 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
96 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
97 module_param_array(bdl_pos_adj, int, NULL, 0644);
98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
99 module_param_array(probe_mask, int, NULL, 0444);
100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
101 module_param_array(probe_only, int, NULL, 0444);
102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
103 module_param_array(jackpoll_ms, int, NULL, 0444);
104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
105 module_param(single_cmd, bool, 0444);
106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
107 "(for debugging only).");
108 module_param(enable_msi, bint, 0444);
109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
111 module_param_array(patch, charp, NULL, 0444);
112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
113 #endif
114 #ifdef CONFIG_SND_HDA_INPUT_BEEP
115 module_param_array(beep_mode, bool, NULL, 0444);
116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
117 "(0=off, 1=on) (default=1).");
118 #endif
119
120 #ifdef CONFIG_PM
121 static int param_set_xint(const char *val, const struct kernel_param *kp);
122 static struct kernel_param_ops param_ops_xint = {
123 .set = param_set_xint,
124 .get = param_get_int,
125 };
126 #define param_check_xint param_check_int
127
128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
129 module_param(power_save, xint, 0644);
130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
131 "(in second, 0 = disable).");
132
133 /* reset the HD-audio controller in power save mode.
134 * this may give more power-saving, but will take longer time to
135 * wake up.
136 */
137 static bool power_save_controller = 1;
138 module_param(power_save_controller, bool, 0644);
139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
140 #endif /* CONFIG_PM */
141
142 static int align_buffer_size = -1;
143 module_param(align_buffer_size, bint, 0644);
144 MODULE_PARM_DESC(align_buffer_size,
145 "Force buffer and period sizes to be multiple of 128 bytes.");
146
147 #ifdef CONFIG_X86
148 static bool hda_snoop = true;
149 module_param_named(snoop, hda_snoop, bool, 0444);
150 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
151 #define azx_snoop(chip) (chip)->snoop
152 #else
153 #define hda_snoop true
154 #define azx_snoop(chip) true
155 #endif
156
157
158 MODULE_LICENSE("GPL");
159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
160 "{Intel, ICH6M},"
161 "{Intel, ICH7},"
162 "{Intel, ESB2},"
163 "{Intel, ICH8},"
164 "{Intel, ICH9},"
165 "{Intel, ICH10},"
166 "{Intel, PCH},"
167 "{Intel, CPT},"
168 "{Intel, PPT},"
169 "{Intel, LPT},"
170 "{Intel, LPT_LP},"
171 "{Intel, HPT},"
172 "{Intel, PBG},"
173 "{Intel, SCH},"
174 "{ATI, SB450},"
175 "{ATI, SB600},"
176 "{ATI, RS600},"
177 "{ATI, RS690},"
178 "{ATI, RS780},"
179 "{ATI, R600},"
180 "{ATI, RV630},"
181 "{ATI, RV610},"
182 "{ATI, RV670},"
183 "{ATI, RV635},"
184 "{ATI, RV620},"
185 "{ATI, RV770},"
186 "{VIA, VT8251},"
187 "{VIA, VT8237A},"
188 "{SiS, SIS966},"
189 "{ULI, M5461}}");
190 MODULE_DESCRIPTION("Intel HDA driver");
191
192 #ifdef CONFIG_SND_VERBOSE_PRINTK
193 #define SFX /* nop */
194 #else
195 #define SFX "hda-intel "
196 #endif
197
198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
199 #ifdef CONFIG_SND_HDA_CODEC_HDMI
200 #define SUPPORT_VGA_SWITCHEROO
201 #endif
202 #endif
203
204
205 /*
206 * registers
207 */
208 #define ICH6_REG_GCAP 0x00
209 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
210 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
211 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
212 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
213 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
214 #define ICH6_REG_VMIN 0x02
215 #define ICH6_REG_VMAJ 0x03
216 #define ICH6_REG_OUTPAY 0x04
217 #define ICH6_REG_INPAY 0x06
218 #define ICH6_REG_GCTL 0x08
219 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
220 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
221 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
222 #define ICH6_REG_WAKEEN 0x0c
223 #define ICH6_REG_STATESTS 0x0e
224 #define ICH6_REG_GSTS 0x10
225 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
226 #define ICH6_REG_INTCTL 0x20
227 #define ICH6_REG_INTSTS 0x24
228 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
229 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
230 #define ICH6_REG_SSYNC 0x38
231 #define ICH6_REG_CORBLBASE 0x40
232 #define ICH6_REG_CORBUBASE 0x44
233 #define ICH6_REG_CORBWP 0x48
234 #define ICH6_REG_CORBRP 0x4a
235 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
236 #define ICH6_REG_CORBCTL 0x4c
237 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
238 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
239 #define ICH6_REG_CORBSTS 0x4d
240 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
241 #define ICH6_REG_CORBSIZE 0x4e
242
243 #define ICH6_REG_RIRBLBASE 0x50
244 #define ICH6_REG_RIRBUBASE 0x54
245 #define ICH6_REG_RIRBWP 0x58
246 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
247 #define ICH6_REG_RINTCNT 0x5a
248 #define ICH6_REG_RIRBCTL 0x5c
249 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
250 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
251 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
252 #define ICH6_REG_RIRBSTS 0x5d
253 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
254 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
255 #define ICH6_REG_RIRBSIZE 0x5e
256
257 #define ICH6_REG_IC 0x60
258 #define ICH6_REG_IR 0x64
259 #define ICH6_REG_IRS 0x68
260 #define ICH6_IRS_VALID (1<<1)
261 #define ICH6_IRS_BUSY (1<<0)
262
263 #define ICH6_REG_DPLBASE 0x70
264 #define ICH6_REG_DPUBASE 0x74
265 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
266
267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
269
270 /* stream register offsets from stream base */
271 #define ICH6_REG_SD_CTL 0x00
272 #define ICH6_REG_SD_STS 0x03
273 #define ICH6_REG_SD_LPIB 0x04
274 #define ICH6_REG_SD_CBL 0x08
275 #define ICH6_REG_SD_LVI 0x0c
276 #define ICH6_REG_SD_FIFOW 0x0e
277 #define ICH6_REG_SD_FIFOSIZE 0x10
278 #define ICH6_REG_SD_FORMAT 0x12
279 #define ICH6_REG_SD_BDLPL 0x18
280 #define ICH6_REG_SD_BDLPU 0x1c
281
282 /* PCI space */
283 #define ICH6_PCIREG_TCSEL 0x44
284
285 /*
286 * other constants
287 */
288
289 /* max number of SDs */
290 /* ICH, ATI and VIA have 4 playback and 4 capture */
291 #define ICH6_NUM_CAPTURE 4
292 #define ICH6_NUM_PLAYBACK 4
293
294 /* ULI has 6 playback and 5 capture */
295 #define ULI_NUM_CAPTURE 5
296 #define ULI_NUM_PLAYBACK 6
297
298 /* ATI HDMI has 1 playback and 0 capture */
299 #define ATIHDMI_NUM_CAPTURE 0
300 #define ATIHDMI_NUM_PLAYBACK 1
301
302 /* TERA has 4 playback and 3 capture */
303 #define TERA_NUM_CAPTURE 3
304 #define TERA_NUM_PLAYBACK 4
305
306 /* this number is statically defined for simplicity */
307 #define MAX_AZX_DEV 16
308
309 /* max number of fragments - we may use more if allocating more pages for BDL */
310 #define BDL_SIZE 4096
311 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
312 #define AZX_MAX_FRAG 32
313 /* max buffer size - no h/w limit, you can increase as you like */
314 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
315
316 /* RIRB int mask: overrun[2], response[0] */
317 #define RIRB_INT_RESPONSE 0x01
318 #define RIRB_INT_OVERRUN 0x04
319 #define RIRB_INT_MASK 0x05
320
321 /* STATESTS int mask: S3,SD2,SD1,SD0 */
322 #define AZX_MAX_CODECS 8
323 #define AZX_DEFAULT_CODECS 4
324 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
325
326 /* SD_CTL bits */
327 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
328 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
329 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
330 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
331 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
332 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
333 #define SD_CTL_STREAM_TAG_SHIFT 20
334
335 /* SD_CTL and SD_STS */
336 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
337 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
338 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
339 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
340 SD_INT_COMPLETE)
341
342 /* SD_STS */
343 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
344
345 /* INTCTL and INTSTS */
346 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
347 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
348 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
349
350 /* below are so far hardcoded - should read registers in future */
351 #define ICH6_MAX_CORB_ENTRIES 256
352 #define ICH6_MAX_RIRB_ENTRIES 256
353
354 /* position fix mode */
355 enum {
356 POS_FIX_AUTO,
357 POS_FIX_LPIB,
358 POS_FIX_POSBUF,
359 POS_FIX_VIACOMBO,
360 POS_FIX_COMBO,
361 };
362
363 /* Defines for ATI HD Audio support in SB450 south bridge */
364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
366
367 /* Defines for Nvidia HDA support */
368 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
369 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
370 #define NVIDIA_HDA_ISTRM_COH 0x4d
371 #define NVIDIA_HDA_OSTRM_COH 0x4c
372 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
373
374 /* Defines for Intel SCH HDA snoop control */
375 #define INTEL_SCH_HDA_DEVC 0x78
376 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
377
378 /* Define IN stream 0 FIFO size offset in VIA controller */
379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
380 /* Define VIA HD Audio Device ID*/
381 #define VIA_HDAC_DEVICE_ID 0x3288
382
383 /* HD Audio class code */
384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
385
386 /*
387 */
388
389 struct azx_dev {
390 struct snd_dma_buffer bdl; /* BDL buffer */
391 u32 *posbuf; /* position buffer pointer */
392
393 unsigned int bufsize; /* size of the play buffer in bytes */
394 unsigned int period_bytes; /* size of the period in bytes */
395 unsigned int frags; /* number for period in the play buffer */
396 unsigned int fifo_size; /* FIFO size */
397 unsigned long start_wallclk; /* start + minimum wallclk */
398 unsigned long period_wallclk; /* wallclk for period */
399
400 void __iomem *sd_addr; /* stream descriptor pointer */
401
402 u32 sd_int_sta_mask; /* stream int status mask */
403
404 /* pcm support */
405 struct snd_pcm_substream *substream; /* assigned substream,
406 * set in PCM open
407 */
408 unsigned int format_val; /* format value to be set in the
409 * controller and the codec
410 */
411 unsigned char stream_tag; /* assigned stream */
412 unsigned char index; /* stream index */
413 int assigned_key; /* last device# key assigned to */
414
415 unsigned int opened :1;
416 unsigned int running :1;
417 unsigned int irq_pending :1;
418 /*
419 * For VIA:
420 * A flag to ensure DMA position is 0
421 * when link position is not greater than FIFO size
422 */
423 unsigned int insufficient :1;
424 unsigned int wc_marked:1;
425 unsigned int no_period_wakeup:1;
426
427 struct timecounter azx_tc;
428 struct cyclecounter azx_cc;
429 };
430
431 /* CORB/RIRB */
432 struct azx_rb {
433 u32 *buf; /* CORB/RIRB buffer
434 * Each CORB entry is 4byte, RIRB is 8byte
435 */
436 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
437 /* for RIRB */
438 unsigned short rp, wp; /* read/write pointers */
439 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
440 u32 res[AZX_MAX_CODECS]; /* last read value */
441 };
442
443 struct azx_pcm {
444 struct azx *chip;
445 struct snd_pcm *pcm;
446 struct hda_codec *codec;
447 struct hda_pcm_stream *hinfo[2];
448 struct list_head list;
449 };
450
451 struct azx {
452 struct snd_card *card;
453 struct pci_dev *pci;
454 int dev_index;
455
456 /* chip type specific */
457 int driver_type;
458 unsigned int driver_caps;
459 int playback_streams;
460 int playback_index_offset;
461 int capture_streams;
462 int capture_index_offset;
463 int num_streams;
464
465 /* pci resources */
466 unsigned long addr;
467 void __iomem *remap_addr;
468 int irq;
469
470 /* locks */
471 spinlock_t reg_lock;
472 struct mutex open_mutex;
473 struct completion probe_wait;
474
475 /* streams (x num_streams) */
476 struct azx_dev *azx_dev;
477
478 /* PCM */
479 struct list_head pcm_list; /* azx_pcm list */
480
481 /* HD codec */
482 unsigned short codec_mask;
483 int codec_probe_mask; /* copied from probe_mask option */
484 struct hda_bus *bus;
485 unsigned int beep_mode;
486
487 /* CORB/RIRB */
488 struct azx_rb corb;
489 struct azx_rb rirb;
490
491 /* CORB/RIRB and position buffers */
492 struct snd_dma_buffer rb;
493 struct snd_dma_buffer posbuf;
494
495 #ifdef CONFIG_SND_HDA_PATCH_LOADER
496 const struct firmware *fw;
497 #endif
498
499 /* flags */
500 int position_fix[2]; /* for both playback/capture streams */
501 int poll_count;
502 unsigned int running :1;
503 unsigned int initialized :1;
504 unsigned int single_cmd :1;
505 unsigned int polling_mode :1;
506 unsigned int msi :1;
507 unsigned int irq_pending_warned :1;
508 unsigned int probing :1; /* codec probing phase */
509 unsigned int snoop:1;
510 unsigned int align_buffer_size:1;
511 unsigned int region_requested:1;
512
513 /* VGA-switcheroo setup */
514 unsigned int use_vga_switcheroo:1;
515 unsigned int vga_switcheroo_registered:1;
516 unsigned int init_failed:1; /* delayed init failed */
517 unsigned int disabled:1; /* disabled by VGA-switcher */
518
519 /* for debugging */
520 unsigned int last_cmd[AZX_MAX_CODECS];
521
522 /* for pending irqs */
523 struct work_struct irq_pending_work;
524
525 /* reboot notifier (for mysterious hangup problem at power-down) */
526 struct notifier_block reboot_notifier;
527
528 /* card list (for power_save trigger) */
529 struct list_head list;
530 };
531
532 #define CREATE_TRACE_POINTS
533 #include "hda_intel_trace.h"
534
535 /* driver types */
536 enum {
537 AZX_DRIVER_ICH,
538 AZX_DRIVER_PCH,
539 AZX_DRIVER_SCH,
540 AZX_DRIVER_ATI,
541 AZX_DRIVER_ATIHDMI,
542 AZX_DRIVER_ATIHDMI_NS,
543 AZX_DRIVER_VIA,
544 AZX_DRIVER_SIS,
545 AZX_DRIVER_ULI,
546 AZX_DRIVER_NVIDIA,
547 AZX_DRIVER_TERA,
548 AZX_DRIVER_CTX,
549 AZX_DRIVER_CTHDA,
550 AZX_DRIVER_GENERIC,
551 AZX_NUM_DRIVERS, /* keep this as last entry */
552 };
553
554 /* driver quirks (capabilities) */
555 /* bits 0-7 are used for indicating driver type */
556 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
557 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
558 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
559 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
560 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
561 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
562 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
563 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
564 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
565 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
566 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
567 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
568 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
569 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
570 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
571 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
572 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
573 #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
574
575 /* quirks for Intel PCH */
576 #define AZX_DCAPS_INTEL_PCH \
577 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
578 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME)
579
580 /* quirks for ATI SB / AMD Hudson */
581 #define AZX_DCAPS_PRESET_ATI_SB \
582 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
583 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
584
585 /* quirks for ATI/AMD HDMI */
586 #define AZX_DCAPS_PRESET_ATI_HDMI \
587 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
588
589 /* quirks for Nvidia */
590 #define AZX_DCAPS_PRESET_NVIDIA \
591 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
592 AZX_DCAPS_ALIGN_BUFSIZE)
593
594 #define AZX_DCAPS_PRESET_CTHDA \
595 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
596
597 /*
598 * VGA-switcher support
599 */
600 #ifdef SUPPORT_VGA_SWITCHEROO
601 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
602 #else
603 #define use_vga_switcheroo(chip) 0
604 #endif
605
606 static char *driver_short_names[] = {
607 [AZX_DRIVER_ICH] = "HDA Intel",
608 [AZX_DRIVER_PCH] = "HDA Intel PCH",
609 [AZX_DRIVER_SCH] = "HDA Intel MID",
610 [AZX_DRIVER_ATI] = "HDA ATI SB",
611 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
612 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
613 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
614 [AZX_DRIVER_SIS] = "HDA SIS966",
615 [AZX_DRIVER_ULI] = "HDA ULI M5461",
616 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
617 [AZX_DRIVER_TERA] = "HDA Teradici",
618 [AZX_DRIVER_CTX] = "HDA Creative",
619 [AZX_DRIVER_CTHDA] = "HDA Creative",
620 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
621 };
622
623 /*
624 * macros for easy use
625 */
626 #define azx_writel(chip,reg,value) \
627 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
628 #define azx_readl(chip,reg) \
629 readl((chip)->remap_addr + ICH6_REG_##reg)
630 #define azx_writew(chip,reg,value) \
631 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
632 #define azx_readw(chip,reg) \
633 readw((chip)->remap_addr + ICH6_REG_##reg)
634 #define azx_writeb(chip,reg,value) \
635 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
636 #define azx_readb(chip,reg) \
637 readb((chip)->remap_addr + ICH6_REG_##reg)
638
639 #define azx_sd_writel(dev,reg,value) \
640 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
641 #define azx_sd_readl(dev,reg) \
642 readl((dev)->sd_addr + ICH6_REG_##reg)
643 #define azx_sd_writew(dev,reg,value) \
644 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
645 #define azx_sd_readw(dev,reg) \
646 readw((dev)->sd_addr + ICH6_REG_##reg)
647 #define azx_sd_writeb(dev,reg,value) \
648 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
649 #define azx_sd_readb(dev,reg) \
650 readb((dev)->sd_addr + ICH6_REG_##reg)
651
652 /* for pcm support */
653 #define get_azx_dev(substream) (substream->runtime->private_data)
654
655 #ifdef CONFIG_X86
656 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
657 {
658 if (azx_snoop(chip))
659 return;
660 if (addr && size) {
661 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
662 if (on)
663 set_memory_wc((unsigned long)addr, pages);
664 else
665 set_memory_wb((unsigned long)addr, pages);
666 }
667 }
668
669 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
670 bool on)
671 {
672 __mark_pages_wc(chip, buf->area, buf->bytes, on);
673 }
674 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
675 struct snd_pcm_runtime *runtime, bool on)
676 {
677 if (azx_dev->wc_marked != on) {
678 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
679 azx_dev->wc_marked = on;
680 }
681 }
682 #else
683 /* NOP for other archs */
684 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
685 bool on)
686 {
687 }
688 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
689 struct snd_pcm_runtime *runtime, bool on)
690 {
691 }
692 #endif
693
694 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
695 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
696 /*
697 * Interface for HD codec
698 */
699
700 /*
701 * CORB / RIRB interface
702 */
703 static int azx_alloc_cmd_io(struct azx *chip)
704 {
705 int err;
706
707 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
708 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
709 snd_dma_pci_data(chip->pci),
710 PAGE_SIZE, &chip->rb);
711 if (err < 0) {
712 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
713 return err;
714 }
715 mark_pages_wc(chip, &chip->rb, true);
716 return 0;
717 }
718
719 static void azx_init_cmd_io(struct azx *chip)
720 {
721 spin_lock_irq(&chip->reg_lock);
722 /* CORB set up */
723 chip->corb.addr = chip->rb.addr;
724 chip->corb.buf = (u32 *)chip->rb.area;
725 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
726 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
727
728 /* set the corb size to 256 entries (ULI requires explicitly) */
729 azx_writeb(chip, CORBSIZE, 0x02);
730 /* set the corb write pointer to 0 */
731 azx_writew(chip, CORBWP, 0);
732 /* reset the corb hw read pointer */
733 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
734 /* enable corb dma */
735 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
736
737 /* RIRB set up */
738 chip->rirb.addr = chip->rb.addr + 2048;
739 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
740 chip->rirb.wp = chip->rirb.rp = 0;
741 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
742 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
743 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
744
745 /* set the rirb size to 256 entries (ULI requires explicitly) */
746 azx_writeb(chip, RIRBSIZE, 0x02);
747 /* reset the rirb hw write pointer */
748 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
749 /* set N=1, get RIRB response interrupt for new entry */
750 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
751 azx_writew(chip, RINTCNT, 0xc0);
752 else
753 azx_writew(chip, RINTCNT, 1);
754 /* enable rirb dma and response irq */
755 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
756 spin_unlock_irq(&chip->reg_lock);
757 }
758
759 static void azx_free_cmd_io(struct azx *chip)
760 {
761 spin_lock_irq(&chip->reg_lock);
762 /* disable ringbuffer DMAs */
763 azx_writeb(chip, RIRBCTL, 0);
764 azx_writeb(chip, CORBCTL, 0);
765 spin_unlock_irq(&chip->reg_lock);
766 }
767
768 static unsigned int azx_command_addr(u32 cmd)
769 {
770 unsigned int addr = cmd >> 28;
771
772 if (addr >= AZX_MAX_CODECS) {
773 snd_BUG();
774 addr = 0;
775 }
776
777 return addr;
778 }
779
780 static unsigned int azx_response_addr(u32 res)
781 {
782 unsigned int addr = res & 0xf;
783
784 if (addr >= AZX_MAX_CODECS) {
785 snd_BUG();
786 addr = 0;
787 }
788
789 return addr;
790 }
791
792 /* send a command */
793 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
794 {
795 struct azx *chip = bus->private_data;
796 unsigned int addr = azx_command_addr(val);
797 unsigned int wp;
798
799 spin_lock_irq(&chip->reg_lock);
800
801 /* add command to corb */
802 wp = azx_readw(chip, CORBWP);
803 if (wp == 0xffff) {
804 /* something wrong, controller likely turned to D3 */
805 spin_unlock_irq(&chip->reg_lock);
806 return -1;
807 }
808 wp++;
809 wp %= ICH6_MAX_CORB_ENTRIES;
810
811 chip->rirb.cmds[addr]++;
812 chip->corb.buf[wp] = cpu_to_le32(val);
813 azx_writel(chip, CORBWP, wp);
814
815 spin_unlock_irq(&chip->reg_lock);
816
817 return 0;
818 }
819
820 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
821
822 /* retrieve RIRB entry - called from interrupt handler */
823 static void azx_update_rirb(struct azx *chip)
824 {
825 unsigned int rp, wp;
826 unsigned int addr;
827 u32 res, res_ex;
828
829 wp = azx_readw(chip, RIRBWP);
830 if (wp == 0xffff) {
831 /* something wrong, controller likely turned to D3 */
832 return;
833 }
834
835 if (wp == chip->rirb.wp)
836 return;
837 chip->rirb.wp = wp;
838
839 while (chip->rirb.rp != wp) {
840 chip->rirb.rp++;
841 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
842
843 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
844 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
845 res = le32_to_cpu(chip->rirb.buf[rp]);
846 addr = azx_response_addr(res_ex);
847 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
848 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
849 else if (chip->rirb.cmds[addr]) {
850 chip->rirb.res[addr] = res;
851 smp_wmb();
852 chip->rirb.cmds[addr]--;
853 } else
854 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
855 "last cmd=%#08x\n",
856 pci_name(chip->pci),
857 res, res_ex,
858 chip->last_cmd[addr]);
859 }
860 }
861
862 /* receive a response */
863 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
864 unsigned int addr)
865 {
866 struct azx *chip = bus->private_data;
867 unsigned long timeout;
868 unsigned long loopcounter;
869 int do_poll = 0;
870
871 again:
872 timeout = jiffies + msecs_to_jiffies(1000);
873
874 for (loopcounter = 0;; loopcounter++) {
875 if (chip->polling_mode || do_poll) {
876 spin_lock_irq(&chip->reg_lock);
877 azx_update_rirb(chip);
878 spin_unlock_irq(&chip->reg_lock);
879 }
880 if (!chip->rirb.cmds[addr]) {
881 smp_rmb();
882 bus->rirb_error = 0;
883
884 if (!do_poll)
885 chip->poll_count = 0;
886 return chip->rirb.res[addr]; /* the last value */
887 }
888 if (time_after(jiffies, timeout))
889 break;
890 if (bus->needs_damn_long_delay || loopcounter > 3000)
891 msleep(2); /* temporary workaround */
892 else {
893 udelay(10);
894 cond_resched();
895 }
896 }
897
898 if (!chip->polling_mode && chip->poll_count < 2) {
899 snd_printdd(SFX "%s: azx_get_response timeout, "
900 "polling the codec once: last cmd=0x%08x\n",
901 pci_name(chip->pci), chip->last_cmd[addr]);
902 do_poll = 1;
903 chip->poll_count++;
904 goto again;
905 }
906
907
908 if (!chip->polling_mode) {
909 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
910 "switching to polling mode: last cmd=0x%08x\n",
911 pci_name(chip->pci), chip->last_cmd[addr]);
912 chip->polling_mode = 1;
913 goto again;
914 }
915
916 if (chip->msi) {
917 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
918 "disabling MSI: last cmd=0x%08x\n",
919 pci_name(chip->pci), chip->last_cmd[addr]);
920 free_irq(chip->irq, chip);
921 chip->irq = -1;
922 pci_disable_msi(chip->pci);
923 chip->msi = 0;
924 if (azx_acquire_irq(chip, 1) < 0) {
925 bus->rirb_error = 1;
926 return -1;
927 }
928 goto again;
929 }
930
931 if (chip->probing) {
932 /* If this critical timeout happens during the codec probing
933 * phase, this is likely an access to a non-existing codec
934 * slot. Better to return an error and reset the system.
935 */
936 return -1;
937 }
938
939 /* a fatal communication error; need either to reset or to fallback
940 * to the single_cmd mode
941 */
942 bus->rirb_error = 1;
943 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
944 bus->response_reset = 1;
945 return -1; /* give a chance to retry */
946 }
947
948 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
949 "switching to single_cmd mode: last cmd=0x%08x\n",
950 chip->last_cmd[addr]);
951 chip->single_cmd = 1;
952 bus->response_reset = 0;
953 /* release CORB/RIRB */
954 azx_free_cmd_io(chip);
955 /* disable unsolicited responses */
956 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
957 return -1;
958 }
959
960 /*
961 * Use the single immediate command instead of CORB/RIRB for simplicity
962 *
963 * Note: according to Intel, this is not preferred use. The command was
964 * intended for the BIOS only, and may get confused with unsolicited
965 * responses. So, we shouldn't use it for normal operation from the
966 * driver.
967 * I left the codes, however, for debugging/testing purposes.
968 */
969
970 /* receive a response */
971 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
972 {
973 int timeout = 50;
974
975 while (timeout--) {
976 /* check IRV busy bit */
977 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
978 /* reuse rirb.res as the response return value */
979 chip->rirb.res[addr] = azx_readl(chip, IR);
980 return 0;
981 }
982 udelay(1);
983 }
984 if (printk_ratelimit())
985 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
986 pci_name(chip->pci), azx_readw(chip, IRS));
987 chip->rirb.res[addr] = -1;
988 return -EIO;
989 }
990
991 /* send a command */
992 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
993 {
994 struct azx *chip = bus->private_data;
995 unsigned int addr = azx_command_addr(val);
996 int timeout = 50;
997
998 bus->rirb_error = 0;
999 while (timeout--) {
1000 /* check ICB busy bit */
1001 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1002 /* Clear IRV valid bit */
1003 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1004 ICH6_IRS_VALID);
1005 azx_writel(chip, IC, val);
1006 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1007 ICH6_IRS_BUSY);
1008 return azx_single_wait_for_response(chip, addr);
1009 }
1010 udelay(1);
1011 }
1012 if (printk_ratelimit())
1013 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1014 pci_name(chip->pci), azx_readw(chip, IRS), val);
1015 return -EIO;
1016 }
1017
1018 /* receive a response */
1019 static unsigned int azx_single_get_response(struct hda_bus *bus,
1020 unsigned int addr)
1021 {
1022 struct azx *chip = bus->private_data;
1023 return chip->rirb.res[addr];
1024 }
1025
1026 /*
1027 * The below are the main callbacks from hda_codec.
1028 *
1029 * They are just the skeleton to call sub-callbacks according to the
1030 * current setting of chip->single_cmd.
1031 */
1032
1033 /* send a command */
1034 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1035 {
1036 struct azx *chip = bus->private_data;
1037
1038 if (chip->disabled)
1039 return 0;
1040 chip->last_cmd[azx_command_addr(val)] = val;
1041 if (chip->single_cmd)
1042 return azx_single_send_cmd(bus, val);
1043 else
1044 return azx_corb_send_cmd(bus, val);
1045 }
1046
1047 /* get a response */
1048 static unsigned int azx_get_response(struct hda_bus *bus,
1049 unsigned int addr)
1050 {
1051 struct azx *chip = bus->private_data;
1052 if (chip->disabled)
1053 return 0;
1054 if (chip->single_cmd)
1055 return azx_single_get_response(bus, addr);
1056 else
1057 return azx_rirb_get_response(bus, addr);
1058 }
1059
1060 #ifdef CONFIG_PM
1061 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1062 #endif
1063
1064 /* reset codec link */
1065 static int azx_reset(struct azx *chip, int full_reset)
1066 {
1067 unsigned long timeout;
1068
1069 if (!full_reset)
1070 goto __skip;
1071
1072 /* clear STATESTS */
1073 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1074
1075 /* reset controller */
1076 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1077
1078 timeout = jiffies + msecs_to_jiffies(100);
1079 while (azx_readb(chip, GCTL) &&
1080 time_before(jiffies, timeout))
1081 usleep_range(500, 1000);
1082
1083 /* delay for >= 100us for codec PLL to settle per spec
1084 * Rev 0.9 section 5.5.1
1085 */
1086 usleep_range(500, 1000);
1087
1088 /* Bring controller out of reset */
1089 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1090
1091 timeout = jiffies + msecs_to_jiffies(100);
1092 while (!azx_readb(chip, GCTL) &&
1093 time_before(jiffies, timeout))
1094 usleep_range(500, 1000);
1095
1096 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1097 usleep_range(1000, 1200);
1098
1099 __skip:
1100 /* check to see if controller is ready */
1101 if (!azx_readb(chip, GCTL)) {
1102 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1103 return -EBUSY;
1104 }
1105
1106 /* Accept unsolicited responses */
1107 if (!chip->single_cmd)
1108 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1109 ICH6_GCTL_UNSOL);
1110
1111 /* detect codecs */
1112 if (!chip->codec_mask) {
1113 chip->codec_mask = azx_readw(chip, STATESTS);
1114 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1115 }
1116
1117 return 0;
1118 }
1119
1120
1121 /*
1122 * Lowlevel interface
1123 */
1124
1125 /* enable interrupts */
1126 static void azx_int_enable(struct azx *chip)
1127 {
1128 /* enable controller CIE and GIE */
1129 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1130 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1131 }
1132
1133 /* disable interrupts */
1134 static void azx_int_disable(struct azx *chip)
1135 {
1136 int i;
1137
1138 /* disable interrupts in stream descriptor */
1139 for (i = 0; i < chip->num_streams; i++) {
1140 struct azx_dev *azx_dev = &chip->azx_dev[i];
1141 azx_sd_writeb(azx_dev, SD_CTL,
1142 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1143 }
1144
1145 /* disable SIE for all streams */
1146 azx_writeb(chip, INTCTL, 0);
1147
1148 /* disable controller CIE and GIE */
1149 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1150 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1151 }
1152
1153 /* clear interrupts */
1154 static void azx_int_clear(struct azx *chip)
1155 {
1156 int i;
1157
1158 /* clear stream status */
1159 for (i = 0; i < chip->num_streams; i++) {
1160 struct azx_dev *azx_dev = &chip->azx_dev[i];
1161 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1162 }
1163
1164 /* clear STATESTS */
1165 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1166
1167 /* clear rirb status */
1168 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1169
1170 /* clear int status */
1171 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1172 }
1173
1174 /* start a stream */
1175 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1176 {
1177 /*
1178 * Before stream start, initialize parameter
1179 */
1180 azx_dev->insufficient = 1;
1181
1182 /* enable SIE */
1183 azx_writel(chip, INTCTL,
1184 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1185 /* set DMA start and interrupt mask */
1186 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1187 SD_CTL_DMA_START | SD_INT_MASK);
1188 }
1189
1190 /* stop DMA */
1191 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1192 {
1193 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1194 ~(SD_CTL_DMA_START | SD_INT_MASK));
1195 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1196 }
1197
1198 /* stop a stream */
1199 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1200 {
1201 azx_stream_clear(chip, azx_dev);
1202 /* disable SIE */
1203 azx_writel(chip, INTCTL,
1204 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1205 }
1206
1207
1208 /*
1209 * reset and start the controller registers
1210 */
1211 static void azx_init_chip(struct azx *chip, int full_reset)
1212 {
1213 if (chip->initialized)
1214 return;
1215
1216 /* reset controller */
1217 azx_reset(chip, full_reset);
1218
1219 /* initialize interrupts */
1220 azx_int_clear(chip);
1221 azx_int_enable(chip);
1222
1223 /* initialize the codec command I/O */
1224 if (!chip->single_cmd)
1225 azx_init_cmd_io(chip);
1226
1227 /* program the position buffer */
1228 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1229 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1230
1231 chip->initialized = 1;
1232 }
1233
1234 /*
1235 * initialize the PCI registers
1236 */
1237 /* update bits in a PCI register byte */
1238 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1239 unsigned char mask, unsigned char val)
1240 {
1241 unsigned char data;
1242
1243 pci_read_config_byte(pci, reg, &data);
1244 data &= ~mask;
1245 data |= (val & mask);
1246 pci_write_config_byte(pci, reg, data);
1247 }
1248
1249 static void azx_init_pci(struct azx *chip)
1250 {
1251 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1252 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1253 * Ensuring these bits are 0 clears playback static on some HD Audio
1254 * codecs.
1255 * The PCI register TCSEL is defined in the Intel manuals.
1256 */
1257 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1258 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1259 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1260 }
1261
1262 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1263 * we need to enable snoop.
1264 */
1265 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1266 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1267 update_pci_byte(chip->pci,
1268 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1269 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1270 }
1271
1272 /* For NVIDIA HDA, enable snoop */
1273 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1274 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1275 update_pci_byte(chip->pci,
1276 NVIDIA_HDA_TRANSREG_ADDR,
1277 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1278 update_pci_byte(chip->pci,
1279 NVIDIA_HDA_ISTRM_COH,
1280 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1281 update_pci_byte(chip->pci,
1282 NVIDIA_HDA_OSTRM_COH,
1283 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1284 }
1285
1286 /* Enable SCH/PCH snoop if needed */
1287 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1288 unsigned short snoop;
1289 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1290 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1291 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1292 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1293 if (!azx_snoop(chip))
1294 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1295 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1296 pci_read_config_word(chip->pci,
1297 INTEL_SCH_HDA_DEVC, &snoop);
1298 }
1299 snd_printdd(SFX "%s: SCH snoop: %s\n",
1300 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1301 ? "Disabled" : "Enabled");
1302 }
1303 }
1304
1305
1306 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1307
1308 /*
1309 * interrupt handler
1310 */
1311 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1312 {
1313 struct azx *chip = dev_id;
1314 struct azx_dev *azx_dev;
1315 u32 status;
1316 u8 sd_status;
1317 int i, ok;
1318
1319 #ifdef CONFIG_PM_RUNTIME
1320 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1321 return IRQ_NONE;
1322 #endif
1323
1324 spin_lock(&chip->reg_lock);
1325
1326 if (chip->disabled) {
1327 spin_unlock(&chip->reg_lock);
1328 return IRQ_NONE;
1329 }
1330
1331 status = azx_readl(chip, INTSTS);
1332 if (status == 0) {
1333 spin_unlock(&chip->reg_lock);
1334 return IRQ_NONE;
1335 }
1336
1337 for (i = 0; i < chip->num_streams; i++) {
1338 azx_dev = &chip->azx_dev[i];
1339 if (status & azx_dev->sd_int_sta_mask) {
1340 sd_status = azx_sd_readb(azx_dev, SD_STS);
1341 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1342 if (!azx_dev->substream || !azx_dev->running ||
1343 !(sd_status & SD_INT_COMPLETE))
1344 continue;
1345 /* check whether this IRQ is really acceptable */
1346 ok = azx_position_ok(chip, azx_dev);
1347 if (ok == 1) {
1348 azx_dev->irq_pending = 0;
1349 spin_unlock(&chip->reg_lock);
1350 snd_pcm_period_elapsed(azx_dev->substream);
1351 spin_lock(&chip->reg_lock);
1352 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1353 /* bogus IRQ, process it later */
1354 azx_dev->irq_pending = 1;
1355 queue_work(chip->bus->workq,
1356 &chip->irq_pending_work);
1357 }
1358 }
1359 }
1360
1361 /* clear rirb int */
1362 status = azx_readb(chip, RIRBSTS);
1363 if (status & RIRB_INT_MASK) {
1364 if (status & RIRB_INT_RESPONSE) {
1365 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1366 udelay(80);
1367 azx_update_rirb(chip);
1368 }
1369 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1370 }
1371
1372 #if 0
1373 /* clear state status int */
1374 if (azx_readb(chip, STATESTS) & 0x04)
1375 azx_writeb(chip, STATESTS, 0x04);
1376 #endif
1377 spin_unlock(&chip->reg_lock);
1378
1379 return IRQ_HANDLED;
1380 }
1381
1382
1383 /*
1384 * set up a BDL entry
1385 */
1386 static int setup_bdle(struct azx *chip,
1387 struct snd_pcm_substream *substream,
1388 struct azx_dev *azx_dev, u32 **bdlp,
1389 int ofs, int size, int with_ioc)
1390 {
1391 u32 *bdl = *bdlp;
1392
1393 while (size > 0) {
1394 dma_addr_t addr;
1395 int chunk;
1396
1397 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1398 return -EINVAL;
1399
1400 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1401 /* program the address field of the BDL entry */
1402 bdl[0] = cpu_to_le32((u32)addr);
1403 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1404 /* program the size field of the BDL entry */
1405 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1406 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1407 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1408 u32 remain = 0x1000 - (ofs & 0xfff);
1409 if (chunk > remain)
1410 chunk = remain;
1411 }
1412 bdl[2] = cpu_to_le32(chunk);
1413 /* program the IOC to enable interrupt
1414 * only when the whole fragment is processed
1415 */
1416 size -= chunk;
1417 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1418 bdl += 4;
1419 azx_dev->frags++;
1420 ofs += chunk;
1421 }
1422 *bdlp = bdl;
1423 return ofs;
1424 }
1425
1426 /*
1427 * set up BDL entries
1428 */
1429 static int azx_setup_periods(struct azx *chip,
1430 struct snd_pcm_substream *substream,
1431 struct azx_dev *azx_dev)
1432 {
1433 u32 *bdl;
1434 int i, ofs, periods, period_bytes;
1435 int pos_adj;
1436
1437 /* reset BDL address */
1438 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1439 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1440
1441 period_bytes = azx_dev->period_bytes;
1442 periods = azx_dev->bufsize / period_bytes;
1443
1444 /* program the initial BDL entries */
1445 bdl = (u32 *)azx_dev->bdl.area;
1446 ofs = 0;
1447 azx_dev->frags = 0;
1448 pos_adj = bdl_pos_adj[chip->dev_index];
1449 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1450 struct snd_pcm_runtime *runtime = substream->runtime;
1451 int pos_align = pos_adj;
1452 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1453 if (!pos_adj)
1454 pos_adj = pos_align;
1455 else
1456 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1457 pos_align;
1458 pos_adj = frames_to_bytes(runtime, pos_adj);
1459 if (pos_adj >= period_bytes) {
1460 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1461 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1462 pos_adj = 0;
1463 } else {
1464 ofs = setup_bdle(chip, substream, azx_dev,
1465 &bdl, ofs, pos_adj, true);
1466 if (ofs < 0)
1467 goto error;
1468 }
1469 } else
1470 pos_adj = 0;
1471 for (i = 0; i < periods; i++) {
1472 if (i == periods - 1 && pos_adj)
1473 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1474 period_bytes - pos_adj, 0);
1475 else
1476 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1477 period_bytes,
1478 !azx_dev->no_period_wakeup);
1479 if (ofs < 0)
1480 goto error;
1481 }
1482 return 0;
1483
1484 error:
1485 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1486 pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1487 return -EINVAL;
1488 }
1489
1490 /* reset stream */
1491 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1492 {
1493 unsigned char val;
1494 int timeout;
1495
1496 azx_stream_clear(chip, azx_dev);
1497
1498 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1499 SD_CTL_STREAM_RESET);
1500 udelay(3);
1501 timeout = 300;
1502 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1503 --timeout)
1504 ;
1505 val &= ~SD_CTL_STREAM_RESET;
1506 azx_sd_writeb(azx_dev, SD_CTL, val);
1507 udelay(3);
1508
1509 timeout = 300;
1510 /* waiting for hardware to report that the stream is out of reset */
1511 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1512 --timeout)
1513 ;
1514
1515 /* reset first position - may not be synced with hw at this time */
1516 *azx_dev->posbuf = 0;
1517 }
1518
1519 /*
1520 * set up the SD for streaming
1521 */
1522 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1523 {
1524 unsigned int val;
1525 /* make sure the run bit is zero for SD */
1526 azx_stream_clear(chip, azx_dev);
1527 /* program the stream_tag */
1528 val = azx_sd_readl(azx_dev, SD_CTL);
1529 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1530 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1531 if (!azx_snoop(chip))
1532 val |= SD_CTL_TRAFFIC_PRIO;
1533 azx_sd_writel(azx_dev, SD_CTL, val);
1534
1535 /* program the length of samples in cyclic buffer */
1536 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1537
1538 /* program the stream format */
1539 /* this value needs to be the same as the one programmed */
1540 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1541
1542 /* program the stream LVI (last valid index) of the BDL */
1543 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1544
1545 /* program the BDL address */
1546 /* lower BDL address */
1547 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1548 /* upper BDL address */
1549 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1550
1551 /* enable the position buffer */
1552 if (chip->position_fix[0] != POS_FIX_LPIB ||
1553 chip->position_fix[1] != POS_FIX_LPIB) {
1554 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1555 azx_writel(chip, DPLBASE,
1556 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1557 }
1558
1559 /* set the interrupt enable bits in the descriptor control register */
1560 azx_sd_writel(azx_dev, SD_CTL,
1561 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1562
1563 return 0;
1564 }
1565
1566 /*
1567 * Probe the given codec address
1568 */
1569 static int probe_codec(struct azx *chip, int addr)
1570 {
1571 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1572 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1573 unsigned int res;
1574
1575 mutex_lock(&chip->bus->cmd_mutex);
1576 chip->probing = 1;
1577 azx_send_cmd(chip->bus, cmd);
1578 res = azx_get_response(chip->bus, addr);
1579 chip->probing = 0;
1580 mutex_unlock(&chip->bus->cmd_mutex);
1581 if (res == -1)
1582 return -EIO;
1583 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1584 return 0;
1585 }
1586
1587 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1588 struct hda_pcm *cpcm);
1589 static void azx_stop_chip(struct azx *chip);
1590
1591 static void azx_bus_reset(struct hda_bus *bus)
1592 {
1593 struct azx *chip = bus->private_data;
1594
1595 bus->in_reset = 1;
1596 azx_stop_chip(chip);
1597 azx_init_chip(chip, 1);
1598 #ifdef CONFIG_PM
1599 if (chip->initialized) {
1600 struct azx_pcm *p;
1601 list_for_each_entry(p, &chip->pcm_list, list)
1602 snd_pcm_suspend_all(p->pcm);
1603 snd_hda_suspend(chip->bus);
1604 snd_hda_resume(chip->bus);
1605 }
1606 #endif
1607 bus->in_reset = 0;
1608 }
1609
1610 static int get_jackpoll_interval(struct azx *chip)
1611 {
1612 int i = jackpoll_ms[chip->dev_index];
1613 unsigned int j;
1614 if (i == 0)
1615 return 0;
1616 if (i < 50 || i > 60000)
1617 j = 0;
1618 else
1619 j = msecs_to_jiffies(i);
1620 if (j == 0)
1621 snd_printk(KERN_WARNING SFX
1622 "jackpoll_ms value out of range: %d\n", i);
1623 return j;
1624 }
1625
1626 /*
1627 * Codec initialization
1628 */
1629
1630 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1631 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1632 [AZX_DRIVER_NVIDIA] = 8,
1633 [AZX_DRIVER_TERA] = 1,
1634 };
1635
1636 static int azx_codec_create(struct azx *chip, const char *model)
1637 {
1638 struct hda_bus_template bus_temp;
1639 int c, codecs, err;
1640 int max_slots;
1641
1642 memset(&bus_temp, 0, sizeof(bus_temp));
1643 bus_temp.private_data = chip;
1644 bus_temp.modelname = model;
1645 bus_temp.pci = chip->pci;
1646 bus_temp.ops.command = azx_send_cmd;
1647 bus_temp.ops.get_response = azx_get_response;
1648 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1649 bus_temp.ops.bus_reset = azx_bus_reset;
1650 #ifdef CONFIG_PM
1651 bus_temp.power_save = &power_save;
1652 bus_temp.ops.pm_notify = azx_power_notify;
1653 #endif
1654
1655 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1656 if (err < 0)
1657 return err;
1658
1659 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1660 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1661 chip->bus->needs_damn_long_delay = 1;
1662 }
1663
1664 codecs = 0;
1665 max_slots = azx_max_codecs[chip->driver_type];
1666 if (!max_slots)
1667 max_slots = AZX_DEFAULT_CODECS;
1668
1669 /* First try to probe all given codec slots */
1670 for (c = 0; c < max_slots; c++) {
1671 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1672 if (probe_codec(chip, c) < 0) {
1673 /* Some BIOSen give you wrong codec addresses
1674 * that don't exist
1675 */
1676 snd_printk(KERN_WARNING SFX
1677 "%s: Codec #%d probe error; "
1678 "disabling it...\n", pci_name(chip->pci), c);
1679 chip->codec_mask &= ~(1 << c);
1680 /* More badly, accessing to a non-existing
1681 * codec often screws up the controller chip,
1682 * and disturbs the further communications.
1683 * Thus if an error occurs during probing,
1684 * better to reset the controller chip to
1685 * get back to the sanity state.
1686 */
1687 azx_stop_chip(chip);
1688 azx_init_chip(chip, 1);
1689 }
1690 }
1691 }
1692
1693 /* AMD chipsets often cause the communication stalls upon certain
1694 * sequence like the pin-detection. It seems that forcing the synced
1695 * access works around the stall. Grrr...
1696 */
1697 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1698 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1699 pci_name(chip->pci));
1700 chip->bus->sync_write = 1;
1701 chip->bus->allow_bus_reset = 1;
1702 }
1703
1704 /* Then create codec instances */
1705 for (c = 0; c < max_slots; c++) {
1706 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1707 struct hda_codec *codec;
1708 err = snd_hda_codec_new(chip->bus, c, &codec);
1709 if (err < 0)
1710 continue;
1711 codec->jackpoll_interval = get_jackpoll_interval(chip);
1712 codec->beep_mode = chip->beep_mode;
1713 codecs++;
1714 }
1715 }
1716 if (!codecs) {
1717 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1718 return -ENXIO;
1719 }
1720 return 0;
1721 }
1722
1723 /* configure each codec instance */
1724 static int azx_codec_configure(struct azx *chip)
1725 {
1726 struct hda_codec *codec;
1727 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1728 snd_hda_codec_configure(codec);
1729 }
1730 return 0;
1731 }
1732
1733
1734 /*
1735 * PCM support
1736 */
1737
1738 /* assign a stream for the PCM */
1739 static inline struct azx_dev *
1740 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1741 {
1742 int dev, i, nums;
1743 struct azx_dev *res = NULL;
1744 /* make a non-zero unique key for the substream */
1745 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1746 (substream->stream + 1);
1747
1748 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1749 dev = chip->playback_index_offset;
1750 nums = chip->playback_streams;
1751 } else {
1752 dev = chip->capture_index_offset;
1753 nums = chip->capture_streams;
1754 }
1755 for (i = 0; i < nums; i++, dev++)
1756 if (!chip->azx_dev[dev].opened) {
1757 res = &chip->azx_dev[dev];
1758 if (res->assigned_key == key)
1759 break;
1760 }
1761 if (res) {
1762 res->opened = 1;
1763 res->assigned_key = key;
1764 }
1765 return res;
1766 }
1767
1768 /* release the assigned stream */
1769 static inline void azx_release_device(struct azx_dev *azx_dev)
1770 {
1771 azx_dev->opened = 0;
1772 }
1773
1774 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1775 {
1776 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1777 struct snd_pcm_substream *substream = azx_dev->substream;
1778 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1779 struct azx *chip = apcm->chip;
1780
1781 return azx_readl(chip, WALLCLK);
1782 }
1783
1784 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1785 bool force, cycle_t last)
1786 {
1787 struct azx_dev *azx_dev = get_azx_dev(substream);
1788 struct timecounter *tc = &azx_dev->azx_tc;
1789 struct cyclecounter *cc = &azx_dev->azx_cc;
1790 u64 nsec;
1791
1792 cc->read = azx_cc_read;
1793 cc->mask = CLOCKSOURCE_MASK(32);
1794
1795 /*
1796 * Converting from 24 MHz to ns means applying a 125/3 factor.
1797 * To avoid any saturation issues in intermediate operations,
1798 * the 125 factor is applied first. The division is applied
1799 * last after reading the timecounter value.
1800 * Applying the 1/3 factor as part of the multiplication
1801 * requires at least 20 bits for a decent precision, however
1802 * overflows occur after about 4 hours or less, not a option.
1803 */
1804
1805 cc->mult = 125; /* saturation after 195 years */
1806 cc->shift = 0;
1807
1808 nsec = 0; /* audio time is elapsed time since trigger */
1809 timecounter_init(tc, cc, nsec);
1810 if (force)
1811 /*
1812 * force timecounter to use predefined value,
1813 * used for synchronized starts
1814 */
1815 tc->cycle_last = last;
1816 }
1817
1818 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1819 struct timespec *ts)
1820 {
1821 struct azx_dev *azx_dev = get_azx_dev(substream);
1822 u64 nsec;
1823
1824 nsec = timecounter_read(&azx_dev->azx_tc);
1825 nsec = div_u64(nsec, 3); /* can be optimized */
1826
1827 *ts = ns_to_timespec(nsec);
1828
1829 return 0;
1830 }
1831
1832 static struct snd_pcm_hardware azx_pcm_hw = {
1833 .info = (SNDRV_PCM_INFO_MMAP |
1834 SNDRV_PCM_INFO_INTERLEAVED |
1835 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1836 SNDRV_PCM_INFO_MMAP_VALID |
1837 /* No full-resume yet implemented */
1838 /* SNDRV_PCM_INFO_RESUME |*/
1839 SNDRV_PCM_INFO_PAUSE |
1840 SNDRV_PCM_INFO_SYNC_START |
1841 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1842 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1843 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1844 .rates = SNDRV_PCM_RATE_48000,
1845 .rate_min = 48000,
1846 .rate_max = 48000,
1847 .channels_min = 2,
1848 .channels_max = 2,
1849 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1850 .period_bytes_min = 128,
1851 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1852 .periods_min = 2,
1853 .periods_max = AZX_MAX_FRAG,
1854 .fifo_size = 0,
1855 };
1856
1857 static int azx_pcm_open(struct snd_pcm_substream *substream)
1858 {
1859 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1860 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1861 struct azx *chip = apcm->chip;
1862 struct azx_dev *azx_dev;
1863 struct snd_pcm_runtime *runtime = substream->runtime;
1864 unsigned long flags;
1865 int err;
1866 int buff_step;
1867
1868 mutex_lock(&chip->open_mutex);
1869 azx_dev = azx_assign_device(chip, substream);
1870 if (azx_dev == NULL) {
1871 mutex_unlock(&chip->open_mutex);
1872 return -EBUSY;
1873 }
1874 runtime->hw = azx_pcm_hw;
1875 runtime->hw.channels_min = hinfo->channels_min;
1876 runtime->hw.channels_max = hinfo->channels_max;
1877 runtime->hw.formats = hinfo->formats;
1878 runtime->hw.rates = hinfo->rates;
1879 snd_pcm_limit_hw_rates(runtime);
1880 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1881
1882 /* avoid wrap-around with wall-clock */
1883 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1884 20,
1885 178000000);
1886
1887 if (chip->align_buffer_size)
1888 /* constrain buffer sizes to be multiple of 128
1889 bytes. This is more efficient in terms of memory
1890 access but isn't required by the HDA spec and
1891 prevents users from specifying exact period/buffer
1892 sizes. For example for 44.1kHz, a period size set
1893 to 20ms will be rounded to 19.59ms. */
1894 buff_step = 128;
1895 else
1896 /* Don't enforce steps on buffer sizes, still need to
1897 be multiple of 4 bytes (HDA spec). Tested on Intel
1898 HDA controllers, may not work on all devices where
1899 option needs to be disabled */
1900 buff_step = 4;
1901
1902 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1903 buff_step);
1904 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1905 buff_step);
1906 snd_hda_power_up_d3wait(apcm->codec);
1907 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1908 if (err < 0) {
1909 azx_release_device(azx_dev);
1910 snd_hda_power_down(apcm->codec);
1911 mutex_unlock(&chip->open_mutex);
1912 return err;
1913 }
1914 snd_pcm_limit_hw_rates(runtime);
1915 /* sanity check */
1916 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1917 snd_BUG_ON(!runtime->hw.channels_max) ||
1918 snd_BUG_ON(!runtime->hw.formats) ||
1919 snd_BUG_ON(!runtime->hw.rates)) {
1920 azx_release_device(azx_dev);
1921 hinfo->ops.close(hinfo, apcm->codec, substream);
1922 snd_hda_power_down(apcm->codec);
1923 mutex_unlock(&chip->open_mutex);
1924 return -EINVAL;
1925 }
1926
1927 /* disable WALLCLOCK timestamps for capture streams
1928 until we figure out how to handle digital inputs */
1929 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1930 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1931
1932 spin_lock_irqsave(&chip->reg_lock, flags);
1933 azx_dev->substream = substream;
1934 azx_dev->running = 0;
1935 spin_unlock_irqrestore(&chip->reg_lock, flags);
1936
1937 runtime->private_data = azx_dev;
1938 snd_pcm_set_sync(substream);
1939 mutex_unlock(&chip->open_mutex);
1940 return 0;
1941 }
1942
1943 static int azx_pcm_close(struct snd_pcm_substream *substream)
1944 {
1945 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1946 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1947 struct azx *chip = apcm->chip;
1948 struct azx_dev *azx_dev = get_azx_dev(substream);
1949 unsigned long flags;
1950
1951 mutex_lock(&chip->open_mutex);
1952 spin_lock_irqsave(&chip->reg_lock, flags);
1953 azx_dev->substream = NULL;
1954 azx_dev->running = 0;
1955 spin_unlock_irqrestore(&chip->reg_lock, flags);
1956 azx_release_device(azx_dev);
1957 hinfo->ops.close(hinfo, apcm->codec, substream);
1958 snd_hda_power_down(apcm->codec);
1959 mutex_unlock(&chip->open_mutex);
1960 return 0;
1961 }
1962
1963 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1964 struct snd_pcm_hw_params *hw_params)
1965 {
1966 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1967 struct azx *chip = apcm->chip;
1968 struct snd_pcm_runtime *runtime = substream->runtime;
1969 struct azx_dev *azx_dev = get_azx_dev(substream);
1970 int ret;
1971
1972 mark_runtime_wc(chip, azx_dev, runtime, false);
1973 azx_dev->bufsize = 0;
1974 azx_dev->period_bytes = 0;
1975 azx_dev->format_val = 0;
1976 ret = snd_pcm_lib_malloc_pages(substream,
1977 params_buffer_bytes(hw_params));
1978 if (ret < 0)
1979 return ret;
1980 mark_runtime_wc(chip, azx_dev, runtime, true);
1981 return ret;
1982 }
1983
1984 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1985 {
1986 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1987 struct azx_dev *azx_dev = get_azx_dev(substream);
1988 struct azx *chip = apcm->chip;
1989 struct snd_pcm_runtime *runtime = substream->runtime;
1990 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1991
1992 /* reset BDL address */
1993 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1994 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1995 azx_sd_writel(azx_dev, SD_CTL, 0);
1996 azx_dev->bufsize = 0;
1997 azx_dev->period_bytes = 0;
1998 azx_dev->format_val = 0;
1999
2000 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2001
2002 mark_runtime_wc(chip, azx_dev, runtime, false);
2003 return snd_pcm_lib_free_pages(substream);
2004 }
2005
2006 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2007 {
2008 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2009 struct azx *chip = apcm->chip;
2010 struct azx_dev *azx_dev = get_azx_dev(substream);
2011 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2012 struct snd_pcm_runtime *runtime = substream->runtime;
2013 unsigned int bufsize, period_bytes, format_val, stream_tag;
2014 int err;
2015 struct hda_spdif_out *spdif =
2016 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2017 unsigned short ctls = spdif ? spdif->ctls : 0;
2018
2019 azx_stream_reset(chip, azx_dev);
2020 format_val = snd_hda_calc_stream_format(runtime->rate,
2021 runtime->channels,
2022 runtime->format,
2023 hinfo->maxbps,
2024 ctls);
2025 if (!format_val) {
2026 snd_printk(KERN_ERR SFX
2027 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2028 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2029 return -EINVAL;
2030 }
2031
2032 bufsize = snd_pcm_lib_buffer_bytes(substream);
2033 period_bytes = snd_pcm_lib_period_bytes(substream);
2034
2035 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2036 pci_name(chip->pci), bufsize, format_val);
2037
2038 if (bufsize != azx_dev->bufsize ||
2039 period_bytes != azx_dev->period_bytes ||
2040 format_val != azx_dev->format_val ||
2041 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2042 azx_dev->bufsize = bufsize;
2043 azx_dev->period_bytes = period_bytes;
2044 azx_dev->format_val = format_val;
2045 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2046 err = azx_setup_periods(chip, substream, azx_dev);
2047 if (err < 0)
2048 return err;
2049 }
2050
2051 /* wallclk has 24Mhz clock source */
2052 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2053 runtime->rate) * 1000);
2054 azx_setup_controller(chip, azx_dev);
2055 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2056 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2057 else
2058 azx_dev->fifo_size = 0;
2059
2060 stream_tag = azx_dev->stream_tag;
2061 /* CA-IBG chips need the playback stream starting from 1 */
2062 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2063 stream_tag > chip->capture_streams)
2064 stream_tag -= chip->capture_streams;
2065 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2066 azx_dev->format_val, substream);
2067 }
2068
2069 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2070 {
2071 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2072 struct azx *chip = apcm->chip;
2073 struct azx_dev *azx_dev;
2074 struct snd_pcm_substream *s;
2075 int rstart = 0, start, nsync = 0, sbits = 0;
2076 int nwait, timeout;
2077
2078 azx_dev = get_azx_dev(substream);
2079 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2080
2081 switch (cmd) {
2082 case SNDRV_PCM_TRIGGER_START:
2083 rstart = 1;
2084 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2085 case SNDRV_PCM_TRIGGER_RESUME:
2086 start = 1;
2087 break;
2088 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2089 case SNDRV_PCM_TRIGGER_SUSPEND:
2090 case SNDRV_PCM_TRIGGER_STOP:
2091 start = 0;
2092 break;
2093 default:
2094 return -EINVAL;
2095 }
2096
2097 snd_pcm_group_for_each_entry(s, substream) {
2098 if (s->pcm->card != substream->pcm->card)
2099 continue;
2100 azx_dev = get_azx_dev(s);
2101 sbits |= 1 << azx_dev->index;
2102 nsync++;
2103 snd_pcm_trigger_done(s, substream);
2104 }
2105
2106 spin_lock(&chip->reg_lock);
2107
2108 /* first, set SYNC bits of corresponding streams */
2109 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2110 azx_writel(chip, OLD_SSYNC,
2111 azx_readl(chip, OLD_SSYNC) | sbits);
2112 else
2113 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2114
2115 snd_pcm_group_for_each_entry(s, substream) {
2116 if (s->pcm->card != substream->pcm->card)
2117 continue;
2118 azx_dev = get_azx_dev(s);
2119 if (start) {
2120 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2121 if (!rstart)
2122 azx_dev->start_wallclk -=
2123 azx_dev->period_wallclk;
2124 azx_stream_start(chip, azx_dev);
2125 } else {
2126 azx_stream_stop(chip, azx_dev);
2127 }
2128 azx_dev->running = start;
2129 }
2130 spin_unlock(&chip->reg_lock);
2131 if (start) {
2132 /* wait until all FIFOs get ready */
2133 for (timeout = 5000; timeout; timeout--) {
2134 nwait = 0;
2135 snd_pcm_group_for_each_entry(s, substream) {
2136 if (s->pcm->card != substream->pcm->card)
2137 continue;
2138 azx_dev = get_azx_dev(s);
2139 if (!(azx_sd_readb(azx_dev, SD_STS) &
2140 SD_STS_FIFO_READY))
2141 nwait++;
2142 }
2143 if (!nwait)
2144 break;
2145 cpu_relax();
2146 }
2147 } else {
2148 /* wait until all RUN bits are cleared */
2149 for (timeout = 5000; timeout; timeout--) {
2150 nwait = 0;
2151 snd_pcm_group_for_each_entry(s, substream) {
2152 if (s->pcm->card != substream->pcm->card)
2153 continue;
2154 azx_dev = get_azx_dev(s);
2155 if (azx_sd_readb(azx_dev, SD_CTL) &
2156 SD_CTL_DMA_START)
2157 nwait++;
2158 }
2159 if (!nwait)
2160 break;
2161 cpu_relax();
2162 }
2163 }
2164 spin_lock(&chip->reg_lock);
2165 /* reset SYNC bits */
2166 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2167 azx_writel(chip, OLD_SSYNC,
2168 azx_readl(chip, OLD_SSYNC) & ~sbits);
2169 else
2170 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2171 if (start) {
2172 azx_timecounter_init(substream, 0, 0);
2173 if (nsync > 1) {
2174 cycle_t cycle_last;
2175
2176 /* same start cycle for master and group */
2177 azx_dev = get_azx_dev(substream);
2178 cycle_last = azx_dev->azx_tc.cycle_last;
2179
2180 snd_pcm_group_for_each_entry(s, substream) {
2181 if (s->pcm->card != substream->pcm->card)
2182 continue;
2183 azx_timecounter_init(s, 1, cycle_last);
2184 }
2185 }
2186 }
2187 spin_unlock(&chip->reg_lock);
2188 return 0;
2189 }
2190
2191 /* get the current DMA position with correction on VIA chips */
2192 static unsigned int azx_via_get_position(struct azx *chip,
2193 struct azx_dev *azx_dev)
2194 {
2195 unsigned int link_pos, mini_pos, bound_pos;
2196 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2197 unsigned int fifo_size;
2198
2199 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2200 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2201 /* Playback, no problem using link position */
2202 return link_pos;
2203 }
2204
2205 /* Capture */
2206 /* For new chipset,
2207 * use mod to get the DMA position just like old chipset
2208 */
2209 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2210 mod_dma_pos %= azx_dev->period_bytes;
2211
2212 /* azx_dev->fifo_size can't get FIFO size of in stream.
2213 * Get from base address + offset.
2214 */
2215 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2216
2217 if (azx_dev->insufficient) {
2218 /* Link position never gather than FIFO size */
2219 if (link_pos <= fifo_size)
2220 return 0;
2221
2222 azx_dev->insufficient = 0;
2223 }
2224
2225 if (link_pos <= fifo_size)
2226 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2227 else
2228 mini_pos = link_pos - fifo_size;
2229
2230 /* Find nearest previous boudary */
2231 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2232 mod_link_pos = link_pos % azx_dev->period_bytes;
2233 if (mod_link_pos >= fifo_size)
2234 bound_pos = link_pos - mod_link_pos;
2235 else if (mod_dma_pos >= mod_mini_pos)
2236 bound_pos = mini_pos - mod_mini_pos;
2237 else {
2238 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2239 if (bound_pos >= azx_dev->bufsize)
2240 bound_pos = 0;
2241 }
2242
2243 /* Calculate real DMA position we want */
2244 return bound_pos + mod_dma_pos;
2245 }
2246
2247 static unsigned int azx_get_position(struct azx *chip,
2248 struct azx_dev *azx_dev,
2249 bool with_check)
2250 {
2251 unsigned int pos;
2252 int stream = azx_dev->substream->stream;
2253 int delay = 0;
2254
2255 switch (chip->position_fix[stream]) {
2256 case POS_FIX_LPIB:
2257 /* read LPIB */
2258 pos = azx_sd_readl(azx_dev, SD_LPIB);
2259 break;
2260 case POS_FIX_VIACOMBO:
2261 pos = azx_via_get_position(chip, azx_dev);
2262 break;
2263 default:
2264 /* use the position buffer */
2265 pos = le32_to_cpu(*azx_dev->posbuf);
2266 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2267 if (!pos || pos == (u32)-1) {
2268 printk(KERN_WARNING
2269 "hda-intel: Invalid position buffer, "
2270 "using LPIB read method instead.\n");
2271 chip->position_fix[stream] = POS_FIX_LPIB;
2272 pos = azx_sd_readl(azx_dev, SD_LPIB);
2273 } else
2274 chip->position_fix[stream] = POS_FIX_POSBUF;
2275 }
2276 break;
2277 }
2278
2279 if (pos >= azx_dev->bufsize)
2280 pos = 0;
2281
2282 /* calculate runtime delay from LPIB */
2283 if (azx_dev->substream->runtime &&
2284 chip->position_fix[stream] == POS_FIX_POSBUF &&
2285 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2286 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2287 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2288 delay = pos - lpib_pos;
2289 else
2290 delay = lpib_pos - pos;
2291 if (delay < 0)
2292 delay += azx_dev->bufsize;
2293 if (delay >= azx_dev->period_bytes) {
2294 snd_printk(KERN_WARNING SFX
2295 "%s: Unstable LPIB (%d >= %d); "
2296 "disabling LPIB delay counting\n",
2297 pci_name(chip->pci), delay, azx_dev->period_bytes);
2298 delay = 0;
2299 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2300 }
2301 azx_dev->substream->runtime->delay =
2302 bytes_to_frames(azx_dev->substream->runtime, delay);
2303 }
2304 trace_azx_get_position(chip, azx_dev, pos, delay);
2305 return pos;
2306 }
2307
2308 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2309 {
2310 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2311 struct azx *chip = apcm->chip;
2312 struct azx_dev *azx_dev = get_azx_dev(substream);
2313 return bytes_to_frames(substream->runtime,
2314 azx_get_position(chip, azx_dev, false));
2315 }
2316
2317 /*
2318 * Check whether the current DMA position is acceptable for updating
2319 * periods. Returns non-zero if it's OK.
2320 *
2321 * Many HD-audio controllers appear pretty inaccurate about
2322 * the update-IRQ timing. The IRQ is issued before actually the
2323 * data is processed. So, we need to process it afterwords in a
2324 * workqueue.
2325 */
2326 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2327 {
2328 u32 wallclk;
2329 unsigned int pos;
2330
2331 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2332 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2333 return -1; /* bogus (too early) interrupt */
2334
2335 pos = azx_get_position(chip, azx_dev, true);
2336
2337 if (WARN_ONCE(!azx_dev->period_bytes,
2338 "hda-intel: zero azx_dev->period_bytes"))
2339 return -1; /* this shouldn't happen! */
2340 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2341 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2342 /* NG - it's below the first next period boundary */
2343 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2344 azx_dev->start_wallclk += wallclk;
2345 return 1; /* OK, it's fine */
2346 }
2347
2348 /*
2349 * The work for pending PCM period updates.
2350 */
2351 static void azx_irq_pending_work(struct work_struct *work)
2352 {
2353 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2354 int i, pending, ok;
2355
2356 if (!chip->irq_pending_warned) {
2357 printk(KERN_WARNING
2358 "hda-intel: IRQ timing workaround is activated "
2359 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2360 chip->card->number);
2361 chip->irq_pending_warned = 1;
2362 }
2363
2364 for (;;) {
2365 pending = 0;
2366 spin_lock_irq(&chip->reg_lock);
2367 for (i = 0; i < chip->num_streams; i++) {
2368 struct azx_dev *azx_dev = &chip->azx_dev[i];
2369 if (!azx_dev->irq_pending ||
2370 !azx_dev->substream ||
2371 !azx_dev->running)
2372 continue;
2373 ok = azx_position_ok(chip, azx_dev);
2374 if (ok > 0) {
2375 azx_dev->irq_pending = 0;
2376 spin_unlock(&chip->reg_lock);
2377 snd_pcm_period_elapsed(azx_dev->substream);
2378 spin_lock(&chip->reg_lock);
2379 } else if (ok < 0) {
2380 pending = 0; /* too early */
2381 } else
2382 pending++;
2383 }
2384 spin_unlock_irq(&chip->reg_lock);
2385 if (!pending)
2386 return;
2387 msleep(1);
2388 }
2389 }
2390
2391 /* clear irq_pending flags and assure no on-going workq */
2392 static void azx_clear_irq_pending(struct azx *chip)
2393 {
2394 int i;
2395
2396 spin_lock_irq(&chip->reg_lock);
2397 for (i = 0; i < chip->num_streams; i++)
2398 chip->azx_dev[i].irq_pending = 0;
2399 spin_unlock_irq(&chip->reg_lock);
2400 }
2401
2402 #ifdef CONFIG_X86
2403 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2404 struct vm_area_struct *area)
2405 {
2406 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2407 struct azx *chip = apcm->chip;
2408 if (!azx_snoop(chip))
2409 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2410 return snd_pcm_lib_default_mmap(substream, area);
2411 }
2412 #else
2413 #define azx_pcm_mmap NULL
2414 #endif
2415
2416 static struct snd_pcm_ops azx_pcm_ops = {
2417 .open = azx_pcm_open,
2418 .close = azx_pcm_close,
2419 .ioctl = snd_pcm_lib_ioctl,
2420 .hw_params = azx_pcm_hw_params,
2421 .hw_free = azx_pcm_hw_free,
2422 .prepare = azx_pcm_prepare,
2423 .trigger = azx_pcm_trigger,
2424 .pointer = azx_pcm_pointer,
2425 .wall_clock = azx_get_wallclock_tstamp,
2426 .mmap = azx_pcm_mmap,
2427 .page = snd_pcm_sgbuf_ops_page,
2428 };
2429
2430 static void azx_pcm_free(struct snd_pcm *pcm)
2431 {
2432 struct azx_pcm *apcm = pcm->private_data;
2433 if (apcm) {
2434 list_del(&apcm->list);
2435 kfree(apcm);
2436 }
2437 }
2438
2439 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2440
2441 static int
2442 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2443 struct hda_pcm *cpcm)
2444 {
2445 struct azx *chip = bus->private_data;
2446 struct snd_pcm *pcm;
2447 struct azx_pcm *apcm;
2448 int pcm_dev = cpcm->device;
2449 unsigned int size;
2450 int s, err;
2451
2452 list_for_each_entry(apcm, &chip->pcm_list, list) {
2453 if (apcm->pcm->device == pcm_dev) {
2454 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2455 pci_name(chip->pci), pcm_dev);
2456 return -EBUSY;
2457 }
2458 }
2459 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2460 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2461 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2462 &pcm);
2463 if (err < 0)
2464 return err;
2465 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2466 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2467 if (apcm == NULL)
2468 return -ENOMEM;
2469 apcm->chip = chip;
2470 apcm->pcm = pcm;
2471 apcm->codec = codec;
2472 pcm->private_data = apcm;
2473 pcm->private_free = azx_pcm_free;
2474 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2475 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2476 list_add_tail(&apcm->list, &chip->pcm_list);
2477 cpcm->pcm = pcm;
2478 for (s = 0; s < 2; s++) {
2479 apcm->hinfo[s] = &cpcm->stream[s];
2480 if (cpcm->stream[s].substreams)
2481 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2482 }
2483 /* buffer pre-allocation */
2484 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2485 if (size > MAX_PREALLOC_SIZE)
2486 size = MAX_PREALLOC_SIZE;
2487 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2488 snd_dma_pci_data(chip->pci),
2489 size, MAX_PREALLOC_SIZE);
2490 return 0;
2491 }
2492
2493 /*
2494 * mixer creation - all stuff is implemented in hda module
2495 */
2496 static int azx_mixer_create(struct azx *chip)
2497 {
2498 return snd_hda_build_controls(chip->bus);
2499 }
2500
2501
2502 /*
2503 * initialize SD streams
2504 */
2505 static int azx_init_stream(struct azx *chip)
2506 {
2507 int i;
2508
2509 /* initialize each stream (aka device)
2510 * assign the starting bdl address to each stream (device)
2511 * and initialize
2512 */
2513 for (i = 0; i < chip->num_streams; i++) {
2514 struct azx_dev *azx_dev = &chip->azx_dev[i];
2515 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2516 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2517 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2518 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2519 azx_dev->sd_int_sta_mask = 1 << i;
2520 /* stream tag: must be non-zero and unique */
2521 azx_dev->index = i;
2522 azx_dev->stream_tag = i + 1;
2523 }
2524
2525 return 0;
2526 }
2527
2528 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2529 {
2530 if (request_irq(chip->pci->irq, azx_interrupt,
2531 chip->msi ? 0 : IRQF_SHARED,
2532 KBUILD_MODNAME, chip)) {
2533 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2534 "disabling device\n", chip->pci->irq);
2535 if (do_disconnect)
2536 snd_card_disconnect(chip->card);
2537 return -1;
2538 }
2539 chip->irq = chip->pci->irq;
2540 pci_intx(chip->pci, !chip->msi);
2541 return 0;
2542 }
2543
2544
2545 static void azx_stop_chip(struct azx *chip)
2546 {
2547 if (!chip->initialized)
2548 return;
2549
2550 /* disable interrupts */
2551 azx_int_disable(chip);
2552 azx_int_clear(chip);
2553
2554 /* disable CORB/RIRB */
2555 azx_free_cmd_io(chip);
2556
2557 /* disable position buffer */
2558 azx_writel(chip, DPLBASE, 0);
2559 azx_writel(chip, DPUBASE, 0);
2560
2561 chip->initialized = 0;
2562 }
2563
2564 #ifdef CONFIG_PM
2565 /* power-up/down the controller */
2566 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2567 {
2568 struct azx *chip = bus->private_data;
2569
2570 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2571 return;
2572
2573 if (power_up)
2574 pm_runtime_get_sync(&chip->pci->dev);
2575 else
2576 pm_runtime_put_sync(&chip->pci->dev);
2577 }
2578
2579 static DEFINE_MUTEX(card_list_lock);
2580 static LIST_HEAD(card_list);
2581
2582 static void azx_add_card_list(struct azx *chip)
2583 {
2584 mutex_lock(&card_list_lock);
2585 list_add(&chip->list, &card_list);
2586 mutex_unlock(&card_list_lock);
2587 }
2588
2589 static void azx_del_card_list(struct azx *chip)
2590 {
2591 mutex_lock(&card_list_lock);
2592 list_del_init(&chip->list);
2593 mutex_unlock(&card_list_lock);
2594 }
2595
2596 /* trigger power-save check at writing parameter */
2597 static int param_set_xint(const char *val, const struct kernel_param *kp)
2598 {
2599 struct azx *chip;
2600 struct hda_codec *c;
2601 int prev = power_save;
2602 int ret = param_set_int(val, kp);
2603
2604 if (ret || prev == power_save)
2605 return ret;
2606
2607 mutex_lock(&card_list_lock);
2608 list_for_each_entry(chip, &card_list, list) {
2609 if (!chip->bus || chip->disabled)
2610 continue;
2611 list_for_each_entry(c, &chip->bus->codec_list, list)
2612 snd_hda_power_sync(c);
2613 }
2614 mutex_unlock(&card_list_lock);
2615 return 0;
2616 }
2617 #else
2618 #define azx_add_card_list(chip) /* NOP */
2619 #define azx_del_card_list(chip) /* NOP */
2620 #endif /* CONFIG_PM */
2621
2622 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2623 /*
2624 * power management
2625 */
2626 static int azx_suspend(struct device *dev)
2627 {
2628 struct pci_dev *pci = to_pci_dev(dev);
2629 struct snd_card *card = dev_get_drvdata(dev);
2630 struct azx *chip = card->private_data;
2631 struct azx_pcm *p;
2632
2633 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2634 azx_clear_irq_pending(chip);
2635 list_for_each_entry(p, &chip->pcm_list, list)
2636 snd_pcm_suspend_all(p->pcm);
2637 if (chip->initialized)
2638 snd_hda_suspend(chip->bus);
2639 azx_stop_chip(chip);
2640 if (chip->irq >= 0) {
2641 free_irq(chip->irq, chip);
2642 chip->irq = -1;
2643 }
2644 if (chip->msi)
2645 pci_disable_msi(chip->pci);
2646 pci_disable_device(pci);
2647 pci_save_state(pci);
2648 pci_set_power_state(pci, PCI_D3hot);
2649 return 0;
2650 }
2651
2652 static int azx_resume(struct device *dev)
2653 {
2654 struct pci_dev *pci = to_pci_dev(dev);
2655 struct snd_card *card = dev_get_drvdata(dev);
2656 struct azx *chip = card->private_data;
2657
2658 pci_set_power_state(pci, PCI_D0);
2659 pci_restore_state(pci);
2660 if (pci_enable_device(pci) < 0) {
2661 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2662 "disabling device\n");
2663 snd_card_disconnect(card);
2664 return -EIO;
2665 }
2666 pci_set_master(pci);
2667 if (chip->msi)
2668 if (pci_enable_msi(pci) < 0)
2669 chip->msi = 0;
2670 if (azx_acquire_irq(chip, 1) < 0)
2671 return -EIO;
2672 azx_init_pci(chip);
2673
2674 azx_init_chip(chip, 1);
2675
2676 snd_hda_resume(chip->bus);
2677 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2678 return 0;
2679 }
2680 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2681
2682 #ifdef CONFIG_PM_RUNTIME
2683 static int azx_runtime_suspend(struct device *dev)
2684 {
2685 struct snd_card *card = dev_get_drvdata(dev);
2686 struct azx *chip = card->private_data;
2687
2688 if (!power_save_controller ||
2689 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2690 return -EAGAIN;
2691
2692 azx_stop_chip(chip);
2693 azx_clear_irq_pending(chip);
2694 return 0;
2695 }
2696
2697 static int azx_runtime_resume(struct device *dev)
2698 {
2699 struct snd_card *card = dev_get_drvdata(dev);
2700 struct azx *chip = card->private_data;
2701
2702 azx_init_pci(chip);
2703 azx_init_chip(chip, 1);
2704 return 0;
2705 }
2706 #endif /* CONFIG_PM_RUNTIME */
2707
2708 #ifdef CONFIG_PM
2709 static const struct dev_pm_ops azx_pm = {
2710 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2711 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2712 };
2713
2714 #define AZX_PM_OPS &azx_pm
2715 #else
2716 #define AZX_PM_OPS NULL
2717 #endif /* CONFIG_PM */
2718
2719
2720 /*
2721 * reboot notifier for hang-up problem at power-down
2722 */
2723 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2724 {
2725 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2726 snd_hda_bus_reboot_notify(chip->bus);
2727 azx_stop_chip(chip);
2728 return NOTIFY_OK;
2729 }
2730
2731 static void azx_notifier_register(struct azx *chip)
2732 {
2733 chip->reboot_notifier.notifier_call = azx_halt;
2734 register_reboot_notifier(&chip->reboot_notifier);
2735 }
2736
2737 static void azx_notifier_unregister(struct azx *chip)
2738 {
2739 if (chip->reboot_notifier.notifier_call)
2740 unregister_reboot_notifier(&chip->reboot_notifier);
2741 }
2742
2743 static int azx_first_init(struct azx *chip);
2744 static int azx_probe_continue(struct azx *chip);
2745
2746 #ifdef SUPPORT_VGA_SWITCHEROO
2747 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
2748
2749 static void azx_vs_set_state(struct pci_dev *pci,
2750 enum vga_switcheroo_state state)
2751 {
2752 struct snd_card *card = pci_get_drvdata(pci);
2753 struct azx *chip = card->private_data;
2754 bool disabled;
2755
2756 wait_for_completion(&chip->probe_wait);
2757 if (chip->init_failed)
2758 return;
2759
2760 disabled = (state == VGA_SWITCHEROO_OFF);
2761 if (chip->disabled == disabled)
2762 return;
2763
2764 if (!chip->bus) {
2765 chip->disabled = disabled;
2766 if (!disabled) {
2767 snd_printk(KERN_INFO SFX
2768 "%s: Start delayed initialization\n",
2769 pci_name(chip->pci));
2770 if (azx_first_init(chip) < 0 ||
2771 azx_probe_continue(chip) < 0) {
2772 snd_printk(KERN_ERR SFX
2773 "%s: initialization error\n",
2774 pci_name(chip->pci));
2775 chip->init_failed = true;
2776 }
2777 }
2778 } else {
2779 snd_printk(KERN_INFO SFX
2780 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
2781 disabled ? "Disabling" : "Enabling");
2782 if (disabled) {
2783 azx_suspend(&pci->dev);
2784 chip->disabled = true;
2785 if (snd_hda_lock_devices(chip->bus))
2786 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
2787 pci_name(chip->pci));
2788 } else {
2789 snd_hda_unlock_devices(chip->bus);
2790 chip->disabled = false;
2791 azx_resume(&pci->dev);
2792 }
2793 }
2794 }
2795
2796 static bool azx_vs_can_switch(struct pci_dev *pci)
2797 {
2798 struct snd_card *card = pci_get_drvdata(pci);
2799 struct azx *chip = card->private_data;
2800
2801 wait_for_completion(&chip->probe_wait);
2802 if (chip->init_failed)
2803 return false;
2804 if (chip->disabled || !chip->bus)
2805 return true;
2806 if (snd_hda_lock_devices(chip->bus))
2807 return false;
2808 snd_hda_unlock_devices(chip->bus);
2809 return true;
2810 }
2811
2812 static void init_vga_switcheroo(struct azx *chip)
2813 {
2814 struct pci_dev *p = get_bound_vga(chip->pci);
2815 if (p) {
2816 snd_printk(KERN_INFO SFX
2817 "%s: Handle VGA-switcheroo audio client\n",
2818 pci_name(chip->pci));
2819 chip->use_vga_switcheroo = 1;
2820 pci_dev_put(p);
2821 }
2822 }
2823
2824 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2825 .set_gpu_state = azx_vs_set_state,
2826 .can_switch = azx_vs_can_switch,
2827 };
2828
2829 static int register_vga_switcheroo(struct azx *chip)
2830 {
2831 int err;
2832
2833 if (!chip->use_vga_switcheroo)
2834 return 0;
2835 /* FIXME: currently only handling DIS controller
2836 * is there any machine with two switchable HDMI audio controllers?
2837 */
2838 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2839 VGA_SWITCHEROO_DIS,
2840 chip->bus != NULL);
2841 if (err < 0)
2842 return err;
2843 chip->vga_switcheroo_registered = 1;
2844 return 0;
2845 }
2846 #else
2847 #define init_vga_switcheroo(chip) /* NOP */
2848 #define register_vga_switcheroo(chip) 0
2849 #define check_hdmi_disabled(pci) false
2850 #endif /* SUPPORT_VGA_SWITCHER */
2851
2852 /*
2853 * destructor
2854 */
2855 static int azx_free(struct azx *chip)
2856 {
2857 int i;
2858
2859 azx_del_card_list(chip);
2860
2861 azx_notifier_unregister(chip);
2862
2863 chip->init_failed = 1; /* to be sure */
2864 complete(&chip->probe_wait);
2865
2866 if (use_vga_switcheroo(chip)) {
2867 if (chip->disabled && chip->bus)
2868 snd_hda_unlock_devices(chip->bus);
2869 if (chip->vga_switcheroo_registered)
2870 vga_switcheroo_unregister_client(chip->pci);
2871 }
2872
2873 if (chip->initialized) {
2874 azx_clear_irq_pending(chip);
2875 for (i = 0; i < chip->num_streams; i++)
2876 azx_stream_stop(chip, &chip->azx_dev[i]);
2877 azx_stop_chip(chip);
2878 }
2879
2880 if (chip->irq >= 0)
2881 free_irq(chip->irq, (void*)chip);
2882 if (chip->msi)
2883 pci_disable_msi(chip->pci);
2884 if (chip->remap_addr)
2885 iounmap(chip->remap_addr);
2886
2887 if (chip->azx_dev) {
2888 for (i = 0; i < chip->num_streams; i++)
2889 if (chip->azx_dev[i].bdl.area) {
2890 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2891 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2892 }
2893 }
2894 if (chip->rb.area) {
2895 mark_pages_wc(chip, &chip->rb, false);
2896 snd_dma_free_pages(&chip->rb);
2897 }
2898 if (chip->posbuf.area) {
2899 mark_pages_wc(chip, &chip->posbuf, false);
2900 snd_dma_free_pages(&chip->posbuf);
2901 }
2902 if (chip->region_requested)
2903 pci_release_regions(chip->pci);
2904 pci_disable_device(chip->pci);
2905 kfree(chip->azx_dev);
2906 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2907 if (chip->fw)
2908 release_firmware(chip->fw);
2909 #endif
2910 kfree(chip);
2911
2912 return 0;
2913 }
2914
2915 static int azx_dev_free(struct snd_device *device)
2916 {
2917 return azx_free(device->device_data);
2918 }
2919
2920 #ifdef SUPPORT_VGA_SWITCHEROO
2921 /*
2922 * Check of disabled HDMI controller by vga-switcheroo
2923 */
2924 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
2925 {
2926 struct pci_dev *p;
2927
2928 /* check only discrete GPU */
2929 switch (pci->vendor) {
2930 case PCI_VENDOR_ID_ATI:
2931 case PCI_VENDOR_ID_AMD:
2932 case PCI_VENDOR_ID_NVIDIA:
2933 if (pci->devfn == 1) {
2934 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2935 pci->bus->number, 0);
2936 if (p) {
2937 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2938 return p;
2939 pci_dev_put(p);
2940 }
2941 }
2942 break;
2943 }
2944 return NULL;
2945 }
2946
2947 static bool check_hdmi_disabled(struct pci_dev *pci)
2948 {
2949 bool vga_inactive = false;
2950 struct pci_dev *p = get_bound_vga(pci);
2951
2952 if (p) {
2953 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2954 vga_inactive = true;
2955 pci_dev_put(p);
2956 }
2957 return vga_inactive;
2958 }
2959 #endif /* SUPPORT_VGA_SWITCHEROO */
2960
2961 /*
2962 * white/black-listing for position_fix
2963 */
2964 static struct snd_pci_quirk position_fix_list[] = {
2965 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2966 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2967 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2968 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2969 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2970 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2971 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2972 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2973 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2974 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2975 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2976 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2977 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2978 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2979 {}
2980 };
2981
2982 static int check_position_fix(struct azx *chip, int fix)
2983 {
2984 const struct snd_pci_quirk *q;
2985
2986 switch (fix) {
2987 case POS_FIX_AUTO:
2988 case POS_FIX_LPIB:
2989 case POS_FIX_POSBUF:
2990 case POS_FIX_VIACOMBO:
2991 case POS_FIX_COMBO:
2992 return fix;
2993 }
2994
2995 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2996 if (q) {
2997 printk(KERN_INFO
2998 "hda_intel: position_fix set to %d "
2999 "for device %04x:%04x\n",
3000 q->value, q->subvendor, q->subdevice);
3001 return q->value;
3002 }
3003
3004 /* Check VIA/ATI HD Audio Controller exist */
3005 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3006 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3007 return POS_FIX_VIACOMBO;
3008 }
3009 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3010 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3011 return POS_FIX_LPIB;
3012 }
3013 return POS_FIX_AUTO;
3014 }
3015
3016 /*
3017 * black-lists for probe_mask
3018 */
3019 static struct snd_pci_quirk probe_mask_list[] = {
3020 /* Thinkpad often breaks the controller communication when accessing
3021 * to the non-working (or non-existing) modem codec slot.
3022 */
3023 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3024 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3025 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3026 /* broken BIOS */
3027 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3028 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3029 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3030 /* forced codec slots */
3031 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3032 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3033 /* WinFast VP200 H (Teradici) user reported broken communication */
3034 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3035 {}
3036 };
3037
3038 #define AZX_FORCE_CODEC_MASK 0x100
3039
3040 static void check_probe_mask(struct azx *chip, int dev)
3041 {
3042 const struct snd_pci_quirk *q;
3043
3044 chip->codec_probe_mask = probe_mask[dev];
3045 if (chip->codec_probe_mask == -1) {
3046 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3047 if (q) {
3048 printk(KERN_INFO
3049 "hda_intel: probe_mask set to 0x%x "
3050 "for device %04x:%04x\n",
3051 q->value, q->subvendor, q->subdevice);
3052 chip->codec_probe_mask = q->value;
3053 }
3054 }
3055
3056 /* check forced option */
3057 if (chip->codec_probe_mask != -1 &&
3058 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3059 chip->codec_mask = chip->codec_probe_mask & 0xff;
3060 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3061 chip->codec_mask);
3062 }
3063 }
3064
3065 /*
3066 * white/black-list for enable_msi
3067 */
3068 static struct snd_pci_quirk msi_black_list[] = {
3069 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3070 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3071 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3072 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3073 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3074 {}
3075 };
3076
3077 static void check_msi(struct azx *chip)
3078 {
3079 const struct snd_pci_quirk *q;
3080
3081 if (enable_msi >= 0) {
3082 chip->msi = !!enable_msi;
3083 return;
3084 }
3085 chip->msi = 1; /* enable MSI as default */
3086 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3087 if (q) {
3088 printk(KERN_INFO
3089 "hda_intel: msi for device %04x:%04x set to %d\n",
3090 q->subvendor, q->subdevice, q->value);
3091 chip->msi = q->value;
3092 return;
3093 }
3094
3095 /* NVidia chipsets seem to cause troubles with MSI */
3096 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3097 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3098 chip->msi = 0;
3099 }
3100 }
3101
3102 /* check the snoop mode availability */
3103 static void azx_check_snoop_available(struct azx *chip)
3104 {
3105 bool snoop = chip->snoop;
3106
3107 switch (chip->driver_type) {
3108 case AZX_DRIVER_VIA:
3109 /* force to non-snoop mode for a new VIA controller
3110 * when BIOS is set
3111 */
3112 if (snoop) {
3113 u8 val;
3114 pci_read_config_byte(chip->pci, 0x42, &val);
3115 if (!(val & 0x80) && chip->pci->revision == 0x30)
3116 snoop = false;
3117 }
3118 break;
3119 case AZX_DRIVER_ATIHDMI_NS:
3120 /* new ATI HDMI requires non-snoop */
3121 snoop = false;
3122 break;
3123 }
3124
3125 if (snoop != chip->snoop) {
3126 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3127 pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3128 chip->snoop = snoop;
3129 }
3130 }
3131
3132 /*
3133 * constructor
3134 */
3135 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3136 int dev, unsigned int driver_caps,
3137 struct azx **rchip)
3138 {
3139 static struct snd_device_ops ops = {
3140 .dev_free = azx_dev_free,
3141 };
3142 struct azx *chip;
3143 int err;
3144
3145 *rchip = NULL;
3146
3147 err = pci_enable_device(pci);
3148 if (err < 0)
3149 return err;
3150
3151 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3152 if (!chip) {
3153 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3154 pci_disable_device(pci);
3155 return -ENOMEM;
3156 }
3157
3158 spin_lock_init(&chip->reg_lock);
3159 mutex_init(&chip->open_mutex);
3160 chip->card = card;
3161 chip->pci = pci;
3162 chip->irq = -1;
3163 chip->driver_caps = driver_caps;
3164 chip->driver_type = driver_caps & 0xff;
3165 check_msi(chip);
3166 chip->dev_index = dev;
3167 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3168 INIT_LIST_HEAD(&chip->pcm_list);
3169 INIT_LIST_HEAD(&chip->list);
3170 init_vga_switcheroo(chip);
3171 init_completion(&chip->probe_wait);
3172
3173 chip->position_fix[0] = chip->position_fix[1] =
3174 check_position_fix(chip, position_fix[dev]);
3175 /* combo mode uses LPIB for playback */
3176 if (chip->position_fix[0] == POS_FIX_COMBO) {
3177 chip->position_fix[0] = POS_FIX_LPIB;
3178 chip->position_fix[1] = POS_FIX_AUTO;
3179 }
3180
3181 check_probe_mask(chip, dev);
3182
3183 chip->single_cmd = single_cmd;
3184 chip->snoop = hda_snoop;
3185 azx_check_snoop_available(chip);
3186
3187 if (bdl_pos_adj[dev] < 0) {
3188 switch (chip->driver_type) {
3189 case AZX_DRIVER_ICH:
3190 case AZX_DRIVER_PCH:
3191 bdl_pos_adj[dev] = 1;
3192 break;
3193 default:
3194 bdl_pos_adj[dev] = 32;
3195 break;
3196 }
3197 }
3198
3199 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3200 if (err < 0) {
3201 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3202 pci_name(chip->pci));
3203 azx_free(chip);
3204 return err;
3205 }
3206
3207 *rchip = chip;
3208 return 0;
3209 }
3210
3211 static int azx_first_init(struct azx *chip)
3212 {
3213 int dev = chip->dev_index;
3214 struct pci_dev *pci = chip->pci;
3215 struct snd_card *card = chip->card;
3216 int i, err;
3217 unsigned short gcap;
3218
3219 #if BITS_PER_LONG != 64
3220 /* Fix up base address on ULI M5461 */
3221 if (chip->driver_type == AZX_DRIVER_ULI) {
3222 u16 tmp3;
3223 pci_read_config_word(pci, 0x40, &tmp3);
3224 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3225 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3226 }
3227 #endif
3228
3229 err = pci_request_regions(pci, "ICH HD audio");
3230 if (err < 0)
3231 return err;
3232 chip->region_requested = 1;
3233
3234 chip->addr = pci_resource_start(pci, 0);
3235 chip->remap_addr = pci_ioremap_bar(pci, 0);
3236 if (chip->remap_addr == NULL) {
3237 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3238 return -ENXIO;
3239 }
3240
3241 if (chip->msi)
3242 if (pci_enable_msi(pci) < 0)
3243 chip->msi = 0;
3244
3245 if (azx_acquire_irq(chip, 0) < 0)
3246 return -EBUSY;
3247
3248 pci_set_master(pci);
3249 synchronize_irq(chip->irq);
3250
3251 gcap = azx_readw(chip, GCAP);
3252 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3253
3254 /* disable SB600 64bit support for safety */
3255 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3256 struct pci_dev *p_smbus;
3257 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3258 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3259 NULL);
3260 if (p_smbus) {
3261 if (p_smbus->revision < 0x30)
3262 gcap &= ~ICH6_GCAP_64OK;
3263 pci_dev_put(p_smbus);
3264 }
3265 }
3266
3267 /* disable 64bit DMA address on some devices */
3268 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3269 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3270 gcap &= ~ICH6_GCAP_64OK;
3271 }
3272
3273 /* disable buffer size rounding to 128-byte multiples if supported */
3274 if (align_buffer_size >= 0)
3275 chip->align_buffer_size = !!align_buffer_size;
3276 else {
3277 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3278 chip->align_buffer_size = 0;
3279 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3280 chip->align_buffer_size = 1;
3281 else
3282 chip->align_buffer_size = 1;
3283 }
3284
3285 /* allow 64bit DMA address if supported by H/W */
3286 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3287 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3288 else {
3289 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3290 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3291 }
3292
3293 /* read number of streams from GCAP register instead of using
3294 * hardcoded value
3295 */
3296 chip->capture_streams = (gcap >> 8) & 0x0f;
3297 chip->playback_streams = (gcap >> 12) & 0x0f;
3298 if (!chip->playback_streams && !chip->capture_streams) {
3299 /* gcap didn't give any info, switching to old method */
3300
3301 switch (chip->driver_type) {
3302 case AZX_DRIVER_ULI:
3303 chip->playback_streams = ULI_NUM_PLAYBACK;
3304 chip->capture_streams = ULI_NUM_CAPTURE;
3305 break;
3306 case AZX_DRIVER_ATIHDMI:
3307 case AZX_DRIVER_ATIHDMI_NS:
3308 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3309 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3310 break;
3311 case AZX_DRIVER_GENERIC:
3312 default:
3313 chip->playback_streams = ICH6_NUM_PLAYBACK;
3314 chip->capture_streams = ICH6_NUM_CAPTURE;
3315 break;
3316 }
3317 }
3318 chip->capture_index_offset = 0;
3319 chip->playback_index_offset = chip->capture_streams;
3320 chip->num_streams = chip->playback_streams + chip->capture_streams;
3321 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3322 GFP_KERNEL);
3323 if (!chip->azx_dev) {
3324 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
3325 return -ENOMEM;
3326 }
3327
3328 for (i = 0; i < chip->num_streams; i++) {
3329 /* allocate memory for the BDL for each stream */
3330 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3331 snd_dma_pci_data(chip->pci),
3332 BDL_SIZE, &chip->azx_dev[i].bdl);
3333 if (err < 0) {
3334 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
3335 return -ENOMEM;
3336 }
3337 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3338 }
3339 /* allocate memory for the position buffer */
3340 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3341 snd_dma_pci_data(chip->pci),
3342 chip->num_streams * 8, &chip->posbuf);
3343 if (err < 0) {
3344 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
3345 return -ENOMEM;
3346 }
3347 mark_pages_wc(chip, &chip->posbuf, true);
3348 /* allocate CORB/RIRB */
3349 err = azx_alloc_cmd_io(chip);
3350 if (err < 0)
3351 return err;
3352
3353 /* initialize streams */
3354 azx_init_stream(chip);
3355
3356 /* initialize chip */
3357 azx_init_pci(chip);
3358 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3359
3360 /* codec detection */
3361 if (!chip->codec_mask) {
3362 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
3363 return -ENODEV;
3364 }
3365
3366 strcpy(card->driver, "HDA-Intel");
3367 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3368 sizeof(card->shortname));
3369 snprintf(card->longname, sizeof(card->longname),
3370 "%s at 0x%lx irq %i",
3371 card->shortname, chip->addr, chip->irq);
3372
3373 return 0;
3374 }
3375
3376 static void power_down_all_codecs(struct azx *chip)
3377 {
3378 #ifdef CONFIG_PM
3379 /* The codecs were powered up in snd_hda_codec_new().
3380 * Now all initialization done, so turn them down if possible
3381 */
3382 struct hda_codec *codec;
3383 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3384 snd_hda_power_down(codec);
3385 }
3386 #endif
3387 }
3388
3389 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3390 /* callback from request_firmware_nowait() */
3391 static void azx_firmware_cb(const struct firmware *fw, void *context)
3392 {
3393 struct snd_card *card = context;
3394 struct azx *chip = card->private_data;
3395 struct pci_dev *pci = chip->pci;
3396
3397 if (!fw) {
3398 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3399 pci_name(chip->pci));
3400 goto error;
3401 }
3402
3403 chip->fw = fw;
3404 if (!chip->disabled) {
3405 /* continue probing */
3406 if (azx_probe_continue(chip))
3407 goto error;
3408 }
3409 return; /* OK */
3410
3411 error:
3412 snd_card_free(card);
3413 pci_set_drvdata(pci, NULL);
3414 }
3415 #endif
3416
3417 static int azx_probe(struct pci_dev *pci,
3418 const struct pci_device_id *pci_id)
3419 {
3420 static int dev;
3421 struct snd_card *card;
3422 struct azx *chip;
3423 bool probe_now;
3424 int err;
3425
3426 if (dev >= SNDRV_CARDS)
3427 return -ENODEV;
3428 if (!enable[dev]) {
3429 dev++;
3430 return -ENOENT;
3431 }
3432
3433 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3434 if (err < 0) {
3435 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
3436 return err;
3437 }
3438
3439 snd_card_set_dev(card, &pci->dev);
3440
3441 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3442 if (err < 0)
3443 goto out_free;
3444 card->private_data = chip;
3445
3446 pci_set_drvdata(pci, card);
3447
3448 err = register_vga_switcheroo(chip);
3449 if (err < 0) {
3450 snd_printk(KERN_ERR SFX
3451 "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
3452 goto out_free;
3453 }
3454
3455 if (check_hdmi_disabled(pci)) {
3456 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
3457 pci_name(pci));
3458 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
3459 chip->disabled = true;
3460 }
3461
3462 probe_now = !chip->disabled;
3463 if (probe_now) {
3464 err = azx_first_init(chip);
3465 if (err < 0)
3466 goto out_free;
3467 }
3468
3469 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3470 if (patch[dev] && *patch[dev]) {
3471 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3472 pci_name(pci), patch[dev]);
3473 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3474 &pci->dev, GFP_KERNEL, card,
3475 azx_firmware_cb);
3476 if (err < 0)
3477 goto out_free;
3478 probe_now = false; /* continued in azx_firmware_cb() */
3479 }
3480 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3481
3482 if (probe_now) {
3483 err = azx_probe_continue(chip);
3484 if (err < 0)
3485 goto out_free;
3486 }
3487
3488 if (pci_dev_run_wake(pci))
3489 pm_runtime_put_noidle(&pci->dev);
3490
3491 dev++;
3492 complete(&chip->probe_wait);
3493 return 0;
3494
3495 out_free:
3496 snd_card_free(card);
3497 pci_set_drvdata(pci, NULL);
3498 return err;
3499 }
3500
3501 static int azx_probe_continue(struct azx *chip)
3502 {
3503 int dev = chip->dev_index;
3504 int err;
3505
3506 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3507 chip->beep_mode = beep_mode[dev];
3508 #endif
3509
3510 /* create codec instances */
3511 err = azx_codec_create(chip, model[dev]);
3512 if (err < 0)
3513 goto out_free;
3514 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3515 if (chip->fw) {
3516 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3517 chip->fw->data);
3518 if (err < 0)
3519 goto out_free;
3520 #ifndef CONFIG_PM
3521 release_firmware(chip->fw); /* no longer needed */
3522 chip->fw = NULL;
3523 #endif
3524 }
3525 #endif
3526 if ((probe_only[dev] & 1) == 0) {
3527 err = azx_codec_configure(chip);
3528 if (err < 0)
3529 goto out_free;
3530 }
3531
3532 /* create PCM streams */
3533 err = snd_hda_build_pcms(chip->bus);
3534 if (err < 0)
3535 goto out_free;
3536
3537 /* create mixer controls */
3538 err = azx_mixer_create(chip);
3539 if (err < 0)
3540 goto out_free;
3541
3542 err = snd_card_register(chip->card);
3543 if (err < 0)
3544 goto out_free;
3545
3546 chip->running = 1;
3547 power_down_all_codecs(chip);
3548 azx_notifier_register(chip);
3549 azx_add_card_list(chip);
3550
3551 return 0;
3552
3553 out_free:
3554 chip->init_failed = 1;
3555 return err;
3556 }
3557
3558 static void azx_remove(struct pci_dev *pci)
3559 {
3560 struct snd_card *card = pci_get_drvdata(pci);
3561
3562 if (pci_dev_run_wake(pci))
3563 pm_runtime_get_noresume(&pci->dev);
3564
3565 if (card)
3566 snd_card_free(card);
3567 pci_set_drvdata(pci, NULL);
3568 }
3569
3570 /* PCI IDs */
3571 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3572 /* CPT */
3573 { PCI_DEVICE(0x8086, 0x1c20),
3574 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3575 /* PBG */
3576 { PCI_DEVICE(0x8086, 0x1d20),
3577 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3578 /* Panther Point */
3579 { PCI_DEVICE(0x8086, 0x1e20),
3580 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3581 /* Lynx Point */
3582 { PCI_DEVICE(0x8086, 0x8c20),
3583 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3584 /* Lynx Point-LP */
3585 { PCI_DEVICE(0x8086, 0x9c20),
3586 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3587 /* Lynx Point-LP */
3588 { PCI_DEVICE(0x8086, 0x9c21),
3589 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3590 /* Haswell */
3591 { PCI_DEVICE(0x8086, 0x0c0c),
3592 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3593 { PCI_DEVICE(0x8086, 0x0d0c),
3594 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3595 /* 5 Series/3400 */
3596 { PCI_DEVICE(0x8086, 0x3b56),
3597 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3598 /* SCH */
3599 { PCI_DEVICE(0x8086, 0x811b),
3600 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3601 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3602 { PCI_DEVICE(0x8086, 0x080a),
3603 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3604 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3605 /* ICH */
3606 { PCI_DEVICE(0x8086, 0x2668),
3607 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3608 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3609 { PCI_DEVICE(0x8086, 0x27d8),
3610 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3611 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3612 { PCI_DEVICE(0x8086, 0x269a),
3613 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3614 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3615 { PCI_DEVICE(0x8086, 0x284b),
3616 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3617 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3618 { PCI_DEVICE(0x8086, 0x293e),
3619 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3620 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3621 { PCI_DEVICE(0x8086, 0x293f),
3622 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3623 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3624 { PCI_DEVICE(0x8086, 0x3a3e),
3625 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3626 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3627 { PCI_DEVICE(0x8086, 0x3a6e),
3628 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3629 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3630 /* Generic Intel */
3631 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3632 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3633 .class_mask = 0xffffff,
3634 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3635 /* ATI SB 450/600/700/800/900 */
3636 { PCI_DEVICE(0x1002, 0x437b),
3637 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3638 { PCI_DEVICE(0x1002, 0x4383),
3639 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3640 /* AMD Hudson */
3641 { PCI_DEVICE(0x1022, 0x780d),
3642 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3643 /* ATI HDMI */
3644 { PCI_DEVICE(0x1002, 0x793b),
3645 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3646 { PCI_DEVICE(0x1002, 0x7919),
3647 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3648 { PCI_DEVICE(0x1002, 0x960f),
3649 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3650 { PCI_DEVICE(0x1002, 0x970f),
3651 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3652 { PCI_DEVICE(0x1002, 0xaa00),
3653 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3654 { PCI_DEVICE(0x1002, 0xaa08),
3655 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3656 { PCI_DEVICE(0x1002, 0xaa10),
3657 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3658 { PCI_DEVICE(0x1002, 0xaa18),
3659 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3660 { PCI_DEVICE(0x1002, 0xaa20),
3661 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3662 { PCI_DEVICE(0x1002, 0xaa28),
3663 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3664 { PCI_DEVICE(0x1002, 0xaa30),
3665 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3666 { PCI_DEVICE(0x1002, 0xaa38),
3667 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3668 { PCI_DEVICE(0x1002, 0xaa40),
3669 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3670 { PCI_DEVICE(0x1002, 0xaa48),
3671 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3672 { PCI_DEVICE(0x1002, 0x9902),
3673 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3674 { PCI_DEVICE(0x1002, 0xaaa0),
3675 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3676 { PCI_DEVICE(0x1002, 0xaaa8),
3677 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3678 { PCI_DEVICE(0x1002, 0xaab0),
3679 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3680 /* VIA VT8251/VT8237A */
3681 { PCI_DEVICE(0x1106, 0x3288),
3682 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3683 /* VIA GFX VT7122/VX900 */
3684 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3685 /* VIA GFX VT6122/VX11 */
3686 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3687 /* SIS966 */
3688 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3689 /* ULI M5461 */
3690 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3691 /* NVIDIA MCP */
3692 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3693 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3694 .class_mask = 0xffffff,
3695 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3696 /* Teradici */
3697 { PCI_DEVICE(0x6549, 0x1200),
3698 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3699 { PCI_DEVICE(0x6549, 0x2200),
3700 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3701 /* Creative X-Fi (CA0110-IBG) */
3702 /* CTHDA chips */
3703 { PCI_DEVICE(0x1102, 0x0010),
3704 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3705 { PCI_DEVICE(0x1102, 0x0012),
3706 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3707 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3708 /* the following entry conflicts with snd-ctxfi driver,
3709 * as ctxfi driver mutates from HD-audio to native mode with
3710 * a special command sequence.
3711 */
3712 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3713 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3714 .class_mask = 0xffffff,
3715 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3716 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3717 #else
3718 /* this entry seems still valid -- i.e. without emu20kx chip */
3719 { PCI_DEVICE(0x1102, 0x0009),
3720 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3721 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3722 #endif
3723 /* Vortex86MX */
3724 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3725 /* VMware HDAudio */
3726 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3727 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3728 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3729 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3730 .class_mask = 0xffffff,
3731 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3732 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3733 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3734 .class_mask = 0xffffff,
3735 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3736 { 0, }
3737 };
3738 MODULE_DEVICE_TABLE(pci, azx_ids);
3739
3740 /* pci_driver definition */
3741 static struct pci_driver azx_driver = {
3742 .name = KBUILD_MODNAME,
3743 .id_table = azx_ids,
3744 .probe = azx_probe,
3745 .remove = azx_remove,
3746 .driver = {
3747 .pm = AZX_PM_OPS,
3748 },
3749 };
3750
3751 module_pci_driver(azx_driver);
Linux kernel - Deliverables
This page took 0.105622 seconds and 4 git commands to generate.