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Merge tag 'for-linus' of git://github.com/gxt/linux
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #ifdef CONFIG_X86
51 /* for snoop control */
52 #include <asm/pgtable.h>
53 #include <asm/cacheflush.h>
54 #endif
55 #include <sound/core.h>
56 #include <sound/initval.h>
57 #include <linux/vgaarb.h>
58 #include <linux/vga_switcheroo.h>
59 #include <linux/firmware.h>
60 #include "hda_codec.h"
61
62
63 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
64 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
65 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
66 static char *model[SNDRV_CARDS];
67 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
68 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
69 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
70 static int probe_only[SNDRV_CARDS];
71 static bool single_cmd;
72 static int enable_msi = -1;
73 #ifdef CONFIG_SND_HDA_PATCH_LOADER
74 static char *patch[SNDRV_CARDS];
75 #endif
76 #ifdef CONFIG_SND_HDA_INPUT_BEEP
77 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
78 CONFIG_SND_HDA_INPUT_BEEP_MODE};
79 #endif
80
81 module_param_array(index, int, NULL, 0444);
82 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
83 module_param_array(id, charp, NULL, 0444);
84 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
85 module_param_array(enable, bool, NULL, 0444);
86 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
87 module_param_array(model, charp, NULL, 0444);
88 MODULE_PARM_DESC(model, "Use the given board model.");
89 module_param_array(position_fix, int, NULL, 0444);
90 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
91 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
92 module_param_array(bdl_pos_adj, int, NULL, 0644);
93 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
94 module_param_array(probe_mask, int, NULL, 0444);
95 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
96 module_param_array(probe_only, int, NULL, 0444);
97 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
98 module_param(single_cmd, bool, 0444);
99 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
100 "(for debugging only).");
101 module_param(enable_msi, bint, 0444);
102 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
103 #ifdef CONFIG_SND_HDA_PATCH_LOADER
104 module_param_array(patch, charp, NULL, 0444);
105 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
106 #endif
107 #ifdef CONFIG_SND_HDA_INPUT_BEEP
108 module_param_array(beep_mode, bool, NULL, 0444);
109 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
110 "(0=off, 1=on) (default=1).");
111 #endif
112
113 #ifdef CONFIG_PM
114 static int param_set_xint(const char *val, const struct kernel_param *kp);
115 static struct kernel_param_ops param_ops_xint = {
116 .set = param_set_xint,
117 .get = param_get_int,
118 };
119 #define param_check_xint param_check_int
120
121 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
122 module_param(power_save, xint, 0644);
123 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
124 "(in second, 0 = disable).");
125
126 /* reset the HD-audio controller in power save mode.
127 * this may give more power-saving, but will take longer time to
128 * wake up.
129 */
130 static bool power_save_controller = 1;
131 module_param(power_save_controller, bool, 0644);
132 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
133 #endif /* CONFIG_PM */
134
135 static int align_buffer_size = -1;
136 module_param(align_buffer_size, bint, 0644);
137 MODULE_PARM_DESC(align_buffer_size,
138 "Force buffer and period sizes to be multiple of 128 bytes.");
139
140 #ifdef CONFIG_X86
141 static bool hda_snoop = true;
142 module_param_named(snoop, hda_snoop, bool, 0444);
143 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
144 #define azx_snoop(chip) (chip)->snoop
145 #else
146 #define hda_snoop true
147 #define azx_snoop(chip) true
148 #endif
149
150
151 MODULE_LICENSE("GPL");
152 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
153 "{Intel, ICH6M},"
154 "{Intel, ICH7},"
155 "{Intel, ESB2},"
156 "{Intel, ICH8},"
157 "{Intel, ICH9},"
158 "{Intel, ICH10},"
159 "{Intel, PCH},"
160 "{Intel, CPT},"
161 "{Intel, PPT},"
162 "{Intel, LPT},"
163 "{Intel, LPT_LP},"
164 "{Intel, HPT},"
165 "{Intel, PBG},"
166 "{Intel, SCH},"
167 "{ATI, SB450},"
168 "{ATI, SB600},"
169 "{ATI, RS600},"
170 "{ATI, RS690},"
171 "{ATI, RS780},"
172 "{ATI, R600},"
173 "{ATI, RV630},"
174 "{ATI, RV610},"
175 "{ATI, RV670},"
176 "{ATI, RV635},"
177 "{ATI, RV620},"
178 "{ATI, RV770},"
179 "{VIA, VT8251},"
180 "{VIA, VT8237A},"
181 "{SiS, SIS966},"
182 "{ULI, M5461}}");
183 MODULE_DESCRIPTION("Intel HDA driver");
184
185 #ifdef CONFIG_SND_VERBOSE_PRINTK
186 #define SFX /* nop */
187 #else
188 #define SFX "hda-intel: "
189 #endif
190
191 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
192 #ifdef CONFIG_SND_HDA_CODEC_HDMI
193 #define SUPPORT_VGA_SWITCHEROO
194 #endif
195 #endif
196
197
198 /*
199 * registers
200 */
201 #define ICH6_REG_GCAP 0x00
202 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
203 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
204 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
205 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
206 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
207 #define ICH6_REG_VMIN 0x02
208 #define ICH6_REG_VMAJ 0x03
209 #define ICH6_REG_OUTPAY 0x04
210 #define ICH6_REG_INPAY 0x06
211 #define ICH6_REG_GCTL 0x08
212 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
213 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
214 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
215 #define ICH6_REG_WAKEEN 0x0c
216 #define ICH6_REG_STATESTS 0x0e
217 #define ICH6_REG_GSTS 0x10
218 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
219 #define ICH6_REG_INTCTL 0x20
220 #define ICH6_REG_INTSTS 0x24
221 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
222 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
223 #define ICH6_REG_SSYNC 0x38
224 #define ICH6_REG_CORBLBASE 0x40
225 #define ICH6_REG_CORBUBASE 0x44
226 #define ICH6_REG_CORBWP 0x48
227 #define ICH6_REG_CORBRP 0x4a
228 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
229 #define ICH6_REG_CORBCTL 0x4c
230 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
231 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
232 #define ICH6_REG_CORBSTS 0x4d
233 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
234 #define ICH6_REG_CORBSIZE 0x4e
235
236 #define ICH6_REG_RIRBLBASE 0x50
237 #define ICH6_REG_RIRBUBASE 0x54
238 #define ICH6_REG_RIRBWP 0x58
239 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
240 #define ICH6_REG_RINTCNT 0x5a
241 #define ICH6_REG_RIRBCTL 0x5c
242 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
243 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
244 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
245 #define ICH6_REG_RIRBSTS 0x5d
246 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
247 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
248 #define ICH6_REG_RIRBSIZE 0x5e
249
250 #define ICH6_REG_IC 0x60
251 #define ICH6_REG_IR 0x64
252 #define ICH6_REG_IRS 0x68
253 #define ICH6_IRS_VALID (1<<1)
254 #define ICH6_IRS_BUSY (1<<0)
255
256 #define ICH6_REG_DPLBASE 0x70
257 #define ICH6_REG_DPUBASE 0x74
258 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
259
260 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
261 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
262
263 /* stream register offsets from stream base */
264 #define ICH6_REG_SD_CTL 0x00
265 #define ICH6_REG_SD_STS 0x03
266 #define ICH6_REG_SD_LPIB 0x04
267 #define ICH6_REG_SD_CBL 0x08
268 #define ICH6_REG_SD_LVI 0x0c
269 #define ICH6_REG_SD_FIFOW 0x0e
270 #define ICH6_REG_SD_FIFOSIZE 0x10
271 #define ICH6_REG_SD_FORMAT 0x12
272 #define ICH6_REG_SD_BDLPL 0x18
273 #define ICH6_REG_SD_BDLPU 0x1c
274
275 /* PCI space */
276 #define ICH6_PCIREG_TCSEL 0x44
277
278 /*
279 * other constants
280 */
281
282 /* max number of SDs */
283 /* ICH, ATI and VIA have 4 playback and 4 capture */
284 #define ICH6_NUM_CAPTURE 4
285 #define ICH6_NUM_PLAYBACK 4
286
287 /* ULI has 6 playback and 5 capture */
288 #define ULI_NUM_CAPTURE 5
289 #define ULI_NUM_PLAYBACK 6
290
291 /* ATI HDMI has 1 playback and 0 capture */
292 #define ATIHDMI_NUM_CAPTURE 0
293 #define ATIHDMI_NUM_PLAYBACK 1
294
295 /* TERA has 4 playback and 3 capture */
296 #define TERA_NUM_CAPTURE 3
297 #define TERA_NUM_PLAYBACK 4
298
299 /* this number is statically defined for simplicity */
300 #define MAX_AZX_DEV 16
301
302 /* max number of fragments - we may use more if allocating more pages for BDL */
303 #define BDL_SIZE 4096
304 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
305 #define AZX_MAX_FRAG 32
306 /* max buffer size - no h/w limit, you can increase as you like */
307 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
308
309 /* RIRB int mask: overrun[2], response[0] */
310 #define RIRB_INT_RESPONSE 0x01
311 #define RIRB_INT_OVERRUN 0x04
312 #define RIRB_INT_MASK 0x05
313
314 /* STATESTS int mask: S3,SD2,SD1,SD0 */
315 #define AZX_MAX_CODECS 8
316 #define AZX_DEFAULT_CODECS 4
317 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
318
319 /* SD_CTL bits */
320 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
321 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
322 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
323 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
324 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
325 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
326 #define SD_CTL_STREAM_TAG_SHIFT 20
327
328 /* SD_CTL and SD_STS */
329 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
330 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
331 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
332 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
333 SD_INT_COMPLETE)
334
335 /* SD_STS */
336 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
337
338 /* INTCTL and INTSTS */
339 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
340 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
341 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
342
343 /* below are so far hardcoded - should read registers in future */
344 #define ICH6_MAX_CORB_ENTRIES 256
345 #define ICH6_MAX_RIRB_ENTRIES 256
346
347 /* position fix mode */
348 enum {
349 POS_FIX_AUTO,
350 POS_FIX_LPIB,
351 POS_FIX_POSBUF,
352 POS_FIX_VIACOMBO,
353 POS_FIX_COMBO,
354 };
355
356 /* Defines for ATI HD Audio support in SB450 south bridge */
357 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
358 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
359
360 /* Defines for Nvidia HDA support */
361 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
362 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
363 #define NVIDIA_HDA_ISTRM_COH 0x4d
364 #define NVIDIA_HDA_OSTRM_COH 0x4c
365 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
366
367 /* Defines for Intel SCH HDA snoop control */
368 #define INTEL_SCH_HDA_DEVC 0x78
369 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
370
371 /* Define IN stream 0 FIFO size offset in VIA controller */
372 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
373 /* Define VIA HD Audio Device ID*/
374 #define VIA_HDAC_DEVICE_ID 0x3288
375
376 /* HD Audio class code */
377 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
378
379 /*
380 */
381
382 struct azx_dev {
383 struct snd_dma_buffer bdl; /* BDL buffer */
384 u32 *posbuf; /* position buffer pointer */
385
386 unsigned int bufsize; /* size of the play buffer in bytes */
387 unsigned int period_bytes; /* size of the period in bytes */
388 unsigned int frags; /* number for period in the play buffer */
389 unsigned int fifo_size; /* FIFO size */
390 unsigned long start_wallclk; /* start + minimum wallclk */
391 unsigned long period_wallclk; /* wallclk for period */
392
393 void __iomem *sd_addr; /* stream descriptor pointer */
394
395 u32 sd_int_sta_mask; /* stream int status mask */
396
397 /* pcm support */
398 struct snd_pcm_substream *substream; /* assigned substream,
399 * set in PCM open
400 */
401 unsigned int format_val; /* format value to be set in the
402 * controller and the codec
403 */
404 unsigned char stream_tag; /* assigned stream */
405 unsigned char index; /* stream index */
406 int assigned_key; /* last device# key assigned to */
407
408 unsigned int opened :1;
409 unsigned int running :1;
410 unsigned int irq_pending :1;
411 /*
412 * For VIA:
413 * A flag to ensure DMA position is 0
414 * when link position is not greater than FIFO size
415 */
416 unsigned int insufficient :1;
417 unsigned int wc_marked:1;
418 unsigned int no_period_wakeup:1;
419 };
420
421 /* CORB/RIRB */
422 struct azx_rb {
423 u32 *buf; /* CORB/RIRB buffer
424 * Each CORB entry is 4byte, RIRB is 8byte
425 */
426 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
427 /* for RIRB */
428 unsigned short rp, wp; /* read/write pointers */
429 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
430 u32 res[AZX_MAX_CODECS]; /* last read value */
431 };
432
433 struct azx_pcm {
434 struct azx *chip;
435 struct snd_pcm *pcm;
436 struct hda_codec *codec;
437 struct hda_pcm_stream *hinfo[2];
438 struct list_head list;
439 };
440
441 struct azx {
442 struct snd_card *card;
443 struct pci_dev *pci;
444 int dev_index;
445
446 /* chip type specific */
447 int driver_type;
448 unsigned int driver_caps;
449 int playback_streams;
450 int playback_index_offset;
451 int capture_streams;
452 int capture_index_offset;
453 int num_streams;
454
455 /* pci resources */
456 unsigned long addr;
457 void __iomem *remap_addr;
458 int irq;
459
460 /* locks */
461 spinlock_t reg_lock;
462 struct mutex open_mutex;
463
464 /* streams (x num_streams) */
465 struct azx_dev *azx_dev;
466
467 /* PCM */
468 struct list_head pcm_list; /* azx_pcm list */
469
470 /* HD codec */
471 unsigned short codec_mask;
472 int codec_probe_mask; /* copied from probe_mask option */
473 struct hda_bus *bus;
474 unsigned int beep_mode;
475
476 /* CORB/RIRB */
477 struct azx_rb corb;
478 struct azx_rb rirb;
479
480 /* CORB/RIRB and position buffers */
481 struct snd_dma_buffer rb;
482 struct snd_dma_buffer posbuf;
483
484 #ifdef CONFIG_SND_HDA_PATCH_LOADER
485 const struct firmware *fw;
486 #endif
487
488 /* flags */
489 int position_fix[2]; /* for both playback/capture streams */
490 int poll_count;
491 unsigned int running :1;
492 unsigned int initialized :1;
493 unsigned int single_cmd :1;
494 unsigned int polling_mode :1;
495 unsigned int msi :1;
496 unsigned int irq_pending_warned :1;
497 unsigned int probing :1; /* codec probing phase */
498 unsigned int snoop:1;
499 unsigned int align_buffer_size:1;
500 unsigned int region_requested:1;
501
502 /* VGA-switcheroo setup */
503 unsigned int use_vga_switcheroo:1;
504 unsigned int vga_switcheroo_registered:1;
505 unsigned int init_failed:1; /* delayed init failed */
506 unsigned int disabled:1; /* disabled by VGA-switcher */
507
508 /* for debugging */
509 unsigned int last_cmd[AZX_MAX_CODECS];
510
511 /* for pending irqs */
512 struct work_struct irq_pending_work;
513
514 /* reboot notifier (for mysterious hangup problem at power-down) */
515 struct notifier_block reboot_notifier;
516
517 /* card list (for power_save trigger) */
518 struct list_head list;
519 };
520
521 /* driver types */
522 enum {
523 AZX_DRIVER_ICH,
524 AZX_DRIVER_PCH,
525 AZX_DRIVER_SCH,
526 AZX_DRIVER_ATI,
527 AZX_DRIVER_ATIHDMI,
528 AZX_DRIVER_ATIHDMI_NS,
529 AZX_DRIVER_VIA,
530 AZX_DRIVER_SIS,
531 AZX_DRIVER_ULI,
532 AZX_DRIVER_NVIDIA,
533 AZX_DRIVER_TERA,
534 AZX_DRIVER_CTX,
535 AZX_DRIVER_CTHDA,
536 AZX_DRIVER_GENERIC,
537 AZX_NUM_DRIVERS, /* keep this as last entry */
538 };
539
540 /* driver quirks (capabilities) */
541 /* bits 0-7 are used for indicating driver type */
542 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
543 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
544 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
545 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
546 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
547 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
548 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
549 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
550 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
551 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
552 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
553 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
554 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
555 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
556 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
557 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
558 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
559
560 /* quirks for ATI SB / AMD Hudson */
561 #define AZX_DCAPS_PRESET_ATI_SB \
562 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
563 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
564
565 /* quirks for ATI/AMD HDMI */
566 #define AZX_DCAPS_PRESET_ATI_HDMI \
567 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
568
569 /* quirks for Nvidia */
570 #define AZX_DCAPS_PRESET_NVIDIA \
571 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
572 AZX_DCAPS_ALIGN_BUFSIZE)
573
574 #define AZX_DCAPS_PRESET_CTHDA \
575 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
576
577 /*
578 * VGA-switcher support
579 */
580 #ifdef SUPPORT_VGA_SWITCHEROO
581 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
582 #else
583 #define use_vga_switcheroo(chip) 0
584 #endif
585
586 #if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
587 #define DELAYED_INIT_MARK
588 #define DELAYED_INITDATA_MARK
589 #else
590 #define DELAYED_INIT_MARK __devinit
591 #define DELAYED_INITDATA_MARK __devinitdata
592 #endif
593
594 static char *driver_short_names[] DELAYED_INITDATA_MARK = {
595 [AZX_DRIVER_ICH] = "HDA Intel",
596 [AZX_DRIVER_PCH] = "HDA Intel PCH",
597 [AZX_DRIVER_SCH] = "HDA Intel MID",
598 [AZX_DRIVER_ATI] = "HDA ATI SB",
599 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
600 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
601 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
602 [AZX_DRIVER_SIS] = "HDA SIS966",
603 [AZX_DRIVER_ULI] = "HDA ULI M5461",
604 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
605 [AZX_DRIVER_TERA] = "HDA Teradici",
606 [AZX_DRIVER_CTX] = "HDA Creative",
607 [AZX_DRIVER_CTHDA] = "HDA Creative",
608 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
609 };
610
611 /*
612 * macros for easy use
613 */
614 #define azx_writel(chip,reg,value) \
615 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
616 #define azx_readl(chip,reg) \
617 readl((chip)->remap_addr + ICH6_REG_##reg)
618 #define azx_writew(chip,reg,value) \
619 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
620 #define azx_readw(chip,reg) \
621 readw((chip)->remap_addr + ICH6_REG_##reg)
622 #define azx_writeb(chip,reg,value) \
623 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
624 #define azx_readb(chip,reg) \
625 readb((chip)->remap_addr + ICH6_REG_##reg)
626
627 #define azx_sd_writel(dev,reg,value) \
628 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
629 #define azx_sd_readl(dev,reg) \
630 readl((dev)->sd_addr + ICH6_REG_##reg)
631 #define azx_sd_writew(dev,reg,value) \
632 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
633 #define azx_sd_readw(dev,reg) \
634 readw((dev)->sd_addr + ICH6_REG_##reg)
635 #define azx_sd_writeb(dev,reg,value) \
636 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
637 #define azx_sd_readb(dev,reg) \
638 readb((dev)->sd_addr + ICH6_REG_##reg)
639
640 /* for pcm support */
641 #define get_azx_dev(substream) (substream->runtime->private_data)
642
643 #ifdef CONFIG_X86
644 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
645 {
646 if (azx_snoop(chip))
647 return;
648 if (addr && size) {
649 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
650 if (on)
651 set_memory_wc((unsigned long)addr, pages);
652 else
653 set_memory_wb((unsigned long)addr, pages);
654 }
655 }
656
657 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
658 bool on)
659 {
660 __mark_pages_wc(chip, buf->area, buf->bytes, on);
661 }
662 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
663 struct snd_pcm_runtime *runtime, bool on)
664 {
665 if (azx_dev->wc_marked != on) {
666 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
667 azx_dev->wc_marked = on;
668 }
669 }
670 #else
671 /* NOP for other archs */
672 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
673 bool on)
674 {
675 }
676 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
677 struct snd_pcm_runtime *runtime, bool on)
678 {
679 }
680 #endif
681
682 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
683 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
684 /*
685 * Interface for HD codec
686 */
687
688 /*
689 * CORB / RIRB interface
690 */
691 static int azx_alloc_cmd_io(struct azx *chip)
692 {
693 int err;
694
695 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
696 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
697 snd_dma_pci_data(chip->pci),
698 PAGE_SIZE, &chip->rb);
699 if (err < 0) {
700 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
701 return err;
702 }
703 mark_pages_wc(chip, &chip->rb, true);
704 return 0;
705 }
706
707 static void azx_init_cmd_io(struct azx *chip)
708 {
709 spin_lock_irq(&chip->reg_lock);
710 /* CORB set up */
711 chip->corb.addr = chip->rb.addr;
712 chip->corb.buf = (u32 *)chip->rb.area;
713 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
714 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
715
716 /* set the corb size to 256 entries (ULI requires explicitly) */
717 azx_writeb(chip, CORBSIZE, 0x02);
718 /* set the corb write pointer to 0 */
719 azx_writew(chip, CORBWP, 0);
720 /* reset the corb hw read pointer */
721 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
722 /* enable corb dma */
723 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
724
725 /* RIRB set up */
726 chip->rirb.addr = chip->rb.addr + 2048;
727 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
728 chip->rirb.wp = chip->rirb.rp = 0;
729 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
730 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
731 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
732
733 /* set the rirb size to 256 entries (ULI requires explicitly) */
734 azx_writeb(chip, RIRBSIZE, 0x02);
735 /* reset the rirb hw write pointer */
736 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
737 /* set N=1, get RIRB response interrupt for new entry */
738 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
739 azx_writew(chip, RINTCNT, 0xc0);
740 else
741 azx_writew(chip, RINTCNT, 1);
742 /* enable rirb dma and response irq */
743 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
744 spin_unlock_irq(&chip->reg_lock);
745 }
746
747 static void azx_free_cmd_io(struct azx *chip)
748 {
749 spin_lock_irq(&chip->reg_lock);
750 /* disable ringbuffer DMAs */
751 azx_writeb(chip, RIRBCTL, 0);
752 azx_writeb(chip, CORBCTL, 0);
753 spin_unlock_irq(&chip->reg_lock);
754 }
755
756 static unsigned int azx_command_addr(u32 cmd)
757 {
758 unsigned int addr = cmd >> 28;
759
760 if (addr >= AZX_MAX_CODECS) {
761 snd_BUG();
762 addr = 0;
763 }
764
765 return addr;
766 }
767
768 static unsigned int azx_response_addr(u32 res)
769 {
770 unsigned int addr = res & 0xf;
771
772 if (addr >= AZX_MAX_CODECS) {
773 snd_BUG();
774 addr = 0;
775 }
776
777 return addr;
778 }
779
780 /* send a command */
781 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
782 {
783 struct azx *chip = bus->private_data;
784 unsigned int addr = azx_command_addr(val);
785 unsigned int wp;
786
787 spin_lock_irq(&chip->reg_lock);
788
789 /* add command to corb */
790 wp = azx_readb(chip, CORBWP);
791 wp++;
792 wp %= ICH6_MAX_CORB_ENTRIES;
793
794 chip->rirb.cmds[addr]++;
795 chip->corb.buf[wp] = cpu_to_le32(val);
796 azx_writel(chip, CORBWP, wp);
797
798 spin_unlock_irq(&chip->reg_lock);
799
800 return 0;
801 }
802
803 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
804
805 /* retrieve RIRB entry - called from interrupt handler */
806 static void azx_update_rirb(struct azx *chip)
807 {
808 unsigned int rp, wp;
809 unsigned int addr;
810 u32 res, res_ex;
811
812 wp = azx_readb(chip, RIRBWP);
813 if (wp == chip->rirb.wp)
814 return;
815 chip->rirb.wp = wp;
816
817 while (chip->rirb.rp != wp) {
818 chip->rirb.rp++;
819 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
820
821 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
822 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
823 res = le32_to_cpu(chip->rirb.buf[rp]);
824 addr = azx_response_addr(res_ex);
825 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
826 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
827 else if (chip->rirb.cmds[addr]) {
828 chip->rirb.res[addr] = res;
829 smp_wmb();
830 chip->rirb.cmds[addr]--;
831 } else
832 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
833 "last cmd=%#08x\n",
834 res, res_ex,
835 chip->last_cmd[addr]);
836 }
837 }
838
839 /* receive a response */
840 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
841 unsigned int addr)
842 {
843 struct azx *chip = bus->private_data;
844 unsigned long timeout;
845 unsigned long loopcounter;
846 int do_poll = 0;
847
848 again:
849 timeout = jiffies + msecs_to_jiffies(1000);
850
851 for (loopcounter = 0;; loopcounter++) {
852 if (chip->polling_mode || do_poll) {
853 spin_lock_irq(&chip->reg_lock);
854 azx_update_rirb(chip);
855 spin_unlock_irq(&chip->reg_lock);
856 }
857 if (!chip->rirb.cmds[addr]) {
858 smp_rmb();
859 bus->rirb_error = 0;
860
861 if (!do_poll)
862 chip->poll_count = 0;
863 return chip->rirb.res[addr]; /* the last value */
864 }
865 if (time_after(jiffies, timeout))
866 break;
867 if (bus->needs_damn_long_delay || loopcounter > 3000)
868 msleep(2); /* temporary workaround */
869 else {
870 udelay(10);
871 cond_resched();
872 }
873 }
874
875 if (!chip->polling_mode && chip->poll_count < 2) {
876 snd_printdd(SFX "azx_get_response timeout, "
877 "polling the codec once: last cmd=0x%08x\n",
878 chip->last_cmd[addr]);
879 do_poll = 1;
880 chip->poll_count++;
881 goto again;
882 }
883
884
885 if (!chip->polling_mode) {
886 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
887 "switching to polling mode: last cmd=0x%08x\n",
888 chip->last_cmd[addr]);
889 chip->polling_mode = 1;
890 goto again;
891 }
892
893 if (chip->msi) {
894 snd_printk(KERN_WARNING SFX "No response from codec, "
895 "disabling MSI: last cmd=0x%08x\n",
896 chip->last_cmd[addr]);
897 free_irq(chip->irq, chip);
898 chip->irq = -1;
899 pci_disable_msi(chip->pci);
900 chip->msi = 0;
901 if (azx_acquire_irq(chip, 1) < 0) {
902 bus->rirb_error = 1;
903 return -1;
904 }
905 goto again;
906 }
907
908 if (chip->probing) {
909 /* If this critical timeout happens during the codec probing
910 * phase, this is likely an access to a non-existing codec
911 * slot. Better to return an error and reset the system.
912 */
913 return -1;
914 }
915
916 /* a fatal communication error; need either to reset or to fallback
917 * to the single_cmd mode
918 */
919 bus->rirb_error = 1;
920 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
921 bus->response_reset = 1;
922 return -1; /* give a chance to retry */
923 }
924
925 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
926 "switching to single_cmd mode: last cmd=0x%08x\n",
927 chip->last_cmd[addr]);
928 chip->single_cmd = 1;
929 bus->response_reset = 0;
930 /* release CORB/RIRB */
931 azx_free_cmd_io(chip);
932 /* disable unsolicited responses */
933 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
934 return -1;
935 }
936
937 /*
938 * Use the single immediate command instead of CORB/RIRB for simplicity
939 *
940 * Note: according to Intel, this is not preferred use. The command was
941 * intended for the BIOS only, and may get confused with unsolicited
942 * responses. So, we shouldn't use it for normal operation from the
943 * driver.
944 * I left the codes, however, for debugging/testing purposes.
945 */
946
947 /* receive a response */
948 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
949 {
950 int timeout = 50;
951
952 while (timeout--) {
953 /* check IRV busy bit */
954 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
955 /* reuse rirb.res as the response return value */
956 chip->rirb.res[addr] = azx_readl(chip, IR);
957 return 0;
958 }
959 udelay(1);
960 }
961 if (printk_ratelimit())
962 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
963 azx_readw(chip, IRS));
964 chip->rirb.res[addr] = -1;
965 return -EIO;
966 }
967
968 /* send a command */
969 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
970 {
971 struct azx *chip = bus->private_data;
972 unsigned int addr = azx_command_addr(val);
973 int timeout = 50;
974
975 bus->rirb_error = 0;
976 while (timeout--) {
977 /* check ICB busy bit */
978 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
979 /* Clear IRV valid bit */
980 azx_writew(chip, IRS, azx_readw(chip, IRS) |
981 ICH6_IRS_VALID);
982 azx_writel(chip, IC, val);
983 azx_writew(chip, IRS, azx_readw(chip, IRS) |
984 ICH6_IRS_BUSY);
985 return azx_single_wait_for_response(chip, addr);
986 }
987 udelay(1);
988 }
989 if (printk_ratelimit())
990 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
991 azx_readw(chip, IRS), val);
992 return -EIO;
993 }
994
995 /* receive a response */
996 static unsigned int azx_single_get_response(struct hda_bus *bus,
997 unsigned int addr)
998 {
999 struct azx *chip = bus->private_data;
1000 return chip->rirb.res[addr];
1001 }
1002
1003 /*
1004 * The below are the main callbacks from hda_codec.
1005 *
1006 * They are just the skeleton to call sub-callbacks according to the
1007 * current setting of chip->single_cmd.
1008 */
1009
1010 /* send a command */
1011 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1012 {
1013 struct azx *chip = bus->private_data;
1014
1015 if (chip->disabled)
1016 return 0;
1017 chip->last_cmd[azx_command_addr(val)] = val;
1018 if (chip->single_cmd)
1019 return azx_single_send_cmd(bus, val);
1020 else
1021 return azx_corb_send_cmd(bus, val);
1022 }
1023
1024 /* get a response */
1025 static unsigned int azx_get_response(struct hda_bus *bus,
1026 unsigned int addr)
1027 {
1028 struct azx *chip = bus->private_data;
1029 if (chip->disabled)
1030 return 0;
1031 if (chip->single_cmd)
1032 return azx_single_get_response(bus, addr);
1033 else
1034 return azx_rirb_get_response(bus, addr);
1035 }
1036
1037 #ifdef CONFIG_PM
1038 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1039 #endif
1040
1041 /* reset codec link */
1042 static int azx_reset(struct azx *chip, int full_reset)
1043 {
1044 int count;
1045
1046 if (!full_reset)
1047 goto __skip;
1048
1049 /* clear STATESTS */
1050 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1051
1052 /* reset controller */
1053 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1054
1055 count = 50;
1056 while (azx_readb(chip, GCTL) && --count)
1057 msleep(1);
1058
1059 /* delay for >= 100us for codec PLL to settle per spec
1060 * Rev 0.9 section 5.5.1
1061 */
1062 msleep(1);
1063
1064 /* Bring controller out of reset */
1065 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1066
1067 count = 50;
1068 while (!azx_readb(chip, GCTL) && --count)
1069 msleep(1);
1070
1071 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1072 msleep(1);
1073
1074 __skip:
1075 /* check to see if controller is ready */
1076 if (!azx_readb(chip, GCTL)) {
1077 snd_printd(SFX "azx_reset: controller not ready!\n");
1078 return -EBUSY;
1079 }
1080
1081 /* Accept unsolicited responses */
1082 if (!chip->single_cmd)
1083 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1084 ICH6_GCTL_UNSOL);
1085
1086 /* detect codecs */
1087 if (!chip->codec_mask) {
1088 chip->codec_mask = azx_readw(chip, STATESTS);
1089 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1090 }
1091
1092 return 0;
1093 }
1094
1095
1096 /*
1097 * Lowlevel interface
1098 */
1099
1100 /* enable interrupts */
1101 static void azx_int_enable(struct azx *chip)
1102 {
1103 /* enable controller CIE and GIE */
1104 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1105 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1106 }
1107
1108 /* disable interrupts */
1109 static void azx_int_disable(struct azx *chip)
1110 {
1111 int i;
1112
1113 /* disable interrupts in stream descriptor */
1114 for (i = 0; i < chip->num_streams; i++) {
1115 struct azx_dev *azx_dev = &chip->azx_dev[i];
1116 azx_sd_writeb(azx_dev, SD_CTL,
1117 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1118 }
1119
1120 /* disable SIE for all streams */
1121 azx_writeb(chip, INTCTL, 0);
1122
1123 /* disable controller CIE and GIE */
1124 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1125 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1126 }
1127
1128 /* clear interrupts */
1129 static void azx_int_clear(struct azx *chip)
1130 {
1131 int i;
1132
1133 /* clear stream status */
1134 for (i = 0; i < chip->num_streams; i++) {
1135 struct azx_dev *azx_dev = &chip->azx_dev[i];
1136 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1137 }
1138
1139 /* clear STATESTS */
1140 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1141
1142 /* clear rirb status */
1143 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1144
1145 /* clear int status */
1146 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1147 }
1148
1149 /* start a stream */
1150 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1151 {
1152 /*
1153 * Before stream start, initialize parameter
1154 */
1155 azx_dev->insufficient = 1;
1156
1157 /* enable SIE */
1158 azx_writel(chip, INTCTL,
1159 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1160 /* set DMA start and interrupt mask */
1161 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1162 SD_CTL_DMA_START | SD_INT_MASK);
1163 }
1164
1165 /* stop DMA */
1166 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1167 {
1168 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1169 ~(SD_CTL_DMA_START | SD_INT_MASK));
1170 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1171 }
1172
1173 /* stop a stream */
1174 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1175 {
1176 azx_stream_clear(chip, azx_dev);
1177 /* disable SIE */
1178 azx_writel(chip, INTCTL,
1179 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1180 }
1181
1182
1183 /*
1184 * reset and start the controller registers
1185 */
1186 static void azx_init_chip(struct azx *chip, int full_reset)
1187 {
1188 if (chip->initialized)
1189 return;
1190
1191 /* reset controller */
1192 azx_reset(chip, full_reset);
1193
1194 /* initialize interrupts */
1195 azx_int_clear(chip);
1196 azx_int_enable(chip);
1197
1198 /* initialize the codec command I/O */
1199 if (!chip->single_cmd)
1200 azx_init_cmd_io(chip);
1201
1202 /* program the position buffer */
1203 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1204 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1205
1206 chip->initialized = 1;
1207 }
1208
1209 /*
1210 * initialize the PCI registers
1211 */
1212 /* update bits in a PCI register byte */
1213 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1214 unsigned char mask, unsigned char val)
1215 {
1216 unsigned char data;
1217
1218 pci_read_config_byte(pci, reg, &data);
1219 data &= ~mask;
1220 data |= (val & mask);
1221 pci_write_config_byte(pci, reg, data);
1222 }
1223
1224 static void azx_init_pci(struct azx *chip)
1225 {
1226 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1227 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1228 * Ensuring these bits are 0 clears playback static on some HD Audio
1229 * codecs.
1230 * The PCI register TCSEL is defined in the Intel manuals.
1231 */
1232 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1233 snd_printdd(SFX "Clearing TCSEL\n");
1234 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1235 }
1236
1237 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1238 * we need to enable snoop.
1239 */
1240 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1241 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1242 update_pci_byte(chip->pci,
1243 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1244 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1245 }
1246
1247 /* For NVIDIA HDA, enable snoop */
1248 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1249 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1250 update_pci_byte(chip->pci,
1251 NVIDIA_HDA_TRANSREG_ADDR,
1252 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1253 update_pci_byte(chip->pci,
1254 NVIDIA_HDA_ISTRM_COH,
1255 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1256 update_pci_byte(chip->pci,
1257 NVIDIA_HDA_OSTRM_COH,
1258 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1259 }
1260
1261 /* Enable SCH/PCH snoop if needed */
1262 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1263 unsigned short snoop;
1264 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1265 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1266 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1267 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1268 if (!azx_snoop(chip))
1269 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1270 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1271 pci_read_config_word(chip->pci,
1272 INTEL_SCH_HDA_DEVC, &snoop);
1273 }
1274 snd_printdd(SFX "SCH snoop: %s\n",
1275 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1276 ? "Disabled" : "Enabled");
1277 }
1278 }
1279
1280
1281 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1282
1283 /*
1284 * interrupt handler
1285 */
1286 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1287 {
1288 struct azx *chip = dev_id;
1289 struct azx_dev *azx_dev;
1290 u32 status;
1291 u8 sd_status;
1292 int i, ok;
1293
1294 #ifdef CONFIG_PM_RUNTIME
1295 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1296 return IRQ_NONE;
1297 #endif
1298
1299 spin_lock(&chip->reg_lock);
1300
1301 if (chip->disabled) {
1302 spin_unlock(&chip->reg_lock);
1303 return IRQ_NONE;
1304 }
1305
1306 status = azx_readl(chip, INTSTS);
1307 if (status == 0) {
1308 spin_unlock(&chip->reg_lock);
1309 return IRQ_NONE;
1310 }
1311
1312 for (i = 0; i < chip->num_streams; i++) {
1313 azx_dev = &chip->azx_dev[i];
1314 if (status & azx_dev->sd_int_sta_mask) {
1315 sd_status = azx_sd_readb(azx_dev, SD_STS);
1316 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1317 if (!azx_dev->substream || !azx_dev->running ||
1318 !(sd_status & SD_INT_COMPLETE))
1319 continue;
1320 /* check whether this IRQ is really acceptable */
1321 ok = azx_position_ok(chip, azx_dev);
1322 if (ok == 1) {
1323 azx_dev->irq_pending = 0;
1324 spin_unlock(&chip->reg_lock);
1325 snd_pcm_period_elapsed(azx_dev->substream);
1326 spin_lock(&chip->reg_lock);
1327 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1328 /* bogus IRQ, process it later */
1329 azx_dev->irq_pending = 1;
1330 queue_work(chip->bus->workq,
1331 &chip->irq_pending_work);
1332 }
1333 }
1334 }
1335
1336 /* clear rirb int */
1337 status = azx_readb(chip, RIRBSTS);
1338 if (status & RIRB_INT_MASK) {
1339 if (status & RIRB_INT_RESPONSE) {
1340 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1341 udelay(80);
1342 azx_update_rirb(chip);
1343 }
1344 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1345 }
1346
1347 #if 0
1348 /* clear state status int */
1349 if (azx_readb(chip, STATESTS) & 0x04)
1350 azx_writeb(chip, STATESTS, 0x04);
1351 #endif
1352 spin_unlock(&chip->reg_lock);
1353
1354 return IRQ_HANDLED;
1355 }
1356
1357
1358 /*
1359 * set up a BDL entry
1360 */
1361 static int setup_bdle(struct azx *chip,
1362 struct snd_pcm_substream *substream,
1363 struct azx_dev *azx_dev, u32 **bdlp,
1364 int ofs, int size, int with_ioc)
1365 {
1366 u32 *bdl = *bdlp;
1367
1368 while (size > 0) {
1369 dma_addr_t addr;
1370 int chunk;
1371
1372 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1373 return -EINVAL;
1374
1375 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1376 /* program the address field of the BDL entry */
1377 bdl[0] = cpu_to_le32((u32)addr);
1378 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1379 /* program the size field of the BDL entry */
1380 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1381 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1382 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1383 u32 remain = 0x1000 - (ofs & 0xfff);
1384 if (chunk > remain)
1385 chunk = remain;
1386 }
1387 bdl[2] = cpu_to_le32(chunk);
1388 /* program the IOC to enable interrupt
1389 * only when the whole fragment is processed
1390 */
1391 size -= chunk;
1392 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1393 bdl += 4;
1394 azx_dev->frags++;
1395 ofs += chunk;
1396 }
1397 *bdlp = bdl;
1398 return ofs;
1399 }
1400
1401 /*
1402 * set up BDL entries
1403 */
1404 static int azx_setup_periods(struct azx *chip,
1405 struct snd_pcm_substream *substream,
1406 struct azx_dev *azx_dev)
1407 {
1408 u32 *bdl;
1409 int i, ofs, periods, period_bytes;
1410 int pos_adj;
1411
1412 /* reset BDL address */
1413 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1414 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1415
1416 period_bytes = azx_dev->period_bytes;
1417 periods = azx_dev->bufsize / period_bytes;
1418
1419 /* program the initial BDL entries */
1420 bdl = (u32 *)azx_dev->bdl.area;
1421 ofs = 0;
1422 azx_dev->frags = 0;
1423 pos_adj = bdl_pos_adj[chip->dev_index];
1424 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1425 struct snd_pcm_runtime *runtime = substream->runtime;
1426 int pos_align = pos_adj;
1427 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1428 if (!pos_adj)
1429 pos_adj = pos_align;
1430 else
1431 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1432 pos_align;
1433 pos_adj = frames_to_bytes(runtime, pos_adj);
1434 if (pos_adj >= period_bytes) {
1435 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1436 bdl_pos_adj[chip->dev_index]);
1437 pos_adj = 0;
1438 } else {
1439 ofs = setup_bdle(chip, substream, azx_dev,
1440 &bdl, ofs, pos_adj, true);
1441 if (ofs < 0)
1442 goto error;
1443 }
1444 } else
1445 pos_adj = 0;
1446 for (i = 0; i < periods; i++) {
1447 if (i == periods - 1 && pos_adj)
1448 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1449 period_bytes - pos_adj, 0);
1450 else
1451 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1452 period_bytes,
1453 !azx_dev->no_period_wakeup);
1454 if (ofs < 0)
1455 goto error;
1456 }
1457 return 0;
1458
1459 error:
1460 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1461 azx_dev->bufsize, period_bytes);
1462 return -EINVAL;
1463 }
1464
1465 /* reset stream */
1466 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1467 {
1468 unsigned char val;
1469 int timeout;
1470
1471 azx_stream_clear(chip, azx_dev);
1472
1473 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1474 SD_CTL_STREAM_RESET);
1475 udelay(3);
1476 timeout = 300;
1477 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1478 --timeout)
1479 ;
1480 val &= ~SD_CTL_STREAM_RESET;
1481 azx_sd_writeb(azx_dev, SD_CTL, val);
1482 udelay(3);
1483
1484 timeout = 300;
1485 /* waiting for hardware to report that the stream is out of reset */
1486 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1487 --timeout)
1488 ;
1489
1490 /* reset first position - may not be synced with hw at this time */
1491 *azx_dev->posbuf = 0;
1492 }
1493
1494 /*
1495 * set up the SD for streaming
1496 */
1497 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1498 {
1499 unsigned int val;
1500 /* make sure the run bit is zero for SD */
1501 azx_stream_clear(chip, azx_dev);
1502 /* program the stream_tag */
1503 val = azx_sd_readl(azx_dev, SD_CTL);
1504 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1505 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1506 if (!azx_snoop(chip))
1507 val |= SD_CTL_TRAFFIC_PRIO;
1508 azx_sd_writel(azx_dev, SD_CTL, val);
1509
1510 /* program the length of samples in cyclic buffer */
1511 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1512
1513 /* program the stream format */
1514 /* this value needs to be the same as the one programmed */
1515 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1516
1517 /* program the stream LVI (last valid index) of the BDL */
1518 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1519
1520 /* program the BDL address */
1521 /* lower BDL address */
1522 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1523 /* upper BDL address */
1524 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1525
1526 /* enable the position buffer */
1527 if (chip->position_fix[0] != POS_FIX_LPIB ||
1528 chip->position_fix[1] != POS_FIX_LPIB) {
1529 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1530 azx_writel(chip, DPLBASE,
1531 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1532 }
1533
1534 /* set the interrupt enable bits in the descriptor control register */
1535 azx_sd_writel(azx_dev, SD_CTL,
1536 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1537
1538 return 0;
1539 }
1540
1541 /*
1542 * Probe the given codec address
1543 */
1544 static int probe_codec(struct azx *chip, int addr)
1545 {
1546 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1547 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1548 unsigned int res;
1549
1550 mutex_lock(&chip->bus->cmd_mutex);
1551 chip->probing = 1;
1552 azx_send_cmd(chip->bus, cmd);
1553 res = azx_get_response(chip->bus, addr);
1554 chip->probing = 0;
1555 mutex_unlock(&chip->bus->cmd_mutex);
1556 if (res == -1)
1557 return -EIO;
1558 snd_printdd(SFX "codec #%d probed OK\n", addr);
1559 return 0;
1560 }
1561
1562 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1563 struct hda_pcm *cpcm);
1564 static void azx_stop_chip(struct azx *chip);
1565
1566 static void azx_bus_reset(struct hda_bus *bus)
1567 {
1568 struct azx *chip = bus->private_data;
1569
1570 bus->in_reset = 1;
1571 azx_stop_chip(chip);
1572 azx_init_chip(chip, 1);
1573 #ifdef CONFIG_PM
1574 if (chip->initialized) {
1575 struct azx_pcm *p;
1576 list_for_each_entry(p, &chip->pcm_list, list)
1577 snd_pcm_suspend_all(p->pcm);
1578 snd_hda_suspend(chip->bus);
1579 snd_hda_resume(chip->bus);
1580 }
1581 #endif
1582 bus->in_reset = 0;
1583 }
1584
1585 /*
1586 * Codec initialization
1587 */
1588
1589 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1590 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
1591 [AZX_DRIVER_NVIDIA] = 8,
1592 [AZX_DRIVER_TERA] = 1,
1593 };
1594
1595 static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1596 {
1597 struct hda_bus_template bus_temp;
1598 int c, codecs, err;
1599 int max_slots;
1600
1601 memset(&bus_temp, 0, sizeof(bus_temp));
1602 bus_temp.private_data = chip;
1603 bus_temp.modelname = model;
1604 bus_temp.pci = chip->pci;
1605 bus_temp.ops.command = azx_send_cmd;
1606 bus_temp.ops.get_response = azx_get_response;
1607 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1608 bus_temp.ops.bus_reset = azx_bus_reset;
1609 #ifdef CONFIG_PM
1610 bus_temp.power_save = &power_save;
1611 bus_temp.ops.pm_notify = azx_power_notify;
1612 #endif
1613
1614 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1615 if (err < 0)
1616 return err;
1617
1618 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1619 snd_printd(SFX "Enable delay in RIRB handling\n");
1620 chip->bus->needs_damn_long_delay = 1;
1621 }
1622
1623 codecs = 0;
1624 max_slots = azx_max_codecs[chip->driver_type];
1625 if (!max_slots)
1626 max_slots = AZX_DEFAULT_CODECS;
1627
1628 /* First try to probe all given codec slots */
1629 for (c = 0; c < max_slots; c++) {
1630 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1631 if (probe_codec(chip, c) < 0) {
1632 /* Some BIOSen give you wrong codec addresses
1633 * that don't exist
1634 */
1635 snd_printk(KERN_WARNING SFX
1636 "Codec #%d probe error; "
1637 "disabling it...\n", c);
1638 chip->codec_mask &= ~(1 << c);
1639 /* More badly, accessing to a non-existing
1640 * codec often screws up the controller chip,
1641 * and disturbs the further communications.
1642 * Thus if an error occurs during probing,
1643 * better to reset the controller chip to
1644 * get back to the sanity state.
1645 */
1646 azx_stop_chip(chip);
1647 azx_init_chip(chip, 1);
1648 }
1649 }
1650 }
1651
1652 /* AMD chipsets often cause the communication stalls upon certain
1653 * sequence like the pin-detection. It seems that forcing the synced
1654 * access works around the stall. Grrr...
1655 */
1656 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1657 snd_printd(SFX "Enable sync_write for stable communication\n");
1658 chip->bus->sync_write = 1;
1659 chip->bus->allow_bus_reset = 1;
1660 }
1661
1662 /* Then create codec instances */
1663 for (c = 0; c < max_slots; c++) {
1664 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1665 struct hda_codec *codec;
1666 err = snd_hda_codec_new(chip->bus, c, &codec);
1667 if (err < 0)
1668 continue;
1669 codec->beep_mode = chip->beep_mode;
1670 codecs++;
1671 }
1672 }
1673 if (!codecs) {
1674 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1675 return -ENXIO;
1676 }
1677 return 0;
1678 }
1679
1680 /* configure each codec instance */
1681 static int __devinit azx_codec_configure(struct azx *chip)
1682 {
1683 struct hda_codec *codec;
1684 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1685 snd_hda_codec_configure(codec);
1686 }
1687 return 0;
1688 }
1689
1690
1691 /*
1692 * PCM support
1693 */
1694
1695 /* assign a stream for the PCM */
1696 static inline struct azx_dev *
1697 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1698 {
1699 int dev, i, nums;
1700 struct azx_dev *res = NULL;
1701 /* make a non-zero unique key for the substream */
1702 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1703 (substream->stream + 1);
1704
1705 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1706 dev = chip->playback_index_offset;
1707 nums = chip->playback_streams;
1708 } else {
1709 dev = chip->capture_index_offset;
1710 nums = chip->capture_streams;
1711 }
1712 for (i = 0; i < nums; i++, dev++)
1713 if (!chip->azx_dev[dev].opened) {
1714 res = &chip->azx_dev[dev];
1715 if (res->assigned_key == key)
1716 break;
1717 }
1718 if (res) {
1719 res->opened = 1;
1720 res->assigned_key = key;
1721 }
1722 return res;
1723 }
1724
1725 /* release the assigned stream */
1726 static inline void azx_release_device(struct azx_dev *azx_dev)
1727 {
1728 azx_dev->opened = 0;
1729 }
1730
1731 static struct snd_pcm_hardware azx_pcm_hw = {
1732 .info = (SNDRV_PCM_INFO_MMAP |
1733 SNDRV_PCM_INFO_INTERLEAVED |
1734 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1735 SNDRV_PCM_INFO_MMAP_VALID |
1736 /* No full-resume yet implemented */
1737 /* SNDRV_PCM_INFO_RESUME |*/
1738 SNDRV_PCM_INFO_PAUSE |
1739 SNDRV_PCM_INFO_SYNC_START |
1740 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1741 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1742 .rates = SNDRV_PCM_RATE_48000,
1743 .rate_min = 48000,
1744 .rate_max = 48000,
1745 .channels_min = 2,
1746 .channels_max = 2,
1747 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1748 .period_bytes_min = 128,
1749 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1750 .periods_min = 2,
1751 .periods_max = AZX_MAX_FRAG,
1752 .fifo_size = 0,
1753 };
1754
1755 static int azx_pcm_open(struct snd_pcm_substream *substream)
1756 {
1757 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1758 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1759 struct azx *chip = apcm->chip;
1760 struct azx_dev *azx_dev;
1761 struct snd_pcm_runtime *runtime = substream->runtime;
1762 unsigned long flags;
1763 int err;
1764 int buff_step;
1765
1766 mutex_lock(&chip->open_mutex);
1767 azx_dev = azx_assign_device(chip, substream);
1768 if (azx_dev == NULL) {
1769 mutex_unlock(&chip->open_mutex);
1770 return -EBUSY;
1771 }
1772 runtime->hw = azx_pcm_hw;
1773 runtime->hw.channels_min = hinfo->channels_min;
1774 runtime->hw.channels_max = hinfo->channels_max;
1775 runtime->hw.formats = hinfo->formats;
1776 runtime->hw.rates = hinfo->rates;
1777 snd_pcm_limit_hw_rates(runtime);
1778 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1779 if (chip->align_buffer_size)
1780 /* constrain buffer sizes to be multiple of 128
1781 bytes. This is more efficient in terms of memory
1782 access but isn't required by the HDA spec and
1783 prevents users from specifying exact period/buffer
1784 sizes. For example for 44.1kHz, a period size set
1785 to 20ms will be rounded to 19.59ms. */
1786 buff_step = 128;
1787 else
1788 /* Don't enforce steps on buffer sizes, still need to
1789 be multiple of 4 bytes (HDA spec). Tested on Intel
1790 HDA controllers, may not work on all devices where
1791 option needs to be disabled */
1792 buff_step = 4;
1793
1794 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1795 buff_step);
1796 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1797 buff_step);
1798 snd_hda_power_up_d3wait(apcm->codec);
1799 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1800 if (err < 0) {
1801 azx_release_device(azx_dev);
1802 snd_hda_power_down(apcm->codec);
1803 mutex_unlock(&chip->open_mutex);
1804 return err;
1805 }
1806 snd_pcm_limit_hw_rates(runtime);
1807 /* sanity check */
1808 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1809 snd_BUG_ON(!runtime->hw.channels_max) ||
1810 snd_BUG_ON(!runtime->hw.formats) ||
1811 snd_BUG_ON(!runtime->hw.rates)) {
1812 azx_release_device(azx_dev);
1813 hinfo->ops.close(hinfo, apcm->codec, substream);
1814 snd_hda_power_down(apcm->codec);
1815 mutex_unlock(&chip->open_mutex);
1816 return -EINVAL;
1817 }
1818 spin_lock_irqsave(&chip->reg_lock, flags);
1819 azx_dev->substream = substream;
1820 azx_dev->running = 0;
1821 spin_unlock_irqrestore(&chip->reg_lock, flags);
1822
1823 runtime->private_data = azx_dev;
1824 snd_pcm_set_sync(substream);
1825 mutex_unlock(&chip->open_mutex);
1826 return 0;
1827 }
1828
1829 static int azx_pcm_close(struct snd_pcm_substream *substream)
1830 {
1831 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1832 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1833 struct azx *chip = apcm->chip;
1834 struct azx_dev *azx_dev = get_azx_dev(substream);
1835 unsigned long flags;
1836
1837 mutex_lock(&chip->open_mutex);
1838 spin_lock_irqsave(&chip->reg_lock, flags);
1839 azx_dev->substream = NULL;
1840 azx_dev->running = 0;
1841 spin_unlock_irqrestore(&chip->reg_lock, flags);
1842 azx_release_device(azx_dev);
1843 hinfo->ops.close(hinfo, apcm->codec, substream);
1844 snd_hda_power_down(apcm->codec);
1845 mutex_unlock(&chip->open_mutex);
1846 return 0;
1847 }
1848
1849 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1850 struct snd_pcm_hw_params *hw_params)
1851 {
1852 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1853 struct azx *chip = apcm->chip;
1854 struct snd_pcm_runtime *runtime = substream->runtime;
1855 struct azx_dev *azx_dev = get_azx_dev(substream);
1856 int ret;
1857
1858 mark_runtime_wc(chip, azx_dev, runtime, false);
1859 azx_dev->bufsize = 0;
1860 azx_dev->period_bytes = 0;
1861 azx_dev->format_val = 0;
1862 ret = snd_pcm_lib_malloc_pages(substream,
1863 params_buffer_bytes(hw_params));
1864 if (ret < 0)
1865 return ret;
1866 mark_runtime_wc(chip, azx_dev, runtime, true);
1867 return ret;
1868 }
1869
1870 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1871 {
1872 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1873 struct azx_dev *azx_dev = get_azx_dev(substream);
1874 struct azx *chip = apcm->chip;
1875 struct snd_pcm_runtime *runtime = substream->runtime;
1876 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1877
1878 /* reset BDL address */
1879 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1880 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1881 azx_sd_writel(azx_dev, SD_CTL, 0);
1882 azx_dev->bufsize = 0;
1883 azx_dev->period_bytes = 0;
1884 azx_dev->format_val = 0;
1885
1886 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1887
1888 mark_runtime_wc(chip, azx_dev, runtime, false);
1889 return snd_pcm_lib_free_pages(substream);
1890 }
1891
1892 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1893 {
1894 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1895 struct azx *chip = apcm->chip;
1896 struct azx_dev *azx_dev = get_azx_dev(substream);
1897 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1898 struct snd_pcm_runtime *runtime = substream->runtime;
1899 unsigned int bufsize, period_bytes, format_val, stream_tag;
1900 int err;
1901 struct hda_spdif_out *spdif =
1902 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1903 unsigned short ctls = spdif ? spdif->ctls : 0;
1904
1905 azx_stream_reset(chip, azx_dev);
1906 format_val = snd_hda_calc_stream_format(runtime->rate,
1907 runtime->channels,
1908 runtime->format,
1909 hinfo->maxbps,
1910 ctls);
1911 if (!format_val) {
1912 snd_printk(KERN_ERR SFX
1913 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1914 runtime->rate, runtime->channels, runtime->format);
1915 return -EINVAL;
1916 }
1917
1918 bufsize = snd_pcm_lib_buffer_bytes(substream);
1919 period_bytes = snd_pcm_lib_period_bytes(substream);
1920
1921 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1922 bufsize, format_val);
1923
1924 if (bufsize != azx_dev->bufsize ||
1925 period_bytes != azx_dev->period_bytes ||
1926 format_val != azx_dev->format_val ||
1927 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
1928 azx_dev->bufsize = bufsize;
1929 azx_dev->period_bytes = period_bytes;
1930 azx_dev->format_val = format_val;
1931 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
1932 err = azx_setup_periods(chip, substream, azx_dev);
1933 if (err < 0)
1934 return err;
1935 }
1936
1937 /* wallclk has 24Mhz clock source */
1938 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1939 runtime->rate) * 1000);
1940 azx_setup_controller(chip, azx_dev);
1941 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1942 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1943 else
1944 azx_dev->fifo_size = 0;
1945
1946 stream_tag = azx_dev->stream_tag;
1947 /* CA-IBG chips need the playback stream starting from 1 */
1948 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1949 stream_tag > chip->capture_streams)
1950 stream_tag -= chip->capture_streams;
1951 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1952 azx_dev->format_val, substream);
1953 }
1954
1955 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1956 {
1957 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1958 struct azx *chip = apcm->chip;
1959 struct azx_dev *azx_dev;
1960 struct snd_pcm_substream *s;
1961 int rstart = 0, start, nsync = 0, sbits = 0;
1962 int nwait, timeout;
1963
1964 switch (cmd) {
1965 case SNDRV_PCM_TRIGGER_START:
1966 rstart = 1;
1967 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1968 case SNDRV_PCM_TRIGGER_RESUME:
1969 start = 1;
1970 break;
1971 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1972 case SNDRV_PCM_TRIGGER_SUSPEND:
1973 case SNDRV_PCM_TRIGGER_STOP:
1974 start = 0;
1975 break;
1976 default:
1977 return -EINVAL;
1978 }
1979
1980 snd_pcm_group_for_each_entry(s, substream) {
1981 if (s->pcm->card != substream->pcm->card)
1982 continue;
1983 azx_dev = get_azx_dev(s);
1984 sbits |= 1 << azx_dev->index;
1985 nsync++;
1986 snd_pcm_trigger_done(s, substream);
1987 }
1988
1989 spin_lock(&chip->reg_lock);
1990
1991 /* first, set SYNC bits of corresponding streams */
1992 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1993 azx_writel(chip, OLD_SSYNC,
1994 azx_readl(chip, OLD_SSYNC) | sbits);
1995 else
1996 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1997
1998 snd_pcm_group_for_each_entry(s, substream) {
1999 if (s->pcm->card != substream->pcm->card)
2000 continue;
2001 azx_dev = get_azx_dev(s);
2002 if (start) {
2003 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2004 if (!rstart)
2005 azx_dev->start_wallclk -=
2006 azx_dev->period_wallclk;
2007 azx_stream_start(chip, azx_dev);
2008 } else {
2009 azx_stream_stop(chip, azx_dev);
2010 }
2011 azx_dev->running = start;
2012 }
2013 spin_unlock(&chip->reg_lock);
2014 if (start) {
2015 /* wait until all FIFOs get ready */
2016 for (timeout = 5000; timeout; timeout--) {
2017 nwait = 0;
2018 snd_pcm_group_for_each_entry(s, substream) {
2019 if (s->pcm->card != substream->pcm->card)
2020 continue;
2021 azx_dev = get_azx_dev(s);
2022 if (!(azx_sd_readb(azx_dev, SD_STS) &
2023 SD_STS_FIFO_READY))
2024 nwait++;
2025 }
2026 if (!nwait)
2027 break;
2028 cpu_relax();
2029 }
2030 } else {
2031 /* wait until all RUN bits are cleared */
2032 for (timeout = 5000; timeout; timeout--) {
2033 nwait = 0;
2034 snd_pcm_group_for_each_entry(s, substream) {
2035 if (s->pcm->card != substream->pcm->card)
2036 continue;
2037 azx_dev = get_azx_dev(s);
2038 if (azx_sd_readb(azx_dev, SD_CTL) &
2039 SD_CTL_DMA_START)
2040 nwait++;
2041 }
2042 if (!nwait)
2043 break;
2044 cpu_relax();
2045 }
2046 }
2047 spin_lock(&chip->reg_lock);
2048 /* reset SYNC bits */
2049 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2050 azx_writel(chip, OLD_SSYNC,
2051 azx_readl(chip, OLD_SSYNC) & ~sbits);
2052 else
2053 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2054 spin_unlock(&chip->reg_lock);
2055 return 0;
2056 }
2057
2058 /* get the current DMA position with correction on VIA chips */
2059 static unsigned int azx_via_get_position(struct azx *chip,
2060 struct azx_dev *azx_dev)
2061 {
2062 unsigned int link_pos, mini_pos, bound_pos;
2063 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2064 unsigned int fifo_size;
2065
2066 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2067 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2068 /* Playback, no problem using link position */
2069 return link_pos;
2070 }
2071
2072 /* Capture */
2073 /* For new chipset,
2074 * use mod to get the DMA position just like old chipset
2075 */
2076 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2077 mod_dma_pos %= azx_dev->period_bytes;
2078
2079 /* azx_dev->fifo_size can't get FIFO size of in stream.
2080 * Get from base address + offset.
2081 */
2082 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2083
2084 if (azx_dev->insufficient) {
2085 /* Link position never gather than FIFO size */
2086 if (link_pos <= fifo_size)
2087 return 0;
2088
2089 azx_dev->insufficient = 0;
2090 }
2091
2092 if (link_pos <= fifo_size)
2093 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2094 else
2095 mini_pos = link_pos - fifo_size;
2096
2097 /* Find nearest previous boudary */
2098 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2099 mod_link_pos = link_pos % azx_dev->period_bytes;
2100 if (mod_link_pos >= fifo_size)
2101 bound_pos = link_pos - mod_link_pos;
2102 else if (mod_dma_pos >= mod_mini_pos)
2103 bound_pos = mini_pos - mod_mini_pos;
2104 else {
2105 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2106 if (bound_pos >= azx_dev->bufsize)
2107 bound_pos = 0;
2108 }
2109
2110 /* Calculate real DMA position we want */
2111 return bound_pos + mod_dma_pos;
2112 }
2113
2114 static unsigned int azx_get_position(struct azx *chip,
2115 struct azx_dev *azx_dev,
2116 bool with_check)
2117 {
2118 unsigned int pos;
2119 int stream = azx_dev->substream->stream;
2120
2121 switch (chip->position_fix[stream]) {
2122 case POS_FIX_LPIB:
2123 /* read LPIB */
2124 pos = azx_sd_readl(azx_dev, SD_LPIB);
2125 break;
2126 case POS_FIX_VIACOMBO:
2127 pos = azx_via_get_position(chip, azx_dev);
2128 break;
2129 default:
2130 /* use the position buffer */
2131 pos = le32_to_cpu(*azx_dev->posbuf);
2132 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2133 if (!pos || pos == (u32)-1) {
2134 printk(KERN_WARNING
2135 "hda-intel: Invalid position buffer, "
2136 "using LPIB read method instead.\n");
2137 chip->position_fix[stream] = POS_FIX_LPIB;
2138 pos = azx_sd_readl(azx_dev, SD_LPIB);
2139 } else
2140 chip->position_fix[stream] = POS_FIX_POSBUF;
2141 }
2142 break;
2143 }
2144
2145 if (pos >= azx_dev->bufsize)
2146 pos = 0;
2147
2148 /* calculate runtime delay from LPIB */
2149 if (azx_dev->substream->runtime &&
2150 chip->position_fix[stream] == POS_FIX_POSBUF &&
2151 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2152 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2153 int delay;
2154 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2155 delay = pos - lpib_pos;
2156 else
2157 delay = lpib_pos - pos;
2158 if (delay < 0)
2159 delay += azx_dev->bufsize;
2160 if (delay >= azx_dev->period_bytes) {
2161 snd_printk(KERN_WARNING SFX
2162 "Unstable LPIB (%d >= %d); "
2163 "disabling LPIB delay counting\n",
2164 delay, azx_dev->period_bytes);
2165 delay = 0;
2166 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2167 }
2168 azx_dev->substream->runtime->delay =
2169 bytes_to_frames(azx_dev->substream->runtime, delay);
2170 }
2171 return pos;
2172 }
2173
2174 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2175 {
2176 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2177 struct azx *chip = apcm->chip;
2178 struct azx_dev *azx_dev = get_azx_dev(substream);
2179 return bytes_to_frames(substream->runtime,
2180 azx_get_position(chip, azx_dev, false));
2181 }
2182
2183 /*
2184 * Check whether the current DMA position is acceptable for updating
2185 * periods. Returns non-zero if it's OK.
2186 *
2187 * Many HD-audio controllers appear pretty inaccurate about
2188 * the update-IRQ timing. The IRQ is issued before actually the
2189 * data is processed. So, we need to process it afterwords in a
2190 * workqueue.
2191 */
2192 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2193 {
2194 u32 wallclk;
2195 unsigned int pos;
2196 int stream;
2197
2198 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2199 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2200 return -1; /* bogus (too early) interrupt */
2201
2202 stream = azx_dev->substream->stream;
2203 pos = azx_get_position(chip, azx_dev, true);
2204
2205 if (WARN_ONCE(!azx_dev->period_bytes,
2206 "hda-intel: zero azx_dev->period_bytes"))
2207 return -1; /* this shouldn't happen! */
2208 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2209 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2210 /* NG - it's below the first next period boundary */
2211 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2212 azx_dev->start_wallclk += wallclk;
2213 return 1; /* OK, it's fine */
2214 }
2215
2216 /*
2217 * The work for pending PCM period updates.
2218 */
2219 static void azx_irq_pending_work(struct work_struct *work)
2220 {
2221 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2222 int i, pending, ok;
2223
2224 if (!chip->irq_pending_warned) {
2225 printk(KERN_WARNING
2226 "hda-intel: IRQ timing workaround is activated "
2227 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2228 chip->card->number);
2229 chip->irq_pending_warned = 1;
2230 }
2231
2232 for (;;) {
2233 pending = 0;
2234 spin_lock_irq(&chip->reg_lock);
2235 for (i = 0; i < chip->num_streams; i++) {
2236 struct azx_dev *azx_dev = &chip->azx_dev[i];
2237 if (!azx_dev->irq_pending ||
2238 !azx_dev->substream ||
2239 !azx_dev->running)
2240 continue;
2241 ok = azx_position_ok(chip, azx_dev);
2242 if (ok > 0) {
2243 azx_dev->irq_pending = 0;
2244 spin_unlock(&chip->reg_lock);
2245 snd_pcm_period_elapsed(azx_dev->substream);
2246 spin_lock(&chip->reg_lock);
2247 } else if (ok < 0) {
2248 pending = 0; /* too early */
2249 } else
2250 pending++;
2251 }
2252 spin_unlock_irq(&chip->reg_lock);
2253 if (!pending)
2254 return;
2255 msleep(1);
2256 }
2257 }
2258
2259 /* clear irq_pending flags and assure no on-going workq */
2260 static void azx_clear_irq_pending(struct azx *chip)
2261 {
2262 int i;
2263
2264 spin_lock_irq(&chip->reg_lock);
2265 for (i = 0; i < chip->num_streams; i++)
2266 chip->azx_dev[i].irq_pending = 0;
2267 spin_unlock_irq(&chip->reg_lock);
2268 }
2269
2270 #ifdef CONFIG_X86
2271 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2272 struct vm_area_struct *area)
2273 {
2274 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2275 struct azx *chip = apcm->chip;
2276 if (!azx_snoop(chip))
2277 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2278 return snd_pcm_lib_default_mmap(substream, area);
2279 }
2280 #else
2281 #define azx_pcm_mmap NULL
2282 #endif
2283
2284 static struct snd_pcm_ops azx_pcm_ops = {
2285 .open = azx_pcm_open,
2286 .close = azx_pcm_close,
2287 .ioctl = snd_pcm_lib_ioctl,
2288 .hw_params = azx_pcm_hw_params,
2289 .hw_free = azx_pcm_hw_free,
2290 .prepare = azx_pcm_prepare,
2291 .trigger = azx_pcm_trigger,
2292 .pointer = azx_pcm_pointer,
2293 .mmap = azx_pcm_mmap,
2294 .page = snd_pcm_sgbuf_ops_page,
2295 };
2296
2297 static void azx_pcm_free(struct snd_pcm *pcm)
2298 {
2299 struct azx_pcm *apcm = pcm->private_data;
2300 if (apcm) {
2301 list_del(&apcm->list);
2302 kfree(apcm);
2303 }
2304 }
2305
2306 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2307
2308 static int
2309 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2310 struct hda_pcm *cpcm)
2311 {
2312 struct azx *chip = bus->private_data;
2313 struct snd_pcm *pcm;
2314 struct azx_pcm *apcm;
2315 int pcm_dev = cpcm->device;
2316 unsigned int size;
2317 int s, err;
2318
2319 list_for_each_entry(apcm, &chip->pcm_list, list) {
2320 if (apcm->pcm->device == pcm_dev) {
2321 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2322 return -EBUSY;
2323 }
2324 }
2325 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2326 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2327 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2328 &pcm);
2329 if (err < 0)
2330 return err;
2331 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2332 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2333 if (apcm == NULL)
2334 return -ENOMEM;
2335 apcm->chip = chip;
2336 apcm->pcm = pcm;
2337 apcm->codec = codec;
2338 pcm->private_data = apcm;
2339 pcm->private_free = azx_pcm_free;
2340 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2341 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2342 list_add_tail(&apcm->list, &chip->pcm_list);
2343 cpcm->pcm = pcm;
2344 for (s = 0; s < 2; s++) {
2345 apcm->hinfo[s] = &cpcm->stream[s];
2346 if (cpcm->stream[s].substreams)
2347 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2348 }
2349 /* buffer pre-allocation */
2350 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2351 if (size > MAX_PREALLOC_SIZE)
2352 size = MAX_PREALLOC_SIZE;
2353 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2354 snd_dma_pci_data(chip->pci),
2355 size, MAX_PREALLOC_SIZE);
2356 return 0;
2357 }
2358
2359 /*
2360 * mixer creation - all stuff is implemented in hda module
2361 */
2362 static int __devinit azx_mixer_create(struct azx *chip)
2363 {
2364 return snd_hda_build_controls(chip->bus);
2365 }
2366
2367
2368 /*
2369 * initialize SD streams
2370 */
2371 static int __devinit azx_init_stream(struct azx *chip)
2372 {
2373 int i;
2374
2375 /* initialize each stream (aka device)
2376 * assign the starting bdl address to each stream (device)
2377 * and initialize
2378 */
2379 for (i = 0; i < chip->num_streams; i++) {
2380 struct azx_dev *azx_dev = &chip->azx_dev[i];
2381 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2382 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2383 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2384 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2385 azx_dev->sd_int_sta_mask = 1 << i;
2386 /* stream tag: must be non-zero and unique */
2387 azx_dev->index = i;
2388 azx_dev->stream_tag = i + 1;
2389 }
2390
2391 return 0;
2392 }
2393
2394 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2395 {
2396 if (request_irq(chip->pci->irq, azx_interrupt,
2397 chip->msi ? 0 : IRQF_SHARED,
2398 KBUILD_MODNAME, chip)) {
2399 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2400 "disabling device\n", chip->pci->irq);
2401 if (do_disconnect)
2402 snd_card_disconnect(chip->card);
2403 return -1;
2404 }
2405 chip->irq = chip->pci->irq;
2406 pci_intx(chip->pci, !chip->msi);
2407 return 0;
2408 }
2409
2410
2411 static void azx_stop_chip(struct azx *chip)
2412 {
2413 if (!chip->initialized)
2414 return;
2415
2416 /* disable interrupts */
2417 azx_int_disable(chip);
2418 azx_int_clear(chip);
2419
2420 /* disable CORB/RIRB */
2421 azx_free_cmd_io(chip);
2422
2423 /* disable position buffer */
2424 azx_writel(chip, DPLBASE, 0);
2425 azx_writel(chip, DPUBASE, 0);
2426
2427 chip->initialized = 0;
2428 }
2429
2430 #ifdef CONFIG_PM
2431 /* power-up/down the controller */
2432 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2433 {
2434 struct azx *chip = bus->private_data;
2435
2436 if (power_up)
2437 pm_runtime_get_sync(&chip->pci->dev);
2438 else
2439 pm_runtime_put_sync(&chip->pci->dev);
2440 }
2441
2442 static DEFINE_MUTEX(card_list_lock);
2443 static LIST_HEAD(card_list);
2444
2445 static void azx_add_card_list(struct azx *chip)
2446 {
2447 mutex_lock(&card_list_lock);
2448 list_add(&chip->list, &card_list);
2449 mutex_unlock(&card_list_lock);
2450 }
2451
2452 static void azx_del_card_list(struct azx *chip)
2453 {
2454 mutex_lock(&card_list_lock);
2455 list_del_init(&chip->list);
2456 mutex_unlock(&card_list_lock);
2457 }
2458
2459 /* trigger power-save check at writing parameter */
2460 static int param_set_xint(const char *val, const struct kernel_param *kp)
2461 {
2462 struct azx *chip;
2463 struct hda_codec *c;
2464 int prev = power_save;
2465 int ret = param_set_int(val, kp);
2466
2467 if (ret || prev == power_save)
2468 return ret;
2469
2470 mutex_lock(&card_list_lock);
2471 list_for_each_entry(chip, &card_list, list) {
2472 if (!chip->bus || chip->disabled)
2473 continue;
2474 list_for_each_entry(c, &chip->bus->codec_list, list)
2475 snd_hda_power_sync(c);
2476 }
2477 mutex_unlock(&card_list_lock);
2478 return 0;
2479 }
2480 #else
2481 #define azx_add_card_list(chip) /* NOP */
2482 #define azx_del_card_list(chip) /* NOP */
2483 #endif /* CONFIG_PM */
2484
2485 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2486 /*
2487 * power management
2488 */
2489 static int azx_suspend(struct device *dev)
2490 {
2491 struct pci_dev *pci = to_pci_dev(dev);
2492 struct snd_card *card = dev_get_drvdata(dev);
2493 struct azx *chip = card->private_data;
2494 struct azx_pcm *p;
2495
2496 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2497 azx_clear_irq_pending(chip);
2498 list_for_each_entry(p, &chip->pcm_list, list)
2499 snd_pcm_suspend_all(p->pcm);
2500 if (chip->initialized)
2501 snd_hda_suspend(chip->bus);
2502 azx_stop_chip(chip);
2503 if (chip->irq >= 0) {
2504 free_irq(chip->irq, chip);
2505 chip->irq = -1;
2506 }
2507 if (chip->msi)
2508 pci_disable_msi(chip->pci);
2509 pci_disable_device(pci);
2510 pci_save_state(pci);
2511 pci_set_power_state(pci, PCI_D3hot);
2512 return 0;
2513 }
2514
2515 static int azx_resume(struct device *dev)
2516 {
2517 struct pci_dev *pci = to_pci_dev(dev);
2518 struct snd_card *card = dev_get_drvdata(dev);
2519 struct azx *chip = card->private_data;
2520
2521 pci_set_power_state(pci, PCI_D0);
2522 pci_restore_state(pci);
2523 if (pci_enable_device(pci) < 0) {
2524 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2525 "disabling device\n");
2526 snd_card_disconnect(card);
2527 return -EIO;
2528 }
2529 pci_set_master(pci);
2530 if (chip->msi)
2531 if (pci_enable_msi(pci) < 0)
2532 chip->msi = 0;
2533 if (azx_acquire_irq(chip, 1) < 0)
2534 return -EIO;
2535 azx_init_pci(chip);
2536
2537 azx_init_chip(chip, 1);
2538
2539 snd_hda_resume(chip->bus);
2540 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2541 return 0;
2542 }
2543 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2544
2545 #ifdef CONFIG_PM_RUNTIME
2546 static int azx_runtime_suspend(struct device *dev)
2547 {
2548 struct snd_card *card = dev_get_drvdata(dev);
2549 struct azx *chip = card->private_data;
2550
2551 if (!power_save_controller)
2552 return -EAGAIN;
2553
2554 azx_stop_chip(chip);
2555 azx_clear_irq_pending(chip);
2556 return 0;
2557 }
2558
2559 static int azx_runtime_resume(struct device *dev)
2560 {
2561 struct snd_card *card = dev_get_drvdata(dev);
2562 struct azx *chip = card->private_data;
2563
2564 azx_init_pci(chip);
2565 azx_init_chip(chip, 1);
2566 return 0;
2567 }
2568 #endif /* CONFIG_PM_RUNTIME */
2569
2570 #ifdef CONFIG_PM
2571 static const struct dev_pm_ops azx_pm = {
2572 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2573 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, NULL)
2574 };
2575
2576 #define AZX_PM_OPS &azx_pm
2577 #else
2578 #define AZX_PM_OPS NULL
2579 #endif /* CONFIG_PM */
2580
2581
2582 /*
2583 * reboot notifier for hang-up problem at power-down
2584 */
2585 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2586 {
2587 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2588 snd_hda_bus_reboot_notify(chip->bus);
2589 azx_stop_chip(chip);
2590 return NOTIFY_OK;
2591 }
2592
2593 static void azx_notifier_register(struct azx *chip)
2594 {
2595 chip->reboot_notifier.notifier_call = azx_halt;
2596 register_reboot_notifier(&chip->reboot_notifier);
2597 }
2598
2599 static void azx_notifier_unregister(struct azx *chip)
2600 {
2601 if (chip->reboot_notifier.notifier_call)
2602 unregister_reboot_notifier(&chip->reboot_notifier);
2603 }
2604
2605 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2606 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2607
2608 #ifdef SUPPORT_VGA_SWITCHEROO
2609 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2610
2611 static void azx_vs_set_state(struct pci_dev *pci,
2612 enum vga_switcheroo_state state)
2613 {
2614 struct snd_card *card = pci_get_drvdata(pci);
2615 struct azx *chip = card->private_data;
2616 bool disabled;
2617
2618 if (chip->init_failed)
2619 return;
2620
2621 disabled = (state == VGA_SWITCHEROO_OFF);
2622 if (chip->disabled == disabled)
2623 return;
2624
2625 if (!chip->bus) {
2626 chip->disabled = disabled;
2627 if (!disabled) {
2628 snd_printk(KERN_INFO SFX
2629 "%s: Start delayed initialization\n",
2630 pci_name(chip->pci));
2631 if (azx_first_init(chip) < 0 ||
2632 azx_probe_continue(chip) < 0) {
2633 snd_printk(KERN_ERR SFX
2634 "%s: initialization error\n",
2635 pci_name(chip->pci));
2636 chip->init_failed = true;
2637 }
2638 }
2639 } else {
2640 snd_printk(KERN_INFO SFX
2641 "%s %s via VGA-switcheroo\n",
2642 disabled ? "Disabling" : "Enabling",
2643 pci_name(chip->pci));
2644 if (disabled) {
2645 azx_suspend(&pci->dev);
2646 chip->disabled = true;
2647 if (snd_hda_lock_devices(chip->bus))
2648 snd_printk(KERN_WARNING SFX
2649 "Cannot lock devices!\n");
2650 } else {
2651 snd_hda_unlock_devices(chip->bus);
2652 chip->disabled = false;
2653 azx_resume(&pci->dev);
2654 }
2655 }
2656 }
2657
2658 static bool azx_vs_can_switch(struct pci_dev *pci)
2659 {
2660 struct snd_card *card = pci_get_drvdata(pci);
2661 struct azx *chip = card->private_data;
2662
2663 if (chip->init_failed)
2664 return false;
2665 if (chip->disabled || !chip->bus)
2666 return true;
2667 if (snd_hda_lock_devices(chip->bus))
2668 return false;
2669 snd_hda_unlock_devices(chip->bus);
2670 return true;
2671 }
2672
2673 static void __devinit init_vga_switcheroo(struct azx *chip)
2674 {
2675 struct pci_dev *p = get_bound_vga(chip->pci);
2676 if (p) {
2677 snd_printk(KERN_INFO SFX
2678 "%s: Handle VGA-switcheroo audio client\n",
2679 pci_name(chip->pci));
2680 chip->use_vga_switcheroo = 1;
2681 pci_dev_put(p);
2682 }
2683 }
2684
2685 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2686 .set_gpu_state = azx_vs_set_state,
2687 .can_switch = azx_vs_can_switch,
2688 };
2689
2690 static int __devinit register_vga_switcheroo(struct azx *chip)
2691 {
2692 int err;
2693
2694 if (!chip->use_vga_switcheroo)
2695 return 0;
2696 /* FIXME: currently only handling DIS controller
2697 * is there any machine with two switchable HDMI audio controllers?
2698 */
2699 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2700 VGA_SWITCHEROO_DIS,
2701 chip->bus != NULL);
2702 if (err < 0)
2703 return err;
2704 chip->vga_switcheroo_registered = 1;
2705 return 0;
2706 }
2707 #else
2708 #define init_vga_switcheroo(chip) /* NOP */
2709 #define register_vga_switcheroo(chip) 0
2710 #define check_hdmi_disabled(pci) false
2711 #endif /* SUPPORT_VGA_SWITCHER */
2712
2713 /*
2714 * destructor
2715 */
2716 static int azx_free(struct azx *chip)
2717 {
2718 int i;
2719
2720 azx_del_card_list(chip);
2721
2722 azx_notifier_unregister(chip);
2723
2724 if (use_vga_switcheroo(chip)) {
2725 if (chip->disabled && chip->bus)
2726 snd_hda_unlock_devices(chip->bus);
2727 if (chip->vga_switcheroo_registered)
2728 vga_switcheroo_unregister_client(chip->pci);
2729 }
2730
2731 if (chip->initialized) {
2732 azx_clear_irq_pending(chip);
2733 for (i = 0; i < chip->num_streams; i++)
2734 azx_stream_stop(chip, &chip->azx_dev[i]);
2735 azx_stop_chip(chip);
2736 }
2737
2738 if (chip->irq >= 0)
2739 free_irq(chip->irq, (void*)chip);
2740 if (chip->msi)
2741 pci_disable_msi(chip->pci);
2742 if (chip->remap_addr)
2743 iounmap(chip->remap_addr);
2744
2745 if (chip->azx_dev) {
2746 for (i = 0; i < chip->num_streams; i++)
2747 if (chip->azx_dev[i].bdl.area) {
2748 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2749 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2750 }
2751 }
2752 if (chip->rb.area) {
2753 mark_pages_wc(chip, &chip->rb, false);
2754 snd_dma_free_pages(&chip->rb);
2755 }
2756 if (chip->posbuf.area) {
2757 mark_pages_wc(chip, &chip->posbuf, false);
2758 snd_dma_free_pages(&chip->posbuf);
2759 }
2760 if (chip->region_requested)
2761 pci_release_regions(chip->pci);
2762 pci_disable_device(chip->pci);
2763 kfree(chip->azx_dev);
2764 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2765 if (chip->fw)
2766 release_firmware(chip->fw);
2767 #endif
2768 kfree(chip);
2769
2770 return 0;
2771 }
2772
2773 static int azx_dev_free(struct snd_device *device)
2774 {
2775 return azx_free(device->device_data);
2776 }
2777
2778 #ifdef SUPPORT_VGA_SWITCHEROO
2779 /*
2780 * Check of disabled HDMI controller by vga-switcheroo
2781 */
2782 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2783 {
2784 struct pci_dev *p;
2785
2786 /* check only discrete GPU */
2787 switch (pci->vendor) {
2788 case PCI_VENDOR_ID_ATI:
2789 case PCI_VENDOR_ID_AMD:
2790 case PCI_VENDOR_ID_NVIDIA:
2791 if (pci->devfn == 1) {
2792 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2793 pci->bus->number, 0);
2794 if (p) {
2795 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2796 return p;
2797 pci_dev_put(p);
2798 }
2799 }
2800 break;
2801 }
2802 return NULL;
2803 }
2804
2805 static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2806 {
2807 bool vga_inactive = false;
2808 struct pci_dev *p = get_bound_vga(pci);
2809
2810 if (p) {
2811 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2812 vga_inactive = true;
2813 pci_dev_put(p);
2814 }
2815 return vga_inactive;
2816 }
2817 #endif /* SUPPORT_VGA_SWITCHEROO */
2818
2819 /*
2820 * white/black-listing for position_fix
2821 */
2822 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2823 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2824 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2825 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2826 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2827 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2828 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2829 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2830 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2831 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2832 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2833 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2834 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2835 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2836 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2837 {}
2838 };
2839
2840 static int __devinit check_position_fix(struct azx *chip, int fix)
2841 {
2842 const struct snd_pci_quirk *q;
2843
2844 switch (fix) {
2845 case POS_FIX_AUTO:
2846 case POS_FIX_LPIB:
2847 case POS_FIX_POSBUF:
2848 case POS_FIX_VIACOMBO:
2849 case POS_FIX_COMBO:
2850 return fix;
2851 }
2852
2853 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2854 if (q) {
2855 printk(KERN_INFO
2856 "hda_intel: position_fix set to %d "
2857 "for device %04x:%04x\n",
2858 q->value, q->subvendor, q->subdevice);
2859 return q->value;
2860 }
2861
2862 /* Check VIA/ATI HD Audio Controller exist */
2863 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2864 snd_printd(SFX "Using VIACOMBO position fix\n");
2865 return POS_FIX_VIACOMBO;
2866 }
2867 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2868 snd_printd(SFX "Using LPIB position fix\n");
2869 return POS_FIX_LPIB;
2870 }
2871 return POS_FIX_AUTO;
2872 }
2873
2874 /*
2875 * black-lists for probe_mask
2876 */
2877 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2878 /* Thinkpad often breaks the controller communication when accessing
2879 * to the non-working (or non-existing) modem codec slot.
2880 */
2881 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2882 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2883 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2884 /* broken BIOS */
2885 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2886 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2887 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2888 /* forced codec slots */
2889 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2890 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2891 /* WinFast VP200 H (Teradici) user reported broken communication */
2892 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
2893 {}
2894 };
2895
2896 #define AZX_FORCE_CODEC_MASK 0x100
2897
2898 static void __devinit check_probe_mask(struct azx *chip, int dev)
2899 {
2900 const struct snd_pci_quirk *q;
2901
2902 chip->codec_probe_mask = probe_mask[dev];
2903 if (chip->codec_probe_mask == -1) {
2904 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2905 if (q) {
2906 printk(KERN_INFO
2907 "hda_intel: probe_mask set to 0x%x "
2908 "for device %04x:%04x\n",
2909 q->value, q->subvendor, q->subdevice);
2910 chip->codec_probe_mask = q->value;
2911 }
2912 }
2913
2914 /* check forced option */
2915 if (chip->codec_probe_mask != -1 &&
2916 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2917 chip->codec_mask = chip->codec_probe_mask & 0xff;
2918 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2919 chip->codec_mask);
2920 }
2921 }
2922
2923 /*
2924 * white/black-list for enable_msi
2925 */
2926 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2927 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2928 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2929 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2930 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2931 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2932 {}
2933 };
2934
2935 static void __devinit check_msi(struct azx *chip)
2936 {
2937 const struct snd_pci_quirk *q;
2938
2939 if (enable_msi >= 0) {
2940 chip->msi = !!enable_msi;
2941 return;
2942 }
2943 chip->msi = 1; /* enable MSI as default */
2944 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2945 if (q) {
2946 printk(KERN_INFO
2947 "hda_intel: msi for device %04x:%04x set to %d\n",
2948 q->subvendor, q->subdevice, q->value);
2949 chip->msi = q->value;
2950 return;
2951 }
2952
2953 /* NVidia chipsets seem to cause troubles with MSI */
2954 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2955 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2956 chip->msi = 0;
2957 }
2958 }
2959
2960 /* check the snoop mode availability */
2961 static void __devinit azx_check_snoop_available(struct azx *chip)
2962 {
2963 bool snoop = chip->snoop;
2964
2965 switch (chip->driver_type) {
2966 case AZX_DRIVER_VIA:
2967 /* force to non-snoop mode for a new VIA controller
2968 * when BIOS is set
2969 */
2970 if (snoop) {
2971 u8 val;
2972 pci_read_config_byte(chip->pci, 0x42, &val);
2973 if (!(val & 0x80) && chip->pci->revision == 0x30)
2974 snoop = false;
2975 }
2976 break;
2977 case AZX_DRIVER_ATIHDMI_NS:
2978 /* new ATI HDMI requires non-snoop */
2979 snoop = false;
2980 break;
2981 }
2982
2983 if (snoop != chip->snoop) {
2984 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2985 snoop ? "snoop" : "non-snoop");
2986 chip->snoop = snoop;
2987 }
2988 }
2989
2990 /*
2991 * constructor
2992 */
2993 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2994 int dev, unsigned int driver_caps,
2995 struct azx **rchip)
2996 {
2997 static struct snd_device_ops ops = {
2998 .dev_free = azx_dev_free,
2999 };
3000 struct azx *chip;
3001 int err;
3002
3003 *rchip = NULL;
3004
3005 err = pci_enable_device(pci);
3006 if (err < 0)
3007 return err;
3008
3009 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3010 if (!chip) {
3011 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
3012 pci_disable_device(pci);
3013 return -ENOMEM;
3014 }
3015
3016 spin_lock_init(&chip->reg_lock);
3017 mutex_init(&chip->open_mutex);
3018 chip->card = card;
3019 chip->pci = pci;
3020 chip->irq = -1;
3021 chip->driver_caps = driver_caps;
3022 chip->driver_type = driver_caps & 0xff;
3023 check_msi(chip);
3024 chip->dev_index = dev;
3025 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3026 INIT_LIST_HEAD(&chip->pcm_list);
3027 INIT_LIST_HEAD(&chip->list);
3028 init_vga_switcheroo(chip);
3029
3030 chip->position_fix[0] = chip->position_fix[1] =
3031 check_position_fix(chip, position_fix[dev]);
3032 /* combo mode uses LPIB for playback */
3033 if (chip->position_fix[0] == POS_FIX_COMBO) {
3034 chip->position_fix[0] = POS_FIX_LPIB;
3035 chip->position_fix[1] = POS_FIX_AUTO;
3036 }
3037
3038 check_probe_mask(chip, dev);
3039
3040 chip->single_cmd = single_cmd;
3041 chip->snoop = hda_snoop;
3042 azx_check_snoop_available(chip);
3043
3044 if (bdl_pos_adj[dev] < 0) {
3045 switch (chip->driver_type) {
3046 case AZX_DRIVER_ICH:
3047 case AZX_DRIVER_PCH:
3048 bdl_pos_adj[dev] = 1;
3049 break;
3050 default:
3051 bdl_pos_adj[dev] = 32;
3052 break;
3053 }
3054 }
3055
3056 if (check_hdmi_disabled(pci)) {
3057 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
3058 pci_name(pci));
3059 if (use_vga_switcheroo(chip)) {
3060 snd_printk(KERN_INFO SFX "Delaying initialization\n");
3061 chip->disabled = true;
3062 goto ok;
3063 }
3064 kfree(chip);
3065 pci_disable_device(pci);
3066 return -ENXIO;
3067 }
3068
3069 err = azx_first_init(chip);
3070 if (err < 0) {
3071 azx_free(chip);
3072 return err;
3073 }
3074
3075 ok:
3076 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3077 if (err < 0) {
3078 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3079 azx_free(chip);
3080 return err;
3081 }
3082
3083 *rchip = chip;
3084 return 0;
3085 }
3086
3087 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3088 {
3089 int dev = chip->dev_index;
3090 struct pci_dev *pci = chip->pci;
3091 struct snd_card *card = chip->card;
3092 int i, err;
3093 unsigned short gcap;
3094
3095 #if BITS_PER_LONG != 64
3096 /* Fix up base address on ULI M5461 */
3097 if (chip->driver_type == AZX_DRIVER_ULI) {
3098 u16 tmp3;
3099 pci_read_config_word(pci, 0x40, &tmp3);
3100 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3101 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3102 }
3103 #endif
3104
3105 err = pci_request_regions(pci, "ICH HD audio");
3106 if (err < 0)
3107 return err;
3108 chip->region_requested = 1;
3109
3110 chip->addr = pci_resource_start(pci, 0);
3111 chip->remap_addr = pci_ioremap_bar(pci, 0);
3112 if (chip->remap_addr == NULL) {
3113 snd_printk(KERN_ERR SFX "ioremap error\n");
3114 return -ENXIO;
3115 }
3116
3117 if (chip->msi)
3118 if (pci_enable_msi(pci) < 0)
3119 chip->msi = 0;
3120
3121 if (azx_acquire_irq(chip, 0) < 0)
3122 return -EBUSY;
3123
3124 pci_set_master(pci);
3125 synchronize_irq(chip->irq);
3126
3127 gcap = azx_readw(chip, GCAP);
3128 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
3129
3130 /* disable SB600 64bit support for safety */
3131 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3132 struct pci_dev *p_smbus;
3133 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3134 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3135 NULL);
3136 if (p_smbus) {
3137 if (p_smbus->revision < 0x30)
3138 gcap &= ~ICH6_GCAP_64OK;
3139 pci_dev_put(p_smbus);
3140 }
3141 }
3142
3143 /* disable 64bit DMA address on some devices */
3144 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3145 snd_printd(SFX "Disabling 64bit DMA\n");
3146 gcap &= ~ICH6_GCAP_64OK;
3147 }
3148
3149 /* disable buffer size rounding to 128-byte multiples if supported */
3150 if (align_buffer_size >= 0)
3151 chip->align_buffer_size = !!align_buffer_size;
3152 else {
3153 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3154 chip->align_buffer_size = 0;
3155 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3156 chip->align_buffer_size = 1;
3157 else
3158 chip->align_buffer_size = 1;
3159 }
3160
3161 /* allow 64bit DMA address if supported by H/W */
3162 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3163 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3164 else {
3165 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3166 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3167 }
3168
3169 /* read number of streams from GCAP register instead of using
3170 * hardcoded value
3171 */
3172 chip->capture_streams = (gcap >> 8) & 0x0f;
3173 chip->playback_streams = (gcap >> 12) & 0x0f;
3174 if (!chip->playback_streams && !chip->capture_streams) {
3175 /* gcap didn't give any info, switching to old method */
3176
3177 switch (chip->driver_type) {
3178 case AZX_DRIVER_ULI:
3179 chip->playback_streams = ULI_NUM_PLAYBACK;
3180 chip->capture_streams = ULI_NUM_CAPTURE;
3181 break;
3182 case AZX_DRIVER_ATIHDMI:
3183 case AZX_DRIVER_ATIHDMI_NS:
3184 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3185 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3186 break;
3187 case AZX_DRIVER_GENERIC:
3188 default:
3189 chip->playback_streams = ICH6_NUM_PLAYBACK;
3190 chip->capture_streams = ICH6_NUM_CAPTURE;
3191 break;
3192 }
3193 }
3194 chip->capture_index_offset = 0;
3195 chip->playback_index_offset = chip->capture_streams;
3196 chip->num_streams = chip->playback_streams + chip->capture_streams;
3197 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3198 GFP_KERNEL);
3199 if (!chip->azx_dev) {
3200 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3201 return -ENOMEM;
3202 }
3203
3204 for (i = 0; i < chip->num_streams; i++) {
3205 /* allocate memory for the BDL for each stream */
3206 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3207 snd_dma_pci_data(chip->pci),
3208 BDL_SIZE, &chip->azx_dev[i].bdl);
3209 if (err < 0) {
3210 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3211 return -ENOMEM;
3212 }
3213 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3214 }
3215 /* allocate memory for the position buffer */
3216 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3217 snd_dma_pci_data(chip->pci),
3218 chip->num_streams * 8, &chip->posbuf);
3219 if (err < 0) {
3220 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3221 return -ENOMEM;
3222 }
3223 mark_pages_wc(chip, &chip->posbuf, true);
3224 /* allocate CORB/RIRB */
3225 err = azx_alloc_cmd_io(chip);
3226 if (err < 0)
3227 return err;
3228
3229 /* initialize streams */
3230 azx_init_stream(chip);
3231
3232 /* initialize chip */
3233 azx_init_pci(chip);
3234 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3235
3236 /* codec detection */
3237 if (!chip->codec_mask) {
3238 snd_printk(KERN_ERR SFX "no codecs found!\n");
3239 return -ENODEV;
3240 }
3241
3242 strcpy(card->driver, "HDA-Intel");
3243 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3244 sizeof(card->shortname));
3245 snprintf(card->longname, sizeof(card->longname),
3246 "%s at 0x%lx irq %i",
3247 card->shortname, chip->addr, chip->irq);
3248
3249 return 0;
3250 }
3251
3252 static void power_down_all_codecs(struct azx *chip)
3253 {
3254 #ifdef CONFIG_PM
3255 /* The codecs were powered up in snd_hda_codec_new().
3256 * Now all initialization done, so turn them down if possible
3257 */
3258 struct hda_codec *codec;
3259 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3260 snd_hda_power_down(codec);
3261 }
3262 #endif
3263 }
3264
3265 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3266 /* callback from request_firmware_nowait() */
3267 static void azx_firmware_cb(const struct firmware *fw, void *context)
3268 {
3269 struct snd_card *card = context;
3270 struct azx *chip = card->private_data;
3271 struct pci_dev *pci = chip->pci;
3272
3273 if (!fw) {
3274 snd_printk(KERN_ERR SFX "Cannot load firmware, aborting\n");
3275 goto error;
3276 }
3277
3278 chip->fw = fw;
3279 if (!chip->disabled) {
3280 /* continue probing */
3281 if (azx_probe_continue(chip))
3282 goto error;
3283 }
3284 return; /* OK */
3285
3286 error:
3287 snd_card_free(card);
3288 pci_set_drvdata(pci, NULL);
3289 }
3290 #endif
3291
3292 static int __devinit azx_probe(struct pci_dev *pci,
3293 const struct pci_device_id *pci_id)
3294 {
3295 static int dev;
3296 struct snd_card *card;
3297 struct azx *chip;
3298 bool probe_now;
3299 int err;
3300
3301 if (dev >= SNDRV_CARDS)
3302 return -ENODEV;
3303 if (!enable[dev]) {
3304 dev++;
3305 return -ENOENT;
3306 }
3307
3308 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3309 if (err < 0) {
3310 snd_printk(KERN_ERR SFX "Error creating card!\n");
3311 return err;
3312 }
3313
3314 snd_card_set_dev(card, &pci->dev);
3315
3316 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3317 if (err < 0)
3318 goto out_free;
3319 card->private_data = chip;
3320 probe_now = !chip->disabled;
3321
3322 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3323 if (patch[dev] && *patch[dev]) {
3324 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3325 patch[dev]);
3326 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3327 &pci->dev, GFP_KERNEL, card,
3328 azx_firmware_cb);
3329 if (err < 0)
3330 goto out_free;
3331 probe_now = false; /* continued in azx_firmware_cb() */
3332 }
3333 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3334
3335 if (probe_now) {
3336 err = azx_probe_continue(chip);
3337 if (err < 0)
3338 goto out_free;
3339 }
3340
3341 pci_set_drvdata(pci, card);
3342
3343 if (pci_dev_run_wake(pci))
3344 pm_runtime_put_noidle(&pci->dev);
3345
3346 err = register_vga_switcheroo(chip);
3347 if (err < 0) {
3348 snd_printk(KERN_ERR SFX
3349 "Error registering VGA-switcheroo client\n");
3350 goto out_free;
3351 }
3352
3353 dev++;
3354 return 0;
3355
3356 out_free:
3357 snd_card_free(card);
3358 return err;
3359 }
3360
3361 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3362 {
3363 int dev = chip->dev_index;
3364 int err;
3365
3366 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3367 chip->beep_mode = beep_mode[dev];
3368 #endif
3369
3370 /* create codec instances */
3371 err = azx_codec_create(chip, model[dev]);
3372 if (err < 0)
3373 goto out_free;
3374 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3375 if (chip->fw) {
3376 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3377 chip->fw->data);
3378 if (err < 0)
3379 goto out_free;
3380 release_firmware(chip->fw); /* no longer needed */
3381 chip->fw = NULL;
3382 }
3383 #endif
3384 if ((probe_only[dev] & 1) == 0) {
3385 err = azx_codec_configure(chip);
3386 if (err < 0)
3387 goto out_free;
3388 }
3389
3390 /* create PCM streams */
3391 err = snd_hda_build_pcms(chip->bus);
3392 if (err < 0)
3393 goto out_free;
3394
3395 /* create mixer controls */
3396 err = azx_mixer_create(chip);
3397 if (err < 0)
3398 goto out_free;
3399
3400 err = snd_card_register(chip->card);
3401 if (err < 0)
3402 goto out_free;
3403
3404 chip->running = 1;
3405 power_down_all_codecs(chip);
3406 azx_notifier_register(chip);
3407 azx_add_card_list(chip);
3408
3409 return 0;
3410
3411 out_free:
3412 chip->init_failed = 1;
3413 return err;
3414 }
3415
3416 static void __devexit azx_remove(struct pci_dev *pci)
3417 {
3418 struct snd_card *card = pci_get_drvdata(pci);
3419
3420 if (pci_dev_run_wake(pci))
3421 pm_runtime_get_noresume(&pci->dev);
3422
3423 if (card)
3424 snd_card_free(card);
3425 pci_set_drvdata(pci, NULL);
3426 }
3427
3428 /* PCI IDs */
3429 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3430 /* CPT */
3431 { PCI_DEVICE(0x8086, 0x1c20),
3432 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3433 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3434 /* PBG */
3435 { PCI_DEVICE(0x8086, 0x1d20),
3436 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3437 AZX_DCAPS_BUFSIZE},
3438 /* Panther Point */
3439 { PCI_DEVICE(0x8086, 0x1e20),
3440 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3441 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3442 /* Lynx Point */
3443 { PCI_DEVICE(0x8086, 0x8c20),
3444 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3445 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3446 /* Lynx Point-LP */
3447 { PCI_DEVICE(0x8086, 0x9c20),
3448 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3449 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3450 /* Lynx Point-LP */
3451 { PCI_DEVICE(0x8086, 0x9c21),
3452 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3453 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3454 /* Haswell */
3455 { PCI_DEVICE(0x8086, 0x0c0c),
3456 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3457 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3458 { PCI_DEVICE(0x8086, 0x0d0c),
3459 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3460 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3461 /* 5 Series/3400 */
3462 { PCI_DEVICE(0x8086, 0x3b56),
3463 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3464 AZX_DCAPS_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY },
3465 /* SCH */
3466 { PCI_DEVICE(0x8086, 0x811b),
3467 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3468 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3469 { PCI_DEVICE(0x8086, 0x080a),
3470 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3471 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3472 /* ICH */
3473 { PCI_DEVICE(0x8086, 0x2668),
3474 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3475 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3476 { PCI_DEVICE(0x8086, 0x27d8),
3477 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3478 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3479 { PCI_DEVICE(0x8086, 0x269a),
3480 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3481 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3482 { PCI_DEVICE(0x8086, 0x284b),
3483 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3484 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3485 { PCI_DEVICE(0x8086, 0x293e),
3486 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3487 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3488 { PCI_DEVICE(0x8086, 0x293f),
3489 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3490 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3491 { PCI_DEVICE(0x8086, 0x3a3e),
3492 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3493 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3494 { PCI_DEVICE(0x8086, 0x3a6e),
3495 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3496 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3497 /* Generic Intel */
3498 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3499 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3500 .class_mask = 0xffffff,
3501 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3502 /* ATI SB 450/600/700/800/900 */
3503 { PCI_DEVICE(0x1002, 0x437b),
3504 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3505 { PCI_DEVICE(0x1002, 0x4383),
3506 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3507 /* AMD Hudson */
3508 { PCI_DEVICE(0x1022, 0x780d),
3509 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3510 /* ATI HDMI */
3511 { PCI_DEVICE(0x1002, 0x793b),
3512 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3513 { PCI_DEVICE(0x1002, 0x7919),
3514 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3515 { PCI_DEVICE(0x1002, 0x960f),
3516 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3517 { PCI_DEVICE(0x1002, 0x970f),
3518 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3519 { PCI_DEVICE(0x1002, 0xaa00),
3520 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3521 { PCI_DEVICE(0x1002, 0xaa08),
3522 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3523 { PCI_DEVICE(0x1002, 0xaa10),
3524 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3525 { PCI_DEVICE(0x1002, 0xaa18),
3526 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3527 { PCI_DEVICE(0x1002, 0xaa20),
3528 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3529 { PCI_DEVICE(0x1002, 0xaa28),
3530 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3531 { PCI_DEVICE(0x1002, 0xaa30),
3532 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3533 { PCI_DEVICE(0x1002, 0xaa38),
3534 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3535 { PCI_DEVICE(0x1002, 0xaa40),
3536 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3537 { PCI_DEVICE(0x1002, 0xaa48),
3538 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3539 { PCI_DEVICE(0x1002, 0x9902),
3540 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3541 { PCI_DEVICE(0x1002, 0xaaa0),
3542 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3543 { PCI_DEVICE(0x1002, 0xaaa8),
3544 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3545 { PCI_DEVICE(0x1002, 0xaab0),
3546 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3547 /* VIA VT8251/VT8237A */
3548 { PCI_DEVICE(0x1106, 0x3288),
3549 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3550 /* VIA GFX VT7122/VX900 */
3551 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3552 /* VIA GFX VT6122/VX11 */
3553 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3554 /* SIS966 */
3555 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3556 /* ULI M5461 */
3557 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3558 /* NVIDIA MCP */
3559 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3560 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3561 .class_mask = 0xffffff,
3562 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3563 /* Teradici */
3564 { PCI_DEVICE(0x6549, 0x1200),
3565 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3566 { PCI_DEVICE(0x6549, 0x2200),
3567 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3568 /* Creative X-Fi (CA0110-IBG) */
3569 /* CTHDA chips */
3570 { PCI_DEVICE(0x1102, 0x0010),
3571 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3572 { PCI_DEVICE(0x1102, 0x0012),
3573 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3574 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3575 /* the following entry conflicts with snd-ctxfi driver,
3576 * as ctxfi driver mutates from HD-audio to native mode with
3577 * a special command sequence.
3578 */
3579 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3580 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3581 .class_mask = 0xffffff,
3582 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3583 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3584 #else
3585 /* this entry seems still valid -- i.e. without emu20kx chip */
3586 { PCI_DEVICE(0x1102, 0x0009),
3587 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3588 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3589 #endif
3590 /* Vortex86MX */
3591 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3592 /* VMware HDAudio */
3593 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3594 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3595 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3596 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3597 .class_mask = 0xffffff,
3598 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3599 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3600 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3601 .class_mask = 0xffffff,
3602 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3603 { 0, }
3604 };
3605 MODULE_DEVICE_TABLE(pci, azx_ids);
3606
3607 /* pci_driver definition */
3608 static struct pci_driver azx_driver = {
3609 .name = KBUILD_MODNAME,
3610 .id_table = azx_ids,
3611 .probe = azx_probe,
3612 .remove = __devexit_p(azx_remove),
3613 .driver = {
3614 .pm = AZX_PM_OPS,
3615 },
3616 };
3617
3618 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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