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Merge branch 'for-linus' into for-next
[deliverable/linux.git] / sound / pci / hda / hda_intel.c
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #ifdef CONFIG_X86
50 /* for snoop control */
51 #include <asm/pgtable.h>
52 #include <asm/cacheflush.h>
53 #endif
54 #include <sound/core.h>
55 #include <sound/initval.h>
56 #include <linux/vgaarb.h>
57 #include <linux/vga_switcheroo.h>
58 #include <linux/firmware.h>
59 #include "hda_codec.h"
60
61
62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
65 static char *model[SNDRV_CARDS];
66 static int position_fix[SNDRV_CARDS];
67 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
68 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
69 static int probe_only[SNDRV_CARDS];
70 static bool single_cmd;
71 static int enable_msi = -1;
72 #ifdef CONFIG_SND_HDA_PATCH_LOADER
73 static char *patch[SNDRV_CARDS];
74 #endif
75 #ifdef CONFIG_SND_HDA_INPUT_BEEP
76 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
77 CONFIG_SND_HDA_INPUT_BEEP_MODE};
78 #endif
79
80 module_param_array(index, int, NULL, 0444);
81 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
82 module_param_array(id, charp, NULL, 0444);
83 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
84 module_param_array(enable, bool, NULL, 0444);
85 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
86 module_param_array(model, charp, NULL, 0444);
87 MODULE_PARM_DESC(model, "Use the given board model.");
88 module_param_array(position_fix, int, NULL, 0444);
89 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
90 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
91 module_param_array(bdl_pos_adj, int, NULL, 0644);
92 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
93 module_param_array(probe_mask, int, NULL, 0444);
94 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
95 module_param_array(probe_only, int, NULL, 0444);
96 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
97 module_param(single_cmd, bool, 0444);
98 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
99 "(for debugging only).");
100 module_param(enable_msi, bint, 0444);
101 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
102 #ifdef CONFIG_SND_HDA_PATCH_LOADER
103 module_param_array(patch, charp, NULL, 0444);
104 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
105 #endif
106 #ifdef CONFIG_SND_HDA_INPUT_BEEP
107 module_param_array(beep_mode, bool, NULL, 0444);
108 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
109 "(0=off, 1=on) (default=1).");
110 #endif
111
112 #ifdef CONFIG_SND_HDA_POWER_SAVE
113 static int param_set_xint(const char *val, const struct kernel_param *kp);
114 static struct kernel_param_ops param_ops_xint = {
115 .set = param_set_xint,
116 .get = param_get_int,
117 };
118 #define param_check_xint param_check_int
119
120 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
121 module_param(power_save, xint, 0644);
122 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
123 "(in second, 0 = disable).");
124
125 /* reset the HD-audio controller in power save mode.
126 * this may give more power-saving, but will take longer time to
127 * wake up.
128 */
129 static bool power_save_controller = 1;
130 module_param(power_save_controller, bool, 0644);
131 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
132 #endif
133
134 static int align_buffer_size = -1;
135 module_param(align_buffer_size, bint, 0644);
136 MODULE_PARM_DESC(align_buffer_size,
137 "Force buffer and period sizes to be multiple of 128 bytes.");
138
139 #ifdef CONFIG_X86
140 static bool hda_snoop = true;
141 module_param_named(snoop, hda_snoop, bool, 0444);
142 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
143 #define azx_snoop(chip) (chip)->snoop
144 #else
145 #define hda_snoop true
146 #define azx_snoop(chip) true
147 #endif
148
149
150 MODULE_LICENSE("GPL");
151 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
152 "{Intel, ICH6M},"
153 "{Intel, ICH7},"
154 "{Intel, ESB2},"
155 "{Intel, ICH8},"
156 "{Intel, ICH9},"
157 "{Intel, ICH10},"
158 "{Intel, PCH},"
159 "{Intel, CPT},"
160 "{Intel, PPT},"
161 "{Intel, LPT},"
162 "{Intel, LPT_LP},"
163 "{Intel, HPT},"
164 "{Intel, PBG},"
165 "{Intel, SCH},"
166 "{ATI, SB450},"
167 "{ATI, SB600},"
168 "{ATI, RS600},"
169 "{ATI, RS690},"
170 "{ATI, RS780},"
171 "{ATI, R600},"
172 "{ATI, RV630},"
173 "{ATI, RV610},"
174 "{ATI, RV670},"
175 "{ATI, RV635},"
176 "{ATI, RV620},"
177 "{ATI, RV770},"
178 "{VIA, VT8251},"
179 "{VIA, VT8237A},"
180 "{SiS, SIS966},"
181 "{ULI, M5461}}");
182 MODULE_DESCRIPTION("Intel HDA driver");
183
184 #ifdef CONFIG_SND_VERBOSE_PRINTK
185 #define SFX /* nop */
186 #else
187 #define SFX "hda-intel: "
188 #endif
189
190 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
191 #ifdef CONFIG_SND_HDA_CODEC_HDMI
192 #define SUPPORT_VGA_SWITCHEROO
193 #endif
194 #endif
195
196
197 /*
198 * registers
199 */
200 #define ICH6_REG_GCAP 0x00
201 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
202 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
203 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
204 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
205 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
206 #define ICH6_REG_VMIN 0x02
207 #define ICH6_REG_VMAJ 0x03
208 #define ICH6_REG_OUTPAY 0x04
209 #define ICH6_REG_INPAY 0x06
210 #define ICH6_REG_GCTL 0x08
211 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
212 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
213 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
214 #define ICH6_REG_WAKEEN 0x0c
215 #define ICH6_REG_STATESTS 0x0e
216 #define ICH6_REG_GSTS 0x10
217 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
218 #define ICH6_REG_INTCTL 0x20
219 #define ICH6_REG_INTSTS 0x24
220 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
221 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
222 #define ICH6_REG_SSYNC 0x38
223 #define ICH6_REG_CORBLBASE 0x40
224 #define ICH6_REG_CORBUBASE 0x44
225 #define ICH6_REG_CORBWP 0x48
226 #define ICH6_REG_CORBRP 0x4a
227 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
228 #define ICH6_REG_CORBCTL 0x4c
229 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
230 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
231 #define ICH6_REG_CORBSTS 0x4d
232 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
233 #define ICH6_REG_CORBSIZE 0x4e
234
235 #define ICH6_REG_RIRBLBASE 0x50
236 #define ICH6_REG_RIRBUBASE 0x54
237 #define ICH6_REG_RIRBWP 0x58
238 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
239 #define ICH6_REG_RINTCNT 0x5a
240 #define ICH6_REG_RIRBCTL 0x5c
241 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
242 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
243 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
244 #define ICH6_REG_RIRBSTS 0x5d
245 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
246 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
247 #define ICH6_REG_RIRBSIZE 0x5e
248
249 #define ICH6_REG_IC 0x60
250 #define ICH6_REG_IR 0x64
251 #define ICH6_REG_IRS 0x68
252 #define ICH6_IRS_VALID (1<<1)
253 #define ICH6_IRS_BUSY (1<<0)
254
255 #define ICH6_REG_DPLBASE 0x70
256 #define ICH6_REG_DPUBASE 0x74
257 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
258
259 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
260 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
261
262 /* stream register offsets from stream base */
263 #define ICH6_REG_SD_CTL 0x00
264 #define ICH6_REG_SD_STS 0x03
265 #define ICH6_REG_SD_LPIB 0x04
266 #define ICH6_REG_SD_CBL 0x08
267 #define ICH6_REG_SD_LVI 0x0c
268 #define ICH6_REG_SD_FIFOW 0x0e
269 #define ICH6_REG_SD_FIFOSIZE 0x10
270 #define ICH6_REG_SD_FORMAT 0x12
271 #define ICH6_REG_SD_BDLPL 0x18
272 #define ICH6_REG_SD_BDLPU 0x1c
273
274 /* PCI space */
275 #define ICH6_PCIREG_TCSEL 0x44
276
277 /*
278 * other constants
279 */
280
281 /* max number of SDs */
282 /* ICH, ATI and VIA have 4 playback and 4 capture */
283 #define ICH6_NUM_CAPTURE 4
284 #define ICH6_NUM_PLAYBACK 4
285
286 /* ULI has 6 playback and 5 capture */
287 #define ULI_NUM_CAPTURE 5
288 #define ULI_NUM_PLAYBACK 6
289
290 /* ATI HDMI has 1 playback and 0 capture */
291 #define ATIHDMI_NUM_CAPTURE 0
292 #define ATIHDMI_NUM_PLAYBACK 1
293
294 /* TERA has 4 playback and 3 capture */
295 #define TERA_NUM_CAPTURE 3
296 #define TERA_NUM_PLAYBACK 4
297
298 /* this number is statically defined for simplicity */
299 #define MAX_AZX_DEV 16
300
301 /* max number of fragments - we may use more if allocating more pages for BDL */
302 #define BDL_SIZE 4096
303 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
304 #define AZX_MAX_FRAG 32
305 /* max buffer size - no h/w limit, you can increase as you like */
306 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
307
308 /* RIRB int mask: overrun[2], response[0] */
309 #define RIRB_INT_RESPONSE 0x01
310 #define RIRB_INT_OVERRUN 0x04
311 #define RIRB_INT_MASK 0x05
312
313 /* STATESTS int mask: S3,SD2,SD1,SD0 */
314 #define AZX_MAX_CODECS 8
315 #define AZX_DEFAULT_CODECS 4
316 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
317
318 /* SD_CTL bits */
319 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
320 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
321 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
322 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
323 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
324 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
325 #define SD_CTL_STREAM_TAG_SHIFT 20
326
327 /* SD_CTL and SD_STS */
328 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
329 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
330 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
331 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
332 SD_INT_COMPLETE)
333
334 /* SD_STS */
335 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
336
337 /* INTCTL and INTSTS */
338 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
339 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
340 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
341
342 /* below are so far hardcoded - should read registers in future */
343 #define ICH6_MAX_CORB_ENTRIES 256
344 #define ICH6_MAX_RIRB_ENTRIES 256
345
346 /* position fix mode */
347 enum {
348 POS_FIX_AUTO,
349 POS_FIX_LPIB,
350 POS_FIX_POSBUF,
351 POS_FIX_VIACOMBO,
352 POS_FIX_COMBO,
353 };
354
355 /* Defines for ATI HD Audio support in SB450 south bridge */
356 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
357 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
358
359 /* Defines for Nvidia HDA support */
360 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
361 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
362 #define NVIDIA_HDA_ISTRM_COH 0x4d
363 #define NVIDIA_HDA_OSTRM_COH 0x4c
364 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
365
366 /* Defines for Intel SCH HDA snoop control */
367 #define INTEL_SCH_HDA_DEVC 0x78
368 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
369
370 /* Define IN stream 0 FIFO size offset in VIA controller */
371 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
372 /* Define VIA HD Audio Device ID*/
373 #define VIA_HDAC_DEVICE_ID 0x3288
374
375 /* HD Audio class code */
376 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
377
378 /*
379 */
380
381 struct azx_dev {
382 struct snd_dma_buffer bdl; /* BDL buffer */
383 u32 *posbuf; /* position buffer pointer */
384
385 unsigned int bufsize; /* size of the play buffer in bytes */
386 unsigned int period_bytes; /* size of the period in bytes */
387 unsigned int frags; /* number for period in the play buffer */
388 unsigned int fifo_size; /* FIFO size */
389 unsigned long start_wallclk; /* start + minimum wallclk */
390 unsigned long period_wallclk; /* wallclk for period */
391
392 void __iomem *sd_addr; /* stream descriptor pointer */
393
394 u32 sd_int_sta_mask; /* stream int status mask */
395
396 /* pcm support */
397 struct snd_pcm_substream *substream; /* assigned substream,
398 * set in PCM open
399 */
400 unsigned int format_val; /* format value to be set in the
401 * controller and the codec
402 */
403 unsigned char stream_tag; /* assigned stream */
404 unsigned char index; /* stream index */
405 int assigned_key; /* last device# key assigned to */
406
407 unsigned int opened :1;
408 unsigned int running :1;
409 unsigned int irq_pending :1;
410 /*
411 * For VIA:
412 * A flag to ensure DMA position is 0
413 * when link position is not greater than FIFO size
414 */
415 unsigned int insufficient :1;
416 unsigned int wc_marked:1;
417 };
418
419 /* CORB/RIRB */
420 struct azx_rb {
421 u32 *buf; /* CORB/RIRB buffer
422 * Each CORB entry is 4byte, RIRB is 8byte
423 */
424 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
425 /* for RIRB */
426 unsigned short rp, wp; /* read/write pointers */
427 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
428 u32 res[AZX_MAX_CODECS]; /* last read value */
429 };
430
431 struct azx_pcm {
432 struct azx *chip;
433 struct snd_pcm *pcm;
434 struct hda_codec *codec;
435 struct hda_pcm_stream *hinfo[2];
436 struct list_head list;
437 };
438
439 struct azx {
440 struct snd_card *card;
441 struct pci_dev *pci;
442 int dev_index;
443
444 /* chip type specific */
445 int driver_type;
446 unsigned int driver_caps;
447 int playback_streams;
448 int playback_index_offset;
449 int capture_streams;
450 int capture_index_offset;
451 int num_streams;
452
453 /* pci resources */
454 unsigned long addr;
455 void __iomem *remap_addr;
456 int irq;
457
458 /* locks */
459 spinlock_t reg_lock;
460 struct mutex open_mutex;
461
462 /* streams (x num_streams) */
463 struct azx_dev *azx_dev;
464
465 /* PCM */
466 struct list_head pcm_list; /* azx_pcm list */
467
468 /* HD codec */
469 unsigned short codec_mask;
470 int codec_probe_mask; /* copied from probe_mask option */
471 struct hda_bus *bus;
472 unsigned int beep_mode;
473
474 /* CORB/RIRB */
475 struct azx_rb corb;
476 struct azx_rb rirb;
477
478 /* CORB/RIRB and position buffers */
479 struct snd_dma_buffer rb;
480 struct snd_dma_buffer posbuf;
481
482 #ifdef CONFIG_SND_HDA_PATCH_LOADER
483 const struct firmware *fw;
484 #endif
485
486 /* flags */
487 int position_fix[2]; /* for both playback/capture streams */
488 int poll_count;
489 unsigned int running :1;
490 unsigned int initialized :1;
491 unsigned int single_cmd :1;
492 unsigned int polling_mode :1;
493 unsigned int msi :1;
494 unsigned int irq_pending_warned :1;
495 unsigned int probing :1; /* codec probing phase */
496 unsigned int snoop:1;
497 unsigned int align_buffer_size:1;
498 unsigned int region_requested:1;
499
500 /* VGA-switcheroo setup */
501 unsigned int use_vga_switcheroo:1;
502 unsigned int init_failed:1; /* delayed init failed */
503 unsigned int disabled:1; /* disabled by VGA-switcher */
504
505 /* for debugging */
506 unsigned int last_cmd[AZX_MAX_CODECS];
507
508 /* for pending irqs */
509 struct work_struct irq_pending_work;
510
511 /* reboot notifier (for mysterious hangup problem at power-down) */
512 struct notifier_block reboot_notifier;
513
514 /* card list (for power_save trigger) */
515 struct list_head list;
516 };
517
518 /* driver types */
519 enum {
520 AZX_DRIVER_ICH,
521 AZX_DRIVER_PCH,
522 AZX_DRIVER_SCH,
523 AZX_DRIVER_ATI,
524 AZX_DRIVER_ATIHDMI,
525 AZX_DRIVER_ATIHDMI_NS,
526 AZX_DRIVER_VIA,
527 AZX_DRIVER_SIS,
528 AZX_DRIVER_ULI,
529 AZX_DRIVER_NVIDIA,
530 AZX_DRIVER_TERA,
531 AZX_DRIVER_CTX,
532 AZX_DRIVER_CTHDA,
533 AZX_DRIVER_GENERIC,
534 AZX_NUM_DRIVERS, /* keep this as last entry */
535 };
536
537 /* driver quirks (capabilities) */
538 /* bits 0-7 are used for indicating driver type */
539 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
540 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
541 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
542 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
543 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
544 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
545 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
546 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
547 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
548 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
549 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
550 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
551 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
552 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
553 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
554 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
555 #define AZX_DCAPS_POSFIX_COMBO (1 << 24) /* Use COMBO as default */
556
557 /* quirks for ATI SB / AMD Hudson */
558 #define AZX_DCAPS_PRESET_ATI_SB \
559 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
560 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
561
562 /* quirks for ATI/AMD HDMI */
563 #define AZX_DCAPS_PRESET_ATI_HDMI \
564 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
565
566 /* quirks for Nvidia */
567 #define AZX_DCAPS_PRESET_NVIDIA \
568 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
569 AZX_DCAPS_ALIGN_BUFSIZE)
570
571 #define AZX_DCAPS_PRESET_CTHDA \
572 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
573
574 /*
575 * VGA-switcher support
576 */
577 #ifdef SUPPORT_VGA_SWITCHEROO
578 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
579 #else
580 #define use_vga_switcheroo(chip) 0
581 #endif
582
583 #if defined(SUPPORT_VGA_SWITCHEROO) || defined(CONFIG_SND_HDA_PATCH_LOADER)
584 #define DELAYED_INIT_MARK
585 #define DELAYED_INITDATA_MARK
586 #else
587 #define DELAYED_INIT_MARK __devinit
588 #define DELAYED_INITDATA_MARK __devinitdata
589 #endif
590
591 static char *driver_short_names[] DELAYED_INITDATA_MARK = {
592 [AZX_DRIVER_ICH] = "HDA Intel",
593 [AZX_DRIVER_PCH] = "HDA Intel PCH",
594 [AZX_DRIVER_SCH] = "HDA Intel MID",
595 [AZX_DRIVER_ATI] = "HDA ATI SB",
596 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
597 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
598 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
599 [AZX_DRIVER_SIS] = "HDA SIS966",
600 [AZX_DRIVER_ULI] = "HDA ULI M5461",
601 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
602 [AZX_DRIVER_TERA] = "HDA Teradici",
603 [AZX_DRIVER_CTX] = "HDA Creative",
604 [AZX_DRIVER_CTHDA] = "HDA Creative",
605 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
606 };
607
608 /*
609 * macros for easy use
610 */
611 #define azx_writel(chip,reg,value) \
612 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
613 #define azx_readl(chip,reg) \
614 readl((chip)->remap_addr + ICH6_REG_##reg)
615 #define azx_writew(chip,reg,value) \
616 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
617 #define azx_readw(chip,reg) \
618 readw((chip)->remap_addr + ICH6_REG_##reg)
619 #define azx_writeb(chip,reg,value) \
620 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
621 #define azx_readb(chip,reg) \
622 readb((chip)->remap_addr + ICH6_REG_##reg)
623
624 #define azx_sd_writel(dev,reg,value) \
625 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
626 #define azx_sd_readl(dev,reg) \
627 readl((dev)->sd_addr + ICH6_REG_##reg)
628 #define azx_sd_writew(dev,reg,value) \
629 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
630 #define azx_sd_readw(dev,reg) \
631 readw((dev)->sd_addr + ICH6_REG_##reg)
632 #define azx_sd_writeb(dev,reg,value) \
633 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
634 #define azx_sd_readb(dev,reg) \
635 readb((dev)->sd_addr + ICH6_REG_##reg)
636
637 /* for pcm support */
638 #define get_azx_dev(substream) (substream->runtime->private_data)
639
640 #ifdef CONFIG_X86
641 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
642 {
643 if (azx_snoop(chip))
644 return;
645 if (addr && size) {
646 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
647 if (on)
648 set_memory_wc((unsigned long)addr, pages);
649 else
650 set_memory_wb((unsigned long)addr, pages);
651 }
652 }
653
654 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
655 bool on)
656 {
657 __mark_pages_wc(chip, buf->area, buf->bytes, on);
658 }
659 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
660 struct snd_pcm_runtime *runtime, bool on)
661 {
662 if (azx_dev->wc_marked != on) {
663 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
664 azx_dev->wc_marked = on;
665 }
666 }
667 #else
668 /* NOP for other archs */
669 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
670 bool on)
671 {
672 }
673 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
674 struct snd_pcm_runtime *runtime, bool on)
675 {
676 }
677 #endif
678
679 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
680 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
681 /*
682 * Interface for HD codec
683 */
684
685 /*
686 * CORB / RIRB interface
687 */
688 static int azx_alloc_cmd_io(struct azx *chip)
689 {
690 int err;
691
692 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
693 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
694 snd_dma_pci_data(chip->pci),
695 PAGE_SIZE, &chip->rb);
696 if (err < 0) {
697 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
698 return err;
699 }
700 mark_pages_wc(chip, &chip->rb, true);
701 return 0;
702 }
703
704 static void azx_init_cmd_io(struct azx *chip)
705 {
706 spin_lock_irq(&chip->reg_lock);
707 /* CORB set up */
708 chip->corb.addr = chip->rb.addr;
709 chip->corb.buf = (u32 *)chip->rb.area;
710 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
711 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
712
713 /* set the corb size to 256 entries (ULI requires explicitly) */
714 azx_writeb(chip, CORBSIZE, 0x02);
715 /* set the corb write pointer to 0 */
716 azx_writew(chip, CORBWP, 0);
717 /* reset the corb hw read pointer */
718 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
719 /* enable corb dma */
720 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
721
722 /* RIRB set up */
723 chip->rirb.addr = chip->rb.addr + 2048;
724 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
725 chip->rirb.wp = chip->rirb.rp = 0;
726 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
727 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
728 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
729
730 /* set the rirb size to 256 entries (ULI requires explicitly) */
731 azx_writeb(chip, RIRBSIZE, 0x02);
732 /* reset the rirb hw write pointer */
733 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
734 /* set N=1, get RIRB response interrupt for new entry */
735 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
736 azx_writew(chip, RINTCNT, 0xc0);
737 else
738 azx_writew(chip, RINTCNT, 1);
739 /* enable rirb dma and response irq */
740 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
741 spin_unlock_irq(&chip->reg_lock);
742 }
743
744 static void azx_free_cmd_io(struct azx *chip)
745 {
746 spin_lock_irq(&chip->reg_lock);
747 /* disable ringbuffer DMAs */
748 azx_writeb(chip, RIRBCTL, 0);
749 azx_writeb(chip, CORBCTL, 0);
750 spin_unlock_irq(&chip->reg_lock);
751 }
752
753 static unsigned int azx_command_addr(u32 cmd)
754 {
755 unsigned int addr = cmd >> 28;
756
757 if (addr >= AZX_MAX_CODECS) {
758 snd_BUG();
759 addr = 0;
760 }
761
762 return addr;
763 }
764
765 static unsigned int azx_response_addr(u32 res)
766 {
767 unsigned int addr = res & 0xf;
768
769 if (addr >= AZX_MAX_CODECS) {
770 snd_BUG();
771 addr = 0;
772 }
773
774 return addr;
775 }
776
777 /* send a command */
778 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
779 {
780 struct azx *chip = bus->private_data;
781 unsigned int addr = azx_command_addr(val);
782 unsigned int wp;
783
784 spin_lock_irq(&chip->reg_lock);
785
786 /* add command to corb */
787 wp = azx_readb(chip, CORBWP);
788 wp++;
789 wp %= ICH6_MAX_CORB_ENTRIES;
790
791 chip->rirb.cmds[addr]++;
792 chip->corb.buf[wp] = cpu_to_le32(val);
793 azx_writel(chip, CORBWP, wp);
794
795 spin_unlock_irq(&chip->reg_lock);
796
797 return 0;
798 }
799
800 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
801
802 /* retrieve RIRB entry - called from interrupt handler */
803 static void azx_update_rirb(struct azx *chip)
804 {
805 unsigned int rp, wp;
806 unsigned int addr;
807 u32 res, res_ex;
808
809 wp = azx_readb(chip, RIRBWP);
810 if (wp == chip->rirb.wp)
811 return;
812 chip->rirb.wp = wp;
813
814 while (chip->rirb.rp != wp) {
815 chip->rirb.rp++;
816 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
817
818 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
819 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
820 res = le32_to_cpu(chip->rirb.buf[rp]);
821 addr = azx_response_addr(res_ex);
822 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
823 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
824 else if (chip->rirb.cmds[addr]) {
825 chip->rirb.res[addr] = res;
826 smp_wmb();
827 chip->rirb.cmds[addr]--;
828 } else
829 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
830 "last cmd=%#08x\n",
831 res, res_ex,
832 chip->last_cmd[addr]);
833 }
834 }
835
836 /* receive a response */
837 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
838 unsigned int addr)
839 {
840 struct azx *chip = bus->private_data;
841 unsigned long timeout;
842 unsigned long loopcounter;
843 int do_poll = 0;
844
845 again:
846 timeout = jiffies + msecs_to_jiffies(1000);
847
848 for (loopcounter = 0;; loopcounter++) {
849 if (chip->polling_mode || do_poll) {
850 spin_lock_irq(&chip->reg_lock);
851 azx_update_rirb(chip);
852 spin_unlock_irq(&chip->reg_lock);
853 }
854 if (!chip->rirb.cmds[addr]) {
855 smp_rmb();
856 bus->rirb_error = 0;
857
858 if (!do_poll)
859 chip->poll_count = 0;
860 return chip->rirb.res[addr]; /* the last value */
861 }
862 if (time_after(jiffies, timeout))
863 break;
864 if (bus->needs_damn_long_delay || loopcounter > 3000)
865 msleep(2); /* temporary workaround */
866 else {
867 udelay(10);
868 cond_resched();
869 }
870 }
871
872 if (!chip->polling_mode && chip->poll_count < 2) {
873 snd_printdd(SFX "azx_get_response timeout, "
874 "polling the codec once: last cmd=0x%08x\n",
875 chip->last_cmd[addr]);
876 do_poll = 1;
877 chip->poll_count++;
878 goto again;
879 }
880
881
882 if (!chip->polling_mode) {
883 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
884 "switching to polling mode: last cmd=0x%08x\n",
885 chip->last_cmd[addr]);
886 chip->polling_mode = 1;
887 goto again;
888 }
889
890 if (chip->msi) {
891 snd_printk(KERN_WARNING SFX "No response from codec, "
892 "disabling MSI: last cmd=0x%08x\n",
893 chip->last_cmd[addr]);
894 free_irq(chip->irq, chip);
895 chip->irq = -1;
896 pci_disable_msi(chip->pci);
897 chip->msi = 0;
898 if (azx_acquire_irq(chip, 1) < 0) {
899 bus->rirb_error = 1;
900 return -1;
901 }
902 goto again;
903 }
904
905 if (chip->probing) {
906 /* If this critical timeout happens during the codec probing
907 * phase, this is likely an access to a non-existing codec
908 * slot. Better to return an error and reset the system.
909 */
910 return -1;
911 }
912
913 /* a fatal communication error; need either to reset or to fallback
914 * to the single_cmd mode
915 */
916 bus->rirb_error = 1;
917 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
918 bus->response_reset = 1;
919 return -1; /* give a chance to retry */
920 }
921
922 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
923 "switching to single_cmd mode: last cmd=0x%08x\n",
924 chip->last_cmd[addr]);
925 chip->single_cmd = 1;
926 bus->response_reset = 0;
927 /* release CORB/RIRB */
928 azx_free_cmd_io(chip);
929 /* disable unsolicited responses */
930 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
931 return -1;
932 }
933
934 /*
935 * Use the single immediate command instead of CORB/RIRB for simplicity
936 *
937 * Note: according to Intel, this is not preferred use. The command was
938 * intended for the BIOS only, and may get confused with unsolicited
939 * responses. So, we shouldn't use it for normal operation from the
940 * driver.
941 * I left the codes, however, for debugging/testing purposes.
942 */
943
944 /* receive a response */
945 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
946 {
947 int timeout = 50;
948
949 while (timeout--) {
950 /* check IRV busy bit */
951 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
952 /* reuse rirb.res as the response return value */
953 chip->rirb.res[addr] = azx_readl(chip, IR);
954 return 0;
955 }
956 udelay(1);
957 }
958 if (printk_ratelimit())
959 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
960 azx_readw(chip, IRS));
961 chip->rirb.res[addr] = -1;
962 return -EIO;
963 }
964
965 /* send a command */
966 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
967 {
968 struct azx *chip = bus->private_data;
969 unsigned int addr = azx_command_addr(val);
970 int timeout = 50;
971
972 bus->rirb_error = 0;
973 while (timeout--) {
974 /* check ICB busy bit */
975 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
976 /* Clear IRV valid bit */
977 azx_writew(chip, IRS, azx_readw(chip, IRS) |
978 ICH6_IRS_VALID);
979 azx_writel(chip, IC, val);
980 azx_writew(chip, IRS, azx_readw(chip, IRS) |
981 ICH6_IRS_BUSY);
982 return azx_single_wait_for_response(chip, addr);
983 }
984 udelay(1);
985 }
986 if (printk_ratelimit())
987 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
988 azx_readw(chip, IRS), val);
989 return -EIO;
990 }
991
992 /* receive a response */
993 static unsigned int azx_single_get_response(struct hda_bus *bus,
994 unsigned int addr)
995 {
996 struct azx *chip = bus->private_data;
997 return chip->rirb.res[addr];
998 }
999
1000 /*
1001 * The below are the main callbacks from hda_codec.
1002 *
1003 * They are just the skeleton to call sub-callbacks according to the
1004 * current setting of chip->single_cmd.
1005 */
1006
1007 /* send a command */
1008 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1009 {
1010 struct azx *chip = bus->private_data;
1011
1012 if (chip->disabled)
1013 return 0;
1014 chip->last_cmd[azx_command_addr(val)] = val;
1015 if (chip->single_cmd)
1016 return azx_single_send_cmd(bus, val);
1017 else
1018 return azx_corb_send_cmd(bus, val);
1019 }
1020
1021 /* get a response */
1022 static unsigned int azx_get_response(struct hda_bus *bus,
1023 unsigned int addr)
1024 {
1025 struct azx *chip = bus->private_data;
1026 if (chip->disabled)
1027 return 0;
1028 if (chip->single_cmd)
1029 return azx_single_get_response(bus, addr);
1030 else
1031 return azx_rirb_get_response(bus, addr);
1032 }
1033
1034 #ifdef CONFIG_SND_HDA_POWER_SAVE
1035 static void azx_power_notify(struct hda_bus *bus);
1036 #endif
1037
1038 /* reset codec link */
1039 static int azx_reset(struct azx *chip, int full_reset)
1040 {
1041 int count;
1042
1043 if (!full_reset)
1044 goto __skip;
1045
1046 /* clear STATESTS */
1047 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1048
1049 /* reset controller */
1050 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1051
1052 count = 50;
1053 while (azx_readb(chip, GCTL) && --count)
1054 msleep(1);
1055
1056 /* delay for >= 100us for codec PLL to settle per spec
1057 * Rev 0.9 section 5.5.1
1058 */
1059 msleep(1);
1060
1061 /* Bring controller out of reset */
1062 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1063
1064 count = 50;
1065 while (!azx_readb(chip, GCTL) && --count)
1066 msleep(1);
1067
1068 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1069 msleep(1);
1070
1071 __skip:
1072 /* check to see if controller is ready */
1073 if (!azx_readb(chip, GCTL)) {
1074 snd_printd(SFX "azx_reset: controller not ready!\n");
1075 return -EBUSY;
1076 }
1077
1078 /* Accept unsolicited responses */
1079 if (!chip->single_cmd)
1080 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1081 ICH6_GCTL_UNSOL);
1082
1083 /* detect codecs */
1084 if (!chip->codec_mask) {
1085 chip->codec_mask = azx_readw(chip, STATESTS);
1086 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1087 }
1088
1089 return 0;
1090 }
1091
1092
1093 /*
1094 * Lowlevel interface
1095 */
1096
1097 /* enable interrupts */
1098 static void azx_int_enable(struct azx *chip)
1099 {
1100 /* enable controller CIE and GIE */
1101 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1102 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1103 }
1104
1105 /* disable interrupts */
1106 static void azx_int_disable(struct azx *chip)
1107 {
1108 int i;
1109
1110 /* disable interrupts in stream descriptor */
1111 for (i = 0; i < chip->num_streams; i++) {
1112 struct azx_dev *azx_dev = &chip->azx_dev[i];
1113 azx_sd_writeb(azx_dev, SD_CTL,
1114 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1115 }
1116
1117 /* disable SIE for all streams */
1118 azx_writeb(chip, INTCTL, 0);
1119
1120 /* disable controller CIE and GIE */
1121 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1122 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1123 }
1124
1125 /* clear interrupts */
1126 static void azx_int_clear(struct azx *chip)
1127 {
1128 int i;
1129
1130 /* clear stream status */
1131 for (i = 0; i < chip->num_streams; i++) {
1132 struct azx_dev *azx_dev = &chip->azx_dev[i];
1133 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1134 }
1135
1136 /* clear STATESTS */
1137 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1138
1139 /* clear rirb status */
1140 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1141
1142 /* clear int status */
1143 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1144 }
1145
1146 /* start a stream */
1147 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1148 {
1149 /*
1150 * Before stream start, initialize parameter
1151 */
1152 azx_dev->insufficient = 1;
1153
1154 /* enable SIE */
1155 azx_writel(chip, INTCTL,
1156 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1157 /* set DMA start and interrupt mask */
1158 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1159 SD_CTL_DMA_START | SD_INT_MASK);
1160 }
1161
1162 /* stop DMA */
1163 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1164 {
1165 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1166 ~(SD_CTL_DMA_START | SD_INT_MASK));
1167 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1168 }
1169
1170 /* stop a stream */
1171 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1172 {
1173 azx_stream_clear(chip, azx_dev);
1174 /* disable SIE */
1175 azx_writel(chip, INTCTL,
1176 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1177 }
1178
1179
1180 /*
1181 * reset and start the controller registers
1182 */
1183 static void azx_init_chip(struct azx *chip, int full_reset)
1184 {
1185 if (chip->initialized)
1186 return;
1187
1188 /* reset controller */
1189 azx_reset(chip, full_reset);
1190
1191 /* initialize interrupts */
1192 azx_int_clear(chip);
1193 azx_int_enable(chip);
1194
1195 /* initialize the codec command I/O */
1196 if (!chip->single_cmd)
1197 azx_init_cmd_io(chip);
1198
1199 /* program the position buffer */
1200 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1201 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1202
1203 chip->initialized = 1;
1204 }
1205
1206 /*
1207 * initialize the PCI registers
1208 */
1209 /* update bits in a PCI register byte */
1210 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1211 unsigned char mask, unsigned char val)
1212 {
1213 unsigned char data;
1214
1215 pci_read_config_byte(pci, reg, &data);
1216 data &= ~mask;
1217 data |= (val & mask);
1218 pci_write_config_byte(pci, reg, data);
1219 }
1220
1221 static void azx_init_pci(struct azx *chip)
1222 {
1223 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1224 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1225 * Ensuring these bits are 0 clears playback static on some HD Audio
1226 * codecs.
1227 * The PCI register TCSEL is defined in the Intel manuals.
1228 */
1229 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1230 snd_printdd(SFX "Clearing TCSEL\n");
1231 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1232 }
1233
1234 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1235 * we need to enable snoop.
1236 */
1237 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1238 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1239 update_pci_byte(chip->pci,
1240 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1241 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1242 }
1243
1244 /* For NVIDIA HDA, enable snoop */
1245 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1246 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1247 update_pci_byte(chip->pci,
1248 NVIDIA_HDA_TRANSREG_ADDR,
1249 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1250 update_pci_byte(chip->pci,
1251 NVIDIA_HDA_ISTRM_COH,
1252 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1253 update_pci_byte(chip->pci,
1254 NVIDIA_HDA_OSTRM_COH,
1255 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1256 }
1257
1258 /* Enable SCH/PCH snoop if needed */
1259 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1260 unsigned short snoop;
1261 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1262 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1263 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1264 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1265 if (!azx_snoop(chip))
1266 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1267 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1268 pci_read_config_word(chip->pci,
1269 INTEL_SCH_HDA_DEVC, &snoop);
1270 }
1271 snd_printdd(SFX "SCH snoop: %s\n",
1272 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1273 ? "Disabled" : "Enabled");
1274 }
1275 }
1276
1277
1278 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1279
1280 /*
1281 * interrupt handler
1282 */
1283 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1284 {
1285 struct azx *chip = dev_id;
1286 struct azx_dev *azx_dev;
1287 u32 status;
1288 u8 sd_status;
1289 int i, ok;
1290
1291 spin_lock(&chip->reg_lock);
1292
1293 if (chip->disabled) {
1294 spin_unlock(&chip->reg_lock);
1295 return IRQ_NONE;
1296 }
1297
1298 status = azx_readl(chip, INTSTS);
1299 if (status == 0) {
1300 spin_unlock(&chip->reg_lock);
1301 return IRQ_NONE;
1302 }
1303
1304 for (i = 0; i < chip->num_streams; i++) {
1305 azx_dev = &chip->azx_dev[i];
1306 if (status & azx_dev->sd_int_sta_mask) {
1307 sd_status = azx_sd_readb(azx_dev, SD_STS);
1308 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1309 if (!azx_dev->substream || !azx_dev->running ||
1310 !(sd_status & SD_INT_COMPLETE))
1311 continue;
1312 /* check whether this IRQ is really acceptable */
1313 ok = azx_position_ok(chip, azx_dev);
1314 if (ok == 1) {
1315 azx_dev->irq_pending = 0;
1316 spin_unlock(&chip->reg_lock);
1317 snd_pcm_period_elapsed(azx_dev->substream);
1318 spin_lock(&chip->reg_lock);
1319 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1320 /* bogus IRQ, process it later */
1321 azx_dev->irq_pending = 1;
1322 queue_work(chip->bus->workq,
1323 &chip->irq_pending_work);
1324 }
1325 }
1326 }
1327
1328 /* clear rirb int */
1329 status = azx_readb(chip, RIRBSTS);
1330 if (status & RIRB_INT_MASK) {
1331 if (status & RIRB_INT_RESPONSE) {
1332 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1333 udelay(80);
1334 azx_update_rirb(chip);
1335 }
1336 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1337 }
1338
1339 #if 0
1340 /* clear state status int */
1341 if (azx_readb(chip, STATESTS) & 0x04)
1342 azx_writeb(chip, STATESTS, 0x04);
1343 #endif
1344 spin_unlock(&chip->reg_lock);
1345
1346 return IRQ_HANDLED;
1347 }
1348
1349
1350 /*
1351 * set up a BDL entry
1352 */
1353 static int setup_bdle(struct azx *chip,
1354 struct snd_pcm_substream *substream,
1355 struct azx_dev *azx_dev, u32 **bdlp,
1356 int ofs, int size, int with_ioc)
1357 {
1358 u32 *bdl = *bdlp;
1359
1360 while (size > 0) {
1361 dma_addr_t addr;
1362 int chunk;
1363
1364 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1365 return -EINVAL;
1366
1367 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1368 /* program the address field of the BDL entry */
1369 bdl[0] = cpu_to_le32((u32)addr);
1370 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1371 /* program the size field of the BDL entry */
1372 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1373 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1374 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1375 u32 remain = 0x1000 - (ofs & 0xfff);
1376 if (chunk > remain)
1377 chunk = remain;
1378 }
1379 bdl[2] = cpu_to_le32(chunk);
1380 /* program the IOC to enable interrupt
1381 * only when the whole fragment is processed
1382 */
1383 size -= chunk;
1384 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1385 bdl += 4;
1386 azx_dev->frags++;
1387 ofs += chunk;
1388 }
1389 *bdlp = bdl;
1390 return ofs;
1391 }
1392
1393 /*
1394 * set up BDL entries
1395 */
1396 static int azx_setup_periods(struct azx *chip,
1397 struct snd_pcm_substream *substream,
1398 struct azx_dev *azx_dev)
1399 {
1400 u32 *bdl;
1401 int i, ofs, periods, period_bytes;
1402 int pos_adj;
1403
1404 /* reset BDL address */
1405 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1406 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1407
1408 period_bytes = azx_dev->period_bytes;
1409 periods = azx_dev->bufsize / period_bytes;
1410
1411 /* program the initial BDL entries */
1412 bdl = (u32 *)azx_dev->bdl.area;
1413 ofs = 0;
1414 azx_dev->frags = 0;
1415 pos_adj = bdl_pos_adj[chip->dev_index];
1416 if (pos_adj > 0) {
1417 struct snd_pcm_runtime *runtime = substream->runtime;
1418 int pos_align = pos_adj;
1419 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1420 if (!pos_adj)
1421 pos_adj = pos_align;
1422 else
1423 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1424 pos_align;
1425 pos_adj = frames_to_bytes(runtime, pos_adj);
1426 if (pos_adj >= period_bytes) {
1427 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1428 bdl_pos_adj[chip->dev_index]);
1429 pos_adj = 0;
1430 } else {
1431 ofs = setup_bdle(chip, substream, azx_dev,
1432 &bdl, ofs, pos_adj,
1433 !substream->runtime->no_period_wakeup);
1434 if (ofs < 0)
1435 goto error;
1436 }
1437 } else
1438 pos_adj = 0;
1439 for (i = 0; i < periods; i++) {
1440 if (i == periods - 1 && pos_adj)
1441 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1442 period_bytes - pos_adj, 0);
1443 else
1444 ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1445 period_bytes,
1446 !substream->runtime->no_period_wakeup);
1447 if (ofs < 0)
1448 goto error;
1449 }
1450 return 0;
1451
1452 error:
1453 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1454 azx_dev->bufsize, period_bytes);
1455 return -EINVAL;
1456 }
1457
1458 /* reset stream */
1459 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1460 {
1461 unsigned char val;
1462 int timeout;
1463
1464 azx_stream_clear(chip, azx_dev);
1465
1466 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1467 SD_CTL_STREAM_RESET);
1468 udelay(3);
1469 timeout = 300;
1470 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1471 --timeout)
1472 ;
1473 val &= ~SD_CTL_STREAM_RESET;
1474 azx_sd_writeb(azx_dev, SD_CTL, val);
1475 udelay(3);
1476
1477 timeout = 300;
1478 /* waiting for hardware to report that the stream is out of reset */
1479 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1480 --timeout)
1481 ;
1482
1483 /* reset first position - may not be synced with hw at this time */
1484 *azx_dev->posbuf = 0;
1485 }
1486
1487 /*
1488 * set up the SD for streaming
1489 */
1490 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1491 {
1492 unsigned int val;
1493 /* make sure the run bit is zero for SD */
1494 azx_stream_clear(chip, azx_dev);
1495 /* program the stream_tag */
1496 val = azx_sd_readl(azx_dev, SD_CTL);
1497 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1498 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1499 if (!azx_snoop(chip))
1500 val |= SD_CTL_TRAFFIC_PRIO;
1501 azx_sd_writel(azx_dev, SD_CTL, val);
1502
1503 /* program the length of samples in cyclic buffer */
1504 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1505
1506 /* program the stream format */
1507 /* this value needs to be the same as the one programmed */
1508 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1509
1510 /* program the stream LVI (last valid index) of the BDL */
1511 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1512
1513 /* program the BDL address */
1514 /* lower BDL address */
1515 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1516 /* upper BDL address */
1517 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1518
1519 /* enable the position buffer */
1520 if (chip->position_fix[0] != POS_FIX_LPIB ||
1521 chip->position_fix[1] != POS_FIX_LPIB) {
1522 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1523 azx_writel(chip, DPLBASE,
1524 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1525 }
1526
1527 /* set the interrupt enable bits in the descriptor control register */
1528 azx_sd_writel(azx_dev, SD_CTL,
1529 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1530
1531 return 0;
1532 }
1533
1534 /*
1535 * Probe the given codec address
1536 */
1537 static int probe_codec(struct azx *chip, int addr)
1538 {
1539 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1540 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1541 unsigned int res;
1542
1543 mutex_lock(&chip->bus->cmd_mutex);
1544 chip->probing = 1;
1545 azx_send_cmd(chip->bus, cmd);
1546 res = azx_get_response(chip->bus, addr);
1547 chip->probing = 0;
1548 mutex_unlock(&chip->bus->cmd_mutex);
1549 if (res == -1)
1550 return -EIO;
1551 snd_printdd(SFX "codec #%d probed OK\n", addr);
1552 return 0;
1553 }
1554
1555 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1556 struct hda_pcm *cpcm);
1557 static void azx_stop_chip(struct azx *chip);
1558
1559 static void azx_bus_reset(struct hda_bus *bus)
1560 {
1561 struct azx *chip = bus->private_data;
1562
1563 bus->in_reset = 1;
1564 azx_stop_chip(chip);
1565 azx_init_chip(chip, 1);
1566 #ifdef CONFIG_PM
1567 if (chip->initialized) {
1568 struct azx_pcm *p;
1569 list_for_each_entry(p, &chip->pcm_list, list)
1570 snd_pcm_suspend_all(p->pcm);
1571 snd_hda_suspend(chip->bus);
1572 snd_hda_resume(chip->bus);
1573 }
1574 #endif
1575 bus->in_reset = 0;
1576 }
1577
1578 /*
1579 * Codec initialization
1580 */
1581
1582 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1583 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] DELAYED_INITDATA_MARK = {
1584 [AZX_DRIVER_NVIDIA] = 8,
1585 [AZX_DRIVER_TERA] = 1,
1586 };
1587
1588 static int DELAYED_INIT_MARK azx_codec_create(struct azx *chip, const char *model)
1589 {
1590 struct hda_bus_template bus_temp;
1591 int c, codecs, err;
1592 int max_slots;
1593
1594 memset(&bus_temp, 0, sizeof(bus_temp));
1595 bus_temp.private_data = chip;
1596 bus_temp.modelname = model;
1597 bus_temp.pci = chip->pci;
1598 bus_temp.ops.command = azx_send_cmd;
1599 bus_temp.ops.get_response = azx_get_response;
1600 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1601 bus_temp.ops.bus_reset = azx_bus_reset;
1602 #ifdef CONFIG_SND_HDA_POWER_SAVE
1603 bus_temp.power_save = &power_save;
1604 bus_temp.ops.pm_notify = azx_power_notify;
1605 #endif
1606
1607 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1608 if (err < 0)
1609 return err;
1610
1611 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1612 snd_printd(SFX "Enable delay in RIRB handling\n");
1613 chip->bus->needs_damn_long_delay = 1;
1614 }
1615
1616 codecs = 0;
1617 max_slots = azx_max_codecs[chip->driver_type];
1618 if (!max_slots)
1619 max_slots = AZX_DEFAULT_CODECS;
1620
1621 /* First try to probe all given codec slots */
1622 for (c = 0; c < max_slots; c++) {
1623 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1624 if (probe_codec(chip, c) < 0) {
1625 /* Some BIOSen give you wrong codec addresses
1626 * that don't exist
1627 */
1628 snd_printk(KERN_WARNING SFX
1629 "Codec #%d probe error; "
1630 "disabling it...\n", c);
1631 chip->codec_mask &= ~(1 << c);
1632 /* More badly, accessing to a non-existing
1633 * codec often screws up the controller chip,
1634 * and disturbs the further communications.
1635 * Thus if an error occurs during probing,
1636 * better to reset the controller chip to
1637 * get back to the sanity state.
1638 */
1639 azx_stop_chip(chip);
1640 azx_init_chip(chip, 1);
1641 }
1642 }
1643 }
1644
1645 /* AMD chipsets often cause the communication stalls upon certain
1646 * sequence like the pin-detection. It seems that forcing the synced
1647 * access works around the stall. Grrr...
1648 */
1649 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1650 snd_printd(SFX "Enable sync_write for stable communication\n");
1651 chip->bus->sync_write = 1;
1652 chip->bus->allow_bus_reset = 1;
1653 }
1654
1655 /* Then create codec instances */
1656 for (c = 0; c < max_slots; c++) {
1657 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1658 struct hda_codec *codec;
1659 err = snd_hda_codec_new(chip->bus, c, &codec);
1660 if (err < 0)
1661 continue;
1662 codec->beep_mode = chip->beep_mode;
1663 codecs++;
1664 }
1665 }
1666 if (!codecs) {
1667 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1668 return -ENXIO;
1669 }
1670 return 0;
1671 }
1672
1673 /* configure each codec instance */
1674 static int __devinit azx_codec_configure(struct azx *chip)
1675 {
1676 struct hda_codec *codec;
1677 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1678 snd_hda_codec_configure(codec);
1679 }
1680 return 0;
1681 }
1682
1683
1684 /*
1685 * PCM support
1686 */
1687
1688 /* assign a stream for the PCM */
1689 static inline struct azx_dev *
1690 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1691 {
1692 int dev, i, nums;
1693 struct azx_dev *res = NULL;
1694 /* make a non-zero unique key for the substream */
1695 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1696 (substream->stream + 1);
1697
1698 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1699 dev = chip->playback_index_offset;
1700 nums = chip->playback_streams;
1701 } else {
1702 dev = chip->capture_index_offset;
1703 nums = chip->capture_streams;
1704 }
1705 for (i = 0; i < nums; i++, dev++)
1706 if (!chip->azx_dev[dev].opened) {
1707 res = &chip->azx_dev[dev];
1708 if (res->assigned_key == key)
1709 break;
1710 }
1711 if (res) {
1712 res->opened = 1;
1713 res->assigned_key = key;
1714 }
1715 return res;
1716 }
1717
1718 /* release the assigned stream */
1719 static inline void azx_release_device(struct azx_dev *azx_dev)
1720 {
1721 azx_dev->opened = 0;
1722 }
1723
1724 static struct snd_pcm_hardware azx_pcm_hw = {
1725 .info = (SNDRV_PCM_INFO_MMAP |
1726 SNDRV_PCM_INFO_INTERLEAVED |
1727 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1728 SNDRV_PCM_INFO_MMAP_VALID |
1729 /* No full-resume yet implemented */
1730 /* SNDRV_PCM_INFO_RESUME |*/
1731 SNDRV_PCM_INFO_PAUSE |
1732 SNDRV_PCM_INFO_SYNC_START |
1733 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1734 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1735 .rates = SNDRV_PCM_RATE_48000,
1736 .rate_min = 48000,
1737 .rate_max = 48000,
1738 .channels_min = 2,
1739 .channels_max = 2,
1740 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1741 .period_bytes_min = 128,
1742 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1743 .periods_min = 2,
1744 .periods_max = AZX_MAX_FRAG,
1745 .fifo_size = 0,
1746 };
1747
1748 static int azx_pcm_open(struct snd_pcm_substream *substream)
1749 {
1750 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1751 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1752 struct azx *chip = apcm->chip;
1753 struct azx_dev *azx_dev;
1754 struct snd_pcm_runtime *runtime = substream->runtime;
1755 unsigned long flags;
1756 int err;
1757 int buff_step;
1758
1759 mutex_lock(&chip->open_mutex);
1760 azx_dev = azx_assign_device(chip, substream);
1761 if (azx_dev == NULL) {
1762 mutex_unlock(&chip->open_mutex);
1763 return -EBUSY;
1764 }
1765 runtime->hw = azx_pcm_hw;
1766 runtime->hw.channels_min = hinfo->channels_min;
1767 runtime->hw.channels_max = hinfo->channels_max;
1768 runtime->hw.formats = hinfo->formats;
1769 runtime->hw.rates = hinfo->rates;
1770 snd_pcm_limit_hw_rates(runtime);
1771 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1772 if (chip->align_buffer_size)
1773 /* constrain buffer sizes to be multiple of 128
1774 bytes. This is more efficient in terms of memory
1775 access but isn't required by the HDA spec and
1776 prevents users from specifying exact period/buffer
1777 sizes. For example for 44.1kHz, a period size set
1778 to 20ms will be rounded to 19.59ms. */
1779 buff_step = 128;
1780 else
1781 /* Don't enforce steps on buffer sizes, still need to
1782 be multiple of 4 bytes (HDA spec). Tested on Intel
1783 HDA controllers, may not work on all devices where
1784 option needs to be disabled */
1785 buff_step = 4;
1786
1787 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1788 buff_step);
1789 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1790 buff_step);
1791 snd_hda_power_up_d3wait(apcm->codec);
1792 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1793 if (err < 0) {
1794 azx_release_device(azx_dev);
1795 snd_hda_power_down(apcm->codec);
1796 mutex_unlock(&chip->open_mutex);
1797 return err;
1798 }
1799 snd_pcm_limit_hw_rates(runtime);
1800 /* sanity check */
1801 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1802 snd_BUG_ON(!runtime->hw.channels_max) ||
1803 snd_BUG_ON(!runtime->hw.formats) ||
1804 snd_BUG_ON(!runtime->hw.rates)) {
1805 azx_release_device(azx_dev);
1806 hinfo->ops.close(hinfo, apcm->codec, substream);
1807 snd_hda_power_down(apcm->codec);
1808 mutex_unlock(&chip->open_mutex);
1809 return -EINVAL;
1810 }
1811 spin_lock_irqsave(&chip->reg_lock, flags);
1812 azx_dev->substream = substream;
1813 azx_dev->running = 0;
1814 spin_unlock_irqrestore(&chip->reg_lock, flags);
1815
1816 runtime->private_data = azx_dev;
1817 snd_pcm_set_sync(substream);
1818 mutex_unlock(&chip->open_mutex);
1819 return 0;
1820 }
1821
1822 static int azx_pcm_close(struct snd_pcm_substream *substream)
1823 {
1824 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1825 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1826 struct azx *chip = apcm->chip;
1827 struct azx_dev *azx_dev = get_azx_dev(substream);
1828 unsigned long flags;
1829
1830 mutex_lock(&chip->open_mutex);
1831 spin_lock_irqsave(&chip->reg_lock, flags);
1832 azx_dev->substream = NULL;
1833 azx_dev->running = 0;
1834 spin_unlock_irqrestore(&chip->reg_lock, flags);
1835 azx_release_device(azx_dev);
1836 hinfo->ops.close(hinfo, apcm->codec, substream);
1837 snd_hda_power_down(apcm->codec);
1838 mutex_unlock(&chip->open_mutex);
1839 return 0;
1840 }
1841
1842 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1843 struct snd_pcm_hw_params *hw_params)
1844 {
1845 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1846 struct azx *chip = apcm->chip;
1847 struct snd_pcm_runtime *runtime = substream->runtime;
1848 struct azx_dev *azx_dev = get_azx_dev(substream);
1849 int ret;
1850
1851 mark_runtime_wc(chip, azx_dev, runtime, false);
1852 azx_dev->bufsize = 0;
1853 azx_dev->period_bytes = 0;
1854 azx_dev->format_val = 0;
1855 ret = snd_pcm_lib_malloc_pages(substream,
1856 params_buffer_bytes(hw_params));
1857 if (ret < 0)
1858 return ret;
1859 mark_runtime_wc(chip, azx_dev, runtime, true);
1860 return ret;
1861 }
1862
1863 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1864 {
1865 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1866 struct azx_dev *azx_dev = get_azx_dev(substream);
1867 struct azx *chip = apcm->chip;
1868 struct snd_pcm_runtime *runtime = substream->runtime;
1869 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1870
1871 /* reset BDL address */
1872 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1873 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1874 azx_sd_writel(azx_dev, SD_CTL, 0);
1875 azx_dev->bufsize = 0;
1876 azx_dev->period_bytes = 0;
1877 azx_dev->format_val = 0;
1878
1879 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1880
1881 mark_runtime_wc(chip, azx_dev, runtime, false);
1882 return snd_pcm_lib_free_pages(substream);
1883 }
1884
1885 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1886 {
1887 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1888 struct azx *chip = apcm->chip;
1889 struct azx_dev *azx_dev = get_azx_dev(substream);
1890 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1891 struct snd_pcm_runtime *runtime = substream->runtime;
1892 unsigned int bufsize, period_bytes, format_val, stream_tag;
1893 int err;
1894 struct hda_spdif_out *spdif =
1895 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1896 unsigned short ctls = spdif ? spdif->ctls : 0;
1897
1898 azx_stream_reset(chip, azx_dev);
1899 format_val = snd_hda_calc_stream_format(runtime->rate,
1900 runtime->channels,
1901 runtime->format,
1902 hinfo->maxbps,
1903 ctls);
1904 if (!format_val) {
1905 snd_printk(KERN_ERR SFX
1906 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1907 runtime->rate, runtime->channels, runtime->format);
1908 return -EINVAL;
1909 }
1910
1911 bufsize = snd_pcm_lib_buffer_bytes(substream);
1912 period_bytes = snd_pcm_lib_period_bytes(substream);
1913
1914 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1915 bufsize, format_val);
1916
1917 if (bufsize != azx_dev->bufsize ||
1918 period_bytes != azx_dev->period_bytes ||
1919 format_val != azx_dev->format_val) {
1920 azx_dev->bufsize = bufsize;
1921 azx_dev->period_bytes = period_bytes;
1922 azx_dev->format_val = format_val;
1923 err = azx_setup_periods(chip, substream, azx_dev);
1924 if (err < 0)
1925 return err;
1926 }
1927
1928 /* wallclk has 24Mhz clock source */
1929 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1930 runtime->rate) * 1000);
1931 azx_setup_controller(chip, azx_dev);
1932 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1933 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1934 else
1935 azx_dev->fifo_size = 0;
1936
1937 stream_tag = azx_dev->stream_tag;
1938 /* CA-IBG chips need the playback stream starting from 1 */
1939 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1940 stream_tag > chip->capture_streams)
1941 stream_tag -= chip->capture_streams;
1942 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1943 azx_dev->format_val, substream);
1944 }
1945
1946 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1947 {
1948 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1949 struct azx *chip = apcm->chip;
1950 struct azx_dev *azx_dev;
1951 struct snd_pcm_substream *s;
1952 int rstart = 0, start, nsync = 0, sbits = 0;
1953 int nwait, timeout;
1954
1955 switch (cmd) {
1956 case SNDRV_PCM_TRIGGER_START:
1957 rstart = 1;
1958 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1959 case SNDRV_PCM_TRIGGER_RESUME:
1960 start = 1;
1961 break;
1962 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1963 case SNDRV_PCM_TRIGGER_SUSPEND:
1964 case SNDRV_PCM_TRIGGER_STOP:
1965 start = 0;
1966 break;
1967 default:
1968 return -EINVAL;
1969 }
1970
1971 snd_pcm_group_for_each_entry(s, substream) {
1972 if (s->pcm->card != substream->pcm->card)
1973 continue;
1974 azx_dev = get_azx_dev(s);
1975 sbits |= 1 << azx_dev->index;
1976 nsync++;
1977 snd_pcm_trigger_done(s, substream);
1978 }
1979
1980 spin_lock(&chip->reg_lock);
1981 if (nsync > 1) {
1982 /* first, set SYNC bits of corresponding streams */
1983 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1984 azx_writel(chip, OLD_SSYNC,
1985 azx_readl(chip, OLD_SSYNC) | sbits);
1986 else
1987 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1988 }
1989 snd_pcm_group_for_each_entry(s, substream) {
1990 if (s->pcm->card != substream->pcm->card)
1991 continue;
1992 azx_dev = get_azx_dev(s);
1993 if (start) {
1994 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1995 if (!rstart)
1996 azx_dev->start_wallclk -=
1997 azx_dev->period_wallclk;
1998 azx_stream_start(chip, azx_dev);
1999 } else {
2000 azx_stream_stop(chip, azx_dev);
2001 }
2002 azx_dev->running = start;
2003 }
2004 spin_unlock(&chip->reg_lock);
2005 if (start) {
2006 if (nsync == 1)
2007 return 0;
2008 /* wait until all FIFOs get ready */
2009 for (timeout = 5000; timeout; timeout--) {
2010 nwait = 0;
2011 snd_pcm_group_for_each_entry(s, substream) {
2012 if (s->pcm->card != substream->pcm->card)
2013 continue;
2014 azx_dev = get_azx_dev(s);
2015 if (!(azx_sd_readb(azx_dev, SD_STS) &
2016 SD_STS_FIFO_READY))
2017 nwait++;
2018 }
2019 if (!nwait)
2020 break;
2021 cpu_relax();
2022 }
2023 } else {
2024 /* wait until all RUN bits are cleared */
2025 for (timeout = 5000; timeout; timeout--) {
2026 nwait = 0;
2027 snd_pcm_group_for_each_entry(s, substream) {
2028 if (s->pcm->card != substream->pcm->card)
2029 continue;
2030 azx_dev = get_azx_dev(s);
2031 if (azx_sd_readb(azx_dev, SD_CTL) &
2032 SD_CTL_DMA_START)
2033 nwait++;
2034 }
2035 if (!nwait)
2036 break;
2037 cpu_relax();
2038 }
2039 }
2040 if (nsync > 1) {
2041 spin_lock(&chip->reg_lock);
2042 /* reset SYNC bits */
2043 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2044 azx_writel(chip, OLD_SSYNC,
2045 azx_readl(chip, OLD_SSYNC) & ~sbits);
2046 else
2047 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2048 spin_unlock(&chip->reg_lock);
2049 }
2050 return 0;
2051 }
2052
2053 /* get the current DMA position with correction on VIA chips */
2054 static unsigned int azx_via_get_position(struct azx *chip,
2055 struct azx_dev *azx_dev)
2056 {
2057 unsigned int link_pos, mini_pos, bound_pos;
2058 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2059 unsigned int fifo_size;
2060
2061 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2062 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2063 /* Playback, no problem using link position */
2064 return link_pos;
2065 }
2066
2067 /* Capture */
2068 /* For new chipset,
2069 * use mod to get the DMA position just like old chipset
2070 */
2071 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2072 mod_dma_pos %= azx_dev->period_bytes;
2073
2074 /* azx_dev->fifo_size can't get FIFO size of in stream.
2075 * Get from base address + offset.
2076 */
2077 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2078
2079 if (azx_dev->insufficient) {
2080 /* Link position never gather than FIFO size */
2081 if (link_pos <= fifo_size)
2082 return 0;
2083
2084 azx_dev->insufficient = 0;
2085 }
2086
2087 if (link_pos <= fifo_size)
2088 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2089 else
2090 mini_pos = link_pos - fifo_size;
2091
2092 /* Find nearest previous boudary */
2093 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2094 mod_link_pos = link_pos % azx_dev->period_bytes;
2095 if (mod_link_pos >= fifo_size)
2096 bound_pos = link_pos - mod_link_pos;
2097 else if (mod_dma_pos >= mod_mini_pos)
2098 bound_pos = mini_pos - mod_mini_pos;
2099 else {
2100 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2101 if (bound_pos >= azx_dev->bufsize)
2102 bound_pos = 0;
2103 }
2104
2105 /* Calculate real DMA position we want */
2106 return bound_pos + mod_dma_pos;
2107 }
2108
2109 static unsigned int azx_get_position(struct azx *chip,
2110 struct azx_dev *azx_dev,
2111 bool with_check)
2112 {
2113 unsigned int pos;
2114 int stream = azx_dev->substream->stream;
2115
2116 switch (chip->position_fix[stream]) {
2117 case POS_FIX_LPIB:
2118 /* read LPIB */
2119 pos = azx_sd_readl(azx_dev, SD_LPIB);
2120 break;
2121 case POS_FIX_VIACOMBO:
2122 pos = azx_via_get_position(chip, azx_dev);
2123 break;
2124 default:
2125 /* use the position buffer */
2126 pos = le32_to_cpu(*azx_dev->posbuf);
2127 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2128 if (!pos || pos == (u32)-1) {
2129 printk(KERN_WARNING
2130 "hda-intel: Invalid position buffer, "
2131 "using LPIB read method instead.\n");
2132 chip->position_fix[stream] = POS_FIX_LPIB;
2133 pos = azx_sd_readl(azx_dev, SD_LPIB);
2134 } else
2135 chip->position_fix[stream] = POS_FIX_POSBUF;
2136 }
2137 break;
2138 }
2139
2140 if (pos >= azx_dev->bufsize)
2141 pos = 0;
2142 return pos;
2143 }
2144
2145 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2146 {
2147 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2148 struct azx *chip = apcm->chip;
2149 struct azx_dev *azx_dev = get_azx_dev(substream);
2150 return bytes_to_frames(substream->runtime,
2151 azx_get_position(chip, azx_dev, false));
2152 }
2153
2154 /*
2155 * Check whether the current DMA position is acceptable for updating
2156 * periods. Returns non-zero if it's OK.
2157 *
2158 * Many HD-audio controllers appear pretty inaccurate about
2159 * the update-IRQ timing. The IRQ is issued before actually the
2160 * data is processed. So, we need to process it afterwords in a
2161 * workqueue.
2162 */
2163 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2164 {
2165 u32 wallclk;
2166 unsigned int pos;
2167 int stream;
2168
2169 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2170 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2171 return -1; /* bogus (too early) interrupt */
2172
2173 stream = azx_dev->substream->stream;
2174 pos = azx_get_position(chip, azx_dev, true);
2175
2176 if (WARN_ONCE(!azx_dev->period_bytes,
2177 "hda-intel: zero azx_dev->period_bytes"))
2178 return -1; /* this shouldn't happen! */
2179 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2180 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2181 /* NG - it's below the first next period boundary */
2182 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2183 azx_dev->start_wallclk += wallclk;
2184 return 1; /* OK, it's fine */
2185 }
2186
2187 /*
2188 * The work for pending PCM period updates.
2189 */
2190 static void azx_irq_pending_work(struct work_struct *work)
2191 {
2192 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2193 int i, pending, ok;
2194
2195 if (!chip->irq_pending_warned) {
2196 printk(KERN_WARNING
2197 "hda-intel: IRQ timing workaround is activated "
2198 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2199 chip->card->number);
2200 chip->irq_pending_warned = 1;
2201 }
2202
2203 for (;;) {
2204 pending = 0;
2205 spin_lock_irq(&chip->reg_lock);
2206 for (i = 0; i < chip->num_streams; i++) {
2207 struct azx_dev *azx_dev = &chip->azx_dev[i];
2208 if (!azx_dev->irq_pending ||
2209 !azx_dev->substream ||
2210 !azx_dev->running)
2211 continue;
2212 ok = azx_position_ok(chip, azx_dev);
2213 if (ok > 0) {
2214 azx_dev->irq_pending = 0;
2215 spin_unlock(&chip->reg_lock);
2216 snd_pcm_period_elapsed(azx_dev->substream);
2217 spin_lock(&chip->reg_lock);
2218 } else if (ok < 0) {
2219 pending = 0; /* too early */
2220 } else
2221 pending++;
2222 }
2223 spin_unlock_irq(&chip->reg_lock);
2224 if (!pending)
2225 return;
2226 msleep(1);
2227 }
2228 }
2229
2230 /* clear irq_pending flags and assure no on-going workq */
2231 static void azx_clear_irq_pending(struct azx *chip)
2232 {
2233 int i;
2234
2235 spin_lock_irq(&chip->reg_lock);
2236 for (i = 0; i < chip->num_streams; i++)
2237 chip->azx_dev[i].irq_pending = 0;
2238 spin_unlock_irq(&chip->reg_lock);
2239 }
2240
2241 #ifdef CONFIG_X86
2242 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2243 struct vm_area_struct *area)
2244 {
2245 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2246 struct azx *chip = apcm->chip;
2247 if (!azx_snoop(chip))
2248 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2249 return snd_pcm_lib_default_mmap(substream, area);
2250 }
2251 #else
2252 #define azx_pcm_mmap NULL
2253 #endif
2254
2255 static struct snd_pcm_ops azx_pcm_ops = {
2256 .open = azx_pcm_open,
2257 .close = azx_pcm_close,
2258 .ioctl = snd_pcm_lib_ioctl,
2259 .hw_params = azx_pcm_hw_params,
2260 .hw_free = azx_pcm_hw_free,
2261 .prepare = azx_pcm_prepare,
2262 .trigger = azx_pcm_trigger,
2263 .pointer = azx_pcm_pointer,
2264 .mmap = azx_pcm_mmap,
2265 .page = snd_pcm_sgbuf_ops_page,
2266 };
2267
2268 static void azx_pcm_free(struct snd_pcm *pcm)
2269 {
2270 struct azx_pcm *apcm = pcm->private_data;
2271 if (apcm) {
2272 list_del(&apcm->list);
2273 kfree(apcm);
2274 }
2275 }
2276
2277 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2278
2279 static int
2280 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2281 struct hda_pcm *cpcm)
2282 {
2283 struct azx *chip = bus->private_data;
2284 struct snd_pcm *pcm;
2285 struct azx_pcm *apcm;
2286 int pcm_dev = cpcm->device;
2287 unsigned int size;
2288 int s, err;
2289
2290 list_for_each_entry(apcm, &chip->pcm_list, list) {
2291 if (apcm->pcm->device == pcm_dev) {
2292 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2293 return -EBUSY;
2294 }
2295 }
2296 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2297 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2298 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2299 &pcm);
2300 if (err < 0)
2301 return err;
2302 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2303 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2304 if (apcm == NULL)
2305 return -ENOMEM;
2306 apcm->chip = chip;
2307 apcm->pcm = pcm;
2308 apcm->codec = codec;
2309 pcm->private_data = apcm;
2310 pcm->private_free = azx_pcm_free;
2311 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2312 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2313 list_add_tail(&apcm->list, &chip->pcm_list);
2314 cpcm->pcm = pcm;
2315 for (s = 0; s < 2; s++) {
2316 apcm->hinfo[s] = &cpcm->stream[s];
2317 if (cpcm->stream[s].substreams)
2318 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2319 }
2320 /* buffer pre-allocation */
2321 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2322 if (size > MAX_PREALLOC_SIZE)
2323 size = MAX_PREALLOC_SIZE;
2324 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2325 snd_dma_pci_data(chip->pci),
2326 size, MAX_PREALLOC_SIZE);
2327 return 0;
2328 }
2329
2330 /*
2331 * mixer creation - all stuff is implemented in hda module
2332 */
2333 static int __devinit azx_mixer_create(struct azx *chip)
2334 {
2335 return snd_hda_build_controls(chip->bus);
2336 }
2337
2338
2339 /*
2340 * initialize SD streams
2341 */
2342 static int __devinit azx_init_stream(struct azx *chip)
2343 {
2344 int i;
2345
2346 /* initialize each stream (aka device)
2347 * assign the starting bdl address to each stream (device)
2348 * and initialize
2349 */
2350 for (i = 0; i < chip->num_streams; i++) {
2351 struct azx_dev *azx_dev = &chip->azx_dev[i];
2352 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2353 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2354 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2355 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2356 azx_dev->sd_int_sta_mask = 1 << i;
2357 /* stream tag: must be non-zero and unique */
2358 azx_dev->index = i;
2359 azx_dev->stream_tag = i + 1;
2360 }
2361
2362 return 0;
2363 }
2364
2365 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2366 {
2367 if (request_irq(chip->pci->irq, azx_interrupt,
2368 chip->msi ? 0 : IRQF_SHARED,
2369 KBUILD_MODNAME, chip)) {
2370 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2371 "disabling device\n", chip->pci->irq);
2372 if (do_disconnect)
2373 snd_card_disconnect(chip->card);
2374 return -1;
2375 }
2376 chip->irq = chip->pci->irq;
2377 pci_intx(chip->pci, !chip->msi);
2378 return 0;
2379 }
2380
2381
2382 static void azx_stop_chip(struct azx *chip)
2383 {
2384 if (!chip->initialized)
2385 return;
2386
2387 /* disable interrupts */
2388 azx_int_disable(chip);
2389 azx_int_clear(chip);
2390
2391 /* disable CORB/RIRB */
2392 azx_free_cmd_io(chip);
2393
2394 /* disable position buffer */
2395 azx_writel(chip, DPLBASE, 0);
2396 azx_writel(chip, DPUBASE, 0);
2397
2398 chip->initialized = 0;
2399 }
2400
2401 #ifdef CONFIG_SND_HDA_POWER_SAVE
2402 /* power-up/down the controller */
2403 static void azx_power_notify(struct hda_bus *bus)
2404 {
2405 struct azx *chip = bus->private_data;
2406 struct hda_codec *c;
2407 int power_on = 0;
2408
2409 list_for_each_entry(c, &bus->codec_list, list) {
2410 if (c->power_on) {
2411 power_on = 1;
2412 break;
2413 }
2414 }
2415 if (power_on)
2416 azx_init_chip(chip, 1);
2417 else if (chip->running && power_save_controller &&
2418 !bus->power_keep_link_on)
2419 azx_stop_chip(chip);
2420 }
2421
2422 static DEFINE_MUTEX(card_list_lock);
2423 static LIST_HEAD(card_list);
2424
2425 static void azx_add_card_list(struct azx *chip)
2426 {
2427 mutex_lock(&card_list_lock);
2428 list_add(&chip->list, &card_list);
2429 mutex_unlock(&card_list_lock);
2430 }
2431
2432 static void azx_del_card_list(struct azx *chip)
2433 {
2434 mutex_lock(&card_list_lock);
2435 list_del_init(&chip->list);
2436 mutex_unlock(&card_list_lock);
2437 }
2438
2439 /* trigger power-save check at writing parameter */
2440 static int param_set_xint(const char *val, const struct kernel_param *kp)
2441 {
2442 struct azx *chip;
2443 struct hda_codec *c;
2444 int prev = power_save;
2445 int ret = param_set_int(val, kp);
2446
2447 if (ret || prev == power_save)
2448 return ret;
2449
2450 mutex_lock(&card_list_lock);
2451 list_for_each_entry(chip, &card_list, list) {
2452 if (!chip->bus || chip->disabled)
2453 continue;
2454 list_for_each_entry(c, &chip->bus->codec_list, list)
2455 snd_hda_power_sync(c);
2456 }
2457 mutex_unlock(&card_list_lock);
2458 return 0;
2459 }
2460 #else
2461 #define azx_add_card_list(chip) /* NOP */
2462 #define azx_del_card_list(chip) /* NOP */
2463 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2464
2465 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2466 /*
2467 * power management
2468 */
2469 static int azx_suspend(struct device *dev)
2470 {
2471 struct pci_dev *pci = to_pci_dev(dev);
2472 struct snd_card *card = dev_get_drvdata(dev);
2473 struct azx *chip = card->private_data;
2474 struct azx_pcm *p;
2475
2476 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2477 azx_clear_irq_pending(chip);
2478 list_for_each_entry(p, &chip->pcm_list, list)
2479 snd_pcm_suspend_all(p->pcm);
2480 if (chip->initialized)
2481 snd_hda_suspend(chip->bus);
2482 azx_stop_chip(chip);
2483 if (chip->irq >= 0) {
2484 free_irq(chip->irq, chip);
2485 chip->irq = -1;
2486 }
2487 if (chip->msi)
2488 pci_disable_msi(chip->pci);
2489 pci_disable_device(pci);
2490 pci_save_state(pci);
2491 pci_set_power_state(pci, PCI_D3hot);
2492 return 0;
2493 }
2494
2495 static int azx_resume(struct device *dev)
2496 {
2497 struct pci_dev *pci = to_pci_dev(dev);
2498 struct snd_card *card = dev_get_drvdata(dev);
2499 struct azx *chip = card->private_data;
2500
2501 pci_set_power_state(pci, PCI_D0);
2502 pci_restore_state(pci);
2503 if (pci_enable_device(pci) < 0) {
2504 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2505 "disabling device\n");
2506 snd_card_disconnect(card);
2507 return -EIO;
2508 }
2509 pci_set_master(pci);
2510 if (chip->msi)
2511 if (pci_enable_msi(pci) < 0)
2512 chip->msi = 0;
2513 if (azx_acquire_irq(chip, 1) < 0)
2514 return -EIO;
2515 azx_init_pci(chip);
2516
2517 azx_init_chip(chip, 1);
2518
2519 snd_hda_resume(chip->bus);
2520 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2521 return 0;
2522 }
2523 static SIMPLE_DEV_PM_OPS(azx_pm, azx_suspend, azx_resume);
2524 #define AZX_PM_OPS &azx_pm
2525 #else
2526 #define AZX_PM_OPS NULL
2527 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2528
2529
2530 /*
2531 * reboot notifier for hang-up problem at power-down
2532 */
2533 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2534 {
2535 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2536 snd_hda_bus_reboot_notify(chip->bus);
2537 azx_stop_chip(chip);
2538 return NOTIFY_OK;
2539 }
2540
2541 static void azx_notifier_register(struct azx *chip)
2542 {
2543 chip->reboot_notifier.notifier_call = azx_halt;
2544 register_reboot_notifier(&chip->reboot_notifier);
2545 }
2546
2547 static void azx_notifier_unregister(struct azx *chip)
2548 {
2549 if (chip->reboot_notifier.notifier_call)
2550 unregister_reboot_notifier(&chip->reboot_notifier);
2551 }
2552
2553 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip);
2554 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip);
2555
2556 #ifdef SUPPORT_VGA_SWITCHEROO
2557 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci);
2558
2559 static void azx_vs_set_state(struct pci_dev *pci,
2560 enum vga_switcheroo_state state)
2561 {
2562 struct snd_card *card = pci_get_drvdata(pci);
2563 struct azx *chip = card->private_data;
2564 bool disabled;
2565
2566 if (chip->init_failed)
2567 return;
2568
2569 disabled = (state == VGA_SWITCHEROO_OFF);
2570 if (chip->disabled == disabled)
2571 return;
2572
2573 if (!chip->bus) {
2574 chip->disabled = disabled;
2575 if (!disabled) {
2576 snd_printk(KERN_INFO SFX
2577 "%s: Start delayed initialization\n",
2578 pci_name(chip->pci));
2579 if (azx_first_init(chip) < 0 ||
2580 azx_probe_continue(chip) < 0) {
2581 snd_printk(KERN_ERR SFX
2582 "%s: initialization error\n",
2583 pci_name(chip->pci));
2584 chip->init_failed = true;
2585 }
2586 }
2587 } else {
2588 snd_printk(KERN_INFO SFX
2589 "%s %s via VGA-switcheroo\n",
2590 disabled ? "Disabling" : "Enabling",
2591 pci_name(chip->pci));
2592 if (disabled) {
2593 azx_suspend(&pci->dev);
2594 chip->disabled = true;
2595 snd_hda_lock_devices(chip->bus);
2596 } else {
2597 snd_hda_unlock_devices(chip->bus);
2598 chip->disabled = false;
2599 azx_resume(&pci->dev);
2600 }
2601 }
2602 }
2603
2604 static bool azx_vs_can_switch(struct pci_dev *pci)
2605 {
2606 struct snd_card *card = pci_get_drvdata(pci);
2607 struct azx *chip = card->private_data;
2608
2609 if (chip->init_failed)
2610 return false;
2611 if (chip->disabled || !chip->bus)
2612 return true;
2613 if (snd_hda_lock_devices(chip->bus))
2614 return false;
2615 snd_hda_unlock_devices(chip->bus);
2616 return true;
2617 }
2618
2619 static void __devinit init_vga_switcheroo(struct azx *chip)
2620 {
2621 struct pci_dev *p = get_bound_vga(chip->pci);
2622 if (p) {
2623 snd_printk(KERN_INFO SFX
2624 "%s: Handle VGA-switcheroo audio client\n",
2625 pci_name(chip->pci));
2626 chip->use_vga_switcheroo = 1;
2627 pci_dev_put(p);
2628 }
2629 }
2630
2631 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2632 .set_gpu_state = azx_vs_set_state,
2633 .can_switch = azx_vs_can_switch,
2634 };
2635
2636 static int __devinit register_vga_switcheroo(struct azx *chip)
2637 {
2638 if (!chip->use_vga_switcheroo)
2639 return 0;
2640 /* FIXME: currently only handling DIS controller
2641 * is there any machine with two switchable HDMI audio controllers?
2642 */
2643 return vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2644 VGA_SWITCHEROO_DIS,
2645 chip->bus != NULL);
2646 }
2647 #else
2648 #define init_vga_switcheroo(chip) /* NOP */
2649 #define register_vga_switcheroo(chip) 0
2650 #define check_hdmi_disabled(pci) false
2651 #endif /* SUPPORT_VGA_SWITCHER */
2652
2653 /*
2654 * destructor
2655 */
2656 static int azx_free(struct azx *chip)
2657 {
2658 int i;
2659
2660 azx_del_card_list(chip);
2661
2662 azx_notifier_unregister(chip);
2663
2664 if (use_vga_switcheroo(chip)) {
2665 if (chip->disabled && chip->bus)
2666 snd_hda_unlock_devices(chip->bus);
2667 vga_switcheroo_unregister_client(chip->pci);
2668 }
2669
2670 if (chip->initialized) {
2671 azx_clear_irq_pending(chip);
2672 for (i = 0; i < chip->num_streams; i++)
2673 azx_stream_stop(chip, &chip->azx_dev[i]);
2674 azx_stop_chip(chip);
2675 }
2676
2677 if (chip->irq >= 0)
2678 free_irq(chip->irq, (void*)chip);
2679 if (chip->msi)
2680 pci_disable_msi(chip->pci);
2681 if (chip->remap_addr)
2682 iounmap(chip->remap_addr);
2683
2684 if (chip->azx_dev) {
2685 for (i = 0; i < chip->num_streams; i++)
2686 if (chip->azx_dev[i].bdl.area) {
2687 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2688 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2689 }
2690 }
2691 if (chip->rb.area) {
2692 mark_pages_wc(chip, &chip->rb, false);
2693 snd_dma_free_pages(&chip->rb);
2694 }
2695 if (chip->posbuf.area) {
2696 mark_pages_wc(chip, &chip->posbuf, false);
2697 snd_dma_free_pages(&chip->posbuf);
2698 }
2699 if (chip->region_requested)
2700 pci_release_regions(chip->pci);
2701 pci_disable_device(chip->pci);
2702 kfree(chip->azx_dev);
2703 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2704 if (chip->fw)
2705 release_firmware(chip->fw);
2706 #endif
2707 kfree(chip);
2708
2709 return 0;
2710 }
2711
2712 static int azx_dev_free(struct snd_device *device)
2713 {
2714 return azx_free(device->device_data);
2715 }
2716
2717 #ifdef SUPPORT_VGA_SWITCHEROO
2718 /*
2719 * Check of disabled HDMI controller by vga-switcheroo
2720 */
2721 static struct pci_dev __devinit *get_bound_vga(struct pci_dev *pci)
2722 {
2723 struct pci_dev *p;
2724
2725 /* check only discrete GPU */
2726 switch (pci->vendor) {
2727 case PCI_VENDOR_ID_ATI:
2728 case PCI_VENDOR_ID_AMD:
2729 case PCI_VENDOR_ID_NVIDIA:
2730 if (pci->devfn == 1) {
2731 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2732 pci->bus->number, 0);
2733 if (p) {
2734 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2735 return p;
2736 pci_dev_put(p);
2737 }
2738 }
2739 break;
2740 }
2741 return NULL;
2742 }
2743
2744 static bool __devinit check_hdmi_disabled(struct pci_dev *pci)
2745 {
2746 bool vga_inactive = false;
2747 struct pci_dev *p = get_bound_vga(pci);
2748
2749 if (p) {
2750 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2751 vga_inactive = true;
2752 pci_dev_put(p);
2753 }
2754 return vga_inactive;
2755 }
2756 #endif /* SUPPORT_VGA_SWITCHEROO */
2757
2758 /*
2759 * white/black-listing for position_fix
2760 */
2761 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2762 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2763 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2764 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2765 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2766 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2767 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2768 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2769 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2770 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2771 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2772 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2773 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2774 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2775 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2776 {}
2777 };
2778
2779 static int __devinit check_position_fix(struct azx *chip, int fix)
2780 {
2781 const struct snd_pci_quirk *q;
2782
2783 switch (fix) {
2784 case POS_FIX_LPIB:
2785 case POS_FIX_POSBUF:
2786 case POS_FIX_VIACOMBO:
2787 case POS_FIX_COMBO:
2788 return fix;
2789 }
2790
2791 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2792 if (q) {
2793 printk(KERN_INFO
2794 "hda_intel: position_fix set to %d "
2795 "for device %04x:%04x\n",
2796 q->value, q->subvendor, q->subdevice);
2797 return q->value;
2798 }
2799
2800 /* Check VIA/ATI HD Audio Controller exist */
2801 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2802 snd_printd(SFX "Using VIACOMBO position fix\n");
2803 return POS_FIX_VIACOMBO;
2804 }
2805 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2806 snd_printd(SFX "Using LPIB position fix\n");
2807 return POS_FIX_LPIB;
2808 }
2809 if (chip->driver_caps & AZX_DCAPS_POSFIX_COMBO) {
2810 snd_printd(SFX "Using COMBO position fix\n");
2811 return POS_FIX_COMBO;
2812 }
2813 return POS_FIX_AUTO;
2814 }
2815
2816 /*
2817 * black-lists for probe_mask
2818 */
2819 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2820 /* Thinkpad often breaks the controller communication when accessing
2821 * to the non-working (or non-existing) modem codec slot.
2822 */
2823 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2824 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2825 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2826 /* broken BIOS */
2827 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2828 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2829 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2830 /* forced codec slots */
2831 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2832 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2833 /* WinFast VP200 H (Teradici) user reported broken communication */
2834 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
2835 {}
2836 };
2837
2838 #define AZX_FORCE_CODEC_MASK 0x100
2839
2840 static void __devinit check_probe_mask(struct azx *chip, int dev)
2841 {
2842 const struct snd_pci_quirk *q;
2843
2844 chip->codec_probe_mask = probe_mask[dev];
2845 if (chip->codec_probe_mask == -1) {
2846 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2847 if (q) {
2848 printk(KERN_INFO
2849 "hda_intel: probe_mask set to 0x%x "
2850 "for device %04x:%04x\n",
2851 q->value, q->subvendor, q->subdevice);
2852 chip->codec_probe_mask = q->value;
2853 }
2854 }
2855
2856 /* check forced option */
2857 if (chip->codec_probe_mask != -1 &&
2858 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2859 chip->codec_mask = chip->codec_probe_mask & 0xff;
2860 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2861 chip->codec_mask);
2862 }
2863 }
2864
2865 /*
2866 * white/black-list for enable_msi
2867 */
2868 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2869 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2870 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2871 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2872 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2873 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2874 {}
2875 };
2876
2877 static void __devinit check_msi(struct azx *chip)
2878 {
2879 const struct snd_pci_quirk *q;
2880
2881 if (enable_msi >= 0) {
2882 chip->msi = !!enable_msi;
2883 return;
2884 }
2885 chip->msi = 1; /* enable MSI as default */
2886 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2887 if (q) {
2888 printk(KERN_INFO
2889 "hda_intel: msi for device %04x:%04x set to %d\n",
2890 q->subvendor, q->subdevice, q->value);
2891 chip->msi = q->value;
2892 return;
2893 }
2894
2895 /* NVidia chipsets seem to cause troubles with MSI */
2896 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2897 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2898 chip->msi = 0;
2899 }
2900 }
2901
2902 /* check the snoop mode availability */
2903 static void __devinit azx_check_snoop_available(struct azx *chip)
2904 {
2905 bool snoop = chip->snoop;
2906
2907 switch (chip->driver_type) {
2908 case AZX_DRIVER_VIA:
2909 /* force to non-snoop mode for a new VIA controller
2910 * when BIOS is set
2911 */
2912 if (snoop) {
2913 u8 val;
2914 pci_read_config_byte(chip->pci, 0x42, &val);
2915 if (!(val & 0x80) && chip->pci->revision == 0x30)
2916 snoop = false;
2917 }
2918 break;
2919 case AZX_DRIVER_ATIHDMI_NS:
2920 /* new ATI HDMI requires non-snoop */
2921 snoop = false;
2922 break;
2923 }
2924
2925 if (snoop != chip->snoop) {
2926 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2927 snoop ? "snoop" : "non-snoop");
2928 chip->snoop = snoop;
2929 }
2930 }
2931
2932 /*
2933 * constructor
2934 */
2935 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2936 int dev, unsigned int driver_caps,
2937 struct azx **rchip)
2938 {
2939 static struct snd_device_ops ops = {
2940 .dev_free = azx_dev_free,
2941 };
2942 struct azx *chip;
2943 int err;
2944
2945 *rchip = NULL;
2946
2947 err = pci_enable_device(pci);
2948 if (err < 0)
2949 return err;
2950
2951 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2952 if (!chip) {
2953 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2954 pci_disable_device(pci);
2955 return -ENOMEM;
2956 }
2957
2958 spin_lock_init(&chip->reg_lock);
2959 mutex_init(&chip->open_mutex);
2960 chip->card = card;
2961 chip->pci = pci;
2962 chip->irq = -1;
2963 chip->driver_caps = driver_caps;
2964 chip->driver_type = driver_caps & 0xff;
2965 check_msi(chip);
2966 chip->dev_index = dev;
2967 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2968 INIT_LIST_HEAD(&chip->pcm_list);
2969 INIT_LIST_HEAD(&chip->list);
2970 init_vga_switcheroo(chip);
2971
2972 chip->position_fix[0] = chip->position_fix[1] =
2973 check_position_fix(chip, position_fix[dev]);
2974 /* combo mode uses LPIB for playback */
2975 if (chip->position_fix[0] == POS_FIX_COMBO) {
2976 chip->position_fix[0] = POS_FIX_LPIB;
2977 chip->position_fix[1] = POS_FIX_AUTO;
2978 }
2979
2980 check_probe_mask(chip, dev);
2981
2982 chip->single_cmd = single_cmd;
2983 chip->snoop = hda_snoop;
2984 azx_check_snoop_available(chip);
2985
2986 if (bdl_pos_adj[dev] < 0) {
2987 switch (chip->driver_type) {
2988 case AZX_DRIVER_ICH:
2989 case AZX_DRIVER_PCH:
2990 bdl_pos_adj[dev] = 1;
2991 break;
2992 default:
2993 bdl_pos_adj[dev] = 32;
2994 break;
2995 }
2996 }
2997
2998 if (check_hdmi_disabled(pci)) {
2999 snd_printk(KERN_INFO SFX "VGA controller for %s is disabled\n",
3000 pci_name(pci));
3001 if (use_vga_switcheroo(chip)) {
3002 snd_printk(KERN_INFO SFX "Delaying initialization\n");
3003 chip->disabled = true;
3004 goto ok;
3005 }
3006 kfree(chip);
3007 pci_disable_device(pci);
3008 return -ENXIO;
3009 }
3010
3011 err = azx_first_init(chip);
3012 if (err < 0) {
3013 azx_free(chip);
3014 return err;
3015 }
3016
3017 ok:
3018 err = register_vga_switcheroo(chip);
3019 if (err < 0) {
3020 snd_printk(KERN_ERR SFX
3021 "Error registering VGA-switcheroo client\n");
3022 azx_free(chip);
3023 return err;
3024 }
3025
3026 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3027 if (err < 0) {
3028 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
3029 azx_free(chip);
3030 return err;
3031 }
3032
3033 *rchip = chip;
3034 return 0;
3035 }
3036
3037 static int DELAYED_INIT_MARK azx_first_init(struct azx *chip)
3038 {
3039 int dev = chip->dev_index;
3040 struct pci_dev *pci = chip->pci;
3041 struct snd_card *card = chip->card;
3042 int i, err;
3043 unsigned short gcap;
3044
3045 #if BITS_PER_LONG != 64
3046 /* Fix up base address on ULI M5461 */
3047 if (chip->driver_type == AZX_DRIVER_ULI) {
3048 u16 tmp3;
3049 pci_read_config_word(pci, 0x40, &tmp3);
3050 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3051 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3052 }
3053 #endif
3054
3055 err = pci_request_regions(pci, "ICH HD audio");
3056 if (err < 0)
3057 return err;
3058 chip->region_requested = 1;
3059
3060 chip->addr = pci_resource_start(pci, 0);
3061 chip->remap_addr = pci_ioremap_bar(pci, 0);
3062 if (chip->remap_addr == NULL) {
3063 snd_printk(KERN_ERR SFX "ioremap error\n");
3064 return -ENXIO;
3065 }
3066
3067 if (chip->msi)
3068 if (pci_enable_msi(pci) < 0)
3069 chip->msi = 0;
3070
3071 if (azx_acquire_irq(chip, 0) < 0)
3072 return -EBUSY;
3073
3074 pci_set_master(pci);
3075 synchronize_irq(chip->irq);
3076
3077 gcap = azx_readw(chip, GCAP);
3078 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
3079
3080 /* disable SB600 64bit support for safety */
3081 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3082 struct pci_dev *p_smbus;
3083 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3084 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3085 NULL);
3086 if (p_smbus) {
3087 if (p_smbus->revision < 0x30)
3088 gcap &= ~ICH6_GCAP_64OK;
3089 pci_dev_put(p_smbus);
3090 }
3091 }
3092
3093 /* disable 64bit DMA address on some devices */
3094 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3095 snd_printd(SFX "Disabling 64bit DMA\n");
3096 gcap &= ~ICH6_GCAP_64OK;
3097 }
3098
3099 /* disable buffer size rounding to 128-byte multiples if supported */
3100 if (align_buffer_size >= 0)
3101 chip->align_buffer_size = !!align_buffer_size;
3102 else {
3103 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3104 chip->align_buffer_size = 0;
3105 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3106 chip->align_buffer_size = 1;
3107 else
3108 chip->align_buffer_size = 1;
3109 }
3110
3111 /* allow 64bit DMA address if supported by H/W */
3112 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3113 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3114 else {
3115 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3116 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3117 }
3118
3119 /* read number of streams from GCAP register instead of using
3120 * hardcoded value
3121 */
3122 chip->capture_streams = (gcap >> 8) & 0x0f;
3123 chip->playback_streams = (gcap >> 12) & 0x0f;
3124 if (!chip->playback_streams && !chip->capture_streams) {
3125 /* gcap didn't give any info, switching to old method */
3126
3127 switch (chip->driver_type) {
3128 case AZX_DRIVER_ULI:
3129 chip->playback_streams = ULI_NUM_PLAYBACK;
3130 chip->capture_streams = ULI_NUM_CAPTURE;
3131 break;
3132 case AZX_DRIVER_ATIHDMI:
3133 case AZX_DRIVER_ATIHDMI_NS:
3134 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3135 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3136 break;
3137 case AZX_DRIVER_GENERIC:
3138 default:
3139 chip->playback_streams = ICH6_NUM_PLAYBACK;
3140 chip->capture_streams = ICH6_NUM_CAPTURE;
3141 break;
3142 }
3143 }
3144 chip->capture_index_offset = 0;
3145 chip->playback_index_offset = chip->capture_streams;
3146 chip->num_streams = chip->playback_streams + chip->capture_streams;
3147 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3148 GFP_KERNEL);
3149 if (!chip->azx_dev) {
3150 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
3151 return -ENOMEM;
3152 }
3153
3154 for (i = 0; i < chip->num_streams; i++) {
3155 /* allocate memory for the BDL for each stream */
3156 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3157 snd_dma_pci_data(chip->pci),
3158 BDL_SIZE, &chip->azx_dev[i].bdl);
3159 if (err < 0) {
3160 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
3161 return -ENOMEM;
3162 }
3163 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3164 }
3165 /* allocate memory for the position buffer */
3166 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3167 snd_dma_pci_data(chip->pci),
3168 chip->num_streams * 8, &chip->posbuf);
3169 if (err < 0) {
3170 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
3171 return -ENOMEM;
3172 }
3173 mark_pages_wc(chip, &chip->posbuf, true);
3174 /* allocate CORB/RIRB */
3175 err = azx_alloc_cmd_io(chip);
3176 if (err < 0)
3177 return err;
3178
3179 /* initialize streams */
3180 azx_init_stream(chip);
3181
3182 /* initialize chip */
3183 azx_init_pci(chip);
3184 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3185
3186 /* codec detection */
3187 if (!chip->codec_mask) {
3188 snd_printk(KERN_ERR SFX "no codecs found!\n");
3189 return -ENODEV;
3190 }
3191
3192 strcpy(card->driver, "HDA-Intel");
3193 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3194 sizeof(card->shortname));
3195 snprintf(card->longname, sizeof(card->longname),
3196 "%s at 0x%lx irq %i",
3197 card->shortname, chip->addr, chip->irq);
3198
3199 return 0;
3200 }
3201
3202 static void power_down_all_codecs(struct azx *chip)
3203 {
3204 #ifdef CONFIG_SND_HDA_POWER_SAVE
3205 /* The codecs were powered up in snd_hda_codec_new().
3206 * Now all initialization done, so turn them down if possible
3207 */
3208 struct hda_codec *codec;
3209 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3210 snd_hda_power_down(codec);
3211 }
3212 #endif
3213 }
3214
3215 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3216 /* callback from request_firmware_nowait() */
3217 static void azx_firmware_cb(const struct firmware *fw, void *context)
3218 {
3219 struct snd_card *card = context;
3220 struct azx *chip = card->private_data;
3221 struct pci_dev *pci = chip->pci;
3222
3223 if (!fw) {
3224 snd_printk(KERN_ERR SFX "Cannot load firmware, aborting\n");
3225 goto error;
3226 }
3227
3228 chip->fw = fw;
3229 if (!chip->disabled) {
3230 /* continue probing */
3231 if (azx_probe_continue(chip))
3232 goto error;
3233 }
3234 return; /* OK */
3235
3236 error:
3237 snd_card_free(card);
3238 pci_set_drvdata(pci, NULL);
3239 }
3240 #endif
3241
3242 static int __devinit azx_probe(struct pci_dev *pci,
3243 const struct pci_device_id *pci_id)
3244 {
3245 static int dev;
3246 struct snd_card *card;
3247 struct azx *chip;
3248 bool probe_now;
3249 int err;
3250
3251 if (dev >= SNDRV_CARDS)
3252 return -ENODEV;
3253 if (!enable[dev]) {
3254 dev++;
3255 return -ENOENT;
3256 }
3257
3258 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3259 if (err < 0) {
3260 snd_printk(KERN_ERR SFX "Error creating card!\n");
3261 return err;
3262 }
3263
3264 snd_card_set_dev(card, &pci->dev);
3265
3266 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3267 if (err < 0)
3268 goto out_free;
3269 card->private_data = chip;
3270 probe_now = !chip->disabled;
3271
3272 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3273 if (patch[dev] && *patch[dev]) {
3274 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
3275 patch[dev]);
3276 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3277 &pci->dev, GFP_KERNEL, card,
3278 azx_firmware_cb);
3279 if (err < 0)
3280 goto out_free;
3281 probe_now = false; /* continued in azx_firmware_cb() */
3282 }
3283 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3284
3285 if (probe_now) {
3286 err = azx_probe_continue(chip);
3287 if (err < 0)
3288 goto out_free;
3289 }
3290
3291 pci_set_drvdata(pci, card);
3292
3293 dev++;
3294 return 0;
3295
3296 out_free:
3297 snd_card_free(card);
3298 return err;
3299 }
3300
3301 static int DELAYED_INIT_MARK azx_probe_continue(struct azx *chip)
3302 {
3303 int dev = chip->dev_index;
3304 int err;
3305
3306 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3307 chip->beep_mode = beep_mode[dev];
3308 #endif
3309
3310 /* create codec instances */
3311 err = azx_codec_create(chip, model[dev]);
3312 if (err < 0)
3313 goto out_free;
3314 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3315 if (chip->fw) {
3316 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3317 chip->fw->data);
3318 if (err < 0)
3319 goto out_free;
3320 release_firmware(chip->fw); /* no longer needed */
3321 chip->fw = NULL;
3322 }
3323 #endif
3324 if ((probe_only[dev] & 1) == 0) {
3325 err = azx_codec_configure(chip);
3326 if (err < 0)
3327 goto out_free;
3328 }
3329
3330 /* create PCM streams */
3331 err = snd_hda_build_pcms(chip->bus);
3332 if (err < 0)
3333 goto out_free;
3334
3335 /* create mixer controls */
3336 err = azx_mixer_create(chip);
3337 if (err < 0)
3338 goto out_free;
3339
3340 err = snd_card_register(chip->card);
3341 if (err < 0)
3342 goto out_free;
3343
3344 chip->running = 1;
3345 power_down_all_codecs(chip);
3346 azx_notifier_register(chip);
3347 azx_add_card_list(chip);
3348
3349 return 0;
3350
3351 out_free:
3352 chip->init_failed = 1;
3353 return err;
3354 }
3355
3356 static void __devexit azx_remove(struct pci_dev *pci)
3357 {
3358 struct snd_card *card = pci_get_drvdata(pci);
3359 if (card)
3360 snd_card_free(card);
3361 pci_set_drvdata(pci, NULL);
3362 }
3363
3364 /* PCI IDs */
3365 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3366 /* CPT */
3367 { PCI_DEVICE(0x8086, 0x1c20),
3368 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3369 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3370 /* PBG */
3371 { PCI_DEVICE(0x8086, 0x1d20),
3372 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3373 AZX_DCAPS_BUFSIZE},
3374 /* Panther Point */
3375 { PCI_DEVICE(0x8086, 0x1e20),
3376 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3377 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3378 /* Lynx Point */
3379 { PCI_DEVICE(0x8086, 0x8c20),
3380 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3381 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3382 /* Lynx Point-LP */
3383 { PCI_DEVICE(0x8086, 0x9c20),
3384 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3385 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3386 /* Lynx Point-LP */
3387 { PCI_DEVICE(0x8086, 0x9c21),
3388 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
3389 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3390 /* Haswell */
3391 { PCI_DEVICE(0x8086, 0x0c0c),
3392 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3393 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_COMBO },
3394 /* SCH */
3395 { PCI_DEVICE(0x8086, 0x811b),
3396 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3397 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3398 { PCI_DEVICE(0x8086, 0x080a),
3399 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3400 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3401 /* ICH */
3402 { PCI_DEVICE(0x8086, 0x2668),
3403 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3404 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3405 { PCI_DEVICE(0x8086, 0x27d8),
3406 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3407 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3408 { PCI_DEVICE(0x8086, 0x269a),
3409 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3410 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3411 { PCI_DEVICE(0x8086, 0x284b),
3412 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3413 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3414 { PCI_DEVICE(0x8086, 0x293e),
3415 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3416 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3417 { PCI_DEVICE(0x8086, 0x293f),
3418 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3419 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3420 { PCI_DEVICE(0x8086, 0x3a3e),
3421 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3422 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3423 { PCI_DEVICE(0x8086, 0x3a6e),
3424 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3425 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3426 /* Generic Intel */
3427 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3428 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3429 .class_mask = 0xffffff,
3430 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3431 /* ATI SB 450/600/700/800/900 */
3432 { PCI_DEVICE(0x1002, 0x437b),
3433 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3434 { PCI_DEVICE(0x1002, 0x4383),
3435 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3436 /* AMD Hudson */
3437 { PCI_DEVICE(0x1022, 0x780d),
3438 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3439 /* ATI HDMI */
3440 { PCI_DEVICE(0x1002, 0x793b),
3441 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3442 { PCI_DEVICE(0x1002, 0x7919),
3443 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3444 { PCI_DEVICE(0x1002, 0x960f),
3445 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3446 { PCI_DEVICE(0x1002, 0x970f),
3447 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3448 { PCI_DEVICE(0x1002, 0xaa00),
3449 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3450 { PCI_DEVICE(0x1002, 0xaa08),
3451 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3452 { PCI_DEVICE(0x1002, 0xaa10),
3453 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3454 { PCI_DEVICE(0x1002, 0xaa18),
3455 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3456 { PCI_DEVICE(0x1002, 0xaa20),
3457 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3458 { PCI_DEVICE(0x1002, 0xaa28),
3459 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3460 { PCI_DEVICE(0x1002, 0xaa30),
3461 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3462 { PCI_DEVICE(0x1002, 0xaa38),
3463 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3464 { PCI_DEVICE(0x1002, 0xaa40),
3465 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3466 { PCI_DEVICE(0x1002, 0xaa48),
3467 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3468 { PCI_DEVICE(0x1002, 0x9902),
3469 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3470 { PCI_DEVICE(0x1002, 0xaaa0),
3471 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3472 { PCI_DEVICE(0x1002, 0xaaa8),
3473 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3474 { PCI_DEVICE(0x1002, 0xaab0),
3475 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3476 /* VIA VT8251/VT8237A */
3477 { PCI_DEVICE(0x1106, 0x3288),
3478 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3479 /* VIA GFX VT7122/VX900 */
3480 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3481 /* VIA GFX VT6122/VX11 */
3482 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3483 /* SIS966 */
3484 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3485 /* ULI M5461 */
3486 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3487 /* NVIDIA MCP */
3488 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3489 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3490 .class_mask = 0xffffff,
3491 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3492 /* Teradici */
3493 { PCI_DEVICE(0x6549, 0x1200),
3494 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3495 /* Creative X-Fi (CA0110-IBG) */
3496 /* CTHDA chips */
3497 { PCI_DEVICE(0x1102, 0x0010),
3498 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3499 { PCI_DEVICE(0x1102, 0x0012),
3500 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3501 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3502 /* the following entry conflicts with snd-ctxfi driver,
3503 * as ctxfi driver mutates from HD-audio to native mode with
3504 * a special command sequence.
3505 */
3506 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3507 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3508 .class_mask = 0xffffff,
3509 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3510 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3511 #else
3512 /* this entry seems still valid -- i.e. without emu20kx chip */
3513 { PCI_DEVICE(0x1102, 0x0009),
3514 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3515 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3516 #endif
3517 /* Vortex86MX */
3518 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3519 /* VMware HDAudio */
3520 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3521 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3522 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3523 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3524 .class_mask = 0xffffff,
3525 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3526 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3527 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3528 .class_mask = 0xffffff,
3529 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3530 { 0, }
3531 };
3532 MODULE_DEVICE_TABLE(pci, azx_ids);
3533
3534 /* pci_driver definition */
3535 static struct pci_driver azx_driver = {
3536 .name = KBUILD_MODNAME,
3537 .id_table = azx_ids,
3538 .probe = azx_probe,
3539 .remove = __devexit_p(azx_remove),
3540 .driver = {
3541 .pm = AZX_PM_OPS,
3542 },
3543 };
3544
3545 module_pci_driver(azx_driver);
Linux kernel - Deliverables
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