sound/pci/hda/hda_priv.h

   1 /*
   2  *  Common defines for the alsa driver code base for HD Audio.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify it
   5  *  under the terms of the GNU General Public License as published by the Free
   6  *  Software Foundation; either version 2 of the License, or (at your option)
   7  *  any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful, but WITHOUT
  10  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  *  more details.
  13  */
  14
  15 #ifndef __SOUND_HDA_PRIV_H
  16 #define __SOUND_HDA_PRIV_H
  17
  18 #include <linux/clocksource.h>
  19 #include <sound/core.h>
  20 #include <sound/pcm.h>
  21
  22 /*
  23  * registers
  24  */
  25 #define ICH6_REG_GCAP                   0x00
  26 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
  27 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
  28 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
  29 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
  30 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
  31 #define ICH6_REG_VMIN                   0x02
  32 #define ICH6_REG_VMAJ                   0x03
  33 #define ICH6_REG_OUTPAY                 0x04
  34 #define ICH6_REG_INPAY                  0x06
  35 #define ICH6_REG_GCTL                   0x08
  36 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
  37 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
  38 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
  39 #define ICH6_REG_WAKEEN                 0x0c
  40 #define ICH6_REG_STATESTS               0x0e
  41 #define ICH6_REG_GSTS                   0x10
  42 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
  43 #define ICH6_REG_INTCTL                 0x20
  44 #define ICH6_REG_INTSTS                 0x24
  45 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
  46 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
  47 #define ICH6_REG_SSYNC                  0x38
  48 #define ICH6_REG_CORBLBASE              0x40
  49 #define ICH6_REG_CORBUBASE              0x44
  50 #define ICH6_REG_CORBWP                 0x48
  51 #define ICH6_REG_CORBRP                 0x4a
  52 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
  53 #define ICH6_REG_CORBCTL                0x4c
  54 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
  55 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
  56 #define ICH6_REG_CORBSTS                0x4d
  57 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
  58 #define ICH6_REG_CORBSIZE               0x4e
  59
  60 #define ICH6_REG_RIRBLBASE              0x50
  61 #define ICH6_REG_RIRBUBASE              0x54
  62 #define ICH6_REG_RIRBWP                 0x58
  63 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
  64 #define ICH6_REG_RINTCNT                0x5a
  65 #define ICH6_REG_RIRBCTL                0x5c
  66 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
  67 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
  68 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
  69 #define ICH6_REG_RIRBSTS                0x5d
  70 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
  71 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
  72 #define ICH6_REG_RIRBSIZE               0x5e
  73
  74 #define ICH6_REG_IC                     0x60
  75 #define ICH6_REG_IR                     0x64
  76 #define ICH6_REG_IRS                    0x68
  77 #define   ICH6_IRS_VALID        (1<<1)
  78 #define   ICH6_IRS_BUSY         (1<<0)
  79
  80 #define ICH6_REG_DPLBASE                0x70
  81 #define ICH6_REG_DPUBASE                0x74
  82 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
  83
  84 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
  85 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
  86
  87 /* stream register offsets from stream base */
  88 #define ICH6_REG_SD_CTL                 0x00
  89 #define ICH6_REG_SD_STS                 0x03
  90 #define ICH6_REG_SD_LPIB                0x04
  91 #define ICH6_REG_SD_CBL                 0x08
  92 #define ICH6_REG_SD_LVI                 0x0c
  93 #define ICH6_REG_SD_FIFOW               0x0e
  94 #define ICH6_REG_SD_FIFOSIZE            0x10
  95 #define ICH6_REG_SD_FORMAT              0x12
  96 #define ICH6_REG_SD_BDLPL               0x18
  97 #define ICH6_REG_SD_BDLPU               0x1c
  98
  99 /* PCI space */
 100 #define ICH6_PCIREG_TCSEL       0x44
 101
 102 /*
 103  * other constants
 104  */
 105
 106 /* max number of SDs */
 107 /* ICH, ATI and VIA have 4 playback and 4 capture */
 108 #define ICH6_NUM_CAPTURE        4
 109 #define ICH6_NUM_PLAYBACK       4
 110
 111 /* ULI has 6 playback and 5 capture */
 112 #define ULI_NUM_CAPTURE         5
 113 #define ULI_NUM_PLAYBACK        6
 114
 115 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 116 #define ATIHDMI_NUM_CAPTURE     0
 117 #define ATIHDMI_NUM_PLAYBACK    8
 118
 119 /* TERA has 4 playback and 3 capture */
 120 #define TERA_NUM_CAPTURE        3
 121 #define TERA_NUM_PLAYBACK       4
 122
 123 /* this number is statically defined for simplicity */
 124 #define MAX_AZX_DEV             16
 125
 126 /* max number of fragments - we may use more if allocating more pages for BDL */
 127 #define BDL_SIZE                4096
 128 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 129 #define AZX_MAX_FRAG            32
 130 /* max buffer size - no h/w limit, you can increase as you like */
 131 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 132
 133 /* RIRB int mask: overrun[2], response[0] */
 134 #define RIRB_INT_RESPONSE       0x01
 135 #define RIRB_INT_OVERRUN        0x04
 136 #define RIRB_INT_MASK           0x05
 137
 138 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 139 #define AZX_MAX_CODECS          8
 140 #define AZX_DEFAULT_CODECS      4
 141 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 142
 143 /* SD_CTL bits */
 144 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 145 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 146 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 147 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 148 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 149 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 150 #define SD_CTL_STREAM_TAG_SHIFT 20
 151
 152 /* SD_CTL and SD_STS */
 153 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 154 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 155 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 156 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 157                                  SD_INT_COMPLETE)
 158
 159 /* SD_STS */
 160 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 161
 162 /* INTCTL and INTSTS */
 163 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 164 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 165 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 166
 167 /* below are so far hardcoded - should read registers in future */
 168 #define ICH6_MAX_CORB_ENTRIES   256
 169 #define ICH6_MAX_RIRB_ENTRIES   256
 170
 171 /* driver quirks (capabilities) */
 172 /* bits 0-7 are used for indicating driver type */
 173 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 174 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 175 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 176 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 177 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 178 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 179 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 180 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 181 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 182 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 183 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 184 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 185 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 186 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 187 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
 188 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
 189 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
 190 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
 191 #define AZX_DCAPS_I915_POWERWELL (1 << 27)      /* HSW i915 powerwell support */
 192
 193 /* position fix mode */
 194 enum {
 195         POS_FIX_AUTO,
 196         POS_FIX_LPIB,
 197         POS_FIX_POSBUF,
 198         POS_FIX_VIACOMBO,
 199         POS_FIX_COMBO,
 200 };
 201
 202 /* Defines for ATI HD Audio support in SB450 south bridge */
 203 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 204 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 205
 206 /* Defines for Nvidia HDA support */
 207 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 208 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 209 #define NVIDIA_HDA_ISTRM_COH          0x4d
 210 #define NVIDIA_HDA_OSTRM_COH          0x4c
 211 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 212
 213 /* Defines for Intel SCH HDA snoop control */
 214 #define INTEL_SCH_HDA_DEVC      0x78
 215 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 216
 217 /* Define IN stream 0 FIFO size offset in VIA controller */
 218 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 219 /* Define VIA HD Audio Device ID*/
 220 #define VIA_HDAC_DEVICE_ID              0x3288
 221
 222 /* HD Audio class code */
 223 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 224
 225 struct azx_dev {
 226         struct snd_dma_buffer bdl; /* BDL buffer */
 227         u32 *posbuf;            /* position buffer pointer */
 228
 229         unsigned int bufsize;   /* size of the play buffer in bytes */
 230         unsigned int period_bytes; /* size of the period in bytes */
 231         unsigned int frags;     /* number for period in the play buffer */
 232         unsigned int fifo_size; /* FIFO size */
 233         unsigned long start_wallclk;    /* start + minimum wallclk */
 234         unsigned long period_wallclk;   /* wallclk for period */
 235
 236         void __iomem *sd_addr;  /* stream descriptor pointer */
 237
 238         u32 sd_int_sta_mask;    /* stream int status mask */
 239
 240         /* pcm support */
 241         struct snd_pcm_substream *substream;    /* assigned substream,
 242                                                  * set in PCM open
 243                                                  */
 244         unsigned int format_val;        /* format value to be set in the
 245                                          * controller and the codec
 246                                          */
 247         unsigned char stream_tag;       /* assigned stream */
 248         unsigned char index;            /* stream index */
 249         int assigned_key;               /* last device# key assigned to */
 250
 251         unsigned int opened:1;
 252         unsigned int running:1;
 253         unsigned int irq_pending:1;
 254         unsigned int prepared:1;
 255         unsigned int locked:1;
 256         /*
 257          * For VIA:
 258          *  A flag to ensure DMA position is 0
 259          *  when link position is not greater than FIFO size
 260          */
 261         unsigned int insufficient:1;
 262         unsigned int wc_marked:1;
 263         unsigned int no_period_wakeup:1;
 264
 265         struct timecounter  azx_tc;
 266         struct cyclecounter azx_cc;
 267
 268         int delay_negative_threshold;
 269
 270 #ifdef CONFIG_SND_HDA_DSP_LOADER
 271         /* Allows dsp load to have sole access to the playback stream. */
 272         struct mutex dsp_mutex;
 273 #endif
 274 };
 275
 276 /* CORB/RIRB */
 277 struct azx_rb {
 278         u32 *buf;               /* CORB/RIRB buffer
 279                                  * Each CORB entry is 4byte, RIRB is 8byte
 280                                  */
 281         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 282         /* for RIRB */
 283         unsigned short rp, wp;  /* read/write pointers */
 284         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 285         u32 res[AZX_MAX_CODECS];        /* last read value */
 286 };
 287
 288 /* Functions to read/write to hda registers. */
 289 struct hda_controller_ops {
 290         /* Register Access */
 291         void (*writel)(u32 value, u32 *addr);
 292         u32 (*readl)(u32 *addr);
 293         void (*writew)(u16 value, u16 *addr);
 294         u16 (*readw)(u16 *addr);
 295         void (*writeb)(u8 value, u8 *addr);
 296         u8 (*readb)(u8 *addr);
 297 };
 298
 299 struct azx_pcm {
 300         struct azx *chip;
 301         struct snd_pcm *pcm;
 302         struct hda_codec *codec;
 303         struct hda_pcm_stream *hinfo[2];
 304         struct list_head list;
 305 };
 306
 307 struct azx {
 308         struct snd_card *card;
 309         struct pci_dev *pci;
 310         int dev_index;
 311
 312         /* chip type specific */
 313         int driver_type;
 314         unsigned int driver_caps;
 315         int playback_streams;
 316         int playback_index_offset;
 317         int capture_streams;
 318         int capture_index_offset;
 319         int num_streams;
 320
 321         /* Register interaction. */
 322         const struct hda_controller_ops *ops;
 323
 324         /* pci resources */
 325         unsigned long addr;
 326         void __iomem *remap_addr;
 327         int irq;
 328
 329         /* locks */
 330         spinlock_t reg_lock;
 331         struct mutex open_mutex; /* Prevents concurrent open/close operations */
 332         struct completion probe_wait;
 333
 334         /* streams (x num_streams) */
 335         struct azx_dev *azx_dev;
 336
 337         /* PCM */
 338         struct list_head pcm_list; /* azx_pcm list */
 339
 340         /* HD codec */
 341         unsigned short codec_mask;
 342         int  codec_probe_mask; /* copied from probe_mask option */
 343         struct hda_bus *bus;
 344         unsigned int beep_mode;
 345
 346         /* CORB/RIRB */
 347         struct azx_rb corb;
 348         struct azx_rb rirb;
 349
 350         /* CORB/RIRB and position buffers */
 351         struct snd_dma_buffer rb;
 352         struct snd_dma_buffer posbuf;
 353
 354 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 355         const struct firmware *fw;
 356 #endif
 357
 358         /* flags */
 359         int position_fix[2]; /* for both playback/capture streams */
 360         const int *bdl_pos_adj;
 361         int poll_count;
 362         unsigned int running:1;
 363         unsigned int initialized:1;
 364         unsigned int single_cmd:1;
 365         unsigned int polling_mode:1;
 366         unsigned int msi:1;
 367         unsigned int irq_pending_warned:1;
 368         unsigned int probing:1; /* codec probing phase */
 369         unsigned int snoop:1;
 370         unsigned int align_buffer_size:1;
 371         unsigned int region_requested:1;
 372
 373         /* VGA-switcheroo setup */
 374         unsigned int use_vga_switcheroo:1;
 375         unsigned int vga_switcheroo_registered:1;
 376         unsigned int init_failed:1; /* delayed init failed */
 377         unsigned int disabled:1; /* disabled by VGA-switcher */
 378
 379         /* for debugging */
 380         unsigned int last_cmd[AZX_MAX_CODECS];
 381
 382         /* for pending irqs */
 383         struct work_struct irq_pending_work;
 384
 385         struct work_struct probe_work;
 386
 387         /* reboot notifier (for mysterious hangup problem at power-down) */
 388         struct notifier_block reboot_notifier;
 389
 390         /* card list (for power_save trigger) */
 391         struct list_head list;
 392
 393 #ifdef CONFIG_SND_HDA_DSP_LOADER
 394         struct azx_dev saved_azx_dev;
 395 #endif
 396
 397         /* secondary power domain for hdmi audio under vga device */
 398         struct dev_pm_domain hdmi_pm_domain;
 399 };
 400
 401 #ifdef CONFIG_SND_VERBOSE_PRINTK
 402 #define SFX     /* nop */
 403 #else
 404 #define SFX     "hda-intel "
 405 #endif
 406
 407 #ifdef CONFIG_X86
 408 #define azx_snoop(chip)         ((chip)->snoop)
 409 #else
 410 #define azx_snoop(chip)         true
 411 #endif
 412
 413 /*
 414  * macros for easy use
 415  */
 416
 417 #define azx_writel(chip, reg, value) \
 418         ((chip)->ops->writel(value, (chip)->remap_addr + ICH6_REG_##reg))
 419 #define azx_readl(chip, reg) \
 420         ((chip)->ops->readl((chip)->remap_addr + ICH6_REG_##reg))
 421 #define azx_writew(chip, reg, value) \
 422         ((chip)->ops->writew(value, (chip)->remap_addr + ICH6_REG_##reg))
 423 #define azx_readw(chip, reg) \
 424         ((chip)->ops->readw((chip)->remap_addr + ICH6_REG_##reg))
 425 #define azx_writeb(chip, reg, value) \
 426         ((chip)->ops->writeb(value, (chip)->remap_addr + ICH6_REG_##reg))
 427 #define azx_readb(chip, reg) \
 428         ((chip)->ops->readb((chip)->remap_addr + ICH6_REG_##reg))
 429
 430 #define azx_sd_writel(chip, dev, reg, value) \
 431         ((chip)->ops->writel(value, (dev)->sd_addr + ICH6_REG_##reg))
 432 #define azx_sd_readl(chip, dev, reg) \
 433         ((chip)->ops->readl((dev)->sd_addr + ICH6_REG_##reg))
 434 #define azx_sd_writew(chip, dev, reg, value) \
 435         ((chip)->ops->writew(value, (dev)->sd_addr + ICH6_REG_##reg))
 436 #define azx_sd_readw(chip, dev, reg) \
 437         ((chip)->ops->readw((dev)->sd_addr + ICH6_REG_##reg))
 438 #define azx_sd_writeb(chip, dev, reg, value) \
 439         ((chip)->ops->writeb(value, (dev)->sd_addr + ICH6_REG_##reg))
 440 #define azx_sd_readb(chip, dev, reg) \
 441         ((chip)->ops->readb((dev)->sd_addr + ICH6_REG_##reg))
 442
 443 #endif /* __SOUND_HDA_PRIV_H */