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Merge tag 'master-2014-11-25' of git://git.kernel.org/pub/scm/linux/kernel/git/linvil...
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
1 /*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include "hda_codec.h"
41 #include "hda_local.h"
42 #include "hda_jack.h"
43
44 static bool static_hdmi_pcm;
45 module_param(static_hdmi_pcm, bool, 0644);
46 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47
48 #define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
49 #define is_broadwell(codec) ((codec)->vendor_id == 0x80862808)
50 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec))
51
52 #define is_valleyview(codec) ((codec)->vendor_id == 0x80862882)
53 #define is_cherryview(codec) ((codec)->vendor_id == 0x80862883)
54 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
55
56 struct hdmi_spec_per_cvt {
57 hda_nid_t cvt_nid;
58 int assigned;
59 unsigned int channels_min;
60 unsigned int channels_max;
61 u32 rates;
62 u64 formats;
63 unsigned int maxbps;
64 };
65
66 /* max. connections to a widget */
67 #define HDA_MAX_CONNECTIONS 32
68
69 struct hdmi_spec_per_pin {
70 hda_nid_t pin_nid;
71 int num_mux_nids;
72 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
73 int mux_idx;
74 hda_nid_t cvt_nid;
75
76 struct hda_codec *codec;
77 struct hdmi_eld sink_eld;
78 struct mutex lock;
79 struct delayed_work work;
80 struct snd_kcontrol *eld_ctl;
81 int repoll_count;
82 bool setup; /* the stream has been set up by prepare callback */
83 int channels; /* current number of channels */
84 bool non_pcm;
85 bool chmap_set; /* channel-map override by ALSA API? */
86 unsigned char chmap[8]; /* ALSA API channel-map */
87 char pcm_name[8]; /* filled in build_pcm callbacks */
88 #ifdef CONFIG_PROC_FS
89 struct snd_info_entry *proc_entry;
90 #endif
91 };
92
93 struct cea_channel_speaker_allocation;
94
95 /* operations used by generic code that can be overridden by patches */
96 struct hdmi_ops {
97 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
98 unsigned char *buf, int *eld_size);
99
100 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
101 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
102 int asp_slot);
103 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
104 int asp_slot, int channel);
105
106 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
107 int ca, int active_channels, int conn_type);
108
109 /* enable/disable HBR (HD passthrough) */
110 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
111
112 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
113 hda_nid_t pin_nid, u32 stream_tag, int format);
114
115 /* Helpers for producing the channel map TLVs. These can be overridden
116 * for devices that have non-standard mapping requirements. */
117 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
118 int channels);
119 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
120 unsigned int *chmap, int channels);
121
122 /* check that the user-given chmap is supported */
123 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
124 };
125
126 struct hdmi_spec {
127 int num_cvts;
128 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
129 hda_nid_t cvt_nids[4]; /* only for haswell fix */
130
131 int num_pins;
132 struct snd_array pins; /* struct hdmi_spec_per_pin */
133 struct snd_array pcm_rec; /* struct hda_pcm */
134 unsigned int channels_max; /* max over all cvts */
135
136 struct hdmi_eld temp_eld;
137 struct hdmi_ops ops;
138
139 bool dyn_pin_out;
140
141 /*
142 * Non-generic VIA/NVIDIA specific
143 */
144 struct hda_multi_out multiout;
145 struct hda_pcm_stream pcm_playback;
146 };
147
148
149 struct hdmi_audio_infoframe {
150 u8 type; /* 0x84 */
151 u8 ver; /* 0x01 */
152 u8 len; /* 0x0a */
153
154 u8 checksum;
155
156 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
157 u8 SS01_SF24;
158 u8 CXT04;
159 u8 CA;
160 u8 LFEPBL01_LSV36_DM_INH7;
161 };
162
163 struct dp_audio_infoframe {
164 u8 type; /* 0x84 */
165 u8 len; /* 0x1b */
166 u8 ver; /* 0x11 << 2 */
167
168 u8 CC02_CT47; /* match with HDMI infoframe from this on */
169 u8 SS01_SF24;
170 u8 CXT04;
171 u8 CA;
172 u8 LFEPBL01_LSV36_DM_INH7;
173 };
174
175 union audio_infoframe {
176 struct hdmi_audio_infoframe hdmi;
177 struct dp_audio_infoframe dp;
178 u8 bytes[0];
179 };
180
181 /*
182 * CEA speaker placement:
183 *
184 * FLH FCH FRH
185 * FLW FL FLC FC FRC FR FRW
186 *
187 * LFE
188 * TC
189 *
190 * RL RLC RC RRC RR
191 *
192 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
193 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
194 */
195 enum cea_speaker_placement {
196 FL = (1 << 0), /* Front Left */
197 FC = (1 << 1), /* Front Center */
198 FR = (1 << 2), /* Front Right */
199 FLC = (1 << 3), /* Front Left Center */
200 FRC = (1 << 4), /* Front Right Center */
201 RL = (1 << 5), /* Rear Left */
202 RC = (1 << 6), /* Rear Center */
203 RR = (1 << 7), /* Rear Right */
204 RLC = (1 << 8), /* Rear Left Center */
205 RRC = (1 << 9), /* Rear Right Center */
206 LFE = (1 << 10), /* Low Frequency Effect */
207 FLW = (1 << 11), /* Front Left Wide */
208 FRW = (1 << 12), /* Front Right Wide */
209 FLH = (1 << 13), /* Front Left High */
210 FCH = (1 << 14), /* Front Center High */
211 FRH = (1 << 15), /* Front Right High */
212 TC = (1 << 16), /* Top Center */
213 };
214
215 /*
216 * ELD SA bits in the CEA Speaker Allocation data block
217 */
218 static int eld_speaker_allocation_bits[] = {
219 [0] = FL | FR,
220 [1] = LFE,
221 [2] = FC,
222 [3] = RL | RR,
223 [4] = RC,
224 [5] = FLC | FRC,
225 [6] = RLC | RRC,
226 /* the following are not defined in ELD yet */
227 [7] = FLW | FRW,
228 [8] = FLH | FRH,
229 [9] = TC,
230 [10] = FCH,
231 };
232
233 struct cea_channel_speaker_allocation {
234 int ca_index;
235 int speakers[8];
236
237 /* derived values, just for convenience */
238 int channels;
239 int spk_mask;
240 };
241
242 /*
243 * ALSA sequence is:
244 *
245 * surround40 surround41 surround50 surround51 surround71
246 * ch0 front left = = = =
247 * ch1 front right = = = =
248 * ch2 rear left = = = =
249 * ch3 rear right = = = =
250 * ch4 LFE center center center
251 * ch5 LFE LFE
252 * ch6 side left
253 * ch7 side right
254 *
255 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
256 */
257 static int hdmi_channel_mapping[0x32][8] = {
258 /* stereo */
259 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
260 /* 2.1 */
261 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
262 /* Dolby Surround */
263 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
264 /* surround40 */
265 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
266 /* 4ch */
267 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
268 /* surround41 */
269 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
270 /* surround50 */
271 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
272 /* surround51 */
273 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
274 /* 7.1 */
275 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
276 };
277
278 /*
279 * This is an ordered list!
280 *
281 * The preceding ones have better chances to be selected by
282 * hdmi_channel_allocation().
283 */
284 static struct cea_channel_speaker_allocation channel_allocations[] = {
285 /* channel: 7 6 5 4 3 2 1 0 */
286 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
287 /* 2.1 */
288 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
289 /* Dolby Surround */
290 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
291 /* surround40 */
292 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
293 /* surround41 */
294 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
295 /* surround50 */
296 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
297 /* surround51 */
298 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
299 /* 6.1 */
300 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
301 /* surround71 */
302 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
303
304 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
305 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
306 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
307 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
308 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
309 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
310 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
311 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
312 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
313 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
314 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
315 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
316 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
317 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
318 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
319 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
320 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
321 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
322 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
323 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
324 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
325 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
326 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
327 { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
328 { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
329 { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
330 { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
331 { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
332 { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
333 { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
334 { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
335 { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
336 { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
337 { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
338 { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
339 { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
340 { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
341 { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
342 { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
343 { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
344 { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
345 };
346
347
348 /*
349 * HDMI routines
350 */
351
352 #define get_pin(spec, idx) \
353 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
354 #define get_cvt(spec, idx) \
355 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
356 #define get_pcm_rec(spec, idx) \
357 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
358
359 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
360 {
361 struct hdmi_spec *spec = codec->spec;
362 int pin_idx;
363
364 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
365 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
366 return pin_idx;
367
368 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
369 return -EINVAL;
370 }
371
372 static int hinfo_to_pin_index(struct hda_codec *codec,
373 struct hda_pcm_stream *hinfo)
374 {
375 struct hdmi_spec *spec = codec->spec;
376 int pin_idx;
377
378 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
379 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
380 return pin_idx;
381
382 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
383 return -EINVAL;
384 }
385
386 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
387 {
388 struct hdmi_spec *spec = codec->spec;
389 int cvt_idx;
390
391 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
392 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
393 return cvt_idx;
394
395 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
396 return -EINVAL;
397 }
398
399 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
400 struct snd_ctl_elem_info *uinfo)
401 {
402 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
403 struct hdmi_spec *spec = codec->spec;
404 struct hdmi_spec_per_pin *per_pin;
405 struct hdmi_eld *eld;
406 int pin_idx;
407
408 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
409
410 pin_idx = kcontrol->private_value;
411 per_pin = get_pin(spec, pin_idx);
412 eld = &per_pin->sink_eld;
413
414 mutex_lock(&per_pin->lock);
415 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
416 mutex_unlock(&per_pin->lock);
417
418 return 0;
419 }
420
421 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_value *ucontrol)
423 {
424 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
425 struct hdmi_spec *spec = codec->spec;
426 struct hdmi_spec_per_pin *per_pin;
427 struct hdmi_eld *eld;
428 int pin_idx;
429
430 pin_idx = kcontrol->private_value;
431 per_pin = get_pin(spec, pin_idx);
432 eld = &per_pin->sink_eld;
433
434 mutex_lock(&per_pin->lock);
435 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
436 mutex_unlock(&per_pin->lock);
437 snd_BUG();
438 return -EINVAL;
439 }
440
441 memset(ucontrol->value.bytes.data, 0,
442 ARRAY_SIZE(ucontrol->value.bytes.data));
443 if (eld->eld_valid)
444 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
445 eld->eld_size);
446 mutex_unlock(&per_pin->lock);
447
448 return 0;
449 }
450
451 static struct snd_kcontrol_new eld_bytes_ctl = {
452 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
453 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
454 .name = "ELD",
455 .info = hdmi_eld_ctl_info,
456 .get = hdmi_eld_ctl_get,
457 };
458
459 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
460 int device)
461 {
462 struct snd_kcontrol *kctl;
463 struct hdmi_spec *spec = codec->spec;
464 int err;
465
466 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
467 if (!kctl)
468 return -ENOMEM;
469 kctl->private_value = pin_idx;
470 kctl->id.device = device;
471
472 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
473 if (err < 0)
474 return err;
475
476 get_pin(spec, pin_idx)->eld_ctl = kctl;
477 return 0;
478 }
479
480 #ifdef BE_PARANOID
481 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
482 int *packet_index, int *byte_index)
483 {
484 int val;
485
486 val = snd_hda_codec_read(codec, pin_nid, 0,
487 AC_VERB_GET_HDMI_DIP_INDEX, 0);
488
489 *packet_index = val >> 5;
490 *byte_index = val & 0x1f;
491 }
492 #endif
493
494 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
495 int packet_index, int byte_index)
496 {
497 int val;
498
499 val = (packet_index << 5) | (byte_index & 0x1f);
500
501 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
502 }
503
504 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
505 unsigned char val)
506 {
507 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
508 }
509
510 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
511 {
512 struct hdmi_spec *spec = codec->spec;
513 int pin_out;
514
515 /* Unmute */
516 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
517 snd_hda_codec_write(codec, pin_nid, 0,
518 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
519
520 if (spec->dyn_pin_out)
521 /* Disable pin out until stream is active */
522 pin_out = 0;
523 else
524 /* Enable pin out: some machines with GM965 gets broken output
525 * when the pin is disabled or changed while using with HDMI
526 */
527 pin_out = PIN_OUT;
528
529 snd_hda_codec_write(codec, pin_nid, 0,
530 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
531 }
532
533 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
534 {
535 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
536 AC_VERB_GET_CVT_CHAN_COUNT, 0);
537 }
538
539 static void hdmi_set_channel_count(struct hda_codec *codec,
540 hda_nid_t cvt_nid, int chs)
541 {
542 if (chs != hdmi_get_channel_count(codec, cvt_nid))
543 snd_hda_codec_write(codec, cvt_nid, 0,
544 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
545 }
546
547 /*
548 * ELD proc files
549 */
550
551 #ifdef CONFIG_PROC_FS
552 static void print_eld_info(struct snd_info_entry *entry,
553 struct snd_info_buffer *buffer)
554 {
555 struct hdmi_spec_per_pin *per_pin = entry->private_data;
556
557 mutex_lock(&per_pin->lock);
558 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
559 mutex_unlock(&per_pin->lock);
560 }
561
562 static void write_eld_info(struct snd_info_entry *entry,
563 struct snd_info_buffer *buffer)
564 {
565 struct hdmi_spec_per_pin *per_pin = entry->private_data;
566
567 mutex_lock(&per_pin->lock);
568 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
569 mutex_unlock(&per_pin->lock);
570 }
571
572 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
573 {
574 char name[32];
575 struct hda_codec *codec = per_pin->codec;
576 struct snd_info_entry *entry;
577 int err;
578
579 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
580 err = snd_card_proc_new(codec->bus->card, name, &entry);
581 if (err < 0)
582 return err;
583
584 snd_info_set_text_ops(entry, per_pin, print_eld_info);
585 entry->c.text.write = write_eld_info;
586 entry->mode |= S_IWUSR;
587 per_pin->proc_entry = entry;
588
589 return 0;
590 }
591
592 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
593 {
594 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
595 snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry);
596 per_pin->proc_entry = NULL;
597 }
598 }
599 #else
600 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
601 int index)
602 {
603 return 0;
604 }
605 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
606 {
607 }
608 #endif
609
610 /*
611 * Channel mapping routines
612 */
613
614 /*
615 * Compute derived values in channel_allocations[].
616 */
617 static void init_channel_allocations(void)
618 {
619 int i, j;
620 struct cea_channel_speaker_allocation *p;
621
622 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
623 p = channel_allocations + i;
624 p->channels = 0;
625 p->spk_mask = 0;
626 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
627 if (p->speakers[j]) {
628 p->channels++;
629 p->spk_mask |= p->speakers[j];
630 }
631 }
632 }
633
634 static int get_channel_allocation_order(int ca)
635 {
636 int i;
637
638 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
639 if (channel_allocations[i].ca_index == ca)
640 break;
641 }
642 return i;
643 }
644
645 /*
646 * The transformation takes two steps:
647 *
648 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
649 * spk_mask => (channel_allocations[]) => ai->CA
650 *
651 * TODO: it could select the wrong CA from multiple candidates.
652 */
653 static int hdmi_channel_allocation(struct hda_codec *codec,
654 struct hdmi_eld *eld, int channels)
655 {
656 int i;
657 int ca = 0;
658 int spk_mask = 0;
659 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
660
661 /*
662 * CA defaults to 0 for basic stereo audio
663 */
664 if (channels <= 2)
665 return 0;
666
667 /*
668 * expand ELD's speaker allocation mask
669 *
670 * ELD tells the speaker mask in a compact(paired) form,
671 * expand ELD's notions to match the ones used by Audio InfoFrame.
672 */
673 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
674 if (eld->info.spk_alloc & (1 << i))
675 spk_mask |= eld_speaker_allocation_bits[i];
676 }
677
678 /* search for the first working match in the CA table */
679 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
680 if (channels == channel_allocations[i].channels &&
681 (spk_mask & channel_allocations[i].spk_mask) ==
682 channel_allocations[i].spk_mask) {
683 ca = channel_allocations[i].ca_index;
684 break;
685 }
686 }
687
688 if (!ca) {
689 /* if there was no match, select the regular ALSA channel
690 * allocation with the matching number of channels */
691 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
692 if (channels == channel_allocations[i].channels) {
693 ca = channel_allocations[i].ca_index;
694 break;
695 }
696 }
697 }
698
699 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
700 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
701 ca, channels, buf);
702
703 return ca;
704 }
705
706 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
707 hda_nid_t pin_nid)
708 {
709 #ifdef CONFIG_SND_DEBUG_VERBOSE
710 struct hdmi_spec *spec = codec->spec;
711 int i;
712 int channel;
713
714 for (i = 0; i < 8; i++) {
715 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
716 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
717 channel, i);
718 }
719 #endif
720 }
721
722 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
723 hda_nid_t pin_nid,
724 bool non_pcm,
725 int ca)
726 {
727 struct hdmi_spec *spec = codec->spec;
728 struct cea_channel_speaker_allocation *ch_alloc;
729 int i;
730 int err;
731 int order;
732 int non_pcm_mapping[8];
733
734 order = get_channel_allocation_order(ca);
735 ch_alloc = &channel_allocations[order];
736
737 if (hdmi_channel_mapping[ca][1] == 0) {
738 int hdmi_slot = 0;
739 /* fill actual channel mappings in ALSA channel (i) order */
740 for (i = 0; i < ch_alloc->channels; i++) {
741 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
742 hdmi_slot++; /* skip zero slots */
743
744 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
745 }
746 /* fill the rest of the slots with ALSA channel 0xf */
747 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
748 if (!ch_alloc->speakers[7 - hdmi_slot])
749 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
750 }
751
752 if (non_pcm) {
753 for (i = 0; i < ch_alloc->channels; i++)
754 non_pcm_mapping[i] = (i << 4) | i;
755 for (; i < 8; i++)
756 non_pcm_mapping[i] = (0xf << 4) | i;
757 }
758
759 for (i = 0; i < 8; i++) {
760 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
761 int hdmi_slot = slotsetup & 0x0f;
762 int channel = (slotsetup & 0xf0) >> 4;
763 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
764 if (err) {
765 codec_dbg(codec, "HDMI: channel mapping failed\n");
766 break;
767 }
768 }
769 }
770
771 struct channel_map_table {
772 unsigned char map; /* ALSA API channel map position */
773 int spk_mask; /* speaker position bit mask */
774 };
775
776 static struct channel_map_table map_tables[] = {
777 { SNDRV_CHMAP_FL, FL },
778 { SNDRV_CHMAP_FR, FR },
779 { SNDRV_CHMAP_RL, RL },
780 { SNDRV_CHMAP_RR, RR },
781 { SNDRV_CHMAP_LFE, LFE },
782 { SNDRV_CHMAP_FC, FC },
783 { SNDRV_CHMAP_RLC, RLC },
784 { SNDRV_CHMAP_RRC, RRC },
785 { SNDRV_CHMAP_RC, RC },
786 { SNDRV_CHMAP_FLC, FLC },
787 { SNDRV_CHMAP_FRC, FRC },
788 { SNDRV_CHMAP_TFL, FLH },
789 { SNDRV_CHMAP_TFR, FRH },
790 { SNDRV_CHMAP_FLW, FLW },
791 { SNDRV_CHMAP_FRW, FRW },
792 { SNDRV_CHMAP_TC, TC },
793 { SNDRV_CHMAP_TFC, FCH },
794 {} /* terminator */
795 };
796
797 /* from ALSA API channel position to speaker bit mask */
798 static int to_spk_mask(unsigned char c)
799 {
800 struct channel_map_table *t = map_tables;
801 for (; t->map; t++) {
802 if (t->map == c)
803 return t->spk_mask;
804 }
805 return 0;
806 }
807
808 /* from ALSA API channel position to CEA slot */
809 static int to_cea_slot(int ordered_ca, unsigned char pos)
810 {
811 int mask = to_spk_mask(pos);
812 int i;
813
814 if (mask) {
815 for (i = 0; i < 8; i++) {
816 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
817 return i;
818 }
819 }
820
821 return -1;
822 }
823
824 /* from speaker bit mask to ALSA API channel position */
825 static int spk_to_chmap(int spk)
826 {
827 struct channel_map_table *t = map_tables;
828 for (; t->map; t++) {
829 if (t->spk_mask == spk)
830 return t->map;
831 }
832 return 0;
833 }
834
835 /* from CEA slot to ALSA API channel position */
836 static int from_cea_slot(int ordered_ca, unsigned char slot)
837 {
838 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
839
840 return spk_to_chmap(mask);
841 }
842
843 /* get the CA index corresponding to the given ALSA API channel map */
844 static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
845 {
846 int i, spks = 0, spk_mask = 0;
847
848 for (i = 0; i < chs; i++) {
849 int mask = to_spk_mask(map[i]);
850 if (mask) {
851 spk_mask |= mask;
852 spks++;
853 }
854 }
855
856 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
857 if ((chs == channel_allocations[i].channels ||
858 spks == channel_allocations[i].channels) &&
859 (spk_mask & channel_allocations[i].spk_mask) ==
860 channel_allocations[i].spk_mask)
861 return channel_allocations[i].ca_index;
862 }
863 return -1;
864 }
865
866 /* set up the channel slots for the given ALSA API channel map */
867 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
868 hda_nid_t pin_nid,
869 int chs, unsigned char *map,
870 int ca)
871 {
872 struct hdmi_spec *spec = codec->spec;
873 int ordered_ca = get_channel_allocation_order(ca);
874 int alsa_pos, hdmi_slot;
875 int assignments[8] = {[0 ... 7] = 0xf};
876
877 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
878
879 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
880
881 if (hdmi_slot < 0)
882 continue; /* unassigned channel */
883
884 assignments[hdmi_slot] = alsa_pos;
885 }
886
887 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
888 int err;
889
890 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
891 assignments[hdmi_slot]);
892 if (err)
893 return -EINVAL;
894 }
895 return 0;
896 }
897
898 /* store ALSA API channel map from the current default map */
899 static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
900 {
901 int i;
902 int ordered_ca = get_channel_allocation_order(ca);
903 for (i = 0; i < 8; i++) {
904 if (i < channel_allocations[ordered_ca].channels)
905 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
906 else
907 map[i] = 0;
908 }
909 }
910
911 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
912 hda_nid_t pin_nid, bool non_pcm, int ca,
913 int channels, unsigned char *map,
914 bool chmap_set)
915 {
916 if (!non_pcm && chmap_set) {
917 hdmi_manual_setup_channel_mapping(codec, pin_nid,
918 channels, map, ca);
919 } else {
920 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
921 hdmi_setup_fake_chmap(map, ca);
922 }
923
924 hdmi_debug_channel_mapping(codec, pin_nid);
925 }
926
927 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
928 int asp_slot, int channel)
929 {
930 return snd_hda_codec_write(codec, pin_nid, 0,
931 AC_VERB_SET_HDMI_CHAN_SLOT,
932 (channel << 4) | asp_slot);
933 }
934
935 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
936 int asp_slot)
937 {
938 return (snd_hda_codec_read(codec, pin_nid, 0,
939 AC_VERB_GET_HDMI_CHAN_SLOT,
940 asp_slot) & 0xf0) >> 4;
941 }
942
943 /*
944 * Audio InfoFrame routines
945 */
946
947 /*
948 * Enable Audio InfoFrame Transmission
949 */
950 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
951 hda_nid_t pin_nid)
952 {
953 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
954 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
955 AC_DIPXMIT_BEST);
956 }
957
958 /*
959 * Disable Audio InfoFrame Transmission
960 */
961 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
962 hda_nid_t pin_nid)
963 {
964 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
965 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
966 AC_DIPXMIT_DISABLE);
967 }
968
969 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
970 {
971 #ifdef CONFIG_SND_DEBUG_VERBOSE
972 int i;
973 int size;
974
975 size = snd_hdmi_get_eld_size(codec, pin_nid);
976 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
977
978 for (i = 0; i < 8; i++) {
979 size = snd_hda_codec_read(codec, pin_nid, 0,
980 AC_VERB_GET_HDMI_DIP_SIZE, i);
981 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
982 }
983 #endif
984 }
985
986 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
987 {
988 #ifdef BE_PARANOID
989 int i, j;
990 int size;
991 int pi, bi;
992 for (i = 0; i < 8; i++) {
993 size = snd_hda_codec_read(codec, pin_nid, 0,
994 AC_VERB_GET_HDMI_DIP_SIZE, i);
995 if (size == 0)
996 continue;
997
998 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
999 for (j = 1; j < 1000; j++) {
1000 hdmi_write_dip_byte(codec, pin_nid, 0x0);
1001 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1002 if (pi != i)
1003 codec_dbg(codec, "dip index %d: %d != %d\n",
1004 bi, pi, i);
1005 if (bi == 0) /* byte index wrapped around */
1006 break;
1007 }
1008 codec_dbg(codec,
1009 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1010 i, size, j);
1011 }
1012 #endif
1013 }
1014
1015 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1016 {
1017 u8 *bytes = (u8 *)hdmi_ai;
1018 u8 sum = 0;
1019 int i;
1020
1021 hdmi_ai->checksum = 0;
1022
1023 for (i = 0; i < sizeof(*hdmi_ai); i++)
1024 sum += bytes[i];
1025
1026 hdmi_ai->checksum = -sum;
1027 }
1028
1029 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1030 hda_nid_t pin_nid,
1031 u8 *dip, int size)
1032 {
1033 int i;
1034
1035 hdmi_debug_dip_size(codec, pin_nid);
1036 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1037
1038 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1039 for (i = 0; i < size; i++)
1040 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1041 }
1042
1043 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1044 u8 *dip, int size)
1045 {
1046 u8 val;
1047 int i;
1048
1049 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1050 != AC_DIPXMIT_BEST)
1051 return false;
1052
1053 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1054 for (i = 0; i < size; i++) {
1055 val = snd_hda_codec_read(codec, pin_nid, 0,
1056 AC_VERB_GET_HDMI_DIP_DATA, 0);
1057 if (val != dip[i])
1058 return false;
1059 }
1060
1061 return true;
1062 }
1063
1064 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1065 hda_nid_t pin_nid,
1066 int ca, int active_channels,
1067 int conn_type)
1068 {
1069 union audio_infoframe ai;
1070
1071 memset(&ai, 0, sizeof(ai));
1072 if (conn_type == 0) { /* HDMI */
1073 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1074
1075 hdmi_ai->type = 0x84;
1076 hdmi_ai->ver = 0x01;
1077 hdmi_ai->len = 0x0a;
1078 hdmi_ai->CC02_CT47 = active_channels - 1;
1079 hdmi_ai->CA = ca;
1080 hdmi_checksum_audio_infoframe(hdmi_ai);
1081 } else if (conn_type == 1) { /* DisplayPort */
1082 struct dp_audio_infoframe *dp_ai = &ai.dp;
1083
1084 dp_ai->type = 0x84;
1085 dp_ai->len = 0x1b;
1086 dp_ai->ver = 0x11 << 2;
1087 dp_ai->CC02_CT47 = active_channels - 1;
1088 dp_ai->CA = ca;
1089 } else {
1090 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1091 pin_nid);
1092 return;
1093 }
1094
1095 /*
1096 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1097 * sizeof(*dp_ai) to avoid partial match/update problems when
1098 * the user switches between HDMI/DP monitors.
1099 */
1100 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1101 sizeof(ai))) {
1102 codec_dbg(codec,
1103 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1104 pin_nid,
1105 active_channels, ca);
1106 hdmi_stop_infoframe_trans(codec, pin_nid);
1107 hdmi_fill_audio_infoframe(codec, pin_nid,
1108 ai.bytes, sizeof(ai));
1109 hdmi_start_infoframe_trans(codec, pin_nid);
1110 }
1111 }
1112
1113 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1114 struct hdmi_spec_per_pin *per_pin,
1115 bool non_pcm)
1116 {
1117 struct hdmi_spec *spec = codec->spec;
1118 hda_nid_t pin_nid = per_pin->pin_nid;
1119 int channels = per_pin->channels;
1120 int active_channels;
1121 struct hdmi_eld *eld;
1122 int ca, ordered_ca;
1123
1124 if (!channels)
1125 return;
1126
1127 if (is_haswell_plus(codec))
1128 snd_hda_codec_write(codec, pin_nid, 0,
1129 AC_VERB_SET_AMP_GAIN_MUTE,
1130 AMP_OUT_UNMUTE);
1131
1132 eld = &per_pin->sink_eld;
1133
1134 if (!non_pcm && per_pin->chmap_set)
1135 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1136 else
1137 ca = hdmi_channel_allocation(codec, eld, channels);
1138 if (ca < 0)
1139 ca = 0;
1140
1141 ordered_ca = get_channel_allocation_order(ca);
1142 active_channels = channel_allocations[ordered_ca].channels;
1143
1144 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1145
1146 /*
1147 * always configure channel mapping, it may have been changed by the
1148 * user in the meantime
1149 */
1150 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1151 channels, per_pin->chmap,
1152 per_pin->chmap_set);
1153
1154 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1155 eld->info.conn_type);
1156
1157 per_pin->non_pcm = non_pcm;
1158 }
1159
1160 /*
1161 * Unsolicited events
1162 */
1163
1164 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1165
1166 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
1167 {
1168 struct hdmi_spec *spec = codec->spec;
1169 int pin_idx = pin_nid_to_pin_index(codec, nid);
1170
1171 if (pin_idx < 0)
1172 return;
1173 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1174 snd_hda_jack_report_sync(codec);
1175 }
1176
1177 static void jack_callback(struct hda_codec *codec,
1178 struct hda_jack_callback *jack)
1179 {
1180 check_presence_and_report(codec, jack->tbl->nid);
1181 }
1182
1183 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1184 {
1185 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1186 struct hda_jack_tbl *jack;
1187 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1188
1189 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1190 if (!jack)
1191 return;
1192 jack->jack_dirty = 1;
1193
1194 codec_dbg(codec,
1195 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1196 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1197 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1198
1199 check_presence_and_report(codec, jack->nid);
1200 }
1201
1202 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1203 {
1204 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1205 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1206 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1207 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1208
1209 codec_info(codec,
1210 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1211 codec->addr,
1212 tag,
1213 subtag,
1214 cp_state,
1215 cp_ready);
1216
1217 /* TODO */
1218 if (cp_state)
1219 ;
1220 if (cp_ready)
1221 ;
1222 }
1223
1224
1225 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1226 {
1227 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1228 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1229
1230 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1231 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1232 return;
1233 }
1234
1235 if (subtag == 0)
1236 hdmi_intrinsic_event(codec, res);
1237 else
1238 hdmi_non_intrinsic_event(codec, res);
1239 }
1240
1241 static void haswell_verify_D0(struct hda_codec *codec,
1242 hda_nid_t cvt_nid, hda_nid_t nid)
1243 {
1244 int pwr;
1245
1246 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1247 * thus pins could only choose converter 0 for use. Make sure the
1248 * converters are in correct power state */
1249 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1250 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1251
1252 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1253 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1254 AC_PWRST_D0);
1255 msleep(40);
1256 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1257 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1258 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1259 }
1260 }
1261
1262 /*
1263 * Callbacks
1264 */
1265
1266 /* HBR should be Non-PCM, 8 channels */
1267 #define is_hbr_format(format) \
1268 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1269
1270 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1271 bool hbr)
1272 {
1273 int pinctl, new_pinctl;
1274
1275 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1276 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1277 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1278
1279 if (pinctl < 0)
1280 return hbr ? -EINVAL : 0;
1281
1282 new_pinctl = pinctl & ~AC_PINCTL_EPT;
1283 if (hbr)
1284 new_pinctl |= AC_PINCTL_EPT_HBR;
1285 else
1286 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1287
1288 codec_dbg(codec,
1289 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1290 pin_nid,
1291 pinctl == new_pinctl ? "" : "new-",
1292 new_pinctl);
1293
1294 if (pinctl != new_pinctl)
1295 snd_hda_codec_write(codec, pin_nid, 0,
1296 AC_VERB_SET_PIN_WIDGET_CONTROL,
1297 new_pinctl);
1298 } else if (hbr)
1299 return -EINVAL;
1300
1301 return 0;
1302 }
1303
1304 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1305 hda_nid_t pin_nid, u32 stream_tag, int format)
1306 {
1307 struct hdmi_spec *spec = codec->spec;
1308 int err;
1309
1310 if (is_haswell_plus(codec))
1311 haswell_verify_D0(codec, cvt_nid, pin_nid);
1312
1313 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1314
1315 if (err) {
1316 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1317 return err;
1318 }
1319
1320 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1321 return 0;
1322 }
1323
1324 static int hdmi_choose_cvt(struct hda_codec *codec,
1325 int pin_idx, int *cvt_id, int *mux_id)
1326 {
1327 struct hdmi_spec *spec = codec->spec;
1328 struct hdmi_spec_per_pin *per_pin;
1329 struct hdmi_spec_per_cvt *per_cvt = NULL;
1330 int cvt_idx, mux_idx = 0;
1331
1332 per_pin = get_pin(spec, pin_idx);
1333
1334 /* Dynamically assign converter to stream */
1335 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1336 per_cvt = get_cvt(spec, cvt_idx);
1337
1338 /* Must not already be assigned */
1339 if (per_cvt->assigned)
1340 continue;
1341 /* Must be in pin's mux's list of converters */
1342 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1343 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1344 break;
1345 /* Not in mux list */
1346 if (mux_idx == per_pin->num_mux_nids)
1347 continue;
1348 break;
1349 }
1350
1351 /* No free converters */
1352 if (cvt_idx == spec->num_cvts)
1353 return -ENODEV;
1354
1355 per_pin->mux_idx = mux_idx;
1356
1357 if (cvt_id)
1358 *cvt_id = cvt_idx;
1359 if (mux_id)
1360 *mux_id = mux_idx;
1361
1362 return 0;
1363 }
1364
1365 /* Assure the pin select the right convetor */
1366 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1367 struct hdmi_spec_per_pin *per_pin)
1368 {
1369 hda_nid_t pin_nid = per_pin->pin_nid;
1370 int mux_idx, curr;
1371
1372 mux_idx = per_pin->mux_idx;
1373 curr = snd_hda_codec_read(codec, pin_nid, 0,
1374 AC_VERB_GET_CONNECT_SEL, 0);
1375 if (curr != mux_idx)
1376 snd_hda_codec_write_cache(codec, pin_nid, 0,
1377 AC_VERB_SET_CONNECT_SEL,
1378 mux_idx);
1379 }
1380
1381 /* Intel HDMI workaround to fix audio routing issue:
1382 * For some Intel display codecs, pins share the same connection list.
1383 * So a conveter can be selected by multiple pins and playback on any of these
1384 * pins will generate sound on the external display, because audio flows from
1385 * the same converter to the display pipeline. Also muting one pin may make
1386 * other pins have no sound output.
1387 * So this function assures that an assigned converter for a pin is not selected
1388 * by any other pins.
1389 */
1390 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1391 hda_nid_t pin_nid, int mux_idx)
1392 {
1393 struct hdmi_spec *spec = codec->spec;
1394 hda_nid_t nid, end_nid;
1395 int cvt_idx, curr;
1396 struct hdmi_spec_per_cvt *per_cvt;
1397
1398 /* configure all pins, including "no physical connection" ones */
1399 end_nid = codec->start_nid + codec->num_nodes;
1400 for (nid = codec->start_nid; nid < end_nid; nid++) {
1401 unsigned int wid_caps = get_wcaps(codec, nid);
1402 unsigned int wid_type = get_wcaps_type(wid_caps);
1403
1404 if (wid_type != AC_WID_PIN)
1405 continue;
1406
1407 if (nid == pin_nid)
1408 continue;
1409
1410 curr = snd_hda_codec_read(codec, nid, 0,
1411 AC_VERB_GET_CONNECT_SEL, 0);
1412 if (curr != mux_idx)
1413 continue;
1414
1415 /* choose an unassigned converter. The conveters in the
1416 * connection list are in the same order as in the codec.
1417 */
1418 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1419 per_cvt = get_cvt(spec, cvt_idx);
1420 if (!per_cvt->assigned) {
1421 codec_dbg(codec,
1422 "choose cvt %d for pin nid %d\n",
1423 cvt_idx, nid);
1424 snd_hda_codec_write_cache(codec, nid, 0,
1425 AC_VERB_SET_CONNECT_SEL,
1426 cvt_idx);
1427 break;
1428 }
1429 }
1430 }
1431 }
1432
1433 /*
1434 * HDA PCM callbacks
1435 */
1436 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1437 struct hda_codec *codec,
1438 struct snd_pcm_substream *substream)
1439 {
1440 struct hdmi_spec *spec = codec->spec;
1441 struct snd_pcm_runtime *runtime = substream->runtime;
1442 int pin_idx, cvt_idx, mux_idx = 0;
1443 struct hdmi_spec_per_pin *per_pin;
1444 struct hdmi_eld *eld;
1445 struct hdmi_spec_per_cvt *per_cvt = NULL;
1446 int err;
1447
1448 /* Validate hinfo */
1449 pin_idx = hinfo_to_pin_index(codec, hinfo);
1450 if (snd_BUG_ON(pin_idx < 0))
1451 return -EINVAL;
1452 per_pin = get_pin(spec, pin_idx);
1453 eld = &per_pin->sink_eld;
1454
1455 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1456 if (err < 0)
1457 return err;
1458
1459 per_cvt = get_cvt(spec, cvt_idx);
1460 /* Claim converter */
1461 per_cvt->assigned = 1;
1462 per_pin->cvt_nid = per_cvt->cvt_nid;
1463 hinfo->nid = per_cvt->cvt_nid;
1464
1465 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1466 AC_VERB_SET_CONNECT_SEL,
1467 mux_idx);
1468
1469 /* configure unused pins to choose other converters */
1470 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1471 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1472
1473 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1474
1475 /* Initially set the converter's capabilities */
1476 hinfo->channels_min = per_cvt->channels_min;
1477 hinfo->channels_max = per_cvt->channels_max;
1478 hinfo->rates = per_cvt->rates;
1479 hinfo->formats = per_cvt->formats;
1480 hinfo->maxbps = per_cvt->maxbps;
1481
1482 /* Restrict capabilities by ELD if this isn't disabled */
1483 if (!static_hdmi_pcm && eld->eld_valid) {
1484 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1485 if (hinfo->channels_min > hinfo->channels_max ||
1486 !hinfo->rates || !hinfo->formats) {
1487 per_cvt->assigned = 0;
1488 hinfo->nid = 0;
1489 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1490 return -ENODEV;
1491 }
1492 }
1493
1494 /* Store the updated parameters */
1495 runtime->hw.channels_min = hinfo->channels_min;
1496 runtime->hw.channels_max = hinfo->channels_max;
1497 runtime->hw.formats = hinfo->formats;
1498 runtime->hw.rates = hinfo->rates;
1499
1500 snd_pcm_hw_constraint_step(substream->runtime, 0,
1501 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1502 return 0;
1503 }
1504
1505 /*
1506 * HDA/HDMI auto parsing
1507 */
1508 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1509 {
1510 struct hdmi_spec *spec = codec->spec;
1511 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1512 hda_nid_t pin_nid = per_pin->pin_nid;
1513
1514 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1515 codec_warn(codec,
1516 "HDMI: pin %d wcaps %#x does not support connection list\n",
1517 pin_nid, get_wcaps(codec, pin_nid));
1518 return -EINVAL;
1519 }
1520
1521 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1522 per_pin->mux_nids,
1523 HDA_MAX_CONNECTIONS);
1524
1525 return 0;
1526 }
1527
1528 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1529 {
1530 struct hda_jack_tbl *jack;
1531 struct hda_codec *codec = per_pin->codec;
1532 struct hdmi_spec *spec = codec->spec;
1533 struct hdmi_eld *eld = &spec->temp_eld;
1534 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1535 hda_nid_t pin_nid = per_pin->pin_nid;
1536 /*
1537 * Always execute a GetPinSense verb here, even when called from
1538 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1539 * response's PD bit is not the real PD value, but indicates that
1540 * the real PD value changed. An older version of the HD-audio
1541 * specification worked this way. Hence, we just ignore the data in
1542 * the unsolicited response to avoid custom WARs.
1543 */
1544 int present;
1545 bool update_eld = false;
1546 bool eld_changed = false;
1547 bool ret;
1548
1549 snd_hda_power_up(codec);
1550 present = snd_hda_pin_sense(codec, pin_nid);
1551
1552 mutex_lock(&per_pin->lock);
1553 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1554 if (pin_eld->monitor_present)
1555 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1556 else
1557 eld->eld_valid = false;
1558
1559 codec_dbg(codec,
1560 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1561 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1562
1563 if (eld->eld_valid) {
1564 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1565 &eld->eld_size) < 0)
1566 eld->eld_valid = false;
1567 else {
1568 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1569 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1570 eld->eld_size) < 0)
1571 eld->eld_valid = false;
1572 }
1573
1574 if (eld->eld_valid) {
1575 snd_hdmi_show_eld(codec, &eld->info);
1576 update_eld = true;
1577 }
1578 else if (repoll) {
1579 queue_delayed_work(codec->bus->workq,
1580 &per_pin->work,
1581 msecs_to_jiffies(300));
1582 goto unlock;
1583 }
1584 }
1585
1586 if (pin_eld->eld_valid != eld->eld_valid)
1587 eld_changed = true;
1588
1589 if (pin_eld->eld_valid && !eld->eld_valid)
1590 update_eld = true;
1591
1592 if (update_eld) {
1593 bool old_eld_valid = pin_eld->eld_valid;
1594 pin_eld->eld_valid = eld->eld_valid;
1595 if (pin_eld->eld_size != eld->eld_size ||
1596 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1597 eld->eld_size) != 0) {
1598 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1599 eld->eld_size);
1600 eld_changed = true;
1601 }
1602 pin_eld->eld_size = eld->eld_size;
1603 pin_eld->info = eld->info;
1604
1605 /*
1606 * Re-setup pin and infoframe. This is needed e.g. when
1607 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1608 * - transcoder can change during stream playback on Haswell
1609 * and this can make HW reset converter selection on a pin.
1610 */
1611 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1612 if (is_haswell_plus(codec) ||
1613 is_valleyview_plus(codec)) {
1614 intel_verify_pin_cvt_connect(codec, per_pin);
1615 intel_not_share_assigned_cvt(codec, pin_nid,
1616 per_pin->mux_idx);
1617 }
1618
1619 hdmi_setup_audio_infoframe(codec, per_pin,
1620 per_pin->non_pcm);
1621 }
1622 }
1623
1624 if (eld_changed)
1625 snd_ctl_notify(codec->bus->card,
1626 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1627 &per_pin->eld_ctl->id);
1628 unlock:
1629 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1630
1631 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1632 if (jack)
1633 jack->block_report = !ret;
1634
1635 mutex_unlock(&per_pin->lock);
1636 snd_hda_power_down(codec);
1637 return ret;
1638 }
1639
1640 static void hdmi_repoll_eld(struct work_struct *work)
1641 {
1642 struct hdmi_spec_per_pin *per_pin =
1643 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1644
1645 if (per_pin->repoll_count++ > 6)
1646 per_pin->repoll_count = 0;
1647
1648 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1649 snd_hda_jack_report_sync(per_pin->codec);
1650 }
1651
1652 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1653 hda_nid_t nid);
1654
1655 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1656 {
1657 struct hdmi_spec *spec = codec->spec;
1658 unsigned int caps, config;
1659 int pin_idx;
1660 struct hdmi_spec_per_pin *per_pin;
1661 int err;
1662
1663 caps = snd_hda_query_pin_caps(codec, pin_nid);
1664 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1665 return 0;
1666
1667 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1668 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1669 return 0;
1670
1671 if (is_haswell_plus(codec))
1672 intel_haswell_fixup_connect_list(codec, pin_nid);
1673
1674 pin_idx = spec->num_pins;
1675 per_pin = snd_array_new(&spec->pins);
1676 if (!per_pin)
1677 return -ENOMEM;
1678
1679 per_pin->pin_nid = pin_nid;
1680 per_pin->non_pcm = false;
1681
1682 err = hdmi_read_pin_conn(codec, pin_idx);
1683 if (err < 0)
1684 return err;
1685
1686 spec->num_pins++;
1687
1688 return 0;
1689 }
1690
1691 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1692 {
1693 struct hdmi_spec *spec = codec->spec;
1694 struct hdmi_spec_per_cvt *per_cvt;
1695 unsigned int chans;
1696 int err;
1697
1698 chans = get_wcaps(codec, cvt_nid);
1699 chans = get_wcaps_channels(chans);
1700
1701 per_cvt = snd_array_new(&spec->cvts);
1702 if (!per_cvt)
1703 return -ENOMEM;
1704
1705 per_cvt->cvt_nid = cvt_nid;
1706 per_cvt->channels_min = 2;
1707 if (chans <= 16) {
1708 per_cvt->channels_max = chans;
1709 if (chans > spec->channels_max)
1710 spec->channels_max = chans;
1711 }
1712
1713 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1714 &per_cvt->rates,
1715 &per_cvt->formats,
1716 &per_cvt->maxbps);
1717 if (err < 0)
1718 return err;
1719
1720 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1721 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1722 spec->num_cvts++;
1723
1724 return 0;
1725 }
1726
1727 static int hdmi_parse_codec(struct hda_codec *codec)
1728 {
1729 hda_nid_t nid;
1730 int i, nodes;
1731
1732 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1733 if (!nid || nodes < 0) {
1734 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1735 return -EINVAL;
1736 }
1737
1738 for (i = 0; i < nodes; i++, nid++) {
1739 unsigned int caps;
1740 unsigned int type;
1741
1742 caps = get_wcaps(codec, nid);
1743 type = get_wcaps_type(caps);
1744
1745 if (!(caps & AC_WCAP_DIGITAL))
1746 continue;
1747
1748 switch (type) {
1749 case AC_WID_AUD_OUT:
1750 hdmi_add_cvt(codec, nid);
1751 break;
1752 case AC_WID_PIN:
1753 hdmi_add_pin(codec, nid);
1754 break;
1755 }
1756 }
1757
1758 return 0;
1759 }
1760
1761 /*
1762 */
1763 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1764 {
1765 struct hda_spdif_out *spdif;
1766 bool non_pcm;
1767
1768 mutex_lock(&codec->spdif_mutex);
1769 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1770 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1771 mutex_unlock(&codec->spdif_mutex);
1772 return non_pcm;
1773 }
1774
1775
1776 /*
1777 * HDMI callbacks
1778 */
1779
1780 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1781 struct hda_codec *codec,
1782 unsigned int stream_tag,
1783 unsigned int format,
1784 struct snd_pcm_substream *substream)
1785 {
1786 hda_nid_t cvt_nid = hinfo->nid;
1787 struct hdmi_spec *spec = codec->spec;
1788 int pin_idx = hinfo_to_pin_index(codec, hinfo);
1789 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1790 hda_nid_t pin_nid = per_pin->pin_nid;
1791 bool non_pcm;
1792 int pinctl;
1793
1794 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1795 /* Verify pin:cvt selections to avoid silent audio after S3.
1796 * After S3, the audio driver restores pin:cvt selections
1797 * but this can happen before gfx is ready and such selection
1798 * is overlooked by HW. Thus multiple pins can share a same
1799 * default convertor and mute control will affect each other,
1800 * which can cause a resumed audio playback become silent
1801 * after S3.
1802 */
1803 intel_verify_pin_cvt_connect(codec, per_pin);
1804 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1805 }
1806
1807 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1808 mutex_lock(&per_pin->lock);
1809 per_pin->channels = substream->runtime->channels;
1810 per_pin->setup = true;
1811
1812 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1813 mutex_unlock(&per_pin->lock);
1814
1815 if (spec->dyn_pin_out) {
1816 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1817 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1818 snd_hda_codec_write(codec, pin_nid, 0,
1819 AC_VERB_SET_PIN_WIDGET_CONTROL,
1820 pinctl | PIN_OUT);
1821 }
1822
1823 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1824 }
1825
1826 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1827 struct hda_codec *codec,
1828 struct snd_pcm_substream *substream)
1829 {
1830 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1831 return 0;
1832 }
1833
1834 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1835 struct hda_codec *codec,
1836 struct snd_pcm_substream *substream)
1837 {
1838 struct hdmi_spec *spec = codec->spec;
1839 int cvt_idx, pin_idx;
1840 struct hdmi_spec_per_cvt *per_cvt;
1841 struct hdmi_spec_per_pin *per_pin;
1842 int pinctl;
1843
1844 if (hinfo->nid) {
1845 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1846 if (snd_BUG_ON(cvt_idx < 0))
1847 return -EINVAL;
1848 per_cvt = get_cvt(spec, cvt_idx);
1849
1850 snd_BUG_ON(!per_cvt->assigned);
1851 per_cvt->assigned = 0;
1852 hinfo->nid = 0;
1853
1854 pin_idx = hinfo_to_pin_index(codec, hinfo);
1855 if (snd_BUG_ON(pin_idx < 0))
1856 return -EINVAL;
1857 per_pin = get_pin(spec, pin_idx);
1858
1859 if (spec->dyn_pin_out) {
1860 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1861 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1862 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1863 AC_VERB_SET_PIN_WIDGET_CONTROL,
1864 pinctl & ~PIN_OUT);
1865 }
1866
1867 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1868
1869 mutex_lock(&per_pin->lock);
1870 per_pin->chmap_set = false;
1871 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1872
1873 per_pin->setup = false;
1874 per_pin->channels = 0;
1875 mutex_unlock(&per_pin->lock);
1876 }
1877
1878 return 0;
1879 }
1880
1881 static const struct hda_pcm_ops generic_ops = {
1882 .open = hdmi_pcm_open,
1883 .close = hdmi_pcm_close,
1884 .prepare = generic_hdmi_playback_pcm_prepare,
1885 .cleanup = generic_hdmi_playback_pcm_cleanup,
1886 };
1887
1888 /*
1889 * ALSA API channel-map control callbacks
1890 */
1891 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1892 struct snd_ctl_elem_info *uinfo)
1893 {
1894 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1895 struct hda_codec *codec = info->private_data;
1896 struct hdmi_spec *spec = codec->spec;
1897 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1898 uinfo->count = spec->channels_max;
1899 uinfo->value.integer.min = 0;
1900 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1901 return 0;
1902 }
1903
1904 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1905 int channels)
1906 {
1907 /* If the speaker allocation matches the channel count, it is OK.*/
1908 if (cap->channels != channels)
1909 return -1;
1910
1911 /* all channels are remappable freely */
1912 return SNDRV_CTL_TLVT_CHMAP_VAR;
1913 }
1914
1915 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1916 unsigned int *chmap, int channels)
1917 {
1918 int count = 0;
1919 int c;
1920
1921 for (c = 7; c >= 0; c--) {
1922 int spk = cap->speakers[c];
1923 if (!spk)
1924 continue;
1925
1926 chmap[count++] = spk_to_chmap(spk);
1927 }
1928
1929 WARN_ON(count != channels);
1930 }
1931
1932 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1933 unsigned int size, unsigned int __user *tlv)
1934 {
1935 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1936 struct hda_codec *codec = info->private_data;
1937 struct hdmi_spec *spec = codec->spec;
1938 unsigned int __user *dst;
1939 int chs, count = 0;
1940
1941 if (size < 8)
1942 return -ENOMEM;
1943 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1944 return -EFAULT;
1945 size -= 8;
1946 dst = tlv + 2;
1947 for (chs = 2; chs <= spec->channels_max; chs++) {
1948 int i;
1949 struct cea_channel_speaker_allocation *cap;
1950 cap = channel_allocations;
1951 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1952 int chs_bytes = chs * 4;
1953 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1954 unsigned int tlv_chmap[8];
1955
1956 if (type < 0)
1957 continue;
1958 if (size < 8)
1959 return -ENOMEM;
1960 if (put_user(type, dst) ||
1961 put_user(chs_bytes, dst + 1))
1962 return -EFAULT;
1963 dst += 2;
1964 size -= 8;
1965 count += 8;
1966 if (size < chs_bytes)
1967 return -ENOMEM;
1968 size -= chs_bytes;
1969 count += chs_bytes;
1970 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1971 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1972 return -EFAULT;
1973 dst += chs;
1974 }
1975 }
1976 if (put_user(count, tlv + 1))
1977 return -EFAULT;
1978 return 0;
1979 }
1980
1981 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1982 struct snd_ctl_elem_value *ucontrol)
1983 {
1984 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1985 struct hda_codec *codec = info->private_data;
1986 struct hdmi_spec *spec = codec->spec;
1987 int pin_idx = kcontrol->private_value;
1988 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1989 int i;
1990
1991 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1992 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1993 return 0;
1994 }
1995
1996 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1997 struct snd_ctl_elem_value *ucontrol)
1998 {
1999 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2000 struct hda_codec *codec = info->private_data;
2001 struct hdmi_spec *spec = codec->spec;
2002 int pin_idx = kcontrol->private_value;
2003 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2004 unsigned int ctl_idx;
2005 struct snd_pcm_substream *substream;
2006 unsigned char chmap[8];
2007 int i, err, ca, prepared = 0;
2008
2009 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2010 substream = snd_pcm_chmap_substream(info, ctl_idx);
2011 if (!substream || !substream->runtime)
2012 return 0; /* just for avoiding error from alsactl restore */
2013 switch (substream->runtime->status->state) {
2014 case SNDRV_PCM_STATE_OPEN:
2015 case SNDRV_PCM_STATE_SETUP:
2016 break;
2017 case SNDRV_PCM_STATE_PREPARED:
2018 prepared = 1;
2019 break;
2020 default:
2021 return -EBUSY;
2022 }
2023 memset(chmap, 0, sizeof(chmap));
2024 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2025 chmap[i] = ucontrol->value.integer.value[i];
2026 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2027 return 0;
2028 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2029 if (ca < 0)
2030 return -EINVAL;
2031 if (spec->ops.chmap_validate) {
2032 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2033 if (err)
2034 return err;
2035 }
2036 mutex_lock(&per_pin->lock);
2037 per_pin->chmap_set = true;
2038 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2039 if (prepared)
2040 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2041 mutex_unlock(&per_pin->lock);
2042
2043 return 0;
2044 }
2045
2046 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2047 {
2048 struct hdmi_spec *spec = codec->spec;
2049 int pin_idx;
2050
2051 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2052 struct hda_pcm *info;
2053 struct hda_pcm_stream *pstr;
2054 struct hdmi_spec_per_pin *per_pin;
2055
2056 per_pin = get_pin(spec, pin_idx);
2057 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
2058 info = snd_array_new(&spec->pcm_rec);
2059 if (!info)
2060 return -ENOMEM;
2061 info->name = per_pin->pcm_name;
2062 info->pcm_type = HDA_PCM_TYPE_HDMI;
2063 info->own_chmap = true;
2064
2065 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2066 pstr->substreams = 1;
2067 pstr->ops = generic_ops;
2068 /* other pstr fields are set in open */
2069 }
2070
2071 codec->num_pcms = spec->num_pins;
2072 codec->pcm_info = spec->pcm_rec.list;
2073
2074 return 0;
2075 }
2076
2077 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2078 {
2079 char hdmi_str[32] = "HDMI/DP";
2080 struct hdmi_spec *spec = codec->spec;
2081 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2082 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2083
2084 if (pcmdev > 0)
2085 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2086 if (!is_jack_detectable(codec, per_pin->pin_nid))
2087 strncat(hdmi_str, " Phantom",
2088 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2089
2090 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
2091 }
2092
2093 static int generic_hdmi_build_controls(struct hda_codec *codec)
2094 {
2095 struct hdmi_spec *spec = codec->spec;
2096 int err;
2097 int pin_idx;
2098
2099 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2100 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2101
2102 err = generic_hdmi_build_jack(codec, pin_idx);
2103 if (err < 0)
2104 return err;
2105
2106 err = snd_hda_create_dig_out_ctls(codec,
2107 per_pin->pin_nid,
2108 per_pin->mux_nids[0],
2109 HDA_PCM_TYPE_HDMI);
2110 if (err < 0)
2111 return err;
2112 snd_hda_spdif_ctls_unassign(codec, pin_idx);
2113
2114 /* add control for ELD Bytes */
2115 err = hdmi_create_eld_ctl(codec, pin_idx,
2116 get_pcm_rec(spec, pin_idx)->device);
2117
2118 if (err < 0)
2119 return err;
2120
2121 hdmi_present_sense(per_pin, 0);
2122 }
2123
2124 /* add channel maps */
2125 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2126 struct snd_pcm_chmap *chmap;
2127 struct snd_kcontrol *kctl;
2128 int i;
2129
2130 if (!codec->pcm_info[pin_idx].pcm)
2131 break;
2132 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
2133 SNDRV_PCM_STREAM_PLAYBACK,
2134 NULL, 0, pin_idx, &chmap);
2135 if (err < 0)
2136 return err;
2137 /* override handlers */
2138 chmap->private_data = codec;
2139 kctl = chmap->kctl;
2140 for (i = 0; i < kctl->count; i++)
2141 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2142 kctl->info = hdmi_chmap_ctl_info;
2143 kctl->get = hdmi_chmap_ctl_get;
2144 kctl->put = hdmi_chmap_ctl_put;
2145 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2146 }
2147
2148 return 0;
2149 }
2150
2151 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2152 {
2153 struct hdmi_spec *spec = codec->spec;
2154 int pin_idx;
2155
2156 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2157 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2158
2159 per_pin->codec = codec;
2160 mutex_init(&per_pin->lock);
2161 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2162 eld_proc_new(per_pin, pin_idx);
2163 }
2164 return 0;
2165 }
2166
2167 static int generic_hdmi_init(struct hda_codec *codec)
2168 {
2169 struct hdmi_spec *spec = codec->spec;
2170 int pin_idx;
2171
2172 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2173 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2174 hda_nid_t pin_nid = per_pin->pin_nid;
2175
2176 hdmi_init_pin(codec, pin_nid);
2177 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2178 codec->jackpoll_interval > 0 ? jack_callback : NULL);
2179 }
2180 return 0;
2181 }
2182
2183 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2184 {
2185 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2186 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2187 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
2188 }
2189
2190 static void hdmi_array_free(struct hdmi_spec *spec)
2191 {
2192 snd_array_free(&spec->pins);
2193 snd_array_free(&spec->cvts);
2194 snd_array_free(&spec->pcm_rec);
2195 }
2196
2197 static void generic_hdmi_free(struct hda_codec *codec)
2198 {
2199 struct hdmi_spec *spec = codec->spec;
2200 int pin_idx;
2201
2202 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2203 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2204
2205 cancel_delayed_work(&per_pin->work);
2206 eld_proc_free(per_pin);
2207 }
2208
2209 flush_workqueue(codec->bus->workq);
2210 hdmi_array_free(spec);
2211 kfree(spec);
2212 }
2213
2214 #ifdef CONFIG_PM
2215 static int generic_hdmi_resume(struct hda_codec *codec)
2216 {
2217 struct hdmi_spec *spec = codec->spec;
2218 int pin_idx;
2219
2220 codec->patch_ops.init(codec);
2221 snd_hda_codec_resume_amp(codec);
2222 snd_hda_codec_resume_cache(codec);
2223
2224 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2225 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2226 hdmi_present_sense(per_pin, 1);
2227 }
2228 return 0;
2229 }
2230 #endif
2231
2232 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2233 .init = generic_hdmi_init,
2234 .free = generic_hdmi_free,
2235 .build_pcms = generic_hdmi_build_pcms,
2236 .build_controls = generic_hdmi_build_controls,
2237 .unsol_event = hdmi_unsol_event,
2238 #ifdef CONFIG_PM
2239 .resume = generic_hdmi_resume,
2240 #endif
2241 };
2242
2243 static const struct hdmi_ops generic_standard_hdmi_ops = {
2244 .pin_get_eld = snd_hdmi_get_eld,
2245 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2246 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2247 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2248 .pin_hbr_setup = hdmi_pin_hbr_setup,
2249 .setup_stream = hdmi_setup_stream,
2250 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2251 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2252 };
2253
2254
2255 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2256 hda_nid_t nid)
2257 {
2258 struct hdmi_spec *spec = codec->spec;
2259 hda_nid_t conns[4];
2260 int nconns;
2261
2262 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2263 if (nconns == spec->num_cvts &&
2264 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2265 return;
2266
2267 /* override pins connection list */
2268 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2269 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2270 }
2271
2272 #define INTEL_VENDOR_NID 0x08
2273 #define INTEL_GET_VENDOR_VERB 0xf81
2274 #define INTEL_SET_VENDOR_VERB 0x781
2275 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2276 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2277
2278 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2279 bool update_tree)
2280 {
2281 unsigned int vendor_param;
2282
2283 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2284 INTEL_GET_VENDOR_VERB, 0);
2285 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2286 return;
2287
2288 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2289 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2290 INTEL_SET_VENDOR_VERB, vendor_param);
2291 if (vendor_param == -1)
2292 return;
2293
2294 if (update_tree)
2295 snd_hda_codec_update_widgets(codec);
2296 }
2297
2298 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2299 {
2300 unsigned int vendor_param;
2301
2302 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2303 INTEL_GET_VENDOR_VERB, 0);
2304 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2305 return;
2306
2307 /* enable DP1.2 mode */
2308 vendor_param |= INTEL_EN_DP12;
2309 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2310 INTEL_SET_VENDOR_VERB, vendor_param);
2311 }
2312
2313 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2314 * Otherwise you may get severe h/w communication errors.
2315 */
2316 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2317 unsigned int power_state)
2318 {
2319 if (power_state == AC_PWRST_D0) {
2320 intel_haswell_enable_all_pins(codec, false);
2321 intel_haswell_fixup_enable_dp12(codec);
2322 }
2323
2324 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2325 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2326 }
2327
2328 static int patch_generic_hdmi(struct hda_codec *codec)
2329 {
2330 struct hdmi_spec *spec;
2331
2332 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2333 if (spec == NULL)
2334 return -ENOMEM;
2335
2336 spec->ops = generic_standard_hdmi_ops;
2337 codec->spec = spec;
2338 hdmi_array_init(spec, 4);
2339
2340 if (is_haswell_plus(codec)) {
2341 intel_haswell_enable_all_pins(codec, true);
2342 intel_haswell_fixup_enable_dp12(codec);
2343 }
2344
2345 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2346 codec->depop_delay = 0;
2347
2348 if (hdmi_parse_codec(codec) < 0) {
2349 codec->spec = NULL;
2350 kfree(spec);
2351 return -EINVAL;
2352 }
2353 codec->patch_ops = generic_hdmi_patch_ops;
2354 if (is_haswell_plus(codec)) {
2355 codec->patch_ops.set_power_state = haswell_set_power_state;
2356 codec->dp_mst = true;
2357 }
2358
2359 generic_hdmi_init_per_pins(codec);
2360
2361 init_channel_allocations();
2362
2363 return 0;
2364 }
2365
2366 /*
2367 * Shared non-generic implementations
2368 */
2369
2370 static int simple_playback_build_pcms(struct hda_codec *codec)
2371 {
2372 struct hdmi_spec *spec = codec->spec;
2373 struct hda_pcm *info;
2374 unsigned int chans;
2375 struct hda_pcm_stream *pstr;
2376 struct hdmi_spec_per_cvt *per_cvt;
2377
2378 per_cvt = get_cvt(spec, 0);
2379 chans = get_wcaps(codec, per_cvt->cvt_nid);
2380 chans = get_wcaps_channels(chans);
2381
2382 info = snd_array_new(&spec->pcm_rec);
2383 if (!info)
2384 return -ENOMEM;
2385 info->name = get_pin(spec, 0)->pcm_name;
2386 sprintf(info->name, "HDMI 0");
2387 info->pcm_type = HDA_PCM_TYPE_HDMI;
2388 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2389 *pstr = spec->pcm_playback;
2390 pstr->nid = per_cvt->cvt_nid;
2391 if (pstr->channels_max <= 2 && chans && chans <= 16)
2392 pstr->channels_max = chans;
2393
2394 codec->num_pcms = 1;
2395 codec->pcm_info = info;
2396
2397 return 0;
2398 }
2399
2400 /* unsolicited event for jack sensing */
2401 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2402 unsigned int res)
2403 {
2404 snd_hda_jack_set_dirty_all(codec);
2405 snd_hda_jack_report_sync(codec);
2406 }
2407
2408 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2409 * as long as spec->pins[] is set correctly
2410 */
2411 #define simple_hdmi_build_jack generic_hdmi_build_jack
2412
2413 static int simple_playback_build_controls(struct hda_codec *codec)
2414 {
2415 struct hdmi_spec *spec = codec->spec;
2416 struct hdmi_spec_per_cvt *per_cvt;
2417 int err;
2418
2419 per_cvt = get_cvt(spec, 0);
2420 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2421 per_cvt->cvt_nid,
2422 HDA_PCM_TYPE_HDMI);
2423 if (err < 0)
2424 return err;
2425 return simple_hdmi_build_jack(codec, 0);
2426 }
2427
2428 static int simple_playback_init(struct hda_codec *codec)
2429 {
2430 struct hdmi_spec *spec = codec->spec;
2431 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2432 hda_nid_t pin = per_pin->pin_nid;
2433
2434 snd_hda_codec_write(codec, pin, 0,
2435 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2436 /* some codecs require to unmute the pin */
2437 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2438 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2439 AMP_OUT_UNMUTE);
2440 snd_hda_jack_detect_enable(codec, pin);
2441 return 0;
2442 }
2443
2444 static void simple_playback_free(struct hda_codec *codec)
2445 {
2446 struct hdmi_spec *spec = codec->spec;
2447
2448 hdmi_array_free(spec);
2449 kfree(spec);
2450 }
2451
2452 /*
2453 * Nvidia specific implementations
2454 */
2455
2456 #define Nv_VERB_SET_Channel_Allocation 0xF79
2457 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2458 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2459 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2460
2461 #define nvhdmi_master_con_nid_7x 0x04
2462 #define nvhdmi_master_pin_nid_7x 0x05
2463
2464 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2465 /*front, rear, clfe, rear_surr */
2466 0x6, 0x8, 0xa, 0xc,
2467 };
2468
2469 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2470 /* set audio protect on */
2471 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2472 /* enable digital output on pin widget */
2473 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2474 {} /* terminator */
2475 };
2476
2477 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2478 /* set audio protect on */
2479 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2480 /* enable digital output on pin widget */
2481 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2482 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2483 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2484 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2485 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2486 {} /* terminator */
2487 };
2488
2489 #ifdef LIMITED_RATE_FMT_SUPPORT
2490 /* support only the safe format and rate */
2491 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2492 #define SUPPORTED_MAXBPS 16
2493 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2494 #else
2495 /* support all rates and formats */
2496 #define SUPPORTED_RATES \
2497 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2498 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2499 SNDRV_PCM_RATE_192000)
2500 #define SUPPORTED_MAXBPS 24
2501 #define SUPPORTED_FORMATS \
2502 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2503 #endif
2504
2505 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2506 {
2507 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2508 return 0;
2509 }
2510
2511 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2512 {
2513 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2514 return 0;
2515 }
2516
2517 static unsigned int channels_2_6_8[] = {
2518 2, 6, 8
2519 };
2520
2521 static unsigned int channels_2_8[] = {
2522 2, 8
2523 };
2524
2525 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2526 .count = ARRAY_SIZE(channels_2_6_8),
2527 .list = channels_2_6_8,
2528 .mask = 0,
2529 };
2530
2531 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2532 .count = ARRAY_SIZE(channels_2_8),
2533 .list = channels_2_8,
2534 .mask = 0,
2535 };
2536
2537 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2538 struct hda_codec *codec,
2539 struct snd_pcm_substream *substream)
2540 {
2541 struct hdmi_spec *spec = codec->spec;
2542 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2543
2544 switch (codec->preset->id) {
2545 case 0x10de0002:
2546 case 0x10de0003:
2547 case 0x10de0005:
2548 case 0x10de0006:
2549 hw_constraints_channels = &hw_constraints_2_8_channels;
2550 break;
2551 case 0x10de0007:
2552 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2553 break;
2554 default:
2555 break;
2556 }
2557
2558 if (hw_constraints_channels != NULL) {
2559 snd_pcm_hw_constraint_list(substream->runtime, 0,
2560 SNDRV_PCM_HW_PARAM_CHANNELS,
2561 hw_constraints_channels);
2562 } else {
2563 snd_pcm_hw_constraint_step(substream->runtime, 0,
2564 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2565 }
2566
2567 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2568 }
2569
2570 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2571 struct hda_codec *codec,
2572 struct snd_pcm_substream *substream)
2573 {
2574 struct hdmi_spec *spec = codec->spec;
2575 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2576 }
2577
2578 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2579 struct hda_codec *codec,
2580 unsigned int stream_tag,
2581 unsigned int format,
2582 struct snd_pcm_substream *substream)
2583 {
2584 struct hdmi_spec *spec = codec->spec;
2585 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2586 stream_tag, format, substream);
2587 }
2588
2589 static const struct hda_pcm_stream simple_pcm_playback = {
2590 .substreams = 1,
2591 .channels_min = 2,
2592 .channels_max = 2,
2593 .ops = {
2594 .open = simple_playback_pcm_open,
2595 .close = simple_playback_pcm_close,
2596 .prepare = simple_playback_pcm_prepare
2597 },
2598 };
2599
2600 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2601 .build_controls = simple_playback_build_controls,
2602 .build_pcms = simple_playback_build_pcms,
2603 .init = simple_playback_init,
2604 .free = simple_playback_free,
2605 .unsol_event = simple_hdmi_unsol_event,
2606 };
2607
2608 static int patch_simple_hdmi(struct hda_codec *codec,
2609 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2610 {
2611 struct hdmi_spec *spec;
2612 struct hdmi_spec_per_cvt *per_cvt;
2613 struct hdmi_spec_per_pin *per_pin;
2614
2615 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2616 if (!spec)
2617 return -ENOMEM;
2618
2619 codec->spec = spec;
2620 hdmi_array_init(spec, 1);
2621
2622 spec->multiout.num_dacs = 0; /* no analog */
2623 spec->multiout.max_channels = 2;
2624 spec->multiout.dig_out_nid = cvt_nid;
2625 spec->num_cvts = 1;
2626 spec->num_pins = 1;
2627 per_pin = snd_array_new(&spec->pins);
2628 per_cvt = snd_array_new(&spec->cvts);
2629 if (!per_pin || !per_cvt) {
2630 simple_playback_free(codec);
2631 return -ENOMEM;
2632 }
2633 per_cvt->cvt_nid = cvt_nid;
2634 per_pin->pin_nid = pin_nid;
2635 spec->pcm_playback = simple_pcm_playback;
2636
2637 codec->patch_ops = simple_hdmi_patch_ops;
2638
2639 return 0;
2640 }
2641
2642 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2643 int channels)
2644 {
2645 unsigned int chanmask;
2646 int chan = channels ? (channels - 1) : 1;
2647
2648 switch (channels) {
2649 default:
2650 case 0:
2651 case 2:
2652 chanmask = 0x00;
2653 break;
2654 case 4:
2655 chanmask = 0x08;
2656 break;
2657 case 6:
2658 chanmask = 0x0b;
2659 break;
2660 case 8:
2661 chanmask = 0x13;
2662 break;
2663 }
2664
2665 /* Set the audio infoframe channel allocation and checksum fields. The
2666 * channel count is computed implicitly by the hardware. */
2667 snd_hda_codec_write(codec, 0x1, 0,
2668 Nv_VERB_SET_Channel_Allocation, chanmask);
2669
2670 snd_hda_codec_write(codec, 0x1, 0,
2671 Nv_VERB_SET_Info_Frame_Checksum,
2672 (0x71 - chan - chanmask));
2673 }
2674
2675 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2676 struct hda_codec *codec,
2677 struct snd_pcm_substream *substream)
2678 {
2679 struct hdmi_spec *spec = codec->spec;
2680 int i;
2681
2682 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2683 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2684 for (i = 0; i < 4; i++) {
2685 /* set the stream id */
2686 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2687 AC_VERB_SET_CHANNEL_STREAMID, 0);
2688 /* set the stream format */
2689 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2690 AC_VERB_SET_STREAM_FORMAT, 0);
2691 }
2692
2693 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2694 * streams are disabled. */
2695 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2696
2697 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2698 }
2699
2700 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2701 struct hda_codec *codec,
2702 unsigned int stream_tag,
2703 unsigned int format,
2704 struct snd_pcm_substream *substream)
2705 {
2706 int chs;
2707 unsigned int dataDCC2, channel_id;
2708 int i;
2709 struct hdmi_spec *spec = codec->spec;
2710 struct hda_spdif_out *spdif;
2711 struct hdmi_spec_per_cvt *per_cvt;
2712
2713 mutex_lock(&codec->spdif_mutex);
2714 per_cvt = get_cvt(spec, 0);
2715 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2716
2717 chs = substream->runtime->channels;
2718
2719 dataDCC2 = 0x2;
2720
2721 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2722 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2723 snd_hda_codec_write(codec,
2724 nvhdmi_master_con_nid_7x,
2725 0,
2726 AC_VERB_SET_DIGI_CONVERT_1,
2727 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2728
2729 /* set the stream id */
2730 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2731 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2732
2733 /* set the stream format */
2734 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2735 AC_VERB_SET_STREAM_FORMAT, format);
2736
2737 /* turn on again (if needed) */
2738 /* enable and set the channel status audio/data flag */
2739 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2740 snd_hda_codec_write(codec,
2741 nvhdmi_master_con_nid_7x,
2742 0,
2743 AC_VERB_SET_DIGI_CONVERT_1,
2744 spdif->ctls & 0xff);
2745 snd_hda_codec_write(codec,
2746 nvhdmi_master_con_nid_7x,
2747 0,
2748 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2749 }
2750
2751 for (i = 0; i < 4; i++) {
2752 if (chs == 2)
2753 channel_id = 0;
2754 else
2755 channel_id = i * 2;
2756
2757 /* turn off SPDIF once;
2758 *otherwise the IEC958 bits won't be updated
2759 */
2760 if (codec->spdif_status_reset &&
2761 (spdif->ctls & AC_DIG1_ENABLE))
2762 snd_hda_codec_write(codec,
2763 nvhdmi_con_nids_7x[i],
2764 0,
2765 AC_VERB_SET_DIGI_CONVERT_1,
2766 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2767 /* set the stream id */
2768 snd_hda_codec_write(codec,
2769 nvhdmi_con_nids_7x[i],
2770 0,
2771 AC_VERB_SET_CHANNEL_STREAMID,
2772 (stream_tag << 4) | channel_id);
2773 /* set the stream format */
2774 snd_hda_codec_write(codec,
2775 nvhdmi_con_nids_7x[i],
2776 0,
2777 AC_VERB_SET_STREAM_FORMAT,
2778 format);
2779 /* turn on again (if needed) */
2780 /* enable and set the channel status audio/data flag */
2781 if (codec->spdif_status_reset &&
2782 (spdif->ctls & AC_DIG1_ENABLE)) {
2783 snd_hda_codec_write(codec,
2784 nvhdmi_con_nids_7x[i],
2785 0,
2786 AC_VERB_SET_DIGI_CONVERT_1,
2787 spdif->ctls & 0xff);
2788 snd_hda_codec_write(codec,
2789 nvhdmi_con_nids_7x[i],
2790 0,
2791 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2792 }
2793 }
2794
2795 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2796
2797 mutex_unlock(&codec->spdif_mutex);
2798 return 0;
2799 }
2800
2801 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2802 .substreams = 1,
2803 .channels_min = 2,
2804 .channels_max = 8,
2805 .nid = nvhdmi_master_con_nid_7x,
2806 .rates = SUPPORTED_RATES,
2807 .maxbps = SUPPORTED_MAXBPS,
2808 .formats = SUPPORTED_FORMATS,
2809 .ops = {
2810 .open = simple_playback_pcm_open,
2811 .close = nvhdmi_8ch_7x_pcm_close,
2812 .prepare = nvhdmi_8ch_7x_pcm_prepare
2813 },
2814 };
2815
2816 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2817 {
2818 struct hdmi_spec *spec;
2819 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2820 nvhdmi_master_pin_nid_7x);
2821 if (err < 0)
2822 return err;
2823
2824 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2825 /* override the PCM rates, etc, as the codec doesn't give full list */
2826 spec = codec->spec;
2827 spec->pcm_playback.rates = SUPPORTED_RATES;
2828 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2829 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2830 return 0;
2831 }
2832
2833 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2834 {
2835 struct hdmi_spec *spec = codec->spec;
2836 int err = simple_playback_build_pcms(codec);
2837 if (!err) {
2838 struct hda_pcm *info = get_pcm_rec(spec, 0);
2839 info->own_chmap = true;
2840 }
2841 return err;
2842 }
2843
2844 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2845 {
2846 struct hdmi_spec *spec = codec->spec;
2847 struct hda_pcm *info;
2848 struct snd_pcm_chmap *chmap;
2849 int err;
2850
2851 err = simple_playback_build_controls(codec);
2852 if (err < 0)
2853 return err;
2854
2855 /* add channel maps */
2856 info = get_pcm_rec(spec, 0);
2857 err = snd_pcm_add_chmap_ctls(info->pcm,
2858 SNDRV_PCM_STREAM_PLAYBACK,
2859 snd_pcm_alt_chmaps, 8, 0, &chmap);
2860 if (err < 0)
2861 return err;
2862 switch (codec->preset->id) {
2863 case 0x10de0002:
2864 case 0x10de0003:
2865 case 0x10de0005:
2866 case 0x10de0006:
2867 chmap->channel_mask = (1U << 2) | (1U << 8);
2868 break;
2869 case 0x10de0007:
2870 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2871 }
2872 return 0;
2873 }
2874
2875 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2876 {
2877 struct hdmi_spec *spec;
2878 int err = patch_nvhdmi_2ch(codec);
2879 if (err < 0)
2880 return err;
2881 spec = codec->spec;
2882 spec->multiout.max_channels = 8;
2883 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2884 codec->patch_ops.init = nvhdmi_7x_init_8ch;
2885 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2886 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2887
2888 /* Initialize the audio infoframe channel mask and checksum to something
2889 * valid */
2890 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2891
2892 return 0;
2893 }
2894
2895 /*
2896 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2897 * - 0x10de0015
2898 * - 0x10de0040
2899 */
2900 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2901 int channels)
2902 {
2903 if (cap->ca_index == 0x00 && channels == 2)
2904 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2905
2906 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2907 }
2908
2909 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2910 {
2911 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2912 return -EINVAL;
2913
2914 return 0;
2915 }
2916
2917 static int patch_nvhdmi(struct hda_codec *codec)
2918 {
2919 struct hdmi_spec *spec;
2920 int err;
2921
2922 err = patch_generic_hdmi(codec);
2923 if (err)
2924 return err;
2925
2926 spec = codec->spec;
2927 spec->dyn_pin_out = true;
2928
2929 spec->ops.chmap_cea_alloc_validate_get_type =
2930 nvhdmi_chmap_cea_alloc_validate_get_type;
2931 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2932
2933 return 0;
2934 }
2935
2936 /*
2937 * ATI/AMD-specific implementations
2938 */
2939
2940 #define is_amdhdmi_rev3_or_later(codec) \
2941 ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300)
2942 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2943
2944 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2945 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2946 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
2947 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
2948 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
2949 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
2950 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
2951 #define ATI_VERB_SET_HBR_CONTROL 0x77c
2952 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
2953 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
2954 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
2955 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
2956 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2957 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2958 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2959 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2960 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2961 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2962 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
2963 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
2964 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2965 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2966 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2967 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2968 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2969
2970 /* AMD specific HDA cvt verbs */
2971 #define ATI_VERB_SET_RAMP_RATE 0x770
2972 #define ATI_VERB_GET_RAMP_RATE 0xf70
2973
2974 #define ATI_OUT_ENABLE 0x1
2975
2976 #define ATI_MULTICHANNEL_MODE_PAIRED 0
2977 #define ATI_MULTICHANNEL_MODE_SINGLE 1
2978
2979 #define ATI_HBR_CAPABLE 0x01
2980 #define ATI_HBR_ENABLE 0x10
2981
2982 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
2983 unsigned char *buf, int *eld_size)
2984 {
2985 /* call hda_eld.c ATI/AMD-specific function */
2986 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
2987 is_amdhdmi_rev3_or_later(codec));
2988 }
2989
2990 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
2991 int active_channels, int conn_type)
2992 {
2993 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
2994 }
2995
2996 static int atihdmi_paired_swap_fc_lfe(int pos)
2997 {
2998 /*
2999 * ATI/AMD have automatic FC/LFE swap built-in
3000 * when in pairwise mapping mode.
3001 */
3002
3003 switch (pos) {
3004 /* see channel_allocations[].speakers[] */
3005 case 2: return 3;
3006 case 3: return 2;
3007 default: break;
3008 }
3009
3010 return pos;
3011 }
3012
3013 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3014 {
3015 struct cea_channel_speaker_allocation *cap;
3016 int i, j;
3017
3018 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3019
3020 cap = &channel_allocations[get_channel_allocation_order(ca)];
3021 for (i = 0; i < chs; ++i) {
3022 int mask = to_spk_mask(map[i]);
3023 bool ok = false;
3024 bool companion_ok = false;
3025
3026 if (!mask)
3027 continue;
3028
3029 for (j = 0 + i % 2; j < 8; j += 2) {
3030 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3031 if (cap->speakers[chan_idx] == mask) {
3032 /* channel is in a supported position */
3033 ok = true;
3034
3035 if (i % 2 == 0 && i + 1 < chs) {
3036 /* even channel, check the odd companion */
3037 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3038 int comp_mask_req = to_spk_mask(map[i+1]);
3039 int comp_mask_act = cap->speakers[comp_chan_idx];
3040
3041 if (comp_mask_req == comp_mask_act)
3042 companion_ok = true;
3043 else
3044 return -EINVAL;
3045 }
3046 break;
3047 }
3048 }
3049
3050 if (!ok)
3051 return -EINVAL;
3052
3053 if (companion_ok)
3054 i++; /* companion channel already checked */
3055 }
3056
3057 return 0;
3058 }
3059
3060 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3061 int hdmi_slot, int stream_channel)
3062 {
3063 int verb;
3064 int ati_channel_setup = 0;
3065
3066 if (hdmi_slot > 7)
3067 return -EINVAL;
3068
3069 if (!has_amd_full_remap_support(codec)) {
3070 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3071
3072 /* In case this is an odd slot but without stream channel, do not
3073 * disable the slot since the corresponding even slot could have a
3074 * channel. In case neither have a channel, the slot pair will be
3075 * disabled when this function is called for the even slot. */
3076 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3077 return 0;
3078
3079 hdmi_slot -= hdmi_slot % 2;
3080
3081 if (stream_channel != 0xf)
3082 stream_channel -= stream_channel % 2;
3083 }
3084
3085 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3086
3087 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3088
3089 if (stream_channel != 0xf)
3090 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3091
3092 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3093 }
3094
3095 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3096 int asp_slot)
3097 {
3098 bool was_odd = false;
3099 int ati_asp_slot = asp_slot;
3100 int verb;
3101 int ati_channel_setup;
3102
3103 if (asp_slot > 7)
3104 return -EINVAL;
3105
3106 if (!has_amd_full_remap_support(codec)) {
3107 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3108 if (ati_asp_slot % 2 != 0) {
3109 ati_asp_slot -= 1;
3110 was_odd = true;
3111 }
3112 }
3113
3114 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3115
3116 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3117
3118 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3119 return 0xf;
3120
3121 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3122 }
3123
3124 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3125 int channels)
3126 {
3127 int c;
3128
3129 /*
3130 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3131 * we need to take that into account (a single channel may take 2
3132 * channel slots if we need to carry a silent channel next to it).
3133 * On Rev3+ AMD codecs this function is not used.
3134 */
3135 int chanpairs = 0;
3136
3137 /* We only produce even-numbered channel count TLVs */
3138 if ((channels % 2) != 0)
3139 return -1;
3140
3141 for (c = 0; c < 7; c += 2) {
3142 if (cap->speakers[c] || cap->speakers[c+1])
3143 chanpairs++;
3144 }
3145
3146 if (chanpairs * 2 != channels)
3147 return -1;
3148
3149 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3150 }
3151
3152 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3153 unsigned int *chmap, int channels)
3154 {
3155 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3156 int count = 0;
3157 int c;
3158
3159 for (c = 7; c >= 0; c--) {
3160 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3161 int spk = cap->speakers[chan];
3162 if (!spk) {
3163 /* add N/A channel if the companion channel is occupied */
3164 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3165 chmap[count++] = SNDRV_CHMAP_NA;
3166
3167 continue;
3168 }
3169
3170 chmap[count++] = spk_to_chmap(spk);
3171 }
3172
3173 WARN_ON(count != channels);
3174 }
3175
3176 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3177 bool hbr)
3178 {
3179 int hbr_ctl, hbr_ctl_new;
3180
3181 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3182 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3183 if (hbr)
3184 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3185 else
3186 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3187
3188 codec_dbg(codec,
3189 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3190 pin_nid,
3191 hbr_ctl == hbr_ctl_new ? "" : "new-",
3192 hbr_ctl_new);
3193
3194 if (hbr_ctl != hbr_ctl_new)
3195 snd_hda_codec_write(codec, pin_nid, 0,
3196 ATI_VERB_SET_HBR_CONTROL,
3197 hbr_ctl_new);
3198
3199 } else if (hbr)
3200 return -EINVAL;
3201
3202 return 0;
3203 }
3204
3205 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3206 hda_nid_t pin_nid, u32 stream_tag, int format)
3207 {
3208
3209 if (is_amdhdmi_rev3_or_later(codec)) {
3210 int ramp_rate = 180; /* default as per AMD spec */
3211 /* disable ramp-up/down for non-pcm as per AMD spec */
3212 if (format & AC_FMT_TYPE_NON_PCM)
3213 ramp_rate = 0;
3214
3215 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3216 }
3217
3218 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3219 }
3220
3221
3222 static int atihdmi_init(struct hda_codec *codec)
3223 {
3224 struct hdmi_spec *spec = codec->spec;
3225 int pin_idx, err;
3226
3227 err = generic_hdmi_init(codec);
3228
3229 if (err)
3230 return err;
3231
3232 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3233 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3234
3235 /* make sure downmix information in infoframe is zero */
3236 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3237
3238 /* enable channel-wise remap mode if supported */
3239 if (has_amd_full_remap_support(codec))
3240 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3241 ATI_VERB_SET_MULTICHANNEL_MODE,
3242 ATI_MULTICHANNEL_MODE_SINGLE);
3243 }
3244
3245 return 0;
3246 }
3247
3248 static int patch_atihdmi(struct hda_codec *codec)
3249 {
3250 struct hdmi_spec *spec;
3251 struct hdmi_spec_per_cvt *per_cvt;
3252 int err, cvt_idx;
3253
3254 err = patch_generic_hdmi(codec);
3255
3256 if (err)
3257 return err;
3258
3259 codec->patch_ops.init = atihdmi_init;
3260
3261 spec = codec->spec;
3262
3263 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3264 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3265 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3266 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3267 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3268 spec->ops.setup_stream = atihdmi_setup_stream;
3269
3270 if (!has_amd_full_remap_support(codec)) {
3271 /* override to ATI/AMD-specific versions with pairwise mapping */
3272 spec->ops.chmap_cea_alloc_validate_get_type =
3273 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3274 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3275 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3276 }
3277
3278 /* ATI/AMD converters do not advertise all of their capabilities */
3279 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3280 per_cvt = get_cvt(spec, cvt_idx);
3281 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3282 per_cvt->rates |= SUPPORTED_RATES;
3283 per_cvt->formats |= SUPPORTED_FORMATS;
3284 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3285 }
3286
3287 spec->channels_max = max(spec->channels_max, 8u);
3288
3289 return 0;
3290 }
3291
3292 /* VIA HDMI Implementation */
3293 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3294 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3295
3296 static int patch_via_hdmi(struct hda_codec *codec)
3297 {
3298 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3299 }
3300
3301 /*
3302 * called from hda_codec.c for generic HDMI support
3303 */
3304 int snd_hda_parse_hdmi_codec(struct hda_codec *codec)
3305 {
3306 return patch_generic_hdmi(codec);
3307 }
3308 EXPORT_SYMBOL_GPL(snd_hda_parse_hdmi_codec);
3309
3310 /*
3311 * patch entries
3312 */
3313 static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
3314 { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3315 { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3316 { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
3317 { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
3318 { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3319 { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3320 { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3321 { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3322 { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3323 { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3324 { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3325 { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
3326 { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
3327 { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
3328 { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi },
3329 { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
3330 { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
3331 { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
3332 { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
3333 { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
3334 { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
3335 { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
3336 { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
3337 /* 17 is known to be absent */
3338 { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
3339 { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
3340 { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
3341 { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
3342 { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
3343 { .id = 0x10de0028, .name = "Tegra12x HDMI", .patch = patch_nvhdmi },
3344 { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
3345 { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
3346 { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
3347 { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
3348 { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
3349 { .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
3350 { .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
3351 { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3352 { .id = 0x10de0070, .name = "GPU 70 HDMI/DP", .patch = patch_nvhdmi },
3353 { .id = 0x10de0071, .name = "GPU 71 HDMI/DP", .patch = patch_nvhdmi },
3354 { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3355 { .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3356 { .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3357 { .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3358 { .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3359 { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3360 { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3361 { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3362 { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3363 { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3364 { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
3365 { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
3366 { .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
3367 { .id = 0x80862808, .name = "Broadwell HDMI", .patch = patch_generic_hdmi },
3368 { .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
3369 { .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
3370 { .id = 0x80862883, .name = "Braswell HDMI", .patch = patch_generic_hdmi },
3371 { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3372 {} /* terminator */
3373 };
3374
3375 MODULE_ALIAS("snd-hda-codec-id:1002793c");
3376 MODULE_ALIAS("snd-hda-codec-id:10027919");
3377 MODULE_ALIAS("snd-hda-codec-id:1002791a");
3378 MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3379 MODULE_ALIAS("snd-hda-codec-id:10951390");
3380 MODULE_ALIAS("snd-hda-codec-id:10951392");
3381 MODULE_ALIAS("snd-hda-codec-id:10de0002");
3382 MODULE_ALIAS("snd-hda-codec-id:10de0003");
3383 MODULE_ALIAS("snd-hda-codec-id:10de0005");
3384 MODULE_ALIAS("snd-hda-codec-id:10de0006");
3385 MODULE_ALIAS("snd-hda-codec-id:10de0007");
3386 MODULE_ALIAS("snd-hda-codec-id:10de000a");
3387 MODULE_ALIAS("snd-hda-codec-id:10de000b");
3388 MODULE_ALIAS("snd-hda-codec-id:10de000c");
3389 MODULE_ALIAS("snd-hda-codec-id:10de000d");
3390 MODULE_ALIAS("snd-hda-codec-id:10de0010");
3391 MODULE_ALIAS("snd-hda-codec-id:10de0011");
3392 MODULE_ALIAS("snd-hda-codec-id:10de0012");
3393 MODULE_ALIAS("snd-hda-codec-id:10de0013");
3394 MODULE_ALIAS("snd-hda-codec-id:10de0014");
3395 MODULE_ALIAS("snd-hda-codec-id:10de0015");
3396 MODULE_ALIAS("snd-hda-codec-id:10de0016");
3397 MODULE_ALIAS("snd-hda-codec-id:10de0018");
3398 MODULE_ALIAS("snd-hda-codec-id:10de0019");
3399 MODULE_ALIAS("snd-hda-codec-id:10de001a");
3400 MODULE_ALIAS("snd-hda-codec-id:10de001b");
3401 MODULE_ALIAS("snd-hda-codec-id:10de001c");
3402 MODULE_ALIAS("snd-hda-codec-id:10de0028");
3403 MODULE_ALIAS("snd-hda-codec-id:10de0040");
3404 MODULE_ALIAS("snd-hda-codec-id:10de0041");
3405 MODULE_ALIAS("snd-hda-codec-id:10de0042");
3406 MODULE_ALIAS("snd-hda-codec-id:10de0043");
3407 MODULE_ALIAS("snd-hda-codec-id:10de0044");
3408 MODULE_ALIAS("snd-hda-codec-id:10de0051");
3409 MODULE_ALIAS("snd-hda-codec-id:10de0060");
3410 MODULE_ALIAS("snd-hda-codec-id:10de0067");
3411 MODULE_ALIAS("snd-hda-codec-id:10de0070");
3412 MODULE_ALIAS("snd-hda-codec-id:10de0071");
3413 MODULE_ALIAS("snd-hda-codec-id:10de8001");
3414 MODULE_ALIAS("snd-hda-codec-id:11069f80");
3415 MODULE_ALIAS("snd-hda-codec-id:11069f81");
3416 MODULE_ALIAS("snd-hda-codec-id:11069f84");
3417 MODULE_ALIAS("snd-hda-codec-id:11069f85");
3418 MODULE_ALIAS("snd-hda-codec-id:17e80047");
3419 MODULE_ALIAS("snd-hda-codec-id:80860054");
3420 MODULE_ALIAS("snd-hda-codec-id:80862801");
3421 MODULE_ALIAS("snd-hda-codec-id:80862802");
3422 MODULE_ALIAS("snd-hda-codec-id:80862803");
3423 MODULE_ALIAS("snd-hda-codec-id:80862804");
3424 MODULE_ALIAS("snd-hda-codec-id:80862805");
3425 MODULE_ALIAS("snd-hda-codec-id:80862806");
3426 MODULE_ALIAS("snd-hda-codec-id:80862807");
3427 MODULE_ALIAS("snd-hda-codec-id:80862808");
3428 MODULE_ALIAS("snd-hda-codec-id:80862880");
3429 MODULE_ALIAS("snd-hda-codec-id:80862882");
3430 MODULE_ALIAS("snd-hda-codec-id:80862883");
3431 MODULE_ALIAS("snd-hda-codec-id:808629fb");
3432
3433 MODULE_LICENSE("GPL");
3434 MODULE_DESCRIPTION("HDMI HD-audio codec");
3435 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3436 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3437 MODULE_ALIAS("snd-hda-codec-atihdmi");
3438
3439 static struct hda_codec_preset_list intel_list = {
3440 .preset = snd_hda_preset_hdmi,
3441 .owner = THIS_MODULE,
3442 };
3443
3444 static int __init patch_hdmi_init(void)
3445 {
3446 return snd_hda_add_codec_preset(&intel_list);
3447 }
3448
3449 static void __exit patch_hdmi_exit(void)
3450 {
3451 snd_hda_delete_codec_preset(&intel_list);
3452 }
3453
3454 module_init(patch_hdmi_init)
3455 module_exit(patch_hdmi_exit)
Linux kernel - Deliverables
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