projects / deliverable / linux.git / blob
? search:


cd9b0ffc91dc555148df8b9b6fd00db7f7e0126c
[deliverable/linux.git] / sound / pci / hda / patch_hdmi.c
1 /*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include <sound/hdaudio.h>
41 #include <sound/hda_i915.h>
42 #include "hda_codec.h"
43 #include "hda_local.h"
44 #include "hda_jack.h"
45
46 static bool static_hdmi_pcm;
47 module_param(static_hdmi_pcm, bool, 0644);
48 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
49
50 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
51 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
52 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
53 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
54 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
55 || is_skylake(codec) || is_broxton(codec))
56
57 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
58 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
59 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
60
61 struct hdmi_spec_per_cvt {
62 hda_nid_t cvt_nid;
63 int assigned;
64 unsigned int channels_min;
65 unsigned int channels_max;
66 u32 rates;
67 u64 formats;
68 unsigned int maxbps;
69 };
70
71 /* max. connections to a widget */
72 #define HDA_MAX_CONNECTIONS 32
73
74 struct hdmi_spec_per_pin {
75 hda_nid_t pin_nid;
76 int num_mux_nids;
77 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
78 int mux_idx;
79 hda_nid_t cvt_nid;
80
81 struct hda_codec *codec;
82 struct hdmi_eld sink_eld;
83 struct mutex lock;
84 struct delayed_work work;
85 struct snd_kcontrol *eld_ctl;
86 struct snd_jack *acomp_jack; /* jack via audio component */
87 int repoll_count;
88 bool setup; /* the stream has been set up by prepare callback */
89 int channels; /* current number of channels */
90 bool non_pcm;
91 bool chmap_set; /* channel-map override by ALSA API? */
92 unsigned char chmap[8]; /* ALSA API channel-map */
93 #ifdef CONFIG_SND_PROC_FS
94 struct snd_info_entry *proc_entry;
95 #endif
96 };
97
98 struct cea_channel_speaker_allocation;
99
100 /* operations used by generic code that can be overridden by patches */
101 struct hdmi_ops {
102 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
103 unsigned char *buf, int *eld_size);
104
105 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
106 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
107 int asp_slot);
108 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
109 int asp_slot, int channel);
110
111 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
112 int ca, int active_channels, int conn_type);
113
114 /* enable/disable HBR (HD passthrough) */
115 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
116
117 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
118 hda_nid_t pin_nid, u32 stream_tag, int format);
119
120 /* Helpers for producing the channel map TLVs. These can be overridden
121 * for devices that have non-standard mapping requirements. */
122 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
123 int channels);
124 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
125 unsigned int *chmap, int channels);
126
127 /* check that the user-given chmap is supported */
128 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
129 };
130
131 struct hdmi_spec {
132 int num_cvts;
133 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
134 hda_nid_t cvt_nids[4]; /* only for haswell fix */
135
136 int num_pins;
137 struct snd_array pins; /* struct hdmi_spec_per_pin */
138 struct hda_pcm *pcm_rec[16];
139 unsigned int channels_max; /* max over all cvts */
140
141 struct hdmi_eld temp_eld;
142 struct hdmi_ops ops;
143
144 bool dyn_pin_out;
145
146 /*
147 * Non-generic VIA/NVIDIA specific
148 */
149 struct hda_multi_out multiout;
150 struct hda_pcm_stream pcm_playback;
151
152 /* i915/powerwell (Haswell+/Valleyview+) specific */
153 struct i915_audio_component_audio_ops i915_audio_ops;
154 bool i915_bound; /* was i915 bound in this driver? */
155 };
156
157 #ifdef CONFIG_SND_HDA_I915
158 #define codec_has_acomp(codec) \
159 ((codec)->bus->core.audio_component != NULL)
160 #else
161 #define codec_has_acomp(codec) false
162 #endif
163
164 struct hdmi_audio_infoframe {
165 u8 type; /* 0x84 */
166 u8 ver; /* 0x01 */
167 u8 len; /* 0x0a */
168
169 u8 checksum;
170
171 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
172 u8 SS01_SF24;
173 u8 CXT04;
174 u8 CA;
175 u8 LFEPBL01_LSV36_DM_INH7;
176 };
177
178 struct dp_audio_infoframe {
179 u8 type; /* 0x84 */
180 u8 len; /* 0x1b */
181 u8 ver; /* 0x11 << 2 */
182
183 u8 CC02_CT47; /* match with HDMI infoframe from this on */
184 u8 SS01_SF24;
185 u8 CXT04;
186 u8 CA;
187 u8 LFEPBL01_LSV36_DM_INH7;
188 };
189
190 union audio_infoframe {
191 struct hdmi_audio_infoframe hdmi;
192 struct dp_audio_infoframe dp;
193 u8 bytes[0];
194 };
195
196 /*
197 * CEA speaker placement:
198 *
199 * FLH FCH FRH
200 * FLW FL FLC FC FRC FR FRW
201 *
202 * LFE
203 * TC
204 *
205 * RL RLC RC RRC RR
206 *
207 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
208 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
209 */
210 enum cea_speaker_placement {
211 FL = (1 << 0), /* Front Left */
212 FC = (1 << 1), /* Front Center */
213 FR = (1 << 2), /* Front Right */
214 FLC = (1 << 3), /* Front Left Center */
215 FRC = (1 << 4), /* Front Right Center */
216 RL = (1 << 5), /* Rear Left */
217 RC = (1 << 6), /* Rear Center */
218 RR = (1 << 7), /* Rear Right */
219 RLC = (1 << 8), /* Rear Left Center */
220 RRC = (1 << 9), /* Rear Right Center */
221 LFE = (1 << 10), /* Low Frequency Effect */
222 FLW = (1 << 11), /* Front Left Wide */
223 FRW = (1 << 12), /* Front Right Wide */
224 FLH = (1 << 13), /* Front Left High */
225 FCH = (1 << 14), /* Front Center High */
226 FRH = (1 << 15), /* Front Right High */
227 TC = (1 << 16), /* Top Center */
228 };
229
230 /*
231 * ELD SA bits in the CEA Speaker Allocation data block
232 */
233 static int eld_speaker_allocation_bits[] = {
234 [0] = FL | FR,
235 [1] = LFE,
236 [2] = FC,
237 [3] = RL | RR,
238 [4] = RC,
239 [5] = FLC | FRC,
240 [6] = RLC | RRC,
241 /* the following are not defined in ELD yet */
242 [7] = FLW | FRW,
243 [8] = FLH | FRH,
244 [9] = TC,
245 [10] = FCH,
246 };
247
248 struct cea_channel_speaker_allocation {
249 int ca_index;
250 int speakers[8];
251
252 /* derived values, just for convenience */
253 int channels;
254 int spk_mask;
255 };
256
257 /*
258 * ALSA sequence is:
259 *
260 * surround40 surround41 surround50 surround51 surround71
261 * ch0 front left = = = =
262 * ch1 front right = = = =
263 * ch2 rear left = = = =
264 * ch3 rear right = = = =
265 * ch4 LFE center center center
266 * ch5 LFE LFE
267 * ch6 side left
268 * ch7 side right
269 *
270 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
271 */
272 static int hdmi_channel_mapping[0x32][8] = {
273 /* stereo */
274 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
275 /* 2.1 */
276 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
277 /* Dolby Surround */
278 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
279 /* surround40 */
280 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
281 /* 4ch */
282 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
283 /* surround41 */
284 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
285 /* surround50 */
286 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
287 /* surround51 */
288 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
289 /* 7.1 */
290 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
291 };
292
293 /*
294 * This is an ordered list!
295 *
296 * The preceding ones have better chances to be selected by
297 * hdmi_channel_allocation().
298 */
299 static struct cea_channel_speaker_allocation channel_allocations[] = {
300 /* channel: 7 6 5 4 3 2 1 0 */
301 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
302 /* 2.1 */
303 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
304 /* Dolby Surround */
305 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
306 /* surround40 */
307 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
308 /* surround41 */
309 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
310 /* surround50 */
311 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
312 /* surround51 */
313 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
314 /* 6.1 */
315 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
316 /* surround71 */
317 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
318
319 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
320 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
321 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
322 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
323 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
324 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
325 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
326 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
327 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
328 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
329 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
330 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
331 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
332 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
333 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
334 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
335 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
336 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
337 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
338 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
339 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
340 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
341 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
342 { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
343 { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
344 { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
345 { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
346 { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
347 { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
348 { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
349 { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
350 { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
351 { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
352 { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
353 { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
354 { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
355 { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
356 { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
357 { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
358 { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
359 { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
360 };
361
362
363 /*
364 * HDMI routines
365 */
366
367 #define get_pin(spec, idx) \
368 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
369 #define get_cvt(spec, idx) \
370 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
371 #define get_pcm_rec(spec, idx) ((spec)->pcm_rec[idx])
372
373 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
374 {
375 struct hdmi_spec *spec = codec->spec;
376 int pin_idx;
377
378 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
379 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
380 return pin_idx;
381
382 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
383 return -EINVAL;
384 }
385
386 static int hinfo_to_pin_index(struct hda_codec *codec,
387 struct hda_pcm_stream *hinfo)
388 {
389 struct hdmi_spec *spec = codec->spec;
390 int pin_idx;
391
392 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
393 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
394 return pin_idx;
395
396 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
397 return -EINVAL;
398 }
399
400 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
401 {
402 struct hdmi_spec *spec = codec->spec;
403 int cvt_idx;
404
405 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
406 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
407 return cvt_idx;
408
409 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
410 return -EINVAL;
411 }
412
413 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
414 struct snd_ctl_elem_info *uinfo)
415 {
416 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
417 struct hdmi_spec *spec = codec->spec;
418 struct hdmi_spec_per_pin *per_pin;
419 struct hdmi_eld *eld;
420 int pin_idx;
421
422 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
423
424 pin_idx = kcontrol->private_value;
425 per_pin = get_pin(spec, pin_idx);
426 eld = &per_pin->sink_eld;
427
428 mutex_lock(&per_pin->lock);
429 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
430 mutex_unlock(&per_pin->lock);
431
432 return 0;
433 }
434
435 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
436 struct snd_ctl_elem_value *ucontrol)
437 {
438 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
439 struct hdmi_spec *spec = codec->spec;
440 struct hdmi_spec_per_pin *per_pin;
441 struct hdmi_eld *eld;
442 int pin_idx;
443
444 pin_idx = kcontrol->private_value;
445 per_pin = get_pin(spec, pin_idx);
446 eld = &per_pin->sink_eld;
447
448 mutex_lock(&per_pin->lock);
449 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
450 mutex_unlock(&per_pin->lock);
451 snd_BUG();
452 return -EINVAL;
453 }
454
455 memset(ucontrol->value.bytes.data, 0,
456 ARRAY_SIZE(ucontrol->value.bytes.data));
457 if (eld->eld_valid)
458 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
459 eld->eld_size);
460 mutex_unlock(&per_pin->lock);
461
462 return 0;
463 }
464
465 static struct snd_kcontrol_new eld_bytes_ctl = {
466 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
467 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
468 .name = "ELD",
469 .info = hdmi_eld_ctl_info,
470 .get = hdmi_eld_ctl_get,
471 };
472
473 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
474 int device)
475 {
476 struct snd_kcontrol *kctl;
477 struct hdmi_spec *spec = codec->spec;
478 int err;
479
480 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
481 if (!kctl)
482 return -ENOMEM;
483 kctl->private_value = pin_idx;
484 kctl->id.device = device;
485
486 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
487 if (err < 0)
488 return err;
489
490 get_pin(spec, pin_idx)->eld_ctl = kctl;
491 return 0;
492 }
493
494 #ifdef BE_PARANOID
495 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
496 int *packet_index, int *byte_index)
497 {
498 int val;
499
500 val = snd_hda_codec_read(codec, pin_nid, 0,
501 AC_VERB_GET_HDMI_DIP_INDEX, 0);
502
503 *packet_index = val >> 5;
504 *byte_index = val & 0x1f;
505 }
506 #endif
507
508 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
509 int packet_index, int byte_index)
510 {
511 int val;
512
513 val = (packet_index << 5) | (byte_index & 0x1f);
514
515 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
516 }
517
518 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
519 unsigned char val)
520 {
521 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
522 }
523
524 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
525 {
526 struct hdmi_spec *spec = codec->spec;
527 int pin_out;
528
529 /* Unmute */
530 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
531 snd_hda_codec_write(codec, pin_nid, 0,
532 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
533
534 if (spec->dyn_pin_out)
535 /* Disable pin out until stream is active */
536 pin_out = 0;
537 else
538 /* Enable pin out: some machines with GM965 gets broken output
539 * when the pin is disabled or changed while using with HDMI
540 */
541 pin_out = PIN_OUT;
542
543 snd_hda_codec_write(codec, pin_nid, 0,
544 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
545 }
546
547 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
548 {
549 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
550 AC_VERB_GET_CVT_CHAN_COUNT, 0);
551 }
552
553 static void hdmi_set_channel_count(struct hda_codec *codec,
554 hda_nid_t cvt_nid, int chs)
555 {
556 if (chs != hdmi_get_channel_count(codec, cvt_nid))
557 snd_hda_codec_write(codec, cvt_nid, 0,
558 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
559 }
560
561 /*
562 * ELD proc files
563 */
564
565 #ifdef CONFIG_SND_PROC_FS
566 static void print_eld_info(struct snd_info_entry *entry,
567 struct snd_info_buffer *buffer)
568 {
569 struct hdmi_spec_per_pin *per_pin = entry->private_data;
570
571 mutex_lock(&per_pin->lock);
572 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
573 mutex_unlock(&per_pin->lock);
574 }
575
576 static void write_eld_info(struct snd_info_entry *entry,
577 struct snd_info_buffer *buffer)
578 {
579 struct hdmi_spec_per_pin *per_pin = entry->private_data;
580
581 mutex_lock(&per_pin->lock);
582 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
583 mutex_unlock(&per_pin->lock);
584 }
585
586 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
587 {
588 char name[32];
589 struct hda_codec *codec = per_pin->codec;
590 struct snd_info_entry *entry;
591 int err;
592
593 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
594 err = snd_card_proc_new(codec->card, name, &entry);
595 if (err < 0)
596 return err;
597
598 snd_info_set_text_ops(entry, per_pin, print_eld_info);
599 entry->c.text.write = write_eld_info;
600 entry->mode |= S_IWUSR;
601 per_pin->proc_entry = entry;
602
603 return 0;
604 }
605
606 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
607 {
608 if (!per_pin->codec->bus->shutdown) {
609 snd_info_free_entry(per_pin->proc_entry);
610 per_pin->proc_entry = NULL;
611 }
612 }
613 #else
614 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
615 int index)
616 {
617 return 0;
618 }
619 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
620 {
621 }
622 #endif
623
624 /*
625 * Channel mapping routines
626 */
627
628 /*
629 * Compute derived values in channel_allocations[].
630 */
631 static void init_channel_allocations(void)
632 {
633 int i, j;
634 struct cea_channel_speaker_allocation *p;
635
636 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
637 p = channel_allocations + i;
638 p->channels = 0;
639 p->spk_mask = 0;
640 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
641 if (p->speakers[j]) {
642 p->channels++;
643 p->spk_mask |= p->speakers[j];
644 }
645 }
646 }
647
648 static int get_channel_allocation_order(int ca)
649 {
650 int i;
651
652 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
653 if (channel_allocations[i].ca_index == ca)
654 break;
655 }
656 return i;
657 }
658
659 /*
660 * The transformation takes two steps:
661 *
662 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
663 * spk_mask => (channel_allocations[]) => ai->CA
664 *
665 * TODO: it could select the wrong CA from multiple candidates.
666 */
667 static int hdmi_channel_allocation(struct hda_codec *codec,
668 struct hdmi_eld *eld, int channels)
669 {
670 int i;
671 int ca = 0;
672 int spk_mask = 0;
673 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
674
675 /*
676 * CA defaults to 0 for basic stereo audio
677 */
678 if (channels <= 2)
679 return 0;
680
681 /*
682 * expand ELD's speaker allocation mask
683 *
684 * ELD tells the speaker mask in a compact(paired) form,
685 * expand ELD's notions to match the ones used by Audio InfoFrame.
686 */
687 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
688 if (eld->info.spk_alloc & (1 << i))
689 spk_mask |= eld_speaker_allocation_bits[i];
690 }
691
692 /* search for the first working match in the CA table */
693 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
694 if (channels == channel_allocations[i].channels &&
695 (spk_mask & channel_allocations[i].spk_mask) ==
696 channel_allocations[i].spk_mask) {
697 ca = channel_allocations[i].ca_index;
698 break;
699 }
700 }
701
702 if (!ca) {
703 /* if there was no match, select the regular ALSA channel
704 * allocation with the matching number of channels */
705 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
706 if (channels == channel_allocations[i].channels) {
707 ca = channel_allocations[i].ca_index;
708 break;
709 }
710 }
711 }
712
713 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
714 codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
715 ca, channels, buf);
716
717 return ca;
718 }
719
720 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
721 hda_nid_t pin_nid)
722 {
723 #ifdef CONFIG_SND_DEBUG_VERBOSE
724 struct hdmi_spec *spec = codec->spec;
725 int i;
726 int channel;
727
728 for (i = 0; i < 8; i++) {
729 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
730 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
731 channel, i);
732 }
733 #endif
734 }
735
736 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
737 hda_nid_t pin_nid,
738 bool non_pcm,
739 int ca)
740 {
741 struct hdmi_spec *spec = codec->spec;
742 struct cea_channel_speaker_allocation *ch_alloc;
743 int i;
744 int err;
745 int order;
746 int non_pcm_mapping[8];
747
748 order = get_channel_allocation_order(ca);
749 ch_alloc = &channel_allocations[order];
750
751 if (hdmi_channel_mapping[ca][1] == 0) {
752 int hdmi_slot = 0;
753 /* fill actual channel mappings in ALSA channel (i) order */
754 for (i = 0; i < ch_alloc->channels; i++) {
755 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
756 hdmi_slot++; /* skip zero slots */
757
758 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
759 }
760 /* fill the rest of the slots with ALSA channel 0xf */
761 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
762 if (!ch_alloc->speakers[7 - hdmi_slot])
763 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
764 }
765
766 if (non_pcm) {
767 for (i = 0; i < ch_alloc->channels; i++)
768 non_pcm_mapping[i] = (i << 4) | i;
769 for (; i < 8; i++)
770 non_pcm_mapping[i] = (0xf << 4) | i;
771 }
772
773 for (i = 0; i < 8; i++) {
774 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
775 int hdmi_slot = slotsetup & 0x0f;
776 int channel = (slotsetup & 0xf0) >> 4;
777 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
778 if (err) {
779 codec_dbg(codec, "HDMI: channel mapping failed\n");
780 break;
781 }
782 }
783 }
784
785 struct channel_map_table {
786 unsigned char map; /* ALSA API channel map position */
787 int spk_mask; /* speaker position bit mask */
788 };
789
790 static struct channel_map_table map_tables[] = {
791 { SNDRV_CHMAP_FL, FL },
792 { SNDRV_CHMAP_FR, FR },
793 { SNDRV_CHMAP_RL, RL },
794 { SNDRV_CHMAP_RR, RR },
795 { SNDRV_CHMAP_LFE, LFE },
796 { SNDRV_CHMAP_FC, FC },
797 { SNDRV_CHMAP_RLC, RLC },
798 { SNDRV_CHMAP_RRC, RRC },
799 { SNDRV_CHMAP_RC, RC },
800 { SNDRV_CHMAP_FLC, FLC },
801 { SNDRV_CHMAP_FRC, FRC },
802 { SNDRV_CHMAP_TFL, FLH },
803 { SNDRV_CHMAP_TFR, FRH },
804 { SNDRV_CHMAP_FLW, FLW },
805 { SNDRV_CHMAP_FRW, FRW },
806 { SNDRV_CHMAP_TC, TC },
807 { SNDRV_CHMAP_TFC, FCH },
808 {} /* terminator */
809 };
810
811 /* from ALSA API channel position to speaker bit mask */
812 static int to_spk_mask(unsigned char c)
813 {
814 struct channel_map_table *t = map_tables;
815 for (; t->map; t++) {
816 if (t->map == c)
817 return t->spk_mask;
818 }
819 return 0;
820 }
821
822 /* from ALSA API channel position to CEA slot */
823 static int to_cea_slot(int ordered_ca, unsigned char pos)
824 {
825 int mask = to_spk_mask(pos);
826 int i;
827
828 if (mask) {
829 for (i = 0; i < 8; i++) {
830 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
831 return i;
832 }
833 }
834
835 return -1;
836 }
837
838 /* from speaker bit mask to ALSA API channel position */
839 static int spk_to_chmap(int spk)
840 {
841 struct channel_map_table *t = map_tables;
842 for (; t->map; t++) {
843 if (t->spk_mask == spk)
844 return t->map;
845 }
846 return 0;
847 }
848
849 /* from CEA slot to ALSA API channel position */
850 static int from_cea_slot(int ordered_ca, unsigned char slot)
851 {
852 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
853
854 return spk_to_chmap(mask);
855 }
856
857 /* get the CA index corresponding to the given ALSA API channel map */
858 static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
859 {
860 int i, spks = 0, spk_mask = 0;
861
862 for (i = 0; i < chs; i++) {
863 int mask = to_spk_mask(map[i]);
864 if (mask) {
865 spk_mask |= mask;
866 spks++;
867 }
868 }
869
870 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
871 if ((chs == channel_allocations[i].channels ||
872 spks == channel_allocations[i].channels) &&
873 (spk_mask & channel_allocations[i].spk_mask) ==
874 channel_allocations[i].spk_mask)
875 return channel_allocations[i].ca_index;
876 }
877 return -1;
878 }
879
880 /* set up the channel slots for the given ALSA API channel map */
881 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
882 hda_nid_t pin_nid,
883 int chs, unsigned char *map,
884 int ca)
885 {
886 struct hdmi_spec *spec = codec->spec;
887 int ordered_ca = get_channel_allocation_order(ca);
888 int alsa_pos, hdmi_slot;
889 int assignments[8] = {[0 ... 7] = 0xf};
890
891 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
892
893 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
894
895 if (hdmi_slot < 0)
896 continue; /* unassigned channel */
897
898 assignments[hdmi_slot] = alsa_pos;
899 }
900
901 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
902 int err;
903
904 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
905 assignments[hdmi_slot]);
906 if (err)
907 return -EINVAL;
908 }
909 return 0;
910 }
911
912 /* store ALSA API channel map from the current default map */
913 static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
914 {
915 int i;
916 int ordered_ca = get_channel_allocation_order(ca);
917 for (i = 0; i < 8; i++) {
918 if (i < channel_allocations[ordered_ca].channels)
919 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
920 else
921 map[i] = 0;
922 }
923 }
924
925 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
926 hda_nid_t pin_nid, bool non_pcm, int ca,
927 int channels, unsigned char *map,
928 bool chmap_set)
929 {
930 if (!non_pcm && chmap_set) {
931 hdmi_manual_setup_channel_mapping(codec, pin_nid,
932 channels, map, ca);
933 } else {
934 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
935 hdmi_setup_fake_chmap(map, ca);
936 }
937
938 hdmi_debug_channel_mapping(codec, pin_nid);
939 }
940
941 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
942 int asp_slot, int channel)
943 {
944 return snd_hda_codec_write(codec, pin_nid, 0,
945 AC_VERB_SET_HDMI_CHAN_SLOT,
946 (channel << 4) | asp_slot);
947 }
948
949 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
950 int asp_slot)
951 {
952 return (snd_hda_codec_read(codec, pin_nid, 0,
953 AC_VERB_GET_HDMI_CHAN_SLOT,
954 asp_slot) & 0xf0) >> 4;
955 }
956
957 /*
958 * Audio InfoFrame routines
959 */
960
961 /*
962 * Enable Audio InfoFrame Transmission
963 */
964 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
965 hda_nid_t pin_nid)
966 {
967 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
968 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
969 AC_DIPXMIT_BEST);
970 }
971
972 /*
973 * Disable Audio InfoFrame Transmission
974 */
975 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
976 hda_nid_t pin_nid)
977 {
978 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
979 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
980 AC_DIPXMIT_DISABLE);
981 }
982
983 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
984 {
985 #ifdef CONFIG_SND_DEBUG_VERBOSE
986 int i;
987 int size;
988
989 size = snd_hdmi_get_eld_size(codec, pin_nid);
990 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
991
992 for (i = 0; i < 8; i++) {
993 size = snd_hda_codec_read(codec, pin_nid, 0,
994 AC_VERB_GET_HDMI_DIP_SIZE, i);
995 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
996 }
997 #endif
998 }
999
1000 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
1001 {
1002 #ifdef BE_PARANOID
1003 int i, j;
1004 int size;
1005 int pi, bi;
1006 for (i = 0; i < 8; i++) {
1007 size = snd_hda_codec_read(codec, pin_nid, 0,
1008 AC_VERB_GET_HDMI_DIP_SIZE, i);
1009 if (size == 0)
1010 continue;
1011
1012 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1013 for (j = 1; j < 1000; j++) {
1014 hdmi_write_dip_byte(codec, pin_nid, 0x0);
1015 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1016 if (pi != i)
1017 codec_dbg(codec, "dip index %d: %d != %d\n",
1018 bi, pi, i);
1019 if (bi == 0) /* byte index wrapped around */
1020 break;
1021 }
1022 codec_dbg(codec,
1023 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1024 i, size, j);
1025 }
1026 #endif
1027 }
1028
1029 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1030 {
1031 u8 *bytes = (u8 *)hdmi_ai;
1032 u8 sum = 0;
1033 int i;
1034
1035 hdmi_ai->checksum = 0;
1036
1037 for (i = 0; i < sizeof(*hdmi_ai); i++)
1038 sum += bytes[i];
1039
1040 hdmi_ai->checksum = -sum;
1041 }
1042
1043 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1044 hda_nid_t pin_nid,
1045 u8 *dip, int size)
1046 {
1047 int i;
1048
1049 hdmi_debug_dip_size(codec, pin_nid);
1050 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1051
1052 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1053 for (i = 0; i < size; i++)
1054 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1055 }
1056
1057 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1058 u8 *dip, int size)
1059 {
1060 u8 val;
1061 int i;
1062
1063 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1064 != AC_DIPXMIT_BEST)
1065 return false;
1066
1067 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1068 for (i = 0; i < size; i++) {
1069 val = snd_hda_codec_read(codec, pin_nid, 0,
1070 AC_VERB_GET_HDMI_DIP_DATA, 0);
1071 if (val != dip[i])
1072 return false;
1073 }
1074
1075 return true;
1076 }
1077
1078 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1079 hda_nid_t pin_nid,
1080 int ca, int active_channels,
1081 int conn_type)
1082 {
1083 union audio_infoframe ai;
1084
1085 memset(&ai, 0, sizeof(ai));
1086 if (conn_type == 0) { /* HDMI */
1087 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1088
1089 hdmi_ai->type = 0x84;
1090 hdmi_ai->ver = 0x01;
1091 hdmi_ai->len = 0x0a;
1092 hdmi_ai->CC02_CT47 = active_channels - 1;
1093 hdmi_ai->CA = ca;
1094 hdmi_checksum_audio_infoframe(hdmi_ai);
1095 } else if (conn_type == 1) { /* DisplayPort */
1096 struct dp_audio_infoframe *dp_ai = &ai.dp;
1097
1098 dp_ai->type = 0x84;
1099 dp_ai->len = 0x1b;
1100 dp_ai->ver = 0x11 << 2;
1101 dp_ai->CC02_CT47 = active_channels - 1;
1102 dp_ai->CA = ca;
1103 } else {
1104 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1105 pin_nid);
1106 return;
1107 }
1108
1109 /*
1110 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1111 * sizeof(*dp_ai) to avoid partial match/update problems when
1112 * the user switches between HDMI/DP monitors.
1113 */
1114 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1115 sizeof(ai))) {
1116 codec_dbg(codec,
1117 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1118 pin_nid,
1119 active_channels, ca);
1120 hdmi_stop_infoframe_trans(codec, pin_nid);
1121 hdmi_fill_audio_infoframe(codec, pin_nid,
1122 ai.bytes, sizeof(ai));
1123 hdmi_start_infoframe_trans(codec, pin_nid);
1124 }
1125 }
1126
1127 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1128 struct hdmi_spec_per_pin *per_pin,
1129 bool non_pcm)
1130 {
1131 struct hdmi_spec *spec = codec->spec;
1132 hda_nid_t pin_nid = per_pin->pin_nid;
1133 int channels = per_pin->channels;
1134 int active_channels;
1135 struct hdmi_eld *eld;
1136 int ca, ordered_ca;
1137
1138 if (!channels)
1139 return;
1140
1141 if (is_haswell_plus(codec))
1142 snd_hda_codec_write(codec, pin_nid, 0,
1143 AC_VERB_SET_AMP_GAIN_MUTE,
1144 AMP_OUT_UNMUTE);
1145
1146 eld = &per_pin->sink_eld;
1147
1148 if (!non_pcm && per_pin->chmap_set)
1149 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1150 else
1151 ca = hdmi_channel_allocation(codec, eld, channels);
1152 if (ca < 0)
1153 ca = 0;
1154
1155 ordered_ca = get_channel_allocation_order(ca);
1156 active_channels = channel_allocations[ordered_ca].channels;
1157
1158 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1159
1160 /*
1161 * always configure channel mapping, it may have been changed by the
1162 * user in the meantime
1163 */
1164 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1165 channels, per_pin->chmap,
1166 per_pin->chmap_set);
1167
1168 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1169 eld->info.conn_type);
1170
1171 per_pin->non_pcm = non_pcm;
1172 }
1173
1174 /*
1175 * Unsolicited events
1176 */
1177
1178 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1179
1180 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
1181 {
1182 struct hdmi_spec *spec = codec->spec;
1183 int pin_idx = pin_nid_to_pin_index(codec, nid);
1184
1185 if (pin_idx < 0)
1186 return;
1187 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1188 snd_hda_jack_report_sync(codec);
1189 }
1190
1191 static void jack_callback(struct hda_codec *codec,
1192 struct hda_jack_callback *jack)
1193 {
1194 check_presence_and_report(codec, jack->tbl->nid);
1195 }
1196
1197 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1198 {
1199 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1200 struct hda_jack_tbl *jack;
1201 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1202
1203 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1204 if (!jack)
1205 return;
1206 jack->jack_dirty = 1;
1207
1208 codec_dbg(codec,
1209 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1210 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1211 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1212
1213 check_presence_and_report(codec, jack->nid);
1214 }
1215
1216 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1217 {
1218 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1219 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1220 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1221 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1222
1223 codec_info(codec,
1224 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1225 codec->addr,
1226 tag,
1227 subtag,
1228 cp_state,
1229 cp_ready);
1230
1231 /* TODO */
1232 if (cp_state)
1233 ;
1234 if (cp_ready)
1235 ;
1236 }
1237
1238
1239 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1240 {
1241 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1242 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1243
1244 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1245 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1246 return;
1247 }
1248
1249 if (subtag == 0)
1250 hdmi_intrinsic_event(codec, res);
1251 else
1252 hdmi_non_intrinsic_event(codec, res);
1253 }
1254
1255 static void haswell_verify_D0(struct hda_codec *codec,
1256 hda_nid_t cvt_nid, hda_nid_t nid)
1257 {
1258 int pwr;
1259
1260 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1261 * thus pins could only choose converter 0 for use. Make sure the
1262 * converters are in correct power state */
1263 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1264 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1265
1266 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1267 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1268 AC_PWRST_D0);
1269 msleep(40);
1270 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1271 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1272 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1273 }
1274 }
1275
1276 /*
1277 * Callbacks
1278 */
1279
1280 /* HBR should be Non-PCM, 8 channels */
1281 #define is_hbr_format(format) \
1282 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1283
1284 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1285 bool hbr)
1286 {
1287 int pinctl, new_pinctl;
1288
1289 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1290 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1291 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1292
1293 if (pinctl < 0)
1294 return hbr ? -EINVAL : 0;
1295
1296 new_pinctl = pinctl & ~AC_PINCTL_EPT;
1297 if (hbr)
1298 new_pinctl |= AC_PINCTL_EPT_HBR;
1299 else
1300 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1301
1302 codec_dbg(codec,
1303 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1304 pin_nid,
1305 pinctl == new_pinctl ? "" : "new-",
1306 new_pinctl);
1307
1308 if (pinctl != new_pinctl)
1309 snd_hda_codec_write(codec, pin_nid, 0,
1310 AC_VERB_SET_PIN_WIDGET_CONTROL,
1311 new_pinctl);
1312 } else if (hbr)
1313 return -EINVAL;
1314
1315 return 0;
1316 }
1317
1318 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1319 hda_nid_t pin_nid, u32 stream_tag, int format)
1320 {
1321 struct hdmi_spec *spec = codec->spec;
1322 int err;
1323
1324 if (is_haswell_plus(codec))
1325 haswell_verify_D0(codec, cvt_nid, pin_nid);
1326
1327 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1328
1329 if (err) {
1330 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1331 return err;
1332 }
1333
1334 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1335 return 0;
1336 }
1337
1338 static int hdmi_choose_cvt(struct hda_codec *codec,
1339 int pin_idx, int *cvt_id, int *mux_id)
1340 {
1341 struct hdmi_spec *spec = codec->spec;
1342 struct hdmi_spec_per_pin *per_pin;
1343 struct hdmi_spec_per_cvt *per_cvt = NULL;
1344 int cvt_idx, mux_idx = 0;
1345
1346 per_pin = get_pin(spec, pin_idx);
1347
1348 /* Dynamically assign converter to stream */
1349 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1350 per_cvt = get_cvt(spec, cvt_idx);
1351
1352 /* Must not already be assigned */
1353 if (per_cvt->assigned)
1354 continue;
1355 /* Must be in pin's mux's list of converters */
1356 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1357 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1358 break;
1359 /* Not in mux list */
1360 if (mux_idx == per_pin->num_mux_nids)
1361 continue;
1362 break;
1363 }
1364
1365 /* No free converters */
1366 if (cvt_idx == spec->num_cvts)
1367 return -ENODEV;
1368
1369 per_pin->mux_idx = mux_idx;
1370
1371 if (cvt_id)
1372 *cvt_id = cvt_idx;
1373 if (mux_id)
1374 *mux_id = mux_idx;
1375
1376 return 0;
1377 }
1378
1379 /* Assure the pin select the right convetor */
1380 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1381 struct hdmi_spec_per_pin *per_pin)
1382 {
1383 hda_nid_t pin_nid = per_pin->pin_nid;
1384 int mux_idx, curr;
1385
1386 mux_idx = per_pin->mux_idx;
1387 curr = snd_hda_codec_read(codec, pin_nid, 0,
1388 AC_VERB_GET_CONNECT_SEL, 0);
1389 if (curr != mux_idx)
1390 snd_hda_codec_write_cache(codec, pin_nid, 0,
1391 AC_VERB_SET_CONNECT_SEL,
1392 mux_idx);
1393 }
1394
1395 /* Intel HDMI workaround to fix audio routing issue:
1396 * For some Intel display codecs, pins share the same connection list.
1397 * So a conveter can be selected by multiple pins and playback on any of these
1398 * pins will generate sound on the external display, because audio flows from
1399 * the same converter to the display pipeline. Also muting one pin may make
1400 * other pins have no sound output.
1401 * So this function assures that an assigned converter for a pin is not selected
1402 * by any other pins.
1403 */
1404 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1405 hda_nid_t pin_nid, int mux_idx)
1406 {
1407 struct hdmi_spec *spec = codec->spec;
1408 hda_nid_t nid;
1409 int cvt_idx, curr;
1410 struct hdmi_spec_per_cvt *per_cvt;
1411
1412 /* configure all pins, including "no physical connection" ones */
1413 for_each_hda_codec_node(nid, codec) {
1414 unsigned int wid_caps = get_wcaps(codec, nid);
1415 unsigned int wid_type = get_wcaps_type(wid_caps);
1416
1417 if (wid_type != AC_WID_PIN)
1418 continue;
1419
1420 if (nid == pin_nid)
1421 continue;
1422
1423 curr = snd_hda_codec_read(codec, nid, 0,
1424 AC_VERB_GET_CONNECT_SEL, 0);
1425 if (curr != mux_idx)
1426 continue;
1427
1428 /* choose an unassigned converter. The conveters in the
1429 * connection list are in the same order as in the codec.
1430 */
1431 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1432 per_cvt = get_cvt(spec, cvt_idx);
1433 if (!per_cvt->assigned) {
1434 codec_dbg(codec,
1435 "choose cvt %d for pin nid %d\n",
1436 cvt_idx, nid);
1437 snd_hda_codec_write_cache(codec, nid, 0,
1438 AC_VERB_SET_CONNECT_SEL,
1439 cvt_idx);
1440 break;
1441 }
1442 }
1443 }
1444 }
1445
1446 /*
1447 * HDA PCM callbacks
1448 */
1449 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1450 struct hda_codec *codec,
1451 struct snd_pcm_substream *substream)
1452 {
1453 struct hdmi_spec *spec = codec->spec;
1454 struct snd_pcm_runtime *runtime = substream->runtime;
1455 int pin_idx, cvt_idx, mux_idx = 0;
1456 struct hdmi_spec_per_pin *per_pin;
1457 struct hdmi_eld *eld;
1458 struct hdmi_spec_per_cvt *per_cvt = NULL;
1459 int err;
1460
1461 /* Validate hinfo */
1462 pin_idx = hinfo_to_pin_index(codec, hinfo);
1463 if (snd_BUG_ON(pin_idx < 0))
1464 return -EINVAL;
1465 per_pin = get_pin(spec, pin_idx);
1466 eld = &per_pin->sink_eld;
1467
1468 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1469 if (err < 0)
1470 return err;
1471
1472 per_cvt = get_cvt(spec, cvt_idx);
1473 /* Claim converter */
1474 per_cvt->assigned = 1;
1475 per_pin->cvt_nid = per_cvt->cvt_nid;
1476 hinfo->nid = per_cvt->cvt_nid;
1477
1478 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1479 AC_VERB_SET_CONNECT_SEL,
1480 mux_idx);
1481
1482 /* configure unused pins to choose other converters */
1483 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1484 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1485
1486 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1487
1488 /* Initially set the converter's capabilities */
1489 hinfo->channels_min = per_cvt->channels_min;
1490 hinfo->channels_max = per_cvt->channels_max;
1491 hinfo->rates = per_cvt->rates;
1492 hinfo->formats = per_cvt->formats;
1493 hinfo->maxbps = per_cvt->maxbps;
1494
1495 /* Restrict capabilities by ELD if this isn't disabled */
1496 if (!static_hdmi_pcm && eld->eld_valid) {
1497 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1498 if (hinfo->channels_min > hinfo->channels_max ||
1499 !hinfo->rates || !hinfo->formats) {
1500 per_cvt->assigned = 0;
1501 hinfo->nid = 0;
1502 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1503 return -ENODEV;
1504 }
1505 }
1506
1507 /* Store the updated parameters */
1508 runtime->hw.channels_min = hinfo->channels_min;
1509 runtime->hw.channels_max = hinfo->channels_max;
1510 runtime->hw.formats = hinfo->formats;
1511 runtime->hw.rates = hinfo->rates;
1512
1513 snd_pcm_hw_constraint_step(substream->runtime, 0,
1514 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1515 return 0;
1516 }
1517
1518 /*
1519 * HDA/HDMI auto parsing
1520 */
1521 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1522 {
1523 struct hdmi_spec *spec = codec->spec;
1524 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1525 hda_nid_t pin_nid = per_pin->pin_nid;
1526
1527 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1528 codec_warn(codec,
1529 "HDMI: pin %d wcaps %#x does not support connection list\n",
1530 pin_nid, get_wcaps(codec, pin_nid));
1531 return -EINVAL;
1532 }
1533
1534 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1535 per_pin->mux_nids,
1536 HDA_MAX_CONNECTIONS);
1537
1538 return 0;
1539 }
1540
1541 /* update per_pin ELD from the given new ELD;
1542 * setup info frame and notification accordingly
1543 */
1544 static void update_eld(struct hda_codec *codec,
1545 struct hdmi_spec_per_pin *per_pin,
1546 struct hdmi_eld *eld)
1547 {
1548 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1549 bool old_eld_valid = pin_eld->eld_valid;
1550 bool eld_changed;
1551
1552 if (eld->eld_valid)
1553 snd_hdmi_show_eld(codec, &eld->info);
1554
1555 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1556 if (eld->eld_valid && pin_eld->eld_valid)
1557 if (pin_eld->eld_size != eld->eld_size ||
1558 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1559 eld->eld_size) != 0)
1560 eld_changed = true;
1561
1562 pin_eld->eld_valid = eld->eld_valid;
1563 pin_eld->eld_size = eld->eld_size;
1564 if (eld->eld_valid)
1565 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1566 pin_eld->info = eld->info;
1567
1568 /*
1569 * Re-setup pin and infoframe. This is needed e.g. when
1570 * - sink is first plugged-in
1571 * - transcoder can change during stream playback on Haswell
1572 * and this can make HW reset converter selection on a pin.
1573 */
1574 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1575 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1576 intel_verify_pin_cvt_connect(codec, per_pin);
1577 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
1578 per_pin->mux_idx);
1579 }
1580
1581 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1582 }
1583
1584 if (eld_changed)
1585 snd_ctl_notify(codec->card,
1586 SNDRV_CTL_EVENT_MASK_VALUE |
1587 SNDRV_CTL_EVENT_MASK_INFO,
1588 &per_pin->eld_ctl->id);
1589 }
1590
1591 /* update ELD and jack state via HD-audio verbs */
1592 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1593 int repoll)
1594 {
1595 struct hda_jack_tbl *jack;
1596 struct hda_codec *codec = per_pin->codec;
1597 struct hdmi_spec *spec = codec->spec;
1598 struct hdmi_eld *eld = &spec->temp_eld;
1599 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1600 hda_nid_t pin_nid = per_pin->pin_nid;
1601 /*
1602 * Always execute a GetPinSense verb here, even when called from
1603 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1604 * response's PD bit is not the real PD value, but indicates that
1605 * the real PD value changed. An older version of the HD-audio
1606 * specification worked this way. Hence, we just ignore the data in
1607 * the unsolicited response to avoid custom WARs.
1608 */
1609 int present;
1610 bool ret;
1611 bool do_repoll = false;
1612
1613 snd_hda_power_up_pm(codec);
1614 present = snd_hda_pin_sense(codec, pin_nid);
1615
1616 mutex_lock(&per_pin->lock);
1617 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1618 if (pin_eld->monitor_present)
1619 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1620 else
1621 eld->eld_valid = false;
1622
1623 codec_dbg(codec,
1624 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1625 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1626
1627 if (eld->eld_valid) {
1628 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1629 &eld->eld_size) < 0)
1630 eld->eld_valid = false;
1631 else {
1632 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1633 eld->eld_size) < 0)
1634 eld->eld_valid = false;
1635 }
1636 if (!eld->eld_valid && repoll)
1637 do_repoll = true;
1638 }
1639
1640 if (do_repoll)
1641 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1642 else
1643 update_eld(codec, per_pin, eld);
1644
1645 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1646
1647 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1648 if (jack)
1649 jack->block_report = !ret;
1650
1651 mutex_unlock(&per_pin->lock);
1652 snd_hda_power_down_pm(codec);
1653 return ret;
1654 }
1655
1656 /* update ELD and jack state via audio component */
1657 static void sync_eld_via_acomp(struct hda_codec *codec,
1658 struct hdmi_spec_per_pin *per_pin)
1659 {
1660 struct hdmi_spec *spec = codec->spec;
1661 struct hdmi_eld *eld = &spec->temp_eld;
1662 int size;
1663
1664 mutex_lock(&per_pin->lock);
1665 size = snd_hdac_acomp_get_eld(&codec->bus->core, per_pin->pin_nid,
1666 &eld->monitor_present, eld->eld_buffer,
1667 ELD_MAX_SIZE);
1668 if (size < 0)
1669 goto unlock;
1670 if (size > 0) {
1671 size = min(size, ELD_MAX_SIZE);
1672 if (snd_hdmi_parse_eld(codec, &eld->info,
1673 eld->eld_buffer, size) < 0)
1674 size = -EINVAL;
1675 }
1676
1677 if (size > 0) {
1678 eld->eld_valid = true;
1679 eld->eld_size = size;
1680 } else {
1681 eld->eld_valid = false;
1682 eld->eld_size = 0;
1683 }
1684
1685 update_eld(codec, per_pin, eld);
1686 snd_jack_report(per_pin->acomp_jack,
1687 eld->monitor_present ? SND_JACK_AVOUT : 0);
1688 unlock:
1689 mutex_unlock(&per_pin->lock);
1690 }
1691
1692 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1693 {
1694 struct hda_codec *codec = per_pin->codec;
1695
1696 if (codec_has_acomp(codec)) {
1697 sync_eld_via_acomp(codec, per_pin);
1698 return false; /* don't call snd_hda_jack_report_sync() */
1699 } else {
1700 return hdmi_present_sense_via_verbs(per_pin, repoll);
1701 }
1702 }
1703
1704 static void hdmi_repoll_eld(struct work_struct *work)
1705 {
1706 struct hdmi_spec_per_pin *per_pin =
1707 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1708
1709 if (per_pin->repoll_count++ > 6)
1710 per_pin->repoll_count = 0;
1711
1712 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1713 snd_hda_jack_report_sync(per_pin->codec);
1714 }
1715
1716 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1717 hda_nid_t nid);
1718
1719 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1720 {
1721 struct hdmi_spec *spec = codec->spec;
1722 unsigned int caps, config;
1723 int pin_idx;
1724 struct hdmi_spec_per_pin *per_pin;
1725 int err;
1726
1727 caps = snd_hda_query_pin_caps(codec, pin_nid);
1728 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1729 return 0;
1730
1731 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1732 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1733 return 0;
1734
1735 if (is_haswell_plus(codec))
1736 intel_haswell_fixup_connect_list(codec, pin_nid);
1737
1738 pin_idx = spec->num_pins;
1739 per_pin = snd_array_new(&spec->pins);
1740 if (!per_pin)
1741 return -ENOMEM;
1742
1743 per_pin->pin_nid = pin_nid;
1744 per_pin->non_pcm = false;
1745
1746 err = hdmi_read_pin_conn(codec, pin_idx);
1747 if (err < 0)
1748 return err;
1749
1750 spec->num_pins++;
1751
1752 return 0;
1753 }
1754
1755 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1756 {
1757 struct hdmi_spec *spec = codec->spec;
1758 struct hdmi_spec_per_cvt *per_cvt;
1759 unsigned int chans;
1760 int err;
1761
1762 chans = get_wcaps(codec, cvt_nid);
1763 chans = get_wcaps_channels(chans);
1764
1765 per_cvt = snd_array_new(&spec->cvts);
1766 if (!per_cvt)
1767 return -ENOMEM;
1768
1769 per_cvt->cvt_nid = cvt_nid;
1770 per_cvt->channels_min = 2;
1771 if (chans <= 16) {
1772 per_cvt->channels_max = chans;
1773 if (chans > spec->channels_max)
1774 spec->channels_max = chans;
1775 }
1776
1777 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1778 &per_cvt->rates,
1779 &per_cvt->formats,
1780 &per_cvt->maxbps);
1781 if (err < 0)
1782 return err;
1783
1784 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1785 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1786 spec->num_cvts++;
1787
1788 return 0;
1789 }
1790
1791 static int hdmi_parse_codec(struct hda_codec *codec)
1792 {
1793 hda_nid_t nid;
1794 int i, nodes;
1795
1796 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1797 if (!nid || nodes < 0) {
1798 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1799 return -EINVAL;
1800 }
1801
1802 for (i = 0; i < nodes; i++, nid++) {
1803 unsigned int caps;
1804 unsigned int type;
1805
1806 caps = get_wcaps(codec, nid);
1807 type = get_wcaps_type(caps);
1808
1809 if (!(caps & AC_WCAP_DIGITAL))
1810 continue;
1811
1812 switch (type) {
1813 case AC_WID_AUD_OUT:
1814 hdmi_add_cvt(codec, nid);
1815 break;
1816 case AC_WID_PIN:
1817 hdmi_add_pin(codec, nid);
1818 break;
1819 }
1820 }
1821
1822 return 0;
1823 }
1824
1825 /*
1826 */
1827 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1828 {
1829 struct hda_spdif_out *spdif;
1830 bool non_pcm;
1831
1832 mutex_lock(&codec->spdif_mutex);
1833 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1834 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1835 mutex_unlock(&codec->spdif_mutex);
1836 return non_pcm;
1837 }
1838
1839 /*
1840 * HDMI callbacks
1841 */
1842
1843 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1844 struct hda_codec *codec,
1845 unsigned int stream_tag,
1846 unsigned int format,
1847 struct snd_pcm_substream *substream)
1848 {
1849 hda_nid_t cvt_nid = hinfo->nid;
1850 struct hdmi_spec *spec = codec->spec;
1851 int pin_idx = hinfo_to_pin_index(codec, hinfo);
1852 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1853 hda_nid_t pin_nid = per_pin->pin_nid;
1854 struct snd_pcm_runtime *runtime = substream->runtime;
1855 bool non_pcm;
1856 int pinctl;
1857
1858 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1859 /* Verify pin:cvt selections to avoid silent audio after S3.
1860 * After S3, the audio driver restores pin:cvt selections
1861 * but this can happen before gfx is ready and such selection
1862 * is overlooked by HW. Thus multiple pins can share a same
1863 * default convertor and mute control will affect each other,
1864 * which can cause a resumed audio playback become silent
1865 * after S3.
1866 */
1867 intel_verify_pin_cvt_connect(codec, per_pin);
1868 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1869 }
1870
1871 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1872 /* Todo: add DP1.2 MST audio support later */
1873 snd_hdac_sync_audio_rate(&codec->bus->core, pin_nid, runtime->rate);
1874
1875 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1876 mutex_lock(&per_pin->lock);
1877 per_pin->channels = substream->runtime->channels;
1878 per_pin->setup = true;
1879
1880 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1881 mutex_unlock(&per_pin->lock);
1882
1883 if (spec->dyn_pin_out) {
1884 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1885 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1886 snd_hda_codec_write(codec, pin_nid, 0,
1887 AC_VERB_SET_PIN_WIDGET_CONTROL,
1888 pinctl | PIN_OUT);
1889 }
1890
1891 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1892 }
1893
1894 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1895 struct hda_codec *codec,
1896 struct snd_pcm_substream *substream)
1897 {
1898 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1899 return 0;
1900 }
1901
1902 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1903 struct hda_codec *codec,
1904 struct snd_pcm_substream *substream)
1905 {
1906 struct hdmi_spec *spec = codec->spec;
1907 int cvt_idx, pin_idx;
1908 struct hdmi_spec_per_cvt *per_cvt;
1909 struct hdmi_spec_per_pin *per_pin;
1910 int pinctl;
1911
1912 if (hinfo->nid) {
1913 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1914 if (snd_BUG_ON(cvt_idx < 0))
1915 return -EINVAL;
1916 per_cvt = get_cvt(spec, cvt_idx);
1917
1918 snd_BUG_ON(!per_cvt->assigned);
1919 per_cvt->assigned = 0;
1920 hinfo->nid = 0;
1921
1922 pin_idx = hinfo_to_pin_index(codec, hinfo);
1923 if (snd_BUG_ON(pin_idx < 0))
1924 return -EINVAL;
1925 per_pin = get_pin(spec, pin_idx);
1926
1927 if (spec->dyn_pin_out) {
1928 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1929 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1930 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1931 AC_VERB_SET_PIN_WIDGET_CONTROL,
1932 pinctl & ~PIN_OUT);
1933 }
1934
1935 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1936
1937 mutex_lock(&per_pin->lock);
1938 per_pin->chmap_set = false;
1939 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1940
1941 per_pin->setup = false;
1942 per_pin->channels = 0;
1943 mutex_unlock(&per_pin->lock);
1944 }
1945
1946 return 0;
1947 }
1948
1949 static const struct hda_pcm_ops generic_ops = {
1950 .open = hdmi_pcm_open,
1951 .close = hdmi_pcm_close,
1952 .prepare = generic_hdmi_playback_pcm_prepare,
1953 .cleanup = generic_hdmi_playback_pcm_cleanup,
1954 };
1955
1956 /*
1957 * ALSA API channel-map control callbacks
1958 */
1959 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1960 struct snd_ctl_elem_info *uinfo)
1961 {
1962 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1963 struct hda_codec *codec = info->private_data;
1964 struct hdmi_spec *spec = codec->spec;
1965 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1966 uinfo->count = spec->channels_max;
1967 uinfo->value.integer.min = 0;
1968 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1969 return 0;
1970 }
1971
1972 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1973 int channels)
1974 {
1975 /* If the speaker allocation matches the channel count, it is OK.*/
1976 if (cap->channels != channels)
1977 return -1;
1978
1979 /* all channels are remappable freely */
1980 return SNDRV_CTL_TLVT_CHMAP_VAR;
1981 }
1982
1983 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1984 unsigned int *chmap, int channels)
1985 {
1986 int count = 0;
1987 int c;
1988
1989 for (c = 7; c >= 0; c--) {
1990 int spk = cap->speakers[c];
1991 if (!spk)
1992 continue;
1993
1994 chmap[count++] = spk_to_chmap(spk);
1995 }
1996
1997 WARN_ON(count != channels);
1998 }
1999
2000 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
2001 unsigned int size, unsigned int __user *tlv)
2002 {
2003 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2004 struct hda_codec *codec = info->private_data;
2005 struct hdmi_spec *spec = codec->spec;
2006 unsigned int __user *dst;
2007 int chs, count = 0;
2008
2009 if (size < 8)
2010 return -ENOMEM;
2011 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
2012 return -EFAULT;
2013 size -= 8;
2014 dst = tlv + 2;
2015 for (chs = 2; chs <= spec->channels_max; chs++) {
2016 int i;
2017 struct cea_channel_speaker_allocation *cap;
2018 cap = channel_allocations;
2019 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
2020 int chs_bytes = chs * 4;
2021 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
2022 unsigned int tlv_chmap[8];
2023
2024 if (type < 0)
2025 continue;
2026 if (size < 8)
2027 return -ENOMEM;
2028 if (put_user(type, dst) ||
2029 put_user(chs_bytes, dst + 1))
2030 return -EFAULT;
2031 dst += 2;
2032 size -= 8;
2033 count += 8;
2034 if (size < chs_bytes)
2035 return -ENOMEM;
2036 size -= chs_bytes;
2037 count += chs_bytes;
2038 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
2039 if (copy_to_user(dst, tlv_chmap, chs_bytes))
2040 return -EFAULT;
2041 dst += chs;
2042 }
2043 }
2044 if (put_user(count, tlv + 1))
2045 return -EFAULT;
2046 return 0;
2047 }
2048
2049 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
2050 struct snd_ctl_elem_value *ucontrol)
2051 {
2052 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2053 struct hda_codec *codec = info->private_data;
2054 struct hdmi_spec *spec = codec->spec;
2055 int pin_idx = kcontrol->private_value;
2056 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2057 int i;
2058
2059 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
2060 ucontrol->value.integer.value[i] = per_pin->chmap[i];
2061 return 0;
2062 }
2063
2064 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2065 struct snd_ctl_elem_value *ucontrol)
2066 {
2067 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2068 struct hda_codec *codec = info->private_data;
2069 struct hdmi_spec *spec = codec->spec;
2070 int pin_idx = kcontrol->private_value;
2071 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2072 unsigned int ctl_idx;
2073 struct snd_pcm_substream *substream;
2074 unsigned char chmap[8];
2075 int i, err, ca, prepared = 0;
2076
2077 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2078 substream = snd_pcm_chmap_substream(info, ctl_idx);
2079 if (!substream || !substream->runtime)
2080 return 0; /* just for avoiding error from alsactl restore */
2081 switch (substream->runtime->status->state) {
2082 case SNDRV_PCM_STATE_OPEN:
2083 case SNDRV_PCM_STATE_SETUP:
2084 break;
2085 case SNDRV_PCM_STATE_PREPARED:
2086 prepared = 1;
2087 break;
2088 default:
2089 return -EBUSY;
2090 }
2091 memset(chmap, 0, sizeof(chmap));
2092 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2093 chmap[i] = ucontrol->value.integer.value[i];
2094 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2095 return 0;
2096 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2097 if (ca < 0)
2098 return -EINVAL;
2099 if (spec->ops.chmap_validate) {
2100 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2101 if (err)
2102 return err;
2103 }
2104 mutex_lock(&per_pin->lock);
2105 per_pin->chmap_set = true;
2106 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2107 if (prepared)
2108 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2109 mutex_unlock(&per_pin->lock);
2110
2111 return 0;
2112 }
2113
2114 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2115 {
2116 struct hdmi_spec *spec = codec->spec;
2117 int pin_idx;
2118
2119 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2120 struct hda_pcm *info;
2121 struct hda_pcm_stream *pstr;
2122
2123 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
2124 if (!info)
2125 return -ENOMEM;
2126 spec->pcm_rec[pin_idx] = info;
2127 info->pcm_type = HDA_PCM_TYPE_HDMI;
2128 info->own_chmap = true;
2129
2130 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2131 pstr->substreams = 1;
2132 pstr->ops = generic_ops;
2133 /* other pstr fields are set in open */
2134 }
2135
2136 return 0;
2137 }
2138
2139 static void free_acomp_jack_priv(struct snd_jack *jack)
2140 {
2141 struct hdmi_spec_per_pin *per_pin = jack->private_data;
2142
2143 per_pin->acomp_jack = NULL;
2144 }
2145
2146 static int add_acomp_jack_kctl(struct hda_codec *codec,
2147 struct hdmi_spec_per_pin *per_pin,
2148 const char *name)
2149 {
2150 struct snd_jack *jack;
2151 int err;
2152
2153 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2154 true, false);
2155 if (err < 0)
2156 return err;
2157 per_pin->acomp_jack = jack;
2158 jack->private_data = per_pin;
2159 jack->private_free = free_acomp_jack_priv;
2160 return 0;
2161 }
2162
2163 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2164 {
2165 char hdmi_str[32] = "HDMI/DP";
2166 struct hdmi_spec *spec = codec->spec;
2167 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2168 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2169 bool phantom_jack;
2170
2171 if (pcmdev > 0)
2172 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2173 if (codec_has_acomp(codec))
2174 return add_acomp_jack_kctl(codec, per_pin, hdmi_str);
2175 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2176 if (phantom_jack)
2177 strncat(hdmi_str, " Phantom",
2178 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2179
2180 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2181 phantom_jack);
2182 }
2183
2184 static int generic_hdmi_build_controls(struct hda_codec *codec)
2185 {
2186 struct hdmi_spec *spec = codec->spec;
2187 int err;
2188 int pin_idx;
2189
2190 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2191 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2192
2193 err = generic_hdmi_build_jack(codec, pin_idx);
2194 if (err < 0)
2195 return err;
2196
2197 err = snd_hda_create_dig_out_ctls(codec,
2198 per_pin->pin_nid,
2199 per_pin->mux_nids[0],
2200 HDA_PCM_TYPE_HDMI);
2201 if (err < 0)
2202 return err;
2203 snd_hda_spdif_ctls_unassign(codec, pin_idx);
2204
2205 /* add control for ELD Bytes */
2206 err = hdmi_create_eld_ctl(codec, pin_idx,
2207 get_pcm_rec(spec, pin_idx)->device);
2208
2209 if (err < 0)
2210 return err;
2211
2212 hdmi_present_sense(per_pin, 0);
2213 }
2214
2215 /* add channel maps */
2216 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2217 struct hda_pcm *pcm;
2218 struct snd_pcm_chmap *chmap;
2219 struct snd_kcontrol *kctl;
2220 int i;
2221
2222 pcm = spec->pcm_rec[pin_idx];
2223 if (!pcm || !pcm->pcm)
2224 break;
2225 err = snd_pcm_add_chmap_ctls(pcm->pcm,
2226 SNDRV_PCM_STREAM_PLAYBACK,
2227 NULL, 0, pin_idx, &chmap);
2228 if (err < 0)
2229 return err;
2230 /* override handlers */
2231 chmap->private_data = codec;
2232 kctl = chmap->kctl;
2233 for (i = 0; i < kctl->count; i++)
2234 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2235 kctl->info = hdmi_chmap_ctl_info;
2236 kctl->get = hdmi_chmap_ctl_get;
2237 kctl->put = hdmi_chmap_ctl_put;
2238 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2239 }
2240
2241 return 0;
2242 }
2243
2244 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2245 {
2246 struct hdmi_spec *spec = codec->spec;
2247 int pin_idx;
2248
2249 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2250 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2251
2252 per_pin->codec = codec;
2253 mutex_init(&per_pin->lock);
2254 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2255 eld_proc_new(per_pin, pin_idx);
2256 }
2257 return 0;
2258 }
2259
2260 static int generic_hdmi_init(struct hda_codec *codec)
2261 {
2262 struct hdmi_spec *spec = codec->spec;
2263 int pin_idx;
2264
2265 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2266 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2267 hda_nid_t pin_nid = per_pin->pin_nid;
2268
2269 hdmi_init_pin(codec, pin_nid);
2270 if (!codec_has_acomp(codec))
2271 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2272 codec->jackpoll_interval > 0 ?
2273 jack_callback : NULL);
2274 }
2275 return 0;
2276 }
2277
2278 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2279 {
2280 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2281 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2282 }
2283
2284 static void hdmi_array_free(struct hdmi_spec *spec)
2285 {
2286 snd_array_free(&spec->pins);
2287 snd_array_free(&spec->cvts);
2288 }
2289
2290 static void generic_hdmi_free(struct hda_codec *codec)
2291 {
2292 struct hdmi_spec *spec = codec->spec;
2293 int pin_idx;
2294
2295 if (codec_has_acomp(codec))
2296 snd_hdac_i915_register_notifier(NULL);
2297
2298 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2299 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2300
2301 cancel_delayed_work_sync(&per_pin->work);
2302 eld_proc_free(per_pin);
2303 if (per_pin->acomp_jack)
2304 snd_device_free(codec->card, per_pin->acomp_jack);
2305 }
2306
2307 if (spec->i915_bound)
2308 snd_hdac_i915_exit(&codec->bus->core);
2309 hdmi_array_free(spec);
2310 kfree(spec);
2311 }
2312
2313 #ifdef CONFIG_PM
2314 static int generic_hdmi_resume(struct hda_codec *codec)
2315 {
2316 struct hdmi_spec *spec = codec->spec;
2317 int pin_idx;
2318
2319 codec->patch_ops.init(codec);
2320 regcache_sync(codec->core.regmap);
2321
2322 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2323 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2324 hdmi_present_sense(per_pin, 1);
2325 }
2326 return 0;
2327 }
2328 #endif
2329
2330 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2331 .init = generic_hdmi_init,
2332 .free = generic_hdmi_free,
2333 .build_pcms = generic_hdmi_build_pcms,
2334 .build_controls = generic_hdmi_build_controls,
2335 .unsol_event = hdmi_unsol_event,
2336 #ifdef CONFIG_PM
2337 .resume = generic_hdmi_resume,
2338 #endif
2339 };
2340
2341 static const struct hdmi_ops generic_standard_hdmi_ops = {
2342 .pin_get_eld = snd_hdmi_get_eld,
2343 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2344 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2345 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2346 .pin_hbr_setup = hdmi_pin_hbr_setup,
2347 .setup_stream = hdmi_setup_stream,
2348 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2349 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2350 };
2351
2352
2353 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2354 hda_nid_t nid)
2355 {
2356 struct hdmi_spec *spec = codec->spec;
2357 hda_nid_t conns[4];
2358 int nconns;
2359
2360 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2361 if (nconns == spec->num_cvts &&
2362 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2363 return;
2364
2365 /* override pins connection list */
2366 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2367 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2368 }
2369
2370 #define INTEL_VENDOR_NID 0x08
2371 #define INTEL_GET_VENDOR_VERB 0xf81
2372 #define INTEL_SET_VENDOR_VERB 0x781
2373 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2374 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2375
2376 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2377 bool update_tree)
2378 {
2379 unsigned int vendor_param;
2380
2381 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2382 INTEL_GET_VENDOR_VERB, 0);
2383 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2384 return;
2385
2386 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2387 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2388 INTEL_SET_VENDOR_VERB, vendor_param);
2389 if (vendor_param == -1)
2390 return;
2391
2392 if (update_tree)
2393 snd_hda_codec_update_widgets(codec);
2394 }
2395
2396 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2397 {
2398 unsigned int vendor_param;
2399
2400 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2401 INTEL_GET_VENDOR_VERB, 0);
2402 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2403 return;
2404
2405 /* enable DP1.2 mode */
2406 vendor_param |= INTEL_EN_DP12;
2407 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2408 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2409 INTEL_SET_VENDOR_VERB, vendor_param);
2410 }
2411
2412 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2413 * Otherwise you may get severe h/w communication errors.
2414 */
2415 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2416 unsigned int power_state)
2417 {
2418 if (power_state == AC_PWRST_D0) {
2419 intel_haswell_enable_all_pins(codec, false);
2420 intel_haswell_fixup_enable_dp12(codec);
2421 }
2422
2423 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2424 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2425 }
2426
2427 static void intel_pin_eld_notify(void *audio_ptr, int port)
2428 {
2429 struct hda_codec *codec = audio_ptr;
2430 int pin_nid = port + 0x04;
2431
2432 /* skip notification during system suspend (but not in runtime PM);
2433 * the state will be updated at resume
2434 */
2435 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2436 return;
2437 /* ditto during suspend/resume process itself */
2438 if (atomic_read(&(codec)->core.in_pm))
2439 return;
2440
2441 check_presence_and_report(codec, pin_nid);
2442 }
2443
2444 static int patch_generic_hdmi(struct hda_codec *codec)
2445 {
2446 struct hdmi_spec *spec;
2447
2448 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2449 if (spec == NULL)
2450 return -ENOMEM;
2451
2452 spec->ops = generic_standard_hdmi_ops;
2453 codec->spec = spec;
2454 hdmi_array_init(spec, 4);
2455
2456 /* Try to bind with i915 for any Intel codecs (if not done yet) */
2457 if (!codec_has_acomp(codec) &&
2458 (codec->core.vendor_id >> 16) == 0x8086)
2459 if (!snd_hdac_i915_init(&codec->bus->core))
2460 spec->i915_bound = true;
2461
2462 if (is_haswell_plus(codec)) {
2463 intel_haswell_enable_all_pins(codec, true);
2464 intel_haswell_fixup_enable_dp12(codec);
2465 }
2466
2467 /* For Valleyview/Cherryview, only the display codec is in the display
2468 * power well and can use link_power ops to request/release the power.
2469 * For Haswell/Broadwell, the controller is also in the power well and
2470 * can cover the codec power request, and so need not set this flag.
2471 * For previous platforms, there is no such power well feature.
2472 */
2473 if (is_valleyview_plus(codec) || is_skylake(codec) ||
2474 is_broxton(codec))
2475 codec->core.link_power_control = 1;
2476
2477 if (codec_has_acomp(codec)) {
2478 codec->depop_delay = 0;
2479 spec->i915_audio_ops.audio_ptr = codec;
2480 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2481 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2482 }
2483
2484 if (hdmi_parse_codec(codec) < 0) {
2485 if (spec->i915_bound)
2486 snd_hdac_i915_exit(&codec->bus->core);
2487 codec->spec = NULL;
2488 kfree(spec);
2489 return -EINVAL;
2490 }
2491 codec->patch_ops = generic_hdmi_patch_ops;
2492 if (is_haswell_plus(codec)) {
2493 codec->patch_ops.set_power_state = haswell_set_power_state;
2494 codec->dp_mst = true;
2495 }
2496
2497 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2498 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2499 codec->auto_runtime_pm = 1;
2500
2501 generic_hdmi_init_per_pins(codec);
2502
2503 init_channel_allocations();
2504
2505 return 0;
2506 }
2507
2508 /*
2509 * Shared non-generic implementations
2510 */
2511
2512 static int simple_playback_build_pcms(struct hda_codec *codec)
2513 {
2514 struct hdmi_spec *spec = codec->spec;
2515 struct hda_pcm *info;
2516 unsigned int chans;
2517 struct hda_pcm_stream *pstr;
2518 struct hdmi_spec_per_cvt *per_cvt;
2519
2520 per_cvt = get_cvt(spec, 0);
2521 chans = get_wcaps(codec, per_cvt->cvt_nid);
2522 chans = get_wcaps_channels(chans);
2523
2524 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2525 if (!info)
2526 return -ENOMEM;
2527 spec->pcm_rec[0] = info;
2528 info->pcm_type = HDA_PCM_TYPE_HDMI;
2529 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2530 *pstr = spec->pcm_playback;
2531 pstr->nid = per_cvt->cvt_nid;
2532 if (pstr->channels_max <= 2 && chans && chans <= 16)
2533 pstr->channels_max = chans;
2534
2535 return 0;
2536 }
2537
2538 /* unsolicited event for jack sensing */
2539 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2540 unsigned int res)
2541 {
2542 snd_hda_jack_set_dirty_all(codec);
2543 snd_hda_jack_report_sync(codec);
2544 }
2545
2546 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2547 * as long as spec->pins[] is set correctly
2548 */
2549 #define simple_hdmi_build_jack generic_hdmi_build_jack
2550
2551 static int simple_playback_build_controls(struct hda_codec *codec)
2552 {
2553 struct hdmi_spec *spec = codec->spec;
2554 struct hdmi_spec_per_cvt *per_cvt;
2555 int err;
2556
2557 per_cvt = get_cvt(spec, 0);
2558 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2559 per_cvt->cvt_nid,
2560 HDA_PCM_TYPE_HDMI);
2561 if (err < 0)
2562 return err;
2563 return simple_hdmi_build_jack(codec, 0);
2564 }
2565
2566 static int simple_playback_init(struct hda_codec *codec)
2567 {
2568 struct hdmi_spec *spec = codec->spec;
2569 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2570 hda_nid_t pin = per_pin->pin_nid;
2571
2572 snd_hda_codec_write(codec, pin, 0,
2573 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2574 /* some codecs require to unmute the pin */
2575 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2576 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2577 AMP_OUT_UNMUTE);
2578 snd_hda_jack_detect_enable(codec, pin);
2579 return 0;
2580 }
2581
2582 static void simple_playback_free(struct hda_codec *codec)
2583 {
2584 struct hdmi_spec *spec = codec->spec;
2585
2586 hdmi_array_free(spec);
2587 kfree(spec);
2588 }
2589
2590 /*
2591 * Nvidia specific implementations
2592 */
2593
2594 #define Nv_VERB_SET_Channel_Allocation 0xF79
2595 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2596 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2597 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2598
2599 #define nvhdmi_master_con_nid_7x 0x04
2600 #define nvhdmi_master_pin_nid_7x 0x05
2601
2602 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2603 /*front, rear, clfe, rear_surr */
2604 0x6, 0x8, 0xa, 0xc,
2605 };
2606
2607 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2608 /* set audio protect on */
2609 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2610 /* enable digital output on pin widget */
2611 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2612 {} /* terminator */
2613 };
2614
2615 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2616 /* set audio protect on */
2617 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2618 /* enable digital output on pin widget */
2619 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2620 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2621 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2622 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2623 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2624 {} /* terminator */
2625 };
2626
2627 #ifdef LIMITED_RATE_FMT_SUPPORT
2628 /* support only the safe format and rate */
2629 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2630 #define SUPPORTED_MAXBPS 16
2631 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2632 #else
2633 /* support all rates and formats */
2634 #define SUPPORTED_RATES \
2635 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2636 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2637 SNDRV_PCM_RATE_192000)
2638 #define SUPPORTED_MAXBPS 24
2639 #define SUPPORTED_FORMATS \
2640 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2641 #endif
2642
2643 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2644 {
2645 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2646 return 0;
2647 }
2648
2649 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2650 {
2651 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2652 return 0;
2653 }
2654
2655 static unsigned int channels_2_6_8[] = {
2656 2, 6, 8
2657 };
2658
2659 static unsigned int channels_2_8[] = {
2660 2, 8
2661 };
2662
2663 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2664 .count = ARRAY_SIZE(channels_2_6_8),
2665 .list = channels_2_6_8,
2666 .mask = 0,
2667 };
2668
2669 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2670 .count = ARRAY_SIZE(channels_2_8),
2671 .list = channels_2_8,
2672 .mask = 0,
2673 };
2674
2675 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2676 struct hda_codec *codec,
2677 struct snd_pcm_substream *substream)
2678 {
2679 struct hdmi_spec *spec = codec->spec;
2680 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2681
2682 switch (codec->preset->vendor_id) {
2683 case 0x10de0002:
2684 case 0x10de0003:
2685 case 0x10de0005:
2686 case 0x10de0006:
2687 hw_constraints_channels = &hw_constraints_2_8_channels;
2688 break;
2689 case 0x10de0007:
2690 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2691 break;
2692 default:
2693 break;
2694 }
2695
2696 if (hw_constraints_channels != NULL) {
2697 snd_pcm_hw_constraint_list(substream->runtime, 0,
2698 SNDRV_PCM_HW_PARAM_CHANNELS,
2699 hw_constraints_channels);
2700 } else {
2701 snd_pcm_hw_constraint_step(substream->runtime, 0,
2702 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2703 }
2704
2705 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2706 }
2707
2708 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2709 struct hda_codec *codec,
2710 struct snd_pcm_substream *substream)
2711 {
2712 struct hdmi_spec *spec = codec->spec;
2713 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2714 }
2715
2716 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2717 struct hda_codec *codec,
2718 unsigned int stream_tag,
2719 unsigned int format,
2720 struct snd_pcm_substream *substream)
2721 {
2722 struct hdmi_spec *spec = codec->spec;
2723 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2724 stream_tag, format, substream);
2725 }
2726
2727 static const struct hda_pcm_stream simple_pcm_playback = {
2728 .substreams = 1,
2729 .channels_min = 2,
2730 .channels_max = 2,
2731 .ops = {
2732 .open = simple_playback_pcm_open,
2733 .close = simple_playback_pcm_close,
2734 .prepare = simple_playback_pcm_prepare
2735 },
2736 };
2737
2738 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2739 .build_controls = simple_playback_build_controls,
2740 .build_pcms = simple_playback_build_pcms,
2741 .init = simple_playback_init,
2742 .free = simple_playback_free,
2743 .unsol_event = simple_hdmi_unsol_event,
2744 };
2745
2746 static int patch_simple_hdmi(struct hda_codec *codec,
2747 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2748 {
2749 struct hdmi_spec *spec;
2750 struct hdmi_spec_per_cvt *per_cvt;
2751 struct hdmi_spec_per_pin *per_pin;
2752
2753 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2754 if (!spec)
2755 return -ENOMEM;
2756
2757 codec->spec = spec;
2758 hdmi_array_init(spec, 1);
2759
2760 spec->multiout.num_dacs = 0; /* no analog */
2761 spec->multiout.max_channels = 2;
2762 spec->multiout.dig_out_nid = cvt_nid;
2763 spec->num_cvts = 1;
2764 spec->num_pins = 1;
2765 per_pin = snd_array_new(&spec->pins);
2766 per_cvt = snd_array_new(&spec->cvts);
2767 if (!per_pin || !per_cvt) {
2768 simple_playback_free(codec);
2769 return -ENOMEM;
2770 }
2771 per_cvt->cvt_nid = cvt_nid;
2772 per_pin->pin_nid = pin_nid;
2773 spec->pcm_playback = simple_pcm_playback;
2774
2775 codec->patch_ops = simple_hdmi_patch_ops;
2776
2777 return 0;
2778 }
2779
2780 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2781 int channels)
2782 {
2783 unsigned int chanmask;
2784 int chan = channels ? (channels - 1) : 1;
2785
2786 switch (channels) {
2787 default:
2788 case 0:
2789 case 2:
2790 chanmask = 0x00;
2791 break;
2792 case 4:
2793 chanmask = 0x08;
2794 break;
2795 case 6:
2796 chanmask = 0x0b;
2797 break;
2798 case 8:
2799 chanmask = 0x13;
2800 break;
2801 }
2802
2803 /* Set the audio infoframe channel allocation and checksum fields. The
2804 * channel count is computed implicitly by the hardware. */
2805 snd_hda_codec_write(codec, 0x1, 0,
2806 Nv_VERB_SET_Channel_Allocation, chanmask);
2807
2808 snd_hda_codec_write(codec, 0x1, 0,
2809 Nv_VERB_SET_Info_Frame_Checksum,
2810 (0x71 - chan - chanmask));
2811 }
2812
2813 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2814 struct hda_codec *codec,
2815 struct snd_pcm_substream *substream)
2816 {
2817 struct hdmi_spec *spec = codec->spec;
2818 int i;
2819
2820 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2821 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2822 for (i = 0; i < 4; i++) {
2823 /* set the stream id */
2824 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2825 AC_VERB_SET_CHANNEL_STREAMID, 0);
2826 /* set the stream format */
2827 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2828 AC_VERB_SET_STREAM_FORMAT, 0);
2829 }
2830
2831 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2832 * streams are disabled. */
2833 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2834
2835 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2836 }
2837
2838 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2839 struct hda_codec *codec,
2840 unsigned int stream_tag,
2841 unsigned int format,
2842 struct snd_pcm_substream *substream)
2843 {
2844 int chs;
2845 unsigned int dataDCC2, channel_id;
2846 int i;
2847 struct hdmi_spec *spec = codec->spec;
2848 struct hda_spdif_out *spdif;
2849 struct hdmi_spec_per_cvt *per_cvt;
2850
2851 mutex_lock(&codec->spdif_mutex);
2852 per_cvt = get_cvt(spec, 0);
2853 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2854
2855 chs = substream->runtime->channels;
2856
2857 dataDCC2 = 0x2;
2858
2859 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2860 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2861 snd_hda_codec_write(codec,
2862 nvhdmi_master_con_nid_7x,
2863 0,
2864 AC_VERB_SET_DIGI_CONVERT_1,
2865 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2866
2867 /* set the stream id */
2868 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2869 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2870
2871 /* set the stream format */
2872 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2873 AC_VERB_SET_STREAM_FORMAT, format);
2874
2875 /* turn on again (if needed) */
2876 /* enable and set the channel status audio/data flag */
2877 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2878 snd_hda_codec_write(codec,
2879 nvhdmi_master_con_nid_7x,
2880 0,
2881 AC_VERB_SET_DIGI_CONVERT_1,
2882 spdif->ctls & 0xff);
2883 snd_hda_codec_write(codec,
2884 nvhdmi_master_con_nid_7x,
2885 0,
2886 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2887 }
2888
2889 for (i = 0; i < 4; i++) {
2890 if (chs == 2)
2891 channel_id = 0;
2892 else
2893 channel_id = i * 2;
2894
2895 /* turn off SPDIF once;
2896 *otherwise the IEC958 bits won't be updated
2897 */
2898 if (codec->spdif_status_reset &&
2899 (spdif->ctls & AC_DIG1_ENABLE))
2900 snd_hda_codec_write(codec,
2901 nvhdmi_con_nids_7x[i],
2902 0,
2903 AC_VERB_SET_DIGI_CONVERT_1,
2904 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2905 /* set the stream id */
2906 snd_hda_codec_write(codec,
2907 nvhdmi_con_nids_7x[i],
2908 0,
2909 AC_VERB_SET_CHANNEL_STREAMID,
2910 (stream_tag << 4) | channel_id);
2911 /* set the stream format */
2912 snd_hda_codec_write(codec,
2913 nvhdmi_con_nids_7x[i],
2914 0,
2915 AC_VERB_SET_STREAM_FORMAT,
2916 format);
2917 /* turn on again (if needed) */
2918 /* enable and set the channel status audio/data flag */
2919 if (codec->spdif_status_reset &&
2920 (spdif->ctls & AC_DIG1_ENABLE)) {
2921 snd_hda_codec_write(codec,
2922 nvhdmi_con_nids_7x[i],
2923 0,
2924 AC_VERB_SET_DIGI_CONVERT_1,
2925 spdif->ctls & 0xff);
2926 snd_hda_codec_write(codec,
2927 nvhdmi_con_nids_7x[i],
2928 0,
2929 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2930 }
2931 }
2932
2933 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2934
2935 mutex_unlock(&codec->spdif_mutex);
2936 return 0;
2937 }
2938
2939 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2940 .substreams = 1,
2941 .channels_min = 2,
2942 .channels_max = 8,
2943 .nid = nvhdmi_master_con_nid_7x,
2944 .rates = SUPPORTED_RATES,
2945 .maxbps = SUPPORTED_MAXBPS,
2946 .formats = SUPPORTED_FORMATS,
2947 .ops = {
2948 .open = simple_playback_pcm_open,
2949 .close = nvhdmi_8ch_7x_pcm_close,
2950 .prepare = nvhdmi_8ch_7x_pcm_prepare
2951 },
2952 };
2953
2954 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2955 {
2956 struct hdmi_spec *spec;
2957 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2958 nvhdmi_master_pin_nid_7x);
2959 if (err < 0)
2960 return err;
2961
2962 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2963 /* override the PCM rates, etc, as the codec doesn't give full list */
2964 spec = codec->spec;
2965 spec->pcm_playback.rates = SUPPORTED_RATES;
2966 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2967 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2968 return 0;
2969 }
2970
2971 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2972 {
2973 struct hdmi_spec *spec = codec->spec;
2974 int err = simple_playback_build_pcms(codec);
2975 if (!err) {
2976 struct hda_pcm *info = get_pcm_rec(spec, 0);
2977 info->own_chmap = true;
2978 }
2979 return err;
2980 }
2981
2982 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2983 {
2984 struct hdmi_spec *spec = codec->spec;
2985 struct hda_pcm *info;
2986 struct snd_pcm_chmap *chmap;
2987 int err;
2988
2989 err = simple_playback_build_controls(codec);
2990 if (err < 0)
2991 return err;
2992
2993 /* add channel maps */
2994 info = get_pcm_rec(spec, 0);
2995 err = snd_pcm_add_chmap_ctls(info->pcm,
2996 SNDRV_PCM_STREAM_PLAYBACK,
2997 snd_pcm_alt_chmaps, 8, 0, &chmap);
2998 if (err < 0)
2999 return err;
3000 switch (codec->preset->vendor_id) {
3001 case 0x10de0002:
3002 case 0x10de0003:
3003 case 0x10de0005:
3004 case 0x10de0006:
3005 chmap->channel_mask = (1U << 2) | (1U << 8);
3006 break;
3007 case 0x10de0007:
3008 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3009 }
3010 return 0;
3011 }
3012
3013 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3014 {
3015 struct hdmi_spec *spec;
3016 int err = patch_nvhdmi_2ch(codec);
3017 if (err < 0)
3018 return err;
3019 spec = codec->spec;
3020 spec->multiout.max_channels = 8;
3021 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3022 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3023 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3024 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3025
3026 /* Initialize the audio infoframe channel mask and checksum to something
3027 * valid */
3028 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3029
3030 return 0;
3031 }
3032
3033 /*
3034 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3035 * - 0x10de0015
3036 * - 0x10de0040
3037 */
3038 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3039 int channels)
3040 {
3041 if (cap->ca_index == 0x00 && channels == 2)
3042 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3043
3044 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
3045 }
3046
3047 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
3048 {
3049 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3050 return -EINVAL;
3051
3052 return 0;
3053 }
3054
3055 static int patch_nvhdmi(struct hda_codec *codec)
3056 {
3057 struct hdmi_spec *spec;
3058 int err;
3059
3060 err = patch_generic_hdmi(codec);
3061 if (err)
3062 return err;
3063
3064 spec = codec->spec;
3065 spec->dyn_pin_out = true;
3066
3067 spec->ops.chmap_cea_alloc_validate_get_type =
3068 nvhdmi_chmap_cea_alloc_validate_get_type;
3069 spec->ops.chmap_validate = nvhdmi_chmap_validate;
3070
3071 return 0;
3072 }
3073
3074 /*
3075 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3076 * accessed using vendor-defined verbs. These registers can be used for
3077 * interoperability between the HDA and HDMI drivers.
3078 */
3079
3080 /* Audio Function Group node */
3081 #define NVIDIA_AFG_NID 0x01
3082
3083 /*
3084 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3085 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3086 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3087 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3088 * additional bit (at position 30) to signal the validity of the format.
3089 *
3090 * | 31 | 30 | 29 16 | 15 0 |
3091 * +---------+-------+--------+--------+
3092 * | TRIGGER | VALID | UNUSED | FORMAT |
3093 * +-----------------------------------|
3094 *
3095 * Note that for the trigger bit to take effect it needs to change value
3096 * (i.e. it needs to be toggled).
3097 */
3098 #define NVIDIA_GET_SCRATCH0 0xfa6
3099 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3100 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3101 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3102 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3103 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3104 #define NVIDIA_SCRATCH_VALID (1 << 6)
3105
3106 #define NVIDIA_GET_SCRATCH1 0xfab
3107 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3108 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3109 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3110 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3111
3112 /*
3113 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3114 * the format is invalidated so that the HDMI codec can be disabled.
3115 */
3116 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3117 {
3118 unsigned int value;
3119
3120 /* bits [31:30] contain the trigger and valid bits */
3121 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3122 NVIDIA_GET_SCRATCH0, 0);
3123 value = (value >> 24) & 0xff;
3124
3125 /* bits [15:0] are used to store the HDA format */
3126 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3127 NVIDIA_SET_SCRATCH0_BYTE0,
3128 (format >> 0) & 0xff);
3129 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3130 NVIDIA_SET_SCRATCH0_BYTE1,
3131 (format >> 8) & 0xff);
3132
3133 /* bits [16:24] are unused */
3134 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3135 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3136
3137 /*
3138 * Bit 30 signals that the data is valid and hence that HDMI audio can
3139 * be enabled.
3140 */
3141 if (format == 0)
3142 value &= ~NVIDIA_SCRATCH_VALID;
3143 else
3144 value |= NVIDIA_SCRATCH_VALID;
3145
3146 /*
3147 * Whenever the trigger bit is toggled, an interrupt is raised in the
3148 * HDMI codec. The HDMI driver will use that as trigger to update its
3149 * configuration.
3150 */
3151 value ^= NVIDIA_SCRATCH_TRIGGER;
3152
3153 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3154 NVIDIA_SET_SCRATCH0_BYTE3, value);
3155 }
3156
3157 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3158 struct hda_codec *codec,
3159 unsigned int stream_tag,
3160 unsigned int format,
3161 struct snd_pcm_substream *substream)
3162 {
3163 int err;
3164
3165 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3166 format, substream);
3167 if (err < 0)
3168 return err;
3169
3170 /* notify the HDMI codec of the format change */
3171 tegra_hdmi_set_format(codec, format);
3172
3173 return 0;
3174 }
3175
3176 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3177 struct hda_codec *codec,
3178 struct snd_pcm_substream *substream)
3179 {
3180 /* invalidate the format in the HDMI codec */
3181 tegra_hdmi_set_format(codec, 0);
3182
3183 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3184 }
3185
3186 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3187 {
3188 struct hdmi_spec *spec = codec->spec;
3189 unsigned int i;
3190
3191 for (i = 0; i < spec->num_pins; i++) {
3192 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3193
3194 if (pcm->pcm_type == type)
3195 return pcm;
3196 }
3197
3198 return NULL;
3199 }
3200
3201 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3202 {
3203 struct hda_pcm_stream *stream;
3204 struct hda_pcm *pcm;
3205 int err;
3206
3207 err = generic_hdmi_build_pcms(codec);
3208 if (err < 0)
3209 return err;
3210
3211 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3212 if (!pcm)
3213 return -ENODEV;
3214
3215 /*
3216 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3217 * codec about format changes.
3218 */
3219 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3220 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3221 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3222
3223 return 0;
3224 }
3225
3226 static int patch_tegra_hdmi(struct hda_codec *codec)
3227 {
3228 int err;
3229
3230 err = patch_generic_hdmi(codec);
3231 if (err)
3232 return err;
3233
3234 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3235
3236 return 0;
3237 }
3238
3239 /*
3240 * ATI/AMD-specific implementations
3241 */
3242
3243 #define is_amdhdmi_rev3_or_later(codec) \
3244 ((codec)->core.vendor_id == 0x1002aa01 && \
3245 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3246 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3247
3248 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3249 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3250 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3251 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3252 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3253 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3254 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3255 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3256 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3257 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3258 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3259 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3260 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3261 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3262 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3263 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3264 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3265 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3266 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3267 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3268 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3269 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3270 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3271 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3272 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3273
3274 /* AMD specific HDA cvt verbs */
3275 #define ATI_VERB_SET_RAMP_RATE 0x770
3276 #define ATI_VERB_GET_RAMP_RATE 0xf70
3277
3278 #define ATI_OUT_ENABLE 0x1
3279
3280 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3281 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3282
3283 #define ATI_HBR_CAPABLE 0x01
3284 #define ATI_HBR_ENABLE 0x10
3285
3286 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3287 unsigned char *buf, int *eld_size)
3288 {
3289 /* call hda_eld.c ATI/AMD-specific function */
3290 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3291 is_amdhdmi_rev3_or_later(codec));
3292 }
3293
3294 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3295 int active_channels, int conn_type)
3296 {
3297 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3298 }
3299
3300 static int atihdmi_paired_swap_fc_lfe(int pos)
3301 {
3302 /*
3303 * ATI/AMD have automatic FC/LFE swap built-in
3304 * when in pairwise mapping mode.
3305 */
3306
3307 switch (pos) {
3308 /* see channel_allocations[].speakers[] */
3309 case 2: return 3;
3310 case 3: return 2;
3311 default: break;
3312 }
3313
3314 return pos;
3315 }
3316
3317 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3318 {
3319 struct cea_channel_speaker_allocation *cap;
3320 int i, j;
3321
3322 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3323
3324 cap = &channel_allocations[get_channel_allocation_order(ca)];
3325 for (i = 0; i < chs; ++i) {
3326 int mask = to_spk_mask(map[i]);
3327 bool ok = false;
3328 bool companion_ok = false;
3329
3330 if (!mask)
3331 continue;
3332
3333 for (j = 0 + i % 2; j < 8; j += 2) {
3334 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3335 if (cap->speakers[chan_idx] == mask) {
3336 /* channel is in a supported position */
3337 ok = true;
3338
3339 if (i % 2 == 0 && i + 1 < chs) {
3340 /* even channel, check the odd companion */
3341 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3342 int comp_mask_req = to_spk_mask(map[i+1]);
3343 int comp_mask_act = cap->speakers[comp_chan_idx];
3344
3345 if (comp_mask_req == comp_mask_act)
3346 companion_ok = true;
3347 else
3348 return -EINVAL;
3349 }
3350 break;
3351 }
3352 }
3353
3354 if (!ok)
3355 return -EINVAL;
3356
3357 if (companion_ok)
3358 i++; /* companion channel already checked */
3359 }
3360
3361 return 0;
3362 }
3363
3364 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3365 int hdmi_slot, int stream_channel)
3366 {
3367 int verb;
3368 int ati_channel_setup = 0;
3369
3370 if (hdmi_slot > 7)
3371 return -EINVAL;
3372
3373 if (!has_amd_full_remap_support(codec)) {
3374 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3375
3376 /* In case this is an odd slot but without stream channel, do not
3377 * disable the slot since the corresponding even slot could have a
3378 * channel. In case neither have a channel, the slot pair will be
3379 * disabled when this function is called for the even slot. */
3380 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3381 return 0;
3382
3383 hdmi_slot -= hdmi_slot % 2;
3384
3385 if (stream_channel != 0xf)
3386 stream_channel -= stream_channel % 2;
3387 }
3388
3389 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3390
3391 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3392
3393 if (stream_channel != 0xf)
3394 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3395
3396 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3397 }
3398
3399 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3400 int asp_slot)
3401 {
3402 bool was_odd = false;
3403 int ati_asp_slot = asp_slot;
3404 int verb;
3405 int ati_channel_setup;
3406
3407 if (asp_slot > 7)
3408 return -EINVAL;
3409
3410 if (!has_amd_full_remap_support(codec)) {
3411 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3412 if (ati_asp_slot % 2 != 0) {
3413 ati_asp_slot -= 1;
3414 was_odd = true;
3415 }
3416 }
3417
3418 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3419
3420 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3421
3422 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3423 return 0xf;
3424
3425 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3426 }
3427
3428 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3429 int channels)
3430 {
3431 int c;
3432
3433 /*
3434 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3435 * we need to take that into account (a single channel may take 2
3436 * channel slots if we need to carry a silent channel next to it).
3437 * On Rev3+ AMD codecs this function is not used.
3438 */
3439 int chanpairs = 0;
3440
3441 /* We only produce even-numbered channel count TLVs */
3442 if ((channels % 2) != 0)
3443 return -1;
3444
3445 for (c = 0; c < 7; c += 2) {
3446 if (cap->speakers[c] || cap->speakers[c+1])
3447 chanpairs++;
3448 }
3449
3450 if (chanpairs * 2 != channels)
3451 return -1;
3452
3453 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3454 }
3455
3456 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3457 unsigned int *chmap, int channels)
3458 {
3459 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3460 int count = 0;
3461 int c;
3462
3463 for (c = 7; c >= 0; c--) {
3464 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3465 int spk = cap->speakers[chan];
3466 if (!spk) {
3467 /* add N/A channel if the companion channel is occupied */
3468 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3469 chmap[count++] = SNDRV_CHMAP_NA;
3470
3471 continue;
3472 }
3473
3474 chmap[count++] = spk_to_chmap(spk);
3475 }
3476
3477 WARN_ON(count != channels);
3478 }
3479
3480 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3481 bool hbr)
3482 {
3483 int hbr_ctl, hbr_ctl_new;
3484
3485 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3486 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3487 if (hbr)
3488 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3489 else
3490 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3491
3492 codec_dbg(codec,
3493 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3494 pin_nid,
3495 hbr_ctl == hbr_ctl_new ? "" : "new-",
3496 hbr_ctl_new);
3497
3498 if (hbr_ctl != hbr_ctl_new)
3499 snd_hda_codec_write(codec, pin_nid, 0,
3500 ATI_VERB_SET_HBR_CONTROL,
3501 hbr_ctl_new);
3502
3503 } else if (hbr)
3504 return -EINVAL;
3505
3506 return 0;
3507 }
3508
3509 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3510 hda_nid_t pin_nid, u32 stream_tag, int format)
3511 {
3512
3513 if (is_amdhdmi_rev3_or_later(codec)) {
3514 int ramp_rate = 180; /* default as per AMD spec */
3515 /* disable ramp-up/down for non-pcm as per AMD spec */
3516 if (format & AC_FMT_TYPE_NON_PCM)
3517 ramp_rate = 0;
3518
3519 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3520 }
3521
3522 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3523 }
3524
3525
3526 static int atihdmi_init(struct hda_codec *codec)
3527 {
3528 struct hdmi_spec *spec = codec->spec;
3529 int pin_idx, err;
3530
3531 err = generic_hdmi_init(codec);
3532
3533 if (err)
3534 return err;
3535
3536 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3537 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3538
3539 /* make sure downmix information in infoframe is zero */
3540 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3541
3542 /* enable channel-wise remap mode if supported */
3543 if (has_amd_full_remap_support(codec))
3544 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3545 ATI_VERB_SET_MULTICHANNEL_MODE,
3546 ATI_MULTICHANNEL_MODE_SINGLE);
3547 }
3548
3549 return 0;
3550 }
3551
3552 static int patch_atihdmi(struct hda_codec *codec)
3553 {
3554 struct hdmi_spec *spec;
3555 struct hdmi_spec_per_cvt *per_cvt;
3556 int err, cvt_idx;
3557
3558 err = patch_generic_hdmi(codec);
3559
3560 if (err)
3561 return err;
3562
3563 codec->patch_ops.init = atihdmi_init;
3564
3565 spec = codec->spec;
3566
3567 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3568 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3569 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3570 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3571 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3572 spec->ops.setup_stream = atihdmi_setup_stream;
3573
3574 if (!has_amd_full_remap_support(codec)) {
3575 /* override to ATI/AMD-specific versions with pairwise mapping */
3576 spec->ops.chmap_cea_alloc_validate_get_type =
3577 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3578 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3579 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3580 }
3581
3582 /* ATI/AMD converters do not advertise all of their capabilities */
3583 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3584 per_cvt = get_cvt(spec, cvt_idx);
3585 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3586 per_cvt->rates |= SUPPORTED_RATES;
3587 per_cvt->formats |= SUPPORTED_FORMATS;
3588 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3589 }
3590
3591 spec->channels_max = max(spec->channels_max, 8u);
3592
3593 return 0;
3594 }
3595
3596 /* VIA HDMI Implementation */
3597 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3598 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3599
3600 static int patch_via_hdmi(struct hda_codec *codec)
3601 {
3602 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3603 }
3604
3605 /*
3606 * patch entries
3607 */
3608 static const struct hda_device_id snd_hda_id_hdmi[] = {
3609 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3610 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3611 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3612 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3613 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3614 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3615 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3616 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3617 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3618 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3619 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3620 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3621 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3622 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3623 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3624 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3625 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3626 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3627 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3628 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3629 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3630 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3631 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3632 /* 17 is known to be absent */
3633 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3634 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3635 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3636 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3637 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3638 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3639 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3640 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3641 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3642 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3643 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3644 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3645 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3646 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3647 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3648 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3649 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3650 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3651 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3652 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3653 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3654 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3655 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3656 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3657 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3658 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3659 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
3660 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3661 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3662 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3663 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
3664 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3665 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3666 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
3667 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
3668 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
3669 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
3670 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3671 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3672 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
3673 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3674 /* special ID for generic HDMI */
3675 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3676 {} /* terminator */
3677 };
3678 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3679
3680 MODULE_LICENSE("GPL");
3681 MODULE_DESCRIPTION("HDMI HD-audio codec");
3682 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3683 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3684 MODULE_ALIAS("snd-hda-codec-atihdmi");
3685
3686 static struct hda_codec_driver hdmi_driver = {
3687 .id = snd_hda_id_hdmi,
3688 };
3689
3690 module_hda_codec_driver(hdmi_driver);
Linux kernel - Deliverables
This page took 0.173081 seconds and 4 git commands to generate.