2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <sound/driver.h>
27 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32 #include <linux/moduleparam.h>
34 #include <sound/core.h>
35 #include <sound/info.h>
36 #include <sound/control.h>
37 #include <sound/pcm.h>
38 #include <sound/pcm_params.h>
39 #include <sound/asoundef.h>
40 #include <sound/initval.h>
44 /* note, two last pcis should be equal, it is not a bug */
46 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
47 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
49 MODULE_LICENSE("GPL");
50 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
54 "{RME,Digi96/8 PAD}}");
56 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
; /* Index 0-MAX */
57 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
; /* ID for this card */
58 static int enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
; /* Enable this card */
60 module_param_array(index
, int, NULL
, 0444);
61 MODULE_PARM_DESC(index
, "Index value for RME Digi96 soundcard.");
62 module_param_array(id
, charp
, NULL
, 0444);
63 MODULE_PARM_DESC(id
, "ID string for RME Digi96 soundcard.");
64 module_param_array(enable
, bool, NULL
, 0444);
65 MODULE_PARM_DESC(enable
, "Enable RME Digi96 soundcard.");
68 * Defines for RME Digi96 series, from internal RME reference documents
72 #define RME96_SPDIF_NCHANNELS 2
74 /* Playback and capture buffer size */
75 #define RME96_BUFFER_SIZE 0x10000
78 #define RME96_IO_SIZE 0x60000
81 #define RME96_IO_PLAY_BUFFER 0x0
82 #define RME96_IO_REC_BUFFER 0x10000
83 #define RME96_IO_CONTROL_REGISTER 0x20000
84 #define RME96_IO_ADDITIONAL_REG 0x20004
85 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
86 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C
87 #define RME96_IO_SET_PLAY_POS 0x40000
88 #define RME96_IO_RESET_PLAY_POS 0x4FFFC
89 #define RME96_IO_SET_REC_POS 0x50000
90 #define RME96_IO_RESET_REC_POS 0x5FFFC
91 #define RME96_IO_GET_PLAY_POS 0x20000
92 #define RME96_IO_GET_REC_POS 0x30000
94 /* Write control register bits */
95 #define RME96_WCR_START (1 << 0)
96 #define RME96_WCR_START_2 (1 << 1)
97 #define RME96_WCR_GAIN_0 (1 << 2)
98 #define RME96_WCR_GAIN_1 (1 << 3)
99 #define RME96_WCR_MODE24 (1 << 4)
100 #define RME96_WCR_MODE24_2 (1 << 5)
101 #define RME96_WCR_BM (1 << 6)
102 #define RME96_WCR_BM_2 (1 << 7)
103 #define RME96_WCR_ADAT (1 << 8)
104 #define RME96_WCR_FREQ_0 (1 << 9)
105 #define RME96_WCR_FREQ_1 (1 << 10)
106 #define RME96_WCR_DS (1 << 11)
107 #define RME96_WCR_PRO (1 << 12)
108 #define RME96_WCR_EMP (1 << 13)
109 #define RME96_WCR_SEL (1 << 14)
110 #define RME96_WCR_MASTER (1 << 15)
111 #define RME96_WCR_PD (1 << 16)
112 #define RME96_WCR_INP_0 (1 << 17)
113 #define RME96_WCR_INP_1 (1 << 18)
114 #define RME96_WCR_THRU_0 (1 << 19)
115 #define RME96_WCR_THRU_1 (1 << 20)
116 #define RME96_WCR_THRU_2 (1 << 21)
117 #define RME96_WCR_THRU_3 (1 << 22)
118 #define RME96_WCR_THRU_4 (1 << 23)
119 #define RME96_WCR_THRU_5 (1 << 24)
120 #define RME96_WCR_THRU_6 (1 << 25)
121 #define RME96_WCR_THRU_7 (1 << 26)
122 #define RME96_WCR_DOLBY (1 << 27)
123 #define RME96_WCR_MONITOR_0 (1 << 28)
124 #define RME96_WCR_MONITOR_1 (1 << 29)
125 #define RME96_WCR_ISEL (1 << 30)
126 #define RME96_WCR_IDIS (1 << 31)
128 #define RME96_WCR_BITPOS_GAIN_0 2
129 #define RME96_WCR_BITPOS_GAIN_1 3
130 #define RME96_WCR_BITPOS_FREQ_0 9
131 #define RME96_WCR_BITPOS_FREQ_1 10
132 #define RME96_WCR_BITPOS_INP_0 17
133 #define RME96_WCR_BITPOS_INP_1 18
134 #define RME96_WCR_BITPOS_MONITOR_0 28
135 #define RME96_WCR_BITPOS_MONITOR_1 29
137 /* Read control register bits */
138 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
139 #define RME96_RCR_IRQ_2 (1 << 16)
140 #define RME96_RCR_T_OUT (1 << 17)
141 #define RME96_RCR_DEV_ID_0 (1 << 21)
142 #define RME96_RCR_DEV_ID_1 (1 << 22)
143 #define RME96_RCR_LOCK (1 << 23)
144 #define RME96_RCR_VERF (1 << 26)
145 #define RME96_RCR_F0 (1 << 27)
146 #define RME96_RCR_F1 (1 << 28)
147 #define RME96_RCR_F2 (1 << 29)
148 #define RME96_RCR_AUTOSYNC (1 << 30)
149 #define RME96_RCR_IRQ (1 << 31)
151 #define RME96_RCR_BITPOS_F0 27
152 #define RME96_RCR_BITPOS_F1 28
153 #define RME96_RCR_BITPOS_F2 29
155 /* Additonal register bits */
156 #define RME96_AR_WSEL (1 << 0)
157 #define RME96_AR_ANALOG (1 << 1)
158 #define RME96_AR_FREQPAD_0 (1 << 2)
159 #define RME96_AR_FREQPAD_1 (1 << 3)
160 #define RME96_AR_FREQPAD_2 (1 << 4)
161 #define RME96_AR_PD2 (1 << 5)
162 #define RME96_AR_DAC_EN (1 << 6)
163 #define RME96_AR_CLATCH (1 << 7)
164 #define RME96_AR_CCLK (1 << 8)
165 #define RME96_AR_CDATA (1 << 9)
167 #define RME96_AR_BITPOS_F0 2
168 #define RME96_AR_BITPOS_F1 3
169 #define RME96_AR_BITPOS_F2 4
172 #define RME96_MONITOR_TRACKS_1_2 0
173 #define RME96_MONITOR_TRACKS_3_4 1
174 #define RME96_MONITOR_TRACKS_5_6 2
175 #define RME96_MONITOR_TRACKS_7_8 3
178 #define RME96_ATTENUATION_0 0
179 #define RME96_ATTENUATION_6 1
180 #define RME96_ATTENUATION_12 2
181 #define RME96_ATTENUATION_18 3
184 #define RME96_INPUT_OPTICAL 0
185 #define RME96_INPUT_COAXIAL 1
186 #define RME96_INPUT_INTERNAL 2
187 #define RME96_INPUT_XLR 3
188 #define RME96_INPUT_ANALOG 4
191 #define RME96_CLOCKMODE_SLAVE 0
192 #define RME96_CLOCKMODE_MASTER 1
193 #define RME96_CLOCKMODE_WORDCLOCK 2
195 /* Block sizes in bytes */
196 #define RME96_SMALL_BLOCK_SIZE 2048
197 #define RME96_LARGE_BLOCK_SIZE 8192
200 #define RME96_AD1852_VOL_BITS 14
201 #define RME96_AD1855_VOL_BITS 10
208 void __iomem
*iobase
;
210 u32 wcreg
; /* cached write control register value */
211 u32 wcreg_spdif
; /* S/PDIF setup */
212 u32 wcreg_spdif_stream
; /* S/PDIF setup (temporary) */
213 u32 rcreg
; /* cached read control register value */
214 u32 areg
; /* cached additional register value */
215 u16 vol
[2]; /* cached volume of analog output */
217 u8 rev
; /* card revision number */
219 struct snd_pcm_substream
*playback_substream
;
220 struct snd_pcm_substream
*capture_substream
;
222 int playback_frlog
; /* log2 of framesize */
225 size_t playback_periodsize
; /* in bytes, zero if not used */
226 size_t capture_periodsize
; /* in bytes, zero if not used */
228 struct snd_card
*card
;
229 struct snd_pcm
*spdif_pcm
;
230 struct snd_pcm
*adat_pcm
;
232 struct snd_kcontrol
*spdif_ctl
;
235 static struct pci_device_id snd_rme96_ids
[] = {
236 { PCI_VENDOR_ID_XILINX
, PCI_DEVICE_ID_RME_DIGI96
,
237 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0, },
238 { PCI_VENDOR_ID_XILINX
, PCI_DEVICE_ID_RME_DIGI96_8
,
239 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0, },
240 { PCI_VENDOR_ID_XILINX
, PCI_DEVICE_ID_RME_DIGI96_8_PRO
,
241 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0, },
242 { PCI_VENDOR_ID_XILINX
, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
,
243 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0, },
247 MODULE_DEVICE_TABLE(pci
, snd_rme96_ids
);
249 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
250 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
251 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
252 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
253 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
254 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
255 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
256 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
257 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
260 snd_rme96_playback_prepare(struct snd_pcm_substream
*substream
);
263 snd_rme96_capture_prepare(struct snd_pcm_substream
*substream
);
266 snd_rme96_playback_trigger(struct snd_pcm_substream
*substream
,
270 snd_rme96_capture_trigger(struct snd_pcm_substream
*substream
,
273 static snd_pcm_uframes_t
274 snd_rme96_playback_pointer(struct snd_pcm_substream
*substream
);
276 static snd_pcm_uframes_t
277 snd_rme96_capture_pointer(struct snd_pcm_substream
*substream
);
279 static void __devinit
280 snd_rme96_proc_init(struct rme96
*rme96
);
283 snd_rme96_create_switches(struct snd_card
*card
,
284 struct rme96
*rme96
);
287 snd_rme96_getinputtype(struct rme96
*rme96
);
289 static inline unsigned int
290 snd_rme96_playback_ptr(struct rme96
*rme96
)
292 return (readl(rme96
->iobase
+ RME96_IO_GET_PLAY_POS
)
293 & RME96_RCR_AUDIO_ADDR_MASK
) >> rme96
->playback_frlog
;
296 static inline unsigned int
297 snd_rme96_capture_ptr(struct rme96
*rme96
)
299 return (readl(rme96
->iobase
+ RME96_IO_GET_REC_POS
)
300 & RME96_RCR_AUDIO_ADDR_MASK
) >> rme96
->capture_frlog
;
304 snd_rme96_ratecode(int rate
)
307 case 32000: return SNDRV_PCM_RATE_32000
;
308 case 44100: return SNDRV_PCM_RATE_44100
;
309 case 48000: return SNDRV_PCM_RATE_48000
;
310 case 64000: return SNDRV_PCM_RATE_64000
;
311 case 88200: return SNDRV_PCM_RATE_88200
;
312 case 96000: return SNDRV_PCM_RATE_96000
;
318 snd_rme96_playback_silence(struct snd_pcm_substream
*substream
,
319 int channel
, /* not used (interleaved data) */
320 snd_pcm_uframes_t pos
,
321 snd_pcm_uframes_t count
)
323 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
324 count
<<= rme96
->playback_frlog
;
325 pos
<<= rme96
->playback_frlog
;
326 memset_io(rme96
->iobase
+ RME96_IO_PLAY_BUFFER
+ pos
,
332 snd_rme96_playback_copy(struct snd_pcm_substream
*substream
,
333 int channel
, /* not used (interleaved data) */
334 snd_pcm_uframes_t pos
,
336 snd_pcm_uframes_t count
)
338 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
339 count
<<= rme96
->playback_frlog
;
340 pos
<<= rme96
->playback_frlog
;
341 copy_from_user_toio(rme96
->iobase
+ RME96_IO_PLAY_BUFFER
+ pos
, src
,
347 snd_rme96_capture_copy(struct snd_pcm_substream
*substream
,
348 int channel
, /* not used (interleaved data) */
349 snd_pcm_uframes_t pos
,
351 snd_pcm_uframes_t count
)
353 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
354 count
<<= rme96
->capture_frlog
;
355 pos
<<= rme96
->capture_frlog
;
356 copy_to_user_fromio(dst
, rme96
->iobase
+ RME96_IO_REC_BUFFER
+ pos
,
362 * Digital output capabilities (S/PDIF)
364 static struct snd_pcm_hardware snd_rme96_playback_spdif_info
=
366 .info
= (SNDRV_PCM_INFO_MMAP_IOMEM
|
367 SNDRV_PCM_INFO_MMAP_VALID
|
368 SNDRV_PCM_INFO_INTERLEAVED
|
369 SNDRV_PCM_INFO_PAUSE
),
370 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
371 SNDRV_PCM_FMTBIT_S32_LE
),
372 .rates
= (SNDRV_PCM_RATE_32000
|
373 SNDRV_PCM_RATE_44100
|
374 SNDRV_PCM_RATE_48000
|
375 SNDRV_PCM_RATE_64000
|
376 SNDRV_PCM_RATE_88200
|
377 SNDRV_PCM_RATE_96000
),
382 .buffer_bytes_max
= RME96_BUFFER_SIZE
,
383 .period_bytes_min
= RME96_SMALL_BLOCK_SIZE
,
384 .period_bytes_max
= RME96_LARGE_BLOCK_SIZE
,
385 .periods_min
= RME96_BUFFER_SIZE
/ RME96_LARGE_BLOCK_SIZE
,
386 .periods_max
= RME96_BUFFER_SIZE
/ RME96_SMALL_BLOCK_SIZE
,
391 * Digital input capabilities (S/PDIF)
393 static struct snd_pcm_hardware snd_rme96_capture_spdif_info
=
395 .info
= (SNDRV_PCM_INFO_MMAP_IOMEM
|
396 SNDRV_PCM_INFO_MMAP_VALID
|
397 SNDRV_PCM_INFO_INTERLEAVED
|
398 SNDRV_PCM_INFO_PAUSE
),
399 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
400 SNDRV_PCM_FMTBIT_S32_LE
),
401 .rates
= (SNDRV_PCM_RATE_32000
|
402 SNDRV_PCM_RATE_44100
|
403 SNDRV_PCM_RATE_48000
|
404 SNDRV_PCM_RATE_64000
|
405 SNDRV_PCM_RATE_88200
|
406 SNDRV_PCM_RATE_96000
),
411 .buffer_bytes_max
= RME96_BUFFER_SIZE
,
412 .period_bytes_min
= RME96_SMALL_BLOCK_SIZE
,
413 .period_bytes_max
= RME96_LARGE_BLOCK_SIZE
,
414 .periods_min
= RME96_BUFFER_SIZE
/ RME96_LARGE_BLOCK_SIZE
,
415 .periods_max
= RME96_BUFFER_SIZE
/ RME96_SMALL_BLOCK_SIZE
,
420 * Digital output capabilities (ADAT)
422 static struct snd_pcm_hardware snd_rme96_playback_adat_info
=
424 .info
= (SNDRV_PCM_INFO_MMAP_IOMEM
|
425 SNDRV_PCM_INFO_MMAP_VALID
|
426 SNDRV_PCM_INFO_INTERLEAVED
|
427 SNDRV_PCM_INFO_PAUSE
),
428 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
429 SNDRV_PCM_FMTBIT_S32_LE
),
430 .rates
= (SNDRV_PCM_RATE_44100
|
431 SNDRV_PCM_RATE_48000
),
436 .buffer_bytes_max
= RME96_BUFFER_SIZE
,
437 .period_bytes_min
= RME96_SMALL_BLOCK_SIZE
,
438 .period_bytes_max
= RME96_LARGE_BLOCK_SIZE
,
439 .periods_min
= RME96_BUFFER_SIZE
/ RME96_LARGE_BLOCK_SIZE
,
440 .periods_max
= RME96_BUFFER_SIZE
/ RME96_SMALL_BLOCK_SIZE
,
445 * Digital input capabilities (ADAT)
447 static struct snd_pcm_hardware snd_rme96_capture_adat_info
=
449 .info
= (SNDRV_PCM_INFO_MMAP_IOMEM
|
450 SNDRV_PCM_INFO_MMAP_VALID
|
451 SNDRV_PCM_INFO_INTERLEAVED
|
452 SNDRV_PCM_INFO_PAUSE
),
453 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
454 SNDRV_PCM_FMTBIT_S32_LE
),
455 .rates
= (SNDRV_PCM_RATE_44100
|
456 SNDRV_PCM_RATE_48000
),
461 .buffer_bytes_max
= RME96_BUFFER_SIZE
,
462 .period_bytes_min
= RME96_SMALL_BLOCK_SIZE
,
463 .period_bytes_max
= RME96_LARGE_BLOCK_SIZE
,
464 .periods_min
= RME96_BUFFER_SIZE
/ RME96_LARGE_BLOCK_SIZE
,
465 .periods_max
= RME96_BUFFER_SIZE
/ RME96_SMALL_BLOCK_SIZE
,
470 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
471 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
472 * on the falling edge of CCLK and be stable on the rising edge. The rising
473 * edge of CLATCH after the last data bit clocks in the whole data word.
474 * A fast processor could probably drive the SPI interface faster than the
475 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
476 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
478 * NOTE: increased delay from 1 to 10, since there where problems setting
482 snd_rme96_write_SPI(struct rme96
*rme96
, u16 val
)
486 for (i
= 0; i
< 16; i
++) {
488 rme96
->areg
|= RME96_AR_CDATA
;
490 rme96
->areg
&= ~RME96_AR_CDATA
;
492 rme96
->areg
&= ~(RME96_AR_CCLK
| RME96_AR_CLATCH
);
493 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
495 rme96
->areg
|= RME96_AR_CCLK
;
496 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
500 rme96
->areg
&= ~(RME96_AR_CCLK
| RME96_AR_CDATA
);
501 rme96
->areg
|= RME96_AR_CLATCH
;
502 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
504 rme96
->areg
&= ~RME96_AR_CLATCH
;
505 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
509 snd_rme96_apply_dac_volume(struct rme96
*rme96
)
511 if (RME96_DAC_IS_1852(rme96
)) {
512 snd_rme96_write_SPI(rme96
, (rme96
->vol
[0] << 2) | 0x0);
513 snd_rme96_write_SPI(rme96
, (rme96
->vol
[1] << 2) | 0x2);
514 } else if (RME96_DAC_IS_1855(rme96
)) {
515 snd_rme96_write_SPI(rme96
, (rme96
->vol
[0] & 0x3FF) | 0x000);
516 snd_rme96_write_SPI(rme96
, (rme96
->vol
[1] & 0x3FF) | 0x400);
521 snd_rme96_reset_dac(struct rme96
*rme96
)
523 writel(rme96
->wcreg
| RME96_WCR_PD
,
524 rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
525 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
529 snd_rme96_getmontracks(struct rme96
*rme96
)
531 return ((rme96
->wcreg
>> RME96_WCR_BITPOS_MONITOR_0
) & 1) +
532 (((rme96
->wcreg
>> RME96_WCR_BITPOS_MONITOR_1
) & 1) << 1);
536 snd_rme96_setmontracks(struct rme96
*rme96
,
540 rme96
->wcreg
|= RME96_WCR_MONITOR_0
;
542 rme96
->wcreg
&= ~RME96_WCR_MONITOR_0
;
545 rme96
->wcreg
|= RME96_WCR_MONITOR_1
;
547 rme96
->wcreg
&= ~RME96_WCR_MONITOR_1
;
549 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
554 snd_rme96_getattenuation(struct rme96
*rme96
)
556 return ((rme96
->wcreg
>> RME96_WCR_BITPOS_GAIN_0
) & 1) +
557 (((rme96
->wcreg
>> RME96_WCR_BITPOS_GAIN_1
) & 1) << 1);
561 snd_rme96_setattenuation(struct rme96
*rme96
,
564 switch (attenuation
) {
566 rme96
->wcreg
= (rme96
->wcreg
& ~RME96_WCR_GAIN_0
) &
570 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_GAIN_0
) &
574 rme96
->wcreg
= (rme96
->wcreg
& ~RME96_WCR_GAIN_0
) |
578 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_GAIN_0
) |
584 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
589 snd_rme96_capture_getrate(struct rme96
*rme96
,
595 if (rme96
->areg
& RME96_AR_ANALOG
) {
596 /* Analog input, overrides S/PDIF setting */
597 n
= ((rme96
->areg
>> RME96_AR_BITPOS_F0
) & 1) +
598 (((rme96
->areg
>> RME96_AR_BITPOS_F1
) & 1) << 1);
612 return (rme96
->areg
& RME96_AR_BITPOS_F2
) ? rate
<< 1 : rate
;
615 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
616 if (rme96
->rcreg
& RME96_RCR_LOCK
) {
619 if (rme96
->rcreg
& RME96_RCR_T_OUT
) {
625 if (rme96
->rcreg
& RME96_RCR_VERF
) {
630 n
= ((rme96
->rcreg
>> RME96_RCR_BITPOS_F0
) & 1) +
631 (((rme96
->rcreg
>> RME96_RCR_BITPOS_F1
) & 1) << 1) +
632 (((rme96
->rcreg
>> RME96_RCR_BITPOS_F2
) & 1) << 2);
636 if (rme96
->rcreg
& RME96_RCR_T_OUT
) {
640 case 3: return 96000;
641 case 4: return 88200;
642 case 5: return 48000;
643 case 6: return 44100;
644 case 7: return 32000;
652 snd_rme96_playback_getrate(struct rme96
*rme96
)
656 if (!(rme96
->wcreg
& RME96_WCR_MASTER
) &&
657 snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
&&
658 (rate
= snd_rme96_capture_getrate(rme96
, &dummy
)) > 0)
663 rate
= ((rme96
->wcreg
>> RME96_WCR_BITPOS_FREQ_0
) & 1) +
664 (((rme96
->wcreg
>> RME96_WCR_BITPOS_FREQ_1
) & 1) << 1);
678 return (rme96
->wcreg
& RME96_WCR_DS
) ? rate
<< 1 : rate
;
682 snd_rme96_playback_setrate(struct rme96
*rme96
,
687 ds
= rme96
->wcreg
& RME96_WCR_DS
;
690 rme96
->wcreg
&= ~RME96_WCR_DS
;
691 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_0
) &
695 rme96
->wcreg
&= ~RME96_WCR_DS
;
696 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_1
) &
700 rme96
->wcreg
&= ~RME96_WCR_DS
;
701 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_0
) |
705 rme96
->wcreg
|= RME96_WCR_DS
;
706 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_0
) &
710 rme96
->wcreg
|= RME96_WCR_DS
;
711 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_1
) &
715 rme96
->wcreg
|= RME96_WCR_DS
;
716 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_0
) |
722 if ((!ds
&& rme96
->wcreg
& RME96_WCR_DS
) ||
723 (ds
&& !(rme96
->wcreg
& RME96_WCR_DS
)))
725 /* change to/from double-speed: reset the DAC (if available) */
726 snd_rme96_reset_dac(rme96
);
728 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
734 snd_rme96_capture_analog_setrate(struct rme96
*rme96
,
739 rme96
->areg
= ((rme96
->areg
| RME96_AR_FREQPAD_0
) &
740 ~RME96_AR_FREQPAD_1
) & ~RME96_AR_FREQPAD_2
;
743 rme96
->areg
= ((rme96
->areg
& ~RME96_AR_FREQPAD_0
) |
744 RME96_AR_FREQPAD_1
) & ~RME96_AR_FREQPAD_2
;
747 rme96
->areg
= ((rme96
->areg
| RME96_AR_FREQPAD_0
) |
748 RME96_AR_FREQPAD_1
) & ~RME96_AR_FREQPAD_2
;
751 if (rme96
->rev
< 4) {
754 rme96
->areg
= ((rme96
->areg
| RME96_AR_FREQPAD_0
) &
755 ~RME96_AR_FREQPAD_1
) | RME96_AR_FREQPAD_2
;
758 if (rme96
->rev
< 4) {
761 rme96
->areg
= ((rme96
->areg
& ~RME96_AR_FREQPAD_0
) |
762 RME96_AR_FREQPAD_1
) | RME96_AR_FREQPAD_2
;
765 rme96
->areg
= ((rme96
->areg
| RME96_AR_FREQPAD_0
) |
766 RME96_AR_FREQPAD_1
) | RME96_AR_FREQPAD_2
;
771 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
776 snd_rme96_setclockmode(struct rme96
*rme96
,
780 case RME96_CLOCKMODE_SLAVE
:
782 rme96
->wcreg
&= ~RME96_WCR_MASTER
;
783 rme96
->areg
&= ~RME96_AR_WSEL
;
785 case RME96_CLOCKMODE_MASTER
:
787 rme96
->wcreg
|= RME96_WCR_MASTER
;
788 rme96
->areg
&= ~RME96_AR_WSEL
;
790 case RME96_CLOCKMODE_WORDCLOCK
:
791 /* Word clock is a master mode */
792 rme96
->wcreg
|= RME96_WCR_MASTER
;
793 rme96
->areg
|= RME96_AR_WSEL
;
798 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
799 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
804 snd_rme96_getclockmode(struct rme96
*rme96
)
806 if (rme96
->areg
& RME96_AR_WSEL
) {
807 return RME96_CLOCKMODE_WORDCLOCK
;
809 return (rme96
->wcreg
& RME96_WCR_MASTER
) ? RME96_CLOCKMODE_MASTER
:
810 RME96_CLOCKMODE_SLAVE
;
814 snd_rme96_setinputtype(struct rme96
*rme96
,
820 case RME96_INPUT_OPTICAL
:
821 rme96
->wcreg
= (rme96
->wcreg
& ~RME96_WCR_INP_0
) &
824 case RME96_INPUT_COAXIAL
:
825 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_INP_0
) &
828 case RME96_INPUT_INTERNAL
:
829 rme96
->wcreg
= (rme96
->wcreg
& ~RME96_WCR_INP_0
) |
832 case RME96_INPUT_XLR
:
833 if ((rme96
->pci
->device
!= PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
&&
834 rme96
->pci
->device
!= PCI_DEVICE_ID_RME_DIGI96_8_PRO
) ||
835 (rme96
->pci
->device
== PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
&&
838 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
841 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_INP_0
) |
844 case RME96_INPUT_ANALOG
:
845 if (!RME96_HAS_ANALOG_IN(rme96
)) {
848 rme96
->areg
|= RME96_AR_ANALOG
;
849 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
850 if (rme96
->rev
< 4) {
852 * Revision less than 004 does not support 64 and
855 if (snd_rme96_capture_getrate(rme96
, &n
) == 88200) {
856 snd_rme96_capture_analog_setrate(rme96
, 44100);
858 if (snd_rme96_capture_getrate(rme96
, &n
) == 64000) {
859 snd_rme96_capture_analog_setrate(rme96
, 32000);
866 if (type
!= RME96_INPUT_ANALOG
&& RME96_HAS_ANALOG_IN(rme96
)) {
867 rme96
->areg
&= ~RME96_AR_ANALOG
;
868 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
870 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
875 snd_rme96_getinputtype(struct rme96
*rme96
)
877 if (rme96
->areg
& RME96_AR_ANALOG
) {
878 return RME96_INPUT_ANALOG
;
880 return ((rme96
->wcreg
>> RME96_WCR_BITPOS_INP_0
) & 1) +
881 (((rme96
->wcreg
>> RME96_WCR_BITPOS_INP_1
) & 1) << 1);
885 snd_rme96_setframelog(struct rme96
*rme96
,
891 if (n_channels
== 2) {
894 /* assume 8 channels */
898 frlog
+= (rme96
->wcreg
& RME96_WCR_MODE24
) ? 2 : 1;
899 rme96
->playback_frlog
= frlog
;
901 frlog
+= (rme96
->wcreg
& RME96_WCR_MODE24_2
) ? 2 : 1;
902 rme96
->capture_frlog
= frlog
;
907 snd_rme96_playback_setformat(struct rme96
*rme96
,
911 case SNDRV_PCM_FORMAT_S16_LE
:
912 rme96
->wcreg
&= ~RME96_WCR_MODE24
;
914 case SNDRV_PCM_FORMAT_S32_LE
:
915 rme96
->wcreg
|= RME96_WCR_MODE24
;
920 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
925 snd_rme96_capture_setformat(struct rme96
*rme96
,
929 case SNDRV_PCM_FORMAT_S16_LE
:
930 rme96
->wcreg
&= ~RME96_WCR_MODE24_2
;
932 case SNDRV_PCM_FORMAT_S32_LE
:
933 rme96
->wcreg
|= RME96_WCR_MODE24_2
;
938 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
943 snd_rme96_set_period_properties(struct rme96
*rme96
,
946 switch (period_bytes
) {
947 case RME96_LARGE_BLOCK_SIZE
:
948 rme96
->wcreg
&= ~RME96_WCR_ISEL
;
950 case RME96_SMALL_BLOCK_SIZE
:
951 rme96
->wcreg
|= RME96_WCR_ISEL
;
957 rme96
->wcreg
&= ~RME96_WCR_IDIS
;
958 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
962 snd_rme96_playback_hw_params(struct snd_pcm_substream
*substream
,
963 struct snd_pcm_hw_params
*params
)
965 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
966 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
967 int err
, rate
, dummy
;
969 runtime
->dma_area
= (void __force
*)(rme96
->iobase
+
970 RME96_IO_PLAY_BUFFER
);
971 runtime
->dma_addr
= rme96
->port
+ RME96_IO_PLAY_BUFFER
;
972 runtime
->dma_bytes
= RME96_BUFFER_SIZE
;
974 spin_lock_irq(&rme96
->lock
);
975 if (!(rme96
->wcreg
& RME96_WCR_MASTER
) &&
976 snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
&&
977 (rate
= snd_rme96_capture_getrate(rme96
, &dummy
)) > 0)
980 if ((int)params_rate(params
) != rate
) {
981 spin_unlock_irq(&rme96
->lock
);
984 } else if ((err
= snd_rme96_playback_setrate(rme96
, params_rate(params
))) < 0) {
985 spin_unlock_irq(&rme96
->lock
);
988 if ((err
= snd_rme96_playback_setformat(rme96
, params_format(params
))) < 0) {
989 spin_unlock_irq(&rme96
->lock
);
992 snd_rme96_setframelog(rme96
, params_channels(params
), 1);
993 if (rme96
->capture_periodsize
!= 0) {
994 if (params_period_size(params
) << rme96
->playback_frlog
!=
995 rme96
->capture_periodsize
)
997 spin_unlock_irq(&rme96
->lock
);
1001 rme96
->playback_periodsize
=
1002 params_period_size(params
) << rme96
->playback_frlog
;
1003 snd_rme96_set_period_properties(rme96
, rme96
->playback_periodsize
);
1005 if ((rme96
->wcreg
& RME96_WCR_ADAT
) == 0) {
1006 rme96
->wcreg
&= ~(RME96_WCR_PRO
| RME96_WCR_DOLBY
| RME96_WCR_EMP
);
1007 writel(rme96
->wcreg
|= rme96
->wcreg_spdif_stream
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1009 spin_unlock_irq(&rme96
->lock
);
1015 snd_rme96_capture_hw_params(struct snd_pcm_substream
*substream
,
1016 struct snd_pcm_hw_params
*params
)
1018 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1019 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1020 int err
, isadat
, rate
;
1022 runtime
->dma_area
= (void __force
*)(rme96
->iobase
+
1023 RME96_IO_REC_BUFFER
);
1024 runtime
->dma_addr
= rme96
->port
+ RME96_IO_REC_BUFFER
;
1025 runtime
->dma_bytes
= RME96_BUFFER_SIZE
;
1027 spin_lock_irq(&rme96
->lock
);
1028 if ((err
= snd_rme96_capture_setformat(rme96
, params_format(params
))) < 0) {
1029 spin_unlock_irq(&rme96
->lock
);
1032 if (snd_rme96_getinputtype(rme96
) == RME96_INPUT_ANALOG
) {
1033 if ((err
= snd_rme96_capture_analog_setrate(rme96
,
1034 params_rate(params
))) < 0)
1036 spin_unlock_irq(&rme96
->lock
);
1039 } else if ((rate
= snd_rme96_capture_getrate(rme96
, &isadat
)) > 0) {
1040 if ((int)params_rate(params
) != rate
) {
1041 spin_unlock_irq(&rme96
->lock
);
1044 if ((isadat
&& runtime
->hw
.channels_min
== 2) ||
1045 (!isadat
&& runtime
->hw
.channels_min
== 8))
1047 spin_unlock_irq(&rme96
->lock
);
1051 snd_rme96_setframelog(rme96
, params_channels(params
), 0);
1052 if (rme96
->playback_periodsize
!= 0) {
1053 if (params_period_size(params
) << rme96
->capture_frlog
!=
1054 rme96
->playback_periodsize
)
1056 spin_unlock_irq(&rme96
->lock
);
1060 rme96
->capture_periodsize
=
1061 params_period_size(params
) << rme96
->capture_frlog
;
1062 snd_rme96_set_period_properties(rme96
, rme96
->capture_periodsize
);
1063 spin_unlock_irq(&rme96
->lock
);
1069 snd_rme96_playback_start(struct rme96
*rme96
,
1073 writel(0, rme96
->iobase
+ RME96_IO_RESET_PLAY_POS
);
1076 rme96
->wcreg
|= RME96_WCR_START
;
1077 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1081 snd_rme96_capture_start(struct rme96
*rme96
,
1085 writel(0, rme96
->iobase
+ RME96_IO_RESET_REC_POS
);
1088 rme96
->wcreg
|= RME96_WCR_START_2
;
1089 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1093 snd_rme96_playback_stop(struct rme96
*rme96
)
1096 * Check if there is an unconfirmed IRQ, if so confirm it, or else
1097 * the hardware will not stop generating interrupts
1099 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1100 if (rme96
->rcreg
& RME96_RCR_IRQ
) {
1101 writel(0, rme96
->iobase
+ RME96_IO_CONFIRM_PLAY_IRQ
);
1103 rme96
->wcreg
&= ~RME96_WCR_START
;
1104 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1108 snd_rme96_capture_stop(struct rme96
*rme96
)
1110 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1111 if (rme96
->rcreg
& RME96_RCR_IRQ_2
) {
1112 writel(0, rme96
->iobase
+ RME96_IO_CONFIRM_REC_IRQ
);
1114 rme96
->wcreg
&= ~RME96_WCR_START_2
;
1115 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1119 snd_rme96_interrupt(int irq
,
1122 struct rme96
*rme96
= (struct rme96
*)dev_id
;
1124 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1125 /* fastpath out, to ease interrupt sharing */
1126 if (!((rme96
->rcreg
& RME96_RCR_IRQ
) ||
1127 (rme96
->rcreg
& RME96_RCR_IRQ_2
)))
1132 if (rme96
->rcreg
& RME96_RCR_IRQ
) {
1134 snd_pcm_period_elapsed(rme96
->playback_substream
);
1135 writel(0, rme96
->iobase
+ RME96_IO_CONFIRM_PLAY_IRQ
);
1137 if (rme96
->rcreg
& RME96_RCR_IRQ_2
) {
1139 snd_pcm_period_elapsed(rme96
->capture_substream
);
1140 writel(0, rme96
->iobase
+ RME96_IO_CONFIRM_REC_IRQ
);
1145 static unsigned int period_bytes
[] = { RME96_SMALL_BLOCK_SIZE
, RME96_LARGE_BLOCK_SIZE
};
1147 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes
= {
1148 .count
= ARRAY_SIZE(period_bytes
),
1149 .list
= period_bytes
,
1154 rme96_set_buffer_size_constraint(struct rme96
*rme96
,
1155 struct snd_pcm_runtime
*runtime
)
1159 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_BYTES
,
1160 RME96_BUFFER_SIZE
, RME96_BUFFER_SIZE
);
1161 if ((size
= rme96
->playback_periodsize
) != 0 ||
1162 (size
= rme96
->capture_periodsize
) != 0)
1163 snd_pcm_hw_constraint_minmax(runtime
,
1164 SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1167 snd_pcm_hw_constraint_list(runtime
, 0,
1168 SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1169 &hw_constraints_period_bytes
);
1173 snd_rme96_playback_spdif_open(struct snd_pcm_substream
*substream
)
1176 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1177 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1179 spin_lock_irq(&rme96
->lock
);
1180 if (rme96
->playback_substream
!= NULL
) {
1181 spin_unlock_irq(&rme96
->lock
);
1184 rme96
->wcreg
&= ~RME96_WCR_ADAT
;
1185 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1186 rme96
->playback_substream
= substream
;
1187 spin_unlock_irq(&rme96
->lock
);
1189 runtime
->hw
= snd_rme96_playback_spdif_info
;
1190 if (!(rme96
->wcreg
& RME96_WCR_MASTER
) &&
1191 snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
&&
1192 (rate
= snd_rme96_capture_getrate(rme96
, &dummy
)) > 0)
1195 runtime
->hw
.rates
= snd_rme96_ratecode(rate
);
1196 runtime
->hw
.rate_min
= rate
;
1197 runtime
->hw
.rate_max
= rate
;
1199 rme96_set_buffer_size_constraint(rme96
, runtime
);
1201 rme96
->wcreg_spdif_stream
= rme96
->wcreg_spdif
;
1202 rme96
->spdif_ctl
->vd
[0].access
&= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
1203 snd_ctl_notify(rme96
->card
, SNDRV_CTL_EVENT_MASK_VALUE
|
1204 SNDRV_CTL_EVENT_MASK_INFO
, &rme96
->spdif_ctl
->id
);
1209 snd_rme96_capture_spdif_open(struct snd_pcm_substream
*substream
)
1212 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1213 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1215 runtime
->hw
= snd_rme96_capture_spdif_info
;
1216 if (snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
&&
1217 (rate
= snd_rme96_capture_getrate(rme96
, &isadat
)) > 0)
1222 runtime
->hw
.rates
= snd_rme96_ratecode(rate
);
1223 runtime
->hw
.rate_min
= rate
;
1224 runtime
->hw
.rate_max
= rate
;
1227 spin_lock_irq(&rme96
->lock
);
1228 if (rme96
->capture_substream
!= NULL
) {
1229 spin_unlock_irq(&rme96
->lock
);
1232 rme96
->capture_substream
= substream
;
1233 spin_unlock_irq(&rme96
->lock
);
1235 rme96_set_buffer_size_constraint(rme96
, runtime
);
1240 snd_rme96_playback_adat_open(struct snd_pcm_substream
*substream
)
1243 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1244 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1246 spin_lock_irq(&rme96
->lock
);
1247 if (rme96
->playback_substream
!= NULL
) {
1248 spin_unlock_irq(&rme96
->lock
);
1251 rme96
->wcreg
|= RME96_WCR_ADAT
;
1252 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1253 rme96
->playback_substream
= substream
;
1254 spin_unlock_irq(&rme96
->lock
);
1256 runtime
->hw
= snd_rme96_playback_adat_info
;
1257 if (!(rme96
->wcreg
& RME96_WCR_MASTER
) &&
1258 snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
&&
1259 (rate
= snd_rme96_capture_getrate(rme96
, &dummy
)) > 0)
1262 runtime
->hw
.rates
= snd_rme96_ratecode(rate
);
1263 runtime
->hw
.rate_min
= rate
;
1264 runtime
->hw
.rate_max
= rate
;
1266 rme96_set_buffer_size_constraint(rme96
, runtime
);
1271 snd_rme96_capture_adat_open(struct snd_pcm_substream
*substream
)
1274 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1275 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1277 runtime
->hw
= snd_rme96_capture_adat_info
;
1278 if (snd_rme96_getinputtype(rme96
) == RME96_INPUT_ANALOG
) {
1279 /* makes no sense to use analog input. Note that analog
1280 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1283 if ((rate
= snd_rme96_capture_getrate(rme96
, &isadat
)) > 0) {
1287 runtime
->hw
.rates
= snd_rme96_ratecode(rate
);
1288 runtime
->hw
.rate_min
= rate
;
1289 runtime
->hw
.rate_max
= rate
;
1292 spin_lock_irq(&rme96
->lock
);
1293 if (rme96
->capture_substream
!= NULL
) {
1294 spin_unlock_irq(&rme96
->lock
);
1297 rme96
->capture_substream
= substream
;
1298 spin_unlock_irq(&rme96
->lock
);
1300 rme96_set_buffer_size_constraint(rme96
, runtime
);
1305 snd_rme96_playback_close(struct snd_pcm_substream
*substream
)
1307 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1310 spin_lock_irq(&rme96
->lock
);
1311 if (RME96_ISPLAYING(rme96
)) {
1312 snd_rme96_playback_stop(rme96
);
1314 rme96
->playback_substream
= NULL
;
1315 rme96
->playback_periodsize
= 0;
1316 spdif
= (rme96
->wcreg
& RME96_WCR_ADAT
) == 0;
1317 spin_unlock_irq(&rme96
->lock
);
1319 rme96
->spdif_ctl
->vd
[0].access
|= SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
1320 snd_ctl_notify(rme96
->card
, SNDRV_CTL_EVENT_MASK_VALUE
|
1321 SNDRV_CTL_EVENT_MASK_INFO
, &rme96
->spdif_ctl
->id
);
1327 snd_rme96_capture_close(struct snd_pcm_substream
*substream
)
1329 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1331 spin_lock_irq(&rme96
->lock
);
1332 if (RME96_ISRECORDING(rme96
)) {
1333 snd_rme96_capture_stop(rme96
);
1335 rme96
->capture_substream
= NULL
;
1336 rme96
->capture_periodsize
= 0;
1337 spin_unlock_irq(&rme96
->lock
);
1342 snd_rme96_playback_prepare(struct snd_pcm_substream
*substream
)
1344 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1346 spin_lock_irq(&rme96
->lock
);
1347 if (RME96_ISPLAYING(rme96
)) {
1348 snd_rme96_playback_stop(rme96
);
1350 writel(0, rme96
->iobase
+ RME96_IO_RESET_PLAY_POS
);
1351 spin_unlock_irq(&rme96
->lock
);
1356 snd_rme96_capture_prepare(struct snd_pcm_substream
*substream
)
1358 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1360 spin_lock_irq(&rme96
->lock
);
1361 if (RME96_ISRECORDING(rme96
)) {
1362 snd_rme96_capture_stop(rme96
);
1364 writel(0, rme96
->iobase
+ RME96_IO_RESET_REC_POS
);
1365 spin_unlock_irq(&rme96
->lock
);
1370 snd_rme96_playback_trigger(struct snd_pcm_substream
*substream
,
1373 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1376 case SNDRV_PCM_TRIGGER_START
:
1377 if (!RME96_ISPLAYING(rme96
)) {
1378 if (substream
!= rme96
->playback_substream
) {
1381 snd_rme96_playback_start(rme96
, 0);
1385 case SNDRV_PCM_TRIGGER_STOP
:
1386 if (RME96_ISPLAYING(rme96
)) {
1387 if (substream
!= rme96
->playback_substream
) {
1390 snd_rme96_playback_stop(rme96
);
1394 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1395 if (RME96_ISPLAYING(rme96
)) {
1396 snd_rme96_playback_stop(rme96
);
1400 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1401 if (!RME96_ISPLAYING(rme96
)) {
1402 snd_rme96_playback_start(rme96
, 1);
1413 snd_rme96_capture_trigger(struct snd_pcm_substream
*substream
,
1416 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1419 case SNDRV_PCM_TRIGGER_START
:
1420 if (!RME96_ISRECORDING(rme96
)) {
1421 if (substream
!= rme96
->capture_substream
) {
1424 snd_rme96_capture_start(rme96
, 0);
1428 case SNDRV_PCM_TRIGGER_STOP
:
1429 if (RME96_ISRECORDING(rme96
)) {
1430 if (substream
!= rme96
->capture_substream
) {
1433 snd_rme96_capture_stop(rme96
);
1437 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1438 if (RME96_ISRECORDING(rme96
)) {
1439 snd_rme96_capture_stop(rme96
);
1443 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1444 if (!RME96_ISRECORDING(rme96
)) {
1445 snd_rme96_capture_start(rme96
, 1);
1456 static snd_pcm_uframes_t
1457 snd_rme96_playback_pointer(struct snd_pcm_substream
*substream
)
1459 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1460 return snd_rme96_playback_ptr(rme96
);
1463 static snd_pcm_uframes_t
1464 snd_rme96_capture_pointer(struct snd_pcm_substream
*substream
)
1466 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1467 return snd_rme96_capture_ptr(rme96
);
1470 static struct snd_pcm_ops snd_rme96_playback_spdif_ops
= {
1471 .open
= snd_rme96_playback_spdif_open
,
1472 .close
= snd_rme96_playback_close
,
1473 .ioctl
= snd_pcm_lib_ioctl
,
1474 .hw_params
= snd_rme96_playback_hw_params
,
1475 .prepare
= snd_rme96_playback_prepare
,
1476 .trigger
= snd_rme96_playback_trigger
,
1477 .pointer
= snd_rme96_playback_pointer
,
1478 .copy
= snd_rme96_playback_copy
,
1479 .silence
= snd_rme96_playback_silence
,
1480 .mmap
= snd_pcm_lib_mmap_iomem
,
1483 static struct snd_pcm_ops snd_rme96_capture_spdif_ops
= {
1484 .open
= snd_rme96_capture_spdif_open
,
1485 .close
= snd_rme96_capture_close
,
1486 .ioctl
= snd_pcm_lib_ioctl
,
1487 .hw_params
= snd_rme96_capture_hw_params
,
1488 .prepare
= snd_rme96_capture_prepare
,
1489 .trigger
= snd_rme96_capture_trigger
,
1490 .pointer
= snd_rme96_capture_pointer
,
1491 .copy
= snd_rme96_capture_copy
,
1492 .mmap
= snd_pcm_lib_mmap_iomem
,
1495 static struct snd_pcm_ops snd_rme96_playback_adat_ops
= {
1496 .open
= snd_rme96_playback_adat_open
,
1497 .close
= snd_rme96_playback_close
,
1498 .ioctl
= snd_pcm_lib_ioctl
,
1499 .hw_params
= snd_rme96_playback_hw_params
,
1500 .prepare
= snd_rme96_playback_prepare
,
1501 .trigger
= snd_rme96_playback_trigger
,
1502 .pointer
= snd_rme96_playback_pointer
,
1503 .copy
= snd_rme96_playback_copy
,
1504 .silence
= snd_rme96_playback_silence
,
1505 .mmap
= snd_pcm_lib_mmap_iomem
,
1508 static struct snd_pcm_ops snd_rme96_capture_adat_ops
= {
1509 .open
= snd_rme96_capture_adat_open
,
1510 .close
= snd_rme96_capture_close
,
1511 .ioctl
= snd_pcm_lib_ioctl
,
1512 .hw_params
= snd_rme96_capture_hw_params
,
1513 .prepare
= snd_rme96_capture_prepare
,
1514 .trigger
= snd_rme96_capture_trigger
,
1515 .pointer
= snd_rme96_capture_pointer
,
1516 .copy
= snd_rme96_capture_copy
,
1517 .mmap
= snd_pcm_lib_mmap_iomem
,
1521 snd_rme96_free(void *private_data
)
1523 struct rme96
*rme96
= (struct rme96
*)private_data
;
1525 if (rme96
== NULL
) {
1528 if (rme96
->irq
>= 0) {
1529 snd_rme96_playback_stop(rme96
);
1530 snd_rme96_capture_stop(rme96
);
1531 rme96
->areg
&= ~RME96_AR_DAC_EN
;
1532 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1533 free_irq(rme96
->irq
, (void *)rme96
);
1536 if (rme96
->iobase
) {
1537 iounmap(rme96
->iobase
);
1538 rme96
->iobase
= NULL
;
1541 pci_release_regions(rme96
->pci
);
1544 pci_disable_device(rme96
->pci
);
1548 snd_rme96_free_spdif_pcm(struct snd_pcm
*pcm
)
1550 struct rme96
*rme96
= (struct rme96
*) pcm
->private_data
;
1551 rme96
->spdif_pcm
= NULL
;
1555 snd_rme96_free_adat_pcm(struct snd_pcm
*pcm
)
1557 struct rme96
*rme96
= (struct rme96
*) pcm
->private_data
;
1558 rme96
->adat_pcm
= NULL
;
1561 static int __devinit
1562 snd_rme96_create(struct rme96
*rme96
)
1564 struct pci_dev
*pci
= rme96
->pci
;
1568 spin_lock_init(&rme96
->lock
);
1570 if ((err
= pci_enable_device(pci
)) < 0)
1573 if ((err
= pci_request_regions(pci
, "RME96")) < 0)
1575 rme96
->port
= pci_resource_start(rme96
->pci
, 0);
1577 if ((rme96
->iobase
= ioremap_nocache(rme96
->port
, RME96_IO_SIZE
)) == 0) {
1578 snd_printk(KERN_ERR
"unable to remap memory region 0x%lx-0x%lx\n", rme96
->port
, rme96
->port
+ RME96_IO_SIZE
- 1);
1582 if (request_irq(pci
->irq
, snd_rme96_interrupt
, IRQF_SHARED
,
1584 snd_printk(KERN_ERR
"unable to grab IRQ %d\n", pci
->irq
);
1587 rme96
->irq
= pci
->irq
;
1589 /* read the card's revision number */
1590 pci_read_config_byte(pci
, 8, &rme96
->rev
);
1592 /* set up ALSA pcm device for S/PDIF */
1593 if ((err
= snd_pcm_new(rme96
->card
, "Digi96 IEC958", 0,
1594 1, 1, &rme96
->spdif_pcm
)) < 0)
1598 rme96
->spdif_pcm
->private_data
= rme96
;
1599 rme96
->spdif_pcm
->private_free
= snd_rme96_free_spdif_pcm
;
1600 strcpy(rme96
->spdif_pcm
->name
, "Digi96 IEC958");
1601 snd_pcm_set_ops(rme96
->spdif_pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_rme96_playback_spdif_ops
);
1602 snd_pcm_set_ops(rme96
->spdif_pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_rme96_capture_spdif_ops
);
1604 rme96
->spdif_pcm
->info_flags
= 0;
1606 /* set up ALSA pcm device for ADAT */
1607 if (pci
->device
== PCI_DEVICE_ID_RME_DIGI96
) {
1608 /* ADAT is not available on the base model */
1609 rme96
->adat_pcm
= NULL
;
1611 if ((err
= snd_pcm_new(rme96
->card
, "Digi96 ADAT", 1,
1612 1, 1, &rme96
->adat_pcm
)) < 0)
1616 rme96
->adat_pcm
->private_data
= rme96
;
1617 rme96
->adat_pcm
->private_free
= snd_rme96_free_adat_pcm
;
1618 strcpy(rme96
->adat_pcm
->name
, "Digi96 ADAT");
1619 snd_pcm_set_ops(rme96
->adat_pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_rme96_playback_adat_ops
);
1620 snd_pcm_set_ops(rme96
->adat_pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_rme96_capture_adat_ops
);
1622 rme96
->adat_pcm
->info_flags
= 0;
1625 rme96
->playback_periodsize
= 0;
1626 rme96
->capture_periodsize
= 0;
1628 /* make sure playback/capture is stopped, if by some reason active */
1629 snd_rme96_playback_stop(rme96
);
1630 snd_rme96_capture_stop(rme96
);
1632 /* set default values in registers */
1634 RME96_WCR_FREQ_1
| /* set 44.1 kHz playback */
1635 RME96_WCR_SEL
| /* normal playback */
1636 RME96_WCR_MASTER
| /* set to master clock mode */
1637 RME96_WCR_INP_0
; /* set coaxial input */
1639 rme96
->areg
= RME96_AR_FREQPAD_1
; /* set 44.1 kHz analog capture */
1641 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1642 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1645 writel(rme96
->areg
| RME96_AR_PD2
,
1646 rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1647 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1649 /* reset and enable the DAC (order is important). */
1650 snd_rme96_reset_dac(rme96
);
1651 rme96
->areg
|= RME96_AR_DAC_EN
;
1652 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1654 /* reset playback and record buffer pointers */
1655 writel(0, rme96
->iobase
+ RME96_IO_RESET_PLAY_POS
);
1656 writel(0, rme96
->iobase
+ RME96_IO_RESET_REC_POS
);
1659 rme96
->vol
[0] = rme96
->vol
[1] = 0;
1660 if (RME96_HAS_ANALOG_OUT(rme96
)) {
1661 snd_rme96_apply_dac_volume(rme96
);
1664 /* init switch interface */
1665 if ((err
= snd_rme96_create_switches(rme96
->card
, rme96
)) < 0) {
1669 /* init proc interface */
1670 snd_rme96_proc_init(rme96
);
1680 snd_rme96_proc_read(struct snd_info_entry
*entry
, struct snd_info_buffer
*buffer
)
1683 struct rme96
*rme96
= (struct rme96
*)entry
->private_data
;
1685 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1687 snd_iprintf(buffer
, rme96
->card
->longname
);
1688 snd_iprintf(buffer
, " (index #%d)\n", rme96
->card
->number
+ 1);
1690 snd_iprintf(buffer
, "\nGeneral settings\n");
1691 if (rme96
->wcreg
& RME96_WCR_IDIS
) {
1692 snd_iprintf(buffer
, " period size: N/A (interrupts "
1694 } else if (rme96
->wcreg
& RME96_WCR_ISEL
) {
1695 snd_iprintf(buffer
, " period size: 2048 bytes\n");
1697 snd_iprintf(buffer
, " period size: 8192 bytes\n");
1699 snd_iprintf(buffer
, "\nInput settings\n");
1700 switch (snd_rme96_getinputtype(rme96
)) {
1701 case RME96_INPUT_OPTICAL
:
1702 snd_iprintf(buffer
, " input: optical");
1704 case RME96_INPUT_COAXIAL
:
1705 snd_iprintf(buffer
, " input: coaxial");
1707 case RME96_INPUT_INTERNAL
:
1708 snd_iprintf(buffer
, " input: internal");
1710 case RME96_INPUT_XLR
:
1711 snd_iprintf(buffer
, " input: XLR");
1713 case RME96_INPUT_ANALOG
:
1714 snd_iprintf(buffer
, " input: analog");
1717 if (snd_rme96_capture_getrate(rme96
, &n
) < 0) {
1718 snd_iprintf(buffer
, "\n sample rate: no valid signal\n");
1721 snd_iprintf(buffer
, " (8 channels)\n");
1723 snd_iprintf(buffer
, " (2 channels)\n");
1725 snd_iprintf(buffer
, " sample rate: %d Hz\n",
1726 snd_rme96_capture_getrate(rme96
, &n
));
1728 if (rme96
->wcreg
& RME96_WCR_MODE24_2
) {
1729 snd_iprintf(buffer
, " sample format: 24 bit\n");
1731 snd_iprintf(buffer
, " sample format: 16 bit\n");
1734 snd_iprintf(buffer
, "\nOutput settings\n");
1735 if (rme96
->wcreg
& RME96_WCR_SEL
) {
1736 snd_iprintf(buffer
, " output signal: normal playback\n");
1738 snd_iprintf(buffer
, " output signal: same as input\n");
1740 snd_iprintf(buffer
, " sample rate: %d Hz\n",
1741 snd_rme96_playback_getrate(rme96
));
1742 if (rme96
->wcreg
& RME96_WCR_MODE24
) {
1743 snd_iprintf(buffer
, " sample format: 24 bit\n");
1745 snd_iprintf(buffer
, " sample format: 16 bit\n");
1747 if (rme96
->areg
& RME96_AR_WSEL
) {
1748 snd_iprintf(buffer
, " sample clock source: word clock\n");
1749 } else if (rme96
->wcreg
& RME96_WCR_MASTER
) {
1750 snd_iprintf(buffer
, " sample clock source: internal\n");
1751 } else if (snd_rme96_getinputtype(rme96
) == RME96_INPUT_ANALOG
) {
1752 snd_iprintf(buffer
, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1753 } else if (snd_rme96_capture_getrate(rme96
, &n
) < 0) {
1754 snd_iprintf(buffer
, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1756 snd_iprintf(buffer
, " sample clock source: autosync\n");
1758 if (rme96
->wcreg
& RME96_WCR_PRO
) {
1759 snd_iprintf(buffer
, " format: AES/EBU (professional)\n");
1761 snd_iprintf(buffer
, " format: IEC958 (consumer)\n");
1763 if (rme96
->wcreg
& RME96_WCR_EMP
) {
1764 snd_iprintf(buffer
, " emphasis: on\n");
1766 snd_iprintf(buffer
, " emphasis: off\n");
1768 if (rme96
->wcreg
& RME96_WCR_DOLBY
) {
1769 snd_iprintf(buffer
, " non-audio (dolby): on\n");
1771 snd_iprintf(buffer
, " non-audio (dolby): off\n");
1773 if (RME96_HAS_ANALOG_IN(rme96
)) {
1774 snd_iprintf(buffer
, "\nAnalog output settings\n");
1775 switch (snd_rme96_getmontracks(rme96
)) {
1776 case RME96_MONITOR_TRACKS_1_2
:
1777 snd_iprintf(buffer
, " monitored ADAT tracks: 1+2\n");
1779 case RME96_MONITOR_TRACKS_3_4
:
1780 snd_iprintf(buffer
, " monitored ADAT tracks: 3+4\n");
1782 case RME96_MONITOR_TRACKS_5_6
:
1783 snd_iprintf(buffer
, " monitored ADAT tracks: 5+6\n");
1785 case RME96_MONITOR_TRACKS_7_8
:
1786 snd_iprintf(buffer
, " monitored ADAT tracks: 7+8\n");
1789 switch (snd_rme96_getattenuation(rme96
)) {
1790 case RME96_ATTENUATION_0
:
1791 snd_iprintf(buffer
, " attenuation: 0 dB\n");
1793 case RME96_ATTENUATION_6
:
1794 snd_iprintf(buffer
, " attenuation: -6 dB\n");
1796 case RME96_ATTENUATION_12
:
1797 snd_iprintf(buffer
, " attenuation: -12 dB\n");
1799 case RME96_ATTENUATION_18
:
1800 snd_iprintf(buffer
, " attenuation: -18 dB\n");
1803 snd_iprintf(buffer
, " volume left: %u\n", rme96
->vol
[0]);
1804 snd_iprintf(buffer
, " volume right: %u\n", rme96
->vol
[1]);
1808 static void __devinit
1809 snd_rme96_proc_init(struct rme96
*rme96
)
1811 struct snd_info_entry
*entry
;
1813 if (! snd_card_proc_new(rme96
->card
, "rme96", &entry
))
1814 snd_info_set_text_ops(entry
, rme96
, snd_rme96_proc_read
);
1821 #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
1824 snd_rme96_get_loopback_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1826 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1828 spin_lock_irq(&rme96
->lock
);
1829 ucontrol
->value
.integer
.value
[0] = rme96
->wcreg
& RME96_WCR_SEL
? 0 : 1;
1830 spin_unlock_irq(&rme96
->lock
);
1834 snd_rme96_put_loopback_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1836 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1840 val
= ucontrol
->value
.integer
.value
[0] ? 0 : RME96_WCR_SEL
;
1841 spin_lock_irq(&rme96
->lock
);
1842 val
= (rme96
->wcreg
& ~RME96_WCR_SEL
) | val
;
1843 change
= val
!= rme96
->wcreg
;
1845 writel(val
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1846 spin_unlock_irq(&rme96
->lock
);
1851 snd_rme96_info_inputtype_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
1853 static char *_texts
[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1854 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1855 char *texts
[5] = { _texts
[0], _texts
[1], _texts
[2], _texts
[3], _texts
[4] };
1857 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
1859 switch (rme96
->pci
->device
) {
1860 case PCI_DEVICE_ID_RME_DIGI96
:
1861 case PCI_DEVICE_ID_RME_DIGI96_8
:
1862 uinfo
->value
.enumerated
.items
= 3;
1864 case PCI_DEVICE_ID_RME_DIGI96_8_PRO
:
1865 uinfo
->value
.enumerated
.items
= 4;
1867 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
:
1868 if (rme96
->rev
> 4) {
1870 uinfo
->value
.enumerated
.items
= 4;
1871 texts
[3] = _texts
[4]; /* Analog instead of XLR */
1874 uinfo
->value
.enumerated
.items
= 5;
1881 if (uinfo
->value
.enumerated
.item
> uinfo
->value
.enumerated
.items
- 1) {
1882 uinfo
->value
.enumerated
.item
= uinfo
->value
.enumerated
.items
- 1;
1884 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
1888 snd_rme96_get_inputtype_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1890 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1891 unsigned int items
= 3;
1893 spin_lock_irq(&rme96
->lock
);
1894 ucontrol
->value
.enumerated
.item
[0] = snd_rme96_getinputtype(rme96
);
1896 switch (rme96
->pci
->device
) {
1897 case PCI_DEVICE_ID_RME_DIGI96
:
1898 case PCI_DEVICE_ID_RME_DIGI96_8
:
1901 case PCI_DEVICE_ID_RME_DIGI96_8_PRO
:
1904 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
:
1905 if (rme96
->rev
> 4) {
1906 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1907 if (ucontrol
->value
.enumerated
.item
[0] == RME96_INPUT_ANALOG
) {
1908 ucontrol
->value
.enumerated
.item
[0] = RME96_INPUT_XLR
;
1919 if (ucontrol
->value
.enumerated
.item
[0] >= items
) {
1920 ucontrol
->value
.enumerated
.item
[0] = items
- 1;
1923 spin_unlock_irq(&rme96
->lock
);
1927 snd_rme96_put_inputtype_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1929 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1931 int change
, items
= 3;
1933 switch (rme96
->pci
->device
) {
1934 case PCI_DEVICE_ID_RME_DIGI96
:
1935 case PCI_DEVICE_ID_RME_DIGI96_8
:
1938 case PCI_DEVICE_ID_RME_DIGI96_8_PRO
:
1941 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
:
1942 if (rme96
->rev
> 4) {
1952 val
= ucontrol
->value
.enumerated
.item
[0] % items
;
1954 /* special case for PST */
1955 if (rme96
->pci
->device
== PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
&& rme96
->rev
> 4) {
1956 if (val
== RME96_INPUT_XLR
) {
1957 val
= RME96_INPUT_ANALOG
;
1961 spin_lock_irq(&rme96
->lock
);
1962 change
= (int)val
!= snd_rme96_getinputtype(rme96
);
1963 snd_rme96_setinputtype(rme96
, val
);
1964 spin_unlock_irq(&rme96
->lock
);
1969 snd_rme96_info_clockmode_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
1971 static char *texts
[3] = { "AutoSync", "Internal", "Word" };
1973 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
1975 uinfo
->value
.enumerated
.items
= 3;
1976 if (uinfo
->value
.enumerated
.item
> 2) {
1977 uinfo
->value
.enumerated
.item
= 2;
1979 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
1983 snd_rme96_get_clockmode_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1985 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1987 spin_lock_irq(&rme96
->lock
);
1988 ucontrol
->value
.enumerated
.item
[0] = snd_rme96_getclockmode(rme96
);
1989 spin_unlock_irq(&rme96
->lock
);
1993 snd_rme96_put_clockmode_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1995 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1999 val
= ucontrol
->value
.enumerated
.item
[0] % 3;
2000 spin_lock_irq(&rme96
->lock
);
2001 change
= (int)val
!= snd_rme96_getclockmode(rme96
);
2002 snd_rme96_setclockmode(rme96
, val
);
2003 spin_unlock_irq(&rme96
->lock
);
2008 snd_rme96_info_attenuation_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2010 static char *texts
[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2012 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2014 uinfo
->value
.enumerated
.items
= 4;
2015 if (uinfo
->value
.enumerated
.item
> 3) {
2016 uinfo
->value
.enumerated
.item
= 3;
2018 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
2022 snd_rme96_get_attenuation_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2024 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2026 spin_lock_irq(&rme96
->lock
);
2027 ucontrol
->value
.enumerated
.item
[0] = snd_rme96_getattenuation(rme96
);
2028 spin_unlock_irq(&rme96
->lock
);
2032 snd_rme96_put_attenuation_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2034 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2038 val
= ucontrol
->value
.enumerated
.item
[0] % 4;
2039 spin_lock_irq(&rme96
->lock
);
2041 change
= (int)val
!= snd_rme96_getattenuation(rme96
);
2042 snd_rme96_setattenuation(rme96
, val
);
2043 spin_unlock_irq(&rme96
->lock
);
2048 snd_rme96_info_montracks_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2050 static char *texts
[4] = { "1+2", "3+4", "5+6", "7+8" };
2052 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2054 uinfo
->value
.enumerated
.items
= 4;
2055 if (uinfo
->value
.enumerated
.item
> 3) {
2056 uinfo
->value
.enumerated
.item
= 3;
2058 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
2062 snd_rme96_get_montracks_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2064 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2066 spin_lock_irq(&rme96
->lock
);
2067 ucontrol
->value
.enumerated
.item
[0] = snd_rme96_getmontracks(rme96
);
2068 spin_unlock_irq(&rme96
->lock
);
2072 snd_rme96_put_montracks_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2074 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2078 val
= ucontrol
->value
.enumerated
.item
[0] % 4;
2079 spin_lock_irq(&rme96
->lock
);
2080 change
= (int)val
!= snd_rme96_getmontracks(rme96
);
2081 snd_rme96_setmontracks(rme96
, val
);
2082 spin_unlock_irq(&rme96
->lock
);
2086 static u32
snd_rme96_convert_from_aes(struct snd_aes_iec958
*aes
)
2089 val
|= (aes
->status
[0] & IEC958_AES0_PROFESSIONAL
) ? RME96_WCR_PRO
: 0;
2090 val
|= (aes
->status
[0] & IEC958_AES0_NONAUDIO
) ? RME96_WCR_DOLBY
: 0;
2091 if (val
& RME96_WCR_PRO
)
2092 val
|= (aes
->status
[0] & IEC958_AES0_PRO_EMPHASIS_5015
) ? RME96_WCR_EMP
: 0;
2094 val
|= (aes
->status
[0] & IEC958_AES0_CON_EMPHASIS_5015
) ? RME96_WCR_EMP
: 0;
2098 static void snd_rme96_convert_to_aes(struct snd_aes_iec958
*aes
, u32 val
)
2100 aes
->status
[0] = ((val
& RME96_WCR_PRO
) ? IEC958_AES0_PROFESSIONAL
: 0) |
2101 ((val
& RME96_WCR_DOLBY
) ? IEC958_AES0_NONAUDIO
: 0);
2102 if (val
& RME96_WCR_PRO
)
2103 aes
->status
[0] |= (val
& RME96_WCR_EMP
) ? IEC958_AES0_PRO_EMPHASIS_5015
: 0;
2105 aes
->status
[0] |= (val
& RME96_WCR_EMP
) ? IEC958_AES0_CON_EMPHASIS_5015
: 0;
2108 static int snd_rme96_control_spdif_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2110 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
2115 static int snd_rme96_control_spdif_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2117 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2119 snd_rme96_convert_to_aes(&ucontrol
->value
.iec958
, rme96
->wcreg_spdif
);
2123 static int snd_rme96_control_spdif_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2125 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2129 val
= snd_rme96_convert_from_aes(&ucontrol
->value
.iec958
);
2130 spin_lock_irq(&rme96
->lock
);
2131 change
= val
!= rme96
->wcreg_spdif
;
2132 rme96
->wcreg_spdif
= val
;
2133 spin_unlock_irq(&rme96
->lock
);
2137 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2139 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
2144 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2146 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2148 snd_rme96_convert_to_aes(&ucontrol
->value
.iec958
, rme96
->wcreg_spdif_stream
);
2152 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2154 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2158 val
= snd_rme96_convert_from_aes(&ucontrol
->value
.iec958
);
2159 spin_lock_irq(&rme96
->lock
);
2160 change
= val
!= rme96
->wcreg_spdif_stream
;
2161 rme96
->wcreg_spdif_stream
= val
;
2162 rme96
->wcreg
&= ~(RME96_WCR_PRO
| RME96_WCR_DOLBY
| RME96_WCR_EMP
);
2163 rme96
->wcreg
|= val
;
2164 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
2165 spin_unlock_irq(&rme96
->lock
);
2169 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2171 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
2176 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2178 ucontrol
->value
.iec958
.status
[0] = kcontrol
->private_value
;
2183 snd_rme96_dac_volume_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2185 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2187 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
2189 uinfo
->value
.integer
.min
= 0;
2190 uinfo
->value
.integer
.max
= RME96_185X_MAX_OUT(rme96
);
2195 snd_rme96_dac_volume_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*u
)
2197 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2199 spin_lock_irq(&rme96
->lock
);
2200 u
->value
.integer
.value
[0] = rme96
->vol
[0];
2201 u
->value
.integer
.value
[1] = rme96
->vol
[1];
2202 spin_unlock_irq(&rme96
->lock
);
2208 snd_rme96_dac_volume_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*u
)
2210 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2213 if (!RME96_HAS_ANALOG_OUT(rme96
)) {
2216 spin_lock_irq(&rme96
->lock
);
2217 if (u
->value
.integer
.value
[0] != rme96
->vol
[0]) {
2218 rme96
->vol
[0] = u
->value
.integer
.value
[0];
2221 if (u
->value
.integer
.value
[1] != rme96
->vol
[1]) {
2222 rme96
->vol
[1] = u
->value
.integer
.value
[1];
2226 snd_rme96_apply_dac_volume(rme96
);
2228 spin_unlock_irq(&rme96
->lock
);
2233 static struct snd_kcontrol_new snd_rme96_controls
[] = {
2235 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2236 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,DEFAULT
),
2237 .info
= snd_rme96_control_spdif_info
,
2238 .get
= snd_rme96_control_spdif_get
,
2239 .put
= snd_rme96_control_spdif_put
2242 .access
= SNDRV_CTL_ELEM_ACCESS_READWRITE
| SNDRV_CTL_ELEM_ACCESS_INACTIVE
,
2243 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2244 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PCM_STREAM
),
2245 .info
= snd_rme96_control_spdif_stream_info
,
2246 .get
= snd_rme96_control_spdif_stream_get
,
2247 .put
= snd_rme96_control_spdif_stream_put
2250 .access
= SNDRV_CTL_ELEM_ACCESS_READ
,
2251 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2252 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,CON_MASK
),
2253 .info
= snd_rme96_control_spdif_mask_info
,
2254 .get
= snd_rme96_control_spdif_mask_get
,
2255 .private_value
= IEC958_AES0_NONAUDIO
|
2256 IEC958_AES0_PROFESSIONAL
|
2257 IEC958_AES0_CON_EMPHASIS
2260 .access
= SNDRV_CTL_ELEM_ACCESS_READ
,
2261 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2262 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PRO_MASK
),
2263 .info
= snd_rme96_control_spdif_mask_info
,
2264 .get
= snd_rme96_control_spdif_mask_get
,
2265 .private_value
= IEC958_AES0_NONAUDIO
|
2266 IEC958_AES0_PROFESSIONAL
|
2267 IEC958_AES0_PRO_EMPHASIS
2270 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2271 .name
= "Input Connector",
2272 .info
= snd_rme96_info_inputtype_control
,
2273 .get
= snd_rme96_get_inputtype_control
,
2274 .put
= snd_rme96_put_inputtype_control
2277 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2278 .name
= "Loopback Input",
2279 .info
= snd_rme96_info_loopback_control
,
2280 .get
= snd_rme96_get_loopback_control
,
2281 .put
= snd_rme96_put_loopback_control
2284 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2285 .name
= "Sample Clock Source",
2286 .info
= snd_rme96_info_clockmode_control
,
2287 .get
= snd_rme96_get_clockmode_control
,
2288 .put
= snd_rme96_put_clockmode_control
2291 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2292 .name
= "Monitor Tracks",
2293 .info
= snd_rme96_info_montracks_control
,
2294 .get
= snd_rme96_get_montracks_control
,
2295 .put
= snd_rme96_put_montracks_control
2298 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2299 .name
= "Attenuation",
2300 .info
= snd_rme96_info_attenuation_control
,
2301 .get
= snd_rme96_get_attenuation_control
,
2302 .put
= snd_rme96_put_attenuation_control
2305 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2306 .name
= "DAC Playback Volume",
2307 .info
= snd_rme96_dac_volume_info
,
2308 .get
= snd_rme96_dac_volume_get
,
2309 .put
= snd_rme96_dac_volume_put
2314 snd_rme96_create_switches(struct snd_card
*card
,
2315 struct rme96
*rme96
)
2318 struct snd_kcontrol
*kctl
;
2320 for (idx
= 0; idx
< 7; idx
++) {
2321 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_rme96_controls
[idx
], rme96
))) < 0)
2323 if (idx
== 1) /* IEC958 (S/PDIF) Stream */
2324 rme96
->spdif_ctl
= kctl
;
2327 if (RME96_HAS_ANALOG_OUT(rme96
)) {
2328 for (idx
= 7; idx
< 10; idx
++)
2329 if ((err
= snd_ctl_add(card
, snd_ctl_new1(&snd_rme96_controls
[idx
], rme96
))) < 0)
2337 * Card initialisation
2340 static void snd_rme96_card_free(struct snd_card
*card
)
2342 snd_rme96_free(card
->private_data
);
2345 static int __devinit
2346 snd_rme96_probe(struct pci_dev
*pci
,
2347 const struct pci_device_id
*pci_id
)
2350 struct rme96
*rme96
;
2351 struct snd_card
*card
;
2355 if (dev
>= SNDRV_CARDS
) {
2362 if ((card
= snd_card_new(index
[dev
], id
[dev
], THIS_MODULE
,
2363 sizeof(struct rme96
))) == NULL
)
2365 card
->private_free
= snd_rme96_card_free
;
2366 rme96
= (struct rme96
*)card
->private_data
;
2369 snd_card_set_dev(card
, &pci
->dev
);
2370 if ((err
= snd_rme96_create(rme96
)) < 0) {
2371 snd_card_free(card
);
2375 strcpy(card
->driver
, "Digi96");
2376 switch (rme96
->pci
->device
) {
2377 case PCI_DEVICE_ID_RME_DIGI96
:
2378 strcpy(card
->shortname
, "RME Digi96");
2380 case PCI_DEVICE_ID_RME_DIGI96_8
:
2381 strcpy(card
->shortname
, "RME Digi96/8");
2383 case PCI_DEVICE_ID_RME_DIGI96_8_PRO
:
2384 strcpy(card
->shortname
, "RME Digi96/8 PRO");
2386 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
:
2387 pci_read_config_byte(rme96
->pci
, 8, &val
);
2389 strcpy(card
->shortname
, "RME Digi96/8 PAD");
2391 strcpy(card
->shortname
, "RME Digi96/8 PST");
2395 sprintf(card
->longname
, "%s at 0x%lx, irq %d", card
->shortname
,
2396 rme96
->port
, rme96
->irq
);
2398 if ((err
= snd_card_register(card
)) < 0) {
2399 snd_card_free(card
);
2402 pci_set_drvdata(pci
, card
);
2407 static void __devexit
snd_rme96_remove(struct pci_dev
*pci
)
2409 snd_card_free(pci_get_drvdata(pci
));
2410 pci_set_drvdata(pci
, NULL
);
2413 static struct pci_driver driver
= {
2414 .name
= "RME Digi96",
2415 .id_table
= snd_rme96_ids
,
2416 .probe
= snd_rme96_probe
,
2417 .remove
= __devexit_p(snd_rme96_remove
),
2420 static int __init
alsa_card_rme96_init(void)
2422 return pci_register_driver(&driver
);
2425 static void __exit
alsa_card_rme96_exit(void)
2427 pci_unregister_driver(&driver
);
2430 module_init(alsa_card_rme96_init
)
2431 module_exit(alsa_card_rme96_exit
)