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866d68461b83f25061f4e85af3df3b2840b3a339
[deliverable/linux.git] / sound / pci / rme9652 / hdsp.c
1 /*
2 * ALSA driver for RME Hammerfall DSP audio interface(s)
3 *
4 * Copyright (c) 2002 Paul Davis
5 * Marcus Andersson
6 * Thomas Charbonnel
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/firmware.h>
29 #include <linux/module.h>
30 #include <linux/math64.h>
31 #include <linux/vmalloc.h>
32
33 #include <sound/core.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/info.h>
37 #include <sound/asoundef.h>
38 #include <sound/rawmidi.h>
39 #include <sound/hwdep.h>
40 #include <sound/initval.h>
41 #include <sound/hdsp.h>
42
43 #include <asm/byteorder.h>
44 #include <asm/current.h>
45 #include <asm/io.h>
46
47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
49 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
50
51 module_param_array(index, int, NULL, 0444);
52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
53 module_param_array(id, charp, NULL, 0444);
54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
55 module_param_array(enable, bool, NULL, 0444);
56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
58 MODULE_DESCRIPTION("RME Hammerfall DSP");
59 MODULE_LICENSE("GPL");
60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
61 "{RME HDSP-9652},"
62 "{RME HDSP-9632}}");
63 MODULE_FIRMWARE("rpm_firmware.bin");
64 MODULE_FIRMWARE("multiface_firmware.bin");
65 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
66 MODULE_FIRMWARE("digiface_firmware.bin");
67 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
68
69 #define HDSP_MAX_CHANNELS 26
70 #define HDSP_MAX_DS_CHANNELS 14
71 #define HDSP_MAX_QS_CHANNELS 8
72 #define DIGIFACE_SS_CHANNELS 26
73 #define DIGIFACE_DS_CHANNELS 14
74 #define MULTIFACE_SS_CHANNELS 18
75 #define MULTIFACE_DS_CHANNELS 14
76 #define H9652_SS_CHANNELS 26
77 #define H9652_DS_CHANNELS 14
78 /* This does not include possible Analog Extension Boards
79 AEBs are detected at card initialization
80 */
81 #define H9632_SS_CHANNELS 12
82 #define H9632_DS_CHANNELS 8
83 #define H9632_QS_CHANNELS 4
84 #define RPM_CHANNELS 6
85
86 /* Write registers. These are defined as byte-offsets from the iobase value.
87 */
88 #define HDSP_resetPointer 0
89 #define HDSP_freqReg 0
90 #define HDSP_outputBufferAddress 32
91 #define HDSP_inputBufferAddress 36
92 #define HDSP_controlRegister 64
93 #define HDSP_interruptConfirmation 96
94 #define HDSP_outputEnable 128
95 #define HDSP_control2Reg 256
96 #define HDSP_midiDataOut0 352
97 #define HDSP_midiDataOut1 356
98 #define HDSP_fifoData 368
99 #define HDSP_inputEnable 384
100
101 /* Read registers. These are defined as byte-offsets from the iobase value
102 */
103
104 #define HDSP_statusRegister 0
105 #define HDSP_timecode 128
106 #define HDSP_status2Register 192
107 #define HDSP_midiDataIn0 360
108 #define HDSP_midiDataIn1 364
109 #define HDSP_midiStatusOut0 384
110 #define HDSP_midiStatusOut1 388
111 #define HDSP_midiStatusIn0 392
112 #define HDSP_midiStatusIn1 396
113 #define HDSP_fifoStatus 400
114
115 /* the meters are regular i/o-mapped registers, but offset
116 considerably from the rest. the peak registers are reset
117 when read; the least-significant 4 bits are full-scale counters;
118 the actual peak value is in the most-significant 24 bits.
119 */
120
121 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
122 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
123 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
124 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
125 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
126
127
128 /* This is for H9652 cards
129 Peak values are read downward from the base
130 Rms values are read upward
131 There are rms values for the outputs too
132 26*3 values are read in ss mode
133 14*3 in ds mode, with no gap between values
134 */
135 #define HDSP_9652_peakBase 7164
136 #define HDSP_9652_rmsBase 4096
137
138 /* c.f. the hdsp_9632_meters_t struct */
139 #define HDSP_9632_metersBase 4096
140
141 #define HDSP_IO_EXTENT 7168
142
143 /* control2 register bits */
144
145 #define HDSP_TMS 0x01
146 #define HDSP_TCK 0x02
147 #define HDSP_TDI 0x04
148 #define HDSP_JTAG 0x08
149 #define HDSP_PWDN 0x10
150 #define HDSP_PROGRAM 0x020
151 #define HDSP_CONFIG_MODE_0 0x040
152 #define HDSP_CONFIG_MODE_1 0x080
153 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
154 #define HDSP_BIGENDIAN_MODE 0x200
155 #define HDSP_RD_MULTIPLE 0x400
156 #define HDSP_9652_ENABLE_MIXER 0x800
157 #define HDSP_S200 0x800
158 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
159 #define HDSP_CYCLIC_MODE 0x1000
160 #define HDSP_TDO 0x10000000
161
162 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
163 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
164
165 /* Control Register bits */
166
167 #define HDSP_Start (1<<0) /* start engine */
168 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
169 #define HDSP_Latency1 (1<<2) /* [ see above ] */
170 #define HDSP_Latency2 (1<<3) /* [ see above ] */
171 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
172 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
173 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
174 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
175 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
176 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
177 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
178 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
179 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
180 #define HDSP_SyncRef2 (1<<13)
181 #define HDSP_SPDIFInputSelect0 (1<<14)
182 #define HDSP_SPDIFInputSelect1 (1<<15)
183 #define HDSP_SyncRef0 (1<<16)
184 #define HDSP_SyncRef1 (1<<17)
185 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
186 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
187 #define HDSP_Midi0InterruptEnable (1<<22)
188 #define HDSP_Midi1InterruptEnable (1<<23)
189 #define HDSP_LineOut (1<<24)
190 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
191 #define HDSP_ADGain1 (1<<26)
192 #define HDSP_DAGain0 (1<<27)
193 #define HDSP_DAGain1 (1<<28)
194 #define HDSP_PhoneGain0 (1<<29)
195 #define HDSP_PhoneGain1 (1<<30)
196 #define HDSP_QuadSpeed (1<<31)
197
198 /* RPM uses some of the registers for special purposes */
199 #define HDSP_RPM_Inp12 0x04A00
200 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */
201 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */
202 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */
203 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */
204 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */
205
206 #define HDSP_RPM_Inp34 0x32000
207 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */
208 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */
209 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */
210 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */
211 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */
212
213 #define HDSP_RPM_Bypass 0x01000
214
215 #define HDSP_RPM_Disconnect 0x00001
216
217 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
218 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
219 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
220 #define HDSP_ADGainLowGain 0
221
222 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
223 #define HDSP_DAGainHighGain HDSP_DAGainMask
224 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
225 #define HDSP_DAGainMinus10dBV 0
226
227 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
228 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
229 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
230 #define HDSP_PhoneGainMinus12dB 0
231
232 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
233 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
234
235 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
236 #define HDSP_SPDIFInputADAT1 0
237 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
238 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
239 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
240
241 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
242 #define HDSP_SyncRef_ADAT1 0
243 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
244 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
245 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
246 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
247 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
248
249 /* Sample Clock Sources */
250
251 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
252 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
253 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
254 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
255 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
256 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
257 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
258 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
259 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
260 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
261
262 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
263
264 #define HDSP_SYNC_FROM_WORD 0
265 #define HDSP_SYNC_FROM_SPDIF 1
266 #define HDSP_SYNC_FROM_ADAT1 2
267 #define HDSP_SYNC_FROM_ADAT_SYNC 3
268 #define HDSP_SYNC_FROM_ADAT2 4
269 #define HDSP_SYNC_FROM_ADAT3 5
270
271 /* SyncCheck status */
272
273 #define HDSP_SYNC_CHECK_NO_LOCK 0
274 #define HDSP_SYNC_CHECK_LOCK 1
275 #define HDSP_SYNC_CHECK_SYNC 2
276
277 /* AutoSync references - used by "autosync_ref" control switch */
278
279 #define HDSP_AUTOSYNC_FROM_WORD 0
280 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
281 #define HDSP_AUTOSYNC_FROM_SPDIF 2
282 #define HDSP_AUTOSYNC_FROM_NONE 3
283 #define HDSP_AUTOSYNC_FROM_ADAT1 4
284 #define HDSP_AUTOSYNC_FROM_ADAT2 5
285 #define HDSP_AUTOSYNC_FROM_ADAT3 6
286
287 /* Possible sources of S/PDIF input */
288
289 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
290 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
291 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
292 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
293
294 #define HDSP_Frequency32KHz HDSP_Frequency0
295 #define HDSP_Frequency44_1KHz HDSP_Frequency1
296 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
297 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
298 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
299 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
300 /* For H9632 cards */
301 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
302 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
303 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
304 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
305 return 104857600000000 / rate; // 100 MHz
306 return 110100480000000 / rate; // 105 MHz
307 */
308 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
309
310 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
311 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
312
313 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
314 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
315
316 /* Status Register bits */
317
318 #define HDSP_audioIRQPending (1<<0)
319 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
320 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
321 #define HDSP_Lock1 (1<<2)
322 #define HDSP_Lock0 (1<<3)
323 #define HDSP_SPDIFSync (1<<4)
324 #define HDSP_TimecodeLock (1<<5)
325 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
326 #define HDSP_Sync2 (1<<16)
327 #define HDSP_Sync1 (1<<17)
328 #define HDSP_Sync0 (1<<18)
329 #define HDSP_DoubleSpeedStatus (1<<19)
330 #define HDSP_ConfigError (1<<20)
331 #define HDSP_DllError (1<<21)
332 #define HDSP_spdifFrequency0 (1<<22)
333 #define HDSP_spdifFrequency1 (1<<23)
334 #define HDSP_spdifFrequency2 (1<<24)
335 #define HDSP_SPDIFErrorFlag (1<<25)
336 #define HDSP_BufferID (1<<26)
337 #define HDSP_TimecodeSync (1<<27)
338 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
339 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
340 #define HDSP_midi0IRQPending (1<<30)
341 #define HDSP_midi1IRQPending (1<<31)
342
343 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
344 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
345 HDSP_spdifFrequency1|\
346 HDSP_spdifFrequency2|\
347 HDSP_spdifFrequency3)
348
349 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
350 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
351 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
352
353 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
354 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
355 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
356
357 /* This is for H9632 cards */
358 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
359 HDSP_spdifFrequency1|\
360 HDSP_spdifFrequency2)
361 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
362 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
363
364 /* Status2 Register bits */
365
366 #define HDSP_version0 (1<<0)
367 #define HDSP_version1 (1<<1)
368 #define HDSP_version2 (1<<2)
369 #define HDSP_wc_lock (1<<3)
370 #define HDSP_wc_sync (1<<4)
371 #define HDSP_inp_freq0 (1<<5)
372 #define HDSP_inp_freq1 (1<<6)
373 #define HDSP_inp_freq2 (1<<7)
374 #define HDSP_SelSyncRef0 (1<<8)
375 #define HDSP_SelSyncRef1 (1<<9)
376 #define HDSP_SelSyncRef2 (1<<10)
377
378 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
379
380 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
381 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
382 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
383 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
384 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
385 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
386 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
387 /* FIXME : more values for 9632 cards ? */
388
389 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
390 #define HDSP_SelSyncRef_ADAT1 0
391 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
392 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
393 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
394 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
395 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
396
397 /* Card state flags */
398
399 #define HDSP_InitializationComplete (1<<0)
400 #define HDSP_FirmwareLoaded (1<<1)
401 #define HDSP_FirmwareCached (1<<2)
402
403 /* FIFO wait times, defined in terms of 1/10ths of msecs */
404
405 #define HDSP_LONG_WAIT 5000
406 #define HDSP_SHORT_WAIT 30
407
408 #define UNITY_GAIN 32768
409 #define MINUS_INFINITY_GAIN 0
410
411 /* the size of a substream (1 mono data stream) */
412
413 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
414 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
415
416 /* the size of the area we need to allocate for DMA transfers. the
417 size is the same regardless of the number of channels - the
418 Multiface still uses the same memory area.
419
420 Note that we allocate 1 more channel than is apparently needed
421 because the h/w seems to write 1 byte beyond the end of the last
422 page. Sigh.
423 */
424
425 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
426 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
427
428 #define HDSP_FIRMWARE_SIZE (24413 * 4)
429
430 struct hdsp_9632_meters {
431 u32 input_peak[16];
432 u32 playback_peak[16];
433 u32 output_peak[16];
434 u32 xxx_peak[16];
435 u32 padding[64];
436 u32 input_rms_low[16];
437 u32 playback_rms_low[16];
438 u32 output_rms_low[16];
439 u32 xxx_rms_low[16];
440 u32 input_rms_high[16];
441 u32 playback_rms_high[16];
442 u32 output_rms_high[16];
443 u32 xxx_rms_high[16];
444 };
445
446 struct hdsp_midi {
447 struct hdsp *hdsp;
448 int id;
449 struct snd_rawmidi *rmidi;
450 struct snd_rawmidi_substream *input;
451 struct snd_rawmidi_substream *output;
452 char istimer; /* timer in use */
453 struct timer_list timer;
454 spinlock_t lock;
455 int pending;
456 };
457
458 struct hdsp {
459 spinlock_t lock;
460 struct snd_pcm_substream *capture_substream;
461 struct snd_pcm_substream *playback_substream;
462 struct hdsp_midi midi[2];
463 struct tasklet_struct midi_tasklet;
464 int use_midi_tasklet;
465 int precise_ptr;
466 u32 control_register; /* cached value */
467 u32 control2_register; /* cached value */
468 u32 creg_spdif;
469 u32 creg_spdif_stream;
470 int clock_source_locked;
471 char *card_name; /* digiface/multiface/rpm */
472 enum HDSP_IO_Type io_type; /* ditto, but for code use */
473 unsigned short firmware_rev;
474 unsigned short state; /* stores state bits */
475 const struct firmware *firmware;
476 u32 *fw_uploaded;
477 size_t period_bytes; /* guess what this is */
478 unsigned char max_channels;
479 unsigned char qs_in_channels; /* quad speed mode for H9632 */
480 unsigned char ds_in_channels;
481 unsigned char ss_in_channels; /* different for multiface/digiface */
482 unsigned char qs_out_channels;
483 unsigned char ds_out_channels;
484 unsigned char ss_out_channels;
485
486 struct snd_dma_buffer capture_dma_buf;
487 struct snd_dma_buffer playback_dma_buf;
488 unsigned char *capture_buffer; /* suitably aligned address */
489 unsigned char *playback_buffer; /* suitably aligned address */
490
491 pid_t capture_pid;
492 pid_t playback_pid;
493 int running;
494 int system_sample_rate;
495 char *channel_map;
496 int dev;
497 int irq;
498 unsigned long port;
499 void __iomem *iobase;
500 struct snd_card *card;
501 struct snd_pcm *pcm;
502 struct snd_hwdep *hwdep;
503 struct pci_dev *pci;
504 struct snd_kcontrol *spdif_ctl;
505 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
506 unsigned int dds_value; /* last value written to freq register */
507 };
508
509 /* These tables map the ALSA channels 1..N to the channels that we
510 need to use in order to find the relevant channel buffer. RME
511 refer to this kind of mapping as between "the ADAT channel and
512 the DMA channel." We index it using the logical audio channel,
513 and the value is the DMA channel (i.e. channel buffer number)
514 where the data for that channel can be read/written from/to.
515 */
516
517 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
518 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
519 18, 19, 20, 21, 22, 23, 24, 25
520 };
521
522 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
523 /* Analog */
524 0, 1, 2, 3, 4, 5, 6, 7,
525 /* ADAT 2 */
526 16, 17, 18, 19, 20, 21, 22, 23,
527 /* SPDIF */
528 24, 25,
529 -1, -1, -1, -1, -1, -1, -1, -1
530 };
531
532 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
533 /* ADAT channels are remapped */
534 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
535 /* channels 12 and 13 are S/PDIF */
536 24, 25,
537 /* others don't exist */
538 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
539 };
540
541 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
542 /* ADAT channels */
543 0, 1, 2, 3, 4, 5, 6, 7,
544 /* SPDIF */
545 8, 9,
546 /* Analog */
547 10, 11,
548 /* AO4S-192 and AI4S-192 extension boards */
549 12, 13, 14, 15,
550 /* others don't exist */
551 -1, -1, -1, -1, -1, -1, -1, -1,
552 -1, -1
553 };
554
555 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
556 /* ADAT */
557 1, 3, 5, 7,
558 /* SPDIF */
559 8, 9,
560 /* Analog */
561 10, 11,
562 /* AO4S-192 and AI4S-192 extension boards */
563 12, 13, 14, 15,
564 /* others don't exist */
565 -1, -1, -1, -1, -1, -1, -1, -1,
566 -1, -1, -1, -1, -1, -1
567 };
568
569 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
570 /* ADAT is disabled in this mode */
571 /* SPDIF */
572 8, 9,
573 /* Analog */
574 10, 11,
575 /* AO4S-192 and AI4S-192 extension boards */
576 12, 13, 14, 15,
577 /* others don't exist */
578 -1, -1, -1, -1, -1, -1, -1, -1,
579 -1, -1, -1, -1, -1, -1, -1, -1,
580 -1, -1
581 };
582
583 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
584 {
585 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
586 dmab->dev.dev = snd_dma_pci_data(pci);
587 if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
588 if (dmab->bytes >= size)
589 return 0;
590 }
591 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
592 size, dmab) < 0)
593 return -ENOMEM;
594 return 0;
595 }
596
597 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
598 {
599 if (dmab->area) {
600 dmab->dev.dev = NULL; /* make it anonymous */
601 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
602 }
603 }
604
605
606 static DEFINE_PCI_DEVICE_TABLE(snd_hdsp_ids) = {
607 {
608 .vendor = PCI_VENDOR_ID_XILINX,
609 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
610 .subvendor = PCI_ANY_ID,
611 .subdevice = PCI_ANY_ID,
612 }, /* RME Hammerfall-DSP */
613 { 0, },
614 };
615
616 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
617
618 /* prototypes */
619 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
620 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
621 static int snd_hdsp_enable_io (struct hdsp *hdsp);
622 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
623 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
624 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
625 static int hdsp_autosync_ref(struct hdsp *hdsp);
626 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
627 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
628
629 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
630 {
631 switch (hdsp->io_type) {
632 case Multiface:
633 case Digiface:
634 case RPM:
635 default:
636 if (hdsp->firmware_rev == 0xa)
637 return (64 * out) + (32 + (in));
638 else
639 return (52 * out) + (26 + (in));
640 case H9632:
641 return (32 * out) + (16 + (in));
642 case H9652:
643 return (52 * out) + (26 + (in));
644 }
645 }
646
647 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
648 {
649 switch (hdsp->io_type) {
650 case Multiface:
651 case Digiface:
652 case RPM:
653 default:
654 if (hdsp->firmware_rev == 0xa)
655 return (64 * out) + in;
656 else
657 return (52 * out) + in;
658 case H9632:
659 return (32 * out) + in;
660 case H9652:
661 return (52 * out) + in;
662 }
663 }
664
665 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
666 {
667 writel(val, hdsp->iobase + reg);
668 }
669
670 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
671 {
672 return readl (hdsp->iobase + reg);
673 }
674
675 static int hdsp_check_for_iobox (struct hdsp *hdsp)
676 {
677 int i;
678
679 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
680 for (i = 0; i < 500; i++) {
681 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
682 HDSP_ConfigError)) {
683 if (i) {
684 snd_printd("Hammerfall-DSP: IO box found after %d ms\n",
685 (20 * i));
686 }
687 return 0;
688 }
689 msleep(20);
690 }
691 snd_printk(KERN_ERR "Hammerfall-DSP: no IO box connected!\n");
692 hdsp->state &= ~HDSP_FirmwareLoaded;
693 return -EIO;
694 }
695
696 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
697 unsigned int delay)
698 {
699 unsigned int i;
700
701 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
702 return 0;
703
704 for (i = 0; i != loops; ++i) {
705 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
706 msleep(delay);
707 else {
708 snd_printd("Hammerfall-DSP: iobox found after %ums!\n",
709 i * delay);
710 return 0;
711 }
712 }
713
714 snd_printk("Hammerfall-DSP: no IO box connected!\n");
715 hdsp->state &= ~HDSP_FirmwareLoaded;
716 return -EIO;
717 }
718
719 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
720
721 int i;
722 unsigned long flags;
723 const u32 *cache;
724
725 if (hdsp->fw_uploaded)
726 cache = hdsp->fw_uploaded;
727 else {
728 if (!hdsp->firmware)
729 return -ENODEV;
730 cache = (u32 *)hdsp->firmware->data;
731 if (!cache)
732 return -ENODEV;
733 }
734
735 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
736
737 snd_printk ("Hammerfall-DSP: loading firmware\n");
738
739 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
740 hdsp_write (hdsp, HDSP_fifoData, 0);
741
742 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
743 snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n");
744 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
745 return -EIO;
746 }
747
748 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
749
750 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
751 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
752 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
753 snd_printk ("Hammerfall-DSP: timeout during firmware loading\n");
754 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
755 return -EIO;
756 }
757 }
758
759 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
760 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
761
762 ssleep(3);
763 #ifdef SNDRV_BIG_ENDIAN
764 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
765 #else
766 hdsp->control2_register = 0;
767 #endif
768 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
769 snd_printk ("Hammerfall-DSP: finished firmware loading\n");
770
771 }
772 if (hdsp->state & HDSP_InitializationComplete) {
773 snd_printk(KERN_INFO "Hammerfall-DSP: firmware loaded from cache, restoring defaults\n");
774 spin_lock_irqsave(&hdsp->lock, flags);
775 snd_hdsp_set_defaults(hdsp);
776 spin_unlock_irqrestore(&hdsp->lock, flags);
777 }
778
779 hdsp->state |= HDSP_FirmwareLoaded;
780
781 return 0;
782 }
783
784 static int hdsp_get_iobox_version (struct hdsp *hdsp)
785 {
786 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
787
788 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
789 hdsp_write(hdsp, HDSP_fifoData, 0);
790
791 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
792 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
793 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
794 }
795
796 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
797 hdsp_write (hdsp, HDSP_fifoData, 0);
798 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
799 hdsp->io_type = Multiface;
800 snd_printk("Hammerfall-DSP: Multiface found\n");
801 return 0;
802 }
803
804 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
805 hdsp_write(hdsp, HDSP_fifoData, 0);
806 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
807 hdsp->io_type = Digiface;
808 snd_printk("Hammerfall-DSP: Digiface found\n");
809 return 0;
810 }
811
812 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
813 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
814 hdsp_write(hdsp, HDSP_fifoData, 0);
815 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
816 hdsp->io_type = Multiface;
817 snd_printk("Hammerfall-DSP: Multiface found\n");
818 return 0;
819 }
820
821 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
822 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
823 hdsp_write(hdsp, HDSP_fifoData, 0);
824 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
825 hdsp->io_type = Multiface;
826 snd_printk("Hammerfall-DSP: Multiface found\n");
827 return 0;
828 }
829
830 hdsp->io_type = RPM;
831 snd_printk("Hammerfall-DSP: RPM found\n");
832 return 0;
833 } else {
834 /* firmware was already loaded, get iobox type */
835 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
836 hdsp->io_type = RPM;
837 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
838 hdsp->io_type = Multiface;
839 else
840 hdsp->io_type = Digiface;
841 }
842 return 0;
843 }
844
845
846 static int hdsp_request_fw_loader(struct hdsp *hdsp);
847
848 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
849 {
850 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
851 return 0;
852 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
853 hdsp->state &= ~HDSP_FirmwareLoaded;
854 if (! load_on_demand)
855 return -EIO;
856 snd_printk(KERN_ERR "Hammerfall-DSP: firmware not present.\n");
857 /* try to load firmware */
858 if (! (hdsp->state & HDSP_FirmwareCached)) {
859 if (! hdsp_request_fw_loader(hdsp))
860 return 0;
861 snd_printk(KERN_ERR
862 "Hammerfall-DSP: No firmware loaded nor "
863 "cached, please upload firmware.\n");
864 return -EIO;
865 }
866 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
867 snd_printk(KERN_ERR
868 "Hammerfall-DSP: Firmware loading from "
869 "cache failed, please upload manually.\n");
870 return -EIO;
871 }
872 }
873 return 0;
874 }
875
876
877 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
878 {
879 int i;
880
881 /* the fifoStatus registers reports on how many words
882 are available in the command FIFO.
883 */
884
885 for (i = 0; i < timeout; i++) {
886
887 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
888 return 0;
889
890 /* not very friendly, but we only do this during a firmware
891 load and changing the mixer, so we just put up with it.
892 */
893
894 udelay (100);
895 }
896
897 snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n",
898 count, timeout);
899 return -1;
900 }
901
902 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
903 {
904 if (addr >= HDSP_MATRIX_MIXER_SIZE)
905 return 0;
906
907 return hdsp->mixer_matrix[addr];
908 }
909
910 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
911 {
912 unsigned int ad;
913
914 if (addr >= HDSP_MATRIX_MIXER_SIZE)
915 return -1;
916
917 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
918
919 /* from martin bjornsen:
920
921 "You can only write dwords to the
922 mixer memory which contain two
923 mixer values in the low and high
924 word. So if you want to change
925 value 0 you have to read value 1
926 from the cache and write both to
927 the first dword in the mixer
928 memory."
929 */
930
931 if (hdsp->io_type == H9632 && addr >= 512)
932 return 0;
933
934 if (hdsp->io_type == H9652 && addr >= 1352)
935 return 0;
936
937 hdsp->mixer_matrix[addr] = data;
938
939
940 /* `addr' addresses a 16-bit wide address, but
941 the address space accessed via hdsp_write
942 uses byte offsets. put another way, addr
943 varies from 0 to 1351, but to access the
944 corresponding memory location, we need
945 to access 0 to 2703 ...
946 */
947 ad = addr/2;
948
949 hdsp_write (hdsp, 4096 + (ad*4),
950 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
951 hdsp->mixer_matrix[addr&0x7fe]);
952
953 return 0;
954
955 } else {
956
957 ad = (addr << 16) + data;
958
959 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
960 return -1;
961
962 hdsp_write (hdsp, HDSP_fifoData, ad);
963 hdsp->mixer_matrix[addr] = data;
964
965 }
966
967 return 0;
968 }
969
970 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
971 {
972 unsigned long flags;
973 int ret = 1;
974
975 spin_lock_irqsave(&hdsp->lock, flags);
976 if ((hdsp->playback_pid != hdsp->capture_pid) &&
977 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
978 ret = 0;
979 spin_unlock_irqrestore(&hdsp->lock, flags);
980 return ret;
981 }
982
983 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
984 {
985 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
986 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
987
988 /* For the 9632, the mask is different */
989 if (hdsp->io_type == H9632)
990 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
991
992 if (status & HDSP_SPDIFErrorFlag)
993 return 0;
994
995 switch (rate_bits) {
996 case HDSP_spdifFrequency32KHz: return 32000;
997 case HDSP_spdifFrequency44_1KHz: return 44100;
998 case HDSP_spdifFrequency48KHz: return 48000;
999 case HDSP_spdifFrequency64KHz: return 64000;
1000 case HDSP_spdifFrequency88_2KHz: return 88200;
1001 case HDSP_spdifFrequency96KHz: return 96000;
1002 case HDSP_spdifFrequency128KHz:
1003 if (hdsp->io_type == H9632) return 128000;
1004 break;
1005 case HDSP_spdifFrequency176_4KHz:
1006 if (hdsp->io_type == H9632) return 176400;
1007 break;
1008 case HDSP_spdifFrequency192KHz:
1009 if (hdsp->io_type == H9632) return 192000;
1010 break;
1011 default:
1012 break;
1013 }
1014 snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
1015 return 0;
1016 }
1017
1018 static int hdsp_external_sample_rate(struct hdsp *hdsp)
1019 {
1020 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
1021 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1022
1023 /* For the 9632 card, there seems to be no bit for indicating external
1024 * sample rate greater than 96kHz. The card reports the corresponding
1025 * single speed. So the best means seems to get spdif rate when
1026 * autosync reference is spdif */
1027 if (hdsp->io_type == H9632 &&
1028 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1029 return hdsp_spdif_sample_rate(hdsp);
1030
1031 switch (rate_bits) {
1032 case HDSP_systemFrequency32: return 32000;
1033 case HDSP_systemFrequency44_1: return 44100;
1034 case HDSP_systemFrequency48: return 48000;
1035 case HDSP_systemFrequency64: return 64000;
1036 case HDSP_systemFrequency88_2: return 88200;
1037 case HDSP_systemFrequency96: return 96000;
1038 default:
1039 return 0;
1040 }
1041 }
1042
1043 static void hdsp_compute_period_size(struct hdsp *hdsp)
1044 {
1045 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1046 }
1047
1048 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1049 {
1050 int position;
1051
1052 position = hdsp_read(hdsp, HDSP_statusRegister);
1053
1054 if (!hdsp->precise_ptr)
1055 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1056
1057 position &= HDSP_BufferPositionMask;
1058 position /= 4;
1059 position &= (hdsp->period_bytes/2) - 1;
1060 return position;
1061 }
1062
1063 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1064 {
1065 hdsp_write (hdsp, HDSP_resetPointer, 0);
1066 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1067 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1068 * requires (?) to write again DDS value after a reset pointer
1069 * (at least, it works like this) */
1070 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1071 }
1072
1073 static void hdsp_start_audio(struct hdsp *s)
1074 {
1075 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1076 hdsp_write(s, HDSP_controlRegister, s->control_register);
1077 }
1078
1079 static void hdsp_stop_audio(struct hdsp *s)
1080 {
1081 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1082 hdsp_write(s, HDSP_controlRegister, s->control_register);
1083 }
1084
1085 static void hdsp_silence_playback(struct hdsp *hdsp)
1086 {
1087 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1088 }
1089
1090 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1091 {
1092 int n;
1093
1094 spin_lock_irq(&s->lock);
1095
1096 frames >>= 7;
1097 n = 0;
1098 while (frames) {
1099 n++;
1100 frames >>= 1;
1101 }
1102
1103 s->control_register &= ~HDSP_LatencyMask;
1104 s->control_register |= hdsp_encode_latency(n);
1105
1106 hdsp_write(s, HDSP_controlRegister, s->control_register);
1107
1108 hdsp_compute_period_size(s);
1109
1110 spin_unlock_irq(&s->lock);
1111
1112 return 0;
1113 }
1114
1115 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1116 {
1117 u64 n;
1118
1119 if (rate >= 112000)
1120 rate /= 4;
1121 else if (rate >= 56000)
1122 rate /= 2;
1123
1124 n = DDS_NUMERATOR;
1125 n = div_u64(n, rate);
1126 /* n should be less than 2^32 for being written to FREQ register */
1127 snd_BUG_ON(n >> 32);
1128 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1129 value to write it after a reset */
1130 hdsp->dds_value = n;
1131 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1132 }
1133
1134 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1135 {
1136 int reject_if_open = 0;
1137 int current_rate;
1138 int rate_bits;
1139
1140 /* ASSUMPTION: hdsp->lock is either held, or
1141 there is no need for it (e.g. during module
1142 initialization).
1143 */
1144
1145 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1146 if (called_internally) {
1147 /* request from ctl or card initialization */
1148 snd_printk(KERN_ERR "Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n");
1149 return -1;
1150 } else {
1151 /* hw_param request while in AutoSync mode */
1152 int external_freq = hdsp_external_sample_rate(hdsp);
1153 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1154
1155 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1156 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in double speed mode\n");
1157 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1158 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in quad speed mode\n");
1159 else if (rate != external_freq) {
1160 snd_printk(KERN_INFO "Hammerfall-DSP: No AutoSync source for requested rate\n");
1161 return -1;
1162 }
1163 }
1164 }
1165
1166 current_rate = hdsp->system_sample_rate;
1167
1168 /* Changing from a "single speed" to a "double speed" rate is
1169 not allowed if any substreams are open. This is because
1170 such a change causes a shift in the location of
1171 the DMA buffers and a reduction in the number of available
1172 buffers.
1173
1174 Note that a similar but essentially insoluble problem
1175 exists for externally-driven rate changes. All we can do
1176 is to flag rate changes in the read/write routines. */
1177
1178 if (rate > 96000 && hdsp->io_type != H9632)
1179 return -EINVAL;
1180
1181 switch (rate) {
1182 case 32000:
1183 if (current_rate > 48000)
1184 reject_if_open = 1;
1185 rate_bits = HDSP_Frequency32KHz;
1186 break;
1187 case 44100:
1188 if (current_rate > 48000)
1189 reject_if_open = 1;
1190 rate_bits = HDSP_Frequency44_1KHz;
1191 break;
1192 case 48000:
1193 if (current_rate > 48000)
1194 reject_if_open = 1;
1195 rate_bits = HDSP_Frequency48KHz;
1196 break;
1197 case 64000:
1198 if (current_rate <= 48000 || current_rate > 96000)
1199 reject_if_open = 1;
1200 rate_bits = HDSP_Frequency64KHz;
1201 break;
1202 case 88200:
1203 if (current_rate <= 48000 || current_rate > 96000)
1204 reject_if_open = 1;
1205 rate_bits = HDSP_Frequency88_2KHz;
1206 break;
1207 case 96000:
1208 if (current_rate <= 48000 || current_rate > 96000)
1209 reject_if_open = 1;
1210 rate_bits = HDSP_Frequency96KHz;
1211 break;
1212 case 128000:
1213 if (current_rate < 128000)
1214 reject_if_open = 1;
1215 rate_bits = HDSP_Frequency128KHz;
1216 break;
1217 case 176400:
1218 if (current_rate < 128000)
1219 reject_if_open = 1;
1220 rate_bits = HDSP_Frequency176_4KHz;
1221 break;
1222 case 192000:
1223 if (current_rate < 128000)
1224 reject_if_open = 1;
1225 rate_bits = HDSP_Frequency192KHz;
1226 break;
1227 default:
1228 return -EINVAL;
1229 }
1230
1231 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1232 snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1233 hdsp->capture_pid,
1234 hdsp->playback_pid);
1235 return -EBUSY;
1236 }
1237
1238 hdsp->control_register &= ~HDSP_FrequencyMask;
1239 hdsp->control_register |= rate_bits;
1240 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1241
1242 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1243 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1244 hdsp_set_dds_value(hdsp, rate);
1245
1246 if (rate >= 128000) {
1247 hdsp->channel_map = channel_map_H9632_qs;
1248 } else if (rate > 48000) {
1249 if (hdsp->io_type == H9632)
1250 hdsp->channel_map = channel_map_H9632_ds;
1251 else
1252 hdsp->channel_map = channel_map_ds;
1253 } else {
1254 switch (hdsp->io_type) {
1255 case RPM:
1256 case Multiface:
1257 hdsp->channel_map = channel_map_mf_ss;
1258 break;
1259 case Digiface:
1260 case H9652:
1261 hdsp->channel_map = channel_map_df_ss;
1262 break;
1263 case H9632:
1264 hdsp->channel_map = channel_map_H9632_ss;
1265 break;
1266 default:
1267 /* should never happen */
1268 break;
1269 }
1270 }
1271
1272 hdsp->system_sample_rate = rate;
1273
1274 return 0;
1275 }
1276
1277 /*----------------------------------------------------------------------------
1278 MIDI
1279 ----------------------------------------------------------------------------*/
1280
1281 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1282 {
1283 /* the hardware already does the relevant bit-mask with 0xff */
1284 if (id)
1285 return hdsp_read(hdsp, HDSP_midiDataIn1);
1286 else
1287 return hdsp_read(hdsp, HDSP_midiDataIn0);
1288 }
1289
1290 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1291 {
1292 /* the hardware already does the relevant bit-mask with 0xff */
1293 if (id)
1294 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1295 else
1296 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1297 }
1298
1299 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1300 {
1301 if (id)
1302 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1303 else
1304 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1305 }
1306
1307 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1308 {
1309 int fifo_bytes_used;
1310
1311 if (id)
1312 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1313 else
1314 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1315
1316 if (fifo_bytes_used < 128)
1317 return 128 - fifo_bytes_used;
1318 else
1319 return 0;
1320 }
1321
1322 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1323 {
1324 while (snd_hdsp_midi_input_available (hdsp, id))
1325 snd_hdsp_midi_read_byte (hdsp, id);
1326 }
1327
1328 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1329 {
1330 unsigned long flags;
1331 int n_pending;
1332 int to_write;
1333 int i;
1334 unsigned char buf[128];
1335
1336 /* Output is not interrupt driven */
1337
1338 spin_lock_irqsave (&hmidi->lock, flags);
1339 if (hmidi->output) {
1340 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1341 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1342 if (n_pending > (int)sizeof (buf))
1343 n_pending = sizeof (buf);
1344
1345 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1346 for (i = 0; i < to_write; ++i)
1347 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1348 }
1349 }
1350 }
1351 }
1352 spin_unlock_irqrestore (&hmidi->lock, flags);
1353 return 0;
1354 }
1355
1356 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1357 {
1358 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1359 unsigned long flags;
1360 int n_pending;
1361 int i;
1362
1363 spin_lock_irqsave (&hmidi->lock, flags);
1364 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1365 if (hmidi->input) {
1366 if (n_pending > (int)sizeof (buf))
1367 n_pending = sizeof (buf);
1368 for (i = 0; i < n_pending; ++i)
1369 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1370 if (n_pending)
1371 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1372 } else {
1373 /* flush the MIDI input FIFO */
1374 while (--n_pending)
1375 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1376 }
1377 }
1378 hmidi->pending = 0;
1379 if (hmidi->id)
1380 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1381 else
1382 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1383 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1384 spin_unlock_irqrestore (&hmidi->lock, flags);
1385 return snd_hdsp_midi_output_write (hmidi);
1386 }
1387
1388 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1389 {
1390 struct hdsp *hdsp;
1391 struct hdsp_midi *hmidi;
1392 unsigned long flags;
1393 u32 ie;
1394
1395 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1396 hdsp = hmidi->hdsp;
1397 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1398 spin_lock_irqsave (&hdsp->lock, flags);
1399 if (up) {
1400 if (!(hdsp->control_register & ie)) {
1401 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1402 hdsp->control_register |= ie;
1403 }
1404 } else {
1405 hdsp->control_register &= ~ie;
1406 tasklet_kill(&hdsp->midi_tasklet);
1407 }
1408
1409 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1410 spin_unlock_irqrestore (&hdsp->lock, flags);
1411 }
1412
1413 static void snd_hdsp_midi_output_timer(unsigned long data)
1414 {
1415 struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
1416 unsigned long flags;
1417
1418 snd_hdsp_midi_output_write(hmidi);
1419 spin_lock_irqsave (&hmidi->lock, flags);
1420
1421 /* this does not bump hmidi->istimer, because the
1422 kernel automatically removed the timer when it
1423 expired, and we are now adding it back, thus
1424 leaving istimer wherever it was set before.
1425 */
1426
1427 if (hmidi->istimer) {
1428 hmidi->timer.expires = 1 + jiffies;
1429 add_timer(&hmidi->timer);
1430 }
1431
1432 spin_unlock_irqrestore (&hmidi->lock, flags);
1433 }
1434
1435 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1436 {
1437 struct hdsp_midi *hmidi;
1438 unsigned long flags;
1439
1440 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1441 spin_lock_irqsave (&hmidi->lock, flags);
1442 if (up) {
1443 if (!hmidi->istimer) {
1444 init_timer(&hmidi->timer);
1445 hmidi->timer.function = snd_hdsp_midi_output_timer;
1446 hmidi->timer.data = (unsigned long) hmidi;
1447 hmidi->timer.expires = 1 + jiffies;
1448 add_timer(&hmidi->timer);
1449 hmidi->istimer++;
1450 }
1451 } else {
1452 if (hmidi->istimer && --hmidi->istimer <= 0)
1453 del_timer (&hmidi->timer);
1454 }
1455 spin_unlock_irqrestore (&hmidi->lock, flags);
1456 if (up)
1457 snd_hdsp_midi_output_write(hmidi);
1458 }
1459
1460 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1461 {
1462 struct hdsp_midi *hmidi;
1463
1464 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1465 spin_lock_irq (&hmidi->lock);
1466 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1467 hmidi->input = substream;
1468 spin_unlock_irq (&hmidi->lock);
1469
1470 return 0;
1471 }
1472
1473 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1474 {
1475 struct hdsp_midi *hmidi;
1476
1477 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1478 spin_lock_irq (&hmidi->lock);
1479 hmidi->output = substream;
1480 spin_unlock_irq (&hmidi->lock);
1481
1482 return 0;
1483 }
1484
1485 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1486 {
1487 struct hdsp_midi *hmidi;
1488
1489 snd_hdsp_midi_input_trigger (substream, 0);
1490
1491 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1492 spin_lock_irq (&hmidi->lock);
1493 hmidi->input = NULL;
1494 spin_unlock_irq (&hmidi->lock);
1495
1496 return 0;
1497 }
1498
1499 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1500 {
1501 struct hdsp_midi *hmidi;
1502
1503 snd_hdsp_midi_output_trigger (substream, 0);
1504
1505 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1506 spin_lock_irq (&hmidi->lock);
1507 hmidi->output = NULL;
1508 spin_unlock_irq (&hmidi->lock);
1509
1510 return 0;
1511 }
1512
1513 static struct snd_rawmidi_ops snd_hdsp_midi_output =
1514 {
1515 .open = snd_hdsp_midi_output_open,
1516 .close = snd_hdsp_midi_output_close,
1517 .trigger = snd_hdsp_midi_output_trigger,
1518 };
1519
1520 static struct snd_rawmidi_ops snd_hdsp_midi_input =
1521 {
1522 .open = snd_hdsp_midi_input_open,
1523 .close = snd_hdsp_midi_input_close,
1524 .trigger = snd_hdsp_midi_input_trigger,
1525 };
1526
1527 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1528 {
1529 char buf[32];
1530
1531 hdsp->midi[id].id = id;
1532 hdsp->midi[id].rmidi = NULL;
1533 hdsp->midi[id].input = NULL;
1534 hdsp->midi[id].output = NULL;
1535 hdsp->midi[id].hdsp = hdsp;
1536 hdsp->midi[id].istimer = 0;
1537 hdsp->midi[id].pending = 0;
1538 spin_lock_init (&hdsp->midi[id].lock);
1539
1540 sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1541 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1542 return -1;
1543
1544 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1545 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1546
1547 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1548 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1549
1550 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1551 SNDRV_RAWMIDI_INFO_INPUT |
1552 SNDRV_RAWMIDI_INFO_DUPLEX;
1553
1554 return 0;
1555 }
1556
1557 /*-----------------------------------------------------------------------------
1558 Control Interface
1559 ----------------------------------------------------------------------------*/
1560
1561 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1562 {
1563 u32 val = 0;
1564 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1565 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1566 if (val & HDSP_SPDIFProfessional)
1567 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1568 else
1569 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1570 return val;
1571 }
1572
1573 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1574 {
1575 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1576 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1577 if (val & HDSP_SPDIFProfessional)
1578 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1579 else
1580 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1581 }
1582
1583 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1584 {
1585 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1586 uinfo->count = 1;
1587 return 0;
1588 }
1589
1590 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1591 {
1592 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1593
1594 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1595 return 0;
1596 }
1597
1598 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1599 {
1600 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1601 int change;
1602 u32 val;
1603
1604 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1605 spin_lock_irq(&hdsp->lock);
1606 change = val != hdsp->creg_spdif;
1607 hdsp->creg_spdif = val;
1608 spin_unlock_irq(&hdsp->lock);
1609 return change;
1610 }
1611
1612 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1613 {
1614 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1615 uinfo->count = 1;
1616 return 0;
1617 }
1618
1619 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1620 {
1621 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1622
1623 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1624 return 0;
1625 }
1626
1627 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1628 {
1629 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1630 int change;
1631 u32 val;
1632
1633 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1634 spin_lock_irq(&hdsp->lock);
1635 change = val != hdsp->creg_spdif_stream;
1636 hdsp->creg_spdif_stream = val;
1637 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1638 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1639 spin_unlock_irq(&hdsp->lock);
1640 return change;
1641 }
1642
1643 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1644 {
1645 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1646 uinfo->count = 1;
1647 return 0;
1648 }
1649
1650 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1651 {
1652 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1653 return 0;
1654 }
1655
1656 #define HDSP_SPDIF_IN(xname, xindex) \
1657 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1658 .name = xname, \
1659 .index = xindex, \
1660 .info = snd_hdsp_info_spdif_in, \
1661 .get = snd_hdsp_get_spdif_in, \
1662 .put = snd_hdsp_put_spdif_in }
1663
1664 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1665 {
1666 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1667 }
1668
1669 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1670 {
1671 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1672 hdsp->control_register |= hdsp_encode_spdif_in(in);
1673 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1674 return 0;
1675 }
1676
1677 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1678 {
1679 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1680 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1681
1682 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1683 uinfo->count = 1;
1684 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1685 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1686 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1687 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1688 return 0;
1689 }
1690
1691 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1692 {
1693 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1694
1695 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1696 return 0;
1697 }
1698
1699 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1700 {
1701 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1702 int change;
1703 unsigned int val;
1704
1705 if (!snd_hdsp_use_is_exclusive(hdsp))
1706 return -EBUSY;
1707 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1708 spin_lock_irq(&hdsp->lock);
1709 change = val != hdsp_spdif_in(hdsp);
1710 if (change)
1711 hdsp_set_spdif_input(hdsp, val);
1712 spin_unlock_irq(&hdsp->lock);
1713 return change;
1714 }
1715
1716 #define HDSP_SPDIF_OUT(xname, xindex) \
1717 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1718 .info = snd_hdsp_info_spdif_bits, \
1719 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1720
1721 static int hdsp_spdif_out(struct hdsp *hdsp)
1722 {
1723 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1724 }
1725
1726 static int hdsp_set_spdif_output(struct hdsp *hdsp, int out)
1727 {
1728 if (out)
1729 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1730 else
1731 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1732 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1733 return 0;
1734 }
1735
1736 #define snd_hdsp_info_spdif_bits snd_ctl_boolean_mono_info
1737
1738 static int snd_hdsp_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1739 {
1740 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1741
1742 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1743 return 0;
1744 }
1745
1746 static int snd_hdsp_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1747 {
1748 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1749 int change;
1750 unsigned int val;
1751
1752 if (!snd_hdsp_use_is_exclusive(hdsp))
1753 return -EBUSY;
1754 val = ucontrol->value.integer.value[0] & 1;
1755 spin_lock_irq(&hdsp->lock);
1756 change = (int)val != hdsp_spdif_out(hdsp);
1757 hdsp_set_spdif_output(hdsp, val);
1758 spin_unlock_irq(&hdsp->lock);
1759 return change;
1760 }
1761
1762 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1763 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1764 .info = snd_hdsp_info_spdif_bits, \
1765 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1766
1767 static int hdsp_spdif_professional(struct hdsp *hdsp)
1768 {
1769 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1770 }
1771
1772 static int hdsp_set_spdif_professional(struct hdsp *hdsp, int val)
1773 {
1774 if (val)
1775 hdsp->control_register |= HDSP_SPDIFProfessional;
1776 else
1777 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1778 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1779 return 0;
1780 }
1781
1782 static int snd_hdsp_get_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1783 {
1784 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1785
1786 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1787 return 0;
1788 }
1789
1790 static int snd_hdsp_put_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1791 {
1792 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1793 int change;
1794 unsigned int val;
1795
1796 if (!snd_hdsp_use_is_exclusive(hdsp))
1797 return -EBUSY;
1798 val = ucontrol->value.integer.value[0] & 1;
1799 spin_lock_irq(&hdsp->lock);
1800 change = (int)val != hdsp_spdif_professional(hdsp);
1801 hdsp_set_spdif_professional(hdsp, val);
1802 spin_unlock_irq(&hdsp->lock);
1803 return change;
1804 }
1805
1806 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1807 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1808 .info = snd_hdsp_info_spdif_bits, \
1809 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1810
1811 static int hdsp_spdif_emphasis(struct hdsp *hdsp)
1812 {
1813 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1814 }
1815
1816 static int hdsp_set_spdif_emphasis(struct hdsp *hdsp, int val)
1817 {
1818 if (val)
1819 hdsp->control_register |= HDSP_SPDIFEmphasis;
1820 else
1821 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1822 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1823 return 0;
1824 }
1825
1826 static int snd_hdsp_get_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1827 {
1828 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1829
1830 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1831 return 0;
1832 }
1833
1834 static int snd_hdsp_put_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1835 {
1836 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1837 int change;
1838 unsigned int val;
1839
1840 if (!snd_hdsp_use_is_exclusive(hdsp))
1841 return -EBUSY;
1842 val = ucontrol->value.integer.value[0] & 1;
1843 spin_lock_irq(&hdsp->lock);
1844 change = (int)val != hdsp_spdif_emphasis(hdsp);
1845 hdsp_set_spdif_emphasis(hdsp, val);
1846 spin_unlock_irq(&hdsp->lock);
1847 return change;
1848 }
1849
1850 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1851 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1852 .info = snd_hdsp_info_spdif_bits, \
1853 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1854
1855 static int hdsp_spdif_nonaudio(struct hdsp *hdsp)
1856 {
1857 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1858 }
1859
1860 static int hdsp_set_spdif_nonaudio(struct hdsp *hdsp, int val)
1861 {
1862 if (val)
1863 hdsp->control_register |= HDSP_SPDIFNonAudio;
1864 else
1865 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1866 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1867 return 0;
1868 }
1869
1870 static int snd_hdsp_get_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1871 {
1872 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1873
1874 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1875 return 0;
1876 }
1877
1878 static int snd_hdsp_put_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1879 {
1880 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1881 int change;
1882 unsigned int val;
1883
1884 if (!snd_hdsp_use_is_exclusive(hdsp))
1885 return -EBUSY;
1886 val = ucontrol->value.integer.value[0] & 1;
1887 spin_lock_irq(&hdsp->lock);
1888 change = (int)val != hdsp_spdif_nonaudio(hdsp);
1889 hdsp_set_spdif_nonaudio(hdsp, val);
1890 spin_unlock_irq(&hdsp->lock);
1891 return change;
1892 }
1893
1894 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1895 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1896 .name = xname, \
1897 .index = xindex, \
1898 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1899 .info = snd_hdsp_info_spdif_sample_rate, \
1900 .get = snd_hdsp_get_spdif_sample_rate \
1901 }
1902
1903 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1904 {
1905 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1906 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1907
1908 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1909 uinfo->count = 1;
1910 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1911 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1912 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1913 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1914 return 0;
1915 }
1916
1917 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1918 {
1919 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1920
1921 switch (hdsp_spdif_sample_rate(hdsp)) {
1922 case 32000:
1923 ucontrol->value.enumerated.item[0] = 0;
1924 break;
1925 case 44100:
1926 ucontrol->value.enumerated.item[0] = 1;
1927 break;
1928 case 48000:
1929 ucontrol->value.enumerated.item[0] = 2;
1930 break;
1931 case 64000:
1932 ucontrol->value.enumerated.item[0] = 3;
1933 break;
1934 case 88200:
1935 ucontrol->value.enumerated.item[0] = 4;
1936 break;
1937 case 96000:
1938 ucontrol->value.enumerated.item[0] = 5;
1939 break;
1940 case 128000:
1941 ucontrol->value.enumerated.item[0] = 7;
1942 break;
1943 case 176400:
1944 ucontrol->value.enumerated.item[0] = 8;
1945 break;
1946 case 192000:
1947 ucontrol->value.enumerated.item[0] = 9;
1948 break;
1949 default:
1950 ucontrol->value.enumerated.item[0] = 6;
1951 }
1952 return 0;
1953 }
1954
1955 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1956 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1957 .name = xname, \
1958 .index = xindex, \
1959 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1960 .info = snd_hdsp_info_system_sample_rate, \
1961 .get = snd_hdsp_get_system_sample_rate \
1962 }
1963
1964 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1965 {
1966 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1967 uinfo->count = 1;
1968 return 0;
1969 }
1970
1971 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1972 {
1973 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1974
1975 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1976 return 0;
1977 }
1978
1979 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1980 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1981 .name = xname, \
1982 .index = xindex, \
1983 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1984 .info = snd_hdsp_info_autosync_sample_rate, \
1985 .get = snd_hdsp_get_autosync_sample_rate \
1986 }
1987
1988 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1989 {
1990 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1991 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1992 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1993 uinfo->count = 1;
1994 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1995 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1996 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1997 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1998 return 0;
1999 }
2000
2001 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2002 {
2003 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2004
2005 switch (hdsp_external_sample_rate(hdsp)) {
2006 case 32000:
2007 ucontrol->value.enumerated.item[0] = 0;
2008 break;
2009 case 44100:
2010 ucontrol->value.enumerated.item[0] = 1;
2011 break;
2012 case 48000:
2013 ucontrol->value.enumerated.item[0] = 2;
2014 break;
2015 case 64000:
2016 ucontrol->value.enumerated.item[0] = 3;
2017 break;
2018 case 88200:
2019 ucontrol->value.enumerated.item[0] = 4;
2020 break;
2021 case 96000:
2022 ucontrol->value.enumerated.item[0] = 5;
2023 break;
2024 case 128000:
2025 ucontrol->value.enumerated.item[0] = 7;
2026 break;
2027 case 176400:
2028 ucontrol->value.enumerated.item[0] = 8;
2029 break;
2030 case 192000:
2031 ucontrol->value.enumerated.item[0] = 9;
2032 break;
2033 default:
2034 ucontrol->value.enumerated.item[0] = 6;
2035 }
2036 return 0;
2037 }
2038
2039 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
2040 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2041 .name = xname, \
2042 .index = xindex, \
2043 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2044 .info = snd_hdsp_info_system_clock_mode, \
2045 .get = snd_hdsp_get_system_clock_mode \
2046 }
2047
2048 static int hdsp_system_clock_mode(struct hdsp *hdsp)
2049 {
2050 if (hdsp->control_register & HDSP_ClockModeMaster)
2051 return 0;
2052 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
2053 return 0;
2054 return 1;
2055 }
2056
2057 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2058 {
2059 static char *texts[] = {"Master", "Slave" };
2060
2061 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2062 uinfo->count = 1;
2063 uinfo->value.enumerated.items = 2;
2064 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2065 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2066 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2067 return 0;
2068 }
2069
2070 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2071 {
2072 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2073
2074 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
2075 return 0;
2076 }
2077
2078 #define HDSP_CLOCK_SOURCE(xname, xindex) \
2079 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2080 .name = xname, \
2081 .index = xindex, \
2082 .info = snd_hdsp_info_clock_source, \
2083 .get = snd_hdsp_get_clock_source, \
2084 .put = snd_hdsp_put_clock_source \
2085 }
2086
2087 static int hdsp_clock_source(struct hdsp *hdsp)
2088 {
2089 if (hdsp->control_register & HDSP_ClockModeMaster) {
2090 switch (hdsp->system_sample_rate) {
2091 case 32000:
2092 return 1;
2093 case 44100:
2094 return 2;
2095 case 48000:
2096 return 3;
2097 case 64000:
2098 return 4;
2099 case 88200:
2100 return 5;
2101 case 96000:
2102 return 6;
2103 case 128000:
2104 return 7;
2105 case 176400:
2106 return 8;
2107 case 192000:
2108 return 9;
2109 default:
2110 return 3;
2111 }
2112 } else {
2113 return 0;
2114 }
2115 }
2116
2117 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
2118 {
2119 int rate;
2120 switch (mode) {
2121 case HDSP_CLOCK_SOURCE_AUTOSYNC:
2122 if (hdsp_external_sample_rate(hdsp) != 0) {
2123 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2124 hdsp->control_register &= ~HDSP_ClockModeMaster;
2125 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2126 return 0;
2127 }
2128 }
2129 return -1;
2130 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2131 rate = 32000;
2132 break;
2133 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2134 rate = 44100;
2135 break;
2136 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2137 rate = 48000;
2138 break;
2139 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2140 rate = 64000;
2141 break;
2142 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2143 rate = 88200;
2144 break;
2145 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2146 rate = 96000;
2147 break;
2148 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2149 rate = 128000;
2150 break;
2151 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2152 rate = 176400;
2153 break;
2154 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2155 rate = 192000;
2156 break;
2157 default:
2158 rate = 48000;
2159 }
2160 hdsp->control_register |= HDSP_ClockModeMaster;
2161 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2162 hdsp_set_rate(hdsp, rate, 1);
2163 return 0;
2164 }
2165
2166 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2167 {
2168 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2169 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2170
2171 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2172 uinfo->count = 1;
2173 if (hdsp->io_type == H9632)
2174 uinfo->value.enumerated.items = 10;
2175 else
2176 uinfo->value.enumerated.items = 7;
2177 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2178 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2179 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2180 return 0;
2181 }
2182
2183 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2184 {
2185 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2186
2187 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2188 return 0;
2189 }
2190
2191 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2192 {
2193 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2194 int change;
2195 int val;
2196
2197 if (!snd_hdsp_use_is_exclusive(hdsp))
2198 return -EBUSY;
2199 val = ucontrol->value.enumerated.item[0];
2200 if (val < 0) val = 0;
2201 if (hdsp->io_type == H9632) {
2202 if (val > 9)
2203 val = 9;
2204 } else {
2205 if (val > 6)
2206 val = 6;
2207 }
2208 spin_lock_irq(&hdsp->lock);
2209 if (val != hdsp_clock_source(hdsp))
2210 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2211 else
2212 change = 0;
2213 spin_unlock_irq(&hdsp->lock);
2214 return change;
2215 }
2216
2217 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2218
2219 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2220 {
2221 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2222
2223 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2224 return 0;
2225 }
2226
2227 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2228 {
2229 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2230 int change;
2231
2232 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2233 if (change)
2234 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2235 return change;
2236 }
2237
2238 #define HDSP_DA_GAIN(xname, xindex) \
2239 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2240 .name = xname, \
2241 .index = xindex, \
2242 .info = snd_hdsp_info_da_gain, \
2243 .get = snd_hdsp_get_da_gain, \
2244 .put = snd_hdsp_put_da_gain \
2245 }
2246
2247 static int hdsp_da_gain(struct hdsp *hdsp)
2248 {
2249 switch (hdsp->control_register & HDSP_DAGainMask) {
2250 case HDSP_DAGainHighGain:
2251 return 0;
2252 case HDSP_DAGainPlus4dBu:
2253 return 1;
2254 case HDSP_DAGainMinus10dBV:
2255 return 2;
2256 default:
2257 return 1;
2258 }
2259 }
2260
2261 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2262 {
2263 hdsp->control_register &= ~HDSP_DAGainMask;
2264 switch (mode) {
2265 case 0:
2266 hdsp->control_register |= HDSP_DAGainHighGain;
2267 break;
2268 case 1:
2269 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2270 break;
2271 case 2:
2272 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2273 break;
2274 default:
2275 return -1;
2276
2277 }
2278 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2279 return 0;
2280 }
2281
2282 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2283 {
2284 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2285
2286 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2287 uinfo->count = 1;
2288 uinfo->value.enumerated.items = 3;
2289 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2290 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2291 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2292 return 0;
2293 }
2294
2295 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2296 {
2297 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2298
2299 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2300 return 0;
2301 }
2302
2303 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2304 {
2305 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2306 int change;
2307 int val;
2308
2309 if (!snd_hdsp_use_is_exclusive(hdsp))
2310 return -EBUSY;
2311 val = ucontrol->value.enumerated.item[0];
2312 if (val < 0) val = 0;
2313 if (val > 2) val = 2;
2314 spin_lock_irq(&hdsp->lock);
2315 if (val != hdsp_da_gain(hdsp))
2316 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2317 else
2318 change = 0;
2319 spin_unlock_irq(&hdsp->lock);
2320 return change;
2321 }
2322
2323 #define HDSP_AD_GAIN(xname, xindex) \
2324 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2325 .name = xname, \
2326 .index = xindex, \
2327 .info = snd_hdsp_info_ad_gain, \
2328 .get = snd_hdsp_get_ad_gain, \
2329 .put = snd_hdsp_put_ad_gain \
2330 }
2331
2332 static int hdsp_ad_gain(struct hdsp *hdsp)
2333 {
2334 switch (hdsp->control_register & HDSP_ADGainMask) {
2335 case HDSP_ADGainMinus10dBV:
2336 return 0;
2337 case HDSP_ADGainPlus4dBu:
2338 return 1;
2339 case HDSP_ADGainLowGain:
2340 return 2;
2341 default:
2342 return 1;
2343 }
2344 }
2345
2346 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2347 {
2348 hdsp->control_register &= ~HDSP_ADGainMask;
2349 switch (mode) {
2350 case 0:
2351 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2352 break;
2353 case 1:
2354 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2355 break;
2356 case 2:
2357 hdsp->control_register |= HDSP_ADGainLowGain;
2358 break;
2359 default:
2360 return -1;
2361
2362 }
2363 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2364 return 0;
2365 }
2366
2367 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2368 {
2369 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2370
2371 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2372 uinfo->count = 1;
2373 uinfo->value.enumerated.items = 3;
2374 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2375 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2376 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2377 return 0;
2378 }
2379
2380 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2381 {
2382 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2383
2384 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2385 return 0;
2386 }
2387
2388 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2389 {
2390 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2391 int change;
2392 int val;
2393
2394 if (!snd_hdsp_use_is_exclusive(hdsp))
2395 return -EBUSY;
2396 val = ucontrol->value.enumerated.item[0];
2397 if (val < 0) val = 0;
2398 if (val > 2) val = 2;
2399 spin_lock_irq(&hdsp->lock);
2400 if (val != hdsp_ad_gain(hdsp))
2401 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2402 else
2403 change = 0;
2404 spin_unlock_irq(&hdsp->lock);
2405 return change;
2406 }
2407
2408 #define HDSP_PHONE_GAIN(xname, xindex) \
2409 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2410 .name = xname, \
2411 .index = xindex, \
2412 .info = snd_hdsp_info_phone_gain, \
2413 .get = snd_hdsp_get_phone_gain, \
2414 .put = snd_hdsp_put_phone_gain \
2415 }
2416
2417 static int hdsp_phone_gain(struct hdsp *hdsp)
2418 {
2419 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2420 case HDSP_PhoneGain0dB:
2421 return 0;
2422 case HDSP_PhoneGainMinus6dB:
2423 return 1;
2424 case HDSP_PhoneGainMinus12dB:
2425 return 2;
2426 default:
2427 return 0;
2428 }
2429 }
2430
2431 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2432 {
2433 hdsp->control_register &= ~HDSP_PhoneGainMask;
2434 switch (mode) {
2435 case 0:
2436 hdsp->control_register |= HDSP_PhoneGain0dB;
2437 break;
2438 case 1:
2439 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2440 break;
2441 case 2:
2442 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2443 break;
2444 default:
2445 return -1;
2446
2447 }
2448 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2449 return 0;
2450 }
2451
2452 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2453 {
2454 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2455
2456 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2457 uinfo->count = 1;
2458 uinfo->value.enumerated.items = 3;
2459 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2460 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2461 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2462 return 0;
2463 }
2464
2465 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2466 {
2467 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2468
2469 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2470 return 0;
2471 }
2472
2473 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2474 {
2475 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2476 int change;
2477 int val;
2478
2479 if (!snd_hdsp_use_is_exclusive(hdsp))
2480 return -EBUSY;
2481 val = ucontrol->value.enumerated.item[0];
2482 if (val < 0) val = 0;
2483 if (val > 2) val = 2;
2484 spin_lock_irq(&hdsp->lock);
2485 if (val != hdsp_phone_gain(hdsp))
2486 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2487 else
2488 change = 0;
2489 spin_unlock_irq(&hdsp->lock);
2490 return change;
2491 }
2492
2493 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2494 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2495 .name = xname, \
2496 .index = xindex, \
2497 .info = snd_hdsp_info_xlr_breakout_cable, \
2498 .get = snd_hdsp_get_xlr_breakout_cable, \
2499 .put = snd_hdsp_put_xlr_breakout_cable \
2500 }
2501
2502 static int hdsp_xlr_breakout_cable(struct hdsp *hdsp)
2503 {
2504 if (hdsp->control_register & HDSP_XLRBreakoutCable)
2505 return 1;
2506 return 0;
2507 }
2508
2509 static int hdsp_set_xlr_breakout_cable(struct hdsp *hdsp, int mode)
2510 {
2511 if (mode)
2512 hdsp->control_register |= HDSP_XLRBreakoutCable;
2513 else
2514 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2515 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2516 return 0;
2517 }
2518
2519 #define snd_hdsp_info_xlr_breakout_cable snd_ctl_boolean_mono_info
2520
2521 static int snd_hdsp_get_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2522 {
2523 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2524
2525 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2526 return 0;
2527 }
2528
2529 static int snd_hdsp_put_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2530 {
2531 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2532 int change;
2533 int val;
2534
2535 if (!snd_hdsp_use_is_exclusive(hdsp))
2536 return -EBUSY;
2537 val = ucontrol->value.integer.value[0] & 1;
2538 spin_lock_irq(&hdsp->lock);
2539 change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2540 hdsp_set_xlr_breakout_cable(hdsp, val);
2541 spin_unlock_irq(&hdsp->lock);
2542 return change;
2543 }
2544
2545 /* (De)activates old RME Analog Extension Board
2546 These are connected to the internal ADAT connector
2547 Switching this on desactivates external ADAT
2548 */
2549 #define HDSP_AEB(xname, xindex) \
2550 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2551 .name = xname, \
2552 .index = xindex, \
2553 .info = snd_hdsp_info_aeb, \
2554 .get = snd_hdsp_get_aeb, \
2555 .put = snd_hdsp_put_aeb \
2556 }
2557
2558 static int hdsp_aeb(struct hdsp *hdsp)
2559 {
2560 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
2561 return 1;
2562 return 0;
2563 }
2564
2565 static int hdsp_set_aeb(struct hdsp *hdsp, int mode)
2566 {
2567 if (mode)
2568 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2569 else
2570 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2571 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2572 return 0;
2573 }
2574
2575 #define snd_hdsp_info_aeb snd_ctl_boolean_mono_info
2576
2577 static int snd_hdsp_get_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2578 {
2579 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2580
2581 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2582 return 0;
2583 }
2584
2585 static int snd_hdsp_put_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2586 {
2587 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2588 int change;
2589 int val;
2590
2591 if (!snd_hdsp_use_is_exclusive(hdsp))
2592 return -EBUSY;
2593 val = ucontrol->value.integer.value[0] & 1;
2594 spin_lock_irq(&hdsp->lock);
2595 change = (int)val != hdsp_aeb(hdsp);
2596 hdsp_set_aeb(hdsp, val);
2597 spin_unlock_irq(&hdsp->lock);
2598 return change;
2599 }
2600
2601 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2602 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2603 .name = xname, \
2604 .index = xindex, \
2605 .info = snd_hdsp_info_pref_sync_ref, \
2606 .get = snd_hdsp_get_pref_sync_ref, \
2607 .put = snd_hdsp_put_pref_sync_ref \
2608 }
2609
2610 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2611 {
2612 /* Notice that this looks at the requested sync source,
2613 not the one actually in use.
2614 */
2615
2616 switch (hdsp->control_register & HDSP_SyncRefMask) {
2617 case HDSP_SyncRef_ADAT1:
2618 return HDSP_SYNC_FROM_ADAT1;
2619 case HDSP_SyncRef_ADAT2:
2620 return HDSP_SYNC_FROM_ADAT2;
2621 case HDSP_SyncRef_ADAT3:
2622 return HDSP_SYNC_FROM_ADAT3;
2623 case HDSP_SyncRef_SPDIF:
2624 return HDSP_SYNC_FROM_SPDIF;
2625 case HDSP_SyncRef_WORD:
2626 return HDSP_SYNC_FROM_WORD;
2627 case HDSP_SyncRef_ADAT_SYNC:
2628 return HDSP_SYNC_FROM_ADAT_SYNC;
2629 default:
2630 return HDSP_SYNC_FROM_WORD;
2631 }
2632 return 0;
2633 }
2634
2635 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2636 {
2637 hdsp->control_register &= ~HDSP_SyncRefMask;
2638 switch (pref) {
2639 case HDSP_SYNC_FROM_ADAT1:
2640 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2641 break;
2642 case HDSP_SYNC_FROM_ADAT2:
2643 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2644 break;
2645 case HDSP_SYNC_FROM_ADAT3:
2646 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2647 break;
2648 case HDSP_SYNC_FROM_SPDIF:
2649 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2650 break;
2651 case HDSP_SYNC_FROM_WORD:
2652 hdsp->control_register |= HDSP_SyncRef_WORD;
2653 break;
2654 case HDSP_SYNC_FROM_ADAT_SYNC:
2655 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2656 break;
2657 default:
2658 return -1;
2659 }
2660 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2661 return 0;
2662 }
2663
2664 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2665 {
2666 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2667 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2668
2669 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2670 uinfo->count = 1;
2671
2672 switch (hdsp->io_type) {
2673 case Digiface:
2674 case H9652:
2675 uinfo->value.enumerated.items = 6;
2676 break;
2677 case Multiface:
2678 uinfo->value.enumerated.items = 4;
2679 break;
2680 case H9632:
2681 uinfo->value.enumerated.items = 3;
2682 break;
2683 default:
2684 return -EINVAL;
2685 }
2686
2687 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2688 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2689 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2690 return 0;
2691 }
2692
2693 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2694 {
2695 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2696
2697 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2698 return 0;
2699 }
2700
2701 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2702 {
2703 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2704 int change, max;
2705 unsigned int val;
2706
2707 if (!snd_hdsp_use_is_exclusive(hdsp))
2708 return -EBUSY;
2709
2710 switch (hdsp->io_type) {
2711 case Digiface:
2712 case H9652:
2713 max = 6;
2714 break;
2715 case Multiface:
2716 max = 4;
2717 break;
2718 case H9632:
2719 max = 3;
2720 break;
2721 default:
2722 return -EIO;
2723 }
2724
2725 val = ucontrol->value.enumerated.item[0] % max;
2726 spin_lock_irq(&hdsp->lock);
2727 change = (int)val != hdsp_pref_sync_ref(hdsp);
2728 hdsp_set_pref_sync_ref(hdsp, val);
2729 spin_unlock_irq(&hdsp->lock);
2730 return change;
2731 }
2732
2733 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2734 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2735 .name = xname, \
2736 .index = xindex, \
2737 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2738 .info = snd_hdsp_info_autosync_ref, \
2739 .get = snd_hdsp_get_autosync_ref, \
2740 }
2741
2742 static int hdsp_autosync_ref(struct hdsp *hdsp)
2743 {
2744 /* This looks at the autosync selected sync reference */
2745 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2746
2747 switch (status2 & HDSP_SelSyncRefMask) {
2748 case HDSP_SelSyncRef_WORD:
2749 return HDSP_AUTOSYNC_FROM_WORD;
2750 case HDSP_SelSyncRef_ADAT_SYNC:
2751 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2752 case HDSP_SelSyncRef_SPDIF:
2753 return HDSP_AUTOSYNC_FROM_SPDIF;
2754 case HDSP_SelSyncRefMask:
2755 return HDSP_AUTOSYNC_FROM_NONE;
2756 case HDSP_SelSyncRef_ADAT1:
2757 return HDSP_AUTOSYNC_FROM_ADAT1;
2758 case HDSP_SelSyncRef_ADAT2:
2759 return HDSP_AUTOSYNC_FROM_ADAT2;
2760 case HDSP_SelSyncRef_ADAT3:
2761 return HDSP_AUTOSYNC_FROM_ADAT3;
2762 default:
2763 return HDSP_AUTOSYNC_FROM_WORD;
2764 }
2765 return 0;
2766 }
2767
2768 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2769 {
2770 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2771
2772 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2773 uinfo->count = 1;
2774 uinfo->value.enumerated.items = 7;
2775 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2776 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2777 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2778 return 0;
2779 }
2780
2781 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2782 {
2783 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2784
2785 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2786 return 0;
2787 }
2788
2789 #define HDSP_LINE_OUT(xname, xindex) \
2790 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2791 .name = xname, \
2792 .index = xindex, \
2793 .info = snd_hdsp_info_line_out, \
2794 .get = snd_hdsp_get_line_out, \
2795 .put = snd_hdsp_put_line_out \
2796 }
2797
2798 static int hdsp_line_out(struct hdsp *hdsp)
2799 {
2800 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2801 }
2802
2803 static int hdsp_set_line_output(struct hdsp *hdsp, int out)
2804 {
2805 if (out)
2806 hdsp->control_register |= HDSP_LineOut;
2807 else
2808 hdsp->control_register &= ~HDSP_LineOut;
2809 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2810 return 0;
2811 }
2812
2813 #define snd_hdsp_info_line_out snd_ctl_boolean_mono_info
2814
2815 static int snd_hdsp_get_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2816 {
2817 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2818
2819 spin_lock_irq(&hdsp->lock);
2820 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2821 spin_unlock_irq(&hdsp->lock);
2822 return 0;
2823 }
2824
2825 static int snd_hdsp_put_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2826 {
2827 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2828 int change;
2829 unsigned int val;
2830
2831 if (!snd_hdsp_use_is_exclusive(hdsp))
2832 return -EBUSY;
2833 val = ucontrol->value.integer.value[0] & 1;
2834 spin_lock_irq(&hdsp->lock);
2835 change = (int)val != hdsp_line_out(hdsp);
2836 hdsp_set_line_output(hdsp, val);
2837 spin_unlock_irq(&hdsp->lock);
2838 return change;
2839 }
2840
2841 #define HDSP_PRECISE_POINTER(xname, xindex) \
2842 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2843 .name = xname, \
2844 .index = xindex, \
2845 .info = snd_hdsp_info_precise_pointer, \
2846 .get = snd_hdsp_get_precise_pointer, \
2847 .put = snd_hdsp_put_precise_pointer \
2848 }
2849
2850 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2851 {
2852 if (precise)
2853 hdsp->precise_ptr = 1;
2854 else
2855 hdsp->precise_ptr = 0;
2856 return 0;
2857 }
2858
2859 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2860
2861 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2862 {
2863 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2864
2865 spin_lock_irq(&hdsp->lock);
2866 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2867 spin_unlock_irq(&hdsp->lock);
2868 return 0;
2869 }
2870
2871 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2872 {
2873 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2874 int change;
2875 unsigned int val;
2876
2877 if (!snd_hdsp_use_is_exclusive(hdsp))
2878 return -EBUSY;
2879 val = ucontrol->value.integer.value[0] & 1;
2880 spin_lock_irq(&hdsp->lock);
2881 change = (int)val != hdsp->precise_ptr;
2882 hdsp_set_precise_pointer(hdsp, val);
2883 spin_unlock_irq(&hdsp->lock);
2884 return change;
2885 }
2886
2887 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2888 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2889 .name = xname, \
2890 .index = xindex, \
2891 .info = snd_hdsp_info_use_midi_tasklet, \
2892 .get = snd_hdsp_get_use_midi_tasklet, \
2893 .put = snd_hdsp_put_use_midi_tasklet \
2894 }
2895
2896 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2897 {
2898 if (use_tasklet)
2899 hdsp->use_midi_tasklet = 1;
2900 else
2901 hdsp->use_midi_tasklet = 0;
2902 return 0;
2903 }
2904
2905 #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
2906
2907 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2908 {
2909 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2910
2911 spin_lock_irq(&hdsp->lock);
2912 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2913 spin_unlock_irq(&hdsp->lock);
2914 return 0;
2915 }
2916
2917 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2918 {
2919 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2920 int change;
2921 unsigned int val;
2922
2923 if (!snd_hdsp_use_is_exclusive(hdsp))
2924 return -EBUSY;
2925 val = ucontrol->value.integer.value[0] & 1;
2926 spin_lock_irq(&hdsp->lock);
2927 change = (int)val != hdsp->use_midi_tasklet;
2928 hdsp_set_use_midi_tasklet(hdsp, val);
2929 spin_unlock_irq(&hdsp->lock);
2930 return change;
2931 }
2932
2933 #define HDSP_MIXER(xname, xindex) \
2934 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2935 .name = xname, \
2936 .index = xindex, \
2937 .device = 0, \
2938 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2939 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2940 .info = snd_hdsp_info_mixer, \
2941 .get = snd_hdsp_get_mixer, \
2942 .put = snd_hdsp_put_mixer \
2943 }
2944
2945 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2946 {
2947 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2948 uinfo->count = 3;
2949 uinfo->value.integer.min = 0;
2950 uinfo->value.integer.max = 65536;
2951 uinfo->value.integer.step = 1;
2952 return 0;
2953 }
2954
2955 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2956 {
2957 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2958 int source;
2959 int destination;
2960 int addr;
2961
2962 source = ucontrol->value.integer.value[0];
2963 destination = ucontrol->value.integer.value[1];
2964
2965 if (source >= hdsp->max_channels)
2966 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2967 else
2968 addr = hdsp_input_to_output_key(hdsp,source, destination);
2969
2970 spin_lock_irq(&hdsp->lock);
2971 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2972 spin_unlock_irq(&hdsp->lock);
2973 return 0;
2974 }
2975
2976 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2977 {
2978 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2979 int change;
2980 int source;
2981 int destination;
2982 int gain;
2983 int addr;
2984
2985 if (!snd_hdsp_use_is_exclusive(hdsp))
2986 return -EBUSY;
2987
2988 source = ucontrol->value.integer.value[0];
2989 destination = ucontrol->value.integer.value[1];
2990
2991 if (source >= hdsp->max_channels)
2992 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2993 else
2994 addr = hdsp_input_to_output_key(hdsp,source, destination);
2995
2996 gain = ucontrol->value.integer.value[2];
2997
2998 spin_lock_irq(&hdsp->lock);
2999 change = gain != hdsp_read_gain(hdsp, addr);
3000 if (change)
3001 hdsp_write_gain(hdsp, addr, gain);
3002 spin_unlock_irq(&hdsp->lock);
3003 return change;
3004 }
3005
3006 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
3007 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3008 .name = xname, \
3009 .index = xindex, \
3010 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3011 .info = snd_hdsp_info_sync_check, \
3012 .get = snd_hdsp_get_wc_sync_check \
3013 }
3014
3015 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3016 {
3017 static char *texts[] = {"No Lock", "Lock", "Sync" };
3018 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3019 uinfo->count = 1;
3020 uinfo->value.enumerated.items = 3;
3021 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3022 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
3023 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
3024 return 0;
3025 }
3026
3027 static int hdsp_wc_sync_check(struct hdsp *hdsp)
3028 {
3029 int status2 = hdsp_read(hdsp, HDSP_status2Register);
3030 if (status2 & HDSP_wc_lock) {
3031 if (status2 & HDSP_wc_sync)
3032 return 2;
3033 else
3034 return 1;
3035 } else
3036 return 0;
3037 return 0;
3038 }
3039
3040 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3041 {
3042 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3043
3044 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
3045 return 0;
3046 }
3047
3048 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
3049 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3050 .name = xname, \
3051 .index = xindex, \
3052 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3053 .info = snd_hdsp_info_sync_check, \
3054 .get = snd_hdsp_get_spdif_sync_check \
3055 }
3056
3057 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
3058 {
3059 int status = hdsp_read(hdsp, HDSP_statusRegister);
3060 if (status & HDSP_SPDIFErrorFlag)
3061 return 0;
3062 else {
3063 if (status & HDSP_SPDIFSync)
3064 return 2;
3065 else
3066 return 1;
3067 }
3068 return 0;
3069 }
3070
3071 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3072 {
3073 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3074
3075 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
3076 return 0;
3077 }
3078
3079 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
3080 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3081 .name = xname, \
3082 .index = xindex, \
3083 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3084 .info = snd_hdsp_info_sync_check, \
3085 .get = snd_hdsp_get_adatsync_sync_check \
3086 }
3087
3088 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
3089 {
3090 int status = hdsp_read(hdsp, HDSP_statusRegister);
3091 if (status & HDSP_TimecodeLock) {
3092 if (status & HDSP_TimecodeSync)
3093 return 2;
3094 else
3095 return 1;
3096 } else
3097 return 0;
3098 }
3099
3100 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3101 {
3102 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3103
3104 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3105 return 0;
3106 }
3107
3108 #define HDSP_ADAT_SYNC_CHECK \
3109 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3110 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3111 .info = snd_hdsp_info_sync_check, \
3112 .get = snd_hdsp_get_adat_sync_check \
3113 }
3114
3115 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
3116 {
3117 int status = hdsp_read(hdsp, HDSP_statusRegister);
3118
3119 if (status & (HDSP_Lock0>>idx)) {
3120 if (status & (HDSP_Sync0>>idx))
3121 return 2;
3122 else
3123 return 1;
3124 } else
3125 return 0;
3126 }
3127
3128 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3129 {
3130 int offset;
3131 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3132
3133 offset = ucontrol->id.index - 1;
3134 snd_BUG_ON(offset < 0);
3135
3136 switch (hdsp->io_type) {
3137 case Digiface:
3138 case H9652:
3139 if (offset >= 3)
3140 return -EINVAL;
3141 break;
3142 case Multiface:
3143 case H9632:
3144 if (offset >= 1)
3145 return -EINVAL;
3146 break;
3147 default:
3148 return -EIO;
3149 }
3150
3151 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3152 return 0;
3153 }
3154
3155 #define HDSP_DDS_OFFSET(xname, xindex) \
3156 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3157 .name = xname, \
3158 .index = xindex, \
3159 .info = snd_hdsp_info_dds_offset, \
3160 .get = snd_hdsp_get_dds_offset, \
3161 .put = snd_hdsp_put_dds_offset \
3162 }
3163
3164 static int hdsp_dds_offset(struct hdsp *hdsp)
3165 {
3166 u64 n;
3167 unsigned int dds_value = hdsp->dds_value;
3168 int system_sample_rate = hdsp->system_sample_rate;
3169
3170 if (!dds_value)
3171 return 0;
3172
3173 n = DDS_NUMERATOR;
3174 /*
3175 * dds_value = n / rate
3176 * rate = n / dds_value
3177 */
3178 n = div_u64(n, dds_value);
3179 if (system_sample_rate >= 112000)
3180 n *= 4;
3181 else if (system_sample_rate >= 56000)
3182 n *= 2;
3183 return ((int)n) - system_sample_rate;
3184 }
3185
3186 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
3187 {
3188 int rate = hdsp->system_sample_rate + offset_hz;
3189 hdsp_set_dds_value(hdsp, rate);
3190 return 0;
3191 }
3192
3193 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3194 {
3195 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3196 uinfo->count = 1;
3197 uinfo->value.integer.min = -5000;
3198 uinfo->value.integer.max = 5000;
3199 return 0;
3200 }
3201
3202 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3203 {
3204 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3205
3206 ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp);
3207 return 0;
3208 }
3209
3210 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3211 {
3212 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3213 int change;
3214 int val;
3215
3216 if (!snd_hdsp_use_is_exclusive(hdsp))
3217 return -EBUSY;
3218 val = ucontrol->value.enumerated.item[0];
3219 spin_lock_irq(&hdsp->lock);
3220 if (val != hdsp_dds_offset(hdsp))
3221 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
3222 else
3223 change = 0;
3224 spin_unlock_irq(&hdsp->lock);
3225 return change;
3226 }
3227
3228 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
3229 HDSP_DA_GAIN("DA Gain", 0),
3230 HDSP_AD_GAIN("AD Gain", 0),
3231 HDSP_PHONE_GAIN("Phones Gain", 0),
3232 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0),
3233 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
3234 };
3235
3236 static struct snd_kcontrol_new snd_hdsp_controls[] = {
3237 {
3238 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3239 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3240 .info = snd_hdsp_control_spdif_info,
3241 .get = snd_hdsp_control_spdif_get,
3242 .put = snd_hdsp_control_spdif_put,
3243 },
3244 {
3245 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3246 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3247 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3248 .info = snd_hdsp_control_spdif_stream_info,
3249 .get = snd_hdsp_control_spdif_stream_get,
3250 .put = snd_hdsp_control_spdif_stream_put,
3251 },
3252 {
3253 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3254 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3255 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3256 .info = snd_hdsp_control_spdif_mask_info,
3257 .get = snd_hdsp_control_spdif_mask_get,
3258 .private_value = IEC958_AES0_NONAUDIO |
3259 IEC958_AES0_PROFESSIONAL |
3260 IEC958_AES0_CON_EMPHASIS,
3261 },
3262 {
3263 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3264 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3265 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3266 .info = snd_hdsp_control_spdif_mask_info,
3267 .get = snd_hdsp_control_spdif_mask_get,
3268 .private_value = IEC958_AES0_NONAUDIO |
3269 IEC958_AES0_PROFESSIONAL |
3270 IEC958_AES0_PRO_EMPHASIS,
3271 },
3272 HDSP_MIXER("Mixer", 0),
3273 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3274 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3275 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3276 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3277 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3278 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3279 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3280 {
3281 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3282 .name = "Sample Clock Source Locking",
3283 .info = snd_hdsp_info_clock_source_lock,
3284 .get = snd_hdsp_get_clock_source_lock,
3285 .put = snd_hdsp_put_clock_source_lock,
3286 },
3287 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3288 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3289 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3290 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3291 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3292 /* 'External Rate' complies with the alsa control naming scheme */
3293 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3294 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3295 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3296 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3297 HDSP_LINE_OUT("Line Out", 0),
3298 HDSP_PRECISE_POINTER("Precise Pointer", 0),
3299 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
3300 };
3301
3302
3303 static int hdsp_rpm_input12(struct hdsp *hdsp)
3304 {
3305 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3306 case HDSP_RPM_Inp12_Phon_6dB:
3307 return 0;
3308 case HDSP_RPM_Inp12_Phon_n6dB:
3309 return 2;
3310 case HDSP_RPM_Inp12_Line_0dB:
3311 return 3;
3312 case HDSP_RPM_Inp12_Line_n6dB:
3313 return 4;
3314 }
3315 return 1;
3316 }
3317
3318
3319 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3320 {
3321 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3322
3323 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
3324 return 0;
3325 }
3326
3327
3328 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
3329 {
3330 hdsp->control_register &= ~HDSP_RPM_Inp12;
3331 switch (mode) {
3332 case 0:
3333 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
3334 break;
3335 case 1:
3336 break;
3337 case 2:
3338 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
3339 break;
3340 case 3:
3341 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
3342 break;
3343 case 4:
3344 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3345 break;
3346 default:
3347 return -1;
3348 }
3349
3350 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3351 return 0;
3352 }
3353
3354
3355 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3356 {
3357 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3358 int change;
3359 int val;
3360
3361 if (!snd_hdsp_use_is_exclusive(hdsp))
3362 return -EBUSY;
3363 val = ucontrol->value.enumerated.item[0];
3364 if (val < 0)
3365 val = 0;
3366 if (val > 4)
3367 val = 4;
3368 spin_lock_irq(&hdsp->lock);
3369 if (val != hdsp_rpm_input12(hdsp))
3370 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3371 else
3372 change = 0;
3373 spin_unlock_irq(&hdsp->lock);
3374 return change;
3375 }
3376
3377
3378 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3379 {
3380 static char *texts[] = {"Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"};
3381
3382 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3383 uinfo->count = 1;
3384 uinfo->value.enumerated.items = 5;
3385 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3386 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
3387 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
3388 return 0;
3389 }
3390
3391
3392 static int hdsp_rpm_input34(struct hdsp *hdsp)
3393 {
3394 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3395 case HDSP_RPM_Inp34_Phon_6dB:
3396 return 0;
3397 case HDSP_RPM_Inp34_Phon_n6dB:
3398 return 2;
3399 case HDSP_RPM_Inp34_Line_0dB:
3400 return 3;
3401 case HDSP_RPM_Inp34_Line_n6dB:
3402 return 4;
3403 }
3404 return 1;
3405 }
3406
3407
3408 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3409 {
3410 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3411
3412 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3413 return 0;
3414 }
3415
3416
3417 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3418 {
3419 hdsp->control_register &= ~HDSP_RPM_Inp34;
3420 switch (mode) {
3421 case 0:
3422 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3423 break;
3424 case 1:
3425 break;
3426 case 2:
3427 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3428 break;
3429 case 3:
3430 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3431 break;
3432 case 4:
3433 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3434 break;
3435 default:
3436 return -1;
3437 }
3438
3439 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3440 return 0;
3441 }
3442
3443
3444 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3445 {
3446 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3447 int change;
3448 int val;
3449
3450 if (!snd_hdsp_use_is_exclusive(hdsp))
3451 return -EBUSY;
3452 val = ucontrol->value.enumerated.item[0];
3453 if (val < 0)
3454 val = 0;
3455 if (val > 4)
3456 val = 4;
3457 spin_lock_irq(&hdsp->lock);
3458 if (val != hdsp_rpm_input34(hdsp))
3459 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3460 else
3461 change = 0;
3462 spin_unlock_irq(&hdsp->lock);
3463 return change;
3464 }
3465
3466
3467 /* RPM Bypass switch */
3468 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3469 {
3470 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3471 }
3472
3473
3474 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3475 {
3476 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3477
3478 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3479 return 0;
3480 }
3481
3482
3483 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3484 {
3485 if (on)
3486 hdsp->control_register |= HDSP_RPM_Bypass;
3487 else
3488 hdsp->control_register &= ~HDSP_RPM_Bypass;
3489 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3490 return 0;
3491 }
3492
3493
3494 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3495 {
3496 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3497 int change;
3498 unsigned int val;
3499
3500 if (!snd_hdsp_use_is_exclusive(hdsp))
3501 return -EBUSY;
3502 val = ucontrol->value.integer.value[0] & 1;
3503 spin_lock_irq(&hdsp->lock);
3504 change = (int)val != hdsp_rpm_bypass(hdsp);
3505 hdsp_set_rpm_bypass(hdsp, val);
3506 spin_unlock_irq(&hdsp->lock);
3507 return change;
3508 }
3509
3510
3511 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3512 {
3513 static char *texts[] = {"On", "Off"};
3514
3515 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3516 uinfo->count = 1;
3517 uinfo->value.enumerated.items = 2;
3518 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3519 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
3520 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
3521 return 0;
3522 }
3523
3524
3525 /* RPM Disconnect switch */
3526 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3527 {
3528 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3529 }
3530
3531
3532 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3533 {
3534 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3535
3536 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3537 return 0;
3538 }
3539
3540
3541 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3542 {
3543 if (on)
3544 hdsp->control_register |= HDSP_RPM_Disconnect;
3545 else
3546 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3547 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3548 return 0;
3549 }
3550
3551
3552 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3553 {
3554 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3555 int change;
3556 unsigned int val;
3557
3558 if (!snd_hdsp_use_is_exclusive(hdsp))
3559 return -EBUSY;
3560 val = ucontrol->value.integer.value[0] & 1;
3561 spin_lock_irq(&hdsp->lock);
3562 change = (int)val != hdsp_rpm_disconnect(hdsp);
3563 hdsp_set_rpm_disconnect(hdsp, val);
3564 spin_unlock_irq(&hdsp->lock);
3565 return change;
3566 }
3567
3568 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3569 {
3570 static char *texts[] = {"On", "Off"};
3571
3572 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3573 uinfo->count = 1;
3574 uinfo->value.enumerated.items = 2;
3575 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3576 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
3577 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
3578 return 0;
3579 }
3580
3581 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3582 {
3583 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3584 .name = "RPM Bypass",
3585 .get = snd_hdsp_get_rpm_bypass,
3586 .put = snd_hdsp_put_rpm_bypass,
3587 .info = snd_hdsp_info_rpm_bypass
3588 },
3589 {
3590 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3591 .name = "RPM Disconnect",
3592 .get = snd_hdsp_get_rpm_disconnect,
3593 .put = snd_hdsp_put_rpm_disconnect,
3594 .info = snd_hdsp_info_rpm_disconnect
3595 },
3596 {
3597 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3598 .name = "Input 1/2",
3599 .get = snd_hdsp_get_rpm_input12,
3600 .put = snd_hdsp_put_rpm_input12,
3601 .info = snd_hdsp_info_rpm_input
3602 },
3603 {
3604 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3605 .name = "Input 3/4",
3606 .get = snd_hdsp_get_rpm_input34,
3607 .put = snd_hdsp_put_rpm_input34,
3608 .info = snd_hdsp_info_rpm_input
3609 },
3610 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3611 HDSP_MIXER("Mixer", 0)
3612 };
3613
3614 static struct snd_kcontrol_new snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3615 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3616
3617 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3618 {
3619 unsigned int idx;
3620 int err;
3621 struct snd_kcontrol *kctl;
3622
3623 if (hdsp->io_type == RPM) {
3624 /* RPM Bypass, Disconnect and Input switches */
3625 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3626 err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3627 if (err < 0)
3628 return err;
3629 }
3630 return 0;
3631 }
3632
3633 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3634 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3635 return err;
3636 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3637 hdsp->spdif_ctl = kctl;
3638 }
3639
3640 /* ADAT SyncCheck status */
3641 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3642 snd_hdsp_adat_sync_check.index = 1;
3643 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3644 return err;
3645 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3646 for (idx = 1; idx < 3; ++idx) {
3647 snd_hdsp_adat_sync_check.index = idx+1;
3648 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3649 return err;
3650 }
3651 }
3652
3653 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3654 if (hdsp->io_type == H9632) {
3655 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3656 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3657 return err;
3658 }
3659 }
3660
3661 /* AEB control for H96xx card */
3662 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3663 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3664 return err;
3665 }
3666
3667 return 0;
3668 }
3669
3670 /*------------------------------------------------------------
3671 /proc interface
3672 ------------------------------------------------------------*/
3673
3674 static void
3675 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3676 {
3677 struct hdsp *hdsp = entry->private_data;
3678 unsigned int status;
3679 unsigned int status2;
3680 char *pref_sync_ref;
3681 char *autosync_ref;
3682 char *system_clock_mode;
3683 char *clock_source;
3684 int x;
3685
3686 status = hdsp_read(hdsp, HDSP_statusRegister);
3687 status2 = hdsp_read(hdsp, HDSP_status2Register);
3688
3689 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3690 hdsp->card->number + 1);
3691 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3692 hdsp->capture_buffer, hdsp->playback_buffer);
3693 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3694 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3695 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3696 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3697 hdsp->control2_register);
3698 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3699 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3700
3701 if (hdsp_check_for_iobox(hdsp)) {
3702 snd_iprintf(buffer, "No I/O box connected.\n"
3703 "Please connect one and upload firmware.\n");
3704 return;
3705 }
3706
3707 if (hdsp_check_for_firmware(hdsp, 0)) {
3708 if (hdsp->state & HDSP_FirmwareCached) {
3709 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3710 snd_iprintf(buffer, "Firmware loading from "
3711 "cache failed, "
3712 "please upload manually.\n");
3713 return;
3714 }
3715 } else {
3716 int err = -EINVAL;
3717 err = hdsp_request_fw_loader(hdsp);
3718 if (err < 0) {
3719 snd_iprintf(buffer,
3720 "No firmware loaded nor cached, "
3721 "please upload firmware.\n");
3722 return;
3723 }
3724 }
3725 }
3726
3727 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3728 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3729 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3730 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3731 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3732 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3733
3734 snd_iprintf(buffer, "\n");
3735
3736 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3737
3738 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3739 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3740 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3741 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3742
3743 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3744
3745 snd_iprintf(buffer, "\n");
3746
3747 switch (hdsp_clock_source(hdsp)) {
3748 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3749 clock_source = "AutoSync";
3750 break;
3751 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3752 clock_source = "Internal 32 kHz";
3753 break;
3754 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3755 clock_source = "Internal 44.1 kHz";
3756 break;
3757 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3758 clock_source = "Internal 48 kHz";
3759 break;
3760 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3761 clock_source = "Internal 64 kHz";
3762 break;
3763 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3764 clock_source = "Internal 88.2 kHz";
3765 break;
3766 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3767 clock_source = "Internal 96 kHz";
3768 break;
3769 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3770 clock_source = "Internal 128 kHz";
3771 break;
3772 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3773 clock_source = "Internal 176.4 kHz";
3774 break;
3775 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3776 clock_source = "Internal 192 kHz";
3777 break;
3778 default:
3779 clock_source = "Error";
3780 }
3781 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3782
3783 if (hdsp_system_clock_mode(hdsp))
3784 system_clock_mode = "Slave";
3785 else
3786 system_clock_mode = "Master";
3787
3788 switch (hdsp_pref_sync_ref (hdsp)) {
3789 case HDSP_SYNC_FROM_WORD:
3790 pref_sync_ref = "Word Clock";
3791 break;
3792 case HDSP_SYNC_FROM_ADAT_SYNC:
3793 pref_sync_ref = "ADAT Sync";
3794 break;
3795 case HDSP_SYNC_FROM_SPDIF:
3796 pref_sync_ref = "SPDIF";
3797 break;
3798 case HDSP_SYNC_FROM_ADAT1:
3799 pref_sync_ref = "ADAT1";
3800 break;
3801 case HDSP_SYNC_FROM_ADAT2:
3802 pref_sync_ref = "ADAT2";
3803 break;
3804 case HDSP_SYNC_FROM_ADAT3:
3805 pref_sync_ref = "ADAT3";
3806 break;
3807 default:
3808 pref_sync_ref = "Word Clock";
3809 break;
3810 }
3811 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3812
3813 switch (hdsp_autosync_ref (hdsp)) {
3814 case HDSP_AUTOSYNC_FROM_WORD:
3815 autosync_ref = "Word Clock";
3816 break;
3817 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3818 autosync_ref = "ADAT Sync";
3819 break;
3820 case HDSP_AUTOSYNC_FROM_SPDIF:
3821 autosync_ref = "SPDIF";
3822 break;
3823 case HDSP_AUTOSYNC_FROM_NONE:
3824 autosync_ref = "None";
3825 break;
3826 case HDSP_AUTOSYNC_FROM_ADAT1:
3827 autosync_ref = "ADAT1";
3828 break;
3829 case HDSP_AUTOSYNC_FROM_ADAT2:
3830 autosync_ref = "ADAT2";
3831 break;
3832 case HDSP_AUTOSYNC_FROM_ADAT3:
3833 autosync_ref = "ADAT3";
3834 break;
3835 default:
3836 autosync_ref = "---";
3837 break;
3838 }
3839 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3840
3841 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3842
3843 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3844
3845 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3846 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3847
3848 snd_iprintf(buffer, "\n");
3849
3850 if (hdsp->io_type != RPM) {
3851 switch (hdsp_spdif_in(hdsp)) {
3852 case HDSP_SPDIFIN_OPTICAL:
3853 snd_iprintf(buffer, "IEC958 input: Optical\n");
3854 break;
3855 case HDSP_SPDIFIN_COAXIAL:
3856 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3857 break;
3858 case HDSP_SPDIFIN_INTERNAL:
3859 snd_iprintf(buffer, "IEC958 input: Internal\n");
3860 break;
3861 case HDSP_SPDIFIN_AES:
3862 snd_iprintf(buffer, "IEC958 input: AES\n");
3863 break;
3864 default:
3865 snd_iprintf(buffer, "IEC958 input: ???\n");
3866 break;
3867 }
3868 }
3869
3870 if (RPM == hdsp->io_type) {
3871 if (hdsp->control_register & HDSP_RPM_Bypass)
3872 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3873 else
3874 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3875 if (hdsp->control_register & HDSP_RPM_Disconnect)
3876 snd_iprintf(buffer, "RPM disconnected\n");
3877 else
3878 snd_iprintf(buffer, "RPM connected\n");
3879
3880 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3881 case HDSP_RPM_Inp12_Phon_6dB:
3882 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3883 break;
3884 case HDSP_RPM_Inp12_Phon_0dB:
3885 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3886 break;
3887 case HDSP_RPM_Inp12_Phon_n6dB:
3888 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3889 break;
3890 case HDSP_RPM_Inp12_Line_0dB:
3891 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3892 break;
3893 case HDSP_RPM_Inp12_Line_n6dB:
3894 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3895 break;
3896 default:
3897 snd_iprintf(buffer, "Input 1/2: ???\n");
3898 }
3899
3900 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3901 case HDSP_RPM_Inp34_Phon_6dB:
3902 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3903 break;
3904 case HDSP_RPM_Inp34_Phon_0dB:
3905 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3906 break;
3907 case HDSP_RPM_Inp34_Phon_n6dB:
3908 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3909 break;
3910 case HDSP_RPM_Inp34_Line_0dB:
3911 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3912 break;
3913 case HDSP_RPM_Inp34_Line_n6dB:
3914 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3915 break;
3916 default:
3917 snd_iprintf(buffer, "Input 3/4: ???\n");
3918 }
3919
3920 } else {
3921 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3922 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3923 else
3924 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3925
3926 if (hdsp->control_register & HDSP_SPDIFProfessional)
3927 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3928 else
3929 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3930
3931 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3932 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3933 else
3934 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3935
3936 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3937 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3938 else
3939 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3940 x = hdsp_spdif_sample_rate(hdsp);
3941 if (x != 0)
3942 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3943 else
3944 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3945 }
3946 snd_iprintf(buffer, "\n");
3947
3948 /* Sync Check */
3949 x = status & HDSP_Sync0;
3950 if (status & HDSP_Lock0)
3951 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3952 else
3953 snd_iprintf(buffer, "ADAT1: No Lock\n");
3954
3955 switch (hdsp->io_type) {
3956 case Digiface:
3957 case H9652:
3958 x = status & HDSP_Sync1;
3959 if (status & HDSP_Lock1)
3960 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3961 else
3962 snd_iprintf(buffer, "ADAT2: No Lock\n");
3963 x = status & HDSP_Sync2;
3964 if (status & HDSP_Lock2)
3965 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3966 else
3967 snd_iprintf(buffer, "ADAT3: No Lock\n");
3968 break;
3969 default:
3970 /* relax */
3971 break;
3972 }
3973
3974 x = status & HDSP_SPDIFSync;
3975 if (status & HDSP_SPDIFErrorFlag)
3976 snd_iprintf (buffer, "SPDIF: No Lock\n");
3977 else
3978 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3979
3980 x = status2 & HDSP_wc_sync;
3981 if (status2 & HDSP_wc_lock)
3982 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3983 else
3984 snd_iprintf (buffer, "Word Clock: No Lock\n");
3985
3986 x = status & HDSP_TimecodeSync;
3987 if (status & HDSP_TimecodeLock)
3988 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3989 else
3990 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3991
3992 snd_iprintf(buffer, "\n");
3993
3994 /* Informations about H9632 specific controls */
3995 if (hdsp->io_type == H9632) {
3996 char *tmp;
3997
3998 switch (hdsp_ad_gain(hdsp)) {
3999 case 0:
4000 tmp = "-10 dBV";
4001 break;
4002 case 1:
4003 tmp = "+4 dBu";
4004 break;
4005 default:
4006 tmp = "Lo Gain";
4007 break;
4008 }
4009 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
4010
4011 switch (hdsp_da_gain(hdsp)) {
4012 case 0:
4013 tmp = "Hi Gain";
4014 break;
4015 case 1:
4016 tmp = "+4 dBu";
4017 break;
4018 default:
4019 tmp = "-10 dBV";
4020 break;
4021 }
4022 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
4023
4024 switch (hdsp_phone_gain(hdsp)) {
4025 case 0:
4026 tmp = "0 dB";
4027 break;
4028 case 1:
4029 tmp = "-6 dB";
4030 break;
4031 default:
4032 tmp = "-12 dB";
4033 break;
4034 }
4035 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
4036
4037 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
4038
4039 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
4040 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
4041 else
4042 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
4043 snd_iprintf(buffer, "\n");
4044 }
4045
4046 }
4047
4048 static void snd_hdsp_proc_init(struct hdsp *hdsp)
4049 {
4050 struct snd_info_entry *entry;
4051
4052 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
4053 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
4054 }
4055
4056 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
4057 {
4058 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
4059 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
4060 }
4061
4062 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
4063 {
4064 unsigned long pb_bus, cb_bus;
4065
4066 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
4067 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
4068 if (hdsp->capture_dma_buf.area)
4069 snd_dma_free_pages(&hdsp->capture_dma_buf);
4070 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
4071 return -ENOMEM;
4072 }
4073
4074 /* Align to bus-space 64K boundary */
4075
4076 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
4077 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
4078
4079 /* Tell the card where it is */
4080
4081 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
4082 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
4083
4084 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
4085 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
4086
4087 return 0;
4088 }
4089
4090 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
4091 {
4092 unsigned int i;
4093
4094 /* ASSUMPTION: hdsp->lock is either held, or
4095 there is no need to hold it (e.g. during module
4096 initialization).
4097 */
4098
4099 /* set defaults:
4100
4101 SPDIF Input via Coax
4102 Master clock mode
4103 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
4104 which implies 2 4096 sample, 32Kbyte periods).
4105 Enable line out.
4106 */
4107
4108 hdsp->control_register = HDSP_ClockModeMaster |
4109 HDSP_SPDIFInputCoaxial |
4110 hdsp_encode_latency(7) |
4111 HDSP_LineOut;
4112
4113
4114 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
4115
4116 #ifdef SNDRV_BIG_ENDIAN
4117 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
4118 #else
4119 hdsp->control2_register = 0;
4120 #endif
4121 if (hdsp->io_type == H9652)
4122 snd_hdsp_9652_enable_mixer (hdsp);
4123 else
4124 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4125
4126 hdsp_reset_hw_pointer(hdsp);
4127 hdsp_compute_period_size(hdsp);
4128
4129 /* silence everything */
4130
4131 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
4132 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
4133
4134 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
4135 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
4136 return -EIO;
4137 }
4138
4139 /* H9632 specific defaults */
4140 if (hdsp->io_type == H9632) {
4141 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
4142 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
4143 }
4144
4145 /* set a default rate so that the channel map is set up.
4146 */
4147
4148 hdsp_set_rate(hdsp, 48000, 1);
4149
4150 return 0;
4151 }
4152
4153 static void hdsp_midi_tasklet(unsigned long arg)
4154 {
4155 struct hdsp *hdsp = (struct hdsp *)arg;
4156
4157 if (hdsp->midi[0].pending)
4158 snd_hdsp_midi_input_read (&hdsp->midi[0]);
4159 if (hdsp->midi[1].pending)
4160 snd_hdsp_midi_input_read (&hdsp->midi[1]);
4161 }
4162
4163 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
4164 {
4165 struct hdsp *hdsp = (struct hdsp *) dev_id;
4166 unsigned int status;
4167 int audio;
4168 int midi0;
4169 int midi1;
4170 unsigned int midi0status;
4171 unsigned int midi1status;
4172 int schedule = 0;
4173
4174 status = hdsp_read(hdsp, HDSP_statusRegister);
4175
4176 audio = status & HDSP_audioIRQPending;
4177 midi0 = status & HDSP_midi0IRQPending;
4178 midi1 = status & HDSP_midi1IRQPending;
4179
4180 if (!audio && !midi0 && !midi1)
4181 return IRQ_NONE;
4182
4183 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
4184
4185 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
4186 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
4187
4188 if (!(hdsp->state & HDSP_InitializationComplete))
4189 return IRQ_HANDLED;
4190
4191 if (audio) {
4192 if (hdsp->capture_substream)
4193 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
4194
4195 if (hdsp->playback_substream)
4196 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
4197 }
4198
4199 if (midi0 && midi0status) {
4200 if (hdsp->use_midi_tasklet) {
4201 /* we disable interrupts for this input until processing is done */
4202 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
4203 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
4204 hdsp->midi[0].pending = 1;
4205 schedule = 1;
4206 } else {
4207 snd_hdsp_midi_input_read (&hdsp->midi[0]);
4208 }
4209 }
4210 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
4211 if (hdsp->use_midi_tasklet) {
4212 /* we disable interrupts for this input until processing is done */
4213 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
4214 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
4215 hdsp->midi[1].pending = 1;
4216 schedule = 1;
4217 } else {
4218 snd_hdsp_midi_input_read (&hdsp->midi[1]);
4219 }
4220 }
4221 if (hdsp->use_midi_tasklet && schedule)
4222 tasklet_schedule(&hdsp->midi_tasklet);
4223 return IRQ_HANDLED;
4224 }
4225
4226 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
4227 {
4228 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4229 return hdsp_hw_pointer(hdsp);
4230 }
4231
4232 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
4233 int stream,
4234 int channel)
4235
4236 {
4237 int mapped_channel;
4238
4239 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
4240 return NULL;
4241
4242 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
4243 return NULL;
4244
4245 if (stream == SNDRV_PCM_STREAM_CAPTURE)
4246 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
4247 else
4248 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
4249 }
4250
4251 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
4252 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
4253 {
4254 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4255 char *channel_buf;
4256
4257 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
4258 return -EINVAL;
4259
4260 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4261 if (snd_BUG_ON(!channel_buf))
4262 return -EIO;
4263 if (copy_from_user(channel_buf + pos * 4, src, count * 4))
4264 return -EFAULT;
4265 return count;
4266 }
4267
4268 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
4269 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
4270 {
4271 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4272 char *channel_buf;
4273
4274 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
4275 return -EINVAL;
4276
4277 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4278 if (snd_BUG_ON(!channel_buf))
4279 return -EIO;
4280 if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
4281 return -EFAULT;
4282 return count;
4283 }
4284
4285 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
4286 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
4287 {
4288 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4289 char *channel_buf;
4290
4291 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4292 if (snd_BUG_ON(!channel_buf))
4293 return -EIO;
4294 memset(channel_buf + pos * 4, 0, count * 4);
4295 return count;
4296 }
4297
4298 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
4299 {
4300 struct snd_pcm_runtime *runtime = substream->runtime;
4301 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4302 struct snd_pcm_substream *other;
4303 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4304 other = hdsp->capture_substream;
4305 else
4306 other = hdsp->playback_substream;
4307 if (hdsp->running)
4308 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
4309 else
4310 runtime->status->hw_ptr = 0;
4311 if (other) {
4312 struct snd_pcm_substream *s;
4313 struct snd_pcm_runtime *oruntime = other->runtime;
4314 snd_pcm_group_for_each_entry(s, substream) {
4315 if (s == other) {
4316 oruntime->status->hw_ptr = runtime->status->hw_ptr;
4317 break;
4318 }
4319 }
4320 }
4321 return 0;
4322 }
4323
4324 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4325 struct snd_pcm_hw_params *params)
4326 {
4327 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4328 int err;
4329 pid_t this_pid;
4330 pid_t other_pid;
4331
4332 if (hdsp_check_for_iobox (hdsp))
4333 return -EIO;
4334
4335 if (hdsp_check_for_firmware(hdsp, 1))
4336 return -EIO;
4337
4338 spin_lock_irq(&hdsp->lock);
4339
4340 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4341 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4342 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4343 this_pid = hdsp->playback_pid;
4344 other_pid = hdsp->capture_pid;
4345 } else {
4346 this_pid = hdsp->capture_pid;
4347 other_pid = hdsp->playback_pid;
4348 }
4349
4350 if ((other_pid > 0) && (this_pid != other_pid)) {
4351
4352 /* The other stream is open, and not by the same
4353 task as this one. Make sure that the parameters
4354 that matter are the same.
4355 */
4356
4357 if (params_rate(params) != hdsp->system_sample_rate) {
4358 spin_unlock_irq(&hdsp->lock);
4359 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4360 return -EBUSY;
4361 }
4362
4363 if (params_period_size(params) != hdsp->period_bytes / 4) {
4364 spin_unlock_irq(&hdsp->lock);
4365 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4366 return -EBUSY;
4367 }
4368
4369 /* We're fine. */
4370
4371 spin_unlock_irq(&hdsp->lock);
4372 return 0;
4373
4374 } else {
4375 spin_unlock_irq(&hdsp->lock);
4376 }
4377
4378 /* how to make sure that the rate matches an externally-set one ?
4379 */
4380
4381 spin_lock_irq(&hdsp->lock);
4382 if (! hdsp->clock_source_locked) {
4383 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4384 spin_unlock_irq(&hdsp->lock);
4385 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4386 return err;
4387 }
4388 }
4389 spin_unlock_irq(&hdsp->lock);
4390
4391 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4392 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4393 return err;
4394 }
4395
4396 return 0;
4397 }
4398
4399 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4400 struct snd_pcm_channel_info *info)
4401 {
4402 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4403 int mapped_channel;
4404
4405 if (snd_BUG_ON(info->channel >= hdsp->max_channels))
4406 return -EINVAL;
4407
4408 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0)
4409 return -EINVAL;
4410
4411 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
4412 info->first = 0;
4413 info->step = 32;
4414 return 0;
4415 }
4416
4417 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4418 unsigned int cmd, void *arg)
4419 {
4420 switch (cmd) {
4421 case SNDRV_PCM_IOCTL1_RESET:
4422 return snd_hdsp_reset(substream);
4423 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4424 return snd_hdsp_channel_info(substream, arg);
4425 default:
4426 break;
4427 }
4428
4429 return snd_pcm_lib_ioctl(substream, cmd, arg);
4430 }
4431
4432 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4433 {
4434 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4435 struct snd_pcm_substream *other;
4436 int running;
4437
4438 if (hdsp_check_for_iobox (hdsp))
4439 return -EIO;
4440
4441 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4442 return -EIO;
4443
4444 spin_lock(&hdsp->lock);
4445 running = hdsp->running;
4446 switch (cmd) {
4447 case SNDRV_PCM_TRIGGER_START:
4448 running |= 1 << substream->stream;
4449 break;
4450 case SNDRV_PCM_TRIGGER_STOP:
4451 running &= ~(1 << substream->stream);
4452 break;
4453 default:
4454 snd_BUG();
4455 spin_unlock(&hdsp->lock);
4456 return -EINVAL;
4457 }
4458 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4459 other = hdsp->capture_substream;
4460 else
4461 other = hdsp->playback_substream;
4462
4463 if (other) {
4464 struct snd_pcm_substream *s;
4465 snd_pcm_group_for_each_entry(s, substream) {
4466 if (s == other) {
4467 snd_pcm_trigger_done(s, substream);
4468 if (cmd == SNDRV_PCM_TRIGGER_START)
4469 running |= 1 << s->stream;
4470 else
4471 running &= ~(1 << s->stream);
4472 goto _ok;
4473 }
4474 }
4475 if (cmd == SNDRV_PCM_TRIGGER_START) {
4476 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4477 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4478 hdsp_silence_playback(hdsp);
4479 } else {
4480 if (running &&
4481 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4482 hdsp_silence_playback(hdsp);
4483 }
4484 } else {
4485 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4486 hdsp_silence_playback(hdsp);
4487 }
4488 _ok:
4489 snd_pcm_trigger_done(substream, substream);
4490 if (!hdsp->running && running)
4491 hdsp_start_audio(hdsp);
4492 else if (hdsp->running && !running)
4493 hdsp_stop_audio(hdsp);
4494 hdsp->running = running;
4495 spin_unlock(&hdsp->lock);
4496
4497 return 0;
4498 }
4499
4500 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4501 {
4502 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4503 int result = 0;
4504
4505 if (hdsp_check_for_iobox (hdsp))
4506 return -EIO;
4507
4508 if (hdsp_check_for_firmware(hdsp, 1))
4509 return -EIO;
4510
4511 spin_lock_irq(&hdsp->lock);
4512 if (!hdsp->running)
4513 hdsp_reset_hw_pointer(hdsp);
4514 spin_unlock_irq(&hdsp->lock);
4515 return result;
4516 }
4517
4518 static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4519 {
4520 .info = (SNDRV_PCM_INFO_MMAP |
4521 SNDRV_PCM_INFO_MMAP_VALID |
4522 SNDRV_PCM_INFO_NONINTERLEAVED |
4523 SNDRV_PCM_INFO_SYNC_START |
4524 SNDRV_PCM_INFO_DOUBLE),
4525 #ifdef SNDRV_BIG_ENDIAN
4526 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4527 #else
4528 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4529 #endif
4530 .rates = (SNDRV_PCM_RATE_32000 |
4531 SNDRV_PCM_RATE_44100 |
4532 SNDRV_PCM_RATE_48000 |
4533 SNDRV_PCM_RATE_64000 |
4534 SNDRV_PCM_RATE_88200 |
4535 SNDRV_PCM_RATE_96000),
4536 .rate_min = 32000,
4537 .rate_max = 96000,
4538 .channels_min = 6,
4539 .channels_max = HDSP_MAX_CHANNELS,
4540 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4541 .period_bytes_min = (64 * 4) * 10,
4542 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4543 .periods_min = 2,
4544 .periods_max = 2,
4545 .fifo_size = 0
4546 };
4547
4548 static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4549 {
4550 .info = (SNDRV_PCM_INFO_MMAP |
4551 SNDRV_PCM_INFO_MMAP_VALID |
4552 SNDRV_PCM_INFO_NONINTERLEAVED |
4553 SNDRV_PCM_INFO_SYNC_START),
4554 #ifdef SNDRV_BIG_ENDIAN
4555 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4556 #else
4557 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4558 #endif
4559 .rates = (SNDRV_PCM_RATE_32000 |
4560 SNDRV_PCM_RATE_44100 |
4561 SNDRV_PCM_RATE_48000 |
4562 SNDRV_PCM_RATE_64000 |
4563 SNDRV_PCM_RATE_88200 |
4564 SNDRV_PCM_RATE_96000),
4565 .rate_min = 32000,
4566 .rate_max = 96000,
4567 .channels_min = 5,
4568 .channels_max = HDSP_MAX_CHANNELS,
4569 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4570 .period_bytes_min = (64 * 4) * 10,
4571 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4572 .periods_min = 2,
4573 .periods_max = 2,
4574 .fifo_size = 0
4575 };
4576
4577 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4578
4579 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4580 .count = ARRAY_SIZE(hdsp_period_sizes),
4581 .list = hdsp_period_sizes,
4582 .mask = 0
4583 };
4584
4585 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4586
4587 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4588 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4589 .list = hdsp_9632_sample_rates,
4590 .mask = 0
4591 };
4592
4593 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4594 struct snd_pcm_hw_rule *rule)
4595 {
4596 struct hdsp *hdsp = rule->private;
4597 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4598 if (hdsp->io_type == H9632) {
4599 unsigned int list[3];
4600 list[0] = hdsp->qs_in_channels;
4601 list[1] = hdsp->ds_in_channels;
4602 list[2] = hdsp->ss_in_channels;
4603 return snd_interval_list(c, 3, list, 0);
4604 } else {
4605 unsigned int list[2];
4606 list[0] = hdsp->ds_in_channels;
4607 list[1] = hdsp->ss_in_channels;
4608 return snd_interval_list(c, 2, list, 0);
4609 }
4610 }
4611
4612 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4613 struct snd_pcm_hw_rule *rule)
4614 {
4615 unsigned int list[3];
4616 struct hdsp *hdsp = rule->private;
4617 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4618 if (hdsp->io_type == H9632) {
4619 list[0] = hdsp->qs_out_channels;
4620 list[1] = hdsp->ds_out_channels;
4621 list[2] = hdsp->ss_out_channels;
4622 return snd_interval_list(c, 3, list, 0);
4623 } else {
4624 list[0] = hdsp->ds_out_channels;
4625 list[1] = hdsp->ss_out_channels;
4626 }
4627 return snd_interval_list(c, 2, list, 0);
4628 }
4629
4630 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4631 struct snd_pcm_hw_rule *rule)
4632 {
4633 struct hdsp *hdsp = rule->private;
4634 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4635 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4636 if (r->min > 96000 && hdsp->io_type == H9632) {
4637 struct snd_interval t = {
4638 .min = hdsp->qs_in_channels,
4639 .max = hdsp->qs_in_channels,
4640 .integer = 1,
4641 };
4642 return snd_interval_refine(c, &t);
4643 } else if (r->min > 48000 && r->max <= 96000) {
4644 struct snd_interval t = {
4645 .min = hdsp->ds_in_channels,
4646 .max = hdsp->ds_in_channels,
4647 .integer = 1,
4648 };
4649 return snd_interval_refine(c, &t);
4650 } else if (r->max < 64000) {
4651 struct snd_interval t = {
4652 .min = hdsp->ss_in_channels,
4653 .max = hdsp->ss_in_channels,
4654 .integer = 1,
4655 };
4656 return snd_interval_refine(c, &t);
4657 }
4658 return 0;
4659 }
4660
4661 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4662 struct snd_pcm_hw_rule *rule)
4663 {
4664 struct hdsp *hdsp = rule->private;
4665 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4666 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4667 if (r->min > 96000 && hdsp->io_type == H9632) {
4668 struct snd_interval t = {
4669 .min = hdsp->qs_out_channels,
4670 .max = hdsp->qs_out_channels,
4671 .integer = 1,
4672 };
4673 return snd_interval_refine(c, &t);
4674 } else if (r->min > 48000 && r->max <= 96000) {
4675 struct snd_interval t = {
4676 .min = hdsp->ds_out_channels,
4677 .max = hdsp->ds_out_channels,
4678 .integer = 1,
4679 };
4680 return snd_interval_refine(c, &t);
4681 } else if (r->max < 64000) {
4682 struct snd_interval t = {
4683 .min = hdsp->ss_out_channels,
4684 .max = hdsp->ss_out_channels,
4685 .integer = 1,
4686 };
4687 return snd_interval_refine(c, &t);
4688 }
4689 return 0;
4690 }
4691
4692 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4693 struct snd_pcm_hw_rule *rule)
4694 {
4695 struct hdsp *hdsp = rule->private;
4696 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4697 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4698 if (c->min >= hdsp->ss_out_channels) {
4699 struct snd_interval t = {
4700 .min = 32000,
4701 .max = 48000,
4702 .integer = 1,
4703 };
4704 return snd_interval_refine(r, &t);
4705 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4706 struct snd_interval t = {
4707 .min = 128000,
4708 .max = 192000,
4709 .integer = 1,
4710 };
4711 return snd_interval_refine(r, &t);
4712 } else if (c->max <= hdsp->ds_out_channels) {
4713 struct snd_interval t = {
4714 .min = 64000,
4715 .max = 96000,
4716 .integer = 1,
4717 };
4718 return snd_interval_refine(r, &t);
4719 }
4720 return 0;
4721 }
4722
4723 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4724 struct snd_pcm_hw_rule *rule)
4725 {
4726 struct hdsp *hdsp = rule->private;
4727 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4728 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4729 if (c->min >= hdsp->ss_in_channels) {
4730 struct snd_interval t = {
4731 .min = 32000,
4732 .max = 48000,
4733 .integer = 1,
4734 };
4735 return snd_interval_refine(r, &t);
4736 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4737 struct snd_interval t = {
4738 .min = 128000,
4739 .max = 192000,
4740 .integer = 1,
4741 };
4742 return snd_interval_refine(r, &t);
4743 } else if (c->max <= hdsp->ds_in_channels) {
4744 struct snd_interval t = {
4745 .min = 64000,
4746 .max = 96000,
4747 .integer = 1,
4748 };
4749 return snd_interval_refine(r, &t);
4750 }
4751 return 0;
4752 }
4753
4754 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4755 {
4756 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4757 struct snd_pcm_runtime *runtime = substream->runtime;
4758
4759 if (hdsp_check_for_iobox (hdsp))
4760 return -EIO;
4761
4762 if (hdsp_check_for_firmware(hdsp, 1))
4763 return -EIO;
4764
4765 spin_lock_irq(&hdsp->lock);
4766
4767 snd_pcm_set_sync(substream);
4768
4769 runtime->hw = snd_hdsp_playback_subinfo;
4770 runtime->dma_area = hdsp->playback_buffer;
4771 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4772
4773 hdsp->playback_pid = current->pid;
4774 hdsp->playback_substream = substream;
4775
4776 spin_unlock_irq(&hdsp->lock);
4777
4778 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4779 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4780 if (hdsp->clock_source_locked) {
4781 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4782 } else if (hdsp->io_type == H9632) {
4783 runtime->hw.rate_max = 192000;
4784 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4785 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4786 }
4787 if (hdsp->io_type == H9632) {
4788 runtime->hw.channels_min = hdsp->qs_out_channels;
4789 runtime->hw.channels_max = hdsp->ss_out_channels;
4790 }
4791
4792 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4793 snd_hdsp_hw_rule_out_channels, hdsp,
4794 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4795 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4796 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4797 SNDRV_PCM_HW_PARAM_RATE, -1);
4798 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4799 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4800 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4801
4802 if (RPM != hdsp->io_type) {
4803 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4804 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4805 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4806 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4807 }
4808 return 0;
4809 }
4810
4811 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4812 {
4813 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4814
4815 spin_lock_irq(&hdsp->lock);
4816
4817 hdsp->playback_pid = -1;
4818 hdsp->playback_substream = NULL;
4819
4820 spin_unlock_irq(&hdsp->lock);
4821
4822 if (RPM != hdsp->io_type) {
4823 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4824 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4825 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4826 }
4827 return 0;
4828 }
4829
4830
4831 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4832 {
4833 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4834 struct snd_pcm_runtime *runtime = substream->runtime;
4835
4836 if (hdsp_check_for_iobox (hdsp))
4837 return -EIO;
4838
4839 if (hdsp_check_for_firmware(hdsp, 1))
4840 return -EIO;
4841
4842 spin_lock_irq(&hdsp->lock);
4843
4844 snd_pcm_set_sync(substream);
4845
4846 runtime->hw = snd_hdsp_capture_subinfo;
4847 runtime->dma_area = hdsp->capture_buffer;
4848 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4849
4850 hdsp->capture_pid = current->pid;
4851 hdsp->capture_substream = substream;
4852
4853 spin_unlock_irq(&hdsp->lock);
4854
4855 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4856 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4857 if (hdsp->io_type == H9632) {
4858 runtime->hw.channels_min = hdsp->qs_in_channels;
4859 runtime->hw.channels_max = hdsp->ss_in_channels;
4860 runtime->hw.rate_max = 192000;
4861 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4862 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4863 }
4864 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4865 snd_hdsp_hw_rule_in_channels, hdsp,
4866 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4867 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4868 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4869 SNDRV_PCM_HW_PARAM_RATE, -1);
4870 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4871 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4872 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4873 return 0;
4874 }
4875
4876 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4877 {
4878 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4879
4880 spin_lock_irq(&hdsp->lock);
4881
4882 hdsp->capture_pid = -1;
4883 hdsp->capture_substream = NULL;
4884
4885 spin_unlock_irq(&hdsp->lock);
4886 return 0;
4887 }
4888
4889 /* helper functions for copying meter values */
4890 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4891 {
4892 u32 val = readl(src);
4893 return copy_to_user(dest, &val, 4);
4894 }
4895
4896 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4897 {
4898 u32 rms_low, rms_high;
4899 u64 rms;
4900 rms_low = readl(src_low);
4901 rms_high = readl(src_high);
4902 rms = ((u64)rms_high << 32) | rms_low;
4903 return copy_to_user(dest, &rms, 8);
4904 }
4905
4906 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4907 {
4908 u32 rms_low, rms_high;
4909 u64 rms;
4910 rms_low = readl(src_low) & 0xffffff00;
4911 rms_high = readl(src_high) & 0xffffff00;
4912 rms = ((u64)rms_high << 32) | rms_low;
4913 return copy_to_user(dest, &rms, 8);
4914 }
4915
4916 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4917 {
4918 int doublespeed = 0;
4919 int i, j, channels, ofs;
4920
4921 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4922 doublespeed = 1;
4923 channels = doublespeed ? 14 : 26;
4924 for (i = 0, j = 0; i < 26; ++i) {
4925 if (doublespeed && (i & 4))
4926 continue;
4927 ofs = HDSP_9652_peakBase - j * 4;
4928 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4929 return -EFAULT;
4930 ofs -= channels * 4;
4931 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4932 return -EFAULT;
4933 ofs -= channels * 4;
4934 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4935 return -EFAULT;
4936 ofs = HDSP_9652_rmsBase + j * 8;
4937 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4938 hdsp->iobase + ofs + 4))
4939 return -EFAULT;
4940 ofs += channels * 8;
4941 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4942 hdsp->iobase + ofs + 4))
4943 return -EFAULT;
4944 ofs += channels * 8;
4945 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4946 hdsp->iobase + ofs + 4))
4947 return -EFAULT;
4948 j++;
4949 }
4950 return 0;
4951 }
4952
4953 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4954 {
4955 int i, j;
4956 struct hdsp_9632_meters __iomem *m;
4957 int doublespeed = 0;
4958
4959 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4960 doublespeed = 1;
4961 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4962 for (i = 0, j = 0; i < 16; ++i, ++j) {
4963 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4964 return -EFAULT;
4965 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4966 return -EFAULT;
4967 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4968 return -EFAULT;
4969 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4970 &m->input_rms_high[j]))
4971 return -EFAULT;
4972 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4973 &m->playback_rms_high[j]))
4974 return -EFAULT;
4975 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4976 &m->output_rms_high[j]))
4977 return -EFAULT;
4978 if (doublespeed && i == 3) i += 4;
4979 }
4980 return 0;
4981 }
4982
4983 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4984 {
4985 int i;
4986
4987 for (i = 0; i < 26; i++) {
4988 if (copy_u32_le(&peak_rms->playback_peaks[i],
4989 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4990 return -EFAULT;
4991 if (copy_u32_le(&peak_rms->input_peaks[i],
4992 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4993 return -EFAULT;
4994 }
4995 for (i = 0; i < 28; i++) {
4996 if (copy_u32_le(&peak_rms->output_peaks[i],
4997 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4998 return -EFAULT;
4999 }
5000 for (i = 0; i < 26; ++i) {
5001 if (copy_u64_le(&peak_rms->playback_rms[i],
5002 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
5003 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
5004 return -EFAULT;
5005 if (copy_u64_le(&peak_rms->input_rms[i],
5006 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
5007 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
5008 return -EFAULT;
5009 }
5010 return 0;
5011 }
5012
5013 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
5014 {
5015 struct hdsp *hdsp = hw->private_data;
5016 void __user *argp = (void __user *)arg;
5017 int err;
5018
5019 switch (cmd) {
5020 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
5021 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
5022
5023 err = hdsp_check_for_iobox(hdsp);
5024 if (err < 0)
5025 return err;
5026
5027 err = hdsp_check_for_firmware(hdsp, 1);
5028 if (err < 0)
5029 return err;
5030
5031 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
5032 snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n");
5033 return -EINVAL;
5034 }
5035
5036 switch (hdsp->io_type) {
5037 case H9652:
5038 return hdsp_9652_get_peak(hdsp, peak_rms);
5039 case H9632:
5040 return hdsp_9632_get_peak(hdsp, peak_rms);
5041 default:
5042 return hdsp_get_peak(hdsp, peak_rms);
5043 }
5044 }
5045 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
5046 struct hdsp_config_info info;
5047 unsigned long flags;
5048 int i;
5049
5050 err = hdsp_check_for_iobox(hdsp);
5051 if (err < 0)
5052 return err;
5053
5054 err = hdsp_check_for_firmware(hdsp, 1);
5055 if (err < 0)
5056 return err;
5057
5058 memset(&info, 0, sizeof(info));
5059 spin_lock_irqsave(&hdsp->lock, flags);
5060 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
5061 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
5062 if (hdsp->io_type != H9632)
5063 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
5064 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
5065 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
5066 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
5067 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
5068 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
5069 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
5070 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
5071 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
5072 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
5073 info.system_sample_rate = hdsp->system_sample_rate;
5074 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
5075 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
5076 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
5077 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
5078 info.line_out = (unsigned char)hdsp_line_out(hdsp);
5079 if (hdsp->io_type == H9632) {
5080 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
5081 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
5082 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
5083 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
5084
5085 } else if (hdsp->io_type == RPM) {
5086 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
5087 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
5088 }
5089 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
5090 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
5091 spin_unlock_irqrestore(&hdsp->lock, flags);
5092 if (copy_to_user(argp, &info, sizeof(info)))
5093 return -EFAULT;
5094 break;
5095 }
5096 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
5097 struct hdsp_9632_aeb h9632_aeb;
5098
5099 if (hdsp->io_type != H9632) return -EINVAL;
5100 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
5101 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
5102 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
5103 return -EFAULT;
5104 break;
5105 }
5106 case SNDRV_HDSP_IOCTL_GET_VERSION: {
5107 struct hdsp_version hdsp_version;
5108 int err;
5109
5110 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
5111 if (hdsp->io_type == Undefined) {
5112 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5113 return err;
5114 }
5115 hdsp_version.io_type = hdsp->io_type;
5116 hdsp_version.firmware_rev = hdsp->firmware_rev;
5117 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
5118 return -EFAULT;
5119 break;
5120 }
5121 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
5122 struct hdsp_firmware __user *firmware;
5123 u32 __user *firmware_data;
5124 int err;
5125
5126 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
5127 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
5128 if (hdsp->io_type == Undefined) return -EINVAL;
5129
5130 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
5131 return -EBUSY;
5132
5133 snd_printk(KERN_INFO "Hammerfall-DSP: initializing firmware upload\n");
5134 firmware = (struct hdsp_firmware __user *)argp;
5135
5136 if (get_user(firmware_data, &firmware->firmware_data))
5137 return -EFAULT;
5138
5139 if (hdsp_check_for_iobox (hdsp))
5140 return -EIO;
5141
5142 if (!hdsp->fw_uploaded) {
5143 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
5144 if (!hdsp->fw_uploaded)
5145 return -ENOMEM;
5146 }
5147
5148 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
5149 HDSP_FIRMWARE_SIZE)) {
5150 vfree(hdsp->fw_uploaded);
5151 hdsp->fw_uploaded = NULL;
5152 return -EFAULT;
5153 }
5154
5155 hdsp->state |= HDSP_FirmwareCached;
5156
5157 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5158 return err;
5159
5160 if (!(hdsp->state & HDSP_InitializationComplete)) {
5161 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5162 return err;
5163
5164 snd_hdsp_initialize_channels(hdsp);
5165 snd_hdsp_initialize_midi_flush(hdsp);
5166
5167 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5168 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
5169 return err;
5170 }
5171 }
5172 break;
5173 }
5174 case SNDRV_HDSP_IOCTL_GET_MIXER: {
5175 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
5176 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
5177 return -EFAULT;
5178 break;
5179 }
5180 default:
5181 return -EINVAL;
5182 }
5183 return 0;
5184 }
5185
5186 static struct snd_pcm_ops snd_hdsp_playback_ops = {
5187 .open = snd_hdsp_playback_open,
5188 .close = snd_hdsp_playback_release,
5189 .ioctl = snd_hdsp_ioctl,
5190 .hw_params = snd_hdsp_hw_params,
5191 .prepare = snd_hdsp_prepare,
5192 .trigger = snd_hdsp_trigger,
5193 .pointer = snd_hdsp_hw_pointer,
5194 .copy = snd_hdsp_playback_copy,
5195 .silence = snd_hdsp_hw_silence,
5196 };
5197
5198 static struct snd_pcm_ops snd_hdsp_capture_ops = {
5199 .open = snd_hdsp_capture_open,
5200 .close = snd_hdsp_capture_release,
5201 .ioctl = snd_hdsp_ioctl,
5202 .hw_params = snd_hdsp_hw_params,
5203 .prepare = snd_hdsp_prepare,
5204 .trigger = snd_hdsp_trigger,
5205 .pointer = snd_hdsp_hw_pointer,
5206 .copy = snd_hdsp_capture_copy,
5207 };
5208
5209 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
5210 {
5211 struct snd_hwdep *hw;
5212 int err;
5213
5214 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
5215 return err;
5216
5217 hdsp->hwdep = hw;
5218 hw->private_data = hdsp;
5219 strcpy(hw->name, "HDSP hwdep interface");
5220
5221 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
5222 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
5223
5224 return 0;
5225 }
5226
5227 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
5228 {
5229 struct snd_pcm *pcm;
5230 int err;
5231
5232 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
5233 return err;
5234
5235 hdsp->pcm = pcm;
5236 pcm->private_data = hdsp;
5237 strcpy(pcm->name, hdsp->card_name);
5238
5239 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
5240 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
5241
5242 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
5243
5244 return 0;
5245 }
5246
5247 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
5248 {
5249 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
5250 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
5251 }
5252
5253 static int snd_hdsp_enable_io (struct hdsp *hdsp)
5254 {
5255 int i;
5256
5257 if (hdsp_fifo_wait (hdsp, 0, 100)) {
5258 snd_printk(KERN_ERR "Hammerfall-DSP: enable_io fifo_wait failed\n");
5259 return -EIO;
5260 }
5261
5262 for (i = 0; i < hdsp->max_channels; ++i) {
5263 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
5264 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
5265 }
5266
5267 return 0;
5268 }
5269
5270 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
5271 {
5272 int status, aebi_channels, aebo_channels;
5273
5274 switch (hdsp->io_type) {
5275 case Digiface:
5276 hdsp->card_name = "RME Hammerfall DSP + Digiface";
5277 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
5278 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
5279 break;
5280
5281 case H9652:
5282 hdsp->card_name = "RME Hammerfall HDSP 9652";
5283 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
5284 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
5285 break;
5286
5287 case H9632:
5288 status = hdsp_read(hdsp, HDSP_statusRegister);
5289 /* HDSP_AEBx bits are low when AEB are connected */
5290 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
5291 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
5292 hdsp->card_name = "RME Hammerfall HDSP 9632";
5293 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5294 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5295 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5296 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5297 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5298 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5299 break;
5300
5301 case Multiface:
5302 hdsp->card_name = "RME Hammerfall DSP + Multiface";
5303 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5304 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5305 break;
5306
5307 case RPM:
5308 hdsp->card_name = "RME Hammerfall DSP + RPM";
5309 hdsp->ss_in_channels = RPM_CHANNELS-1;
5310 hdsp->ss_out_channels = RPM_CHANNELS;
5311 hdsp->ds_in_channels = RPM_CHANNELS-1;
5312 hdsp->ds_out_channels = RPM_CHANNELS;
5313 break;
5314
5315 default:
5316 /* should never get here */
5317 break;
5318 }
5319 }
5320
5321 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5322 {
5323 snd_hdsp_flush_midi_input (hdsp, 0);
5324 snd_hdsp_flush_midi_input (hdsp, 1);
5325 }
5326
5327 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5328 {
5329 int err;
5330
5331 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5332 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating pcm interface\n");
5333 return err;
5334 }
5335
5336
5337 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5338 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating first midi interface\n");
5339 return err;
5340 }
5341
5342 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5343 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5344 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating second midi interface\n");
5345 return err;
5346 }
5347 }
5348
5349 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5350 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating ctl interface\n");
5351 return err;
5352 }
5353
5354 snd_hdsp_proc_init(hdsp);
5355
5356 hdsp->system_sample_rate = -1;
5357 hdsp->playback_pid = -1;
5358 hdsp->capture_pid = -1;
5359 hdsp->capture_substream = NULL;
5360 hdsp->playback_substream = NULL;
5361
5362 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5363 snd_printk(KERN_ERR "Hammerfall-DSP: Error setting default values\n");
5364 return err;
5365 }
5366
5367 if (!(hdsp->state & HDSP_InitializationComplete)) {
5368 strcpy(card->shortname, "Hammerfall DSP");
5369 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5370 hdsp->port, hdsp->irq);
5371
5372 if ((err = snd_card_register(card)) < 0) {
5373 snd_printk(KERN_ERR "Hammerfall-DSP: error registering card\n");
5374 return err;
5375 }
5376 hdsp->state |= HDSP_InitializationComplete;
5377 }
5378
5379 return 0;
5380 }
5381
5382 /* load firmware via hotplug fw loader */
5383 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5384 {
5385 const char *fwfile;
5386 const struct firmware *fw;
5387 int err;
5388
5389 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5390 return 0;
5391 if (hdsp->io_type == Undefined) {
5392 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5393 return err;
5394 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5395 return 0;
5396 }
5397
5398 /* caution: max length of firmware filename is 30! */
5399 switch (hdsp->io_type) {
5400 case RPM:
5401 fwfile = "rpm_firmware.bin";
5402 break;
5403 case Multiface:
5404 if (hdsp->firmware_rev == 0xa)
5405 fwfile = "multiface_firmware.bin";
5406 else
5407 fwfile = "multiface_firmware_rev11.bin";
5408 break;
5409 case Digiface:
5410 if (hdsp->firmware_rev == 0xa)
5411 fwfile = "digiface_firmware.bin";
5412 else
5413 fwfile = "digiface_firmware_rev11.bin";
5414 break;
5415 default:
5416 snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type);
5417 return -EINVAL;
5418 }
5419
5420 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5421 snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile);
5422 return -ENOENT;
5423 }
5424 if (fw->size < HDSP_FIRMWARE_SIZE) {
5425 snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n",
5426 (int)fw->size, HDSP_FIRMWARE_SIZE);
5427 return -EINVAL;
5428 }
5429
5430 hdsp->firmware = fw;
5431
5432 hdsp->state |= HDSP_FirmwareCached;
5433
5434 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5435 return err;
5436
5437 if (!(hdsp->state & HDSP_InitializationComplete)) {
5438 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5439 return err;
5440
5441 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5442 snd_printk(KERN_ERR "Hammerfall-DSP: error creating hwdep device\n");
5443 return err;
5444 }
5445 snd_hdsp_initialize_channels(hdsp);
5446 snd_hdsp_initialize_midi_flush(hdsp);
5447 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5448 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
5449 return err;
5450 }
5451 }
5452 return 0;
5453 }
5454
5455 static int snd_hdsp_create(struct snd_card *card,
5456 struct hdsp *hdsp)
5457 {
5458 struct pci_dev *pci = hdsp->pci;
5459 int err;
5460 int is_9652 = 0;
5461 int is_9632 = 0;
5462
5463 hdsp->irq = -1;
5464 hdsp->state = 0;
5465 hdsp->midi[0].rmidi = NULL;
5466 hdsp->midi[1].rmidi = NULL;
5467 hdsp->midi[0].input = NULL;
5468 hdsp->midi[1].input = NULL;
5469 hdsp->midi[0].output = NULL;
5470 hdsp->midi[1].output = NULL;
5471 hdsp->midi[0].pending = 0;
5472 hdsp->midi[1].pending = 0;
5473 spin_lock_init(&hdsp->midi[0].lock);
5474 spin_lock_init(&hdsp->midi[1].lock);
5475 hdsp->iobase = NULL;
5476 hdsp->control_register = 0;
5477 hdsp->control2_register = 0;
5478 hdsp->io_type = Undefined;
5479 hdsp->max_channels = 26;
5480
5481 hdsp->card = card;
5482
5483 spin_lock_init(&hdsp->lock);
5484
5485 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5486
5487 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5488 hdsp->firmware_rev &= 0xff;
5489
5490 /* From Martin Bjoernsen :
5491 "It is important that the card's latency timer register in
5492 the PCI configuration space is set to a value much larger
5493 than 0 by the computer's BIOS or the driver.
5494 The windows driver always sets this 8 bit register [...]
5495 to its maximum 255 to avoid problems with some computers."
5496 */
5497 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5498
5499 strcpy(card->driver, "H-DSP");
5500 strcpy(card->mixername, "Xilinx FPGA");
5501
5502 if (hdsp->firmware_rev < 0xa)
5503 return -ENODEV;
5504 else if (hdsp->firmware_rev < 0x64)
5505 hdsp->card_name = "RME Hammerfall DSP";
5506 else if (hdsp->firmware_rev < 0x96) {
5507 hdsp->card_name = "RME HDSP 9652";
5508 is_9652 = 1;
5509 } else {
5510 hdsp->card_name = "RME HDSP 9632";
5511 hdsp->max_channels = 16;
5512 is_9632 = 1;
5513 }
5514
5515 if ((err = pci_enable_device(pci)) < 0)
5516 return err;
5517
5518 pci_set_master(hdsp->pci);
5519
5520 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5521 return err;
5522 hdsp->port = pci_resource_start(pci, 0);
5523 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5524 snd_printk(KERN_ERR "Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5525 return -EBUSY;
5526 }
5527
5528 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5529 KBUILD_MODNAME, hdsp)) {
5530 snd_printk(KERN_ERR "Hammerfall-DSP: unable to use IRQ %d\n", pci->irq);
5531 return -EBUSY;
5532 }
5533
5534 hdsp->irq = pci->irq;
5535 hdsp->precise_ptr = 0;
5536 hdsp->use_midi_tasklet = 1;
5537 hdsp->dds_value = 0;
5538
5539 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5540 return err;
5541
5542 if (!is_9652 && !is_9632) {
5543 /* we wait a maximum of 10 seconds to let freshly
5544 * inserted cardbus cards do their hardware init */
5545 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5546
5547 if (err < 0)
5548 return err;
5549
5550 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5551 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5552 /* we don't fail as this can happen
5553 if userspace is not ready for
5554 firmware upload
5555 */
5556 snd_printk(KERN_ERR "Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n");
5557 else
5558 /* init is complete, we return */
5559 return 0;
5560 /* we defer initialization */
5561 snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n");
5562 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5563 return err;
5564 return 0;
5565 } else {
5566 snd_printk(KERN_INFO "Hammerfall-DSP: Firmware already present, initializing card.\n");
5567 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5568 hdsp->io_type = RPM;
5569 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5570 hdsp->io_type = Multiface;
5571 else
5572 hdsp->io_type = Digiface;
5573 }
5574 }
5575
5576 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5577 return err;
5578
5579 if (is_9652)
5580 hdsp->io_type = H9652;
5581
5582 if (is_9632)
5583 hdsp->io_type = H9632;
5584
5585 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5586 return err;
5587
5588 snd_hdsp_initialize_channels(hdsp);
5589 snd_hdsp_initialize_midi_flush(hdsp);
5590
5591 hdsp->state |= HDSP_FirmwareLoaded;
5592
5593 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5594 return err;
5595
5596 return 0;
5597 }
5598
5599 static int snd_hdsp_free(struct hdsp *hdsp)
5600 {
5601 if (hdsp->port) {
5602 /* stop the audio, and cancel all interrupts */
5603 tasklet_kill(&hdsp->midi_tasklet);
5604 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5605 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5606 }
5607
5608 if (hdsp->irq >= 0)
5609 free_irq(hdsp->irq, (void *)hdsp);
5610
5611 snd_hdsp_free_buffers(hdsp);
5612
5613 if (hdsp->firmware)
5614 release_firmware(hdsp->firmware);
5615 vfree(hdsp->fw_uploaded);
5616
5617 if (hdsp->iobase)
5618 iounmap(hdsp->iobase);
5619
5620 if (hdsp->port)
5621 pci_release_regions(hdsp->pci);
5622
5623 pci_disable_device(hdsp->pci);
5624 return 0;
5625 }
5626
5627 static void snd_hdsp_card_free(struct snd_card *card)
5628 {
5629 struct hdsp *hdsp = card->private_data;
5630
5631 if (hdsp)
5632 snd_hdsp_free(hdsp);
5633 }
5634
5635 static int snd_hdsp_probe(struct pci_dev *pci,
5636 const struct pci_device_id *pci_id)
5637 {
5638 static int dev;
5639 struct hdsp *hdsp;
5640 struct snd_card *card;
5641 int err;
5642
5643 if (dev >= SNDRV_CARDS)
5644 return -ENODEV;
5645 if (!enable[dev]) {
5646 dev++;
5647 return -ENOENT;
5648 }
5649
5650 err = snd_card_create(index[dev], id[dev], THIS_MODULE,
5651 sizeof(struct hdsp), &card);
5652 if (err < 0)
5653 return err;
5654
5655 hdsp = card->private_data;
5656 card->private_free = snd_hdsp_card_free;
5657 hdsp->dev = dev;
5658 hdsp->pci = pci;
5659 snd_card_set_dev(card, &pci->dev);
5660
5661 if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5662 snd_card_free(card);
5663 return err;
5664 }
5665
5666 strcpy(card->shortname, "Hammerfall DSP");
5667 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5668 hdsp->port, hdsp->irq);
5669
5670 if ((err = snd_card_register(card)) < 0) {
5671 snd_card_free(card);
5672 return err;
5673 }
5674 pci_set_drvdata(pci, card);
5675 dev++;
5676 return 0;
5677 }
5678
5679 static void snd_hdsp_remove(struct pci_dev *pci)
5680 {
5681 snd_card_free(pci_get_drvdata(pci));
5682 pci_set_drvdata(pci, NULL);
5683 }
5684
5685 static struct pci_driver hdsp_driver = {
5686 .name = KBUILD_MODNAME,
5687 .id_table = snd_hdsp_ids,
5688 .probe = snd_hdsp_probe,
5689 .remove = snd_hdsp_remove,
5690 };
5691
5692 module_pci_driver(hdsp_driver);
Linux kernel - Deliverables
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