sound/pci/rme9652/hdsp.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP audio interface(s)
   3  *
   4  *      Copyright (c) 2002  Paul Davis
   5  *                          Marcus Andersson
   6  *                          Thomas Charbonnel
   7  *
   8  *   This program is free software; you can redistribute it and/or modify
   9  *   it under the terms of the GNU General Public License as published by
  10  *   the Free Software Foundation; either version 2 of the License, or
  11  *   (at your option) any later version.
  12  *
  13  *   This program is distributed in the hope that it will be useful,
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *   GNU General Public License for more details.
  17  *
  18  *   You should have received a copy of the GNU General Public License
  19  *   along with this program; if not, write to the Free Software
  20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/delay.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/pci.h>
  28 #include <linux/firmware.h>
  29 #include <linux/module.h>
  30 #include <linux/math64.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/io.h>
  33
  34 #include <sound/core.h>
  35 #include <sound/control.h>
  36 #include <sound/pcm.h>
  37 #include <sound/info.h>
  38 #include <sound/asoundef.h>
  39 #include <sound/rawmidi.h>
  40 #include <sound/hwdep.h>
  41 #include <sound/initval.h>
  42 #include <sound/hdsp.h>
  43
  44 #include <asm/byteorder.h>
  45 #include <asm/current.h>
  46
  47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  49 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
  50
  51 module_param_array(index, int, NULL, 0444);
  52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
  53 module_param_array(id, charp, NULL, 0444);
  54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
  55 module_param_array(enable, bool, NULL, 0444);
  56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
  57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
  58 MODULE_DESCRIPTION("RME Hammerfall DSP");
  59 MODULE_LICENSE("GPL");
  60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
  61                 "{RME HDSP-9652},"
  62                 "{RME HDSP-9632}}");
  63 MODULE_FIRMWARE("rpm_firmware.bin");
  64 MODULE_FIRMWARE("multiface_firmware.bin");
  65 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
  66 MODULE_FIRMWARE("digiface_firmware.bin");
  67 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
  68
  69 #define HDSP_MAX_CHANNELS        26
  70 #define HDSP_MAX_DS_CHANNELS     14
  71 #define HDSP_MAX_QS_CHANNELS     8
  72 #define DIGIFACE_SS_CHANNELS     26
  73 #define DIGIFACE_DS_CHANNELS     14
  74 #define MULTIFACE_SS_CHANNELS    18
  75 #define MULTIFACE_DS_CHANNELS    14
  76 #define H9652_SS_CHANNELS        26
  77 #define H9652_DS_CHANNELS        14
  78 /* This does not include possible Analog Extension Boards
  79    AEBs are detected at card initialization
  80 */
  81 #define H9632_SS_CHANNELS        12
  82 #define H9632_DS_CHANNELS        8
  83 #define H9632_QS_CHANNELS        4
  84 #define RPM_CHANNELS             6
  85
  86 /* Write registers. These are defined as byte-offsets from the iobase value.
  87  */
  88 #define HDSP_resetPointer               0
  89 #define HDSP_freqReg                    0
  90 #define HDSP_outputBufferAddress        32
  91 #define HDSP_inputBufferAddress         36
  92 #define HDSP_controlRegister            64
  93 #define HDSP_interruptConfirmation      96
  94 #define HDSP_outputEnable               128
  95 #define HDSP_control2Reg                256
  96 #define HDSP_midiDataOut0               352
  97 #define HDSP_midiDataOut1               356
  98 #define HDSP_fifoData                   368
  99 #define HDSP_inputEnable                384
 100
 101 /* Read registers. These are defined as byte-offsets from the iobase value
 102  */
 103
 104 #define HDSP_statusRegister    0
 105 #define HDSP_timecode        128
 106 #define HDSP_status2Register 192
 107 #define HDSP_midiDataIn0     360
 108 #define HDSP_midiDataIn1     364
 109 #define HDSP_midiStatusOut0  384
 110 #define HDSP_midiStatusOut1  388
 111 #define HDSP_midiStatusIn0   392
 112 #define HDSP_midiStatusIn1   396
 113 #define HDSP_fifoStatus      400
 114
 115 /* the meters are regular i/o-mapped registers, but offset
 116    considerably from the rest. the peak registers are reset
 117    when read; the least-significant 4 bits are full-scale counters;
 118    the actual peak value is in the most-significant 24 bits.
 119 */
 120
 121 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
 122 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
 123 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
 124 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
 125 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
 126
 127
 128 /* This is for H9652 cards
 129    Peak values are read downward from the base
 130    Rms values are read upward
 131    There are rms values for the outputs too
 132    26*3 values are read in ss mode
 133    14*3 in ds mode, with no gap between values
 134 */
 135 #define HDSP_9652_peakBase      7164
 136 #define HDSP_9652_rmsBase       4096
 137
 138 /* c.f. the hdsp_9632_meters_t struct */
 139 #define HDSP_9632_metersBase    4096
 140
 141 #define HDSP_IO_EXTENT     7168
 142
 143 /* control2 register bits */
 144
 145 #define HDSP_TMS                0x01
 146 #define HDSP_TCK                0x02
 147 #define HDSP_TDI                0x04
 148 #define HDSP_JTAG               0x08
 149 #define HDSP_PWDN               0x10
 150 #define HDSP_PROGRAM            0x020
 151 #define HDSP_CONFIG_MODE_0      0x040
 152 #define HDSP_CONFIG_MODE_1      0x080
 153 #define HDSP_VERSION_BIT        (0x100 | HDSP_S_LOAD)
 154 #define HDSP_BIGENDIAN_MODE     0x200
 155 #define HDSP_RD_MULTIPLE        0x400
 156 #define HDSP_9652_ENABLE_MIXER  0x800
 157 #define HDSP_S200               0x800
 158 #define HDSP_S300               (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
 159 #define HDSP_CYCLIC_MODE        0x1000
 160 #define HDSP_TDO                0x10000000
 161
 162 #define HDSP_S_PROGRAM      (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
 163 #define HDSP_S_LOAD         (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
 164
 165 /* Control Register bits */
 166
 167 #define HDSP_Start                (1<<0)  /* start engine */
 168 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
 169 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
 170 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
 171 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
 172 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
 173 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
 174 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
 175 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
 176 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
 177 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
 178 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
 179 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
 180 #define HDSP_SyncRef2             (1<<13)
 181 #define HDSP_SPDIFInputSelect0    (1<<14)
 182 #define HDSP_SPDIFInputSelect1    (1<<15)
 183 #define HDSP_SyncRef0             (1<<16)
 184 #define HDSP_SyncRef1             (1<<17)
 185 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
 186 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
 187 #define HDSP_Midi0InterruptEnable (1<<22)
 188 #define HDSP_Midi1InterruptEnable (1<<23)
 189 #define HDSP_LineOut              (1<<24)
 190 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
 191 #define HDSP_ADGain1              (1<<26)
 192 #define HDSP_DAGain0              (1<<27)
 193 #define HDSP_DAGain1              (1<<28)
 194 #define HDSP_PhoneGain0           (1<<29)
 195 #define HDSP_PhoneGain1           (1<<30)
 196 #define HDSP_QuadSpeed            (1<<31)
 197
 198 /* RPM uses some of the registers for special purposes */
 199 #define HDSP_RPM_Inp12            0x04A00
 200 #define HDSP_RPM_Inp12_Phon_6dB   0x00800  /* Dolby */
 201 #define HDSP_RPM_Inp12_Phon_0dB   0x00000  /* .. */
 202 #define HDSP_RPM_Inp12_Phon_n6dB  0x04000  /* inp_0 */
 203 #define HDSP_RPM_Inp12_Line_0dB   0x04200  /* Dolby+PRO */
 204 #define HDSP_RPM_Inp12_Line_n6dB  0x00200  /* PRO */
 205
 206 #define HDSP_RPM_Inp34            0x32000
 207 #define HDSP_RPM_Inp34_Phon_6dB   0x20000  /* SyncRef1 */
 208 #define HDSP_RPM_Inp34_Phon_0dB   0x00000  /* .. */
 209 #define HDSP_RPM_Inp34_Phon_n6dB  0x02000  /* SyncRef2 */
 210 #define HDSP_RPM_Inp34_Line_0dB   0x30000  /* SyncRef1+SyncRef0 */
 211 #define HDSP_RPM_Inp34_Line_n6dB  0x10000  /* SyncRef0 */
 212
 213 #define HDSP_RPM_Bypass           0x01000
 214
 215 #define HDSP_RPM_Disconnect       0x00001
 216
 217 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
 218 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
 219 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
 220 #define HDSP_ADGainLowGain     0
 221
 222 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
 223 #define HDSP_DAGainHighGain      HDSP_DAGainMask
 224 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
 225 #define HDSP_DAGainMinus10dBV    0
 226
 227 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
 228 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
 229 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
 230 #define HDSP_PhoneGainMinus12dB  0
 231
 232 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
 233 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
 234
 235 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 236 #define HDSP_SPDIFInputADAT1    0
 237 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
 238 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
 239 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 240
 241 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
 242 #define HDSP_SyncRef_ADAT1       0
 243 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
 244 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
 245 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
 246 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
 247 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
 248
 249 /* Sample Clock Sources */
 250
 251 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
 252 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
 253 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
 254 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
 255 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
 256 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
 257 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
 258 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
 259 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
 260 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
 261
 262 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
 263
 264 #define HDSP_SYNC_FROM_WORD      0
 265 #define HDSP_SYNC_FROM_SPDIF     1
 266 #define HDSP_SYNC_FROM_ADAT1     2
 267 #define HDSP_SYNC_FROM_ADAT_SYNC 3
 268 #define HDSP_SYNC_FROM_ADAT2     4
 269 #define HDSP_SYNC_FROM_ADAT3     5
 270
 271 /* SyncCheck status */
 272
 273 #define HDSP_SYNC_CHECK_NO_LOCK 0
 274 #define HDSP_SYNC_CHECK_LOCK    1
 275 #define HDSP_SYNC_CHECK_SYNC    2
 276
 277 /* AutoSync references - used by "autosync_ref" control switch */
 278
 279 #define HDSP_AUTOSYNC_FROM_WORD      0
 280 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
 281 #define HDSP_AUTOSYNC_FROM_SPDIF     2
 282 #define HDSP_AUTOSYNC_FROM_NONE      3
 283 #define HDSP_AUTOSYNC_FROM_ADAT1     4
 284 #define HDSP_AUTOSYNC_FROM_ADAT2     5
 285 #define HDSP_AUTOSYNC_FROM_ADAT3     6
 286
 287 /* Possible sources of S/PDIF input */
 288
 289 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
 290 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
 291 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
 292 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
 293
 294 #define HDSP_Frequency32KHz    HDSP_Frequency0
 295 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
 296 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
 297 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
 298 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
 299 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 300 /* For H9632 cards */
 301 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
 302 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
 303 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 304 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
 305         return 104857600000000 / rate; // 100 MHz
 306         return 110100480000000 / rate; // 105 MHz
 307 */
 308 #define DDS_NUMERATOR 104857600000000ULL;  /*  =  2^20 * 10^8 */
 309
 310 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
 311 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
 312
 313 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
 314 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
 315
 316 /* Status Register bits */
 317
 318 #define HDSP_audioIRQPending    (1<<0)
 319 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
 320 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
 321 #define HDSP_Lock1              (1<<2)
 322 #define HDSP_Lock0              (1<<3)
 323 #define HDSP_SPDIFSync          (1<<4)
 324 #define HDSP_TimecodeLock       (1<<5)
 325 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 326 #define HDSP_Sync2              (1<<16)
 327 #define HDSP_Sync1              (1<<17)
 328 #define HDSP_Sync0              (1<<18)
 329 #define HDSP_DoubleSpeedStatus  (1<<19)
 330 #define HDSP_ConfigError        (1<<20)
 331 #define HDSP_DllError           (1<<21)
 332 #define HDSP_spdifFrequency0    (1<<22)
 333 #define HDSP_spdifFrequency1    (1<<23)
 334 #define HDSP_spdifFrequency2    (1<<24)
 335 #define HDSP_SPDIFErrorFlag     (1<<25)
 336 #define HDSP_BufferID           (1<<26)
 337 #define HDSP_TimecodeSync       (1<<27)
 338 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
 339 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
 340 #define HDSP_midi0IRQPending    (1<<30)
 341 #define HDSP_midi1IRQPending    (1<<31)
 342
 343 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
 344 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
 345                                       HDSP_spdifFrequency1|\
 346                                       HDSP_spdifFrequency2|\
 347                                       HDSP_spdifFrequency3)
 348
 349 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
 350 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
 351 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
 352
 353 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
 354 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
 355 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
 356
 357 /* This is for H9632 cards */
 358 #define HDSP_spdifFrequency128KHz   (HDSP_spdifFrequency0|\
 359                                      HDSP_spdifFrequency1|\
 360                                      HDSP_spdifFrequency2)
 361 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
 362 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
 363
 364 /* Status2 Register bits */
 365
 366 #define HDSP_version0     (1<<0)
 367 #define HDSP_version1     (1<<1)
 368 #define HDSP_version2     (1<<2)
 369 #define HDSP_wc_lock      (1<<3)
 370 #define HDSP_wc_sync      (1<<4)
 371 #define HDSP_inp_freq0    (1<<5)
 372 #define HDSP_inp_freq1    (1<<6)
 373 #define HDSP_inp_freq2    (1<<7)
 374 #define HDSP_SelSyncRef0  (1<<8)
 375 #define HDSP_SelSyncRef1  (1<<9)
 376 #define HDSP_SelSyncRef2  (1<<10)
 377
 378 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
 379
 380 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
 381 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
 382 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
 383 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
 384 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
 385 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
 386 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
 387 /* FIXME : more values for 9632 cards ? */
 388
 389 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
 390 #define HDSP_SelSyncRef_ADAT1      0
 391 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
 392 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
 393 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
 394 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
 395 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
 396
 397 /* Card state flags */
 398
 399 #define HDSP_InitializationComplete  (1<<0)
 400 #define HDSP_FirmwareLoaded          (1<<1)
 401 #define HDSP_FirmwareCached          (1<<2)
 402
 403 /* FIFO wait times, defined in terms of 1/10ths of msecs */
 404
 405 #define HDSP_LONG_WAIT   5000
 406 #define HDSP_SHORT_WAIT  30
 407
 408 #define UNITY_GAIN                       32768
 409 #define MINUS_INFINITY_GAIN              0
 410
 411 /* the size of a substream (1 mono data stream) */
 412
 413 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
 414 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
 415
 416 /* the size of the area we need to allocate for DMA transfers. the
 417    size is the same regardless of the number of channels - the
 418    Multiface still uses the same memory area.
 419
 420    Note that we allocate 1 more channel than is apparently needed
 421    because the h/w seems to write 1 byte beyond the end of the last
 422    page. Sigh.
 423 */
 424
 425 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
 426 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
 427
 428 #define HDSP_FIRMWARE_SIZE      (24413 * 4)
 429
 430 struct hdsp_9632_meters {
 431     u32 input_peak[16];
 432     u32 playback_peak[16];
 433     u32 output_peak[16];
 434     u32 xxx_peak[16];
 435     u32 padding[64];
 436     u32 input_rms_low[16];
 437     u32 playback_rms_low[16];
 438     u32 output_rms_low[16];
 439     u32 xxx_rms_low[16];
 440     u32 input_rms_high[16];
 441     u32 playback_rms_high[16];
 442     u32 output_rms_high[16];
 443     u32 xxx_rms_high[16];
 444 };
 445
 446 struct hdsp_midi {
 447     struct hdsp             *hdsp;
 448     int                      id;
 449     struct snd_rawmidi           *rmidi;
 450     struct snd_rawmidi_substream *input;
 451     struct snd_rawmidi_substream *output;
 452     char                     istimer; /* timer in use */
 453     struct timer_list        timer;
 454     spinlock_t               lock;
 455     int                      pending;
 456 };
 457
 458 struct hdsp {
 459         spinlock_t            lock;
 460         struct snd_pcm_substream *capture_substream;
 461         struct snd_pcm_substream *playback_substream;
 462         struct hdsp_midi      midi[2];
 463         struct tasklet_struct midi_tasklet;
 464         int                   use_midi_tasklet;
 465         int                   precise_ptr;
 466         u32                   control_register;      /* cached value */
 467         u32                   control2_register;     /* cached value */
 468         u32                   creg_spdif;
 469         u32                   creg_spdif_stream;
 470         int                   clock_source_locked;
 471         char                 *card_name;         /* digiface/multiface/rpm */
 472         enum HDSP_IO_Type     io_type;               /* ditto, but for code use */
 473         unsigned short        firmware_rev;
 474         unsigned short        state;                 /* stores state bits */
 475         const struct firmware *firmware;
 476         u32                  *fw_uploaded;
 477         size_t                period_bytes;          /* guess what this is */
 478         unsigned char         max_channels;
 479         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
 480         unsigned char         ds_in_channels;
 481         unsigned char         ss_in_channels;       /* different for multiface/digiface */
 482         unsigned char         qs_out_channels;
 483         unsigned char         ds_out_channels;
 484         unsigned char         ss_out_channels;
 485
 486         struct snd_dma_buffer capture_dma_buf;
 487         struct snd_dma_buffer playback_dma_buf;
 488         unsigned char        *capture_buffer;       /* suitably aligned address */
 489         unsigned char        *playback_buffer;      /* suitably aligned address */
 490
 491         pid_t                 capture_pid;
 492         pid_t                 playback_pid;
 493         int                   running;
 494         int                   system_sample_rate;
 495         char                 *channel_map;
 496         int                   dev;
 497         int                   irq;
 498         unsigned long         port;
 499         void __iomem         *iobase;
 500         struct snd_card *card;
 501         struct snd_pcm *pcm;
 502         struct snd_hwdep          *hwdep;
 503         struct pci_dev       *pci;
 504         struct snd_kcontrol *spdif_ctl;
 505         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
 506         unsigned int          dds_value; /* last value written to freq register */
 507 };
 508
 509 /* These tables map the ALSA channels 1..N to the channels that we
 510    need to use in order to find the relevant channel buffer. RME
 511    refer to this kind of mapping as between "the ADAT channel and
 512    the DMA channel." We index it using the logical audio channel,
 513    and the value is the DMA channel (i.e. channel buffer number)
 514    where the data for that channel can be read/written from/to.
 515 */
 516
 517 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
 518         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
 519         18, 19, 20, 21, 22, 23, 24, 25
 520 };
 521
 522 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
 523         /* Analog */
 524         0, 1, 2, 3, 4, 5, 6, 7,
 525         /* ADAT 2 */
 526         16, 17, 18, 19, 20, 21, 22, 23,
 527         /* SPDIF */
 528         24, 25,
 529         -1, -1, -1, -1, -1, -1, -1, -1
 530 };
 531
 532 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
 533         /* ADAT channels are remapped */
 534         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
 535         /* channels 12 and 13 are S/PDIF */
 536         24, 25,
 537         /* others don't exist */
 538         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 539 };
 540
 541 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
 542         /* ADAT channels */
 543         0, 1, 2, 3, 4, 5, 6, 7,
 544         /* SPDIF */
 545         8, 9,
 546         /* Analog */
 547         10, 11,
 548         /* AO4S-192 and AI4S-192 extension boards */
 549         12, 13, 14, 15,
 550         /* others don't exist */
 551         -1, -1, -1, -1, -1, -1, -1, -1,
 552         -1, -1
 553 };
 554
 555 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
 556         /* ADAT */
 557         1, 3, 5, 7,
 558         /* SPDIF */
 559         8, 9,
 560         /* Analog */
 561         10, 11,
 562         /* AO4S-192 and AI4S-192 extension boards */
 563         12, 13, 14, 15,
 564         /* others don't exist */
 565         -1, -1, -1, -1, -1, -1, -1, -1,
 566         -1, -1, -1, -1, -1, -1
 567 };
 568
 569 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
 570         /* ADAT is disabled in this mode */
 571         /* SPDIF */
 572         8, 9,
 573         /* Analog */
 574         10, 11,
 575         /* AO4S-192 and AI4S-192 extension boards */
 576         12, 13, 14, 15,
 577         /* others don't exist */
 578         -1, -1, -1, -1, -1, -1, -1, -1,
 579         -1, -1, -1, -1, -1, -1, -1, -1,
 580         -1, -1
 581 };
 582
 583 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
 584 {
 585         dmab->dev.type = SNDRV_DMA_TYPE_DEV;
 586         dmab->dev.dev = snd_dma_pci_data(pci);
 587         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
 588                                 size, dmab) < 0)
 589                 return -ENOMEM;
 590         return 0;
 591 }
 592
 593 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
 594 {
 595         if (dmab->area)
 596                 snd_dma_free_pages(dmab);
 597 }
 598
 599
 600 static const struct pci_device_id snd_hdsp_ids[] = {
 601         {
 602                 .vendor = PCI_VENDOR_ID_XILINX,
 603                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
 604                 .subvendor = PCI_ANY_ID,
 605                 .subdevice = PCI_ANY_ID,
 606         }, /* RME Hammerfall-DSP */
 607         { 0, },
 608 };
 609
 610 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
 611
 612 /* prototypes */
 613 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
 614 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
 615 static int snd_hdsp_enable_io (struct hdsp *hdsp);
 616 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
 617 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
 618 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
 619 static int hdsp_autosync_ref(struct hdsp *hdsp);
 620 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
 621 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
 622
 623 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
 624 {
 625         switch (hdsp->io_type) {
 626         case Multiface:
 627         case Digiface:
 628         case RPM:
 629         default:
 630                 if (hdsp->firmware_rev == 0xa)
 631                         return (64 * out) + (32 + (in));
 632                 else
 633                         return (52 * out) + (26 + (in));
 634         case H9632:
 635                 return (32 * out) + (16 + (in));
 636         case H9652:
 637                 return (52 * out) + (26 + (in));
 638         }
 639 }
 640
 641 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
 642 {
 643         switch (hdsp->io_type) {
 644         case Multiface:
 645         case Digiface:
 646         case RPM:
 647         default:
 648                 if (hdsp->firmware_rev == 0xa)
 649                         return (64 * out) + in;
 650                 else
 651                         return (52 * out) + in;
 652         case H9632:
 653                 return (32 * out) + in;
 654         case H9652:
 655                 return (52 * out) + in;
 656         }
 657 }
 658
 659 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
 660 {
 661         writel(val, hdsp->iobase + reg);
 662 }
 663
 664 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
 665 {
 666         return readl (hdsp->iobase + reg);
 667 }
 668
 669 static int hdsp_check_for_iobox (struct hdsp *hdsp)
 670 {
 671         int i;
 672
 673         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 674         for (i = 0; i < 500; i++) {
 675                 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
 676                                         HDSP_ConfigError)) {
 677                         if (i) {
 678                                 dev_dbg(hdsp->card->dev,
 679                                         "IO box found after %d ms\n",
 680                                                 (20 * i));
 681                         }
 682                         return 0;
 683                 }
 684                 msleep(20);
 685         }
 686         dev_err(hdsp->card->dev, "no IO box connected!\n");
 687         hdsp->state &= ~HDSP_FirmwareLoaded;
 688         return -EIO;
 689 }
 690
 691 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
 692                                unsigned int delay)
 693 {
 694         unsigned int i;
 695
 696         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 697                 return 0;
 698
 699         for (i = 0; i != loops; ++i) {
 700                 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
 701                         msleep(delay);
 702                 else {
 703                         dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
 704                                    i * delay);
 705                         return 0;
 706                 }
 707         }
 708
 709         dev_info(hdsp->card->dev, "no IO box connected!\n");
 710         hdsp->state &= ~HDSP_FirmwareLoaded;
 711         return -EIO;
 712 }
 713
 714 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
 715
 716         int i;
 717         unsigned long flags;
 718         const u32 *cache;
 719
 720         if (hdsp->fw_uploaded)
 721                 cache = hdsp->fw_uploaded;
 722         else {
 723                 if (!hdsp->firmware)
 724                         return -ENODEV;
 725                 cache = (u32 *)hdsp->firmware->data;
 726                 if (!cache)
 727                         return -ENODEV;
 728         }
 729
 730         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 731
 732                 dev_info(hdsp->card->dev, "loading firmware\n");
 733
 734                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
 735                 hdsp_write (hdsp, HDSP_fifoData, 0);
 736
 737                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 738                         dev_info(hdsp->card->dev,
 739                                  "timeout waiting for download preparation\n");
 740                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 741                         return -EIO;
 742                 }
 743
 744                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 745
 746                 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
 747                         hdsp_write(hdsp, HDSP_fifoData, cache[i]);
 748                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
 749                                 dev_info(hdsp->card->dev,
 750                                          "timeout during firmware loading\n");
 751                                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 752                                 return -EIO;
 753                         }
 754                 }
 755
 756                 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
 757                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 758
 759                 ssleep(3);
 760 #ifdef SNDRV_BIG_ENDIAN
 761                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
 762 #else
 763                 hdsp->control2_register = 0;
 764 #endif
 765                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
 766                 dev_info(hdsp->card->dev, "finished firmware loading\n");
 767
 768         }
 769         if (hdsp->state & HDSP_InitializationComplete) {
 770                 dev_info(hdsp->card->dev,
 771                          "firmware loaded from cache, restoring defaults\n");
 772                 spin_lock_irqsave(&hdsp->lock, flags);
 773                 snd_hdsp_set_defaults(hdsp);
 774                 spin_unlock_irqrestore(&hdsp->lock, flags);
 775         }
 776
 777         hdsp->state |= HDSP_FirmwareLoaded;
 778
 779         return 0;
 780 }
 781
 782 static int hdsp_get_iobox_version (struct hdsp *hdsp)
 783 {
 784         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 785
 786                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 787                 hdsp_write(hdsp, HDSP_fifoData, 0);
 788
 789                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 790                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 791                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 792                 }
 793
 794                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
 795                 hdsp_write (hdsp, HDSP_fifoData, 0);
 796                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 797                         hdsp->io_type = Multiface;
 798                         dev_info(hdsp->card->dev, "Multiface found\n");
 799                         return 0;
 800                 }
 801
 802                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 803                 hdsp_write(hdsp, HDSP_fifoData, 0);
 804                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
 805                         hdsp->io_type = Digiface;
 806                         dev_info(hdsp->card->dev, "Digiface found\n");
 807                         return 0;
 808                 }
 809
 810                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 811                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 812                 hdsp_write(hdsp, HDSP_fifoData, 0);
 813                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
 814                         hdsp->io_type = Multiface;
 815                         dev_info(hdsp->card->dev, "Multiface found\n");
 816                         return 0;
 817                 }
 818
 819                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 820                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 821                 hdsp_write(hdsp, HDSP_fifoData, 0);
 822                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 823                         hdsp->io_type = Multiface;
 824                         dev_info(hdsp->card->dev, "Multiface found\n");
 825                         return 0;
 826                 }
 827
 828                 hdsp->io_type = RPM;
 829                 dev_info(hdsp->card->dev, "RPM found\n");
 830                 return 0;
 831         } else {
 832                 /* firmware was already loaded, get iobox type */
 833                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
 834                         hdsp->io_type = RPM;
 835                 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
 836                         hdsp->io_type = Multiface;
 837                 else
 838                         hdsp->io_type = Digiface;
 839         }
 840         return 0;
 841 }
 842
 843
 844 static int hdsp_request_fw_loader(struct hdsp *hdsp);
 845
 846 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
 847 {
 848         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 849                 return 0;
 850         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 851                 hdsp->state &= ~HDSP_FirmwareLoaded;
 852                 if (! load_on_demand)
 853                         return -EIO;
 854                 dev_err(hdsp->card->dev, "firmware not present.\n");
 855                 /* try to load firmware */
 856                 if (! (hdsp->state & HDSP_FirmwareCached)) {
 857                         if (! hdsp_request_fw_loader(hdsp))
 858                                 return 0;
 859                         dev_err(hdsp->card->dev,
 860                                    "No firmware loaded nor cached, please upload firmware.\n");
 861                         return -EIO;
 862                 }
 863                 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
 864                         dev_err(hdsp->card->dev,
 865                                    "Firmware loading from cache failed, please upload manually.\n");
 866                         return -EIO;
 867                 }
 868         }
 869         return 0;
 870 }
 871
 872
 873 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
 874 {
 875         int i;
 876
 877         /* the fifoStatus registers reports on how many words
 878            are available in the command FIFO.
 879         */
 880
 881         for (i = 0; i < timeout; i++) {
 882
 883                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
 884                         return 0;
 885
 886                 /* not very friendly, but we only do this during a firmware
 887                    load and changing the mixer, so we just put up with it.
 888                 */
 889
 890                 udelay (100);
 891         }
 892
 893         dev_warn(hdsp->card->dev,
 894                  "wait for FIFO status <= %d failed after %d iterations\n",
 895                     count, timeout);
 896         return -1;
 897 }
 898
 899 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
 900 {
 901         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 902                 return 0;
 903
 904         return hdsp->mixer_matrix[addr];
 905 }
 906
 907 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
 908 {
 909         unsigned int ad;
 910
 911         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 912                 return -1;
 913
 914         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
 915
 916                 /* from martin bjornsen:
 917
 918                    "You can only write dwords to the
 919                    mixer memory which contain two
 920                    mixer values in the low and high
 921                    word. So if you want to change
 922                    value 0 you have to read value 1
 923                    from the cache and write both to
 924                    the first dword in the mixer
 925                    memory."
 926                 */
 927
 928                 if (hdsp->io_type == H9632 && addr >= 512)
 929                         return 0;
 930
 931                 if (hdsp->io_type == H9652 && addr >= 1352)
 932                         return 0;
 933
 934                 hdsp->mixer_matrix[addr] = data;
 935
 936
 937                 /* `addr' addresses a 16-bit wide address, but
 938                    the address space accessed via hdsp_write
 939                    uses byte offsets. put another way, addr
 940                    varies from 0 to 1351, but to access the
 941                    corresponding memory location, we need
 942                    to access 0 to 2703 ...
 943                 */
 944                 ad = addr/2;
 945
 946                 hdsp_write (hdsp, 4096 + (ad*4),
 947                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
 948                             hdsp->mixer_matrix[addr&0x7fe]);
 949
 950                 return 0;
 951
 952         } else {
 953
 954                 ad = (addr << 16) + data;
 955
 956                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
 957                         return -1;
 958
 959                 hdsp_write (hdsp, HDSP_fifoData, ad);
 960                 hdsp->mixer_matrix[addr] = data;
 961
 962         }
 963
 964         return 0;
 965 }
 966
 967 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
 968 {
 969         unsigned long flags;
 970         int ret = 1;
 971
 972         spin_lock_irqsave(&hdsp->lock, flags);
 973         if ((hdsp->playback_pid != hdsp->capture_pid) &&
 974             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
 975                 ret = 0;
 976         spin_unlock_irqrestore(&hdsp->lock, flags);
 977         return ret;
 978 }
 979
 980 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
 981 {
 982         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
 983         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
 984
 985         /* For the 9632, the mask is different */
 986         if (hdsp->io_type == H9632)
 987                  rate_bits = (status & HDSP_spdifFrequencyMask_9632);
 988
 989         if (status & HDSP_SPDIFErrorFlag)
 990                 return 0;
 991
 992         switch (rate_bits) {
 993         case HDSP_spdifFrequency32KHz: return 32000;
 994         case HDSP_spdifFrequency44_1KHz: return 44100;
 995         case HDSP_spdifFrequency48KHz: return 48000;
 996         case HDSP_spdifFrequency64KHz: return 64000;
 997         case HDSP_spdifFrequency88_2KHz: return 88200;
 998         case HDSP_spdifFrequency96KHz: return 96000;
 999         case HDSP_spdifFrequency128KHz:
1000                 if (hdsp->io_type == H9632) return 128000;
1001                 break;
1002         case HDSP_spdifFrequency176_4KHz:
1003                 if (hdsp->io_type == H9632) return 176400;
1004                 break;
1005         case HDSP_spdifFrequency192KHz:
1006                 if (hdsp->io_type == H9632) return 192000;
1007                 break;
1008         default:
1009                 break;
1010         }
1011         dev_warn(hdsp->card->dev,
1012                  "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
1013                  rate_bits, status);
1014         return 0;
1015 }
1016
1017 static int hdsp_external_sample_rate(struct hdsp *hdsp)
1018 {
1019         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
1020         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1021
1022         /* For the 9632 card, there seems to be no bit for indicating external
1023          * sample rate greater than 96kHz. The card reports the corresponding
1024          * single speed. So the best means seems to get spdif rate when
1025          * autosync reference is spdif */
1026         if (hdsp->io_type == H9632 &&
1027             hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1028                  return hdsp_spdif_sample_rate(hdsp);
1029
1030         switch (rate_bits) {
1031         case HDSP_systemFrequency32:   return 32000;
1032         case HDSP_systemFrequency44_1: return 44100;
1033         case HDSP_systemFrequency48:   return 48000;
1034         case HDSP_systemFrequency64:   return 64000;
1035         case HDSP_systemFrequency88_2: return 88200;
1036         case HDSP_systemFrequency96:   return 96000;
1037         default:
1038                 return 0;
1039         }
1040 }
1041
1042 static void hdsp_compute_period_size(struct hdsp *hdsp)
1043 {
1044         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1045 }
1046
1047 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1048 {
1049         int position;
1050
1051         position = hdsp_read(hdsp, HDSP_statusRegister);
1052
1053         if (!hdsp->precise_ptr)
1054                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1055
1056         position &= HDSP_BufferPositionMask;
1057         position /= 4;
1058         position &= (hdsp->period_bytes/2) - 1;
1059         return position;
1060 }
1061
1062 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1063 {
1064         hdsp_write (hdsp, HDSP_resetPointer, 0);
1065         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1066                 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1067                  * requires (?) to write again DDS value after a reset pointer
1068                  * (at least, it works like this) */
1069                 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1070 }
1071
1072 static void hdsp_start_audio(struct hdsp *s)
1073 {
1074         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1075         hdsp_write(s, HDSP_controlRegister, s->control_register);
1076 }
1077
1078 static void hdsp_stop_audio(struct hdsp *s)
1079 {
1080         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1081         hdsp_write(s, HDSP_controlRegister, s->control_register);
1082 }
1083
1084 static void hdsp_silence_playback(struct hdsp *hdsp)
1085 {
1086         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1087 }
1088
1089 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1090 {
1091         int n;
1092
1093         spin_lock_irq(&s->lock);
1094
1095         frames >>= 7;
1096         n = 0;
1097         while (frames) {
1098                 n++;
1099                 frames >>= 1;
1100         }
1101
1102         s->control_register &= ~HDSP_LatencyMask;
1103         s->control_register |= hdsp_encode_latency(n);
1104
1105         hdsp_write(s, HDSP_controlRegister, s->control_register);
1106
1107         hdsp_compute_period_size(s);
1108
1109         spin_unlock_irq(&s->lock);
1110
1111         return 0;
1112 }
1113
1114 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1115 {
1116         u64 n;
1117
1118         if (rate >= 112000)
1119                 rate /= 4;
1120         else if (rate >= 56000)
1121                 rate /= 2;
1122
1123         n = DDS_NUMERATOR;
1124         n = div_u64(n, rate);
1125         /* n should be less than 2^32 for being written to FREQ register */
1126         snd_BUG_ON(n >> 32);
1127         /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1128            value to write it after a reset */
1129         hdsp->dds_value = n;
1130         hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1131 }
1132
1133 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1134 {
1135         int reject_if_open = 0;
1136         int current_rate;
1137         int rate_bits;
1138
1139         /* ASSUMPTION: hdsp->lock is either held, or
1140            there is no need for it (e.g. during module
1141            initialization).
1142         */
1143
1144         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1145                 if (called_internally) {
1146                         /* request from ctl or card initialization */
1147                         dev_err(hdsp->card->dev,
1148                                 "device is not running as a clock master: cannot set sample rate.\n");
1149                         return -1;
1150                 } else {
1151                         /* hw_param request while in AutoSync mode */
1152                         int external_freq = hdsp_external_sample_rate(hdsp);
1153                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1154
1155                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1156                                 dev_info(hdsp->card->dev,
1157                                          "Detected ADAT in double speed mode\n");
1158                         else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1159                                 dev_info(hdsp->card->dev,
1160                                          "Detected ADAT in quad speed mode\n");
1161                         else if (rate != external_freq) {
1162                                 dev_info(hdsp->card->dev,
1163                                          "No AutoSync source for requested rate\n");
1164                                 return -1;
1165                         }
1166                 }
1167         }
1168
1169         current_rate = hdsp->system_sample_rate;
1170
1171         /* Changing from a "single speed" to a "double speed" rate is
1172            not allowed if any substreams are open. This is because
1173            such a change causes a shift in the location of
1174            the DMA buffers and a reduction in the number of available
1175            buffers.
1176
1177            Note that a similar but essentially insoluble problem
1178            exists for externally-driven rate changes. All we can do
1179            is to flag rate changes in the read/write routines.  */
1180
1181         if (rate > 96000 && hdsp->io_type != H9632)
1182                 return -EINVAL;
1183
1184         switch (rate) {
1185         case 32000:
1186                 if (current_rate > 48000)
1187                         reject_if_open = 1;
1188                 rate_bits = HDSP_Frequency32KHz;
1189                 break;
1190         case 44100:
1191                 if (current_rate > 48000)
1192                         reject_if_open = 1;
1193                 rate_bits = HDSP_Frequency44_1KHz;
1194                 break;
1195         case 48000:
1196                 if (current_rate > 48000)
1197                         reject_if_open = 1;
1198                 rate_bits = HDSP_Frequency48KHz;
1199                 break;
1200         case 64000:
1201                 if (current_rate <= 48000 || current_rate > 96000)
1202                         reject_if_open = 1;
1203                 rate_bits = HDSP_Frequency64KHz;
1204                 break;
1205         case 88200:
1206                 if (current_rate <= 48000 || current_rate > 96000)
1207                         reject_if_open = 1;
1208                 rate_bits = HDSP_Frequency88_2KHz;
1209                 break;
1210         case 96000:
1211                 if (current_rate <= 48000 || current_rate > 96000)
1212                         reject_if_open = 1;
1213                 rate_bits = HDSP_Frequency96KHz;
1214                 break;
1215         case 128000:
1216                 if (current_rate < 128000)
1217                         reject_if_open = 1;
1218                 rate_bits = HDSP_Frequency128KHz;
1219                 break;
1220         case 176400:
1221                 if (current_rate < 128000)
1222                         reject_if_open = 1;
1223                 rate_bits = HDSP_Frequency176_4KHz;
1224                 break;
1225         case 192000:
1226                 if (current_rate < 128000)
1227                         reject_if_open = 1;
1228                 rate_bits = HDSP_Frequency192KHz;
1229                 break;
1230         default:
1231                 return -EINVAL;
1232         }
1233
1234         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1235                 dev_warn(hdsp->card->dev,
1236                          "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1237                             hdsp->capture_pid,
1238                             hdsp->playback_pid);
1239                 return -EBUSY;
1240         }
1241
1242         hdsp->control_register &= ~HDSP_FrequencyMask;
1243         hdsp->control_register |= rate_bits;
1244         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1245
1246         /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1247         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1248                 hdsp_set_dds_value(hdsp, rate);
1249
1250         if (rate >= 128000) {
1251                 hdsp->channel_map = channel_map_H9632_qs;
1252         } else if (rate > 48000) {
1253                 if (hdsp->io_type == H9632)
1254                         hdsp->channel_map = channel_map_H9632_ds;
1255                 else
1256                         hdsp->channel_map = channel_map_ds;
1257         } else {
1258                 switch (hdsp->io_type) {
1259                 case RPM:
1260                 case Multiface:
1261                         hdsp->channel_map = channel_map_mf_ss;
1262                         break;
1263                 case Digiface:
1264                 case H9652:
1265                         hdsp->channel_map = channel_map_df_ss;
1266                         break;
1267                 case H9632:
1268                         hdsp->channel_map = channel_map_H9632_ss;
1269                         break;
1270                 default:
1271                         /* should never happen */
1272                         break;
1273                 }
1274         }
1275
1276         hdsp->system_sample_rate = rate;
1277
1278         return 0;
1279 }
1280
1281 /*----------------------------------------------------------------------------
1282    MIDI
1283   ----------------------------------------------------------------------------*/
1284
1285 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1286 {
1287         /* the hardware already does the relevant bit-mask with 0xff */
1288         if (id)
1289                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1290         else
1291                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1292 }
1293
1294 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1295 {
1296         /* the hardware already does the relevant bit-mask with 0xff */
1297         if (id)
1298                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1299         else
1300                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1301 }
1302
1303 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1304 {
1305         if (id)
1306                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1307         else
1308                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1309 }
1310
1311 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1312 {
1313         int fifo_bytes_used;
1314
1315         if (id)
1316                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1317         else
1318                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1319
1320         if (fifo_bytes_used < 128)
1321                 return  128 - fifo_bytes_used;
1322         else
1323                 return 0;
1324 }
1325
1326 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1327 {
1328         while (snd_hdsp_midi_input_available (hdsp, id))
1329                 snd_hdsp_midi_read_byte (hdsp, id);
1330 }
1331
1332 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1333 {
1334         unsigned long flags;
1335         int n_pending;
1336         int to_write;
1337         int i;
1338         unsigned char buf[128];
1339
1340         /* Output is not interrupt driven */
1341
1342         spin_lock_irqsave (&hmidi->lock, flags);
1343         if (hmidi->output) {
1344                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1345                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1346                                 if (n_pending > (int)sizeof (buf))
1347                                         n_pending = sizeof (buf);
1348
1349                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1350                                         for (i = 0; i < to_write; ++i)
1351                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1352                                 }
1353                         }
1354                 }
1355         }
1356         spin_unlock_irqrestore (&hmidi->lock, flags);
1357         return 0;
1358 }
1359
1360 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1361 {
1362         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1363         unsigned long flags;
1364         int n_pending;
1365         int i;
1366
1367         spin_lock_irqsave (&hmidi->lock, flags);
1368         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1369                 if (hmidi->input) {
1370                         if (n_pending > (int)sizeof (buf))
1371                                 n_pending = sizeof (buf);
1372                         for (i = 0; i < n_pending; ++i)
1373                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1374                         if (n_pending)
1375                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1376                 } else {
1377                         /* flush the MIDI input FIFO */
1378                         while (--n_pending)
1379                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1380                 }
1381         }
1382         hmidi->pending = 0;
1383         if (hmidi->id)
1384                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1385         else
1386                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1387         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1388         spin_unlock_irqrestore (&hmidi->lock, flags);
1389         return snd_hdsp_midi_output_write (hmidi);
1390 }
1391
1392 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1393 {
1394         struct hdsp *hdsp;
1395         struct hdsp_midi *hmidi;
1396         unsigned long flags;
1397         u32 ie;
1398
1399         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1400         hdsp = hmidi->hdsp;
1401         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1402         spin_lock_irqsave (&hdsp->lock, flags);
1403         if (up) {
1404                 if (!(hdsp->control_register & ie)) {
1405                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1406                         hdsp->control_register |= ie;
1407                 }
1408         } else {
1409                 hdsp->control_register &= ~ie;
1410                 tasklet_kill(&hdsp->midi_tasklet);
1411         }
1412
1413         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1414         spin_unlock_irqrestore (&hdsp->lock, flags);
1415 }
1416
1417 static void snd_hdsp_midi_output_timer(unsigned long data)
1418 {
1419         struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
1420         unsigned long flags;
1421
1422         snd_hdsp_midi_output_write(hmidi);
1423         spin_lock_irqsave (&hmidi->lock, flags);
1424
1425         /* this does not bump hmidi->istimer, because the
1426            kernel automatically removed the timer when it
1427            expired, and we are now adding it back, thus
1428            leaving istimer wherever it was set before.
1429         */
1430
1431         if (hmidi->istimer)
1432                 mod_timer(&hmidi->timer, 1 + jiffies);
1433
1434         spin_unlock_irqrestore (&hmidi->lock, flags);
1435 }
1436
1437 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1438 {
1439         struct hdsp_midi *hmidi;
1440         unsigned long flags;
1441
1442         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1443         spin_lock_irqsave (&hmidi->lock, flags);
1444         if (up) {
1445                 if (!hmidi->istimer) {
1446                         setup_timer(&hmidi->timer, snd_hdsp_midi_output_timer,
1447                                     (unsigned long) hmidi);
1448                         mod_timer(&hmidi->timer, 1 + jiffies);
1449                         hmidi->istimer++;
1450                 }
1451         } else {
1452                 if (hmidi->istimer && --hmidi->istimer <= 0)
1453                         del_timer (&hmidi->timer);
1454         }
1455         spin_unlock_irqrestore (&hmidi->lock, flags);
1456         if (up)
1457                 snd_hdsp_midi_output_write(hmidi);
1458 }
1459
1460 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1461 {
1462         struct hdsp_midi *hmidi;
1463
1464         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1465         spin_lock_irq (&hmidi->lock);
1466         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1467         hmidi->input = substream;
1468         spin_unlock_irq (&hmidi->lock);
1469
1470         return 0;
1471 }
1472
1473 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1474 {
1475         struct hdsp_midi *hmidi;
1476
1477         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1478         spin_lock_irq (&hmidi->lock);
1479         hmidi->output = substream;
1480         spin_unlock_irq (&hmidi->lock);
1481
1482         return 0;
1483 }
1484
1485 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1486 {
1487         struct hdsp_midi *hmidi;
1488
1489         snd_hdsp_midi_input_trigger (substream, 0);
1490
1491         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1492         spin_lock_irq (&hmidi->lock);
1493         hmidi->input = NULL;
1494         spin_unlock_irq (&hmidi->lock);
1495
1496         return 0;
1497 }
1498
1499 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1500 {
1501         struct hdsp_midi *hmidi;
1502
1503         snd_hdsp_midi_output_trigger (substream, 0);
1504
1505         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1506         spin_lock_irq (&hmidi->lock);
1507         hmidi->output = NULL;
1508         spin_unlock_irq (&hmidi->lock);
1509
1510         return 0;
1511 }
1512
1513 static struct snd_rawmidi_ops snd_hdsp_midi_output =
1514 {
1515         .open =         snd_hdsp_midi_output_open,
1516         .close =        snd_hdsp_midi_output_close,
1517         .trigger =      snd_hdsp_midi_output_trigger,
1518 };
1519
1520 static struct snd_rawmidi_ops snd_hdsp_midi_input =
1521 {
1522         .open =         snd_hdsp_midi_input_open,
1523         .close =        snd_hdsp_midi_input_close,
1524         .trigger =      snd_hdsp_midi_input_trigger,
1525 };
1526
1527 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1528 {
1529         char buf[32];
1530
1531         hdsp->midi[id].id = id;
1532         hdsp->midi[id].rmidi = NULL;
1533         hdsp->midi[id].input = NULL;
1534         hdsp->midi[id].output = NULL;
1535         hdsp->midi[id].hdsp = hdsp;
1536         hdsp->midi[id].istimer = 0;
1537         hdsp->midi[id].pending = 0;
1538         spin_lock_init (&hdsp->midi[id].lock);
1539
1540         sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1541         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1542                 return -1;
1543
1544         sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1545         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1546
1547         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1548         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1549
1550         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1551                 SNDRV_RAWMIDI_INFO_INPUT |
1552                 SNDRV_RAWMIDI_INFO_DUPLEX;
1553
1554         return 0;
1555 }
1556
1557 /*-----------------------------------------------------------------------------
1558   Control Interface
1559   ----------------------------------------------------------------------------*/
1560
1561 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1562 {
1563         u32 val = 0;
1564         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1565         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1566         if (val & HDSP_SPDIFProfessional)
1567                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1568         else
1569                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1570         return val;
1571 }
1572
1573 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1574 {
1575         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1576                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1577         if (val & HDSP_SPDIFProfessional)
1578                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1579         else
1580                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1581 }
1582
1583 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1584 {
1585         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1586         uinfo->count = 1;
1587         return 0;
1588 }
1589
1590 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1591 {
1592         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1593
1594         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1595         return 0;
1596 }
1597
1598 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1599 {
1600         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1601         int change;
1602         u32 val;
1603
1604         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1605         spin_lock_irq(&hdsp->lock);
1606         change = val != hdsp->creg_spdif;
1607         hdsp->creg_spdif = val;
1608         spin_unlock_irq(&hdsp->lock);
1609         return change;
1610 }
1611
1612 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1613 {
1614         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1615         uinfo->count = 1;
1616         return 0;
1617 }
1618
1619 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1620 {
1621         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1622
1623         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1624         return 0;
1625 }
1626
1627 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1628 {
1629         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1630         int change;
1631         u32 val;
1632
1633         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1634         spin_lock_irq(&hdsp->lock);
1635         change = val != hdsp->creg_spdif_stream;
1636         hdsp->creg_spdif_stream = val;
1637         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1638         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1639         spin_unlock_irq(&hdsp->lock);
1640         return change;
1641 }
1642
1643 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1644 {
1645         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1646         uinfo->count = 1;
1647         return 0;
1648 }
1649
1650 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1651 {
1652         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1653         return 0;
1654 }
1655
1656 #define HDSP_SPDIF_IN(xname, xindex) \
1657 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1658   .name = xname, \
1659   .index = xindex, \
1660   .info = snd_hdsp_info_spdif_in, \
1661   .get = snd_hdsp_get_spdif_in, \
1662   .put = snd_hdsp_put_spdif_in }
1663
1664 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1665 {
1666         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1667 }
1668
1669 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1670 {
1671         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1672         hdsp->control_register |= hdsp_encode_spdif_in(in);
1673         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1674         return 0;
1675 }
1676
1677 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1678 {
1679         static const char * const texts[4] = {
1680                 "Optical", "Coaxial", "Internal", "AES"
1681         };
1682         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1683
1684         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1685                                  texts);
1686 }
1687
1688 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1689 {
1690         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1691
1692         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1693         return 0;
1694 }
1695
1696 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1697 {
1698         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1699         int change;
1700         unsigned int val;
1701
1702         if (!snd_hdsp_use_is_exclusive(hdsp))
1703                 return -EBUSY;
1704         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1705         spin_lock_irq(&hdsp->lock);
1706         change = val != hdsp_spdif_in(hdsp);
1707         if (change)
1708                 hdsp_set_spdif_input(hdsp, val);
1709         spin_unlock_irq(&hdsp->lock);
1710         return change;
1711 }
1712
1713 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1714 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1715         .name = xname, \
1716         .private_value = xindex, \
1717         .info = snd_hdsp_info_toggle_setting, \
1718         .get = snd_hdsp_get_toggle_setting, \
1719         .put = snd_hdsp_put_toggle_setting \
1720 }
1721
1722 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1723 {
1724         return (hdsp->control_register & regmask) ? 1 : 0;
1725 }
1726
1727 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1728 {
1729         if (out)
1730                 hdsp->control_register |= regmask;
1731         else
1732                 hdsp->control_register &= ~regmask;
1733         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1734
1735         return 0;
1736 }
1737
1738 #define snd_hdsp_info_toggle_setting               snd_ctl_boolean_mono_info
1739
1740 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1741                 struct snd_ctl_elem_value *ucontrol)
1742 {
1743         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1744         u32 regmask = kcontrol->private_value;
1745
1746         spin_lock_irq(&hdsp->lock);
1747         ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1748         spin_unlock_irq(&hdsp->lock);
1749         return 0;
1750 }
1751
1752 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1753                 struct snd_ctl_elem_value *ucontrol)
1754 {
1755         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1756         u32 regmask = kcontrol->private_value;
1757         int change;
1758         unsigned int val;
1759
1760         if (!snd_hdsp_use_is_exclusive(hdsp))
1761                 return -EBUSY;
1762         val = ucontrol->value.integer.value[0] & 1;
1763         spin_lock_irq(&hdsp->lock);
1764         change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1765         if (change)
1766                 hdsp_set_toggle_setting(hdsp, regmask, val);
1767         spin_unlock_irq(&hdsp->lock);
1768         return change;
1769 }
1770
1771 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1772 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1773   .name = xname, \
1774   .index = xindex, \
1775   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1776   .info = snd_hdsp_info_spdif_sample_rate, \
1777   .get = snd_hdsp_get_spdif_sample_rate \
1778 }
1779
1780 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1781 {
1782         static const char * const texts[] = {
1783                 "32000", "44100", "48000", "64000", "88200", "96000",
1784                 "None", "128000", "176400", "192000"
1785         };
1786         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1787
1788         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1789                                  texts);
1790 }
1791
1792 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1793 {
1794         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1795
1796         switch (hdsp_spdif_sample_rate(hdsp)) {
1797         case 32000:
1798                 ucontrol->value.enumerated.item[0] = 0;
1799                 break;
1800         case 44100:
1801                 ucontrol->value.enumerated.item[0] = 1;
1802                 break;
1803         case 48000:
1804                 ucontrol->value.enumerated.item[0] = 2;
1805                 break;
1806         case 64000:
1807                 ucontrol->value.enumerated.item[0] = 3;
1808                 break;
1809         case 88200:
1810                 ucontrol->value.enumerated.item[0] = 4;
1811                 break;
1812         case 96000:
1813                 ucontrol->value.enumerated.item[0] = 5;
1814                 break;
1815         case 128000:
1816                 ucontrol->value.enumerated.item[0] = 7;
1817                 break;
1818         case 176400:
1819                 ucontrol->value.enumerated.item[0] = 8;
1820                 break;
1821         case 192000:
1822                 ucontrol->value.enumerated.item[0] = 9;
1823                 break;
1824         default:
1825                 ucontrol->value.enumerated.item[0] = 6;
1826         }
1827         return 0;
1828 }
1829
1830 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1831 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1832   .name = xname, \
1833   .index = xindex, \
1834   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1835   .info = snd_hdsp_info_system_sample_rate, \
1836   .get = snd_hdsp_get_system_sample_rate \
1837 }
1838
1839 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1840 {
1841         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1842         uinfo->count = 1;
1843         return 0;
1844 }
1845
1846 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1847 {
1848         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1849
1850         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1851         return 0;
1852 }
1853
1854 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1855 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1856   .name = xname, \
1857   .index = xindex, \
1858   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1859   .info = snd_hdsp_info_autosync_sample_rate, \
1860   .get = snd_hdsp_get_autosync_sample_rate \
1861 }
1862
1863 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1864 {
1865         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1866         static const char * const texts[] = {
1867                 "32000", "44100", "48000", "64000", "88200", "96000",
1868                 "None", "128000", "176400", "192000"
1869         };
1870
1871         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1872                                  texts);
1873 }
1874
1875 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1876 {
1877         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1878
1879         switch (hdsp_external_sample_rate(hdsp)) {
1880         case 32000:
1881                 ucontrol->value.enumerated.item[0] = 0;
1882                 break;
1883         case 44100:
1884                 ucontrol->value.enumerated.item[0] = 1;
1885                 break;
1886         case 48000:
1887                 ucontrol->value.enumerated.item[0] = 2;
1888                 break;
1889         case 64000:
1890                 ucontrol->value.enumerated.item[0] = 3;
1891                 break;
1892         case 88200:
1893                 ucontrol->value.enumerated.item[0] = 4;
1894                 break;
1895         case 96000:
1896                 ucontrol->value.enumerated.item[0] = 5;
1897                 break;
1898         case 128000:
1899                 ucontrol->value.enumerated.item[0] = 7;
1900                 break;
1901         case 176400:
1902                 ucontrol->value.enumerated.item[0] = 8;
1903                 break;
1904         case 192000:
1905                 ucontrol->value.enumerated.item[0] = 9;
1906                 break;
1907         default:
1908                 ucontrol->value.enumerated.item[0] = 6;
1909         }
1910         return 0;
1911 }
1912
1913 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1914 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1915   .name = xname, \
1916   .index = xindex, \
1917   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1918   .info = snd_hdsp_info_system_clock_mode, \
1919   .get = snd_hdsp_get_system_clock_mode \
1920 }
1921
1922 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1923 {
1924         if (hdsp->control_register & HDSP_ClockModeMaster)
1925                 return 0;
1926         else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1927                         return 0;
1928         return 1;
1929 }
1930
1931 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1932 {
1933         static const char * const texts[] = {"Master", "Slave" };
1934
1935         return snd_ctl_enum_info(uinfo, 1, 2, texts);
1936 }
1937
1938 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1939 {
1940         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1941
1942         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1943         return 0;
1944 }
1945
1946 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1947 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1948   .name = xname, \
1949   .index = xindex, \
1950   .info = snd_hdsp_info_clock_source, \
1951   .get = snd_hdsp_get_clock_source, \
1952   .put = snd_hdsp_put_clock_source \
1953 }
1954
1955 static int hdsp_clock_source(struct hdsp *hdsp)
1956 {
1957         if (hdsp->control_register & HDSP_ClockModeMaster) {
1958                 switch (hdsp->system_sample_rate) {
1959                 case 32000:
1960                         return 1;
1961                 case 44100:
1962                         return 2;
1963                 case 48000:
1964                         return 3;
1965                 case 64000:
1966                         return 4;
1967                 case 88200:
1968                         return 5;
1969                 case 96000:
1970                         return 6;
1971                 case 128000:
1972                         return 7;
1973                 case 176400:
1974                         return 8;
1975                 case 192000:
1976                         return 9;
1977                 default:
1978                         return 3;
1979                 }
1980         } else {
1981                 return 0;
1982         }
1983 }
1984
1985 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1986 {
1987         int rate;
1988         switch (mode) {
1989         case HDSP_CLOCK_SOURCE_AUTOSYNC:
1990                 if (hdsp_external_sample_rate(hdsp) != 0) {
1991                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1992                         hdsp->control_register &= ~HDSP_ClockModeMaster;
1993                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1994                         return 0;
1995                     }
1996                 }
1997                 return -1;
1998         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1999                 rate = 32000;
2000                 break;
2001         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2002                 rate = 44100;
2003                 break;
2004         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2005                 rate = 48000;
2006                 break;
2007         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2008                 rate = 64000;
2009                 break;
2010         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2011                 rate = 88200;
2012                 break;
2013         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2014                 rate = 96000;
2015                 break;
2016         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2017                 rate = 128000;
2018                 break;
2019         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2020                 rate = 176400;
2021                 break;
2022         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2023                 rate = 192000;
2024                 break;
2025         default:
2026                 rate = 48000;
2027         }
2028         hdsp->control_register |= HDSP_ClockModeMaster;
2029         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2030         hdsp_set_rate(hdsp, rate, 1);
2031         return 0;
2032 }
2033
2034 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2035 {
2036         static const char * const texts[] = {
2037                 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2038                 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2039                 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2040                 "Internal 192.0 KHz"
2041         };
2042         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2043
2044         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2045                                  texts);
2046 }
2047
2048 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2049 {
2050         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2051
2052         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2053         return 0;
2054 }
2055
2056 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2057 {
2058         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2059         int change;
2060         int val;
2061
2062         if (!snd_hdsp_use_is_exclusive(hdsp))
2063                 return -EBUSY;
2064         val = ucontrol->value.enumerated.item[0];
2065         if (val < 0) val = 0;
2066         if (hdsp->io_type == H9632) {
2067                 if (val > 9)
2068                         val = 9;
2069         } else {
2070                 if (val > 6)
2071                         val = 6;
2072         }
2073         spin_lock_irq(&hdsp->lock);
2074         if (val != hdsp_clock_source(hdsp))
2075                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2076         else
2077                 change = 0;
2078         spin_unlock_irq(&hdsp->lock);
2079         return change;
2080 }
2081
2082 #define snd_hdsp_info_clock_source_lock         snd_ctl_boolean_mono_info
2083
2084 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2085 {
2086         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2087
2088         ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2089         return 0;
2090 }
2091
2092 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2093 {
2094         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2095         int change;
2096
2097         change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2098         if (change)
2099                 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2100         return change;
2101 }
2102
2103 #define HDSP_DA_GAIN(xname, xindex) \
2104 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2105   .name = xname, \
2106   .index = xindex, \
2107   .info = snd_hdsp_info_da_gain, \
2108   .get = snd_hdsp_get_da_gain, \
2109   .put = snd_hdsp_put_da_gain \
2110 }
2111
2112 static int hdsp_da_gain(struct hdsp *hdsp)
2113 {
2114         switch (hdsp->control_register & HDSP_DAGainMask) {
2115         case HDSP_DAGainHighGain:
2116                 return 0;
2117         case HDSP_DAGainPlus4dBu:
2118                 return 1;
2119         case HDSP_DAGainMinus10dBV:
2120                 return 2;
2121         default:
2122                 return 1;
2123         }
2124 }
2125
2126 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2127 {
2128         hdsp->control_register &= ~HDSP_DAGainMask;
2129         switch (mode) {
2130         case 0:
2131                 hdsp->control_register |= HDSP_DAGainHighGain;
2132                 break;
2133         case 1:
2134                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2135                 break;
2136         case 2:
2137                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2138                 break;
2139         default:
2140                 return -1;
2141
2142         }
2143         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2144         return 0;
2145 }
2146
2147 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2148 {
2149         static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2150
2151         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2152 }
2153
2154 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2155 {
2156         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2157
2158         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2159         return 0;
2160 }
2161
2162 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2163 {
2164         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2165         int change;
2166         int val;
2167
2168         if (!snd_hdsp_use_is_exclusive(hdsp))
2169                 return -EBUSY;
2170         val = ucontrol->value.enumerated.item[0];
2171         if (val < 0) val = 0;
2172         if (val > 2) val = 2;
2173         spin_lock_irq(&hdsp->lock);
2174         if (val != hdsp_da_gain(hdsp))
2175                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2176         else
2177                 change = 0;
2178         spin_unlock_irq(&hdsp->lock);
2179         return change;
2180 }
2181
2182 #define HDSP_AD_GAIN(xname, xindex) \
2183 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2184   .name = xname, \
2185   .index = xindex, \
2186   .info = snd_hdsp_info_ad_gain, \
2187   .get = snd_hdsp_get_ad_gain, \
2188   .put = snd_hdsp_put_ad_gain \
2189 }
2190
2191 static int hdsp_ad_gain(struct hdsp *hdsp)
2192 {
2193         switch (hdsp->control_register & HDSP_ADGainMask) {
2194         case HDSP_ADGainMinus10dBV:
2195                 return 0;
2196         case HDSP_ADGainPlus4dBu:
2197                 return 1;
2198         case HDSP_ADGainLowGain:
2199                 return 2;
2200         default:
2201                 return 1;
2202         }
2203 }
2204
2205 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2206 {
2207         hdsp->control_register &= ~HDSP_ADGainMask;
2208         switch (mode) {
2209         case 0:
2210                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2211                 break;
2212         case 1:
2213                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2214                 break;
2215         case 2:
2216                 hdsp->control_register |= HDSP_ADGainLowGain;
2217                 break;
2218         default:
2219                 return -1;
2220
2221         }
2222         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2223         return 0;
2224 }
2225
2226 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2227 {
2228         static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2229
2230         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2231 }
2232
2233 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2234 {
2235         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2236
2237         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2238         return 0;
2239 }
2240
2241 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2242 {
2243         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2244         int change;
2245         int val;
2246
2247         if (!snd_hdsp_use_is_exclusive(hdsp))
2248                 return -EBUSY;
2249         val = ucontrol->value.enumerated.item[0];
2250         if (val < 0) val = 0;
2251         if (val > 2) val = 2;
2252         spin_lock_irq(&hdsp->lock);
2253         if (val != hdsp_ad_gain(hdsp))
2254                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2255         else
2256                 change = 0;
2257         spin_unlock_irq(&hdsp->lock);
2258         return change;
2259 }
2260
2261 #define HDSP_PHONE_GAIN(xname, xindex) \
2262 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2263   .name = xname, \
2264   .index = xindex, \
2265   .info = snd_hdsp_info_phone_gain, \
2266   .get = snd_hdsp_get_phone_gain, \
2267   .put = snd_hdsp_put_phone_gain \
2268 }
2269
2270 static int hdsp_phone_gain(struct hdsp *hdsp)
2271 {
2272         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2273         case HDSP_PhoneGain0dB:
2274                 return 0;
2275         case HDSP_PhoneGainMinus6dB:
2276                 return 1;
2277         case HDSP_PhoneGainMinus12dB:
2278                 return 2;
2279         default:
2280                 return 0;
2281         }
2282 }
2283
2284 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2285 {
2286         hdsp->control_register &= ~HDSP_PhoneGainMask;
2287         switch (mode) {
2288         case 0:
2289                 hdsp->control_register |= HDSP_PhoneGain0dB;
2290                 break;
2291         case 1:
2292                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2293                 break;
2294         case 2:
2295                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2296                 break;
2297         default:
2298                 return -1;
2299
2300         }
2301         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2302         return 0;
2303 }
2304
2305 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2306 {
2307         static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2308
2309         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2310 }
2311
2312 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2313 {
2314         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2315
2316         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2317         return 0;
2318 }
2319
2320 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2321 {
2322         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2323         int change;
2324         int val;
2325
2326         if (!snd_hdsp_use_is_exclusive(hdsp))
2327                 return -EBUSY;
2328         val = ucontrol->value.enumerated.item[0];
2329         if (val < 0) val = 0;
2330         if (val > 2) val = 2;
2331         spin_lock_irq(&hdsp->lock);
2332         if (val != hdsp_phone_gain(hdsp))
2333                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2334         else
2335                 change = 0;
2336         spin_unlock_irq(&hdsp->lock);
2337         return change;
2338 }
2339
2340 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2341 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2342   .name = xname, \
2343   .index = xindex, \
2344   .info = snd_hdsp_info_pref_sync_ref, \
2345   .get = snd_hdsp_get_pref_sync_ref, \
2346   .put = snd_hdsp_put_pref_sync_ref \
2347 }
2348
2349 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2350 {
2351         /* Notice that this looks at the requested sync source,
2352            not the one actually in use.
2353         */
2354
2355         switch (hdsp->control_register & HDSP_SyncRefMask) {
2356         case HDSP_SyncRef_ADAT1:
2357                 return HDSP_SYNC_FROM_ADAT1;
2358         case HDSP_SyncRef_ADAT2:
2359                 return HDSP_SYNC_FROM_ADAT2;
2360         case HDSP_SyncRef_ADAT3:
2361                 return HDSP_SYNC_FROM_ADAT3;
2362         case HDSP_SyncRef_SPDIF:
2363                 return HDSP_SYNC_FROM_SPDIF;
2364         case HDSP_SyncRef_WORD:
2365                 return HDSP_SYNC_FROM_WORD;
2366         case HDSP_SyncRef_ADAT_SYNC:
2367                 return HDSP_SYNC_FROM_ADAT_SYNC;
2368         default:
2369                 return HDSP_SYNC_FROM_WORD;
2370         }
2371         return 0;
2372 }
2373
2374 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2375 {
2376         hdsp->control_register &= ~HDSP_SyncRefMask;
2377         switch (pref) {
2378         case HDSP_SYNC_FROM_ADAT1:
2379                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2380                 break;
2381         case HDSP_SYNC_FROM_ADAT2:
2382                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2383                 break;
2384         case HDSP_SYNC_FROM_ADAT3:
2385                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2386                 break;
2387         case HDSP_SYNC_FROM_SPDIF:
2388                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2389                 break;
2390         case HDSP_SYNC_FROM_WORD:
2391                 hdsp->control_register |= HDSP_SyncRef_WORD;
2392                 break;
2393         case HDSP_SYNC_FROM_ADAT_SYNC:
2394                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2395                 break;
2396         default:
2397                 return -1;
2398         }
2399         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2400         return 0;
2401 }
2402
2403 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2404 {
2405         static const char * const texts[] = {
2406                 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2407         };
2408         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2409         int num_items;
2410
2411         switch (hdsp->io_type) {
2412         case Digiface:
2413         case H9652:
2414                 num_items = 6;
2415                 break;
2416         case Multiface:
2417                 num_items = 4;
2418                 break;
2419         case H9632:
2420                 num_items = 3;
2421                 break;
2422         default:
2423                 return -EINVAL;
2424         }
2425
2426         return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2427 }
2428
2429 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2430 {
2431         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2432
2433         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2434         return 0;
2435 }
2436
2437 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2438 {
2439         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2440         int change, max;
2441         unsigned int val;
2442
2443         if (!snd_hdsp_use_is_exclusive(hdsp))
2444                 return -EBUSY;
2445
2446         switch (hdsp->io_type) {
2447         case Digiface:
2448         case H9652:
2449                 max = 6;
2450                 break;
2451         case Multiface:
2452                 max = 4;
2453                 break;
2454         case H9632:
2455                 max = 3;
2456                 break;
2457         default:
2458                 return -EIO;
2459         }
2460
2461         val = ucontrol->value.enumerated.item[0] % max;
2462         spin_lock_irq(&hdsp->lock);
2463         change = (int)val != hdsp_pref_sync_ref(hdsp);
2464         hdsp_set_pref_sync_ref(hdsp, val);
2465         spin_unlock_irq(&hdsp->lock);
2466         return change;
2467 }
2468
2469 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2470 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2471   .name = xname, \
2472   .index = xindex, \
2473   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2474   .info = snd_hdsp_info_autosync_ref, \
2475   .get = snd_hdsp_get_autosync_ref, \
2476 }
2477
2478 static int hdsp_autosync_ref(struct hdsp *hdsp)
2479 {
2480         /* This looks at the autosync selected sync reference */
2481         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2482
2483         switch (status2 & HDSP_SelSyncRefMask) {
2484         case HDSP_SelSyncRef_WORD:
2485                 return HDSP_AUTOSYNC_FROM_WORD;
2486         case HDSP_SelSyncRef_ADAT_SYNC:
2487                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2488         case HDSP_SelSyncRef_SPDIF:
2489                 return HDSP_AUTOSYNC_FROM_SPDIF;
2490         case HDSP_SelSyncRefMask:
2491                 return HDSP_AUTOSYNC_FROM_NONE;
2492         case HDSP_SelSyncRef_ADAT1:
2493                 return HDSP_AUTOSYNC_FROM_ADAT1;
2494         case HDSP_SelSyncRef_ADAT2:
2495                 return HDSP_AUTOSYNC_FROM_ADAT2;
2496         case HDSP_SelSyncRef_ADAT3:
2497                 return HDSP_AUTOSYNC_FROM_ADAT3;
2498         default:
2499                 return HDSP_AUTOSYNC_FROM_WORD;
2500         }
2501         return 0;
2502 }
2503
2504 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2505 {
2506         static const char * const texts[] = {
2507                 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2508         };
2509
2510         return snd_ctl_enum_info(uinfo, 1, 7, texts);
2511 }
2512
2513 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2514 {
2515         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2516
2517         ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2518         return 0;
2519 }
2520
2521 #define HDSP_PRECISE_POINTER(xname, xindex) \
2522 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2523   .name = xname, \
2524   .index = xindex, \
2525   .info = snd_hdsp_info_precise_pointer, \
2526   .get = snd_hdsp_get_precise_pointer, \
2527   .put = snd_hdsp_put_precise_pointer \
2528 }
2529
2530 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2531 {
2532         if (precise)
2533                 hdsp->precise_ptr = 1;
2534         else
2535                 hdsp->precise_ptr = 0;
2536         return 0;
2537 }
2538
2539 #define snd_hdsp_info_precise_pointer           snd_ctl_boolean_mono_info
2540
2541 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2542 {
2543         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2544
2545         spin_lock_irq(&hdsp->lock);
2546         ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2547         spin_unlock_irq(&hdsp->lock);
2548         return 0;
2549 }
2550
2551 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2552 {
2553         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2554         int change;
2555         unsigned int val;
2556
2557         if (!snd_hdsp_use_is_exclusive(hdsp))
2558                 return -EBUSY;
2559         val = ucontrol->value.integer.value[0] & 1;
2560         spin_lock_irq(&hdsp->lock);
2561         change = (int)val != hdsp->precise_ptr;
2562         hdsp_set_precise_pointer(hdsp, val);
2563         spin_unlock_irq(&hdsp->lock);
2564         return change;
2565 }
2566
2567 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2568 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2569   .name = xname, \
2570   .index = xindex, \
2571   .info = snd_hdsp_info_use_midi_tasklet, \
2572   .get = snd_hdsp_get_use_midi_tasklet, \
2573   .put = snd_hdsp_put_use_midi_tasklet \
2574 }
2575
2576 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2577 {
2578         if (use_tasklet)
2579                 hdsp->use_midi_tasklet = 1;
2580         else
2581                 hdsp->use_midi_tasklet = 0;
2582         return 0;
2583 }
2584
2585 #define snd_hdsp_info_use_midi_tasklet          snd_ctl_boolean_mono_info
2586
2587 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2588 {
2589         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2590
2591         spin_lock_irq(&hdsp->lock);
2592         ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2593         spin_unlock_irq(&hdsp->lock);
2594         return 0;
2595 }
2596
2597 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2598 {
2599         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2600         int change;
2601         unsigned int val;
2602
2603         if (!snd_hdsp_use_is_exclusive(hdsp))
2604                 return -EBUSY;
2605         val = ucontrol->value.integer.value[0] & 1;
2606         spin_lock_irq(&hdsp->lock);
2607         change = (int)val != hdsp->use_midi_tasklet;
2608         hdsp_set_use_midi_tasklet(hdsp, val);
2609         spin_unlock_irq(&hdsp->lock);
2610         return change;
2611 }
2612
2613 #define HDSP_MIXER(xname, xindex) \
2614 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2615   .name = xname, \
2616   .index = xindex, \
2617   .device = 0, \
2618   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2619                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2620   .info = snd_hdsp_info_mixer, \
2621   .get = snd_hdsp_get_mixer, \
2622   .put = snd_hdsp_put_mixer \
2623 }
2624
2625 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2626 {
2627         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2628         uinfo->count = 3;
2629         uinfo->value.integer.min = 0;
2630         uinfo->value.integer.max = 65536;
2631         uinfo->value.integer.step = 1;
2632         return 0;
2633 }
2634
2635 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2636 {
2637         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2638         int source;
2639         int destination;
2640         int addr;
2641
2642         source = ucontrol->value.integer.value[0];
2643         destination = ucontrol->value.integer.value[1];
2644
2645         if (source >= hdsp->max_channels)
2646                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2647         else
2648                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2649
2650         spin_lock_irq(&hdsp->lock);
2651         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2652         spin_unlock_irq(&hdsp->lock);
2653         return 0;
2654 }
2655
2656 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2657 {
2658         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2659         int change;
2660         int source;
2661         int destination;
2662         int gain;
2663         int addr;
2664
2665         if (!snd_hdsp_use_is_exclusive(hdsp))
2666                 return -EBUSY;
2667
2668         source = ucontrol->value.integer.value[0];
2669         destination = ucontrol->value.integer.value[1];
2670
2671         if (source >= hdsp->max_channels)
2672                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2673         else
2674                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2675
2676         gain = ucontrol->value.integer.value[2];
2677
2678         spin_lock_irq(&hdsp->lock);
2679         change = gain != hdsp_read_gain(hdsp, addr);
2680         if (change)
2681                 hdsp_write_gain(hdsp, addr, gain);
2682         spin_unlock_irq(&hdsp->lock);
2683         return change;
2684 }
2685
2686 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2687 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2688   .name = xname, \
2689   .index = xindex, \
2690   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2691   .info = snd_hdsp_info_sync_check, \
2692   .get = snd_hdsp_get_wc_sync_check \
2693 }
2694
2695 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2696 {
2697         static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2698
2699         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2700 }
2701
2702 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2703 {
2704         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2705         if (status2 & HDSP_wc_lock) {
2706                 if (status2 & HDSP_wc_sync)
2707                         return 2;
2708                 else
2709                          return 1;
2710         } else
2711                 return 0;
2712         return 0;
2713 }
2714
2715 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2716 {
2717         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2718
2719         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2720         return 0;
2721 }
2722
2723 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2724 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2725   .name = xname, \
2726   .index = xindex, \
2727   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2728   .info = snd_hdsp_info_sync_check, \
2729   .get = snd_hdsp_get_spdif_sync_check \
2730 }
2731
2732 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2733 {
2734         int status = hdsp_read(hdsp, HDSP_statusRegister);
2735         if (status & HDSP_SPDIFErrorFlag)
2736                 return 0;
2737         else {
2738                 if (status & HDSP_SPDIFSync)
2739                         return 2;
2740                 else
2741                         return 1;
2742         }
2743         return 0;
2744 }
2745
2746 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2747 {
2748         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2749
2750         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2751         return 0;
2752 }
2753
2754 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2755 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2756   .name = xname, \
2757   .index = xindex, \
2758   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2759   .info = snd_hdsp_info_sync_check, \
2760   .get = snd_hdsp_get_adatsync_sync_check \
2761 }
2762
2763 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2764 {
2765         int status = hdsp_read(hdsp, HDSP_statusRegister);
2766         if (status & HDSP_TimecodeLock) {
2767                 if (status & HDSP_TimecodeSync)
2768                         return 2;
2769                 else
2770                         return 1;
2771         } else
2772                 return 0;
2773 }
2774
2775 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2776 {
2777         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2778
2779         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2780         return 0;
2781 }
2782
2783 #define HDSP_ADAT_SYNC_CHECK \
2784 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2785   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2786   .info = snd_hdsp_info_sync_check, \
2787   .get = snd_hdsp_get_adat_sync_check \
2788 }
2789
2790 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2791 {
2792         int status = hdsp_read(hdsp, HDSP_statusRegister);
2793
2794         if (status & (HDSP_Lock0>>idx)) {
2795                 if (status & (HDSP_Sync0>>idx))
2796                         return 2;
2797                 else
2798                         return 1;
2799         } else
2800                 return 0;
2801 }
2802
2803 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2804 {
2805         int offset;
2806         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2807
2808         offset = ucontrol->id.index - 1;
2809         snd_BUG_ON(offset < 0);
2810
2811         switch (hdsp->io_type) {
2812         case Digiface:
2813         case H9652:
2814                 if (offset >= 3)
2815                         return -EINVAL;
2816                 break;
2817         case Multiface:
2818         case H9632:
2819                 if (offset >= 1)
2820                         return -EINVAL;
2821                 break;
2822         default:
2823                 return -EIO;
2824         }
2825
2826         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2827         return 0;
2828 }
2829
2830 #define HDSP_DDS_OFFSET(xname, xindex) \
2831 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2832   .name = xname, \
2833   .index = xindex, \
2834   .info = snd_hdsp_info_dds_offset, \
2835   .get = snd_hdsp_get_dds_offset, \
2836   .put = snd_hdsp_put_dds_offset \
2837 }
2838
2839 static int hdsp_dds_offset(struct hdsp *hdsp)
2840 {
2841         u64 n;
2842         unsigned int dds_value = hdsp->dds_value;
2843         int system_sample_rate = hdsp->system_sample_rate;
2844
2845         if (!dds_value)
2846                 return 0;
2847
2848         n = DDS_NUMERATOR;
2849         /*
2850          * dds_value = n / rate
2851          * rate = n / dds_value
2852          */
2853         n = div_u64(n, dds_value);
2854         if (system_sample_rate >= 112000)
2855                 n *= 4;
2856         else if (system_sample_rate >= 56000)
2857                 n *= 2;
2858         return ((int)n) - system_sample_rate;
2859 }
2860
2861 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2862 {
2863         int rate = hdsp->system_sample_rate + offset_hz;
2864         hdsp_set_dds_value(hdsp, rate);
2865         return 0;
2866 }
2867
2868 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2869 {
2870         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2871         uinfo->count = 1;
2872         uinfo->value.integer.min = -5000;
2873         uinfo->value.integer.max = 5000;
2874         return 0;
2875 }
2876
2877 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2878 {
2879         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2880
2881         ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp);
2882         return 0;
2883 }
2884
2885 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2886 {
2887         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2888         int change;
2889         int val;
2890
2891         if (!snd_hdsp_use_is_exclusive(hdsp))
2892                 return -EBUSY;
2893         val = ucontrol->value.enumerated.item[0];
2894         spin_lock_irq(&hdsp->lock);
2895         if (val != hdsp_dds_offset(hdsp))
2896                 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2897         else
2898                 change = 0;
2899         spin_unlock_irq(&hdsp->lock);
2900         return change;
2901 }
2902
2903 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2904 HDSP_DA_GAIN("DA Gain", 0),
2905 HDSP_AD_GAIN("AD Gain", 0),
2906 HDSP_PHONE_GAIN("Phones Gain", 0),
2907 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2908 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2909 };
2910
2911 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2912 {
2913         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2914         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2915         .info =         snd_hdsp_control_spdif_info,
2916         .get =          snd_hdsp_control_spdif_get,
2917         .put =          snd_hdsp_control_spdif_put,
2918 },
2919 {
2920         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2921         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2922         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2923         .info =         snd_hdsp_control_spdif_stream_info,
2924         .get =          snd_hdsp_control_spdif_stream_get,
2925         .put =          snd_hdsp_control_spdif_stream_put,
2926 },
2927 {
2928         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2929         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2930         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2931         .info =         snd_hdsp_control_spdif_mask_info,
2932         .get =          snd_hdsp_control_spdif_mask_get,
2933         .private_value = IEC958_AES0_NONAUDIO |
2934                          IEC958_AES0_PROFESSIONAL |
2935                          IEC958_AES0_CON_EMPHASIS,
2936 },
2937 {
2938         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2939         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2940         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2941         .info =         snd_hdsp_control_spdif_mask_info,
2942         .get =          snd_hdsp_control_spdif_mask_get,
2943         .private_value = IEC958_AES0_NONAUDIO |
2944                          IEC958_AES0_PROFESSIONAL |
2945                          IEC958_AES0_PRO_EMPHASIS,
2946 },
2947 HDSP_MIXER("Mixer", 0),
2948 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2949 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2950 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2951 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2952 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2953 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2954 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2955 {
2956         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2957         .name = "Sample Clock Source Locking",
2958         .info = snd_hdsp_info_clock_source_lock,
2959         .get = snd_hdsp_get_clock_source_lock,
2960         .put = snd_hdsp_put_clock_source_lock,
2961 },
2962 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2963 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2964 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2965 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2966 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2967 /* 'External Rate' complies with the alsa control naming scheme */
2968 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2969 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2970 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2971 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2972 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2973 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2974 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2975 };
2976
2977
2978 static int hdsp_rpm_input12(struct hdsp *hdsp)
2979 {
2980         switch (hdsp->control_register & HDSP_RPM_Inp12) {
2981         case HDSP_RPM_Inp12_Phon_6dB:
2982                 return 0;
2983         case HDSP_RPM_Inp12_Phon_n6dB:
2984                 return 2;
2985         case HDSP_RPM_Inp12_Line_0dB:
2986                 return 3;
2987         case HDSP_RPM_Inp12_Line_n6dB:
2988                 return 4;
2989         }
2990         return 1;
2991 }
2992
2993
2994 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2995 {
2996         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2997
2998         ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2999         return 0;
3000 }
3001
3002
3003 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
3004 {
3005         hdsp->control_register &= ~HDSP_RPM_Inp12;
3006         switch (mode) {
3007         case 0:
3008                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
3009                 break;
3010         case 1:
3011                 break;
3012         case 2:
3013                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
3014                 break;
3015         case 3:
3016                 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
3017                 break;
3018         case 4:
3019                 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3020                 break;
3021         default:
3022                 return -1;
3023         }
3024
3025         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3026         return 0;
3027 }
3028
3029
3030 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3031 {
3032         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3033         int change;
3034         int val;
3035
3036         if (!snd_hdsp_use_is_exclusive(hdsp))
3037                 return -EBUSY;
3038         val = ucontrol->value.enumerated.item[0];
3039         if (val < 0)
3040                 val = 0;
3041         if (val > 4)
3042                 val = 4;
3043         spin_lock_irq(&hdsp->lock);
3044         if (val != hdsp_rpm_input12(hdsp))
3045                 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3046         else
3047                 change = 0;
3048         spin_unlock_irq(&hdsp->lock);
3049         return change;
3050 }
3051
3052
3053 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3054 {
3055         static const char * const texts[] = {
3056                 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3057         };
3058
3059         return snd_ctl_enum_info(uinfo, 1, 5, texts);
3060 }
3061
3062
3063 static int hdsp_rpm_input34(struct hdsp *hdsp)
3064 {
3065         switch (hdsp->control_register & HDSP_RPM_Inp34) {
3066         case HDSP_RPM_Inp34_Phon_6dB:
3067                 return 0;
3068         case HDSP_RPM_Inp34_Phon_n6dB:
3069                 return 2;
3070         case HDSP_RPM_Inp34_Line_0dB:
3071                 return 3;
3072         case HDSP_RPM_Inp34_Line_n6dB:
3073                 return 4;
3074         }
3075         return 1;
3076 }
3077
3078
3079 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3080 {
3081         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3082
3083         ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3084         return 0;
3085 }
3086
3087
3088 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3089 {
3090         hdsp->control_register &= ~HDSP_RPM_Inp34;
3091         switch (mode) {
3092         case 0:
3093                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3094                 break;
3095         case 1:
3096                 break;
3097         case 2:
3098                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3099                 break;
3100         case 3:
3101                 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3102                 break;
3103         case 4:
3104                 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3105                 break;
3106         default:
3107                 return -1;
3108         }
3109
3110         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3111         return 0;
3112 }
3113
3114
3115 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3116 {
3117         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3118         int change;
3119         int val;
3120
3121         if (!snd_hdsp_use_is_exclusive(hdsp))
3122                 return -EBUSY;
3123         val = ucontrol->value.enumerated.item[0];
3124         if (val < 0)
3125                 val = 0;
3126         if (val > 4)
3127                 val = 4;
3128         spin_lock_irq(&hdsp->lock);
3129         if (val != hdsp_rpm_input34(hdsp))
3130                 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3131         else
3132                 change = 0;
3133         spin_unlock_irq(&hdsp->lock);
3134         return change;
3135 }
3136
3137
3138 /* RPM Bypass switch */
3139 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3140 {
3141         return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3142 }
3143
3144
3145 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3146 {
3147         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3148
3149         ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3150         return 0;
3151 }
3152
3153
3154 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3155 {
3156         if (on)
3157                 hdsp->control_register |= HDSP_RPM_Bypass;
3158         else
3159                 hdsp->control_register &= ~HDSP_RPM_Bypass;
3160         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3161         return 0;
3162 }
3163
3164
3165 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3166 {
3167         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3168         int change;
3169         unsigned int val;
3170
3171         if (!snd_hdsp_use_is_exclusive(hdsp))
3172                 return -EBUSY;
3173         val = ucontrol->value.integer.value[0] & 1;
3174         spin_lock_irq(&hdsp->lock);
3175         change = (int)val != hdsp_rpm_bypass(hdsp);
3176         hdsp_set_rpm_bypass(hdsp, val);
3177         spin_unlock_irq(&hdsp->lock);
3178         return change;
3179 }
3180
3181
3182 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3183 {
3184         static const char * const texts[] = {"On", "Off"};
3185
3186         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3187 }
3188
3189
3190 /* RPM Disconnect switch */
3191 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3192 {
3193         return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3194 }
3195
3196
3197 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3198 {
3199         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3200
3201         ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3202         return 0;
3203 }
3204
3205
3206 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3207 {
3208         if (on)
3209                 hdsp->control_register |= HDSP_RPM_Disconnect;
3210         else
3211                 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3212         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3213         return 0;
3214 }
3215
3216
3217 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3218 {
3219         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3220         int change;
3221         unsigned int val;
3222
3223         if (!snd_hdsp_use_is_exclusive(hdsp))
3224                 return -EBUSY;
3225         val = ucontrol->value.integer.value[0] & 1;
3226         spin_lock_irq(&hdsp->lock);
3227         change = (int)val != hdsp_rpm_disconnect(hdsp);
3228         hdsp_set_rpm_disconnect(hdsp, val);
3229         spin_unlock_irq(&hdsp->lock);
3230         return change;
3231 }
3232
3233 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3234 {
3235         static const char * const texts[] = {"On", "Off"};
3236
3237         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3238 }
3239
3240 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3241         {
3242                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3243                 .name = "RPM Bypass",
3244                 .get = snd_hdsp_get_rpm_bypass,
3245                 .put = snd_hdsp_put_rpm_bypass,
3246                 .info = snd_hdsp_info_rpm_bypass
3247         },
3248         {
3249                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3250                 .name = "RPM Disconnect",
3251                 .get = snd_hdsp_get_rpm_disconnect,
3252                 .put = snd_hdsp_put_rpm_disconnect,
3253                 .info = snd_hdsp_info_rpm_disconnect
3254         },
3255         {
3256                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3257                 .name = "Input 1/2",
3258                 .get = snd_hdsp_get_rpm_input12,
3259                 .put = snd_hdsp_put_rpm_input12,
3260                 .info = snd_hdsp_info_rpm_input
3261         },
3262         {
3263                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3264                 .name = "Input 3/4",
3265                 .get = snd_hdsp_get_rpm_input34,
3266                 .put = snd_hdsp_put_rpm_input34,
3267                 .info = snd_hdsp_info_rpm_input
3268         },
3269         HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3270         HDSP_MIXER("Mixer", 0)
3271 };
3272
3273 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3274         HDSP_TOGGLE_SETTING("Analog Extension Board",
3275                         HDSP_AnalogExtensionBoard);
3276 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3277
3278 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3279 {
3280         unsigned int idx;
3281         int err;
3282         struct snd_kcontrol *kctl;
3283
3284         if (hdsp->io_type == RPM) {
3285                 /* RPM Bypass, Disconnect and Input switches */
3286                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3287                         err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3288                         if (err < 0)
3289                                 return err;
3290                 }
3291                 return 0;
3292         }
3293
3294         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3295                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3296                         return err;
3297                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3298                         hdsp->spdif_ctl = kctl;
3299         }
3300
3301         /* ADAT SyncCheck status */
3302         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3303         snd_hdsp_adat_sync_check.index = 1;
3304         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3305                 return err;
3306         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3307                 for (idx = 1; idx < 3; ++idx) {
3308                         snd_hdsp_adat_sync_check.index = idx+1;
3309                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3310                                 return err;
3311                 }
3312         }
3313
3314         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3315         if (hdsp->io_type == H9632) {
3316                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3317                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3318                                 return err;
3319                 }
3320         }
3321
3322         /* AEB control for H96xx card */
3323         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3324                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3325                                 return err;
3326         }
3327
3328         return 0;
3329 }
3330
3331 /*------------------------------------------------------------
3332    /proc interface
3333  ------------------------------------------------------------*/
3334
3335 static void
3336 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3337 {
3338         struct hdsp *hdsp = entry->private_data;
3339         unsigned int status;
3340         unsigned int status2;
3341         char *pref_sync_ref;
3342         char *autosync_ref;
3343         char *system_clock_mode;
3344         char *clock_source;
3345         int x;
3346
3347         status = hdsp_read(hdsp, HDSP_statusRegister);
3348         status2 = hdsp_read(hdsp, HDSP_status2Register);
3349
3350         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3351                     hdsp->card->number + 1);
3352         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3353                     hdsp->capture_buffer, hdsp->playback_buffer);
3354         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3355                     hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3356         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3357         snd_iprintf(buffer, "Control2 register: 0x%x\n",
3358                     hdsp->control2_register);
3359         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3360         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3361
3362         if (hdsp_check_for_iobox(hdsp)) {
3363                 snd_iprintf(buffer, "No I/O box connected.\n"
3364                             "Please connect one and upload firmware.\n");
3365                 return;
3366         }
3367
3368         if (hdsp_check_for_firmware(hdsp, 0)) {
3369                 if (hdsp->state & HDSP_FirmwareCached) {
3370                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3371                                 snd_iprintf(buffer, "Firmware loading from "
3372                                             "cache failed, "
3373                                             "please upload manually.\n");
3374                                 return;
3375                         }
3376                 } else {
3377                         int err = -EINVAL;
3378                         err = hdsp_request_fw_loader(hdsp);
3379                         if (err < 0) {
3380                                 snd_iprintf(buffer,
3381                                             "No firmware loaded nor cached, "
3382                                             "please upload firmware.\n");
3383                                 return;
3384                         }
3385                 }
3386         }
3387
3388         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3389         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3390         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3391         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3392         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3393         snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3394
3395         snd_iprintf(buffer, "\n");
3396
3397         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3398
3399         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3400         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3401         snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3402         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3403
3404         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3405
3406         snd_iprintf(buffer, "\n");
3407
3408         switch (hdsp_clock_source(hdsp)) {
3409         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3410                 clock_source = "AutoSync";
3411                 break;
3412         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3413                 clock_source = "Internal 32 kHz";
3414                 break;
3415         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3416                 clock_source = "Internal 44.1 kHz";
3417                 break;
3418         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3419                 clock_source = "Internal 48 kHz";
3420                 break;
3421         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3422                 clock_source = "Internal 64 kHz";
3423                 break;
3424         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3425                 clock_source = "Internal 88.2 kHz";
3426                 break;
3427         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3428                 clock_source = "Internal 96 kHz";
3429                 break;
3430         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3431                 clock_source = "Internal 128 kHz";
3432                 break;
3433         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3434                 clock_source = "Internal 176.4 kHz";
3435                 break;
3436                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3437                 clock_source = "Internal 192 kHz";
3438                 break;
3439         default:
3440                 clock_source = "Error";
3441         }
3442         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3443
3444         if (hdsp_system_clock_mode(hdsp))
3445                 system_clock_mode = "Slave";
3446         else
3447                 system_clock_mode = "Master";
3448
3449         switch (hdsp_pref_sync_ref (hdsp)) {
3450         case HDSP_SYNC_FROM_WORD:
3451                 pref_sync_ref = "Word Clock";
3452                 break;
3453         case HDSP_SYNC_FROM_ADAT_SYNC:
3454                 pref_sync_ref = "ADAT Sync";
3455                 break;
3456         case HDSP_SYNC_FROM_SPDIF:
3457                 pref_sync_ref = "SPDIF";
3458                 break;
3459         case HDSP_SYNC_FROM_ADAT1:
3460                 pref_sync_ref = "ADAT1";
3461                 break;
3462         case HDSP_SYNC_FROM_ADAT2:
3463                 pref_sync_ref = "ADAT2";
3464                 break;
3465         case HDSP_SYNC_FROM_ADAT3:
3466                 pref_sync_ref = "ADAT3";
3467                 break;
3468         default:
3469                 pref_sync_ref = "Word Clock";
3470                 break;
3471         }
3472         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3473
3474         switch (hdsp_autosync_ref (hdsp)) {
3475         case HDSP_AUTOSYNC_FROM_WORD:
3476                 autosync_ref = "Word Clock";
3477                 break;
3478         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3479                 autosync_ref = "ADAT Sync";
3480                 break;
3481         case HDSP_AUTOSYNC_FROM_SPDIF:
3482                 autosync_ref = "SPDIF";
3483                 break;
3484         case HDSP_AUTOSYNC_FROM_NONE:
3485                 autosync_ref = "None";
3486                 break;
3487         case HDSP_AUTOSYNC_FROM_ADAT1:
3488                 autosync_ref = "ADAT1";
3489                 break;
3490         case HDSP_AUTOSYNC_FROM_ADAT2:
3491                 autosync_ref = "ADAT2";
3492                 break;
3493         case HDSP_AUTOSYNC_FROM_ADAT3:
3494                 autosync_ref = "ADAT3";
3495                 break;
3496         default:
3497                 autosync_ref = "---";
3498                 break;
3499         }
3500         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3501
3502         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3503
3504         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3505
3506         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3507         snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3508
3509         snd_iprintf(buffer, "\n");
3510
3511         if (hdsp->io_type != RPM) {
3512                 switch (hdsp_spdif_in(hdsp)) {
3513                 case HDSP_SPDIFIN_OPTICAL:
3514                         snd_iprintf(buffer, "IEC958 input: Optical\n");
3515                         break;
3516                 case HDSP_SPDIFIN_COAXIAL:
3517                         snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3518                         break;
3519                 case HDSP_SPDIFIN_INTERNAL:
3520                         snd_iprintf(buffer, "IEC958 input: Internal\n");
3521                         break;
3522                 case HDSP_SPDIFIN_AES:
3523                         snd_iprintf(buffer, "IEC958 input: AES\n");
3524                         break;
3525                 default:
3526                         snd_iprintf(buffer, "IEC958 input: ???\n");
3527                         break;
3528                 }
3529         }
3530
3531         if (RPM == hdsp->io_type) {
3532                 if (hdsp->control_register & HDSP_RPM_Bypass)
3533                         snd_iprintf(buffer, "RPM Bypass: disabled\n");
3534                 else
3535                         snd_iprintf(buffer, "RPM Bypass: enabled\n");
3536                 if (hdsp->control_register & HDSP_RPM_Disconnect)
3537                         snd_iprintf(buffer, "RPM disconnected\n");
3538                 else
3539                         snd_iprintf(buffer, "RPM connected\n");
3540
3541                 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3542                 case HDSP_RPM_Inp12_Phon_6dB:
3543                         snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3544                         break;
3545                 case HDSP_RPM_Inp12_Phon_0dB:
3546                         snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3547                         break;
3548                 case HDSP_RPM_Inp12_Phon_n6dB:
3549                         snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3550                         break;
3551                 case HDSP_RPM_Inp12_Line_0dB:
3552                         snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3553                         break;
3554                 case HDSP_RPM_Inp12_Line_n6dB:
3555                         snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3556                         break;
3557                 default:
3558                         snd_iprintf(buffer, "Input 1/2: ???\n");
3559                 }
3560
3561                 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3562                 case HDSP_RPM_Inp34_Phon_6dB:
3563                         snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3564                         break;
3565                 case HDSP_RPM_Inp34_Phon_0dB:
3566                         snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3567                         break;
3568                 case HDSP_RPM_Inp34_Phon_n6dB:
3569                         snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3570                         break;
3571                 case HDSP_RPM_Inp34_Line_0dB:
3572                         snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3573                         break;
3574                 case HDSP_RPM_Inp34_Line_n6dB:
3575                         snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3576                         break;
3577                 default:
3578                         snd_iprintf(buffer, "Input 3/4: ???\n");
3579                 }
3580
3581         } else {
3582                 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3583                         snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3584                 else
3585                         snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3586
3587                 if (hdsp->control_register & HDSP_SPDIFProfessional)
3588                         snd_iprintf(buffer, "IEC958 quality: Professional\n");
3589                 else
3590                         snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3591
3592                 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3593                         snd_iprintf(buffer, "IEC958 emphasis: on\n");
3594                 else
3595                         snd_iprintf(buffer, "IEC958 emphasis: off\n");
3596
3597                 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3598                         snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3599                 else
3600                         snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3601                 x = hdsp_spdif_sample_rate(hdsp);
3602                 if (x != 0)
3603                         snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3604                 else
3605                         snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3606         }
3607         snd_iprintf(buffer, "\n");
3608
3609         /* Sync Check */
3610         x = status & HDSP_Sync0;
3611         if (status & HDSP_Lock0)
3612                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3613         else
3614                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3615
3616         switch (hdsp->io_type) {
3617         case Digiface:
3618         case H9652:
3619                 x = status & HDSP_Sync1;
3620                 if (status & HDSP_Lock1)
3621                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3622                 else
3623                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3624                 x = status & HDSP_Sync2;
3625                 if (status & HDSP_Lock2)
3626                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3627                 else
3628                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3629                 break;
3630         default:
3631                 /* relax */
3632                 break;
3633         }
3634
3635         x = status & HDSP_SPDIFSync;
3636         if (status & HDSP_SPDIFErrorFlag)
3637                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3638         else
3639                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3640
3641         x = status2 & HDSP_wc_sync;
3642         if (status2 & HDSP_wc_lock)
3643                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3644         else
3645                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3646
3647         x = status & HDSP_TimecodeSync;
3648         if (status & HDSP_TimecodeLock)
3649                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3650         else
3651                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3652
3653         snd_iprintf(buffer, "\n");
3654
3655         /* Informations about H9632 specific controls */
3656         if (hdsp->io_type == H9632) {
3657                 char *tmp;
3658
3659                 switch (hdsp_ad_gain(hdsp)) {
3660                 case 0:
3661                         tmp = "-10 dBV";
3662                         break;
3663                 case 1:
3664                         tmp = "+4 dBu";
3665                         break;
3666                 default:
3667                         tmp = "Lo Gain";
3668                         break;
3669                 }
3670                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3671
3672                 switch (hdsp_da_gain(hdsp)) {
3673                 case 0:
3674                         tmp = "Hi Gain";
3675                         break;
3676                 case 1:
3677                         tmp = "+4 dBu";
3678                         break;
3679                 default:
3680                         tmp = "-10 dBV";
3681                         break;
3682                 }
3683                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3684
3685                 switch (hdsp_phone_gain(hdsp)) {
3686                 case 0:
3687                         tmp = "0 dB";
3688                         break;
3689                 case 1:
3690                         tmp = "-6 dB";
3691                         break;
3692                 default:
3693                         tmp = "-12 dB";
3694                         break;
3695                 }
3696                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3697
3698                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3699                         hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3700                         "yes" : "no");
3701
3702                 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3703                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3704                 else
3705                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3706                 snd_iprintf(buffer, "\n");
3707         }
3708
3709 }
3710
3711 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3712 {
3713         struct snd_info_entry *entry;
3714
3715         if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3716                 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3717 }
3718
3719 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3720 {
3721         snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3722         snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3723 }
3724
3725 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3726 {
3727         unsigned long pb_bus, cb_bus;
3728
3729         if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3730             snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3731                 if (hdsp->capture_dma_buf.area)
3732                         snd_dma_free_pages(&hdsp->capture_dma_buf);
3733                 dev_err(hdsp->card->dev,
3734                         "%s: no buffers available\n", hdsp->card_name);
3735                 return -ENOMEM;
3736         }
3737
3738         /* Align to bus-space 64K boundary */
3739
3740         cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3741         pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3742
3743         /* Tell the card where it is */
3744
3745         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3746         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3747
3748         hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3749         hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3750
3751         return 0;
3752 }
3753
3754 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3755 {
3756         unsigned int i;
3757
3758         /* ASSUMPTION: hdsp->lock is either held, or
3759            there is no need to hold it (e.g. during module
3760            initialization).
3761          */
3762
3763         /* set defaults:
3764
3765            SPDIF Input via Coax
3766            Master clock mode
3767            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3768                             which implies 2 4096 sample, 32Kbyte periods).
3769            Enable line out.
3770          */
3771
3772         hdsp->control_register = HDSP_ClockModeMaster |
3773                                  HDSP_SPDIFInputCoaxial |
3774                                  hdsp_encode_latency(7) |
3775                                  HDSP_LineOut;
3776
3777
3778         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3779
3780 #ifdef SNDRV_BIG_ENDIAN
3781         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3782 #else
3783         hdsp->control2_register = 0;
3784 #endif
3785         if (hdsp->io_type == H9652)
3786                 snd_hdsp_9652_enable_mixer (hdsp);
3787         else
3788                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3789
3790         hdsp_reset_hw_pointer(hdsp);
3791         hdsp_compute_period_size(hdsp);
3792
3793         /* silence everything */
3794
3795         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3796                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3797
3798         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3799                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3800                         return -EIO;
3801         }
3802
3803         /* H9632 specific defaults */
3804         if (hdsp->io_type == H9632) {
3805                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3806                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3807         }
3808
3809         /* set a default rate so that the channel map is set up.
3810          */
3811
3812         hdsp_set_rate(hdsp, 48000, 1);
3813
3814         return 0;
3815 }
3816
3817 static void hdsp_midi_tasklet(unsigned long arg)
3818 {
3819         struct hdsp *hdsp = (struct hdsp *)arg;
3820
3821         if (hdsp->midi[0].pending)
3822                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3823         if (hdsp->midi[1].pending)
3824                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3825 }
3826
3827 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3828 {
3829         struct hdsp *hdsp = (struct hdsp *) dev_id;
3830         unsigned int status;
3831         int audio;
3832         int midi0;
3833         int midi1;
3834         unsigned int midi0status;
3835         unsigned int midi1status;
3836         int schedule = 0;
3837
3838         status = hdsp_read(hdsp, HDSP_statusRegister);
3839
3840         audio = status & HDSP_audioIRQPending;
3841         midi0 = status & HDSP_midi0IRQPending;
3842         midi1 = status & HDSP_midi1IRQPending;
3843
3844         if (!audio && !midi0 && !midi1)
3845                 return IRQ_NONE;
3846
3847         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3848
3849         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3850         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3851
3852         if (!(hdsp->state & HDSP_InitializationComplete))
3853                 return IRQ_HANDLED;
3854
3855         if (audio) {
3856                 if (hdsp->capture_substream)
3857                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3858
3859                 if (hdsp->playback_substream)
3860                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3861         }
3862
3863         if (midi0 && midi0status) {
3864                 if (hdsp->use_midi_tasklet) {
3865                         /* we disable interrupts for this input until processing is done */
3866                         hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3867                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3868                         hdsp->midi[0].pending = 1;
3869                         schedule = 1;
3870                 } else {
3871                         snd_hdsp_midi_input_read (&hdsp->midi[0]);
3872                 }
3873         }
3874         if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3875                 if (hdsp->use_midi_tasklet) {
3876                         /* we disable interrupts for this input until processing is done */
3877                         hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3878                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3879                         hdsp->midi[1].pending = 1;
3880                         schedule = 1;
3881                 } else {
3882                         snd_hdsp_midi_input_read (&hdsp->midi[1]);
3883                 }
3884         }
3885         if (hdsp->use_midi_tasklet && schedule)
3886                 tasklet_schedule(&hdsp->midi_tasklet);
3887         return IRQ_HANDLED;
3888 }
3889
3890 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3891 {
3892         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3893         return hdsp_hw_pointer(hdsp);
3894 }
3895
3896 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3897                                              int stream,
3898                                              int channel)
3899
3900 {
3901         int mapped_channel;
3902
3903         if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3904                 return NULL;
3905
3906         if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3907                 return NULL;
3908
3909         if (stream == SNDRV_PCM_STREAM_CAPTURE)
3910                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3911         else
3912                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3913 }
3914
3915 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
3916                                   snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3917 {
3918         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3919         char *channel_buf;
3920
3921         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3922                 return -EINVAL;
3923
3924         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3925         if (snd_BUG_ON(!channel_buf))
3926                 return -EIO;
3927         if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3928                 return -EFAULT;
3929         return count;
3930 }
3931
3932 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
3933                                  snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3934 {
3935         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3936         char *channel_buf;
3937
3938         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3939                 return -EINVAL;
3940
3941         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3942         if (snd_BUG_ON(!channel_buf))
3943                 return -EIO;
3944         if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3945                 return -EFAULT;
3946         return count;
3947 }
3948
3949 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
3950                                   snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3951 {
3952         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3953         char *channel_buf;
3954
3955         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3956         if (snd_BUG_ON(!channel_buf))
3957                 return -EIO;
3958         memset(channel_buf + pos * 4, 0, count * 4);
3959         return count;
3960 }
3961
3962 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3963 {
3964         struct snd_pcm_runtime *runtime = substream->runtime;
3965         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3966         struct snd_pcm_substream *other;
3967         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3968                 other = hdsp->capture_substream;
3969         else
3970                 other = hdsp->playback_substream;
3971         if (hdsp->running)
3972                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3973         else
3974                 runtime->status->hw_ptr = 0;
3975         if (other) {
3976                 struct snd_pcm_substream *s;
3977                 struct snd_pcm_runtime *oruntime = other->runtime;
3978                 snd_pcm_group_for_each_entry(s, substream) {
3979                         if (s == other) {
3980                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3981                                 break;
3982                         }
3983                 }
3984         }
3985         return 0;
3986 }
3987
3988 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3989                                  struct snd_pcm_hw_params *params)
3990 {
3991         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3992         int err;
3993         pid_t this_pid;
3994         pid_t other_pid;
3995
3996         if (hdsp_check_for_iobox (hdsp))
3997                 return -EIO;
3998
3999         if (hdsp_check_for_firmware(hdsp, 1))
4000                 return -EIO;
4001
4002         spin_lock_irq(&hdsp->lock);
4003
4004         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4005                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4006                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4007                 this_pid = hdsp->playback_pid;
4008                 other_pid = hdsp->capture_pid;
4009         } else {
4010                 this_pid = hdsp->capture_pid;
4011                 other_pid = hdsp->playback_pid;
4012         }
4013
4014         if ((other_pid > 0) && (this_pid != other_pid)) {
4015
4016                 /* The other stream is open, and not by the same
4017                    task as this one. Make sure that the parameters
4018                    that matter are the same.
4019                  */
4020
4021                 if (params_rate(params) != hdsp->system_sample_rate) {
4022                         spin_unlock_irq(&hdsp->lock);
4023                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4024                         return -EBUSY;
4025                 }
4026
4027                 if (params_period_size(params) != hdsp->period_bytes / 4) {
4028                         spin_unlock_irq(&hdsp->lock);
4029                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4030                         return -EBUSY;
4031                 }
4032
4033                 /* We're fine. */
4034
4035                 spin_unlock_irq(&hdsp->lock);
4036                 return 0;
4037
4038         } else {
4039                 spin_unlock_irq(&hdsp->lock);
4040         }
4041
4042         /* how to make sure that the rate matches an externally-set one ?
4043          */
4044
4045         spin_lock_irq(&hdsp->lock);
4046         if (! hdsp->clock_source_locked) {
4047                 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4048                         spin_unlock_irq(&hdsp->lock);
4049                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4050                         return err;
4051                 }
4052         }
4053         spin_unlock_irq(&hdsp->lock);
4054
4055         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4056                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4057                 return err;
4058         }
4059
4060         return 0;
4061 }
4062
4063 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4064                                     struct snd_pcm_channel_info *info)
4065 {
4066         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4067         int mapped_channel;
4068
4069         if (snd_BUG_ON(info->channel >= hdsp->max_channels))
4070                 return -EINVAL;
4071
4072         if ((mapped_channel = hdsp->channel_map[info->channel]) < 0)
4073                 return -EINVAL;
4074
4075         info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
4076         info->first = 0;
4077         info->step = 32;
4078         return 0;
4079 }
4080
4081 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4082                              unsigned int cmd, void *arg)
4083 {
4084         switch (cmd) {
4085         case SNDRV_PCM_IOCTL1_RESET:
4086                 return snd_hdsp_reset(substream);
4087         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4088                 return snd_hdsp_channel_info(substream, arg);
4089         default:
4090                 break;
4091         }
4092
4093         return snd_pcm_lib_ioctl(substream, cmd, arg);
4094 }
4095
4096 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4097 {
4098         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4099         struct snd_pcm_substream *other;
4100         int running;
4101
4102         if (hdsp_check_for_iobox (hdsp))
4103                 return -EIO;
4104
4105         if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4106                 return -EIO;
4107
4108         spin_lock(&hdsp->lock);
4109         running = hdsp->running;
4110         switch (cmd) {
4111         case SNDRV_PCM_TRIGGER_START:
4112                 running |= 1 << substream->stream;
4113                 break;
4114         case SNDRV_PCM_TRIGGER_STOP:
4115                 running &= ~(1 << substream->stream);
4116                 break;
4117         default:
4118                 snd_BUG();
4119                 spin_unlock(&hdsp->lock);
4120                 return -EINVAL;
4121         }
4122         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4123                 other = hdsp->capture_substream;
4124         else
4125                 other = hdsp->playback_substream;
4126
4127         if (other) {
4128                 struct snd_pcm_substream *s;
4129                 snd_pcm_group_for_each_entry(s, substream) {
4130                         if (s == other) {
4131                                 snd_pcm_trigger_done(s, substream);
4132                                 if (cmd == SNDRV_PCM_TRIGGER_START)
4133                                         running |= 1 << s->stream;
4134                                 else
4135                                         running &= ~(1 << s->stream);
4136                                 goto _ok;
4137                         }
4138                 }
4139                 if (cmd == SNDRV_PCM_TRIGGER_START) {
4140                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4141                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4142                                 hdsp_silence_playback(hdsp);
4143                 } else {
4144                         if (running &&
4145                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4146                                 hdsp_silence_playback(hdsp);
4147                 }
4148         } else {
4149                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4150                                 hdsp_silence_playback(hdsp);
4151         }
4152  _ok:
4153         snd_pcm_trigger_done(substream, substream);
4154         if (!hdsp->running && running)
4155                 hdsp_start_audio(hdsp);
4156         else if (hdsp->running && !running)
4157                 hdsp_stop_audio(hdsp);
4158         hdsp->running = running;
4159         spin_unlock(&hdsp->lock);
4160
4161         return 0;
4162 }
4163
4164 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4165 {
4166         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4167         int result = 0;
4168
4169         if (hdsp_check_for_iobox (hdsp))
4170                 return -EIO;
4171
4172         if (hdsp_check_for_firmware(hdsp, 1))
4173                 return -EIO;
4174
4175         spin_lock_irq(&hdsp->lock);
4176         if (!hdsp->running)
4177                 hdsp_reset_hw_pointer(hdsp);
4178         spin_unlock_irq(&hdsp->lock);
4179         return result;
4180 }
4181
4182 static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4183 {
4184         .info =                 (SNDRV_PCM_INFO_MMAP |
4185                                  SNDRV_PCM_INFO_MMAP_VALID |
4186                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4187                                  SNDRV_PCM_INFO_SYNC_START |
4188                                  SNDRV_PCM_INFO_DOUBLE),
4189 #ifdef SNDRV_BIG_ENDIAN
4190         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4191 #else
4192         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4193 #endif
4194         .rates =                (SNDRV_PCM_RATE_32000 |
4195                                  SNDRV_PCM_RATE_44100 |
4196                                  SNDRV_PCM_RATE_48000 |
4197                                  SNDRV_PCM_RATE_64000 |
4198                                  SNDRV_PCM_RATE_88200 |
4199                                  SNDRV_PCM_RATE_96000),
4200         .rate_min =             32000,
4201         .rate_max =             96000,
4202         .channels_min =         6,
4203         .channels_max =         HDSP_MAX_CHANNELS,
4204         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4205         .period_bytes_min =     (64 * 4) * 10,
4206         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4207         .periods_min =          2,
4208         .periods_max =          2,
4209         .fifo_size =            0
4210 };
4211
4212 static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4213 {
4214         .info =                 (SNDRV_PCM_INFO_MMAP |
4215                                  SNDRV_PCM_INFO_MMAP_VALID |
4216                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4217                                  SNDRV_PCM_INFO_SYNC_START),
4218 #ifdef SNDRV_BIG_ENDIAN
4219         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4220 #else
4221         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4222 #endif
4223         .rates =                (SNDRV_PCM_RATE_32000 |
4224                                  SNDRV_PCM_RATE_44100 |
4225                                  SNDRV_PCM_RATE_48000 |
4226                                  SNDRV_PCM_RATE_64000 |
4227                                  SNDRV_PCM_RATE_88200 |
4228                                  SNDRV_PCM_RATE_96000),
4229         .rate_min =             32000,
4230         .rate_max =             96000,
4231         .channels_min =         5,
4232         .channels_max =         HDSP_MAX_CHANNELS,
4233         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4234         .period_bytes_min =     (64 * 4) * 10,
4235         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4236         .periods_min =          2,
4237         .periods_max =          2,
4238         .fifo_size =            0
4239 };
4240
4241 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4242
4243 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4244         .count = ARRAY_SIZE(hdsp_period_sizes),
4245         .list = hdsp_period_sizes,
4246         .mask = 0
4247 };
4248
4249 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4250
4251 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4252         .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4253         .list = hdsp_9632_sample_rates,
4254         .mask = 0
4255 };
4256
4257 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4258                                         struct snd_pcm_hw_rule *rule)
4259 {
4260         struct hdsp *hdsp = rule->private;
4261         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4262         if (hdsp->io_type == H9632) {
4263                 unsigned int list[3];
4264                 list[0] = hdsp->qs_in_channels;
4265                 list[1] = hdsp->ds_in_channels;
4266                 list[2] = hdsp->ss_in_channels;
4267                 return snd_interval_list(c, 3, list, 0);
4268         } else {
4269                 unsigned int list[2];
4270                 list[0] = hdsp->ds_in_channels;
4271                 list[1] = hdsp->ss_in_channels;
4272                 return snd_interval_list(c, 2, list, 0);
4273         }
4274 }
4275
4276 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4277                                         struct snd_pcm_hw_rule *rule)
4278 {
4279         unsigned int list[3];
4280         struct hdsp *hdsp = rule->private;
4281         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4282         if (hdsp->io_type == H9632) {
4283                 list[0] = hdsp->qs_out_channels;
4284                 list[1] = hdsp->ds_out_channels;
4285                 list[2] = hdsp->ss_out_channels;
4286                 return snd_interval_list(c, 3, list, 0);
4287         } else {
4288                 list[0] = hdsp->ds_out_channels;
4289                 list[1] = hdsp->ss_out_channels;
4290         }
4291         return snd_interval_list(c, 2, list, 0);
4292 }
4293
4294 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4295                                              struct snd_pcm_hw_rule *rule)
4296 {
4297         struct hdsp *hdsp = rule->private;
4298         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4299         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4300         if (r->min > 96000 && hdsp->io_type == H9632) {
4301                 struct snd_interval t = {
4302                         .min = hdsp->qs_in_channels,
4303                         .max = hdsp->qs_in_channels,
4304                         .integer = 1,
4305                 };
4306                 return snd_interval_refine(c, &t);
4307         } else if (r->min > 48000 && r->max <= 96000) {
4308                 struct snd_interval t = {
4309                         .min = hdsp->ds_in_channels,
4310                         .max = hdsp->ds_in_channels,
4311                         .integer = 1,
4312                 };
4313                 return snd_interval_refine(c, &t);
4314         } else if (r->max < 64000) {
4315                 struct snd_interval t = {
4316                         .min = hdsp->ss_in_channels,
4317                         .max = hdsp->ss_in_channels,
4318                         .integer = 1,
4319                 };
4320                 return snd_interval_refine(c, &t);
4321         }
4322         return 0;
4323 }
4324
4325 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4326                                              struct snd_pcm_hw_rule *rule)
4327 {
4328         struct hdsp *hdsp = rule->private;
4329         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4330         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4331         if (r->min > 96000 && hdsp->io_type == H9632) {
4332                 struct snd_interval t = {
4333                         .min = hdsp->qs_out_channels,
4334                         .max = hdsp->qs_out_channels,
4335                         .integer = 1,
4336                 };
4337                 return snd_interval_refine(c, &t);
4338         } else if (r->min > 48000 && r->max <= 96000) {
4339                 struct snd_interval t = {
4340                         .min = hdsp->ds_out_channels,
4341                         .max = hdsp->ds_out_channels,
4342                         .integer = 1,
4343                 };
4344                 return snd_interval_refine(c, &t);
4345         } else if (r->max < 64000) {
4346                 struct snd_interval t = {
4347                         .min = hdsp->ss_out_channels,
4348                         .max = hdsp->ss_out_channels,
4349                         .integer = 1,
4350                 };
4351                 return snd_interval_refine(c, &t);
4352         }
4353         return 0;
4354 }
4355
4356 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4357                                              struct snd_pcm_hw_rule *rule)
4358 {
4359         struct hdsp *hdsp = rule->private;
4360         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4361         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4362         if (c->min >= hdsp->ss_out_channels) {
4363                 struct snd_interval t = {
4364                         .min = 32000,
4365                         .max = 48000,
4366                         .integer = 1,
4367                 };
4368                 return snd_interval_refine(r, &t);
4369         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4370                 struct snd_interval t = {
4371                         .min = 128000,
4372                         .max = 192000,
4373                         .integer = 1,
4374                 };
4375                 return snd_interval_refine(r, &t);
4376         } else if (c->max <= hdsp->ds_out_channels) {
4377                 struct snd_interval t = {
4378                         .min = 64000,
4379                         .max = 96000,
4380                         .integer = 1,
4381                 };
4382                 return snd_interval_refine(r, &t);
4383         }
4384         return 0;
4385 }
4386
4387 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4388                                              struct snd_pcm_hw_rule *rule)
4389 {
4390         struct hdsp *hdsp = rule->private;
4391         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4392         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4393         if (c->min >= hdsp->ss_in_channels) {
4394                 struct snd_interval t = {
4395                         .min = 32000,
4396                         .max = 48000,
4397                         .integer = 1,
4398                 };
4399                 return snd_interval_refine(r, &t);
4400         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4401                 struct snd_interval t = {
4402                         .min = 128000,
4403                         .max = 192000,
4404                         .integer = 1,
4405                 };
4406                 return snd_interval_refine(r, &t);
4407         } else if (c->max <= hdsp->ds_in_channels) {
4408                 struct snd_interval t = {
4409                         .min = 64000,
4410                         .max = 96000,
4411                         .integer = 1,
4412                 };
4413                 return snd_interval_refine(r, &t);
4414         }
4415         return 0;
4416 }
4417
4418 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4419 {
4420         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4421         struct snd_pcm_runtime *runtime = substream->runtime;
4422
4423         if (hdsp_check_for_iobox (hdsp))
4424                 return -EIO;
4425
4426         if (hdsp_check_for_firmware(hdsp, 1))
4427                 return -EIO;
4428
4429         spin_lock_irq(&hdsp->lock);
4430
4431         snd_pcm_set_sync(substream);
4432
4433         runtime->hw = snd_hdsp_playback_subinfo;
4434         runtime->dma_area = hdsp->playback_buffer;
4435         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4436
4437         hdsp->playback_pid = current->pid;
4438         hdsp->playback_substream = substream;
4439
4440         spin_unlock_irq(&hdsp->lock);
4441
4442         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4443         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4444         if (hdsp->clock_source_locked) {
4445                 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4446         } else if (hdsp->io_type == H9632) {
4447                 runtime->hw.rate_max = 192000;
4448                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4449                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4450         }
4451         if (hdsp->io_type == H9632) {
4452                 runtime->hw.channels_min = hdsp->qs_out_channels;
4453                 runtime->hw.channels_max = hdsp->ss_out_channels;
4454         }
4455
4456         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4457                              snd_hdsp_hw_rule_out_channels, hdsp,
4458                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4459         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4460                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4461                              SNDRV_PCM_HW_PARAM_RATE, -1);
4462         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4463                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4464                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4465
4466         if (RPM != hdsp->io_type) {
4467                 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4468                 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4469                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4470                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4471         }
4472         return 0;
4473 }
4474
4475 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4476 {
4477         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4478
4479         spin_lock_irq(&hdsp->lock);
4480
4481         hdsp->playback_pid = -1;
4482         hdsp->playback_substream = NULL;
4483
4484         spin_unlock_irq(&hdsp->lock);
4485
4486         if (RPM != hdsp->io_type) {
4487                 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4488                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4489                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4490         }
4491         return 0;
4492 }
4493
4494
4495 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4496 {
4497         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4498         struct snd_pcm_runtime *runtime = substream->runtime;
4499
4500         if (hdsp_check_for_iobox (hdsp))
4501                 return -EIO;
4502
4503         if (hdsp_check_for_firmware(hdsp, 1))
4504                 return -EIO;
4505
4506         spin_lock_irq(&hdsp->lock);
4507
4508         snd_pcm_set_sync(substream);
4509
4510         runtime->hw = snd_hdsp_capture_subinfo;
4511         runtime->dma_area = hdsp->capture_buffer;
4512         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4513
4514         hdsp->capture_pid = current->pid;
4515         hdsp->capture_substream = substream;
4516
4517         spin_unlock_irq(&hdsp->lock);
4518
4519         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4520         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4521         if (hdsp->io_type == H9632) {
4522                 runtime->hw.channels_min = hdsp->qs_in_channels;
4523                 runtime->hw.channels_max = hdsp->ss_in_channels;
4524                 runtime->hw.rate_max = 192000;
4525                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4526                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4527         }
4528         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4529                              snd_hdsp_hw_rule_in_channels, hdsp,
4530                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4531         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4532                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4533                              SNDRV_PCM_HW_PARAM_RATE, -1);
4534         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4535                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4536                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4537         return 0;
4538 }
4539
4540 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4541 {
4542         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4543
4544         spin_lock_irq(&hdsp->lock);
4545
4546         hdsp->capture_pid = -1;
4547         hdsp->capture_substream = NULL;
4548
4549         spin_unlock_irq(&hdsp->lock);
4550         return 0;
4551 }
4552
4553 /* helper functions for copying meter values */
4554 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4555 {
4556         u32 val = readl(src);
4557         return copy_to_user(dest, &val, 4);
4558 }
4559
4560 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4561 {
4562         u32 rms_low, rms_high;
4563         u64 rms;
4564         rms_low = readl(src_low);
4565         rms_high = readl(src_high);
4566         rms = ((u64)rms_high << 32) | rms_low;
4567         return copy_to_user(dest, &rms, 8);
4568 }
4569
4570 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4571 {
4572         u32 rms_low, rms_high;
4573         u64 rms;
4574         rms_low = readl(src_low) & 0xffffff00;
4575         rms_high = readl(src_high) & 0xffffff00;
4576         rms = ((u64)rms_high << 32) | rms_low;
4577         return copy_to_user(dest, &rms, 8);
4578 }
4579
4580 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4581 {
4582         int doublespeed = 0;
4583         int i, j, channels, ofs;
4584
4585         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4586                 doublespeed = 1;
4587         channels = doublespeed ? 14 : 26;
4588         for (i = 0, j = 0; i < 26; ++i) {
4589                 if (doublespeed && (i & 4))
4590                         continue;
4591                 ofs = HDSP_9652_peakBase - j * 4;
4592                 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4593                         return -EFAULT;
4594                 ofs -= channels * 4;
4595                 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4596                         return -EFAULT;
4597                 ofs -= channels * 4;
4598                 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4599                         return -EFAULT;
4600                 ofs = HDSP_9652_rmsBase + j * 8;
4601                 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4602                                 hdsp->iobase + ofs + 4))
4603                         return -EFAULT;
4604                 ofs += channels * 8;
4605                 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4606                                 hdsp->iobase + ofs + 4))
4607                         return -EFAULT;
4608                 ofs += channels * 8;
4609                 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4610                                 hdsp->iobase + ofs + 4))
4611                         return -EFAULT;
4612                 j++;
4613         }
4614         return 0;
4615 }
4616
4617 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4618 {
4619         int i, j;
4620         struct hdsp_9632_meters __iomem *m;
4621         int doublespeed = 0;
4622
4623         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4624                 doublespeed = 1;
4625         m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4626         for (i = 0, j = 0; i < 16; ++i, ++j) {
4627                 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4628                         return -EFAULT;
4629                 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4630                         return -EFAULT;
4631                 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4632                         return -EFAULT;
4633                 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4634                                 &m->input_rms_high[j]))
4635                         return -EFAULT;
4636                 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4637                                 &m->playback_rms_high[j]))
4638                         return -EFAULT;
4639                 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4640                                 &m->output_rms_high[j]))
4641                         return -EFAULT;
4642                 if (doublespeed && i == 3) i += 4;
4643         }
4644         return 0;
4645 }
4646
4647 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4648 {
4649         int i;
4650
4651         for (i = 0; i < 26; i++) {
4652                 if (copy_u32_le(&peak_rms->playback_peaks[i],
4653                                 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4654                         return -EFAULT;
4655                 if (copy_u32_le(&peak_rms->input_peaks[i],
4656                                 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4657                         return -EFAULT;
4658         }
4659         for (i = 0; i < 28; i++) {
4660                 if (copy_u32_le(&peak_rms->output_peaks[i],
4661                                 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4662                         return -EFAULT;
4663         }
4664         for (i = 0; i < 26; ++i) {
4665                 if (copy_u64_le(&peak_rms->playback_rms[i],
4666                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4667                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4668                         return -EFAULT;
4669                 if (copy_u64_le(&peak_rms->input_rms[i],
4670                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4671                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4672                         return -EFAULT;
4673         }
4674         return 0;
4675 }
4676
4677 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4678 {
4679         struct hdsp *hdsp = hw->private_data;
4680         void __user *argp = (void __user *)arg;
4681         int err;
4682
4683         switch (cmd) {
4684         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4685                 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4686
4687                 err = hdsp_check_for_iobox(hdsp);
4688                 if (err < 0)
4689                         return err;
4690
4691                 err = hdsp_check_for_firmware(hdsp, 1);
4692                 if (err < 0)
4693                         return err;
4694
4695                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4696                         dev_err(hdsp->card->dev,
4697                                 "firmware needs to be uploaded to the card.\n");
4698                         return -EINVAL;
4699                 }
4700
4701                 switch (hdsp->io_type) {
4702                 case H9652:
4703                         return hdsp_9652_get_peak(hdsp, peak_rms);
4704                 case H9632:
4705                         return hdsp_9632_get_peak(hdsp, peak_rms);
4706                 default:
4707                         return hdsp_get_peak(hdsp, peak_rms);
4708                 }
4709         }
4710         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4711                 struct hdsp_config_info info;
4712                 unsigned long flags;
4713                 int i;
4714
4715                 err = hdsp_check_for_iobox(hdsp);
4716                 if (err < 0)
4717                         return err;
4718
4719                 err = hdsp_check_for_firmware(hdsp, 1);
4720                 if (err < 0)
4721                         return err;
4722
4723                 memset(&info, 0, sizeof(info));
4724                 spin_lock_irqsave(&hdsp->lock, flags);
4725                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4726                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4727                 if (hdsp->io_type != H9632)
4728                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4729                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4730                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4731                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4732                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4733                 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4734                                 HDSP_SPDIFOpticalOut);
4735                 info.spdif_professional = (unsigned char)
4736                         hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4737                 info.spdif_emphasis = (unsigned char)
4738                         hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4739                 info.spdif_nonaudio = (unsigned char)
4740                         hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4741                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4742                 info.system_sample_rate = hdsp->system_sample_rate;
4743                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4744                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4745                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4746                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4747                 info.line_out = (unsigned char)
4748                         hdsp_toggle_setting(hdsp, HDSP_LineOut);
4749                 if (hdsp->io_type == H9632) {
4750                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4751                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4752                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4753                         info.xlr_breakout_cable =
4754                                 (unsigned char)hdsp_toggle_setting(hdsp,
4755                                         HDSP_XLRBreakoutCable);
4756
4757                 } else if (hdsp->io_type == RPM) {
4758                         info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4759                         info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4760                 }
4761                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4762                         info.analog_extension_board =
4763                                 (unsigned char)hdsp_toggle_setting(hdsp,
4764                                             HDSP_AnalogExtensionBoard);
4765                 spin_unlock_irqrestore(&hdsp->lock, flags);
4766                 if (copy_to_user(argp, &info, sizeof(info)))
4767                         return -EFAULT;
4768                 break;
4769         }
4770         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4771                 struct hdsp_9632_aeb h9632_aeb;
4772
4773                 if (hdsp->io_type != H9632) return -EINVAL;
4774                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4775                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4776                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4777                         return -EFAULT;
4778                 break;
4779         }
4780         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4781                 struct hdsp_version hdsp_version;
4782                 int err;
4783
4784                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4785                 if (hdsp->io_type == Undefined) {
4786                         if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4787                                 return err;
4788                 }
4789                 memset(&hdsp_version, 0, sizeof(hdsp_version));
4790                 hdsp_version.io_type = hdsp->io_type;
4791                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4792                 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4793                         return -EFAULT;
4794                 break;
4795         }
4796         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4797                 struct hdsp_firmware __user *firmware;
4798                 u32 __user *firmware_data;
4799                 int err;
4800
4801                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4802                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4803                 if (hdsp->io_type == Undefined) return -EINVAL;
4804
4805                 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4806                         return -EBUSY;
4807
4808                 dev_info(hdsp->card->dev,
4809                          "initializing firmware upload\n");
4810                 firmware = (struct hdsp_firmware __user *)argp;
4811
4812                 if (get_user(firmware_data, &firmware->firmware_data))
4813                         return -EFAULT;
4814
4815                 if (hdsp_check_for_iobox (hdsp))
4816                         return -EIO;
4817
4818                 if (!hdsp->fw_uploaded) {
4819                         hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4820                         if (!hdsp->fw_uploaded)
4821                                 return -ENOMEM;
4822                 }
4823
4824                 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4825                                    HDSP_FIRMWARE_SIZE)) {
4826                         vfree(hdsp->fw_uploaded);
4827                         hdsp->fw_uploaded = NULL;
4828                         return -EFAULT;
4829                 }
4830
4831                 hdsp->state |= HDSP_FirmwareCached;
4832
4833                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4834                         return err;
4835
4836                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4837                         if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4838                                 return err;
4839
4840                         snd_hdsp_initialize_channels(hdsp);
4841                         snd_hdsp_initialize_midi_flush(hdsp);
4842
4843                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4844                                 dev_err(hdsp->card->dev,
4845                                         "error creating alsa devices\n");
4846                                 return err;
4847                         }
4848                 }
4849                 break;
4850         }
4851         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4852                 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4853                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4854                         return -EFAULT;
4855                 break;
4856         }
4857         default:
4858                 return -EINVAL;
4859         }
4860         return 0;
4861 }
4862
4863 static struct snd_pcm_ops snd_hdsp_playback_ops = {
4864         .open =         snd_hdsp_playback_open,
4865         .close =        snd_hdsp_playback_release,
4866         .ioctl =        snd_hdsp_ioctl,
4867         .hw_params =    snd_hdsp_hw_params,
4868         .prepare =      snd_hdsp_prepare,
4869         .trigger =      snd_hdsp_trigger,
4870         .pointer =      snd_hdsp_hw_pointer,
4871         .copy =         snd_hdsp_playback_copy,
4872         .silence =      snd_hdsp_hw_silence,
4873 };
4874
4875 static struct snd_pcm_ops snd_hdsp_capture_ops = {
4876         .open =         snd_hdsp_capture_open,
4877         .close =        snd_hdsp_capture_release,
4878         .ioctl =        snd_hdsp_ioctl,
4879         .hw_params =    snd_hdsp_hw_params,
4880         .prepare =      snd_hdsp_prepare,
4881         .trigger =      snd_hdsp_trigger,
4882         .pointer =      snd_hdsp_hw_pointer,
4883         .copy =         snd_hdsp_capture_copy,
4884 };
4885
4886 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4887 {
4888         struct snd_hwdep *hw;
4889         int err;
4890
4891         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4892                 return err;
4893
4894         hdsp->hwdep = hw;
4895         hw->private_data = hdsp;
4896         strcpy(hw->name, "HDSP hwdep interface");
4897
4898         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4899         hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4900
4901         return 0;
4902 }
4903
4904 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4905 {
4906         struct snd_pcm *pcm;
4907         int err;
4908
4909         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4910                 return err;
4911
4912         hdsp->pcm = pcm;
4913         pcm->private_data = hdsp;
4914         strcpy(pcm->name, hdsp->card_name);
4915
4916         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4917         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4918
4919         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4920
4921         return 0;
4922 }
4923
4924 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4925 {
4926         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4927         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4928 }
4929
4930 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4931 {
4932         int i;
4933
4934         if (hdsp_fifo_wait (hdsp, 0, 100)) {
4935                 dev_err(hdsp->card->dev,
4936                         "enable_io fifo_wait failed\n");
4937                 return -EIO;
4938         }
4939
4940         for (i = 0; i < hdsp->max_channels; ++i) {
4941                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4942                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4943         }
4944
4945         return 0;
4946 }
4947
4948 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4949 {
4950         int status, aebi_channels, aebo_channels;
4951
4952         switch (hdsp->io_type) {
4953         case Digiface:
4954                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4955                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4956                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4957                 break;
4958
4959         case H9652:
4960                 hdsp->card_name = "RME Hammerfall HDSP 9652";
4961                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4962                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4963                 break;
4964
4965         case H9632:
4966                 status = hdsp_read(hdsp, HDSP_statusRegister);
4967                 /* HDSP_AEBx bits are low when AEB are connected */
4968                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4969                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4970                 hdsp->card_name = "RME Hammerfall HDSP 9632";
4971                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4972                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4973                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4974                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4975                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4976                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4977                 break;
4978
4979         case Multiface:
4980                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4981                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4982                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4983                 break;
4984
4985         case RPM:
4986                 hdsp->card_name = "RME Hammerfall DSP + RPM";
4987                 hdsp->ss_in_channels = RPM_CHANNELS-1;
4988                 hdsp->ss_out_channels = RPM_CHANNELS;
4989                 hdsp->ds_in_channels = RPM_CHANNELS-1;
4990                 hdsp->ds_out_channels = RPM_CHANNELS;
4991                 break;
4992
4993         default:
4994                 /* should never get here */
4995                 break;
4996         }
4997 }
4998
4999 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5000 {
5001         snd_hdsp_flush_midi_input (hdsp, 0);
5002         snd_hdsp_flush_midi_input (hdsp, 1);
5003 }
5004
5005 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5006 {
5007         int err;
5008
5009         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5010                 dev_err(card->dev,
5011                         "Error creating pcm interface\n");
5012                 return err;
5013         }
5014
5015
5016         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5017                 dev_err(card->dev,
5018                         "Error creating first midi interface\n");
5019                 return err;
5020         }
5021
5022         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5023                 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5024                         dev_err(card->dev,
5025                                 "Error creating second midi interface\n");
5026                         return err;
5027                 }
5028         }
5029
5030         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5031                 dev_err(card->dev,
5032                         "Error creating ctl interface\n");
5033                 return err;
5034         }
5035
5036         snd_hdsp_proc_init(hdsp);
5037
5038         hdsp->system_sample_rate = -1;
5039         hdsp->playback_pid = -1;
5040         hdsp->capture_pid = -1;
5041         hdsp->capture_substream = NULL;
5042         hdsp->playback_substream = NULL;
5043
5044         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5045                 dev_err(card->dev,
5046                         "Error setting default values\n");
5047                 return err;
5048         }
5049
5050         if (!(hdsp->state & HDSP_InitializationComplete)) {
5051                 strcpy(card->shortname, "Hammerfall DSP");
5052                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5053                         hdsp->port, hdsp->irq);
5054
5055                 if ((err = snd_card_register(card)) < 0) {
5056                         dev_err(card->dev,
5057                                 "error registering card\n");
5058                         return err;
5059                 }
5060                 hdsp->state |= HDSP_InitializationComplete;
5061         }
5062
5063         return 0;
5064 }
5065
5066 /* load firmware via hotplug fw loader */
5067 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5068 {
5069         const char *fwfile;
5070         const struct firmware *fw;
5071         int err;
5072
5073         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5074                 return 0;
5075         if (hdsp->io_type == Undefined) {
5076                 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5077                         return err;
5078                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5079                         return 0;
5080         }
5081
5082         /* caution: max length of firmware filename is 30! */
5083         switch (hdsp->io_type) {
5084         case RPM:
5085                 fwfile = "rpm_firmware.bin";
5086                 break;
5087         case Multiface:
5088                 if (hdsp->firmware_rev == 0xa)
5089                         fwfile = "multiface_firmware.bin";
5090                 else
5091                         fwfile = "multiface_firmware_rev11.bin";
5092                 break;
5093         case Digiface:
5094                 if (hdsp->firmware_rev == 0xa)
5095                         fwfile = "digiface_firmware.bin";
5096                 else
5097                         fwfile = "digiface_firmware_rev11.bin";
5098                 break;
5099         default:
5100                 dev_err(hdsp->card->dev,
5101                         "invalid io_type %d\n", hdsp->io_type);
5102                 return -EINVAL;
5103         }
5104
5105         if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5106                 dev_err(hdsp->card->dev,
5107                         "cannot load firmware %s\n", fwfile);
5108                 return -ENOENT;
5109         }
5110         if (fw->size < HDSP_FIRMWARE_SIZE) {
5111                 dev_err(hdsp->card->dev,
5112                         "too short firmware size %d (expected %d)\n",
5113                            (int)fw->size, HDSP_FIRMWARE_SIZE);
5114                 return -EINVAL;
5115         }
5116
5117         hdsp->firmware = fw;
5118
5119         hdsp->state |= HDSP_FirmwareCached;
5120
5121         if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5122                 return err;
5123
5124         if (!(hdsp->state & HDSP_InitializationComplete)) {
5125                 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5126                         return err;
5127
5128                 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5129                         dev_err(hdsp->card->dev,
5130                                 "error creating hwdep device\n");
5131                         return err;
5132                 }
5133                 snd_hdsp_initialize_channels(hdsp);
5134                 snd_hdsp_initialize_midi_flush(hdsp);
5135                 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5136                         dev_err(hdsp->card->dev,
5137                                 "error creating alsa devices\n");
5138                         return err;
5139                 }
5140         }
5141         return 0;
5142 }
5143
5144 static int snd_hdsp_create(struct snd_card *card,
5145                            struct hdsp *hdsp)
5146 {
5147         struct pci_dev *pci = hdsp->pci;
5148         int err;
5149         int is_9652 = 0;
5150         int is_9632 = 0;
5151
5152         hdsp->irq = -1;
5153         hdsp->state = 0;
5154         hdsp->midi[0].rmidi = NULL;
5155         hdsp->midi[1].rmidi = NULL;
5156         hdsp->midi[0].input = NULL;
5157         hdsp->midi[1].input = NULL;
5158         hdsp->midi[0].output = NULL;
5159         hdsp->midi[1].output = NULL;
5160         hdsp->midi[0].pending = 0;
5161         hdsp->midi[1].pending = 0;
5162         spin_lock_init(&hdsp->midi[0].lock);
5163         spin_lock_init(&hdsp->midi[1].lock);
5164         hdsp->iobase = NULL;
5165         hdsp->control_register = 0;
5166         hdsp->control2_register = 0;
5167         hdsp->io_type = Undefined;
5168         hdsp->max_channels = 26;
5169
5170         hdsp->card = card;
5171
5172         spin_lock_init(&hdsp->lock);
5173
5174         tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5175
5176         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5177         hdsp->firmware_rev &= 0xff;
5178
5179         /* From Martin Bjoernsen :
5180             "It is important that the card's latency timer register in
5181             the PCI configuration space is set to a value much larger
5182             than 0 by the computer's BIOS or the driver.
5183             The windows driver always sets this 8 bit register [...]
5184             to its maximum 255 to avoid problems with some computers."
5185         */
5186         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5187
5188         strcpy(card->driver, "H-DSP");
5189         strcpy(card->mixername, "Xilinx FPGA");
5190
5191         if (hdsp->firmware_rev < 0xa)
5192                 return -ENODEV;
5193         else if (hdsp->firmware_rev < 0x64)
5194                 hdsp->card_name = "RME Hammerfall DSP";
5195         else if (hdsp->firmware_rev < 0x96) {
5196                 hdsp->card_name = "RME HDSP 9652";
5197                 is_9652 = 1;
5198         } else {
5199                 hdsp->card_name = "RME HDSP 9632";
5200                 hdsp->max_channels = 16;
5201                 is_9632 = 1;
5202         }
5203
5204         if ((err = pci_enable_device(pci)) < 0)
5205                 return err;
5206
5207         pci_set_master(hdsp->pci);
5208
5209         if ((err = pci_request_regions(pci, "hdsp")) < 0)
5210                 return err;
5211         hdsp->port = pci_resource_start(pci, 0);
5212         if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5213                 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5214                         hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5215                 return -EBUSY;
5216         }
5217
5218         if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5219                         KBUILD_MODNAME, hdsp)) {
5220                 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5221                 return -EBUSY;
5222         }
5223
5224         hdsp->irq = pci->irq;
5225         hdsp->precise_ptr = 0;
5226         hdsp->use_midi_tasklet = 1;
5227         hdsp->dds_value = 0;
5228
5229         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5230                 return err;
5231
5232         if (!is_9652 && !is_9632) {
5233                 /* we wait a maximum of 10 seconds to let freshly
5234                  * inserted cardbus cards do their hardware init */
5235                 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5236
5237                 if (err < 0)
5238                         return err;
5239
5240                 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5241                         if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5242                                 /* we don't fail as this can happen
5243                                    if userspace is not ready for
5244                                    firmware upload
5245                                 */
5246                                 dev_err(hdsp->card->dev,
5247                                         "couldn't get firmware from userspace. try using hdsploader\n");
5248                         else
5249                                 /* init is complete, we return */
5250                                 return 0;
5251                         /* we defer initialization */
5252                         dev_info(hdsp->card->dev,
5253                                  "card initialization pending : waiting for firmware\n");
5254                         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5255                                 return err;
5256                         return 0;
5257                 } else {
5258                         dev_info(hdsp->card->dev,
5259                                  "Firmware already present, initializing card.\n");
5260                         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5261                                 hdsp->io_type = RPM;
5262                         else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5263                                 hdsp->io_type = Multiface;
5264                         else
5265                                 hdsp->io_type = Digiface;
5266                 }
5267         }
5268
5269         if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5270                 return err;
5271
5272         if (is_9652)
5273                 hdsp->io_type = H9652;
5274
5275         if (is_9632)
5276                 hdsp->io_type = H9632;
5277
5278         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5279                 return err;
5280
5281         snd_hdsp_initialize_channels(hdsp);
5282         snd_hdsp_initialize_midi_flush(hdsp);
5283
5284         hdsp->state |= HDSP_FirmwareLoaded;
5285
5286         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5287                 return err;
5288
5289         return 0;
5290 }
5291
5292 static int snd_hdsp_free(struct hdsp *hdsp)
5293 {
5294         if (hdsp->port) {
5295                 /* stop the audio, and cancel all interrupts */
5296                 tasklet_kill(&hdsp->midi_tasklet);
5297                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5298                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5299         }
5300
5301         if (hdsp->irq >= 0)
5302                 free_irq(hdsp->irq, (void *)hdsp);
5303
5304         snd_hdsp_free_buffers(hdsp);
5305
5306         release_firmware(hdsp->firmware);
5307         vfree(hdsp->fw_uploaded);
5308         iounmap(hdsp->iobase);
5309
5310         if (hdsp->port)
5311                 pci_release_regions(hdsp->pci);
5312
5313         pci_disable_device(hdsp->pci);
5314         return 0;
5315 }
5316
5317 static void snd_hdsp_card_free(struct snd_card *card)
5318 {
5319         struct hdsp *hdsp = card->private_data;
5320
5321         if (hdsp)
5322                 snd_hdsp_free(hdsp);
5323 }
5324
5325 static int snd_hdsp_probe(struct pci_dev *pci,
5326                           const struct pci_device_id *pci_id)
5327 {
5328         static int dev;
5329         struct hdsp *hdsp;
5330         struct snd_card *card;
5331         int err;
5332
5333         if (dev >= SNDRV_CARDS)
5334                 return -ENODEV;
5335         if (!enable[dev]) {
5336                 dev++;
5337                 return -ENOENT;
5338         }
5339
5340         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5341                            sizeof(struct hdsp), &card);
5342         if (err < 0)
5343                 return err;
5344
5345         hdsp = card->private_data;
5346         card->private_free = snd_hdsp_card_free;
5347         hdsp->dev = dev;
5348         hdsp->pci = pci;
5349
5350         if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5351                 snd_card_free(card);
5352                 return err;
5353         }
5354
5355         strcpy(card->shortname, "Hammerfall DSP");
5356         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5357                 hdsp->port, hdsp->irq);
5358
5359         if ((err = snd_card_register(card)) < 0) {
5360                 snd_card_free(card);
5361                 return err;
5362         }
5363         pci_set_drvdata(pci, card);
5364         dev++;
5365         return 0;
5366 }
5367
5368 static void snd_hdsp_remove(struct pci_dev *pci)
5369 {
5370         snd_card_free(pci_get_drvdata(pci));
5371 }
5372
5373 static struct pci_driver hdsp_driver = {
5374         .name =     KBUILD_MODNAME,
5375         .id_table = snd_hdsp_ids,
5376         .probe =    snd_hdsp_probe,
5377         .remove = snd_hdsp_remove,
5378 };
5379
5380 module_pci_driver(hdsp_driver);