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Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/agpgart
[deliverable/linux.git] / sound / pci / rme9652 / hdsp.c
1 /*
2 * ALSA driver for RME Hammerfall DSP audio interface(s)
3 *
4 * Copyright (c) 2002 Paul Davis
5 * Marcus Andersson
6 * Thomas Charbonnel
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <sound/driver.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/interrupt.h>
28 #include <linux/slab.h>
29 #include <linux/pci.h>
30 #include <linux/firmware.h>
31 #include <linux/moduleparam.h>
32
33 #include <sound/core.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/info.h>
37 #include <sound/asoundef.h>
38 #include <sound/rawmidi.h>
39 #include <sound/hwdep.h>
40 #include <sound/initval.h>
41 #include <sound/hdsp.h>
42
43 #include <asm/byteorder.h>
44 #include <asm/current.h>
45 #include <asm/io.h>
46
47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
49 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
50
51 module_param_array(index, int, NULL, 0444);
52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
53 module_param_array(id, charp, NULL, 0444);
54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
55 module_param_array(enable, bool, NULL, 0444);
56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
58 MODULE_DESCRIPTION("RME Hammerfall DSP");
59 MODULE_LICENSE("GPL");
60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
61 "{RME HDSP-9652},"
62 "{RME HDSP-9632}}");
63
64 #define HDSP_MAX_CHANNELS 26
65 #define HDSP_MAX_DS_CHANNELS 14
66 #define HDSP_MAX_QS_CHANNELS 8
67 #define DIGIFACE_SS_CHANNELS 26
68 #define DIGIFACE_DS_CHANNELS 14
69 #define MULTIFACE_SS_CHANNELS 18
70 #define MULTIFACE_DS_CHANNELS 14
71 #define H9652_SS_CHANNELS 26
72 #define H9652_DS_CHANNELS 14
73 /* This does not include possible Analog Extension Boards
74 AEBs are detected at card initialization
75 */
76 #define H9632_SS_CHANNELS 12
77 #define H9632_DS_CHANNELS 8
78 #define H9632_QS_CHANNELS 4
79
80 /* Write registers. These are defined as byte-offsets from the iobase value.
81 */
82 #define HDSP_resetPointer 0
83 #define HDSP_freqReg 0
84 #define HDSP_outputBufferAddress 32
85 #define HDSP_inputBufferAddress 36
86 #define HDSP_controlRegister 64
87 #define HDSP_interruptConfirmation 96
88 #define HDSP_outputEnable 128
89 #define HDSP_control2Reg 256
90 #define HDSP_midiDataOut0 352
91 #define HDSP_midiDataOut1 356
92 #define HDSP_fifoData 368
93 #define HDSP_inputEnable 384
94
95 /* Read registers. These are defined as byte-offsets from the iobase value
96 */
97
98 #define HDSP_statusRegister 0
99 #define HDSP_timecode 128
100 #define HDSP_status2Register 192
101 #define HDSP_midiDataOut0 352
102 #define HDSP_midiDataOut1 356
103 #define HDSP_midiDataIn0 360
104 #define HDSP_midiDataIn1 364
105 #define HDSP_midiStatusOut0 384
106 #define HDSP_midiStatusOut1 388
107 #define HDSP_midiStatusIn0 392
108 #define HDSP_midiStatusIn1 396
109 #define HDSP_fifoStatus 400
110
111 /* the meters are regular i/o-mapped registers, but offset
112 considerably from the rest. the peak registers are reset
113 when read; the least-significant 4 bits are full-scale counters;
114 the actual peak value is in the most-significant 24 bits.
115 */
116
117 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
118 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
119 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
120 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
121 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
122
123
124 /* This is for H9652 cards
125 Peak values are read downward from the base
126 Rms values are read upward
127 There are rms values for the outputs too
128 26*3 values are read in ss mode
129 14*3 in ds mode, with no gap between values
130 */
131 #define HDSP_9652_peakBase 7164
132 #define HDSP_9652_rmsBase 4096
133
134 /* c.f. the hdsp_9632_meters_t struct */
135 #define HDSP_9632_metersBase 4096
136
137 #define HDSP_IO_EXTENT 7168
138
139 /* control2 register bits */
140
141 #define HDSP_TMS 0x01
142 #define HDSP_TCK 0x02
143 #define HDSP_TDI 0x04
144 #define HDSP_JTAG 0x08
145 #define HDSP_PWDN 0x10
146 #define HDSP_PROGRAM 0x020
147 #define HDSP_CONFIG_MODE_0 0x040
148 #define HDSP_CONFIG_MODE_1 0x080
149 #define HDSP_VERSION_BIT 0x100
150 #define HDSP_BIGENDIAN_MODE 0x200
151 #define HDSP_RD_MULTIPLE 0x400
152 #define HDSP_9652_ENABLE_MIXER 0x800
153 #define HDSP_TDO 0x10000000
154
155 #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
156 #define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
157
158 /* Control Register bits */
159
160 #define HDSP_Start (1<<0) /* start engine */
161 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
162 #define HDSP_Latency1 (1<<2) /* [ see above ] */
163 #define HDSP_Latency2 (1<<3) /* [ see above ] */
164 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
165 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
166 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
167 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
168 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
169 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
170 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
171 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
172 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
173 #define HDSP_SyncRef2 (1<<13)
174 #define HDSP_SPDIFInputSelect0 (1<<14)
175 #define HDSP_SPDIFInputSelect1 (1<<15)
176 #define HDSP_SyncRef0 (1<<16)
177 #define HDSP_SyncRef1 (1<<17)
178 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
179 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
180 #define HDSP_Midi0InterruptEnable (1<<22)
181 #define HDSP_Midi1InterruptEnable (1<<23)
182 #define HDSP_LineOut (1<<24)
183 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
184 #define HDSP_ADGain1 (1<<26)
185 #define HDSP_DAGain0 (1<<27)
186 #define HDSP_DAGain1 (1<<28)
187 #define HDSP_PhoneGain0 (1<<29)
188 #define HDSP_PhoneGain1 (1<<30)
189 #define HDSP_QuadSpeed (1<<31)
190
191 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
192 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
193 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
194 #define HDSP_ADGainLowGain 0
195
196 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
197 #define HDSP_DAGainHighGain HDSP_DAGainMask
198 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
199 #define HDSP_DAGainMinus10dBV 0
200
201 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
202 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
203 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
204 #define HDSP_PhoneGainMinus12dB 0
205
206 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
207 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
208
209 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
210 #define HDSP_SPDIFInputADAT1 0
211 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
212 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
213 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
214
215 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
216 #define HDSP_SyncRef_ADAT1 0
217 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
218 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
219 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
220 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
221 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
222
223 /* Sample Clock Sources */
224
225 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
226 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
227 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
228 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
229 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
230 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
231 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
232 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
233 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
234 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
235
236 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
237
238 #define HDSP_SYNC_FROM_WORD 0
239 #define HDSP_SYNC_FROM_SPDIF 1
240 #define HDSP_SYNC_FROM_ADAT1 2
241 #define HDSP_SYNC_FROM_ADAT_SYNC 3
242 #define HDSP_SYNC_FROM_ADAT2 4
243 #define HDSP_SYNC_FROM_ADAT3 5
244
245 /* SyncCheck status */
246
247 #define HDSP_SYNC_CHECK_NO_LOCK 0
248 #define HDSP_SYNC_CHECK_LOCK 1
249 #define HDSP_SYNC_CHECK_SYNC 2
250
251 /* AutoSync references - used by "autosync_ref" control switch */
252
253 #define HDSP_AUTOSYNC_FROM_WORD 0
254 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
255 #define HDSP_AUTOSYNC_FROM_SPDIF 2
256 #define HDSP_AUTOSYNC_FROM_NONE 3
257 #define HDSP_AUTOSYNC_FROM_ADAT1 4
258 #define HDSP_AUTOSYNC_FROM_ADAT2 5
259 #define HDSP_AUTOSYNC_FROM_ADAT3 6
260
261 /* Possible sources of S/PDIF input */
262
263 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
264 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
265 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
266 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
267
268 #define HDSP_Frequency32KHz HDSP_Frequency0
269 #define HDSP_Frequency44_1KHz HDSP_Frequency1
270 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
271 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
272 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
273 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
274 /* For H9632 cards */
275 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
276 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
277 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
278
279 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
280 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
281
282 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
283 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
284
285 /* Status Register bits */
286
287 #define HDSP_audioIRQPending (1<<0)
288 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
289 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
290 #define HDSP_Lock1 (1<<2)
291 #define HDSP_Lock0 (1<<3)
292 #define HDSP_SPDIFSync (1<<4)
293 #define HDSP_TimecodeLock (1<<5)
294 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
295 #define HDSP_Sync2 (1<<16)
296 #define HDSP_Sync1 (1<<17)
297 #define HDSP_Sync0 (1<<18)
298 #define HDSP_DoubleSpeedStatus (1<<19)
299 #define HDSP_ConfigError (1<<20)
300 #define HDSP_DllError (1<<21)
301 #define HDSP_spdifFrequency0 (1<<22)
302 #define HDSP_spdifFrequency1 (1<<23)
303 #define HDSP_spdifFrequency2 (1<<24)
304 #define HDSP_SPDIFErrorFlag (1<<25)
305 #define HDSP_BufferID (1<<26)
306 #define HDSP_TimecodeSync (1<<27)
307 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
308 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
309 #define HDSP_midi0IRQPending (1<<30)
310 #define HDSP_midi1IRQPending (1<<31)
311
312 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
313
314 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
315 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
316 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
317
318 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
319 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
320 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
321
322 /* This is for H9632 cards */
323 #define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask
324 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
325 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
326
327 /* Status2 Register bits */
328
329 #define HDSP_version0 (1<<0)
330 #define HDSP_version1 (1<<1)
331 #define HDSP_version2 (1<<2)
332 #define HDSP_wc_lock (1<<3)
333 #define HDSP_wc_sync (1<<4)
334 #define HDSP_inp_freq0 (1<<5)
335 #define HDSP_inp_freq1 (1<<6)
336 #define HDSP_inp_freq2 (1<<7)
337 #define HDSP_SelSyncRef0 (1<<8)
338 #define HDSP_SelSyncRef1 (1<<9)
339 #define HDSP_SelSyncRef2 (1<<10)
340
341 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
342
343 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
344 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
345 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
346 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
347 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
348 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
349 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
350 /* FIXME : more values for 9632 cards ? */
351
352 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
353 #define HDSP_SelSyncRef_ADAT1 0
354 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
355 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
356 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
357 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
358 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
359
360 /* Card state flags */
361
362 #define HDSP_InitializationComplete (1<<0)
363 #define HDSP_FirmwareLoaded (1<<1)
364 #define HDSP_FirmwareCached (1<<2)
365
366 /* FIFO wait times, defined in terms of 1/10ths of msecs */
367
368 #define HDSP_LONG_WAIT 5000
369 #define HDSP_SHORT_WAIT 30
370
371 #define UNITY_GAIN 32768
372 #define MINUS_INFINITY_GAIN 0
373
374 /* the size of a substream (1 mono data stream) */
375
376 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
377 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
378
379 /* the size of the area we need to allocate for DMA transfers. the
380 size is the same regardless of the number of channels - the
381 Multiface still uses the same memory area.
382
383 Note that we allocate 1 more channel than is apparently needed
384 because the h/w seems to write 1 byte beyond the end of the last
385 page. Sigh.
386 */
387
388 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
389 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
390
391 /* use hotplug firmeare loader? */
392 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
393 #if !defined(HDSP_USE_HWDEP_LOADER) && !defined(CONFIG_SND_HDSP)
394 #define HDSP_FW_LOADER
395 #endif
396 #endif
397
398 struct hdsp_9632_meters {
399 u32 input_peak[16];
400 u32 playback_peak[16];
401 u32 output_peak[16];
402 u32 xxx_peak[16];
403 u32 padding[64];
404 u32 input_rms_low[16];
405 u32 playback_rms_low[16];
406 u32 output_rms_low[16];
407 u32 xxx_rms_low[16];
408 u32 input_rms_high[16];
409 u32 playback_rms_high[16];
410 u32 output_rms_high[16];
411 u32 xxx_rms_high[16];
412 };
413
414 struct hdsp_midi {
415 struct hdsp *hdsp;
416 int id;
417 struct snd_rawmidi *rmidi;
418 struct snd_rawmidi_substream *input;
419 struct snd_rawmidi_substream *output;
420 char istimer; /* timer in use */
421 struct timer_list timer;
422 spinlock_t lock;
423 int pending;
424 };
425
426 struct hdsp {
427 spinlock_t lock;
428 struct snd_pcm_substream *capture_substream;
429 struct snd_pcm_substream *playback_substream;
430 struct hdsp_midi midi[2];
431 struct tasklet_struct midi_tasklet;
432 int use_midi_tasklet;
433 int precise_ptr;
434 u32 control_register; /* cached value */
435 u32 control2_register; /* cached value */
436 u32 creg_spdif;
437 u32 creg_spdif_stream;
438 int clock_source_locked;
439 char *card_name; /* digiface/multiface */
440 enum HDSP_IO_Type io_type; /* ditto, but for code use */
441 unsigned short firmware_rev;
442 unsigned short state; /* stores state bits */
443 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
444 size_t period_bytes; /* guess what this is */
445 unsigned char max_channels;
446 unsigned char qs_in_channels; /* quad speed mode for H9632 */
447 unsigned char ds_in_channels;
448 unsigned char ss_in_channels; /* different for multiface/digiface */
449 unsigned char qs_out_channels;
450 unsigned char ds_out_channels;
451 unsigned char ss_out_channels;
452
453 struct snd_dma_buffer capture_dma_buf;
454 struct snd_dma_buffer playback_dma_buf;
455 unsigned char *capture_buffer; /* suitably aligned address */
456 unsigned char *playback_buffer; /* suitably aligned address */
457
458 pid_t capture_pid;
459 pid_t playback_pid;
460 int running;
461 int system_sample_rate;
462 char *channel_map;
463 int dev;
464 int irq;
465 unsigned long port;
466 void __iomem *iobase;
467 struct snd_card *card;
468 struct snd_pcm *pcm;
469 struct snd_hwdep *hwdep;
470 struct pci_dev *pci;
471 struct snd_kcontrol *spdif_ctl;
472 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
473 unsigned int dds_value; /* last value written to freq register */
474 };
475
476 /* These tables map the ALSA channels 1..N to the channels that we
477 need to use in order to find the relevant channel buffer. RME
478 refer to this kind of mapping as between "the ADAT channel and
479 the DMA channel." We index it using the logical audio channel,
480 and the value is the DMA channel (i.e. channel buffer number)
481 where the data for that channel can be read/written from/to.
482 */
483
484 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
485 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
486 18, 19, 20, 21, 22, 23, 24, 25
487 };
488
489 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
490 /* Analog */
491 0, 1, 2, 3, 4, 5, 6, 7,
492 /* ADAT 2 */
493 16, 17, 18, 19, 20, 21, 22, 23,
494 /* SPDIF */
495 24, 25,
496 -1, -1, -1, -1, -1, -1, -1, -1
497 };
498
499 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
500 /* ADAT channels are remapped */
501 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
502 /* channels 12 and 13 are S/PDIF */
503 24, 25,
504 /* others don't exist */
505 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
506 };
507
508 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
509 /* ADAT channels */
510 0, 1, 2, 3, 4, 5, 6, 7,
511 /* SPDIF */
512 8, 9,
513 /* Analog */
514 10, 11,
515 /* AO4S-192 and AI4S-192 extension boards */
516 12, 13, 14, 15,
517 /* others don't exist */
518 -1, -1, -1, -1, -1, -1, -1, -1,
519 -1, -1
520 };
521
522 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
523 /* ADAT */
524 1, 3, 5, 7,
525 /* SPDIF */
526 8, 9,
527 /* Analog */
528 10, 11,
529 /* AO4S-192 and AI4S-192 extension boards */
530 12, 13, 14, 15,
531 /* others don't exist */
532 -1, -1, -1, -1, -1, -1, -1, -1,
533 -1, -1, -1, -1, -1, -1
534 };
535
536 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
537 /* ADAT is disabled in this mode */
538 /* SPDIF */
539 8, 9,
540 /* Analog */
541 10, 11,
542 /* AO4S-192 and AI4S-192 extension boards */
543 12, 13, 14, 15,
544 /* others don't exist */
545 -1, -1, -1, -1, -1, -1, -1, -1,
546 -1, -1, -1, -1, -1, -1, -1, -1,
547 -1, -1
548 };
549
550 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
551 {
552 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
553 dmab->dev.dev = snd_dma_pci_data(pci);
554 if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
555 if (dmab->bytes >= size)
556 return 0;
557 }
558 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
559 size, dmab) < 0)
560 return -ENOMEM;
561 return 0;
562 }
563
564 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
565 {
566 if (dmab->area) {
567 dmab->dev.dev = NULL; /* make it anonymous */
568 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
569 }
570 }
571
572
573 static struct pci_device_id snd_hdsp_ids[] = {
574 {
575 .vendor = PCI_VENDOR_ID_XILINX,
576 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
577 .subvendor = PCI_ANY_ID,
578 .subdevice = PCI_ANY_ID,
579 }, /* RME Hammerfall-DSP */
580 { 0, },
581 };
582
583 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
584
585 /* prototypes */
586 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
587 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
588 static int snd_hdsp_enable_io (struct hdsp *hdsp);
589 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
590 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
591 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
592 static int hdsp_autosync_ref(struct hdsp *hdsp);
593 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
594 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
595
596 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
597 {
598 switch (hdsp->firmware_rev) {
599 case 0xa:
600 return (64 * out) + (32 + (in));
601 case 0x96:
602 case 0x97:
603 case 0x98:
604 return (32 * out) + (16 + (in));
605 default:
606 return (52 * out) + (26 + (in));
607 }
608 }
609
610 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
611 {
612 switch (hdsp->firmware_rev) {
613 case 0xa:
614 return (64 * out) + in;
615 case 0x96:
616 case 0x97:
617 case 0x98:
618 return (32 * out) + in;
619 default:
620 return (52 * out) + in;
621 }
622 }
623
624 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
625 {
626 writel(val, hdsp->iobase + reg);
627 }
628
629 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
630 {
631 return readl (hdsp->iobase + reg);
632 }
633
634 static int hdsp_check_for_iobox (struct hdsp *hdsp)
635 {
636
637 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
638 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
639 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
640 hdsp->state &= ~HDSP_FirmwareLoaded;
641 return -EIO;
642 }
643 return 0;
644
645 }
646
647 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
648
649 int i;
650 unsigned long flags;
651
652 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
653
654 snd_printk ("Hammerfall-DSP: loading firmware\n");
655
656 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
657 hdsp_write (hdsp, HDSP_fifoData, 0);
658
659 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
660 snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n");
661 return -EIO;
662 }
663
664 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
665
666 for (i = 0; i < 24413; ++i) {
667 hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
668 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
669 snd_printk ("Hammerfall-DSP: timeout during firmware loading\n");
670 return -EIO;
671 }
672 }
673
674 ssleep(3);
675
676 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
677 snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n");
678 return -EIO;
679 }
680
681 #ifdef SNDRV_BIG_ENDIAN
682 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
683 #else
684 hdsp->control2_register = 0;
685 #endif
686 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
687 snd_printk ("Hammerfall-DSP: finished firmware loading\n");
688
689 }
690 if (hdsp->state & HDSP_InitializationComplete) {
691 snd_printk(KERN_INFO "Hammerfall-DSP: firmware loaded from cache, restoring defaults\n");
692 spin_lock_irqsave(&hdsp->lock, flags);
693 snd_hdsp_set_defaults(hdsp);
694 spin_unlock_irqrestore(&hdsp->lock, flags);
695 }
696
697 hdsp->state |= HDSP_FirmwareLoaded;
698
699 return 0;
700 }
701
702 static int hdsp_get_iobox_version (struct hdsp *hdsp)
703 {
704 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
705
706 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
707 hdsp_write (hdsp, HDSP_fifoData, 0);
708 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0)
709 return -EIO;
710
711 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
712 hdsp_write (hdsp, HDSP_fifoData, 0);
713
714 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
715 hdsp->io_type = Multiface;
716 hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
717 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
718 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
719 } else {
720 hdsp->io_type = Digiface;
721 }
722 } else {
723 /* firmware was already loaded, get iobox type */
724 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
725 hdsp->io_type = Multiface;
726 else
727 hdsp->io_type = Digiface;
728 }
729 return 0;
730 }
731
732
733 #ifdef HDSP_FW_LOADER
734 static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp);
735 #endif
736
737 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
738 {
739 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
740 return 0;
741 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
742 hdsp->state &= ~HDSP_FirmwareLoaded;
743 if (! load_on_demand)
744 return -EIO;
745 snd_printk(KERN_ERR "Hammerfall-DSP: firmware not present.\n");
746 /* try to load firmware */
747 if (! (hdsp->state & HDSP_FirmwareCached)) {
748 #ifdef HDSP_FW_LOADER
749 if (! hdsp_request_fw_loader(hdsp))
750 return 0;
751 #endif
752 snd_printk(KERN_ERR
753 "Hammerfall-DSP: No firmware loaded nor "
754 "cached, please upload firmware.\n");
755 return -EIO;
756 }
757 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
758 snd_printk(KERN_ERR
759 "Hammerfall-DSP: Firmware loading from "
760 "cache failed, please upload manually.\n");
761 return -EIO;
762 }
763 }
764 return 0;
765 }
766
767
768 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
769 {
770 int i;
771
772 /* the fifoStatus registers reports on how many words
773 are available in the command FIFO.
774 */
775
776 for (i = 0; i < timeout; i++) {
777
778 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
779 return 0;
780
781 /* not very friendly, but we only do this during a firmware
782 load and changing the mixer, so we just put up with it.
783 */
784
785 udelay (100);
786 }
787
788 snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n",
789 count, timeout);
790 return -1;
791 }
792
793 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
794 {
795 if (addr >= HDSP_MATRIX_MIXER_SIZE)
796 return 0;
797
798 return hdsp->mixer_matrix[addr];
799 }
800
801 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
802 {
803 unsigned int ad;
804
805 if (addr >= HDSP_MATRIX_MIXER_SIZE)
806 return -1;
807
808 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
809
810 /* from martin bjornsen:
811
812 "You can only write dwords to the
813 mixer memory which contain two
814 mixer values in the low and high
815 word. So if you want to change
816 value 0 you have to read value 1
817 from the cache and write both to
818 the first dword in the mixer
819 memory."
820 */
821
822 if (hdsp->io_type == H9632 && addr >= 512)
823 return 0;
824
825 if (hdsp->io_type == H9652 && addr >= 1352)
826 return 0;
827
828 hdsp->mixer_matrix[addr] = data;
829
830
831 /* `addr' addresses a 16-bit wide address, but
832 the address space accessed via hdsp_write
833 uses byte offsets. put another way, addr
834 varies from 0 to 1351, but to access the
835 corresponding memory location, we need
836 to access 0 to 2703 ...
837 */
838 ad = addr/2;
839
840 hdsp_write (hdsp, 4096 + (ad*4),
841 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
842 hdsp->mixer_matrix[addr&0x7fe]);
843
844 return 0;
845
846 } else {
847
848 ad = (addr << 16) + data;
849
850 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
851 return -1;
852
853 hdsp_write (hdsp, HDSP_fifoData, ad);
854 hdsp->mixer_matrix[addr] = data;
855
856 }
857
858 return 0;
859 }
860
861 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
862 {
863 unsigned long flags;
864 int ret = 1;
865
866 spin_lock_irqsave(&hdsp->lock, flags);
867 if ((hdsp->playback_pid != hdsp->capture_pid) &&
868 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
869 ret = 0;
870 spin_unlock_irqrestore(&hdsp->lock, flags);
871 return ret;
872 }
873
874 static int hdsp_external_sample_rate (struct hdsp *hdsp)
875 {
876 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
877 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
878
879 switch (rate_bits) {
880 case HDSP_systemFrequency32: return 32000;
881 case HDSP_systemFrequency44_1: return 44100;
882 case HDSP_systemFrequency48: return 48000;
883 case HDSP_systemFrequency64: return 64000;
884 case HDSP_systemFrequency88_2: return 88200;
885 case HDSP_systemFrequency96: return 96000;
886 default:
887 return 0;
888 }
889 }
890
891 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
892 {
893 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
894 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
895
896 if (status & HDSP_SPDIFErrorFlag)
897 return 0;
898
899 switch (rate_bits) {
900 case HDSP_spdifFrequency32KHz: return 32000;
901 case HDSP_spdifFrequency44_1KHz: return 44100;
902 case HDSP_spdifFrequency48KHz: return 48000;
903 case HDSP_spdifFrequency64KHz: return 64000;
904 case HDSP_spdifFrequency88_2KHz: return 88200;
905 case HDSP_spdifFrequency96KHz: return 96000;
906 case HDSP_spdifFrequency128KHz:
907 if (hdsp->io_type == H9632) return 128000;
908 break;
909 case HDSP_spdifFrequency176_4KHz:
910 if (hdsp->io_type == H9632) return 176400;
911 break;
912 case HDSP_spdifFrequency192KHz:
913 if (hdsp->io_type == H9632) return 192000;
914 break;
915 default:
916 break;
917 }
918 snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
919 return 0;
920 }
921
922 static void hdsp_compute_period_size(struct hdsp *hdsp)
923 {
924 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
925 }
926
927 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
928 {
929 int position;
930
931 position = hdsp_read(hdsp, HDSP_statusRegister);
932
933 if (!hdsp->precise_ptr)
934 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
935
936 position &= HDSP_BufferPositionMask;
937 position /= 4;
938 position &= (hdsp->period_bytes/2) - 1;
939 return position;
940 }
941
942 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
943 {
944 hdsp_write (hdsp, HDSP_resetPointer, 0);
945 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
946 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
947 * requires (?) to write again DDS value after a reset pointer
948 * (at least, it works like this) */
949 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
950 }
951
952 static void hdsp_start_audio(struct hdsp *s)
953 {
954 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
955 hdsp_write(s, HDSP_controlRegister, s->control_register);
956 }
957
958 static void hdsp_stop_audio(struct hdsp *s)
959 {
960 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
961 hdsp_write(s, HDSP_controlRegister, s->control_register);
962 }
963
964 static void hdsp_silence_playback(struct hdsp *hdsp)
965 {
966 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
967 }
968
969 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
970 {
971 int n;
972
973 spin_lock_irq(&s->lock);
974
975 frames >>= 7;
976 n = 0;
977 while (frames) {
978 n++;
979 frames >>= 1;
980 }
981
982 s->control_register &= ~HDSP_LatencyMask;
983 s->control_register |= hdsp_encode_latency(n);
984
985 hdsp_write(s, HDSP_controlRegister, s->control_register);
986
987 hdsp_compute_period_size(s);
988
989 spin_unlock_irq(&s->lock);
990
991 return 0;
992 }
993
994 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
995 {
996 u64 n;
997 u32 r;
998
999 if (rate >= 112000)
1000 rate /= 4;
1001 else if (rate >= 56000)
1002 rate /= 2;
1003
1004 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
1005 // return 104857600000000 / rate; // 100 MHz
1006 return 110100480000000 / rate; // 105 MHz
1007 */
1008 n = 104857600000000ULL; /* = 2^20 * 10^8 */
1009 div64_32(&n, rate, &r);
1010 /* n should be less than 2^32 for being written to FREQ register */
1011 snd_assert((n >> 32) == 0);
1012 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1013 value to write it after a reset */
1014 hdsp->dds_value = n;
1015 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1016 }
1017
1018 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1019 {
1020 int reject_if_open = 0;
1021 int current_rate;
1022 int rate_bits;
1023
1024 /* ASSUMPTION: hdsp->lock is either held, or
1025 there is no need for it (e.g. during module
1026 initialization).
1027 */
1028
1029 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1030 if (called_internally) {
1031 /* request from ctl or card initialization */
1032 snd_printk(KERN_ERR "Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n");
1033 return -1;
1034 } else {
1035 /* hw_param request while in AutoSync mode */
1036 int external_freq = hdsp_external_sample_rate(hdsp);
1037 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1038
1039 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1040 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in double speed mode\n");
1041 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1042 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in quad speed mode\n");
1043 else if (rate != external_freq) {
1044 snd_printk(KERN_INFO "Hammerfall-DSP: No AutoSync source for requested rate\n");
1045 return -1;
1046 }
1047 }
1048 }
1049
1050 current_rate = hdsp->system_sample_rate;
1051
1052 /* Changing from a "single speed" to a "double speed" rate is
1053 not allowed if any substreams are open. This is because
1054 such a change causes a shift in the location of
1055 the DMA buffers and a reduction in the number of available
1056 buffers.
1057
1058 Note that a similar but essentially insoluble problem
1059 exists for externally-driven rate changes. All we can do
1060 is to flag rate changes in the read/write routines. */
1061
1062 if (rate > 96000 && hdsp->io_type != H9632)
1063 return -EINVAL;
1064
1065 switch (rate) {
1066 case 32000:
1067 if (current_rate > 48000)
1068 reject_if_open = 1;
1069 rate_bits = HDSP_Frequency32KHz;
1070 break;
1071 case 44100:
1072 if (current_rate > 48000)
1073 reject_if_open = 1;
1074 rate_bits = HDSP_Frequency44_1KHz;
1075 break;
1076 case 48000:
1077 if (current_rate > 48000)
1078 reject_if_open = 1;
1079 rate_bits = HDSP_Frequency48KHz;
1080 break;
1081 case 64000:
1082 if (current_rate <= 48000 || current_rate > 96000)
1083 reject_if_open = 1;
1084 rate_bits = HDSP_Frequency64KHz;
1085 break;
1086 case 88200:
1087 if (current_rate <= 48000 || current_rate > 96000)
1088 reject_if_open = 1;
1089 rate_bits = HDSP_Frequency88_2KHz;
1090 break;
1091 case 96000:
1092 if (current_rate <= 48000 || current_rate > 96000)
1093 reject_if_open = 1;
1094 rate_bits = HDSP_Frequency96KHz;
1095 break;
1096 case 128000:
1097 if (current_rate < 128000)
1098 reject_if_open = 1;
1099 rate_bits = HDSP_Frequency128KHz;
1100 break;
1101 case 176400:
1102 if (current_rate < 128000)
1103 reject_if_open = 1;
1104 rate_bits = HDSP_Frequency176_4KHz;
1105 break;
1106 case 192000:
1107 if (current_rate < 128000)
1108 reject_if_open = 1;
1109 rate_bits = HDSP_Frequency192KHz;
1110 break;
1111 default:
1112 return -EINVAL;
1113 }
1114
1115 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1116 snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1117 hdsp->capture_pid,
1118 hdsp->playback_pid);
1119 return -EBUSY;
1120 }
1121
1122 hdsp->control_register &= ~HDSP_FrequencyMask;
1123 hdsp->control_register |= rate_bits;
1124 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1125
1126 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1127 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1128 hdsp_set_dds_value(hdsp, rate);
1129
1130 if (rate >= 128000) {
1131 hdsp->channel_map = channel_map_H9632_qs;
1132 } else if (rate > 48000) {
1133 if (hdsp->io_type == H9632)
1134 hdsp->channel_map = channel_map_H9632_ds;
1135 else
1136 hdsp->channel_map = channel_map_ds;
1137 } else {
1138 switch (hdsp->io_type) {
1139 case Multiface:
1140 hdsp->channel_map = channel_map_mf_ss;
1141 break;
1142 case Digiface:
1143 case H9652:
1144 hdsp->channel_map = channel_map_df_ss;
1145 break;
1146 case H9632:
1147 hdsp->channel_map = channel_map_H9632_ss;
1148 break;
1149 default:
1150 /* should never happen */
1151 break;
1152 }
1153 }
1154
1155 hdsp->system_sample_rate = rate;
1156
1157 return 0;
1158 }
1159
1160 /*----------------------------------------------------------------------------
1161 MIDI
1162 ----------------------------------------------------------------------------*/
1163
1164 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1165 {
1166 /* the hardware already does the relevant bit-mask with 0xff */
1167 if (id)
1168 return hdsp_read(hdsp, HDSP_midiDataIn1);
1169 else
1170 return hdsp_read(hdsp, HDSP_midiDataIn0);
1171 }
1172
1173 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1174 {
1175 /* the hardware already does the relevant bit-mask with 0xff */
1176 if (id)
1177 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1178 else
1179 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1180 }
1181
1182 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1183 {
1184 if (id)
1185 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1186 else
1187 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1188 }
1189
1190 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1191 {
1192 int fifo_bytes_used;
1193
1194 if (id)
1195 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1196 else
1197 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1198
1199 if (fifo_bytes_used < 128)
1200 return 128 - fifo_bytes_used;
1201 else
1202 return 0;
1203 }
1204
1205 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1206 {
1207 while (snd_hdsp_midi_input_available (hdsp, id))
1208 snd_hdsp_midi_read_byte (hdsp, id);
1209 }
1210
1211 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1212 {
1213 unsigned long flags;
1214 int n_pending;
1215 int to_write;
1216 int i;
1217 unsigned char buf[128];
1218
1219 /* Output is not interrupt driven */
1220
1221 spin_lock_irqsave (&hmidi->lock, flags);
1222 if (hmidi->output) {
1223 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1224 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1225 if (n_pending > (int)sizeof (buf))
1226 n_pending = sizeof (buf);
1227
1228 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1229 for (i = 0; i < to_write; ++i)
1230 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1231 }
1232 }
1233 }
1234 }
1235 spin_unlock_irqrestore (&hmidi->lock, flags);
1236 return 0;
1237 }
1238
1239 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1240 {
1241 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1242 unsigned long flags;
1243 int n_pending;
1244 int i;
1245
1246 spin_lock_irqsave (&hmidi->lock, flags);
1247 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1248 if (hmidi->input) {
1249 if (n_pending > (int)sizeof (buf))
1250 n_pending = sizeof (buf);
1251 for (i = 0; i < n_pending; ++i)
1252 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1253 if (n_pending)
1254 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1255 } else {
1256 /* flush the MIDI input FIFO */
1257 while (--n_pending)
1258 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1259 }
1260 }
1261 hmidi->pending = 0;
1262 if (hmidi->id)
1263 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1264 else
1265 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1266 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1267 spin_unlock_irqrestore (&hmidi->lock, flags);
1268 return snd_hdsp_midi_output_write (hmidi);
1269 }
1270
1271 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1272 {
1273 struct hdsp *hdsp;
1274 struct hdsp_midi *hmidi;
1275 unsigned long flags;
1276 u32 ie;
1277
1278 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1279 hdsp = hmidi->hdsp;
1280 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1281 spin_lock_irqsave (&hdsp->lock, flags);
1282 if (up) {
1283 if (!(hdsp->control_register & ie)) {
1284 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1285 hdsp->control_register |= ie;
1286 }
1287 } else {
1288 hdsp->control_register &= ~ie;
1289 tasklet_kill(&hdsp->midi_tasklet);
1290 }
1291
1292 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1293 spin_unlock_irqrestore (&hdsp->lock, flags);
1294 }
1295
1296 static void snd_hdsp_midi_output_timer(unsigned long data)
1297 {
1298 struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
1299 unsigned long flags;
1300
1301 snd_hdsp_midi_output_write(hmidi);
1302 spin_lock_irqsave (&hmidi->lock, flags);
1303
1304 /* this does not bump hmidi->istimer, because the
1305 kernel automatically removed the timer when it
1306 expired, and we are now adding it back, thus
1307 leaving istimer wherever it was set before.
1308 */
1309
1310 if (hmidi->istimer) {
1311 hmidi->timer.expires = 1 + jiffies;
1312 add_timer(&hmidi->timer);
1313 }
1314
1315 spin_unlock_irqrestore (&hmidi->lock, flags);
1316 }
1317
1318 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1319 {
1320 struct hdsp_midi *hmidi;
1321 unsigned long flags;
1322
1323 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1324 spin_lock_irqsave (&hmidi->lock, flags);
1325 if (up) {
1326 if (!hmidi->istimer) {
1327 init_timer(&hmidi->timer);
1328 hmidi->timer.function = snd_hdsp_midi_output_timer;
1329 hmidi->timer.data = (unsigned long) hmidi;
1330 hmidi->timer.expires = 1 + jiffies;
1331 add_timer(&hmidi->timer);
1332 hmidi->istimer++;
1333 }
1334 } else {
1335 if (hmidi->istimer && --hmidi->istimer <= 0)
1336 del_timer (&hmidi->timer);
1337 }
1338 spin_unlock_irqrestore (&hmidi->lock, flags);
1339 if (up)
1340 snd_hdsp_midi_output_write(hmidi);
1341 }
1342
1343 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1344 {
1345 struct hdsp_midi *hmidi;
1346
1347 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1348 spin_lock_irq (&hmidi->lock);
1349 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1350 hmidi->input = substream;
1351 spin_unlock_irq (&hmidi->lock);
1352
1353 return 0;
1354 }
1355
1356 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1357 {
1358 struct hdsp_midi *hmidi;
1359
1360 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1361 spin_lock_irq (&hmidi->lock);
1362 hmidi->output = substream;
1363 spin_unlock_irq (&hmidi->lock);
1364
1365 return 0;
1366 }
1367
1368 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1369 {
1370 struct hdsp_midi *hmidi;
1371
1372 snd_hdsp_midi_input_trigger (substream, 0);
1373
1374 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1375 spin_lock_irq (&hmidi->lock);
1376 hmidi->input = NULL;
1377 spin_unlock_irq (&hmidi->lock);
1378
1379 return 0;
1380 }
1381
1382 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1383 {
1384 struct hdsp_midi *hmidi;
1385
1386 snd_hdsp_midi_output_trigger (substream, 0);
1387
1388 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1389 spin_lock_irq (&hmidi->lock);
1390 hmidi->output = NULL;
1391 spin_unlock_irq (&hmidi->lock);
1392
1393 return 0;
1394 }
1395
1396 static struct snd_rawmidi_ops snd_hdsp_midi_output =
1397 {
1398 .open = snd_hdsp_midi_output_open,
1399 .close = snd_hdsp_midi_output_close,
1400 .trigger = snd_hdsp_midi_output_trigger,
1401 };
1402
1403 static struct snd_rawmidi_ops snd_hdsp_midi_input =
1404 {
1405 .open = snd_hdsp_midi_input_open,
1406 .close = snd_hdsp_midi_input_close,
1407 .trigger = snd_hdsp_midi_input_trigger,
1408 };
1409
1410 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1411 {
1412 char buf[32];
1413
1414 hdsp->midi[id].id = id;
1415 hdsp->midi[id].rmidi = NULL;
1416 hdsp->midi[id].input = NULL;
1417 hdsp->midi[id].output = NULL;
1418 hdsp->midi[id].hdsp = hdsp;
1419 hdsp->midi[id].istimer = 0;
1420 hdsp->midi[id].pending = 0;
1421 spin_lock_init (&hdsp->midi[id].lock);
1422
1423 sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1424 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1425 return -1;
1426
1427 sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1428 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1429
1430 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1431 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1432
1433 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1434 SNDRV_RAWMIDI_INFO_INPUT |
1435 SNDRV_RAWMIDI_INFO_DUPLEX;
1436
1437 return 0;
1438 }
1439
1440 /*-----------------------------------------------------------------------------
1441 Control Interface
1442 ----------------------------------------------------------------------------*/
1443
1444 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1445 {
1446 u32 val = 0;
1447 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1448 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1449 if (val & HDSP_SPDIFProfessional)
1450 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1451 else
1452 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1453 return val;
1454 }
1455
1456 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1457 {
1458 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1459 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1460 if (val & HDSP_SPDIFProfessional)
1461 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1462 else
1463 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1464 }
1465
1466 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1467 {
1468 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1469 uinfo->count = 1;
1470 return 0;
1471 }
1472
1473 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1474 {
1475 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1476
1477 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1478 return 0;
1479 }
1480
1481 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1482 {
1483 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1484 int change;
1485 u32 val;
1486
1487 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1488 spin_lock_irq(&hdsp->lock);
1489 change = val != hdsp->creg_spdif;
1490 hdsp->creg_spdif = val;
1491 spin_unlock_irq(&hdsp->lock);
1492 return change;
1493 }
1494
1495 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1496 {
1497 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1498 uinfo->count = 1;
1499 return 0;
1500 }
1501
1502 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1503 {
1504 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1505
1506 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1507 return 0;
1508 }
1509
1510 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1511 {
1512 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1513 int change;
1514 u32 val;
1515
1516 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1517 spin_lock_irq(&hdsp->lock);
1518 change = val != hdsp->creg_spdif_stream;
1519 hdsp->creg_spdif_stream = val;
1520 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1521 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1522 spin_unlock_irq(&hdsp->lock);
1523 return change;
1524 }
1525
1526 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1527 {
1528 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1529 uinfo->count = 1;
1530 return 0;
1531 }
1532
1533 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1534 {
1535 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1536 return 0;
1537 }
1538
1539 #define HDSP_SPDIF_IN(xname, xindex) \
1540 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1541 .name = xname, \
1542 .index = xindex, \
1543 .info = snd_hdsp_info_spdif_in, \
1544 .get = snd_hdsp_get_spdif_in, \
1545 .put = snd_hdsp_put_spdif_in }
1546
1547 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1548 {
1549 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1550 }
1551
1552 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1553 {
1554 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1555 hdsp->control_register |= hdsp_encode_spdif_in(in);
1556 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1557 return 0;
1558 }
1559
1560 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1561 {
1562 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1563 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1564
1565 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1566 uinfo->count = 1;
1567 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1568 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1569 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1570 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1571 return 0;
1572 }
1573
1574 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1575 {
1576 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1577
1578 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1579 return 0;
1580 }
1581
1582 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1583 {
1584 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1585 int change;
1586 unsigned int val;
1587
1588 if (!snd_hdsp_use_is_exclusive(hdsp))
1589 return -EBUSY;
1590 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1591 spin_lock_irq(&hdsp->lock);
1592 change = val != hdsp_spdif_in(hdsp);
1593 if (change)
1594 hdsp_set_spdif_input(hdsp, val);
1595 spin_unlock_irq(&hdsp->lock);
1596 return change;
1597 }
1598
1599 #define HDSP_SPDIF_OUT(xname, xindex) \
1600 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1601 .info = snd_hdsp_info_spdif_bits, \
1602 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1603
1604 static int hdsp_spdif_out(struct hdsp *hdsp)
1605 {
1606 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1607 }
1608
1609 static int hdsp_set_spdif_output(struct hdsp *hdsp, int out)
1610 {
1611 if (out)
1612 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1613 else
1614 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1615 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1616 return 0;
1617 }
1618
1619 static int snd_hdsp_info_spdif_bits(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1620 {
1621 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1622 uinfo->count = 1;
1623 uinfo->value.integer.min = 0;
1624 uinfo->value.integer.max = 1;
1625 return 0;
1626 }
1627
1628 static int snd_hdsp_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1629 {
1630 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1631
1632 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1633 return 0;
1634 }
1635
1636 static int snd_hdsp_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1637 {
1638 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1639 int change;
1640 unsigned int val;
1641
1642 if (!snd_hdsp_use_is_exclusive(hdsp))
1643 return -EBUSY;
1644 val = ucontrol->value.integer.value[0] & 1;
1645 spin_lock_irq(&hdsp->lock);
1646 change = (int)val != hdsp_spdif_out(hdsp);
1647 hdsp_set_spdif_output(hdsp, val);
1648 spin_unlock_irq(&hdsp->lock);
1649 return change;
1650 }
1651
1652 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1653 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1654 .info = snd_hdsp_info_spdif_bits, \
1655 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1656
1657 static int hdsp_spdif_professional(struct hdsp *hdsp)
1658 {
1659 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1660 }
1661
1662 static int hdsp_set_spdif_professional(struct hdsp *hdsp, int val)
1663 {
1664 if (val)
1665 hdsp->control_register |= HDSP_SPDIFProfessional;
1666 else
1667 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1668 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1669 return 0;
1670 }
1671
1672 static int snd_hdsp_get_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1673 {
1674 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1675
1676 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1677 return 0;
1678 }
1679
1680 static int snd_hdsp_put_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1681 {
1682 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1683 int change;
1684 unsigned int val;
1685
1686 if (!snd_hdsp_use_is_exclusive(hdsp))
1687 return -EBUSY;
1688 val = ucontrol->value.integer.value[0] & 1;
1689 spin_lock_irq(&hdsp->lock);
1690 change = (int)val != hdsp_spdif_professional(hdsp);
1691 hdsp_set_spdif_professional(hdsp, val);
1692 spin_unlock_irq(&hdsp->lock);
1693 return change;
1694 }
1695
1696 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1697 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1698 .info = snd_hdsp_info_spdif_bits, \
1699 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1700
1701 static int hdsp_spdif_emphasis(struct hdsp *hdsp)
1702 {
1703 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1704 }
1705
1706 static int hdsp_set_spdif_emphasis(struct hdsp *hdsp, int val)
1707 {
1708 if (val)
1709 hdsp->control_register |= HDSP_SPDIFEmphasis;
1710 else
1711 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1712 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1713 return 0;
1714 }
1715
1716 static int snd_hdsp_get_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1717 {
1718 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1719
1720 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1721 return 0;
1722 }
1723
1724 static int snd_hdsp_put_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1725 {
1726 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1727 int change;
1728 unsigned int val;
1729
1730 if (!snd_hdsp_use_is_exclusive(hdsp))
1731 return -EBUSY;
1732 val = ucontrol->value.integer.value[0] & 1;
1733 spin_lock_irq(&hdsp->lock);
1734 change = (int)val != hdsp_spdif_emphasis(hdsp);
1735 hdsp_set_spdif_emphasis(hdsp, val);
1736 spin_unlock_irq(&hdsp->lock);
1737 return change;
1738 }
1739
1740 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1741 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1742 .info = snd_hdsp_info_spdif_bits, \
1743 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1744
1745 static int hdsp_spdif_nonaudio(struct hdsp *hdsp)
1746 {
1747 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1748 }
1749
1750 static int hdsp_set_spdif_nonaudio(struct hdsp *hdsp, int val)
1751 {
1752 if (val)
1753 hdsp->control_register |= HDSP_SPDIFNonAudio;
1754 else
1755 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1756 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1757 return 0;
1758 }
1759
1760 static int snd_hdsp_get_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1761 {
1762 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1763
1764 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1765 return 0;
1766 }
1767
1768 static int snd_hdsp_put_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1769 {
1770 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1771 int change;
1772 unsigned int val;
1773
1774 if (!snd_hdsp_use_is_exclusive(hdsp))
1775 return -EBUSY;
1776 val = ucontrol->value.integer.value[0] & 1;
1777 spin_lock_irq(&hdsp->lock);
1778 change = (int)val != hdsp_spdif_nonaudio(hdsp);
1779 hdsp_set_spdif_nonaudio(hdsp, val);
1780 spin_unlock_irq(&hdsp->lock);
1781 return change;
1782 }
1783
1784 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1785 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1786 .name = xname, \
1787 .index = xindex, \
1788 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1789 .info = snd_hdsp_info_spdif_sample_rate, \
1790 .get = snd_hdsp_get_spdif_sample_rate \
1791 }
1792
1793 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1794 {
1795 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1796 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1797
1798 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1799 uinfo->count = 1;
1800 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1801 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1802 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1803 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1804 return 0;
1805 }
1806
1807 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1808 {
1809 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1810
1811 switch (hdsp_spdif_sample_rate(hdsp)) {
1812 case 32000:
1813 ucontrol->value.enumerated.item[0] = 0;
1814 break;
1815 case 44100:
1816 ucontrol->value.enumerated.item[0] = 1;
1817 break;
1818 case 48000:
1819 ucontrol->value.enumerated.item[0] = 2;
1820 break;
1821 case 64000:
1822 ucontrol->value.enumerated.item[0] = 3;
1823 break;
1824 case 88200:
1825 ucontrol->value.enumerated.item[0] = 4;
1826 break;
1827 case 96000:
1828 ucontrol->value.enumerated.item[0] = 5;
1829 break;
1830 case 128000:
1831 ucontrol->value.enumerated.item[0] = 7;
1832 break;
1833 case 176400:
1834 ucontrol->value.enumerated.item[0] = 8;
1835 break;
1836 case 192000:
1837 ucontrol->value.enumerated.item[0] = 9;
1838 break;
1839 default:
1840 ucontrol->value.enumerated.item[0] = 6;
1841 }
1842 return 0;
1843 }
1844
1845 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1846 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1847 .name = xname, \
1848 .index = xindex, \
1849 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1850 .info = snd_hdsp_info_system_sample_rate, \
1851 .get = snd_hdsp_get_system_sample_rate \
1852 }
1853
1854 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1855 {
1856 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1857 uinfo->count = 1;
1858 return 0;
1859 }
1860
1861 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1862 {
1863 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1864
1865 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1866 return 0;
1867 }
1868
1869 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1870 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1871 .name = xname, \
1872 .index = xindex, \
1873 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1874 .info = snd_hdsp_info_autosync_sample_rate, \
1875 .get = snd_hdsp_get_autosync_sample_rate \
1876 }
1877
1878 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1879 {
1880 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1881 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1882 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1883 uinfo->count = 1;
1884 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1885 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1886 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1887 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1888 return 0;
1889 }
1890
1891 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1892 {
1893 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1894
1895 switch (hdsp_external_sample_rate(hdsp)) {
1896 case 32000:
1897 ucontrol->value.enumerated.item[0] = 0;
1898 break;
1899 case 44100:
1900 ucontrol->value.enumerated.item[0] = 1;
1901 break;
1902 case 48000:
1903 ucontrol->value.enumerated.item[0] = 2;
1904 break;
1905 case 64000:
1906 ucontrol->value.enumerated.item[0] = 3;
1907 break;
1908 case 88200:
1909 ucontrol->value.enumerated.item[0] = 4;
1910 break;
1911 case 96000:
1912 ucontrol->value.enumerated.item[0] = 5;
1913 break;
1914 case 128000:
1915 ucontrol->value.enumerated.item[0] = 7;
1916 break;
1917 case 176400:
1918 ucontrol->value.enumerated.item[0] = 8;
1919 break;
1920 case 192000:
1921 ucontrol->value.enumerated.item[0] = 9;
1922 break;
1923 default:
1924 ucontrol->value.enumerated.item[0] = 6;
1925 }
1926 return 0;
1927 }
1928
1929 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1930 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1931 .name = xname, \
1932 .index = xindex, \
1933 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1934 .info = snd_hdsp_info_system_clock_mode, \
1935 .get = snd_hdsp_get_system_clock_mode \
1936 }
1937
1938 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1939 {
1940 if (hdsp->control_register & HDSP_ClockModeMaster)
1941 return 0;
1942 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1943 return 0;
1944 return 1;
1945 }
1946
1947 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1948 {
1949 static char *texts[] = {"Master", "Slave" };
1950
1951 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1952 uinfo->count = 1;
1953 uinfo->value.enumerated.items = 2;
1954 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1955 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1956 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1957 return 0;
1958 }
1959
1960 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1961 {
1962 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1963
1964 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1965 return 0;
1966 }
1967
1968 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1969 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1970 .name = xname, \
1971 .index = xindex, \
1972 .info = snd_hdsp_info_clock_source, \
1973 .get = snd_hdsp_get_clock_source, \
1974 .put = snd_hdsp_put_clock_source \
1975 }
1976
1977 static int hdsp_clock_source(struct hdsp *hdsp)
1978 {
1979 if (hdsp->control_register & HDSP_ClockModeMaster) {
1980 switch (hdsp->system_sample_rate) {
1981 case 32000:
1982 return 1;
1983 case 44100:
1984 return 2;
1985 case 48000:
1986 return 3;
1987 case 64000:
1988 return 4;
1989 case 88200:
1990 return 5;
1991 case 96000:
1992 return 6;
1993 case 128000:
1994 return 7;
1995 case 176400:
1996 return 8;
1997 case 192000:
1998 return 9;
1999 default:
2000 return 3;
2001 }
2002 } else {
2003 return 0;
2004 }
2005 }
2006
2007 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
2008 {
2009 int rate;
2010 switch (mode) {
2011 case HDSP_CLOCK_SOURCE_AUTOSYNC:
2012 if (hdsp_external_sample_rate(hdsp) != 0) {
2013 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2014 hdsp->control_register &= ~HDSP_ClockModeMaster;
2015 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2016 return 0;
2017 }
2018 }
2019 return -1;
2020 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2021 rate = 32000;
2022 break;
2023 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2024 rate = 44100;
2025 break;
2026 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2027 rate = 48000;
2028 break;
2029 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2030 rate = 64000;
2031 break;
2032 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2033 rate = 88200;
2034 break;
2035 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2036 rate = 96000;
2037 break;
2038 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2039 rate = 128000;
2040 break;
2041 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2042 rate = 176400;
2043 break;
2044 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2045 rate = 192000;
2046 break;
2047 default:
2048 rate = 48000;
2049 }
2050 hdsp->control_register |= HDSP_ClockModeMaster;
2051 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2052 hdsp_set_rate(hdsp, rate, 1);
2053 return 0;
2054 }
2055
2056 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2057 {
2058 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2059 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2060
2061 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2062 uinfo->count = 1;
2063 if (hdsp->io_type == H9632)
2064 uinfo->value.enumerated.items = 10;
2065 else
2066 uinfo->value.enumerated.items = 7;
2067 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2068 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2069 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2070 return 0;
2071 }
2072
2073 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2074 {
2075 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2076
2077 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2078 return 0;
2079 }
2080
2081 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2082 {
2083 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2084 int change;
2085 int val;
2086
2087 if (!snd_hdsp_use_is_exclusive(hdsp))
2088 return -EBUSY;
2089 val = ucontrol->value.enumerated.item[0];
2090 if (val < 0) val = 0;
2091 if (hdsp->io_type == H9632) {
2092 if (val > 9)
2093 val = 9;
2094 } else {
2095 if (val > 6)
2096 val = 6;
2097 }
2098 spin_lock_irq(&hdsp->lock);
2099 if (val != hdsp_clock_source(hdsp))
2100 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2101 else
2102 change = 0;
2103 spin_unlock_irq(&hdsp->lock);
2104 return change;
2105 }
2106
2107 static int snd_hdsp_info_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2108 {
2109 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2110 uinfo->count = 1;
2111 uinfo->value.integer.min = 0;
2112 uinfo->value.integer.max = 1;
2113 return 0;
2114 }
2115
2116 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2117 {
2118 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2119
2120 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2121 return 0;
2122 }
2123
2124 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2125 {
2126 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2127 int change;
2128
2129 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2130 if (change)
2131 hdsp->clock_source_locked = ucontrol->value.integer.value[0];
2132 return change;
2133 }
2134
2135 #define HDSP_DA_GAIN(xname, xindex) \
2136 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2137 .name = xname, \
2138 .index = xindex, \
2139 .info = snd_hdsp_info_da_gain, \
2140 .get = snd_hdsp_get_da_gain, \
2141 .put = snd_hdsp_put_da_gain \
2142 }
2143
2144 static int hdsp_da_gain(struct hdsp *hdsp)
2145 {
2146 switch (hdsp->control_register & HDSP_DAGainMask) {
2147 case HDSP_DAGainHighGain:
2148 return 0;
2149 case HDSP_DAGainPlus4dBu:
2150 return 1;
2151 case HDSP_DAGainMinus10dBV:
2152 return 2;
2153 default:
2154 return 1;
2155 }
2156 }
2157
2158 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2159 {
2160 hdsp->control_register &= ~HDSP_DAGainMask;
2161 switch (mode) {
2162 case 0:
2163 hdsp->control_register |= HDSP_DAGainHighGain;
2164 break;
2165 case 1:
2166 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2167 break;
2168 case 2:
2169 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2170 break;
2171 default:
2172 return -1;
2173
2174 }
2175 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2176 return 0;
2177 }
2178
2179 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2180 {
2181 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2182
2183 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2184 uinfo->count = 1;
2185 uinfo->value.enumerated.items = 3;
2186 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2187 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2188 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2189 return 0;
2190 }
2191
2192 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2193 {
2194 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2195
2196 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2197 return 0;
2198 }
2199
2200 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2201 {
2202 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2203 int change;
2204 int val;
2205
2206 if (!snd_hdsp_use_is_exclusive(hdsp))
2207 return -EBUSY;
2208 val = ucontrol->value.enumerated.item[0];
2209 if (val < 0) val = 0;
2210 if (val > 2) val = 2;
2211 spin_lock_irq(&hdsp->lock);
2212 if (val != hdsp_da_gain(hdsp))
2213 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2214 else
2215 change = 0;
2216 spin_unlock_irq(&hdsp->lock);
2217 return change;
2218 }
2219
2220 #define HDSP_AD_GAIN(xname, xindex) \
2221 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2222 .name = xname, \
2223 .index = xindex, \
2224 .info = snd_hdsp_info_ad_gain, \
2225 .get = snd_hdsp_get_ad_gain, \
2226 .put = snd_hdsp_put_ad_gain \
2227 }
2228
2229 static int hdsp_ad_gain(struct hdsp *hdsp)
2230 {
2231 switch (hdsp->control_register & HDSP_ADGainMask) {
2232 case HDSP_ADGainMinus10dBV:
2233 return 0;
2234 case HDSP_ADGainPlus4dBu:
2235 return 1;
2236 case HDSP_ADGainLowGain:
2237 return 2;
2238 default:
2239 return 1;
2240 }
2241 }
2242
2243 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2244 {
2245 hdsp->control_register &= ~HDSP_ADGainMask;
2246 switch (mode) {
2247 case 0:
2248 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2249 break;
2250 case 1:
2251 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2252 break;
2253 case 2:
2254 hdsp->control_register |= HDSP_ADGainLowGain;
2255 break;
2256 default:
2257 return -1;
2258
2259 }
2260 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2261 return 0;
2262 }
2263
2264 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2265 {
2266 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2267
2268 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2269 uinfo->count = 1;
2270 uinfo->value.enumerated.items = 3;
2271 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2272 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2273 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2274 return 0;
2275 }
2276
2277 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2278 {
2279 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2280
2281 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2282 return 0;
2283 }
2284
2285 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2286 {
2287 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2288 int change;
2289 int val;
2290
2291 if (!snd_hdsp_use_is_exclusive(hdsp))
2292 return -EBUSY;
2293 val = ucontrol->value.enumerated.item[0];
2294 if (val < 0) val = 0;
2295 if (val > 2) val = 2;
2296 spin_lock_irq(&hdsp->lock);
2297 if (val != hdsp_ad_gain(hdsp))
2298 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2299 else
2300 change = 0;
2301 spin_unlock_irq(&hdsp->lock);
2302 return change;
2303 }
2304
2305 #define HDSP_PHONE_GAIN(xname, xindex) \
2306 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2307 .name = xname, \
2308 .index = xindex, \
2309 .info = snd_hdsp_info_phone_gain, \
2310 .get = snd_hdsp_get_phone_gain, \
2311 .put = snd_hdsp_put_phone_gain \
2312 }
2313
2314 static int hdsp_phone_gain(struct hdsp *hdsp)
2315 {
2316 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2317 case HDSP_PhoneGain0dB:
2318 return 0;
2319 case HDSP_PhoneGainMinus6dB:
2320 return 1;
2321 case HDSP_PhoneGainMinus12dB:
2322 return 2;
2323 default:
2324 return 0;
2325 }
2326 }
2327
2328 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2329 {
2330 hdsp->control_register &= ~HDSP_PhoneGainMask;
2331 switch (mode) {
2332 case 0:
2333 hdsp->control_register |= HDSP_PhoneGain0dB;
2334 break;
2335 case 1:
2336 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2337 break;
2338 case 2:
2339 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2340 break;
2341 default:
2342 return -1;
2343
2344 }
2345 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2346 return 0;
2347 }
2348
2349 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2350 {
2351 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2352
2353 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2354 uinfo->count = 1;
2355 uinfo->value.enumerated.items = 3;
2356 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2357 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2358 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2359 return 0;
2360 }
2361
2362 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2363 {
2364 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2365
2366 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2367 return 0;
2368 }
2369
2370 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2371 {
2372 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2373 int change;
2374 int val;
2375
2376 if (!snd_hdsp_use_is_exclusive(hdsp))
2377 return -EBUSY;
2378 val = ucontrol->value.enumerated.item[0];
2379 if (val < 0) val = 0;
2380 if (val > 2) val = 2;
2381 spin_lock_irq(&hdsp->lock);
2382 if (val != hdsp_phone_gain(hdsp))
2383 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2384 else
2385 change = 0;
2386 spin_unlock_irq(&hdsp->lock);
2387 return change;
2388 }
2389
2390 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2391 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2392 .name = xname, \
2393 .index = xindex, \
2394 .info = snd_hdsp_info_xlr_breakout_cable, \
2395 .get = snd_hdsp_get_xlr_breakout_cable, \
2396 .put = snd_hdsp_put_xlr_breakout_cable \
2397 }
2398
2399 static int hdsp_xlr_breakout_cable(struct hdsp *hdsp)
2400 {
2401 if (hdsp->control_register & HDSP_XLRBreakoutCable)
2402 return 1;
2403 return 0;
2404 }
2405
2406 static int hdsp_set_xlr_breakout_cable(struct hdsp *hdsp, int mode)
2407 {
2408 if (mode)
2409 hdsp->control_register |= HDSP_XLRBreakoutCable;
2410 else
2411 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2412 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2413 return 0;
2414 }
2415
2416 static int snd_hdsp_info_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2417 {
2418 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2419 uinfo->count = 1;
2420 uinfo->value.integer.min = 0;
2421 uinfo->value.integer.max = 1;
2422 return 0;
2423 }
2424
2425 static int snd_hdsp_get_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2426 {
2427 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2428
2429 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2430 return 0;
2431 }
2432
2433 static int snd_hdsp_put_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2434 {
2435 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2436 int change;
2437 int val;
2438
2439 if (!snd_hdsp_use_is_exclusive(hdsp))
2440 return -EBUSY;
2441 val = ucontrol->value.integer.value[0] & 1;
2442 spin_lock_irq(&hdsp->lock);
2443 change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2444 hdsp_set_xlr_breakout_cable(hdsp, val);
2445 spin_unlock_irq(&hdsp->lock);
2446 return change;
2447 }
2448
2449 /* (De)activates old RME Analog Extension Board
2450 These are connected to the internal ADAT connector
2451 Switching this on desactivates external ADAT
2452 */
2453 #define HDSP_AEB(xname, xindex) \
2454 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2455 .name = xname, \
2456 .index = xindex, \
2457 .info = snd_hdsp_info_aeb, \
2458 .get = snd_hdsp_get_aeb, \
2459 .put = snd_hdsp_put_aeb \
2460 }
2461
2462 static int hdsp_aeb(struct hdsp *hdsp)
2463 {
2464 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
2465 return 1;
2466 return 0;
2467 }
2468
2469 static int hdsp_set_aeb(struct hdsp *hdsp, int mode)
2470 {
2471 if (mode)
2472 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2473 else
2474 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2475 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2476 return 0;
2477 }
2478
2479 static int snd_hdsp_info_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2480 {
2481 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2482 uinfo->count = 1;
2483 uinfo->value.integer.min = 0;
2484 uinfo->value.integer.max = 1;
2485 return 0;
2486 }
2487
2488 static int snd_hdsp_get_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2489 {
2490 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2491
2492 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2493 return 0;
2494 }
2495
2496 static int snd_hdsp_put_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2497 {
2498 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2499 int change;
2500 int val;
2501
2502 if (!snd_hdsp_use_is_exclusive(hdsp))
2503 return -EBUSY;
2504 val = ucontrol->value.integer.value[0] & 1;
2505 spin_lock_irq(&hdsp->lock);
2506 change = (int)val != hdsp_aeb(hdsp);
2507 hdsp_set_aeb(hdsp, val);
2508 spin_unlock_irq(&hdsp->lock);
2509 return change;
2510 }
2511
2512 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2513 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2514 .name = xname, \
2515 .index = xindex, \
2516 .info = snd_hdsp_info_pref_sync_ref, \
2517 .get = snd_hdsp_get_pref_sync_ref, \
2518 .put = snd_hdsp_put_pref_sync_ref \
2519 }
2520
2521 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2522 {
2523 /* Notice that this looks at the requested sync source,
2524 not the one actually in use.
2525 */
2526
2527 switch (hdsp->control_register & HDSP_SyncRefMask) {
2528 case HDSP_SyncRef_ADAT1:
2529 return HDSP_SYNC_FROM_ADAT1;
2530 case HDSP_SyncRef_ADAT2:
2531 return HDSP_SYNC_FROM_ADAT2;
2532 case HDSP_SyncRef_ADAT3:
2533 return HDSP_SYNC_FROM_ADAT3;
2534 case HDSP_SyncRef_SPDIF:
2535 return HDSP_SYNC_FROM_SPDIF;
2536 case HDSP_SyncRef_WORD:
2537 return HDSP_SYNC_FROM_WORD;
2538 case HDSP_SyncRef_ADAT_SYNC:
2539 return HDSP_SYNC_FROM_ADAT_SYNC;
2540 default:
2541 return HDSP_SYNC_FROM_WORD;
2542 }
2543 return 0;
2544 }
2545
2546 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2547 {
2548 hdsp->control_register &= ~HDSP_SyncRefMask;
2549 switch (pref) {
2550 case HDSP_SYNC_FROM_ADAT1:
2551 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2552 break;
2553 case HDSP_SYNC_FROM_ADAT2:
2554 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2555 break;
2556 case HDSP_SYNC_FROM_ADAT3:
2557 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2558 break;
2559 case HDSP_SYNC_FROM_SPDIF:
2560 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2561 break;
2562 case HDSP_SYNC_FROM_WORD:
2563 hdsp->control_register |= HDSP_SyncRef_WORD;
2564 break;
2565 case HDSP_SYNC_FROM_ADAT_SYNC:
2566 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2567 break;
2568 default:
2569 return -1;
2570 }
2571 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2572 return 0;
2573 }
2574
2575 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2576 {
2577 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2578 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2579
2580 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2581 uinfo->count = 1;
2582
2583 switch (hdsp->io_type) {
2584 case Digiface:
2585 case H9652:
2586 uinfo->value.enumerated.items = 6;
2587 break;
2588 case Multiface:
2589 uinfo->value.enumerated.items = 4;
2590 break;
2591 case H9632:
2592 uinfo->value.enumerated.items = 3;
2593 break;
2594 default:
2595 uinfo->value.enumerated.items = 0;
2596 break;
2597 }
2598
2599 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2600 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2601 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2602 return 0;
2603 }
2604
2605 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2606 {
2607 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2608
2609 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2610 return 0;
2611 }
2612
2613 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2614 {
2615 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2616 int change, max;
2617 unsigned int val;
2618
2619 if (!snd_hdsp_use_is_exclusive(hdsp))
2620 return -EBUSY;
2621
2622 switch (hdsp->io_type) {
2623 case Digiface:
2624 case H9652:
2625 max = 6;
2626 break;
2627 case Multiface:
2628 max = 4;
2629 break;
2630 case H9632:
2631 max = 3;
2632 break;
2633 default:
2634 return -EIO;
2635 }
2636
2637 val = ucontrol->value.enumerated.item[0] % max;
2638 spin_lock_irq(&hdsp->lock);
2639 change = (int)val != hdsp_pref_sync_ref(hdsp);
2640 hdsp_set_pref_sync_ref(hdsp, val);
2641 spin_unlock_irq(&hdsp->lock);
2642 return change;
2643 }
2644
2645 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2646 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2647 .name = xname, \
2648 .index = xindex, \
2649 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2650 .info = snd_hdsp_info_autosync_ref, \
2651 .get = snd_hdsp_get_autosync_ref, \
2652 }
2653
2654 static int hdsp_autosync_ref(struct hdsp *hdsp)
2655 {
2656 /* This looks at the autosync selected sync reference */
2657 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2658
2659 switch (status2 & HDSP_SelSyncRefMask) {
2660 case HDSP_SelSyncRef_WORD:
2661 return HDSP_AUTOSYNC_FROM_WORD;
2662 case HDSP_SelSyncRef_ADAT_SYNC:
2663 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2664 case HDSP_SelSyncRef_SPDIF:
2665 return HDSP_AUTOSYNC_FROM_SPDIF;
2666 case HDSP_SelSyncRefMask:
2667 return HDSP_AUTOSYNC_FROM_NONE;
2668 case HDSP_SelSyncRef_ADAT1:
2669 return HDSP_AUTOSYNC_FROM_ADAT1;
2670 case HDSP_SelSyncRef_ADAT2:
2671 return HDSP_AUTOSYNC_FROM_ADAT2;
2672 case HDSP_SelSyncRef_ADAT3:
2673 return HDSP_AUTOSYNC_FROM_ADAT3;
2674 default:
2675 return HDSP_AUTOSYNC_FROM_WORD;
2676 }
2677 return 0;
2678 }
2679
2680 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2681 {
2682 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2683
2684 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2685 uinfo->count = 1;
2686 uinfo->value.enumerated.items = 7;
2687 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2688 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2689 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2690 return 0;
2691 }
2692
2693 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2694 {
2695 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2696
2697 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2698 return 0;
2699 }
2700
2701 #define HDSP_LINE_OUT(xname, xindex) \
2702 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2703 .name = xname, \
2704 .index = xindex, \
2705 .info = snd_hdsp_info_line_out, \
2706 .get = snd_hdsp_get_line_out, \
2707 .put = snd_hdsp_put_line_out \
2708 }
2709
2710 static int hdsp_line_out(struct hdsp *hdsp)
2711 {
2712 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2713 }
2714
2715 static int hdsp_set_line_output(struct hdsp *hdsp, int out)
2716 {
2717 if (out)
2718 hdsp->control_register |= HDSP_LineOut;
2719 else
2720 hdsp->control_register &= ~HDSP_LineOut;
2721 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2722 return 0;
2723 }
2724
2725 static int snd_hdsp_info_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2726 {
2727 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2728 uinfo->count = 1;
2729 uinfo->value.integer.min = 0;
2730 uinfo->value.integer.max = 1;
2731 return 0;
2732 }
2733
2734 static int snd_hdsp_get_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2735 {
2736 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2737
2738 spin_lock_irq(&hdsp->lock);
2739 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2740 spin_unlock_irq(&hdsp->lock);
2741 return 0;
2742 }
2743
2744 static int snd_hdsp_put_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2745 {
2746 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2747 int change;
2748 unsigned int val;
2749
2750 if (!snd_hdsp_use_is_exclusive(hdsp))
2751 return -EBUSY;
2752 val = ucontrol->value.integer.value[0] & 1;
2753 spin_lock_irq(&hdsp->lock);
2754 change = (int)val != hdsp_line_out(hdsp);
2755 hdsp_set_line_output(hdsp, val);
2756 spin_unlock_irq(&hdsp->lock);
2757 return change;
2758 }
2759
2760 #define HDSP_PRECISE_POINTER(xname, xindex) \
2761 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2762 .name = xname, \
2763 .index = xindex, \
2764 .info = snd_hdsp_info_precise_pointer, \
2765 .get = snd_hdsp_get_precise_pointer, \
2766 .put = snd_hdsp_put_precise_pointer \
2767 }
2768
2769 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2770 {
2771 if (precise)
2772 hdsp->precise_ptr = 1;
2773 else
2774 hdsp->precise_ptr = 0;
2775 return 0;
2776 }
2777
2778 static int snd_hdsp_info_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2779 {
2780 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2781 uinfo->count = 1;
2782 uinfo->value.integer.min = 0;
2783 uinfo->value.integer.max = 1;
2784 return 0;
2785 }
2786
2787 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2788 {
2789 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2790
2791 spin_lock_irq(&hdsp->lock);
2792 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2793 spin_unlock_irq(&hdsp->lock);
2794 return 0;
2795 }
2796
2797 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2798 {
2799 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2800 int change;
2801 unsigned int val;
2802
2803 if (!snd_hdsp_use_is_exclusive(hdsp))
2804 return -EBUSY;
2805 val = ucontrol->value.integer.value[0] & 1;
2806 spin_lock_irq(&hdsp->lock);
2807 change = (int)val != hdsp->precise_ptr;
2808 hdsp_set_precise_pointer(hdsp, val);
2809 spin_unlock_irq(&hdsp->lock);
2810 return change;
2811 }
2812
2813 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2814 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2815 .name = xname, \
2816 .index = xindex, \
2817 .info = snd_hdsp_info_use_midi_tasklet, \
2818 .get = snd_hdsp_get_use_midi_tasklet, \
2819 .put = snd_hdsp_put_use_midi_tasklet \
2820 }
2821
2822 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2823 {
2824 if (use_tasklet)
2825 hdsp->use_midi_tasklet = 1;
2826 else
2827 hdsp->use_midi_tasklet = 0;
2828 return 0;
2829 }
2830
2831 static int snd_hdsp_info_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2832 {
2833 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2834 uinfo->count = 1;
2835 uinfo->value.integer.min = 0;
2836 uinfo->value.integer.max = 1;
2837 return 0;
2838 }
2839
2840 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2841 {
2842 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2843
2844 spin_lock_irq(&hdsp->lock);
2845 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2846 spin_unlock_irq(&hdsp->lock);
2847 return 0;
2848 }
2849
2850 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2851 {
2852 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2853 int change;
2854 unsigned int val;
2855
2856 if (!snd_hdsp_use_is_exclusive(hdsp))
2857 return -EBUSY;
2858 val = ucontrol->value.integer.value[0] & 1;
2859 spin_lock_irq(&hdsp->lock);
2860 change = (int)val != hdsp->use_midi_tasklet;
2861 hdsp_set_use_midi_tasklet(hdsp, val);
2862 spin_unlock_irq(&hdsp->lock);
2863 return change;
2864 }
2865
2866 #define HDSP_MIXER(xname, xindex) \
2867 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2868 .name = xname, \
2869 .index = xindex, \
2870 .device = 0, \
2871 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2872 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2873 .info = snd_hdsp_info_mixer, \
2874 .get = snd_hdsp_get_mixer, \
2875 .put = snd_hdsp_put_mixer \
2876 }
2877
2878 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2879 {
2880 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2881 uinfo->count = 3;
2882 uinfo->value.integer.min = 0;
2883 uinfo->value.integer.max = 65536;
2884 uinfo->value.integer.step = 1;
2885 return 0;
2886 }
2887
2888 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2889 {
2890 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2891 int source;
2892 int destination;
2893 int addr;
2894
2895 source = ucontrol->value.integer.value[0];
2896 destination = ucontrol->value.integer.value[1];
2897
2898 if (source >= hdsp->max_channels)
2899 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2900 else
2901 addr = hdsp_input_to_output_key(hdsp,source, destination);
2902
2903 spin_lock_irq(&hdsp->lock);
2904 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2905 spin_unlock_irq(&hdsp->lock);
2906 return 0;
2907 }
2908
2909 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2910 {
2911 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2912 int change;
2913 int source;
2914 int destination;
2915 int gain;
2916 int addr;
2917
2918 if (!snd_hdsp_use_is_exclusive(hdsp))
2919 return -EBUSY;
2920
2921 source = ucontrol->value.integer.value[0];
2922 destination = ucontrol->value.integer.value[1];
2923
2924 if (source >= hdsp->max_channels)
2925 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2926 else
2927 addr = hdsp_input_to_output_key(hdsp,source, destination);
2928
2929 gain = ucontrol->value.integer.value[2];
2930
2931 spin_lock_irq(&hdsp->lock);
2932 change = gain != hdsp_read_gain(hdsp, addr);
2933 if (change)
2934 hdsp_write_gain(hdsp, addr, gain);
2935 spin_unlock_irq(&hdsp->lock);
2936 return change;
2937 }
2938
2939 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2940 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2941 .name = xname, \
2942 .index = xindex, \
2943 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2944 .info = snd_hdsp_info_sync_check, \
2945 .get = snd_hdsp_get_wc_sync_check \
2946 }
2947
2948 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2949 {
2950 static char *texts[] = {"No Lock", "Lock", "Sync" };
2951 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2952 uinfo->count = 1;
2953 uinfo->value.enumerated.items = 3;
2954 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2955 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2956 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2957 return 0;
2958 }
2959
2960 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2961 {
2962 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2963 if (status2 & HDSP_wc_lock) {
2964 if (status2 & HDSP_wc_sync)
2965 return 2;
2966 else
2967 return 1;
2968 } else
2969 return 0;
2970 return 0;
2971 }
2972
2973 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2974 {
2975 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2976
2977 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2978 return 0;
2979 }
2980
2981 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2982 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2983 .name = xname, \
2984 .index = xindex, \
2985 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2986 .info = snd_hdsp_info_sync_check, \
2987 .get = snd_hdsp_get_spdif_sync_check \
2988 }
2989
2990 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2991 {
2992 int status = hdsp_read(hdsp, HDSP_statusRegister);
2993 if (status & HDSP_SPDIFErrorFlag)
2994 return 0;
2995 else {
2996 if (status & HDSP_SPDIFSync)
2997 return 2;
2998 else
2999 return 1;
3000 }
3001 return 0;
3002 }
3003
3004 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3005 {
3006 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3007
3008 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
3009 return 0;
3010 }
3011
3012 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
3013 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3014 .name = xname, \
3015 .index = xindex, \
3016 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3017 .info = snd_hdsp_info_sync_check, \
3018 .get = snd_hdsp_get_adatsync_sync_check \
3019 }
3020
3021 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
3022 {
3023 int status = hdsp_read(hdsp, HDSP_statusRegister);
3024 if (status & HDSP_TimecodeLock) {
3025 if (status & HDSP_TimecodeSync)
3026 return 2;
3027 else
3028 return 1;
3029 } else
3030 return 0;
3031 }
3032
3033 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3034 {
3035 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3036
3037 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3038 return 0;
3039 }
3040
3041 #define HDSP_ADAT_SYNC_CHECK \
3042 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3043 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3044 .info = snd_hdsp_info_sync_check, \
3045 .get = snd_hdsp_get_adat_sync_check \
3046 }
3047
3048 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
3049 {
3050 int status = hdsp_read(hdsp, HDSP_statusRegister);
3051
3052 if (status & (HDSP_Lock0>>idx)) {
3053 if (status & (HDSP_Sync0>>idx))
3054 return 2;
3055 else
3056 return 1;
3057 } else
3058 return 0;
3059 }
3060
3061 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3062 {
3063 int offset;
3064 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3065
3066 offset = ucontrol->id.index - 1;
3067 snd_assert(offset >= 0);
3068
3069 switch (hdsp->io_type) {
3070 case Digiface:
3071 case H9652:
3072 if (offset >= 3)
3073 return -EINVAL;
3074 break;
3075 case Multiface:
3076 case H9632:
3077 if (offset >= 1)
3078 return -EINVAL;
3079 break;
3080 default:
3081 return -EIO;
3082 }
3083
3084 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3085 return 0;
3086 }
3087
3088 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
3089 HDSP_DA_GAIN("DA Gain", 0),
3090 HDSP_AD_GAIN("AD Gain", 0),
3091 HDSP_PHONE_GAIN("Phones Gain", 0),
3092 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0)
3093 };
3094
3095 static struct snd_kcontrol_new snd_hdsp_controls[] = {
3096 {
3097 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3098 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3099 .info = snd_hdsp_control_spdif_info,
3100 .get = snd_hdsp_control_spdif_get,
3101 .put = snd_hdsp_control_spdif_put,
3102 },
3103 {
3104 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3105 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3106 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3107 .info = snd_hdsp_control_spdif_stream_info,
3108 .get = snd_hdsp_control_spdif_stream_get,
3109 .put = snd_hdsp_control_spdif_stream_put,
3110 },
3111 {
3112 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3113 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3114 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3115 .info = snd_hdsp_control_spdif_mask_info,
3116 .get = snd_hdsp_control_spdif_mask_get,
3117 .private_value = IEC958_AES0_NONAUDIO |
3118 IEC958_AES0_PROFESSIONAL |
3119 IEC958_AES0_CON_EMPHASIS,
3120 },
3121 {
3122 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3123 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3124 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3125 .info = snd_hdsp_control_spdif_mask_info,
3126 .get = snd_hdsp_control_spdif_mask_get,
3127 .private_value = IEC958_AES0_NONAUDIO |
3128 IEC958_AES0_PROFESSIONAL |
3129 IEC958_AES0_PRO_EMPHASIS,
3130 },
3131 HDSP_MIXER("Mixer", 0),
3132 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3133 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3134 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3135 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3136 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3137 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3138 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3139 {
3140 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3141 .name = "Sample Clock Source Locking",
3142 .info = snd_hdsp_info_clock_source_lock,
3143 .get = snd_hdsp_get_clock_source_lock,
3144 .put = snd_hdsp_put_clock_source_lock,
3145 },
3146 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3147 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3148 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3149 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3150 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3151 /* 'External Rate' complies with the alsa control naming scheme */
3152 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3153 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3154 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3155 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3156 HDSP_LINE_OUT("Line Out", 0),
3157 HDSP_PRECISE_POINTER("Precise Pointer", 0),
3158 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
3159 };
3160
3161 static struct snd_kcontrol_new snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3162 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3163
3164 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3165 {
3166 unsigned int idx;
3167 int err;
3168 struct snd_kcontrol *kctl;
3169
3170 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3171 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3172 return err;
3173 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3174 hdsp->spdif_ctl = kctl;
3175 }
3176
3177 /* ADAT SyncCheck status */
3178 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3179 snd_hdsp_adat_sync_check.index = 1;
3180 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3181 return err;
3182 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3183 for (idx = 1; idx < 3; ++idx) {
3184 snd_hdsp_adat_sync_check.index = idx+1;
3185 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3186 return err;
3187 }
3188 }
3189
3190 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3191 if (hdsp->io_type == H9632) {
3192 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3193 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3194 return err;
3195 }
3196 }
3197
3198 /* AEB control for H96xx card */
3199 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3200 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3201 return err;
3202 }
3203
3204 return 0;
3205 }
3206
3207 /*------------------------------------------------------------
3208 /proc interface
3209 ------------------------------------------------------------*/
3210
3211 static void
3212 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3213 {
3214 struct hdsp *hdsp = (struct hdsp *) entry->private_data;
3215 unsigned int status;
3216 unsigned int status2;
3217 char *pref_sync_ref;
3218 char *autosync_ref;
3219 char *system_clock_mode;
3220 char *clock_source;
3221 int x;
3222
3223 if (hdsp_check_for_iobox (hdsp)) {
3224 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3225 return;
3226 }
3227
3228 if (hdsp_check_for_firmware(hdsp, 0)) {
3229 if (hdsp->state & HDSP_FirmwareCached) {
3230 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3231 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3232 return;
3233 }
3234 } else {
3235 int err = -EINVAL;
3236 #ifdef HDSP_FW_LOADER
3237 err = hdsp_request_fw_loader(hdsp);
3238 #endif
3239 if (err < 0) {
3240 snd_iprintf(buffer,
3241 "No firmware loaded nor cached, "
3242 "please upload firmware.\n");
3243 return;
3244 }
3245 }
3246 }
3247
3248 status = hdsp_read(hdsp, HDSP_statusRegister);
3249 status2 = hdsp_read(hdsp, HDSP_status2Register);
3250
3251 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3252 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3253 hdsp->capture_buffer, hdsp->playback_buffer);
3254 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3255 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3256 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3257 snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3258 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3259 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3260 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3261 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3262 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3263 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3264 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3265 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3266
3267 snd_iprintf(buffer, "\n");
3268
3269 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3270
3271 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3272 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3273 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3274 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3275
3276 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3277
3278 snd_iprintf(buffer, "\n");
3279
3280
3281 switch (hdsp_clock_source(hdsp)) {
3282 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3283 clock_source = "AutoSync";
3284 break;
3285 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3286 clock_source = "Internal 32 kHz";
3287 break;
3288 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3289 clock_source = "Internal 44.1 kHz";
3290 break;
3291 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3292 clock_source = "Internal 48 kHz";
3293 break;
3294 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3295 clock_source = "Internal 64 kHz";
3296 break;
3297 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3298 clock_source = "Internal 88.2 kHz";
3299 break;
3300 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3301 clock_source = "Internal 96 kHz";
3302 break;
3303 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3304 clock_source = "Internal 128 kHz";
3305 break;
3306 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3307 clock_source = "Internal 176.4 kHz";
3308 break;
3309 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3310 clock_source = "Internal 192 kHz";
3311 break;
3312 default:
3313 clock_source = "Error";
3314 }
3315 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3316
3317 if (hdsp_system_clock_mode(hdsp))
3318 system_clock_mode = "Slave";
3319 else
3320 system_clock_mode = "Master";
3321
3322 switch (hdsp_pref_sync_ref (hdsp)) {
3323 case HDSP_SYNC_FROM_WORD:
3324 pref_sync_ref = "Word Clock";
3325 break;
3326 case HDSP_SYNC_FROM_ADAT_SYNC:
3327 pref_sync_ref = "ADAT Sync";
3328 break;
3329 case HDSP_SYNC_FROM_SPDIF:
3330 pref_sync_ref = "SPDIF";
3331 break;
3332 case HDSP_SYNC_FROM_ADAT1:
3333 pref_sync_ref = "ADAT1";
3334 break;
3335 case HDSP_SYNC_FROM_ADAT2:
3336 pref_sync_ref = "ADAT2";
3337 break;
3338 case HDSP_SYNC_FROM_ADAT3:
3339 pref_sync_ref = "ADAT3";
3340 break;
3341 default:
3342 pref_sync_ref = "Word Clock";
3343 break;
3344 }
3345 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3346
3347 switch (hdsp_autosync_ref (hdsp)) {
3348 case HDSP_AUTOSYNC_FROM_WORD:
3349 autosync_ref = "Word Clock";
3350 break;
3351 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3352 autosync_ref = "ADAT Sync";
3353 break;
3354 case HDSP_AUTOSYNC_FROM_SPDIF:
3355 autosync_ref = "SPDIF";
3356 break;
3357 case HDSP_AUTOSYNC_FROM_NONE:
3358 autosync_ref = "None";
3359 break;
3360 case HDSP_AUTOSYNC_FROM_ADAT1:
3361 autosync_ref = "ADAT1";
3362 break;
3363 case HDSP_AUTOSYNC_FROM_ADAT2:
3364 autosync_ref = "ADAT2";
3365 break;
3366 case HDSP_AUTOSYNC_FROM_ADAT3:
3367 autosync_ref = "ADAT3";
3368 break;
3369 default:
3370 autosync_ref = "---";
3371 break;
3372 }
3373 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3374
3375 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3376
3377 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3378
3379 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3380 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3381
3382 snd_iprintf(buffer, "\n");
3383
3384 switch (hdsp_spdif_in(hdsp)) {
3385 case HDSP_SPDIFIN_OPTICAL:
3386 snd_iprintf(buffer, "IEC958 input: Optical\n");
3387 break;
3388 case HDSP_SPDIFIN_COAXIAL:
3389 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3390 break;
3391 case HDSP_SPDIFIN_INTERNAL:
3392 snd_iprintf(buffer, "IEC958 input: Internal\n");
3393 break;
3394 case HDSP_SPDIFIN_AES:
3395 snd_iprintf(buffer, "IEC958 input: AES\n");
3396 break;
3397 default:
3398 snd_iprintf(buffer, "IEC958 input: ???\n");
3399 break;
3400 }
3401
3402 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3403 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3404 else
3405 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3406
3407 if (hdsp->control_register & HDSP_SPDIFProfessional)
3408 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3409 else
3410 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3411
3412 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3413 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3414 else
3415 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3416
3417 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3418 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3419 else
3420 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3421 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0)
3422 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3423 else
3424 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3425
3426 snd_iprintf(buffer, "\n");
3427
3428 /* Sync Check */
3429 x = status & HDSP_Sync0;
3430 if (status & HDSP_Lock0)
3431 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3432 else
3433 snd_iprintf(buffer, "ADAT1: No Lock\n");
3434
3435 switch (hdsp->io_type) {
3436 case Digiface:
3437 case H9652:
3438 x = status & HDSP_Sync1;
3439 if (status & HDSP_Lock1)
3440 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3441 else
3442 snd_iprintf(buffer, "ADAT2: No Lock\n");
3443 x = status & HDSP_Sync2;
3444 if (status & HDSP_Lock2)
3445 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3446 else
3447 snd_iprintf(buffer, "ADAT3: No Lock\n");
3448 break;
3449 default:
3450 /* relax */
3451 break;
3452 }
3453
3454 x = status & HDSP_SPDIFSync;
3455 if (status & HDSP_SPDIFErrorFlag)
3456 snd_iprintf (buffer, "SPDIF: No Lock\n");
3457 else
3458 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3459
3460 x = status2 & HDSP_wc_sync;
3461 if (status2 & HDSP_wc_lock)
3462 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3463 else
3464 snd_iprintf (buffer, "Word Clock: No Lock\n");
3465
3466 x = status & HDSP_TimecodeSync;
3467 if (status & HDSP_TimecodeLock)
3468 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3469 else
3470 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3471
3472 snd_iprintf(buffer, "\n");
3473
3474 /* Informations about H9632 specific controls */
3475 if (hdsp->io_type == H9632) {
3476 char *tmp;
3477
3478 switch (hdsp_ad_gain(hdsp)) {
3479 case 0:
3480 tmp = "-10 dBV";
3481 break;
3482 case 1:
3483 tmp = "+4 dBu";
3484 break;
3485 default:
3486 tmp = "Lo Gain";
3487 break;
3488 }
3489 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3490
3491 switch (hdsp_da_gain(hdsp)) {
3492 case 0:
3493 tmp = "Hi Gain";
3494 break;
3495 case 1:
3496 tmp = "+4 dBu";
3497 break;
3498 default:
3499 tmp = "-10 dBV";
3500 break;
3501 }
3502 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3503
3504 switch (hdsp_phone_gain(hdsp)) {
3505 case 0:
3506 tmp = "0 dB";
3507 break;
3508 case 1:
3509 tmp = "-6 dB";
3510 break;
3511 default:
3512 tmp = "-12 dB";
3513 break;
3514 }
3515 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3516
3517 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3518
3519 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3520 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3521 else
3522 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3523 snd_iprintf(buffer, "\n");
3524 }
3525
3526 }
3527
3528 static void __devinit snd_hdsp_proc_init(struct hdsp *hdsp)
3529 {
3530 struct snd_info_entry *entry;
3531
3532 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3533 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3534 }
3535
3536 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3537 {
3538 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3539 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3540 }
3541
3542 static int __devinit snd_hdsp_initialize_memory(struct hdsp *hdsp)
3543 {
3544 unsigned long pb_bus, cb_bus;
3545
3546 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3547 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3548 if (hdsp->capture_dma_buf.area)
3549 snd_dma_free_pages(&hdsp->capture_dma_buf);
3550 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3551 return -ENOMEM;
3552 }
3553
3554 /* Align to bus-space 64K boundary */
3555
3556 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3557 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3558
3559 /* Tell the card where it is */
3560
3561 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3562 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3563
3564 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3565 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3566
3567 return 0;
3568 }
3569
3570 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3571 {
3572 unsigned int i;
3573
3574 /* ASSUMPTION: hdsp->lock is either held, or
3575 there is no need to hold it (e.g. during module
3576 initalization).
3577 */
3578
3579 /* set defaults:
3580
3581 SPDIF Input via Coax
3582 Master clock mode
3583 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3584 which implies 2 4096 sample, 32Kbyte periods).
3585 Enable line out.
3586 */
3587
3588 hdsp->control_register = HDSP_ClockModeMaster |
3589 HDSP_SPDIFInputCoaxial |
3590 hdsp_encode_latency(7) |
3591 HDSP_LineOut;
3592
3593
3594 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3595
3596 #ifdef SNDRV_BIG_ENDIAN
3597 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3598 #else
3599 hdsp->control2_register = 0;
3600 #endif
3601 if (hdsp->io_type == H9652)
3602 snd_hdsp_9652_enable_mixer (hdsp);
3603 else
3604 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3605
3606 hdsp_reset_hw_pointer(hdsp);
3607 hdsp_compute_period_size(hdsp);
3608
3609 /* silence everything */
3610
3611 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3612 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3613
3614 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3615 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3616 return -EIO;
3617 }
3618
3619 /* H9632 specific defaults */
3620 if (hdsp->io_type == H9632) {
3621 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3622 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3623 }
3624
3625 /* set a default rate so that the channel map is set up.
3626 */
3627
3628 hdsp_set_rate(hdsp, 48000, 1);
3629
3630 return 0;
3631 }
3632
3633 static void hdsp_midi_tasklet(unsigned long arg)
3634 {
3635 struct hdsp *hdsp = (struct hdsp *)arg;
3636
3637 if (hdsp->midi[0].pending)
3638 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3639 if (hdsp->midi[1].pending)
3640 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3641 }
3642
3643 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3644 {
3645 struct hdsp *hdsp = (struct hdsp *) dev_id;
3646 unsigned int status;
3647 int audio;
3648 int midi0;
3649 int midi1;
3650 unsigned int midi0status;
3651 unsigned int midi1status;
3652 int schedule = 0;
3653
3654 status = hdsp_read(hdsp, HDSP_statusRegister);
3655
3656 audio = status & HDSP_audioIRQPending;
3657 midi0 = status & HDSP_midi0IRQPending;
3658 midi1 = status & HDSP_midi1IRQPending;
3659
3660 if (!audio && !midi0 && !midi1)
3661 return IRQ_NONE;
3662
3663 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3664
3665 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3666 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3667
3668 if (audio) {
3669 if (hdsp->capture_substream)
3670 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3671
3672 if (hdsp->playback_substream)
3673 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3674 }
3675
3676 if (midi0 && midi0status) {
3677 if (hdsp->use_midi_tasklet) {
3678 /* we disable interrupts for this input until processing is done */
3679 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3680 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3681 hdsp->midi[0].pending = 1;
3682 schedule = 1;
3683 } else {
3684 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3685 }
3686 }
3687 if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) {
3688 if (hdsp->use_midi_tasklet) {
3689 /* we disable interrupts for this input until processing is done */
3690 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3691 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3692 hdsp->midi[1].pending = 1;
3693 schedule = 1;
3694 } else {
3695 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3696 }
3697 }
3698 if (hdsp->use_midi_tasklet && schedule)
3699 tasklet_hi_schedule(&hdsp->midi_tasklet);
3700 return IRQ_HANDLED;
3701 }
3702
3703 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3704 {
3705 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3706 return hdsp_hw_pointer(hdsp);
3707 }
3708
3709 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3710 int stream,
3711 int channel)
3712
3713 {
3714 int mapped_channel;
3715
3716 snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3717
3718 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3719 return NULL;
3720
3721 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3722 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3723 else
3724 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3725 }
3726
3727 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
3728 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3729 {
3730 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3731 char *channel_buf;
3732
3733 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3734
3735 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3736 snd_assert(channel_buf != NULL, return -EIO);
3737 if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3738 return -EFAULT;
3739 return count;
3740 }
3741
3742 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
3743 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3744 {
3745 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3746 char *channel_buf;
3747
3748 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3749
3750 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3751 snd_assert(channel_buf != NULL, return -EIO);
3752 if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3753 return -EFAULT;
3754 return count;
3755 }
3756
3757 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
3758 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3759 {
3760 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3761 char *channel_buf;
3762
3763 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3764 snd_assert(channel_buf != NULL, return -EIO);
3765 memset(channel_buf + pos * 4, 0, count * 4);
3766 return count;
3767 }
3768
3769 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3770 {
3771 struct snd_pcm_runtime *runtime = substream->runtime;
3772 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3773 struct snd_pcm_substream *other;
3774 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3775 other = hdsp->capture_substream;
3776 else
3777 other = hdsp->playback_substream;
3778 if (hdsp->running)
3779 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3780 else
3781 runtime->status->hw_ptr = 0;
3782 if (other) {
3783 struct list_head *pos;
3784 struct snd_pcm_substream *s;
3785 struct snd_pcm_runtime *oruntime = other->runtime;
3786 snd_pcm_group_for_each(pos, substream) {
3787 s = snd_pcm_group_substream_entry(pos);
3788 if (s == other) {
3789 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3790 break;
3791 }
3792 }
3793 }
3794 return 0;
3795 }
3796
3797 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3798 struct snd_pcm_hw_params *params)
3799 {
3800 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3801 int err;
3802 pid_t this_pid;
3803 pid_t other_pid;
3804
3805 if (hdsp_check_for_iobox (hdsp))
3806 return -EIO;
3807
3808 if (hdsp_check_for_firmware(hdsp, 1))
3809 return -EIO;
3810
3811 spin_lock_irq(&hdsp->lock);
3812
3813 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3814 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3815 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3816 this_pid = hdsp->playback_pid;
3817 other_pid = hdsp->capture_pid;
3818 } else {
3819 this_pid = hdsp->capture_pid;
3820 other_pid = hdsp->playback_pid;
3821 }
3822
3823 if ((other_pid > 0) && (this_pid != other_pid)) {
3824
3825 /* The other stream is open, and not by the same
3826 task as this one. Make sure that the parameters
3827 that matter are the same.
3828 */
3829
3830 if (params_rate(params) != hdsp->system_sample_rate) {
3831 spin_unlock_irq(&hdsp->lock);
3832 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3833 return -EBUSY;
3834 }
3835
3836 if (params_period_size(params) != hdsp->period_bytes / 4) {
3837 spin_unlock_irq(&hdsp->lock);
3838 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3839 return -EBUSY;
3840 }
3841
3842 /* We're fine. */
3843
3844 spin_unlock_irq(&hdsp->lock);
3845 return 0;
3846
3847 } else {
3848 spin_unlock_irq(&hdsp->lock);
3849 }
3850
3851 /* how to make sure that the rate matches an externally-set one ?
3852 */
3853
3854 spin_lock_irq(&hdsp->lock);
3855 if (! hdsp->clock_source_locked) {
3856 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3857 spin_unlock_irq(&hdsp->lock);
3858 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3859 return err;
3860 }
3861 }
3862 spin_unlock_irq(&hdsp->lock);
3863
3864 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3865 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3866 return err;
3867 }
3868
3869 return 0;
3870 }
3871
3872 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
3873 struct snd_pcm_channel_info *info)
3874 {
3875 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3876 int mapped_channel;
3877
3878 snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3879
3880 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0)
3881 return -EINVAL;
3882
3883 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
3884 info->first = 0;
3885 info->step = 32;
3886 return 0;
3887 }
3888
3889 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
3890 unsigned int cmd, void *arg)
3891 {
3892 switch (cmd) {
3893 case SNDRV_PCM_IOCTL1_RESET:
3894 return snd_hdsp_reset(substream);
3895 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3896 return snd_hdsp_channel_info(substream, arg);
3897 default:
3898 break;
3899 }
3900
3901 return snd_pcm_lib_ioctl(substream, cmd, arg);
3902 }
3903
3904 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
3905 {
3906 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3907 struct snd_pcm_substream *other;
3908 int running;
3909
3910 if (hdsp_check_for_iobox (hdsp))
3911 return -EIO;
3912
3913 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
3914 return -EIO;
3915
3916 spin_lock(&hdsp->lock);
3917 running = hdsp->running;
3918 switch (cmd) {
3919 case SNDRV_PCM_TRIGGER_START:
3920 running |= 1 << substream->stream;
3921 break;
3922 case SNDRV_PCM_TRIGGER_STOP:
3923 running &= ~(1 << substream->stream);
3924 break;
3925 default:
3926 snd_BUG();
3927 spin_unlock(&hdsp->lock);
3928 return -EINVAL;
3929 }
3930 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3931 other = hdsp->capture_substream;
3932 else
3933 other = hdsp->playback_substream;
3934
3935 if (other) {
3936 struct list_head *pos;
3937 struct snd_pcm_substream *s;
3938 snd_pcm_group_for_each(pos, substream) {
3939 s = snd_pcm_group_substream_entry(pos);
3940 if (s == other) {
3941 snd_pcm_trigger_done(s, substream);
3942 if (cmd == SNDRV_PCM_TRIGGER_START)
3943 running |= 1 << s->stream;
3944 else
3945 running &= ~(1 << s->stream);
3946 goto _ok;
3947 }
3948 }
3949 if (cmd == SNDRV_PCM_TRIGGER_START) {
3950 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
3951 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3952 hdsp_silence_playback(hdsp);
3953 } else {
3954 if (running &&
3955 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3956 hdsp_silence_playback(hdsp);
3957 }
3958 } else {
3959 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3960 hdsp_silence_playback(hdsp);
3961 }
3962 _ok:
3963 snd_pcm_trigger_done(substream, substream);
3964 if (!hdsp->running && running)
3965 hdsp_start_audio(hdsp);
3966 else if (hdsp->running && !running)
3967 hdsp_stop_audio(hdsp);
3968 hdsp->running = running;
3969 spin_unlock(&hdsp->lock);
3970
3971 return 0;
3972 }
3973
3974 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
3975 {
3976 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3977 int result = 0;
3978
3979 if (hdsp_check_for_iobox (hdsp))
3980 return -EIO;
3981
3982 if (hdsp_check_for_firmware(hdsp, 1))
3983 return -EIO;
3984
3985 spin_lock_irq(&hdsp->lock);
3986 if (!hdsp->running)
3987 hdsp_reset_hw_pointer(hdsp);
3988 spin_unlock_irq(&hdsp->lock);
3989 return result;
3990 }
3991
3992 static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
3993 {
3994 .info = (SNDRV_PCM_INFO_MMAP |
3995 SNDRV_PCM_INFO_MMAP_VALID |
3996 SNDRV_PCM_INFO_NONINTERLEAVED |
3997 SNDRV_PCM_INFO_SYNC_START |
3998 SNDRV_PCM_INFO_DOUBLE),
3999 #ifdef SNDRV_BIG_ENDIAN
4000 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4001 #else
4002 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4003 #endif
4004 .rates = (SNDRV_PCM_RATE_32000 |
4005 SNDRV_PCM_RATE_44100 |
4006 SNDRV_PCM_RATE_48000 |
4007 SNDRV_PCM_RATE_64000 |
4008 SNDRV_PCM_RATE_88200 |
4009 SNDRV_PCM_RATE_96000),
4010 .rate_min = 32000,
4011 .rate_max = 96000,
4012 .channels_min = 14,
4013 .channels_max = HDSP_MAX_CHANNELS,
4014 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4015 .period_bytes_min = (64 * 4) * 10,
4016 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4017 .periods_min = 2,
4018 .periods_max = 2,
4019 .fifo_size = 0
4020 };
4021
4022 static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4023 {
4024 .info = (SNDRV_PCM_INFO_MMAP |
4025 SNDRV_PCM_INFO_MMAP_VALID |
4026 SNDRV_PCM_INFO_NONINTERLEAVED |
4027 SNDRV_PCM_INFO_SYNC_START),
4028 #ifdef SNDRV_BIG_ENDIAN
4029 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4030 #else
4031 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4032 #endif
4033 .rates = (SNDRV_PCM_RATE_32000 |
4034 SNDRV_PCM_RATE_44100 |
4035 SNDRV_PCM_RATE_48000 |
4036 SNDRV_PCM_RATE_64000 |
4037 SNDRV_PCM_RATE_88200 |
4038 SNDRV_PCM_RATE_96000),
4039 .rate_min = 32000,
4040 .rate_max = 96000,
4041 .channels_min = 14,
4042 .channels_max = HDSP_MAX_CHANNELS,
4043 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4044 .period_bytes_min = (64 * 4) * 10,
4045 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4046 .periods_min = 2,
4047 .periods_max = 2,
4048 .fifo_size = 0
4049 };
4050
4051 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4052
4053 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4054 .count = ARRAY_SIZE(hdsp_period_sizes),
4055 .list = hdsp_period_sizes,
4056 .mask = 0
4057 };
4058
4059 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4060
4061 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4062 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4063 .list = hdsp_9632_sample_rates,
4064 .mask = 0
4065 };
4066
4067 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4068 struct snd_pcm_hw_rule *rule)
4069 {
4070 struct hdsp *hdsp = rule->private;
4071 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4072 if (hdsp->io_type == H9632) {
4073 unsigned int list[3];
4074 list[0] = hdsp->qs_in_channels;
4075 list[1] = hdsp->ds_in_channels;
4076 list[2] = hdsp->ss_in_channels;
4077 return snd_interval_list(c, 3, list, 0);
4078 } else {
4079 unsigned int list[2];
4080 list[0] = hdsp->ds_in_channels;
4081 list[1] = hdsp->ss_in_channels;
4082 return snd_interval_list(c, 2, list, 0);
4083 }
4084 }
4085
4086 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4087 struct snd_pcm_hw_rule *rule)
4088 {
4089 unsigned int list[3];
4090 struct hdsp *hdsp = rule->private;
4091 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4092 if (hdsp->io_type == H9632) {
4093 list[0] = hdsp->qs_out_channels;
4094 list[1] = hdsp->ds_out_channels;
4095 list[2] = hdsp->ss_out_channels;
4096 return snd_interval_list(c, 3, list, 0);
4097 } else {
4098 list[0] = hdsp->ds_out_channels;
4099 list[1] = hdsp->ss_out_channels;
4100 }
4101 return snd_interval_list(c, 2, list, 0);
4102 }
4103
4104 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4105 struct snd_pcm_hw_rule *rule)
4106 {
4107 struct hdsp *hdsp = rule->private;
4108 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4109 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4110 if (r->min > 96000 && hdsp->io_type == H9632) {
4111 struct snd_interval t = {
4112 .min = hdsp->qs_in_channels,
4113 .max = hdsp->qs_in_channels,
4114 .integer = 1,
4115 };
4116 return snd_interval_refine(c, &t);
4117 } else if (r->min > 48000 && r->max <= 96000) {
4118 struct snd_interval t = {
4119 .min = hdsp->ds_in_channels,
4120 .max = hdsp->ds_in_channels,
4121 .integer = 1,
4122 };
4123 return snd_interval_refine(c, &t);
4124 } else if (r->max < 64000) {
4125 struct snd_interval t = {
4126 .min = hdsp->ss_in_channels,
4127 .max = hdsp->ss_in_channels,
4128 .integer = 1,
4129 };
4130 return snd_interval_refine(c, &t);
4131 }
4132 return 0;
4133 }
4134
4135 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4136 struct snd_pcm_hw_rule *rule)
4137 {
4138 struct hdsp *hdsp = rule->private;
4139 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4140 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4141 if (r->min > 96000 && hdsp->io_type == H9632) {
4142 struct snd_interval t = {
4143 .min = hdsp->qs_out_channels,
4144 .max = hdsp->qs_out_channels,
4145 .integer = 1,
4146 };
4147 return snd_interval_refine(c, &t);
4148 } else if (r->min > 48000 && r->max <= 96000) {
4149 struct snd_interval t = {
4150 .min = hdsp->ds_out_channels,
4151 .max = hdsp->ds_out_channels,
4152 .integer = 1,
4153 };
4154 return snd_interval_refine(c, &t);
4155 } else if (r->max < 64000) {
4156 struct snd_interval t = {
4157 .min = hdsp->ss_out_channels,
4158 .max = hdsp->ss_out_channels,
4159 .integer = 1,
4160 };
4161 return snd_interval_refine(c, &t);
4162 }
4163 return 0;
4164 }
4165
4166 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4167 struct snd_pcm_hw_rule *rule)
4168 {
4169 struct hdsp *hdsp = rule->private;
4170 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4171 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4172 if (c->min >= hdsp->ss_out_channels) {
4173 struct snd_interval t = {
4174 .min = 32000,
4175 .max = 48000,
4176 .integer = 1,
4177 };
4178 return snd_interval_refine(r, &t);
4179 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4180 struct snd_interval t = {
4181 .min = 128000,
4182 .max = 192000,
4183 .integer = 1,
4184 };
4185 return snd_interval_refine(r, &t);
4186 } else if (c->max <= hdsp->ds_out_channels) {
4187 struct snd_interval t = {
4188 .min = 64000,
4189 .max = 96000,
4190 .integer = 1,
4191 };
4192 return snd_interval_refine(r, &t);
4193 }
4194 return 0;
4195 }
4196
4197 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4198 struct snd_pcm_hw_rule *rule)
4199 {
4200 struct hdsp *hdsp = rule->private;
4201 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4202 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4203 if (c->min >= hdsp->ss_in_channels) {
4204 struct snd_interval t = {
4205 .min = 32000,
4206 .max = 48000,
4207 .integer = 1,
4208 };
4209 return snd_interval_refine(r, &t);
4210 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4211 struct snd_interval t = {
4212 .min = 128000,
4213 .max = 192000,
4214 .integer = 1,
4215 };
4216 return snd_interval_refine(r, &t);
4217 } else if (c->max <= hdsp->ds_in_channels) {
4218 struct snd_interval t = {
4219 .min = 64000,
4220 .max = 96000,
4221 .integer = 1,
4222 };
4223 return snd_interval_refine(r, &t);
4224 }
4225 return 0;
4226 }
4227
4228 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4229 {
4230 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4231 struct snd_pcm_runtime *runtime = substream->runtime;
4232
4233 if (hdsp_check_for_iobox (hdsp))
4234 return -EIO;
4235
4236 if (hdsp_check_for_firmware(hdsp, 1))
4237 return -EIO;
4238
4239 spin_lock_irq(&hdsp->lock);
4240
4241 snd_pcm_set_sync(substream);
4242
4243 runtime->hw = snd_hdsp_playback_subinfo;
4244 runtime->dma_area = hdsp->playback_buffer;
4245 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4246
4247 hdsp->playback_pid = current->pid;
4248 hdsp->playback_substream = substream;
4249
4250 spin_unlock_irq(&hdsp->lock);
4251
4252 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4253 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4254 if (hdsp->clock_source_locked) {
4255 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4256 } else if (hdsp->io_type == H9632) {
4257 runtime->hw.rate_max = 192000;
4258 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4259 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4260 }
4261 if (hdsp->io_type == H9632) {
4262 runtime->hw.channels_min = hdsp->qs_out_channels;
4263 runtime->hw.channels_max = hdsp->ss_out_channels;
4264 }
4265
4266 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4267 snd_hdsp_hw_rule_out_channels, hdsp,
4268 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4269 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4270 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4271 SNDRV_PCM_HW_PARAM_RATE, -1);
4272 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4273 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4274 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4275
4276 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4277 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4278 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4279 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4280 return 0;
4281 }
4282
4283 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4284 {
4285 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4286
4287 spin_lock_irq(&hdsp->lock);
4288
4289 hdsp->playback_pid = -1;
4290 hdsp->playback_substream = NULL;
4291
4292 spin_unlock_irq(&hdsp->lock);
4293
4294 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4295 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4296 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4297 return 0;
4298 }
4299
4300
4301 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4302 {
4303 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4304 struct snd_pcm_runtime *runtime = substream->runtime;
4305
4306 if (hdsp_check_for_iobox (hdsp))
4307 return -EIO;
4308
4309 if (hdsp_check_for_firmware(hdsp, 1))
4310 return -EIO;
4311
4312 spin_lock_irq(&hdsp->lock);
4313
4314 snd_pcm_set_sync(substream);
4315
4316 runtime->hw = snd_hdsp_capture_subinfo;
4317 runtime->dma_area = hdsp->capture_buffer;
4318 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4319
4320 hdsp->capture_pid = current->pid;
4321 hdsp->capture_substream = substream;
4322
4323 spin_unlock_irq(&hdsp->lock);
4324
4325 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4326 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4327 if (hdsp->io_type == H9632) {
4328 runtime->hw.channels_min = hdsp->qs_in_channels;
4329 runtime->hw.channels_max = hdsp->ss_in_channels;
4330 runtime->hw.rate_max = 192000;
4331 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4332 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4333 }
4334 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4335 snd_hdsp_hw_rule_in_channels, hdsp,
4336 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4337 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4338 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4339 SNDRV_PCM_HW_PARAM_RATE, -1);
4340 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4341 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4342 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4343 return 0;
4344 }
4345
4346 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4347 {
4348 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4349
4350 spin_lock_irq(&hdsp->lock);
4351
4352 hdsp->capture_pid = -1;
4353 hdsp->capture_substream = NULL;
4354
4355 spin_unlock_irq(&hdsp->lock);
4356 return 0;
4357 }
4358
4359 static int snd_hdsp_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
4360 {
4361 /* we have nothing to initialize but the call is required */
4362 return 0;
4363 }
4364
4365
4366 /* helper functions for copying meter values */
4367 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4368 {
4369 u32 val = readl(src);
4370 return copy_to_user(dest, &val, 4);
4371 }
4372
4373 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4374 {
4375 u32 rms_low, rms_high;
4376 u64 rms;
4377 rms_low = readl(src_low);
4378 rms_high = readl(src_high);
4379 rms = ((u64)rms_high << 32) | rms_low;
4380 return copy_to_user(dest, &rms, 8);
4381 }
4382
4383 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4384 {
4385 u32 rms_low, rms_high;
4386 u64 rms;
4387 rms_low = readl(src_low) & 0xffffff00;
4388 rms_high = readl(src_high) & 0xffffff00;
4389 rms = ((u64)rms_high << 32) | rms_low;
4390 return copy_to_user(dest, &rms, 8);
4391 }
4392
4393 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4394 {
4395 int doublespeed = 0;
4396 int i, j, channels, ofs;
4397
4398 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4399 doublespeed = 1;
4400 channels = doublespeed ? 14 : 26;
4401 for (i = 0, j = 0; i < 26; ++i) {
4402 if (doublespeed && (i & 4))
4403 continue;
4404 ofs = HDSP_9652_peakBase - j * 4;
4405 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4406 return -EFAULT;
4407 ofs -= channels * 4;
4408 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4409 return -EFAULT;
4410 ofs -= channels * 4;
4411 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4412 return -EFAULT;
4413 ofs = HDSP_9652_rmsBase + j * 8;
4414 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4415 hdsp->iobase + ofs + 4))
4416 return -EFAULT;
4417 ofs += channels * 8;
4418 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4419 hdsp->iobase + ofs + 4))
4420 return -EFAULT;
4421 ofs += channels * 8;
4422 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4423 hdsp->iobase + ofs + 4))
4424 return -EFAULT;
4425 j++;
4426 }
4427 return 0;
4428 }
4429
4430 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4431 {
4432 int i, j;
4433 struct hdsp_9632_meters __iomem *m;
4434 int doublespeed = 0;
4435
4436 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4437 doublespeed = 1;
4438 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4439 for (i = 0, j = 0; i < 16; ++i, ++j) {
4440 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4441 return -EFAULT;
4442 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4443 return -EFAULT;
4444 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4445 return -EFAULT;
4446 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4447 &m->input_rms_high[j]))
4448 return -EFAULT;
4449 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4450 &m->playback_rms_high[j]))
4451 return -EFAULT;
4452 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4453 &m->output_rms_high[j]))
4454 return -EFAULT;
4455 if (doublespeed && i == 3) i += 4;
4456 }
4457 return 0;
4458 }
4459
4460 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4461 {
4462 int i;
4463
4464 for (i = 0; i < 26; i++) {
4465 if (copy_u32_le(&peak_rms->playback_peaks[i],
4466 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4467 return -EFAULT;
4468 if (copy_u32_le(&peak_rms->input_peaks[i],
4469 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4470 return -EFAULT;
4471 }
4472 for (i = 0; i < 28; i++) {
4473 if (copy_u32_le(&peak_rms->output_peaks[i],
4474 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4475 return -EFAULT;
4476 }
4477 for (i = 0; i < 26; ++i) {
4478 if (copy_u64_le(&peak_rms->playback_rms[i],
4479 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4480 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4481 return -EFAULT;
4482 if (copy_u64_le(&peak_rms->input_rms[i],
4483 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4484 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4485 return -EFAULT;
4486 }
4487 return 0;
4488 }
4489
4490 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4491 {
4492 struct hdsp *hdsp = (struct hdsp *)hw->private_data;
4493 void __user *argp = (void __user *)arg;
4494
4495 switch (cmd) {
4496 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4497 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4498
4499 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4500 snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n");
4501 return -EINVAL;
4502 }
4503
4504 switch (hdsp->io_type) {
4505 case H9652:
4506 return hdsp_9652_get_peak(hdsp, peak_rms);
4507 case H9632:
4508 return hdsp_9632_get_peak(hdsp, peak_rms);
4509 default:
4510 return hdsp_get_peak(hdsp, peak_rms);
4511 }
4512 }
4513 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4514 struct hdsp_config_info info;
4515 unsigned long flags;
4516 int i;
4517
4518 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4519 snd_printk(KERN_ERR "Hammerfall-DSP: Firmware needs to be uploaded to the card.\n");
4520 return -EINVAL;
4521 }
4522 spin_lock_irqsave(&hdsp->lock, flags);
4523 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4524 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4525 if (hdsp->io_type != H9632)
4526 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4527 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4528 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i)
4529 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4530 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4531 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4532 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4533 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4534 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4535 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4536 info.system_sample_rate = hdsp->system_sample_rate;
4537 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4538 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4539 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4540 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4541 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4542 if (hdsp->io_type == H9632) {
4543 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4544 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4545 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4546 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4547
4548 }
4549 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4550 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4551 spin_unlock_irqrestore(&hdsp->lock, flags);
4552 if (copy_to_user(argp, &info, sizeof(info)))
4553 return -EFAULT;
4554 break;
4555 }
4556 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4557 struct hdsp_9632_aeb h9632_aeb;
4558
4559 if (hdsp->io_type != H9632) return -EINVAL;
4560 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4561 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4562 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4563 return -EFAULT;
4564 break;
4565 }
4566 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4567 struct hdsp_version hdsp_version;
4568 int err;
4569
4570 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4571 if (hdsp->io_type == Undefined) {
4572 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4573 return err;
4574 }
4575 hdsp_version.io_type = hdsp->io_type;
4576 hdsp_version.firmware_rev = hdsp->firmware_rev;
4577 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4578 return -EFAULT;
4579 break;
4580 }
4581 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4582 struct hdsp_firmware __user *firmware;
4583 u32 __user *firmware_data;
4584 int err;
4585
4586 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4587 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4588 if (hdsp->io_type == Undefined) return -EINVAL;
4589
4590 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4591 return -EBUSY;
4592
4593 snd_printk(KERN_INFO "Hammerfall-DSP: initializing firmware upload\n");
4594 firmware = (struct hdsp_firmware __user *)argp;
4595
4596 if (get_user(firmware_data, &firmware->firmware_data))
4597 return -EFAULT;
4598
4599 if (hdsp_check_for_iobox (hdsp))
4600 return -EIO;
4601
4602 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0)
4603 return -EFAULT;
4604
4605 hdsp->state |= HDSP_FirmwareCached;
4606
4607 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4608 return err;
4609
4610 if (!(hdsp->state & HDSP_InitializationComplete)) {
4611 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4612 return err;
4613
4614 snd_hdsp_initialize_channels(hdsp);
4615 snd_hdsp_initialize_midi_flush(hdsp);
4616
4617 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4618 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
4619 return err;
4620 }
4621 }
4622 break;
4623 }
4624 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4625 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4626 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4627 return -EFAULT;
4628 break;
4629 }
4630 default:
4631 return -EINVAL;
4632 }
4633 return 0;
4634 }
4635
4636 static struct snd_pcm_ops snd_hdsp_playback_ops = {
4637 .open = snd_hdsp_playback_open,
4638 .close = snd_hdsp_playback_release,
4639 .ioctl = snd_hdsp_ioctl,
4640 .hw_params = snd_hdsp_hw_params,
4641 .prepare = snd_hdsp_prepare,
4642 .trigger = snd_hdsp_trigger,
4643 .pointer = snd_hdsp_hw_pointer,
4644 .copy = snd_hdsp_playback_copy,
4645 .silence = snd_hdsp_hw_silence,
4646 };
4647
4648 static struct snd_pcm_ops snd_hdsp_capture_ops = {
4649 .open = snd_hdsp_capture_open,
4650 .close = snd_hdsp_capture_release,
4651 .ioctl = snd_hdsp_ioctl,
4652 .hw_params = snd_hdsp_hw_params,
4653 .prepare = snd_hdsp_prepare,
4654 .trigger = snd_hdsp_trigger,
4655 .pointer = snd_hdsp_hw_pointer,
4656 .copy = snd_hdsp_capture_copy,
4657 };
4658
4659 static int __devinit snd_hdsp_create_hwdep(struct snd_card *card,
4660 struct hdsp *hdsp)
4661 {
4662 struct snd_hwdep *hw;
4663 int err;
4664
4665 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4666 return err;
4667
4668 hdsp->hwdep = hw;
4669 hw->private_data = hdsp;
4670 strcpy(hw->name, "HDSP hwdep interface");
4671
4672 hw->ops.open = snd_hdsp_hwdep_dummy_op;
4673 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4674 hw->ops.release = snd_hdsp_hwdep_dummy_op;
4675
4676 return 0;
4677 }
4678
4679 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4680 {
4681 struct snd_pcm *pcm;
4682 int err;
4683
4684 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4685 return err;
4686
4687 hdsp->pcm = pcm;
4688 pcm->private_data = hdsp;
4689 strcpy(pcm->name, hdsp->card_name);
4690
4691 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4692 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4693
4694 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4695
4696 return 0;
4697 }
4698
4699 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4700 {
4701 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4702 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4703 }
4704
4705 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4706 {
4707 int i;
4708
4709 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4710 snd_printk(KERN_ERR "Hammerfall-DSP: enable_io fifo_wait failed\n");
4711 return -EIO;
4712 }
4713
4714 for (i = 0; i < hdsp->max_channels; ++i) {
4715 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4716 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4717 }
4718
4719 return 0;
4720 }
4721
4722 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4723 {
4724 int status, aebi_channels, aebo_channels;
4725
4726 switch (hdsp->io_type) {
4727 case Digiface:
4728 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4729 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4730 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4731 break;
4732
4733 case H9652:
4734 hdsp->card_name = "RME Hammerfall HDSP 9652";
4735 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4736 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4737 break;
4738
4739 case H9632:
4740 status = hdsp_read(hdsp, HDSP_statusRegister);
4741 /* HDSP_AEBx bits are low when AEB are connected */
4742 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4743 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4744 hdsp->card_name = "RME Hammerfall HDSP 9632";
4745 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4746 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4747 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4748 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4749 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4750 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4751 break;
4752
4753 case Multiface:
4754 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4755 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4756 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4757 break;
4758
4759 default:
4760 /* should never get here */
4761 break;
4762 }
4763 }
4764
4765 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
4766 {
4767 snd_hdsp_flush_midi_input (hdsp, 0);
4768 snd_hdsp_flush_midi_input (hdsp, 1);
4769 }
4770
4771 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
4772 {
4773 int err;
4774
4775 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4776 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating pcm interface\n");
4777 return err;
4778 }
4779
4780
4781 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4782 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating first midi interface\n");
4783 return err;
4784 }
4785
4786 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
4787 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4788 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating second midi interface\n");
4789 return err;
4790 }
4791 }
4792
4793 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4794 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating ctl interface\n");
4795 return err;
4796 }
4797
4798 snd_hdsp_proc_init(hdsp);
4799
4800 hdsp->system_sample_rate = -1;
4801 hdsp->playback_pid = -1;
4802 hdsp->capture_pid = -1;
4803 hdsp->capture_substream = NULL;
4804 hdsp->playback_substream = NULL;
4805
4806 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4807 snd_printk(KERN_ERR "Hammerfall-DSP: Error setting default values\n");
4808 return err;
4809 }
4810
4811 if (!(hdsp->state & HDSP_InitializationComplete)) {
4812 strcpy(card->shortname, "Hammerfall DSP");
4813 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4814 hdsp->port, hdsp->irq);
4815
4816 if ((err = snd_card_register(card)) < 0) {
4817 snd_printk(KERN_ERR "Hammerfall-DSP: error registering card\n");
4818 return err;
4819 }
4820 hdsp->state |= HDSP_InitializationComplete;
4821 }
4822
4823 return 0;
4824 }
4825
4826 #ifdef HDSP_FW_LOADER
4827 /* load firmware via hotplug fw loader */
4828 static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp)
4829 {
4830 const char *fwfile;
4831 const struct firmware *fw;
4832 int err;
4833
4834 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4835 return 0;
4836 if (hdsp->io_type == Undefined) {
4837 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4838 return err;
4839 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4840 return 0;
4841 }
4842
4843 /* caution: max length of firmware filename is 30! */
4844 switch (hdsp->io_type) {
4845 case Multiface:
4846 if (hdsp->firmware_rev == 0xa)
4847 fwfile = "multiface_firmware.bin";
4848 else
4849 fwfile = "multiface_firmware_rev11.bin";
4850 break;
4851 case Digiface:
4852 if (hdsp->firmware_rev == 0xa)
4853 fwfile = "digiface_firmware.bin";
4854 else
4855 fwfile = "digiface_firmware_rev11.bin";
4856 break;
4857 default:
4858 snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type);
4859 return -EINVAL;
4860 }
4861
4862 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
4863 snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile);
4864 return -ENOENT;
4865 }
4866 if (fw->size < sizeof(hdsp->firmware_cache)) {
4867 snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n",
4868 (int)fw->size, (int)sizeof(hdsp->firmware_cache));
4869 release_firmware(fw);
4870 return -EINVAL;
4871 }
4872
4873 memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache));
4874
4875 release_firmware(fw);
4876
4877 hdsp->state |= HDSP_FirmwareCached;
4878
4879 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4880 return err;
4881
4882 if (!(hdsp->state & HDSP_InitializationComplete)) {
4883 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4884 return err;
4885
4886 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
4887 snd_printk(KERN_ERR "Hammerfall-DSP: error creating hwdep device\n");
4888 return err;
4889 }
4890 snd_hdsp_initialize_channels(hdsp);
4891 snd_hdsp_initialize_midi_flush(hdsp);
4892 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4893 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
4894 return err;
4895 }
4896 }
4897 return 0;
4898 }
4899 #endif
4900
4901 static int __devinit snd_hdsp_create(struct snd_card *card,
4902 struct hdsp *hdsp)
4903 {
4904 struct pci_dev *pci = hdsp->pci;
4905 int err;
4906 int is_9652 = 0;
4907 int is_9632 = 0;
4908
4909 hdsp->irq = -1;
4910 hdsp->state = 0;
4911 hdsp->midi[0].rmidi = NULL;
4912 hdsp->midi[1].rmidi = NULL;
4913 hdsp->midi[0].input = NULL;
4914 hdsp->midi[1].input = NULL;
4915 hdsp->midi[0].output = NULL;
4916 hdsp->midi[1].output = NULL;
4917 hdsp->midi[0].pending = 0;
4918 hdsp->midi[1].pending = 0;
4919 spin_lock_init(&hdsp->midi[0].lock);
4920 spin_lock_init(&hdsp->midi[1].lock);
4921 hdsp->iobase = NULL;
4922 hdsp->control_register = 0;
4923 hdsp->control2_register = 0;
4924 hdsp->io_type = Undefined;
4925 hdsp->max_channels = 26;
4926
4927 hdsp->card = card;
4928
4929 spin_lock_init(&hdsp->lock);
4930
4931 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
4932
4933 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
4934 hdsp->firmware_rev &= 0xff;
4935
4936 /* From Martin Bjoernsen :
4937 "It is important that the card's latency timer register in
4938 the PCI configuration space is set to a value much larger
4939 than 0 by the computer's BIOS or the driver.
4940 The windows driver always sets this 8 bit register [...]
4941 to its maximum 255 to avoid problems with some computers."
4942 */
4943 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
4944
4945 strcpy(card->driver, "H-DSP");
4946 strcpy(card->mixername, "Xilinx FPGA");
4947
4948 if (hdsp->firmware_rev < 0xa)
4949 return -ENODEV;
4950 else if (hdsp->firmware_rev < 0x64)
4951 hdsp->card_name = "RME Hammerfall DSP";
4952 else if (hdsp->firmware_rev < 0x96) {
4953 hdsp->card_name = "RME HDSP 9652";
4954 is_9652 = 1;
4955 } else {
4956 hdsp->card_name = "RME HDSP 9632";
4957 hdsp->max_channels = 16;
4958 is_9632 = 1;
4959 }
4960
4961 if ((err = pci_enable_device(pci)) < 0)
4962 return err;
4963
4964 pci_set_master(hdsp->pci);
4965
4966 if ((err = pci_request_regions(pci, "hdsp")) < 0)
4967 return err;
4968 hdsp->port = pci_resource_start(pci, 0);
4969 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
4970 snd_printk(KERN_ERR "Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
4971 return -EBUSY;
4972 }
4973
4974 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
4975 "hdsp", hdsp)) {
4976 snd_printk(KERN_ERR "Hammerfall-DSP: unable to use IRQ %d\n", pci->irq);
4977 return -EBUSY;
4978 }
4979
4980 hdsp->irq = pci->irq;
4981 hdsp->precise_ptr = 0;
4982 hdsp->use_midi_tasklet = 1;
4983 hdsp->dds_value = 0;
4984
4985 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
4986 return err;
4987
4988 if (!is_9652 && !is_9632) {
4989 /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */
4990 ssleep(2);
4991
4992 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
4993 #ifdef HDSP_FW_LOADER
4994 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
4995 /* we don't fail as this can happen
4996 if userspace is not ready for
4997 firmware upload
4998 */
4999 snd_printk(KERN_ERR "Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n");
5000 else
5001 /* init is complete, we return */
5002 return 0;
5003 #endif
5004 /* no iobox connected, we defer initialization */
5005 snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n");
5006 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5007 return err;
5008 return 0;
5009 } else {
5010 snd_printk(KERN_INFO "Hammerfall-DSP: Firmware already present, initializing card.\n");
5011 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5012 hdsp->io_type = Multiface;
5013 else
5014 hdsp->io_type = Digiface;
5015 }
5016 }
5017
5018 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5019 return err;
5020
5021 if (is_9652)
5022 hdsp->io_type = H9652;
5023
5024 if (is_9632)
5025 hdsp->io_type = H9632;
5026
5027 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5028 return err;
5029
5030 snd_hdsp_initialize_channels(hdsp);
5031 snd_hdsp_initialize_midi_flush(hdsp);
5032
5033 hdsp->state |= HDSP_FirmwareLoaded;
5034
5035 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5036 return err;
5037
5038 return 0;
5039 }
5040
5041 static int snd_hdsp_free(struct hdsp *hdsp)
5042 {
5043 if (hdsp->port) {
5044 /* stop the audio, and cancel all interrupts */
5045 tasklet_kill(&hdsp->midi_tasklet);
5046 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5047 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5048 }
5049
5050 if (hdsp->irq >= 0)
5051 free_irq(hdsp->irq, (void *)hdsp);
5052
5053 snd_hdsp_free_buffers(hdsp);
5054
5055 if (hdsp->iobase)
5056 iounmap(hdsp->iobase);
5057
5058 if (hdsp->port)
5059 pci_release_regions(hdsp->pci);
5060
5061 pci_disable_device(hdsp->pci);
5062 return 0;
5063 }
5064
5065 static void snd_hdsp_card_free(struct snd_card *card)
5066 {
5067 struct hdsp *hdsp = (struct hdsp *) card->private_data;
5068
5069 if (hdsp)
5070 snd_hdsp_free(hdsp);
5071 }
5072
5073 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5074 const struct pci_device_id *pci_id)
5075 {
5076 static int dev;
5077 struct hdsp *hdsp;
5078 struct snd_card *card;
5079 int err;
5080
5081 if (dev >= SNDRV_CARDS)
5082 return -ENODEV;
5083 if (!enable[dev]) {
5084 dev++;
5085 return -ENOENT;
5086 }
5087
5088 if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(struct hdsp))))
5089 return -ENOMEM;
5090
5091 hdsp = (struct hdsp *) card->private_data;
5092 card->private_free = snd_hdsp_card_free;
5093 hdsp->dev = dev;
5094 hdsp->pci = pci;
5095 snd_card_set_dev(card, &pci->dev);
5096
5097 if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5098 snd_card_free(card);
5099 return err;
5100 }
5101
5102 strcpy(card->shortname, "Hammerfall DSP");
5103 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5104 hdsp->port, hdsp->irq);
5105
5106 if ((err = snd_card_register(card)) < 0) {
5107 snd_card_free(card);
5108 return err;
5109 }
5110 pci_set_drvdata(pci, card);
5111 dev++;
5112 return 0;
5113 }
5114
5115 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5116 {
5117 snd_card_free(pci_get_drvdata(pci));
5118 pci_set_drvdata(pci, NULL);
5119 }
5120
5121 static struct pci_driver driver = {
5122 .name = "RME Hammerfall DSP",
5123 .id_table = snd_hdsp_ids,
5124 .probe = snd_hdsp_probe,
5125 .remove = __devexit_p(snd_hdsp_remove),
5126 };
5127
5128 static int __init alsa_card_hdsp_init(void)
5129 {
5130 return pci_register_driver(&driver);
5131 }
5132
5133 static void __exit alsa_card_hdsp_exit(void)
5134 {
5135 pci_unregister_driver(&driver);
5136 }
5137
5138 module_init(alsa_card_hdsp_init)
5139 module_exit(alsa_card_hdsp_exit)
Linux kernel - Deliverables
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