projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[ALSA] hdsp - Add 'Sample Clock Source Locking' control
[deliverable/linux.git] / sound / pci / rme9652 / hdsp.c
1 /*
2 * ALSA driver for RME Hammerfall DSP audio interface(s)
3 *
4 * Copyright (c) 2002 Paul Davis
5 * Marcus Andersson
6 * Thomas Charbonnel
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <sound/driver.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/interrupt.h>
28 #include <linux/slab.h>
29 #include <linux/pci.h>
30 #include <linux/firmware.h>
31 #include <linux/moduleparam.h>
32
33 #include <sound/core.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/info.h>
37 #include <sound/asoundef.h>
38 #include <sound/rawmidi.h>
39 #include <sound/hwdep.h>
40 #include <sound/initval.h>
41 #include <sound/hdsp.h>
42
43 #include <asm/byteorder.h>
44 #include <asm/current.h>
45 #include <asm/io.h>
46
47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
49 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
50
51 module_param_array(index, int, NULL, 0444);
52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
53 module_param_array(id, charp, NULL, 0444);
54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
55 module_param_array(enable, bool, NULL, 0444);
56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
58 MODULE_DESCRIPTION("RME Hammerfall DSP");
59 MODULE_LICENSE("GPL");
60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
61 "{RME HDSP-9652},"
62 "{RME HDSP-9632}}");
63
64 #define HDSP_MAX_CHANNELS 26
65 #define HDSP_MAX_DS_CHANNELS 14
66 #define HDSP_MAX_QS_CHANNELS 8
67 #define DIGIFACE_SS_CHANNELS 26
68 #define DIGIFACE_DS_CHANNELS 14
69 #define MULTIFACE_SS_CHANNELS 18
70 #define MULTIFACE_DS_CHANNELS 14
71 #define H9652_SS_CHANNELS 26
72 #define H9652_DS_CHANNELS 14
73 /* This does not include possible Analog Extension Boards
74 AEBs are detected at card initialization
75 */
76 #define H9632_SS_CHANNELS 12
77 #define H9632_DS_CHANNELS 8
78 #define H9632_QS_CHANNELS 4
79
80 /* Write registers. These are defined as byte-offsets from the iobase value.
81 */
82 #define HDSP_resetPointer 0
83 #define HDSP_outputBufferAddress 32
84 #define HDSP_inputBufferAddress 36
85 #define HDSP_controlRegister 64
86 #define HDSP_interruptConfirmation 96
87 #define HDSP_outputEnable 128
88 #define HDSP_control2Reg 256
89 #define HDSP_midiDataOut0 352
90 #define HDSP_midiDataOut1 356
91 #define HDSP_fifoData 368
92 #define HDSP_inputEnable 384
93
94 /* Read registers. These are defined as byte-offsets from the iobase value
95 */
96
97 #define HDSP_statusRegister 0
98 #define HDSP_timecode 128
99 #define HDSP_status2Register 192
100 #define HDSP_midiDataOut0 352
101 #define HDSP_midiDataOut1 356
102 #define HDSP_midiDataIn0 360
103 #define HDSP_midiDataIn1 364
104 #define HDSP_midiStatusOut0 384
105 #define HDSP_midiStatusOut1 388
106 #define HDSP_midiStatusIn0 392
107 #define HDSP_midiStatusIn1 396
108 #define HDSP_fifoStatus 400
109
110 /* the meters are regular i/o-mapped registers, but offset
111 considerably from the rest. the peak registers are reset
112 when read; the least-significant 4 bits are full-scale counters;
113 the actual peak value is in the most-significant 24 bits.
114 */
115
116 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
117 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
118 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
119 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
120 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
121
122
123 /* This is for H9652 cards
124 Peak values are read downward from the base
125 Rms values are read upward
126 There are rms values for the outputs too
127 26*3 values are read in ss mode
128 14*3 in ds mode, with no gap between values
129 */
130 #define HDSP_9652_peakBase 7164
131 #define HDSP_9652_rmsBase 4096
132
133 /* c.f. the hdsp_9632_meters_t struct */
134 #define HDSP_9632_metersBase 4096
135
136 #define HDSP_IO_EXTENT 7168
137
138 /* control2 register bits */
139
140 #define HDSP_TMS 0x01
141 #define HDSP_TCK 0x02
142 #define HDSP_TDI 0x04
143 #define HDSP_JTAG 0x08
144 #define HDSP_PWDN 0x10
145 #define HDSP_PROGRAM 0x020
146 #define HDSP_CONFIG_MODE_0 0x040
147 #define HDSP_CONFIG_MODE_1 0x080
148 #define HDSP_VERSION_BIT 0x100
149 #define HDSP_BIGENDIAN_MODE 0x200
150 #define HDSP_RD_MULTIPLE 0x400
151 #define HDSP_9652_ENABLE_MIXER 0x800
152 #define HDSP_TDO 0x10000000
153
154 #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
155 #define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
156
157 /* Control Register bits */
158
159 #define HDSP_Start (1<<0) /* start engine */
160 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
161 #define HDSP_Latency1 (1<<2) /* [ see above ] */
162 #define HDSP_Latency2 (1<<3) /* [ see above ] */
163 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
164 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
165 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
166 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
167 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
168 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
169 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
170 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
171 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
172 #define HDSP_SyncRef2 (1<<13)
173 #define HDSP_SPDIFInputSelect0 (1<<14)
174 #define HDSP_SPDIFInputSelect1 (1<<15)
175 #define HDSP_SyncRef0 (1<<16)
176 #define HDSP_SyncRef1 (1<<17)
177 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
178 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
179 #define HDSP_Midi0InterruptEnable (1<<22)
180 #define HDSP_Midi1InterruptEnable (1<<23)
181 #define HDSP_LineOut (1<<24)
182 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
183 #define HDSP_ADGain1 (1<<26)
184 #define HDSP_DAGain0 (1<<27)
185 #define HDSP_DAGain1 (1<<28)
186 #define HDSP_PhoneGain0 (1<<29)
187 #define HDSP_PhoneGain1 (1<<30)
188 #define HDSP_QuadSpeed (1<<31)
189
190 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
191 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
192 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
193 #define HDSP_ADGainLowGain 0
194
195 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
196 #define HDSP_DAGainHighGain HDSP_DAGainMask
197 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
198 #define HDSP_DAGainMinus10dBV 0
199
200 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
201 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
202 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
203 #define HDSP_PhoneGainMinus12dB 0
204
205 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
206 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
207
208 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
209 #define HDSP_SPDIFInputADAT1 0
210 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
211 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
212 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
213
214 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
215 #define HDSP_SyncRef_ADAT1 0
216 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
217 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
218 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
219 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
220 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
221
222 /* Sample Clock Sources */
223
224 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
225 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
226 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
227 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
228 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
229 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
230 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
231 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
232 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
233 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
234
235 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
236
237 #define HDSP_SYNC_FROM_WORD 0
238 #define HDSP_SYNC_FROM_SPDIF 1
239 #define HDSP_SYNC_FROM_ADAT1 2
240 #define HDSP_SYNC_FROM_ADAT_SYNC 3
241 #define HDSP_SYNC_FROM_ADAT2 4
242 #define HDSP_SYNC_FROM_ADAT3 5
243
244 /* SyncCheck status */
245
246 #define HDSP_SYNC_CHECK_NO_LOCK 0
247 #define HDSP_SYNC_CHECK_LOCK 1
248 #define HDSP_SYNC_CHECK_SYNC 2
249
250 /* AutoSync references - used by "autosync_ref" control switch */
251
252 #define HDSP_AUTOSYNC_FROM_WORD 0
253 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
254 #define HDSP_AUTOSYNC_FROM_SPDIF 2
255 #define HDSP_AUTOSYNC_FROM_NONE 3
256 #define HDSP_AUTOSYNC_FROM_ADAT1 4
257 #define HDSP_AUTOSYNC_FROM_ADAT2 5
258 #define HDSP_AUTOSYNC_FROM_ADAT3 6
259
260 /* Possible sources of S/PDIF input */
261
262 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
263 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
264 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
265 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
266
267 #define HDSP_Frequency32KHz HDSP_Frequency0
268 #define HDSP_Frequency44_1KHz HDSP_Frequency1
269 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
270 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
271 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
272 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
273 /* For H9632 cards */
274 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
275 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
276 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
277
278 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
279 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
280
281 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
282 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
283
284 /* Status Register bits */
285
286 #define HDSP_audioIRQPending (1<<0)
287 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
288 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
289 #define HDSP_Lock1 (1<<2)
290 #define HDSP_Lock0 (1<<3)
291 #define HDSP_SPDIFSync (1<<4)
292 #define HDSP_TimecodeLock (1<<5)
293 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
294 #define HDSP_Sync2 (1<<16)
295 #define HDSP_Sync1 (1<<17)
296 #define HDSP_Sync0 (1<<18)
297 #define HDSP_DoubleSpeedStatus (1<<19)
298 #define HDSP_ConfigError (1<<20)
299 #define HDSP_DllError (1<<21)
300 #define HDSP_spdifFrequency0 (1<<22)
301 #define HDSP_spdifFrequency1 (1<<23)
302 #define HDSP_spdifFrequency2 (1<<24)
303 #define HDSP_SPDIFErrorFlag (1<<25)
304 #define HDSP_BufferID (1<<26)
305 #define HDSP_TimecodeSync (1<<27)
306 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
307 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
308 #define HDSP_midi0IRQPending (1<<30)
309 #define HDSP_midi1IRQPending (1<<31)
310
311 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
312
313 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
314 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
315 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
316
317 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
318 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
319 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
320
321 /* This is for H9632 cards */
322 #define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask
323 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
324 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
325
326 /* Status2 Register bits */
327
328 #define HDSP_version0 (1<<0)
329 #define HDSP_version1 (1<<1)
330 #define HDSP_version2 (1<<2)
331 #define HDSP_wc_lock (1<<3)
332 #define HDSP_wc_sync (1<<4)
333 #define HDSP_inp_freq0 (1<<5)
334 #define HDSP_inp_freq1 (1<<6)
335 #define HDSP_inp_freq2 (1<<7)
336 #define HDSP_SelSyncRef0 (1<<8)
337 #define HDSP_SelSyncRef1 (1<<9)
338 #define HDSP_SelSyncRef2 (1<<10)
339
340 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
341
342 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
343 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
344 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
345 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
346 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
347 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
348 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
349 /* FIXME : more values for 9632 cards ? */
350
351 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
352 #define HDSP_SelSyncRef_ADAT1 0
353 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
354 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
355 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
356 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
357 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
358
359 /* Card state flags */
360
361 #define HDSP_InitializationComplete (1<<0)
362 #define HDSP_FirmwareLoaded (1<<1)
363 #define HDSP_FirmwareCached (1<<2)
364
365 /* FIFO wait times, defined in terms of 1/10ths of msecs */
366
367 #define HDSP_LONG_WAIT 5000
368 #define HDSP_SHORT_WAIT 30
369
370 #define UNITY_GAIN 32768
371 #define MINUS_INFINITY_GAIN 0
372
373 #ifndef PCI_VENDOR_ID_XILINX
374 #define PCI_VENDOR_ID_XILINX 0x10ee
375 #endif
376 #ifndef PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP
377 #define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
378 #endif
379
380 /* the size of a substream (1 mono data stream) */
381
382 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
383 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
384
385 /* the size of the area we need to allocate for DMA transfers. the
386 size is the same regardless of the number of channels - the
387 Multiface still uses the same memory area.
388
389 Note that we allocate 1 more channel than is apparently needed
390 because the h/w seems to write 1 byte beyond the end of the last
391 page. Sigh.
392 */
393
394 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
395 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
396
397 /* use hotplug firmeare loader? */
398 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
399 #ifndef HDSP_USE_HWDEP_LOADER
400 #define HDSP_FW_LOADER
401 #endif
402 #endif
403
404 typedef struct _hdsp hdsp_t;
405 typedef struct _hdsp_midi hdsp_midi_t;
406 typedef struct _hdsp_9632_meters hdsp_9632_meters_t;
407
408 struct _hdsp_9632_meters {
409 u32 input_peak[16];
410 u32 playback_peak[16];
411 u32 output_peak[16];
412 u32 xxx_peak[16];
413 u32 padding[64];
414 u32 input_rms_low[16];
415 u32 playback_rms_low[16];
416 u32 output_rms_low[16];
417 u32 xxx_rms_low[16];
418 u32 input_rms_high[16];
419 u32 playback_rms_high[16];
420 u32 output_rms_high[16];
421 u32 xxx_rms_high[16];
422 };
423
424 struct _hdsp_midi {
425 hdsp_t *hdsp;
426 int id;
427 snd_rawmidi_t *rmidi;
428 snd_rawmidi_substream_t *input;
429 snd_rawmidi_substream_t *output;
430 char istimer; /* timer in use */
431 struct timer_list timer;
432 spinlock_t lock;
433 int pending;
434 };
435
436 struct _hdsp {
437 spinlock_t lock;
438 snd_pcm_substream_t *capture_substream;
439 snd_pcm_substream_t *playback_substream;
440 hdsp_midi_t midi[2];
441 struct tasklet_struct midi_tasklet;
442 int use_midi_tasklet;
443 int precise_ptr;
444 u32 control_register; /* cached value */
445 u32 control2_register; /* cached value */
446 u32 creg_spdif;
447 u32 creg_spdif_stream;
448 int clock_source_locked;
449 char *card_name; /* digiface/multiface */
450 HDSP_IO_Type io_type; /* ditto, but for code use */
451 unsigned short firmware_rev;
452 unsigned short state; /* stores state bits */
453 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
454 size_t period_bytes; /* guess what this is */
455 unsigned char max_channels;
456 unsigned char qs_in_channels; /* quad speed mode for H9632 */
457 unsigned char ds_in_channels;
458 unsigned char ss_in_channels; /* different for multiface/digiface */
459 unsigned char qs_out_channels;
460 unsigned char ds_out_channels;
461 unsigned char ss_out_channels;
462
463 struct snd_dma_buffer capture_dma_buf;
464 struct snd_dma_buffer playback_dma_buf;
465 unsigned char *capture_buffer; /* suitably aligned address */
466 unsigned char *playback_buffer; /* suitably aligned address */
467
468 pid_t capture_pid;
469 pid_t playback_pid;
470 int running;
471 int system_sample_rate;
472 char *channel_map;
473 int dev;
474 int irq;
475 unsigned long port;
476 void __iomem *iobase;
477 snd_card_t *card;
478 snd_pcm_t *pcm;
479 snd_hwdep_t *hwdep;
480 struct pci_dev *pci;
481 snd_kcontrol_t *spdif_ctl;
482 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
483 };
484
485 /* These tables map the ALSA channels 1..N to the channels that we
486 need to use in order to find the relevant channel buffer. RME
487 refer to this kind of mapping as between "the ADAT channel and
488 the DMA channel." We index it using the logical audio channel,
489 and the value is the DMA channel (i.e. channel buffer number)
490 where the data for that channel can be read/written from/to.
491 */
492
493 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
494 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
495 18, 19, 20, 21, 22, 23, 24, 25
496 };
497
498 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
499 /* Analog */
500 0, 1, 2, 3, 4, 5, 6, 7,
501 /* ADAT 2 */
502 16, 17, 18, 19, 20, 21, 22, 23,
503 /* SPDIF */
504 24, 25,
505 -1, -1, -1, -1, -1, -1, -1, -1
506 };
507
508 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
509 /* ADAT channels are remapped */
510 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
511 /* channels 12 and 13 are S/PDIF */
512 24, 25,
513 /* others don't exist */
514 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
515 };
516
517 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
518 /* ADAT channels */
519 0, 1, 2, 3, 4, 5, 6, 7,
520 /* SPDIF */
521 8, 9,
522 /* Analog */
523 10, 11,
524 /* AO4S-192 and AI4S-192 extension boards */
525 12, 13, 14, 15,
526 /* others don't exist */
527 -1, -1, -1, -1, -1, -1, -1, -1,
528 -1, -1
529 };
530
531 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
532 /* ADAT */
533 1, 3, 5, 7,
534 /* SPDIF */
535 8, 9,
536 /* Analog */
537 10, 11,
538 /* AO4S-192 and AI4S-192 extension boards */
539 12, 13, 14, 15,
540 /* others don't exist */
541 -1, -1, -1, -1, -1, -1, -1, -1,
542 -1, -1, -1, -1, -1, -1
543 };
544
545 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
546 /* ADAT is disabled in this mode */
547 /* SPDIF */
548 8, 9,
549 /* Analog */
550 10, 11,
551 /* AO4S-192 and AI4S-192 extension boards */
552 12, 13, 14, 15,
553 /* others don't exist */
554 -1, -1, -1, -1, -1, -1, -1, -1,
555 -1, -1, -1, -1, -1, -1, -1, -1,
556 -1, -1
557 };
558
559 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
560 {
561 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
562 dmab->dev.dev = snd_dma_pci_data(pci);
563 if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
564 if (dmab->bytes >= size)
565 return 0;
566 }
567 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
568 size, dmab) < 0)
569 return -ENOMEM;
570 return 0;
571 }
572
573 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
574 {
575 if (dmab->area) {
576 dmab->dev.dev = NULL; /* make it anonymous */
577 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
578 }
579 }
580
581
582 static struct pci_device_id snd_hdsp_ids[] = {
583 {
584 .vendor = PCI_VENDOR_ID_XILINX,
585 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
586 .subvendor = PCI_ANY_ID,
587 .subdevice = PCI_ANY_ID,
588 }, /* RME Hammerfall-DSP */
589 { 0, },
590 };
591
592 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
593
594 /* prototypes */
595 static int snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp);
596 static int snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp);
597 static int snd_hdsp_enable_io (hdsp_t *hdsp);
598 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp);
599 static void snd_hdsp_initialize_channels (hdsp_t *hdsp);
600 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout);
601 static int hdsp_autosync_ref(hdsp_t *hdsp);
602 static int snd_hdsp_set_defaults(hdsp_t *hdsp);
603 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp);
604
605 static int hdsp_playback_to_output_key (hdsp_t *hdsp, int in, int out)
606 {
607 switch (hdsp->firmware_rev) {
608 case 0xa:
609 return (64 * out) + (32 + (in));
610 case 0x96:
611 case 0x97:
612 return (32 * out) + (16 + (in));
613 default:
614 return (52 * out) + (26 + (in));
615 }
616 }
617
618 static int hdsp_input_to_output_key (hdsp_t *hdsp, int in, int out)
619 {
620 switch (hdsp->firmware_rev) {
621 case 0xa:
622 return (64 * out) + in;
623 case 0x96:
624 case 0x97:
625 return (32 * out) + in;
626 default:
627 return (52 * out) + in;
628 }
629 }
630
631 static void hdsp_write(hdsp_t *hdsp, int reg, int val)
632 {
633 writel(val, hdsp->iobase + reg);
634 }
635
636 static unsigned int hdsp_read(hdsp_t *hdsp, int reg)
637 {
638 return readl (hdsp->iobase + reg);
639 }
640
641 static int hdsp_check_for_iobox (hdsp_t *hdsp)
642 {
643
644 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
645 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
646 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
647 hdsp->state &= ~HDSP_FirmwareLoaded;
648 return -EIO;
649 }
650 return 0;
651
652 }
653
654 static int snd_hdsp_load_firmware_from_cache(hdsp_t *hdsp) {
655
656 int i;
657 unsigned long flags;
658
659 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
660
661 snd_printk ("Hammerfall-DSP: loading firmware\n");
662
663 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
664 hdsp_write (hdsp, HDSP_fifoData, 0);
665
666 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
667 snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n");
668 return -EIO;
669 }
670
671 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
672
673 for (i = 0; i < 24413; ++i) {
674 hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
675 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
676 snd_printk ("Hammerfall-DSP: timeout during firmware loading\n");
677 return -EIO;
678 }
679 }
680
681 if ((1000 / HZ) < 3000) {
682 set_current_state(TASK_UNINTERRUPTIBLE);
683 schedule_timeout((3000 * HZ + 999) / 1000);
684 } else {
685 mdelay(3000);
686 }
687
688 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
689 snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n");
690 return -EIO;
691 }
692
693 #ifdef SNDRV_BIG_ENDIAN
694 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
695 #else
696 hdsp->control2_register = 0;
697 #endif
698 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
699 snd_printk ("Hammerfall-DSP: finished firmware loading\n");
700
701 }
702 if (hdsp->state & HDSP_InitializationComplete) {
703 snd_printk("Hammerfall-DSP: firmware loaded from cache, restoring defaults\n");
704 spin_lock_irqsave(&hdsp->lock, flags);
705 snd_hdsp_set_defaults(hdsp);
706 spin_unlock_irqrestore(&hdsp->lock, flags);
707 }
708
709 hdsp->state |= HDSP_FirmwareLoaded;
710
711 return 0;
712 }
713
714 static int hdsp_get_iobox_version (hdsp_t *hdsp)
715 {
716 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
717
718 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
719 hdsp_write (hdsp, HDSP_fifoData, 0);
720 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) {
721 return -EIO;
722 }
723
724 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
725 hdsp_write (hdsp, HDSP_fifoData, 0);
726
727 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
728 hdsp->io_type = Multiface;
729 hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
730 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
731 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
732 } else {
733 hdsp->io_type = Digiface;
734 }
735 } else {
736 /* firmware was already loaded, get iobox type */
737 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
738 hdsp->io_type = Multiface;
739 } else {
740 hdsp->io_type = Digiface;
741 }
742 }
743 return 0;
744 }
745
746
747 static int hdsp_check_for_firmware (hdsp_t *hdsp)
748 {
749 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
750 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
751 snd_printk("Hammerfall-DSP: firmware not present.\n");
752 hdsp->state &= ~HDSP_FirmwareLoaded;
753 return -EIO;
754 }
755 return 0;
756 }
757
758
759 static int hdsp_fifo_wait(hdsp_t *hdsp, int count, int timeout)
760 {
761 int i;
762
763 /* the fifoStatus registers reports on how many words
764 are available in the command FIFO.
765 */
766
767 for (i = 0; i < timeout; i++) {
768
769 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
770 return 0;
771
772 /* not very friendly, but we only do this during a firmware
773 load and changing the mixer, so we just put up with it.
774 */
775
776 udelay (100);
777 }
778
779 snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n",
780 count, timeout);
781 return -1;
782 }
783
784 static int hdsp_read_gain (hdsp_t *hdsp, unsigned int addr)
785 {
786 if (addr >= HDSP_MATRIX_MIXER_SIZE) {
787 return 0;
788 }
789 return hdsp->mixer_matrix[addr];
790 }
791
792 static int hdsp_write_gain(hdsp_t *hdsp, unsigned int addr, unsigned short data)
793 {
794 unsigned int ad;
795
796 if (addr >= HDSP_MATRIX_MIXER_SIZE)
797 return -1;
798
799 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
800
801 /* from martin bjornsen:
802
803 "You can only write dwords to the
804 mixer memory which contain two
805 mixer values in the low and high
806 word. So if you want to change
807 value 0 you have to read value 1
808 from the cache and write both to
809 the first dword in the mixer
810 memory."
811 */
812
813 if (hdsp->io_type == H9632 && addr >= 512) {
814 return 0;
815 }
816
817 if (hdsp->io_type == H9652 && addr >= 1352) {
818 return 0;
819 }
820
821 hdsp->mixer_matrix[addr] = data;
822
823
824 /* `addr' addresses a 16-bit wide address, but
825 the address space accessed via hdsp_write
826 uses byte offsets. put another way, addr
827 varies from 0 to 1351, but to access the
828 corresponding memory location, we need
829 to access 0 to 2703 ...
830 */
831 ad = addr/2;
832
833 hdsp_write (hdsp, 4096 + (ad*4),
834 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
835 hdsp->mixer_matrix[addr&0x7fe]);
836
837 return 0;
838
839 } else {
840
841 ad = (addr << 16) + data;
842
843 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) {
844 return -1;
845 }
846
847 hdsp_write (hdsp, HDSP_fifoData, ad);
848 hdsp->mixer_matrix[addr] = data;
849
850 }
851
852 return 0;
853 }
854
855 static int snd_hdsp_use_is_exclusive(hdsp_t *hdsp)
856 {
857 unsigned long flags;
858 int ret = 1;
859
860 spin_lock_irqsave(&hdsp->lock, flags);
861 if ((hdsp->playback_pid != hdsp->capture_pid) &&
862 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) {
863 ret = 0;
864 }
865 spin_unlock_irqrestore(&hdsp->lock, flags);
866 return ret;
867 }
868
869 static int hdsp_external_sample_rate (hdsp_t *hdsp)
870 {
871 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
872 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
873
874 switch (rate_bits) {
875 case HDSP_systemFrequency32: return 32000;
876 case HDSP_systemFrequency44_1: return 44100;
877 case HDSP_systemFrequency48: return 48000;
878 case HDSP_systemFrequency64: return 64000;
879 case HDSP_systemFrequency88_2: return 88200;
880 case HDSP_systemFrequency96: return 96000;
881 default:
882 return 0;
883 }
884 }
885
886 static int hdsp_spdif_sample_rate(hdsp_t *hdsp)
887 {
888 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
889 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
890
891 if (status & HDSP_SPDIFErrorFlag) {
892 return 0;
893 }
894
895 switch (rate_bits) {
896 case HDSP_spdifFrequency32KHz: return 32000;
897 case HDSP_spdifFrequency44_1KHz: return 44100;
898 case HDSP_spdifFrequency48KHz: return 48000;
899 case HDSP_spdifFrequency64KHz: return 64000;
900 case HDSP_spdifFrequency88_2KHz: return 88200;
901 case HDSP_spdifFrequency96KHz: return 96000;
902 case HDSP_spdifFrequency128KHz:
903 if (hdsp->io_type == H9632) return 128000;
904 break;
905 case HDSP_spdifFrequency176_4KHz:
906 if (hdsp->io_type == H9632) return 176400;
907 break;
908 case HDSP_spdifFrequency192KHz:
909 if (hdsp->io_type == H9632) return 192000;
910 break;
911 default:
912 break;
913 }
914 snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
915 return 0;
916 }
917
918 static void hdsp_compute_period_size(hdsp_t *hdsp)
919 {
920 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
921 }
922
923 static snd_pcm_uframes_t hdsp_hw_pointer(hdsp_t *hdsp)
924 {
925 int position;
926
927 position = hdsp_read(hdsp, HDSP_statusRegister);
928
929 if (!hdsp->precise_ptr) {
930 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
931 }
932
933 position &= HDSP_BufferPositionMask;
934 position /= 4;
935 position &= (hdsp->period_bytes/2) - 1;
936 return position;
937 }
938
939 static void hdsp_reset_hw_pointer(hdsp_t *hdsp)
940 {
941 hdsp_write (hdsp, HDSP_resetPointer, 0);
942 }
943
944 static void hdsp_start_audio(hdsp_t *s)
945 {
946 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
947 hdsp_write(s, HDSP_controlRegister, s->control_register);
948 }
949
950 static void hdsp_stop_audio(hdsp_t *s)
951 {
952 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
953 hdsp_write(s, HDSP_controlRegister, s->control_register);
954 }
955
956 static void hdsp_silence_playback(hdsp_t *hdsp)
957 {
958 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
959 }
960
961 static int hdsp_set_interrupt_interval(hdsp_t *s, unsigned int frames)
962 {
963 int n;
964
965 spin_lock_irq(&s->lock);
966
967 frames >>= 7;
968 n = 0;
969 while (frames) {
970 n++;
971 frames >>= 1;
972 }
973
974 s->control_register &= ~HDSP_LatencyMask;
975 s->control_register |= hdsp_encode_latency(n);
976
977 hdsp_write(s, HDSP_controlRegister, s->control_register);
978
979 hdsp_compute_period_size(s);
980
981 spin_unlock_irq(&s->lock);
982
983 return 0;
984 }
985
986 static int hdsp_set_rate(hdsp_t *hdsp, int rate, int called_internally)
987 {
988 int reject_if_open = 0;
989 int current_rate;
990 int rate_bits;
991
992 /* ASSUMPTION: hdsp->lock is either held, or
993 there is no need for it (e.g. during module
994 initialization).
995 */
996
997 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
998 if (called_internally) {
999 /* request from ctl or card initialization */
1000 snd_printk("Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n");
1001 return -1;
1002 } else {
1003 /* hw_param request while in AutoSync mode */
1004 int external_freq = hdsp_external_sample_rate(hdsp);
1005 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1006
1007 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1008 snd_printk("Hammerfall-DSP: Detected ADAT in double speed mode\n");
1009 } else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) {
1010 snd_printk("Hammerfall-DSP: Detected ADAT in quad speed mode\n");
1011 } else if (rate != external_freq) {
1012 snd_printk("Hammerfall-DSP: No AutoSync source for requested rate\n");
1013 return -1;
1014 }
1015 }
1016 }
1017
1018 current_rate = hdsp->system_sample_rate;
1019
1020 /* Changing from a "single speed" to a "double speed" rate is
1021 not allowed if any substreams are open. This is because
1022 such a change causes a shift in the location of
1023 the DMA buffers and a reduction in the number of available
1024 buffers.
1025
1026 Note that a similar but essentially insoluble problem
1027 exists for externally-driven rate changes. All we can do
1028 is to flag rate changes in the read/write routines. */
1029
1030 if (rate > 96000 && hdsp->io_type != H9632) {
1031 return -EINVAL;
1032 }
1033
1034 switch (rate) {
1035 case 32000:
1036 if (current_rate > 48000) {
1037 reject_if_open = 1;
1038 }
1039 rate_bits = HDSP_Frequency32KHz;
1040 break;
1041 case 44100:
1042 if (current_rate > 48000) {
1043 reject_if_open = 1;
1044 }
1045 rate_bits = HDSP_Frequency44_1KHz;
1046 break;
1047 case 48000:
1048 if (current_rate > 48000) {
1049 reject_if_open = 1;
1050 }
1051 rate_bits = HDSP_Frequency48KHz;
1052 break;
1053 case 64000:
1054 if (current_rate <= 48000 || current_rate > 96000) {
1055 reject_if_open = 1;
1056 }
1057 rate_bits = HDSP_Frequency64KHz;
1058 break;
1059 case 88200:
1060 if (current_rate <= 48000 || current_rate > 96000) {
1061 reject_if_open = 1;
1062 }
1063 rate_bits = HDSP_Frequency88_2KHz;
1064 break;
1065 case 96000:
1066 if (current_rate <= 48000 || current_rate > 96000) {
1067 reject_if_open = 1;
1068 }
1069 rate_bits = HDSP_Frequency96KHz;
1070 break;
1071 case 128000:
1072 if (current_rate < 128000) {
1073 reject_if_open = 1;
1074 }
1075 rate_bits = HDSP_Frequency128KHz;
1076 break;
1077 case 176400:
1078 if (current_rate < 128000) {
1079 reject_if_open = 1;
1080 }
1081 rate_bits = HDSP_Frequency176_4KHz;
1082 break;
1083 case 192000:
1084 if (current_rate < 128000) {
1085 reject_if_open = 1;
1086 }
1087 rate_bits = HDSP_Frequency192KHz;
1088 break;
1089 default:
1090 return -EINVAL;
1091 }
1092
1093 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1094 snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1095 hdsp->capture_pid,
1096 hdsp->playback_pid);
1097 return -EBUSY;
1098 }
1099
1100 hdsp->control_register &= ~HDSP_FrequencyMask;
1101 hdsp->control_register |= rate_bits;
1102 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1103
1104 if (rate >= 128000) {
1105 hdsp->channel_map = channel_map_H9632_qs;
1106 } else if (rate > 48000) {
1107 if (hdsp->io_type == H9632) {
1108 hdsp->channel_map = channel_map_H9632_ds;
1109 } else {
1110 hdsp->channel_map = channel_map_ds;
1111 }
1112 } else {
1113 switch (hdsp->io_type) {
1114 case Multiface:
1115 hdsp->channel_map = channel_map_mf_ss;
1116 break;
1117 case Digiface:
1118 case H9652:
1119 hdsp->channel_map = channel_map_df_ss;
1120 break;
1121 case H9632:
1122 hdsp->channel_map = channel_map_H9632_ss;
1123 break;
1124 default:
1125 /* should never happen */
1126 break;
1127 }
1128 }
1129
1130 hdsp->system_sample_rate = rate;
1131
1132 return 0;
1133 }
1134
1135 /*----------------------------------------------------------------------------
1136 MIDI
1137 ----------------------------------------------------------------------------*/
1138
1139 static unsigned char snd_hdsp_midi_read_byte (hdsp_t *hdsp, int id)
1140 {
1141 /* the hardware already does the relevant bit-mask with 0xff */
1142 if (id) {
1143 return hdsp_read(hdsp, HDSP_midiDataIn1);
1144 } else {
1145 return hdsp_read(hdsp, HDSP_midiDataIn0);
1146 }
1147 }
1148
1149 static void snd_hdsp_midi_write_byte (hdsp_t *hdsp, int id, int val)
1150 {
1151 /* the hardware already does the relevant bit-mask with 0xff */
1152 if (id) {
1153 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1154 } else {
1155 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1156 }
1157 }
1158
1159 static int snd_hdsp_midi_input_available (hdsp_t *hdsp, int id)
1160 {
1161 if (id) {
1162 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1163 } else {
1164 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1165 }
1166 }
1167
1168 static int snd_hdsp_midi_output_possible (hdsp_t *hdsp, int id)
1169 {
1170 int fifo_bytes_used;
1171
1172 if (id) {
1173 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1174 } else {
1175 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1176 }
1177
1178 if (fifo_bytes_used < 128) {
1179 return 128 - fifo_bytes_used;
1180 } else {
1181 return 0;
1182 }
1183 }
1184
1185 static void snd_hdsp_flush_midi_input (hdsp_t *hdsp, int id)
1186 {
1187 while (snd_hdsp_midi_input_available (hdsp, id)) {
1188 snd_hdsp_midi_read_byte (hdsp, id);
1189 }
1190 }
1191
1192 static int snd_hdsp_midi_output_write (hdsp_midi_t *hmidi)
1193 {
1194 unsigned long flags;
1195 int n_pending;
1196 int to_write;
1197 int i;
1198 unsigned char buf[128];
1199
1200 /* Output is not interrupt driven */
1201
1202 spin_lock_irqsave (&hmidi->lock, flags);
1203 if (hmidi->output) {
1204 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1205 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1206 if (n_pending > (int)sizeof (buf))
1207 n_pending = sizeof (buf);
1208
1209 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1210 for (i = 0; i < to_write; ++i)
1211 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1212 }
1213 }
1214 }
1215 }
1216 spin_unlock_irqrestore (&hmidi->lock, flags);
1217 return 0;
1218 }
1219
1220 static int snd_hdsp_midi_input_read (hdsp_midi_t *hmidi)
1221 {
1222 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1223 unsigned long flags;
1224 int n_pending;
1225 int i;
1226
1227 spin_lock_irqsave (&hmidi->lock, flags);
1228 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1229 if (hmidi->input) {
1230 if (n_pending > (int)sizeof (buf)) {
1231 n_pending = sizeof (buf);
1232 }
1233 for (i = 0; i < n_pending; ++i) {
1234 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1235 }
1236 if (n_pending) {
1237 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1238 }
1239 } else {
1240 /* flush the MIDI input FIFO */
1241 while (--n_pending) {
1242 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1243 }
1244 }
1245 }
1246 hmidi->pending = 0;
1247 if (hmidi->id) {
1248 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1249 } else {
1250 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1251 }
1252 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1253 spin_unlock_irqrestore (&hmidi->lock, flags);
1254 return snd_hdsp_midi_output_write (hmidi);
1255 }
1256
1257 static void snd_hdsp_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
1258 {
1259 hdsp_t *hdsp;
1260 hdsp_midi_t *hmidi;
1261 unsigned long flags;
1262 u32 ie;
1263
1264 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1265 hdsp = hmidi->hdsp;
1266 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1267 spin_lock_irqsave (&hdsp->lock, flags);
1268 if (up) {
1269 if (!(hdsp->control_register & ie)) {
1270 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1271 hdsp->control_register |= ie;
1272 }
1273 } else {
1274 hdsp->control_register &= ~ie;
1275 tasklet_kill(&hdsp->midi_tasklet);
1276 }
1277
1278 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1279 spin_unlock_irqrestore (&hdsp->lock, flags);
1280 }
1281
1282 static void snd_hdsp_midi_output_timer(unsigned long data)
1283 {
1284 hdsp_midi_t *hmidi = (hdsp_midi_t *) data;
1285 unsigned long flags;
1286
1287 snd_hdsp_midi_output_write(hmidi);
1288 spin_lock_irqsave (&hmidi->lock, flags);
1289
1290 /* this does not bump hmidi->istimer, because the
1291 kernel automatically removed the timer when it
1292 expired, and we are now adding it back, thus
1293 leaving istimer wherever it was set before.
1294 */
1295
1296 if (hmidi->istimer) {
1297 hmidi->timer.expires = 1 + jiffies;
1298 add_timer(&hmidi->timer);
1299 }
1300
1301 spin_unlock_irqrestore (&hmidi->lock, flags);
1302 }
1303
1304 static void snd_hdsp_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
1305 {
1306 hdsp_midi_t *hmidi;
1307 unsigned long flags;
1308
1309 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1310 spin_lock_irqsave (&hmidi->lock, flags);
1311 if (up) {
1312 if (!hmidi->istimer) {
1313 init_timer(&hmidi->timer);
1314 hmidi->timer.function = snd_hdsp_midi_output_timer;
1315 hmidi->timer.data = (unsigned long) hmidi;
1316 hmidi->timer.expires = 1 + jiffies;
1317 add_timer(&hmidi->timer);
1318 hmidi->istimer++;
1319 }
1320 } else {
1321 if (hmidi->istimer && --hmidi->istimer <= 0) {
1322 del_timer (&hmidi->timer);
1323 }
1324 }
1325 spin_unlock_irqrestore (&hmidi->lock, flags);
1326 if (up)
1327 snd_hdsp_midi_output_write(hmidi);
1328 }
1329
1330 static int snd_hdsp_midi_input_open(snd_rawmidi_substream_t * substream)
1331 {
1332 hdsp_midi_t *hmidi;
1333
1334 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1335 spin_lock_irq (&hmidi->lock);
1336 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1337 hmidi->input = substream;
1338 spin_unlock_irq (&hmidi->lock);
1339
1340 return 0;
1341 }
1342
1343 static int snd_hdsp_midi_output_open(snd_rawmidi_substream_t * substream)
1344 {
1345 hdsp_midi_t *hmidi;
1346
1347 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1348 spin_lock_irq (&hmidi->lock);
1349 hmidi->output = substream;
1350 spin_unlock_irq (&hmidi->lock);
1351
1352 return 0;
1353 }
1354
1355 static int snd_hdsp_midi_input_close(snd_rawmidi_substream_t * substream)
1356 {
1357 hdsp_midi_t *hmidi;
1358
1359 snd_hdsp_midi_input_trigger (substream, 0);
1360
1361 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1362 spin_lock_irq (&hmidi->lock);
1363 hmidi->input = NULL;
1364 spin_unlock_irq (&hmidi->lock);
1365
1366 return 0;
1367 }
1368
1369 static int snd_hdsp_midi_output_close(snd_rawmidi_substream_t * substream)
1370 {
1371 hdsp_midi_t *hmidi;
1372
1373 snd_hdsp_midi_output_trigger (substream, 0);
1374
1375 hmidi = (hdsp_midi_t *) substream->rmidi->private_data;
1376 spin_lock_irq (&hmidi->lock);
1377 hmidi->output = NULL;
1378 spin_unlock_irq (&hmidi->lock);
1379
1380 return 0;
1381 }
1382
1383 static snd_rawmidi_ops_t snd_hdsp_midi_output =
1384 {
1385 .open = snd_hdsp_midi_output_open,
1386 .close = snd_hdsp_midi_output_close,
1387 .trigger = snd_hdsp_midi_output_trigger,
1388 };
1389
1390 static snd_rawmidi_ops_t snd_hdsp_midi_input =
1391 {
1392 .open = snd_hdsp_midi_input_open,
1393 .close = snd_hdsp_midi_input_close,
1394 .trigger = snd_hdsp_midi_input_trigger,
1395 };
1396
1397 static int __devinit snd_hdsp_create_midi (snd_card_t *card, hdsp_t *hdsp, int id)
1398 {
1399 char buf[32];
1400
1401 hdsp->midi[id].id = id;
1402 hdsp->midi[id].rmidi = NULL;
1403 hdsp->midi[id].input = NULL;
1404 hdsp->midi[id].output = NULL;
1405 hdsp->midi[id].hdsp = hdsp;
1406 hdsp->midi[id].istimer = 0;
1407 hdsp->midi[id].pending = 0;
1408 spin_lock_init (&hdsp->midi[id].lock);
1409
1410 sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1411 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) {
1412 return -1;
1413 }
1414
1415 sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1416 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1417
1418 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1419 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1420
1421 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1422 SNDRV_RAWMIDI_INFO_INPUT |
1423 SNDRV_RAWMIDI_INFO_DUPLEX;
1424
1425 return 0;
1426 }
1427
1428 /*-----------------------------------------------------------------------------
1429 Control Interface
1430 ----------------------------------------------------------------------------*/
1431
1432 static u32 snd_hdsp_convert_from_aes(snd_aes_iec958_t *aes)
1433 {
1434 u32 val = 0;
1435 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1436 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1437 if (val & HDSP_SPDIFProfessional)
1438 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1439 else
1440 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1441 return val;
1442 }
1443
1444 static void snd_hdsp_convert_to_aes(snd_aes_iec958_t *aes, u32 val)
1445 {
1446 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1447 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1448 if (val & HDSP_SPDIFProfessional)
1449 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1450 else
1451 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1452 }
1453
1454 static int snd_hdsp_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1455 {
1456 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1457 uinfo->count = 1;
1458 return 0;
1459 }
1460
1461 static int snd_hdsp_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1462 {
1463 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1464
1465 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1466 return 0;
1467 }
1468
1469 static int snd_hdsp_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1470 {
1471 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1472 int change;
1473 u32 val;
1474
1475 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1476 spin_lock_irq(&hdsp->lock);
1477 change = val != hdsp->creg_spdif;
1478 hdsp->creg_spdif = val;
1479 spin_unlock_irq(&hdsp->lock);
1480 return change;
1481 }
1482
1483 static int snd_hdsp_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1484 {
1485 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1486 uinfo->count = 1;
1487 return 0;
1488 }
1489
1490 static int snd_hdsp_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1491 {
1492 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1493
1494 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1495 return 0;
1496 }
1497
1498 static int snd_hdsp_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1499 {
1500 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1501 int change;
1502 u32 val;
1503
1504 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1505 spin_lock_irq(&hdsp->lock);
1506 change = val != hdsp->creg_spdif_stream;
1507 hdsp->creg_spdif_stream = val;
1508 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1509 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1510 spin_unlock_irq(&hdsp->lock);
1511 return change;
1512 }
1513
1514 static int snd_hdsp_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1515 {
1516 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1517 uinfo->count = 1;
1518 return 0;
1519 }
1520
1521 static int snd_hdsp_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1522 {
1523 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1524 return 0;
1525 }
1526
1527 #define HDSP_SPDIF_IN(xname, xindex) \
1528 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1529 .name = xname, \
1530 .index = xindex, \
1531 .info = snd_hdsp_info_spdif_in, \
1532 .get = snd_hdsp_get_spdif_in, \
1533 .put = snd_hdsp_put_spdif_in }
1534
1535 static unsigned int hdsp_spdif_in(hdsp_t *hdsp)
1536 {
1537 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1538 }
1539
1540 static int hdsp_set_spdif_input(hdsp_t *hdsp, int in)
1541 {
1542 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1543 hdsp->control_register |= hdsp_encode_spdif_in(in);
1544 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1545 return 0;
1546 }
1547
1548 static int snd_hdsp_info_spdif_in(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1549 {
1550 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1551 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1552
1553 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1554 uinfo->count = 1;
1555 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1556 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1557 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1558 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1559 return 0;
1560 }
1561
1562 static int snd_hdsp_get_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1563 {
1564 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1565
1566 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1567 return 0;
1568 }
1569
1570 static int snd_hdsp_put_spdif_in(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1571 {
1572 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1573 int change;
1574 unsigned int val;
1575
1576 if (!snd_hdsp_use_is_exclusive(hdsp))
1577 return -EBUSY;
1578 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1579 spin_lock_irq(&hdsp->lock);
1580 change = val != hdsp_spdif_in(hdsp);
1581 if (change)
1582 hdsp_set_spdif_input(hdsp, val);
1583 spin_unlock_irq(&hdsp->lock);
1584 return change;
1585 }
1586
1587 #define HDSP_SPDIF_OUT(xname, xindex) \
1588 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1589 .info = snd_hdsp_info_spdif_bits, \
1590 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1591
1592 static int hdsp_spdif_out(hdsp_t *hdsp)
1593 {
1594 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1595 }
1596
1597 static int hdsp_set_spdif_output(hdsp_t *hdsp, int out)
1598 {
1599 if (out) {
1600 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1601 } else {
1602 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1603 }
1604 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1605 return 0;
1606 }
1607
1608 static int snd_hdsp_info_spdif_bits(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1609 {
1610 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1611 uinfo->count = 1;
1612 uinfo->value.integer.min = 0;
1613 uinfo->value.integer.max = 1;
1614 return 0;
1615 }
1616
1617 static int snd_hdsp_get_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1618 {
1619 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1620
1621 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1622 return 0;
1623 }
1624
1625 static int snd_hdsp_put_spdif_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1626 {
1627 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1628 int change;
1629 unsigned int val;
1630
1631 if (!snd_hdsp_use_is_exclusive(hdsp))
1632 return -EBUSY;
1633 val = ucontrol->value.integer.value[0] & 1;
1634 spin_lock_irq(&hdsp->lock);
1635 change = (int)val != hdsp_spdif_out(hdsp);
1636 hdsp_set_spdif_output(hdsp, val);
1637 spin_unlock_irq(&hdsp->lock);
1638 return change;
1639 }
1640
1641 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1642 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1643 .info = snd_hdsp_info_spdif_bits, \
1644 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1645
1646 static int hdsp_spdif_professional(hdsp_t *hdsp)
1647 {
1648 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1649 }
1650
1651 static int hdsp_set_spdif_professional(hdsp_t *hdsp, int val)
1652 {
1653 if (val) {
1654 hdsp->control_register |= HDSP_SPDIFProfessional;
1655 } else {
1656 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1657 }
1658 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1659 return 0;
1660 }
1661
1662 static int snd_hdsp_get_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1663 {
1664 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1665
1666 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1667 return 0;
1668 }
1669
1670 static int snd_hdsp_put_spdif_professional(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1671 {
1672 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1673 int change;
1674 unsigned int val;
1675
1676 if (!snd_hdsp_use_is_exclusive(hdsp))
1677 return -EBUSY;
1678 val = ucontrol->value.integer.value[0] & 1;
1679 spin_lock_irq(&hdsp->lock);
1680 change = (int)val != hdsp_spdif_professional(hdsp);
1681 hdsp_set_spdif_professional(hdsp, val);
1682 spin_unlock_irq(&hdsp->lock);
1683 return change;
1684 }
1685
1686 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1687 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1688 .info = snd_hdsp_info_spdif_bits, \
1689 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1690
1691 static int hdsp_spdif_emphasis(hdsp_t *hdsp)
1692 {
1693 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1694 }
1695
1696 static int hdsp_set_spdif_emphasis(hdsp_t *hdsp, int val)
1697 {
1698 if (val) {
1699 hdsp->control_register |= HDSP_SPDIFEmphasis;
1700 } else {
1701 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1702 }
1703 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1704 return 0;
1705 }
1706
1707 static int snd_hdsp_get_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1708 {
1709 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1710
1711 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1712 return 0;
1713 }
1714
1715 static int snd_hdsp_put_spdif_emphasis(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1716 {
1717 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1718 int change;
1719 unsigned int val;
1720
1721 if (!snd_hdsp_use_is_exclusive(hdsp))
1722 return -EBUSY;
1723 val = ucontrol->value.integer.value[0] & 1;
1724 spin_lock_irq(&hdsp->lock);
1725 change = (int)val != hdsp_spdif_emphasis(hdsp);
1726 hdsp_set_spdif_emphasis(hdsp, val);
1727 spin_unlock_irq(&hdsp->lock);
1728 return change;
1729 }
1730
1731 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1732 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, .name = xname, .index = xindex, \
1733 .info = snd_hdsp_info_spdif_bits, \
1734 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1735
1736 static int hdsp_spdif_nonaudio(hdsp_t *hdsp)
1737 {
1738 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1739 }
1740
1741 static int hdsp_set_spdif_nonaudio(hdsp_t *hdsp, int val)
1742 {
1743 if (val) {
1744 hdsp->control_register |= HDSP_SPDIFNonAudio;
1745 } else {
1746 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1747 }
1748 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1749 return 0;
1750 }
1751
1752 static int snd_hdsp_get_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1753 {
1754 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1755
1756 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1757 return 0;
1758 }
1759
1760 static int snd_hdsp_put_spdif_nonaudio(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1761 {
1762 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1763 int change;
1764 unsigned int val;
1765
1766 if (!snd_hdsp_use_is_exclusive(hdsp))
1767 return -EBUSY;
1768 val = ucontrol->value.integer.value[0] & 1;
1769 spin_lock_irq(&hdsp->lock);
1770 change = (int)val != hdsp_spdif_nonaudio(hdsp);
1771 hdsp_set_spdif_nonaudio(hdsp, val);
1772 spin_unlock_irq(&hdsp->lock);
1773 return change;
1774 }
1775
1776 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1777 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1778 .name = xname, \
1779 .index = xindex, \
1780 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1781 .info = snd_hdsp_info_spdif_sample_rate, \
1782 .get = snd_hdsp_get_spdif_sample_rate \
1783 }
1784
1785 static int snd_hdsp_info_spdif_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1786 {
1787 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1788 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1789
1790 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1791 uinfo->count = 1;
1792 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1793 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1794 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1795 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1796 return 0;
1797 }
1798
1799 static int snd_hdsp_get_spdif_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1800 {
1801 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1802
1803 switch (hdsp_spdif_sample_rate(hdsp)) {
1804 case 32000:
1805 ucontrol->value.enumerated.item[0] = 0;
1806 break;
1807 case 44100:
1808 ucontrol->value.enumerated.item[0] = 1;
1809 break;
1810 case 48000:
1811 ucontrol->value.enumerated.item[0] = 2;
1812 break;
1813 case 64000:
1814 ucontrol->value.enumerated.item[0] = 3;
1815 break;
1816 case 88200:
1817 ucontrol->value.enumerated.item[0] = 4;
1818 break;
1819 case 96000:
1820 ucontrol->value.enumerated.item[0] = 5;
1821 break;
1822 case 128000:
1823 ucontrol->value.enumerated.item[0] = 7;
1824 break;
1825 case 176400:
1826 ucontrol->value.enumerated.item[0] = 8;
1827 break;
1828 case 192000:
1829 ucontrol->value.enumerated.item[0] = 9;
1830 break;
1831 default:
1832 ucontrol->value.enumerated.item[0] = 6;
1833 }
1834 return 0;
1835 }
1836
1837 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1838 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1839 .name = xname, \
1840 .index = xindex, \
1841 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1842 .info = snd_hdsp_info_system_sample_rate, \
1843 .get = snd_hdsp_get_system_sample_rate \
1844 }
1845
1846 static int snd_hdsp_info_system_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1847 {
1848 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1849 uinfo->count = 1;
1850 return 0;
1851 }
1852
1853 static int snd_hdsp_get_system_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1854 {
1855 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1856
1857 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1858 return 0;
1859 }
1860
1861 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1862 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1863 .name = xname, \
1864 .index = xindex, \
1865 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1866 .info = snd_hdsp_info_autosync_sample_rate, \
1867 .get = snd_hdsp_get_autosync_sample_rate \
1868 }
1869
1870 static int snd_hdsp_info_autosync_sample_rate(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1871 {
1872 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1873 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1874 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1875 uinfo->count = 1;
1876 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1877 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1878 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1879 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1880 return 0;
1881 }
1882
1883 static int snd_hdsp_get_autosync_sample_rate(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1884 {
1885 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1886
1887 switch (hdsp_external_sample_rate(hdsp)) {
1888 case 32000:
1889 ucontrol->value.enumerated.item[0] = 0;
1890 break;
1891 case 44100:
1892 ucontrol->value.enumerated.item[0] = 1;
1893 break;
1894 case 48000:
1895 ucontrol->value.enumerated.item[0] = 2;
1896 break;
1897 case 64000:
1898 ucontrol->value.enumerated.item[0] = 3;
1899 break;
1900 case 88200:
1901 ucontrol->value.enumerated.item[0] = 4;
1902 break;
1903 case 96000:
1904 ucontrol->value.enumerated.item[0] = 5;
1905 break;
1906 case 128000:
1907 ucontrol->value.enumerated.item[0] = 7;
1908 break;
1909 case 176400:
1910 ucontrol->value.enumerated.item[0] = 8;
1911 break;
1912 case 192000:
1913 ucontrol->value.enumerated.item[0] = 9;
1914 break;
1915 default:
1916 ucontrol->value.enumerated.item[0] = 6;
1917 }
1918 return 0;
1919 }
1920
1921 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1922 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
1923 .name = xname, \
1924 .index = xindex, \
1925 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1926 .info = snd_hdsp_info_system_clock_mode, \
1927 .get = snd_hdsp_get_system_clock_mode \
1928 }
1929
1930 static int hdsp_system_clock_mode(hdsp_t *hdsp)
1931 {
1932 if (hdsp->control_register & HDSP_ClockModeMaster) {
1933 return 0;
1934 } else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) {
1935 return 0;
1936 }
1937 return 1;
1938 }
1939
1940 static int snd_hdsp_info_system_clock_mode(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1941 {
1942 static char *texts[] = {"Master", "Slave" };
1943
1944 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1945 uinfo->count = 1;
1946 uinfo->value.enumerated.items = 2;
1947 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1948 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1949 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1950 return 0;
1951 }
1952
1953 static int snd_hdsp_get_system_clock_mode(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1954 {
1955 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
1956
1957 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1958 return 0;
1959 }
1960
1961 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1962 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, \
1963 .name = xname, \
1964 .index = xindex, \
1965 .info = snd_hdsp_info_clock_source, \
1966 .get = snd_hdsp_get_clock_source, \
1967 .put = snd_hdsp_put_clock_source \
1968 }
1969
1970 static int hdsp_clock_source(hdsp_t *hdsp)
1971 {
1972 if (hdsp->control_register & HDSP_ClockModeMaster) {
1973 switch (hdsp->system_sample_rate) {
1974 case 32000:
1975 return 1;
1976 case 44100:
1977 return 2;
1978 case 48000:
1979 return 3;
1980 case 64000:
1981 return 4;
1982 case 88200:
1983 return 5;
1984 case 96000:
1985 return 6;
1986 case 128000:
1987 return 7;
1988 case 176400:
1989 return 8;
1990 case 192000:
1991 return 9;
1992 default:
1993 return 3;
1994 }
1995 } else {
1996 return 0;
1997 }
1998 }
1999
2000 static int hdsp_set_clock_source(hdsp_t *hdsp, int mode)
2001 {
2002 int rate;
2003 switch (mode) {
2004 case HDSP_CLOCK_SOURCE_AUTOSYNC:
2005 if (hdsp_external_sample_rate(hdsp) != 0) {
2006 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2007 hdsp->control_register &= ~HDSP_ClockModeMaster;
2008 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2009 return 0;
2010 }
2011 }
2012 return -1;
2013 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2014 rate = 32000;
2015 break;
2016 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2017 rate = 44100;
2018 break;
2019 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2020 rate = 48000;
2021 break;
2022 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2023 rate = 64000;
2024 break;
2025 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2026 rate = 88200;
2027 break;
2028 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2029 rate = 96000;
2030 break;
2031 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2032 rate = 128000;
2033 break;
2034 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2035 rate = 176400;
2036 break;
2037 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2038 rate = 192000;
2039 break;
2040 default:
2041 rate = 48000;
2042 }
2043 hdsp->control_register |= HDSP_ClockModeMaster;
2044 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2045 hdsp_set_rate(hdsp, rate, 1);
2046 return 0;
2047 }
2048
2049 static int snd_hdsp_info_clock_source(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2050 {
2051 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2052 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2053
2054 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2055 uinfo->count = 1;
2056 if (hdsp->io_type == H9632)
2057 uinfo->value.enumerated.items = 10;
2058 else
2059 uinfo->value.enumerated.items = 7;
2060 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2061 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2062 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2063 return 0;
2064 }
2065
2066 static int snd_hdsp_get_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2067 {
2068 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2069
2070 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2071 return 0;
2072 }
2073
2074 static int snd_hdsp_put_clock_source(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2075 {
2076 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2077 int change;
2078 int val;
2079
2080 if (!snd_hdsp_use_is_exclusive(hdsp))
2081 return -EBUSY;
2082 val = ucontrol->value.enumerated.item[0];
2083 if (val < 0) val = 0;
2084 if (hdsp->io_type == H9632) {
2085 if (val > 9) val = 9;
2086 } else {
2087 if (val > 6) val = 6;
2088 }
2089 spin_lock_irq(&hdsp->lock);
2090 if (val != hdsp_clock_source(hdsp)) {
2091 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2092 } else {
2093 change = 0;
2094 }
2095 spin_unlock_irq(&hdsp->lock);
2096 return change;
2097 }
2098
2099 static int snd_hdsp_info_clock_source_lock(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2100 {
2101 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2102 uinfo->count = 1;
2103 uinfo->value.integer.min = 0;
2104 uinfo->value.integer.max = 1;
2105 return 0;
2106 }
2107
2108 static int snd_hdsp_get_clock_source_lock(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2109 {
2110 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2111
2112 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2113 return 0;
2114 }
2115
2116 static int snd_hdsp_put_clock_source_lock(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2117 {
2118 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2119 int change;
2120
2121 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2122 if (change)
2123 hdsp->clock_source_locked = ucontrol->value.integer.value[0];
2124 return change;
2125 }
2126
2127 #define HDSP_DA_GAIN(xname, xindex) \
2128 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2129 .name = xname, \
2130 .index = xindex, \
2131 .info = snd_hdsp_info_da_gain, \
2132 .get = snd_hdsp_get_da_gain, \
2133 .put = snd_hdsp_put_da_gain \
2134 }
2135
2136 static int hdsp_da_gain(hdsp_t *hdsp)
2137 {
2138 switch (hdsp->control_register & HDSP_DAGainMask) {
2139 case HDSP_DAGainHighGain:
2140 return 0;
2141 case HDSP_DAGainPlus4dBu:
2142 return 1;
2143 case HDSP_DAGainMinus10dBV:
2144 return 2;
2145 default:
2146 return 1;
2147 }
2148 }
2149
2150 static int hdsp_set_da_gain(hdsp_t *hdsp, int mode)
2151 {
2152 hdsp->control_register &= ~HDSP_DAGainMask;
2153 switch (mode) {
2154 case 0:
2155 hdsp->control_register |= HDSP_DAGainHighGain;
2156 break;
2157 case 1:
2158 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2159 break;
2160 case 2:
2161 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2162 break;
2163 default:
2164 return -1;
2165
2166 }
2167 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2168 return 0;
2169 }
2170
2171 static int snd_hdsp_info_da_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2172 {
2173 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2174
2175 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2176 uinfo->count = 1;
2177 uinfo->value.enumerated.items = 3;
2178 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2179 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2180 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2181 return 0;
2182 }
2183
2184 static int snd_hdsp_get_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2185 {
2186 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2187
2188 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2189 return 0;
2190 }
2191
2192 static int snd_hdsp_put_da_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2193 {
2194 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2195 int change;
2196 int val;
2197
2198 if (!snd_hdsp_use_is_exclusive(hdsp))
2199 return -EBUSY;
2200 val = ucontrol->value.enumerated.item[0];
2201 if (val < 0) val = 0;
2202 if (val > 2) val = 2;
2203 spin_lock_irq(&hdsp->lock);
2204 if (val != hdsp_da_gain(hdsp)) {
2205 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2206 } else {
2207 change = 0;
2208 }
2209 spin_unlock_irq(&hdsp->lock);
2210 return change;
2211 }
2212
2213 #define HDSP_AD_GAIN(xname, xindex) \
2214 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2215 .name = xname, \
2216 .index = xindex, \
2217 .info = snd_hdsp_info_ad_gain, \
2218 .get = snd_hdsp_get_ad_gain, \
2219 .put = snd_hdsp_put_ad_gain \
2220 }
2221
2222 static int hdsp_ad_gain(hdsp_t *hdsp)
2223 {
2224 switch (hdsp->control_register & HDSP_ADGainMask) {
2225 case HDSP_ADGainMinus10dBV:
2226 return 0;
2227 case HDSP_ADGainPlus4dBu:
2228 return 1;
2229 case HDSP_ADGainLowGain:
2230 return 2;
2231 default:
2232 return 1;
2233 }
2234 }
2235
2236 static int hdsp_set_ad_gain(hdsp_t *hdsp, int mode)
2237 {
2238 hdsp->control_register &= ~HDSP_ADGainMask;
2239 switch (mode) {
2240 case 0:
2241 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2242 break;
2243 case 1:
2244 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2245 break;
2246 case 2:
2247 hdsp->control_register |= HDSP_ADGainLowGain;
2248 break;
2249 default:
2250 return -1;
2251
2252 }
2253 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2254 return 0;
2255 }
2256
2257 static int snd_hdsp_info_ad_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2258 {
2259 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2260
2261 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2262 uinfo->count = 1;
2263 uinfo->value.enumerated.items = 3;
2264 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2265 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2266 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2267 return 0;
2268 }
2269
2270 static int snd_hdsp_get_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2271 {
2272 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2273
2274 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2275 return 0;
2276 }
2277
2278 static int snd_hdsp_put_ad_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2279 {
2280 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2281 int change;
2282 int val;
2283
2284 if (!snd_hdsp_use_is_exclusive(hdsp))
2285 return -EBUSY;
2286 val = ucontrol->value.enumerated.item[0];
2287 if (val < 0) val = 0;
2288 if (val > 2) val = 2;
2289 spin_lock_irq(&hdsp->lock);
2290 if (val != hdsp_ad_gain(hdsp)) {
2291 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2292 } else {
2293 change = 0;
2294 }
2295 spin_unlock_irq(&hdsp->lock);
2296 return change;
2297 }
2298
2299 #define HDSP_PHONE_GAIN(xname, xindex) \
2300 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2301 .name = xname, \
2302 .index = xindex, \
2303 .info = snd_hdsp_info_phone_gain, \
2304 .get = snd_hdsp_get_phone_gain, \
2305 .put = snd_hdsp_put_phone_gain \
2306 }
2307
2308 static int hdsp_phone_gain(hdsp_t *hdsp)
2309 {
2310 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2311 case HDSP_PhoneGain0dB:
2312 return 0;
2313 case HDSP_PhoneGainMinus6dB:
2314 return 1;
2315 case HDSP_PhoneGainMinus12dB:
2316 return 2;
2317 default:
2318 return 0;
2319 }
2320 }
2321
2322 static int hdsp_set_phone_gain(hdsp_t *hdsp, int mode)
2323 {
2324 hdsp->control_register &= ~HDSP_PhoneGainMask;
2325 switch (mode) {
2326 case 0:
2327 hdsp->control_register |= HDSP_PhoneGain0dB;
2328 break;
2329 case 1:
2330 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2331 break;
2332 case 2:
2333 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2334 break;
2335 default:
2336 return -1;
2337
2338 }
2339 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2340 return 0;
2341 }
2342
2343 static int snd_hdsp_info_phone_gain(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2344 {
2345 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2346
2347 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2348 uinfo->count = 1;
2349 uinfo->value.enumerated.items = 3;
2350 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2351 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2352 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2353 return 0;
2354 }
2355
2356 static int snd_hdsp_get_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2357 {
2358 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2359
2360 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2361 return 0;
2362 }
2363
2364 static int snd_hdsp_put_phone_gain(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2365 {
2366 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2367 int change;
2368 int val;
2369
2370 if (!snd_hdsp_use_is_exclusive(hdsp))
2371 return -EBUSY;
2372 val = ucontrol->value.enumerated.item[0];
2373 if (val < 0) val = 0;
2374 if (val > 2) val = 2;
2375 spin_lock_irq(&hdsp->lock);
2376 if (val != hdsp_phone_gain(hdsp)) {
2377 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2378 } else {
2379 change = 0;
2380 }
2381 spin_unlock_irq(&hdsp->lock);
2382 return change;
2383 }
2384
2385 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2386 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2387 .name = xname, \
2388 .index = xindex, \
2389 .info = snd_hdsp_info_xlr_breakout_cable, \
2390 .get = snd_hdsp_get_xlr_breakout_cable, \
2391 .put = snd_hdsp_put_xlr_breakout_cable \
2392 }
2393
2394 static int hdsp_xlr_breakout_cable(hdsp_t *hdsp)
2395 {
2396 if (hdsp->control_register & HDSP_XLRBreakoutCable) {
2397 return 1;
2398 }
2399 return 0;
2400 }
2401
2402 static int hdsp_set_xlr_breakout_cable(hdsp_t *hdsp, int mode)
2403 {
2404 if (mode) {
2405 hdsp->control_register |= HDSP_XLRBreakoutCable;
2406 } else {
2407 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2408 }
2409 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2410 return 0;
2411 }
2412
2413 static int snd_hdsp_info_xlr_breakout_cable(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2414 {
2415 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2416 uinfo->count = 1;
2417 uinfo->value.integer.min = 0;
2418 uinfo->value.integer.max = 1;
2419 return 0;
2420 }
2421
2422 static int snd_hdsp_get_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2423 {
2424 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2425
2426 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2427 return 0;
2428 }
2429
2430 static int snd_hdsp_put_xlr_breakout_cable(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2431 {
2432 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2433 int change;
2434 int val;
2435
2436 if (!snd_hdsp_use_is_exclusive(hdsp))
2437 return -EBUSY;
2438 val = ucontrol->value.integer.value[0] & 1;
2439 spin_lock_irq(&hdsp->lock);
2440 change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2441 hdsp_set_xlr_breakout_cable(hdsp, val);
2442 spin_unlock_irq(&hdsp->lock);
2443 return change;
2444 }
2445
2446 /* (De)activates old RME Analog Extension Board
2447 These are connected to the internal ADAT connector
2448 Switching this on desactivates external ADAT
2449 */
2450 #define HDSP_AEB(xname, xindex) \
2451 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2452 .name = xname, \
2453 .index = xindex, \
2454 .info = snd_hdsp_info_aeb, \
2455 .get = snd_hdsp_get_aeb, \
2456 .put = snd_hdsp_put_aeb \
2457 }
2458
2459 static int hdsp_aeb(hdsp_t *hdsp)
2460 {
2461 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
2462 return 1;
2463 }
2464 return 0;
2465 }
2466
2467 static int hdsp_set_aeb(hdsp_t *hdsp, int mode)
2468 {
2469 if (mode) {
2470 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2471 } else {
2472 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2473 }
2474 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2475 return 0;
2476 }
2477
2478 static int snd_hdsp_info_aeb(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2479 {
2480 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2481 uinfo->count = 1;
2482 uinfo->value.integer.min = 0;
2483 uinfo->value.integer.max = 1;
2484 return 0;
2485 }
2486
2487 static int snd_hdsp_get_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2488 {
2489 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2490
2491 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2492 return 0;
2493 }
2494
2495 static int snd_hdsp_put_aeb(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2496 {
2497 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2498 int change;
2499 int val;
2500
2501 if (!snd_hdsp_use_is_exclusive(hdsp))
2502 return -EBUSY;
2503 val = ucontrol->value.integer.value[0] & 1;
2504 spin_lock_irq(&hdsp->lock);
2505 change = (int)val != hdsp_aeb(hdsp);
2506 hdsp_set_aeb(hdsp, val);
2507 spin_unlock_irq(&hdsp->lock);
2508 return change;
2509 }
2510
2511 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2512 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2513 .name = xname, \
2514 .index = xindex, \
2515 .info = snd_hdsp_info_pref_sync_ref, \
2516 .get = snd_hdsp_get_pref_sync_ref, \
2517 .put = snd_hdsp_put_pref_sync_ref \
2518 }
2519
2520 static int hdsp_pref_sync_ref(hdsp_t *hdsp)
2521 {
2522 /* Notice that this looks at the requested sync source,
2523 not the one actually in use.
2524 */
2525
2526 switch (hdsp->control_register & HDSP_SyncRefMask) {
2527 case HDSP_SyncRef_ADAT1:
2528 return HDSP_SYNC_FROM_ADAT1;
2529 case HDSP_SyncRef_ADAT2:
2530 return HDSP_SYNC_FROM_ADAT2;
2531 case HDSP_SyncRef_ADAT3:
2532 return HDSP_SYNC_FROM_ADAT3;
2533 case HDSP_SyncRef_SPDIF:
2534 return HDSP_SYNC_FROM_SPDIF;
2535 case HDSP_SyncRef_WORD:
2536 return HDSP_SYNC_FROM_WORD;
2537 case HDSP_SyncRef_ADAT_SYNC:
2538 return HDSP_SYNC_FROM_ADAT_SYNC;
2539 default:
2540 return HDSP_SYNC_FROM_WORD;
2541 }
2542 return 0;
2543 }
2544
2545 static int hdsp_set_pref_sync_ref(hdsp_t *hdsp, int pref)
2546 {
2547 hdsp->control_register &= ~HDSP_SyncRefMask;
2548 switch (pref) {
2549 case HDSP_SYNC_FROM_ADAT1:
2550 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2551 break;
2552 case HDSP_SYNC_FROM_ADAT2:
2553 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2554 break;
2555 case HDSP_SYNC_FROM_ADAT3:
2556 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2557 break;
2558 case HDSP_SYNC_FROM_SPDIF:
2559 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2560 break;
2561 case HDSP_SYNC_FROM_WORD:
2562 hdsp->control_register |= HDSP_SyncRef_WORD;
2563 break;
2564 case HDSP_SYNC_FROM_ADAT_SYNC:
2565 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2566 break;
2567 default:
2568 return -1;
2569 }
2570 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2571 return 0;
2572 }
2573
2574 static int snd_hdsp_info_pref_sync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2575 {
2576 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2577 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2578
2579 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2580 uinfo->count = 1;
2581
2582 switch (hdsp->io_type) {
2583 case Digiface:
2584 case H9652:
2585 uinfo->value.enumerated.items = 6;
2586 break;
2587 case Multiface:
2588 uinfo->value.enumerated.items = 4;
2589 break;
2590 case H9632:
2591 uinfo->value.enumerated.items = 3;
2592 break;
2593 default:
2594 uinfo->value.enumerated.items = 0;
2595 break;
2596 }
2597
2598 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2599 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2600 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2601 return 0;
2602 }
2603
2604 static int snd_hdsp_get_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2605 {
2606 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2607
2608 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2609 return 0;
2610 }
2611
2612 static int snd_hdsp_put_pref_sync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2613 {
2614 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2615 int change, max;
2616 unsigned int val;
2617
2618 if (!snd_hdsp_use_is_exclusive(hdsp))
2619 return -EBUSY;
2620
2621 switch (hdsp->io_type) {
2622 case Digiface:
2623 case H9652:
2624 max = 6;
2625 break;
2626 case Multiface:
2627 max = 4;
2628 break;
2629 case H9632:
2630 max = 3;
2631 break;
2632 default:
2633 return -EIO;
2634 }
2635
2636 val = ucontrol->value.enumerated.item[0] % max;
2637 spin_lock_irq(&hdsp->lock);
2638 change = (int)val != hdsp_pref_sync_ref(hdsp);
2639 hdsp_set_pref_sync_ref(hdsp, val);
2640 spin_unlock_irq(&hdsp->lock);
2641 return change;
2642 }
2643
2644 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2645 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2646 .name = xname, \
2647 .index = xindex, \
2648 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2649 .info = snd_hdsp_info_autosync_ref, \
2650 .get = snd_hdsp_get_autosync_ref, \
2651 }
2652
2653 static int hdsp_autosync_ref(hdsp_t *hdsp)
2654 {
2655 /* This looks at the autosync selected sync reference */
2656 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2657
2658 switch (status2 & HDSP_SelSyncRefMask) {
2659 case HDSP_SelSyncRef_WORD:
2660 return HDSP_AUTOSYNC_FROM_WORD;
2661 case HDSP_SelSyncRef_ADAT_SYNC:
2662 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2663 case HDSP_SelSyncRef_SPDIF:
2664 return HDSP_AUTOSYNC_FROM_SPDIF;
2665 case HDSP_SelSyncRefMask:
2666 return HDSP_AUTOSYNC_FROM_NONE;
2667 case HDSP_SelSyncRef_ADAT1:
2668 return HDSP_AUTOSYNC_FROM_ADAT1;
2669 case HDSP_SelSyncRef_ADAT2:
2670 return HDSP_AUTOSYNC_FROM_ADAT2;
2671 case HDSP_SelSyncRef_ADAT3:
2672 return HDSP_AUTOSYNC_FROM_ADAT3;
2673 default:
2674 return HDSP_AUTOSYNC_FROM_WORD;
2675 }
2676 return 0;
2677 }
2678
2679 static int snd_hdsp_info_autosync_ref(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2680 {
2681 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2682
2683 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2684 uinfo->count = 1;
2685 uinfo->value.enumerated.items = 7;
2686 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2687 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2688 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2689 return 0;
2690 }
2691
2692 static int snd_hdsp_get_autosync_ref(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2693 {
2694 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2695
2696 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2697 return 0;
2698 }
2699
2700 #define HDSP_LINE_OUT(xname, xindex) \
2701 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2702 .name = xname, \
2703 .index = xindex, \
2704 .info = snd_hdsp_info_line_out, \
2705 .get = snd_hdsp_get_line_out, \
2706 .put = snd_hdsp_put_line_out \
2707 }
2708
2709 static int hdsp_line_out(hdsp_t *hdsp)
2710 {
2711 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2712 }
2713
2714 static int hdsp_set_line_output(hdsp_t *hdsp, int out)
2715 {
2716 if (out) {
2717 hdsp->control_register |= HDSP_LineOut;
2718 } else {
2719 hdsp->control_register &= ~HDSP_LineOut;
2720 }
2721 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2722 return 0;
2723 }
2724
2725 static int snd_hdsp_info_line_out(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2726 {
2727 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2728 uinfo->count = 1;
2729 uinfo->value.integer.min = 0;
2730 uinfo->value.integer.max = 1;
2731 return 0;
2732 }
2733
2734 static int snd_hdsp_get_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2735 {
2736 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2737
2738 spin_lock_irq(&hdsp->lock);
2739 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2740 spin_unlock_irq(&hdsp->lock);
2741 return 0;
2742 }
2743
2744 static int snd_hdsp_put_line_out(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2745 {
2746 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2747 int change;
2748 unsigned int val;
2749
2750 if (!snd_hdsp_use_is_exclusive(hdsp))
2751 return -EBUSY;
2752 val = ucontrol->value.integer.value[0] & 1;
2753 spin_lock_irq(&hdsp->lock);
2754 change = (int)val != hdsp_line_out(hdsp);
2755 hdsp_set_line_output(hdsp, val);
2756 spin_unlock_irq(&hdsp->lock);
2757 return change;
2758 }
2759
2760 #define HDSP_PRECISE_POINTER(xname, xindex) \
2761 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2762 .name = xname, \
2763 .index = xindex, \
2764 .info = snd_hdsp_info_precise_pointer, \
2765 .get = snd_hdsp_get_precise_pointer, \
2766 .put = snd_hdsp_put_precise_pointer \
2767 }
2768
2769 static int hdsp_set_precise_pointer(hdsp_t *hdsp, int precise)
2770 {
2771 if (precise) {
2772 hdsp->precise_ptr = 1;
2773 } else {
2774 hdsp->precise_ptr = 0;
2775 }
2776 return 0;
2777 }
2778
2779 static int snd_hdsp_info_precise_pointer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2780 {
2781 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2782 uinfo->count = 1;
2783 uinfo->value.integer.min = 0;
2784 uinfo->value.integer.max = 1;
2785 return 0;
2786 }
2787
2788 static int snd_hdsp_get_precise_pointer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2789 {
2790 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2791
2792 spin_lock_irq(&hdsp->lock);
2793 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2794 spin_unlock_irq(&hdsp->lock);
2795 return 0;
2796 }
2797
2798 static int snd_hdsp_put_precise_pointer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2799 {
2800 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2801 int change;
2802 unsigned int val;
2803
2804 if (!snd_hdsp_use_is_exclusive(hdsp))
2805 return -EBUSY;
2806 val = ucontrol->value.integer.value[0] & 1;
2807 spin_lock_irq(&hdsp->lock);
2808 change = (int)val != hdsp->precise_ptr;
2809 hdsp_set_precise_pointer(hdsp, val);
2810 spin_unlock_irq(&hdsp->lock);
2811 return change;
2812 }
2813
2814 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2815 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2816 .name = xname, \
2817 .index = xindex, \
2818 .info = snd_hdsp_info_use_midi_tasklet, \
2819 .get = snd_hdsp_get_use_midi_tasklet, \
2820 .put = snd_hdsp_put_use_midi_tasklet \
2821 }
2822
2823 static int hdsp_set_use_midi_tasklet(hdsp_t *hdsp, int use_tasklet)
2824 {
2825 if (use_tasklet) {
2826 hdsp->use_midi_tasklet = 1;
2827 } else {
2828 hdsp->use_midi_tasklet = 0;
2829 }
2830 return 0;
2831 }
2832
2833 static int snd_hdsp_info_use_midi_tasklet(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2834 {
2835 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2836 uinfo->count = 1;
2837 uinfo->value.integer.min = 0;
2838 uinfo->value.integer.max = 1;
2839 return 0;
2840 }
2841
2842 static int snd_hdsp_get_use_midi_tasklet(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2843 {
2844 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2845
2846 spin_lock_irq(&hdsp->lock);
2847 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2848 spin_unlock_irq(&hdsp->lock);
2849 return 0;
2850 }
2851
2852 static int snd_hdsp_put_use_midi_tasklet(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2853 {
2854 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2855 int change;
2856 unsigned int val;
2857
2858 if (!snd_hdsp_use_is_exclusive(hdsp))
2859 return -EBUSY;
2860 val = ucontrol->value.integer.value[0] & 1;
2861 spin_lock_irq(&hdsp->lock);
2862 change = (int)val != hdsp->use_midi_tasklet;
2863 hdsp_set_use_midi_tasklet(hdsp, val);
2864 spin_unlock_irq(&hdsp->lock);
2865 return change;
2866 }
2867
2868 #define HDSP_MIXER(xname, xindex) \
2869 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2870 .name = xname, \
2871 .index = xindex, \
2872 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2873 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2874 .info = snd_hdsp_info_mixer, \
2875 .get = snd_hdsp_get_mixer, \
2876 .put = snd_hdsp_put_mixer \
2877 }
2878
2879 static int snd_hdsp_info_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2880 {
2881 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2882 uinfo->count = 3;
2883 uinfo->value.integer.min = 0;
2884 uinfo->value.integer.max = 65536;
2885 uinfo->value.integer.step = 1;
2886 return 0;
2887 }
2888
2889 static int snd_hdsp_get_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2890 {
2891 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2892 int source;
2893 int destination;
2894 int addr;
2895
2896 source = ucontrol->value.integer.value[0];
2897 destination = ucontrol->value.integer.value[1];
2898
2899 if (source >= hdsp->max_channels) {
2900 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2901 } else {
2902 addr = hdsp_input_to_output_key(hdsp,source, destination);
2903 }
2904
2905 spin_lock_irq(&hdsp->lock);
2906 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2907 spin_unlock_irq(&hdsp->lock);
2908 return 0;
2909 }
2910
2911 static int snd_hdsp_put_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2912 {
2913 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2914 int change;
2915 int source;
2916 int destination;
2917 int gain;
2918 int addr;
2919
2920 if (!snd_hdsp_use_is_exclusive(hdsp))
2921 return -EBUSY;
2922
2923 source = ucontrol->value.integer.value[0];
2924 destination = ucontrol->value.integer.value[1];
2925
2926 if (source >= hdsp->max_channels) {
2927 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2928 } else {
2929 addr = hdsp_input_to_output_key(hdsp,source, destination);
2930 }
2931
2932 gain = ucontrol->value.integer.value[2];
2933
2934 spin_lock_irq(&hdsp->lock);
2935 change = gain != hdsp_read_gain(hdsp, addr);
2936 if (change)
2937 hdsp_write_gain(hdsp, addr, gain);
2938 spin_unlock_irq(&hdsp->lock);
2939 return change;
2940 }
2941
2942 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2943 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2944 .name = xname, \
2945 .index = xindex, \
2946 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2947 .info = snd_hdsp_info_sync_check, \
2948 .get = snd_hdsp_get_wc_sync_check \
2949 }
2950
2951 static int snd_hdsp_info_sync_check(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
2952 {
2953 static char *texts[] = {"No Lock", "Lock", "Sync" };
2954 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2955 uinfo->count = 1;
2956 uinfo->value.enumerated.items = 3;
2957 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2958 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2959 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2960 return 0;
2961 }
2962
2963 static int hdsp_wc_sync_check(hdsp_t *hdsp)
2964 {
2965 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2966 if (status2 & HDSP_wc_lock) {
2967 if (status2 & HDSP_wc_sync) {
2968 return 2;
2969 } else {
2970 return 1;
2971 }
2972 } else {
2973 return 0;
2974 }
2975 return 0;
2976 }
2977
2978 static int snd_hdsp_get_wc_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
2979 {
2980 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
2981
2982 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2983 return 0;
2984 }
2985
2986 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2987 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2988 .name = xname, \
2989 .index = xindex, \
2990 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2991 .info = snd_hdsp_info_sync_check, \
2992 .get = snd_hdsp_get_spdif_sync_check \
2993 }
2994
2995 static int hdsp_spdif_sync_check(hdsp_t *hdsp)
2996 {
2997 int status = hdsp_read(hdsp, HDSP_statusRegister);
2998 if (status & HDSP_SPDIFErrorFlag) {
2999 return 0;
3000 } else {
3001 if (status & HDSP_SPDIFSync) {
3002 return 2;
3003 } else {
3004 return 1;
3005 }
3006 }
3007 return 0;
3008 }
3009
3010 static int snd_hdsp_get_spdif_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3011 {
3012 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3013
3014 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
3015 return 0;
3016 }
3017
3018 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
3019 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3020 .name = xname, \
3021 .index = xindex, \
3022 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3023 .info = snd_hdsp_info_sync_check, \
3024 .get = snd_hdsp_get_adatsync_sync_check \
3025 }
3026
3027 static int hdsp_adatsync_sync_check(hdsp_t *hdsp)
3028 {
3029 int status = hdsp_read(hdsp, HDSP_statusRegister);
3030 if (status & HDSP_TimecodeLock) {
3031 if (status & HDSP_TimecodeSync) {
3032 return 2;
3033 } else {
3034 return 1;
3035 }
3036 } else {
3037 return 0;
3038 }
3039 }
3040
3041 static int snd_hdsp_get_adatsync_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3042 {
3043 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3044
3045 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3046 return 0;
3047 }
3048
3049 #define HDSP_ADAT_SYNC_CHECK \
3050 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3051 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3052 .info = snd_hdsp_info_sync_check, \
3053 .get = snd_hdsp_get_adat_sync_check \
3054 }
3055
3056 static int hdsp_adat_sync_check(hdsp_t *hdsp, int idx)
3057 {
3058 int status = hdsp_read(hdsp, HDSP_statusRegister);
3059
3060 if (status & (HDSP_Lock0>>idx)) {
3061 if (status & (HDSP_Sync0>>idx)) {
3062 return 2;
3063 } else {
3064 return 1;
3065 }
3066 } else {
3067 return 0;
3068 }
3069 }
3070
3071 static int snd_hdsp_get_adat_sync_check(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
3072 {
3073 int offset;
3074 hdsp_t *hdsp = snd_kcontrol_chip(kcontrol);
3075
3076 offset = ucontrol->id.index - 1;
3077 snd_assert(offset >= 0);
3078
3079 switch (hdsp->io_type) {
3080 case Digiface:
3081 case H9652:
3082 if (offset >= 3)
3083 return -EINVAL;
3084 break;
3085 case Multiface:
3086 case H9632:
3087 if (offset >= 1)
3088 return -EINVAL;
3089 break;
3090 default:
3091 return -EIO;
3092 }
3093
3094 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3095 return 0;
3096 }
3097
3098 static snd_kcontrol_new_t snd_hdsp_9632_controls[] = {
3099 HDSP_DA_GAIN("DA Gain", 0),
3100 HDSP_AD_GAIN("AD Gain", 0),
3101 HDSP_PHONE_GAIN("Phones Gain", 0),
3102 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0)
3103 };
3104
3105 static snd_kcontrol_new_t snd_hdsp_controls[] = {
3106 {
3107 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3108 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3109 .info = snd_hdsp_control_spdif_info,
3110 .get = snd_hdsp_control_spdif_get,
3111 .put = snd_hdsp_control_spdif_put,
3112 },
3113 {
3114 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3115 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3116 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3117 .info = snd_hdsp_control_spdif_stream_info,
3118 .get = snd_hdsp_control_spdif_stream_get,
3119 .put = snd_hdsp_control_spdif_stream_put,
3120 },
3121 {
3122 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3123 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3124 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3125 .info = snd_hdsp_control_spdif_mask_info,
3126 .get = snd_hdsp_control_spdif_mask_get,
3127 .private_value = IEC958_AES0_NONAUDIO |
3128 IEC958_AES0_PROFESSIONAL |
3129 IEC958_AES0_CON_EMPHASIS,
3130 },
3131 {
3132 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3133 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3134 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3135 .info = snd_hdsp_control_spdif_mask_info,
3136 .get = snd_hdsp_control_spdif_mask_get,
3137 .private_value = IEC958_AES0_NONAUDIO |
3138 IEC958_AES0_PROFESSIONAL |
3139 IEC958_AES0_PRO_EMPHASIS,
3140 },
3141 HDSP_MIXER("Mixer", 0),
3142 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3143 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3144 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3145 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3146 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3147 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3148 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3149 {
3150 /* FIXME: should be PCM or MIXER? */
3151 /* .iface = SNDRV_CTL_ELEM_IFACE_PCM, */
3152 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3153 .name = "Sample Clock Source Locking",
3154 .info = snd_hdsp_info_clock_source_lock,
3155 .get = snd_hdsp_get_clock_source_lock,
3156 .put = snd_hdsp_put_clock_source_lock,
3157 },
3158 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3159 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3160 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3161 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3162 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3163 /* 'External Rate' complies with the alsa control naming scheme */
3164 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3165 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3166 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3167 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3168 HDSP_LINE_OUT("Line Out", 0),
3169 HDSP_PRECISE_POINTER("Precise Pointer", 0),
3170 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
3171 };
3172
3173 static snd_kcontrol_new_t snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3174 static snd_kcontrol_new_t snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3175
3176 static int snd_hdsp_create_controls(snd_card_t *card, hdsp_t *hdsp)
3177 {
3178 unsigned int idx;
3179 int err;
3180 snd_kcontrol_t *kctl;
3181
3182 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3183 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) {
3184 return err;
3185 }
3186 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3187 hdsp->spdif_ctl = kctl;
3188 }
3189
3190 /* ADAT SyncCheck status */
3191 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3192 snd_hdsp_adat_sync_check.index = 1;
3193 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3194 return err;
3195 }
3196 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3197 for (idx = 1; idx < 3; ++idx) {
3198 snd_hdsp_adat_sync_check.index = idx+1;
3199 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) {
3200 return err;
3201 }
3202 }
3203 }
3204
3205 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3206 if (hdsp->io_type == H9632) {
3207 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3208 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) {
3209 return err;
3210 }
3211 }
3212 }
3213
3214 /* AEB control for H96xx card */
3215 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3216 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) {
3217 return err;
3218 }
3219 }
3220
3221 return 0;
3222 }
3223
3224 /*------------------------------------------------------------
3225 /proc interface
3226 ------------------------------------------------------------*/
3227
3228 static void
3229 snd_hdsp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
3230 {
3231 hdsp_t *hdsp = (hdsp_t *) entry->private_data;
3232 unsigned int status;
3233 unsigned int status2;
3234 char *pref_sync_ref;
3235 char *autosync_ref;
3236 char *system_clock_mode;
3237 char *clock_source;
3238 int x;
3239
3240 if (hdsp_check_for_iobox (hdsp)) {
3241 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3242 return;
3243 }
3244
3245 if (hdsp_check_for_firmware(hdsp)) {
3246 if (hdsp->state & HDSP_FirmwareCached) {
3247 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3248 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3249 return;
3250 }
3251 } else {
3252 snd_iprintf(buffer, "No firmware loaded nor cached, please upload firmware.\n");
3253 return;
3254 }
3255 }
3256
3257 status = hdsp_read(hdsp, HDSP_statusRegister);
3258 status2 = hdsp_read(hdsp, HDSP_status2Register);
3259
3260 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3261 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3262 hdsp->capture_buffer, hdsp->playback_buffer);
3263 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3264 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3265 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3266 snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3267 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3268 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3269 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3270 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3271 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3272 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3273 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3274 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3275
3276 snd_iprintf(buffer, "\n");
3277
3278 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3279
3280 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3281 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3282 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3283 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3284
3285 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3286
3287 snd_iprintf(buffer, "\n");
3288
3289
3290 switch (hdsp_clock_source(hdsp)) {
3291 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3292 clock_source = "AutoSync";
3293 break;
3294 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3295 clock_source = "Internal 32 kHz";
3296 break;
3297 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3298 clock_source = "Internal 44.1 kHz";
3299 break;
3300 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3301 clock_source = "Internal 48 kHz";
3302 break;
3303 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3304 clock_source = "Internal 64 kHz";
3305 break;
3306 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3307 clock_source = "Internal 88.2 kHz";
3308 break;
3309 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3310 clock_source = "Internal 96 kHz";
3311 break;
3312 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3313 clock_source = "Internal 128 kHz";
3314 break;
3315 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3316 clock_source = "Internal 176.4 kHz";
3317 break;
3318 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3319 clock_source = "Internal 192 kHz";
3320 break;
3321 default:
3322 clock_source = "Error";
3323 }
3324 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3325
3326 if (hdsp_system_clock_mode(hdsp)) {
3327 system_clock_mode = "Slave";
3328 } else {
3329 system_clock_mode = "Master";
3330 }
3331
3332 switch (hdsp_pref_sync_ref (hdsp)) {
3333 case HDSP_SYNC_FROM_WORD:
3334 pref_sync_ref = "Word Clock";
3335 break;
3336 case HDSP_SYNC_FROM_ADAT_SYNC:
3337 pref_sync_ref = "ADAT Sync";
3338 break;
3339 case HDSP_SYNC_FROM_SPDIF:
3340 pref_sync_ref = "SPDIF";
3341 break;
3342 case HDSP_SYNC_FROM_ADAT1:
3343 pref_sync_ref = "ADAT1";
3344 break;
3345 case HDSP_SYNC_FROM_ADAT2:
3346 pref_sync_ref = "ADAT2";
3347 break;
3348 case HDSP_SYNC_FROM_ADAT3:
3349 pref_sync_ref = "ADAT3";
3350 break;
3351 default:
3352 pref_sync_ref = "Word Clock";
3353 break;
3354 }
3355 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3356
3357 switch (hdsp_autosync_ref (hdsp)) {
3358 case HDSP_AUTOSYNC_FROM_WORD:
3359 autosync_ref = "Word Clock";
3360 break;
3361 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3362 autosync_ref = "ADAT Sync";
3363 break;
3364 case HDSP_AUTOSYNC_FROM_SPDIF:
3365 autosync_ref = "SPDIF";
3366 break;
3367 case HDSP_AUTOSYNC_FROM_NONE:
3368 autosync_ref = "None";
3369 break;
3370 case HDSP_AUTOSYNC_FROM_ADAT1:
3371 autosync_ref = "ADAT1";
3372 break;
3373 case HDSP_AUTOSYNC_FROM_ADAT2:
3374 autosync_ref = "ADAT2";
3375 break;
3376 case HDSP_AUTOSYNC_FROM_ADAT3:
3377 autosync_ref = "ADAT3";
3378 break;
3379 default:
3380 autosync_ref = "---";
3381 break;
3382 }
3383 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3384
3385 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3386
3387 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3388
3389 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3390 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3391
3392 snd_iprintf(buffer, "\n");
3393
3394 switch (hdsp_spdif_in(hdsp)) {
3395 case HDSP_SPDIFIN_OPTICAL:
3396 snd_iprintf(buffer, "IEC958 input: Optical\n");
3397 break;
3398 case HDSP_SPDIFIN_COAXIAL:
3399 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3400 break;
3401 case HDSP_SPDIFIN_INTERNAL:
3402 snd_iprintf(buffer, "IEC958 input: Internal\n");
3403 break;
3404 case HDSP_SPDIFIN_AES:
3405 snd_iprintf(buffer, "IEC958 input: AES\n");
3406 break;
3407 default:
3408 snd_iprintf(buffer, "IEC958 input: ???\n");
3409 break;
3410 }
3411
3412 if (hdsp->control_register & HDSP_SPDIFOpticalOut) {
3413 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3414 } else {
3415 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3416 }
3417
3418 if (hdsp->control_register & HDSP_SPDIFProfessional) {
3419 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3420 } else {
3421 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3422 }
3423
3424 if (hdsp->control_register & HDSP_SPDIFEmphasis) {
3425 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3426 } else {
3427 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3428 }
3429
3430 if (hdsp->control_register & HDSP_SPDIFNonAudio) {
3431 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3432 } else {
3433 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3434 }
3435 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) {
3436 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3437 } else {
3438 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3439 }
3440
3441 snd_iprintf(buffer, "\n");
3442
3443 /* Sync Check */
3444 x = status & HDSP_Sync0;
3445 if (status & HDSP_Lock0) {
3446 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3447 } else {
3448 snd_iprintf(buffer, "ADAT1: No Lock\n");
3449 }
3450
3451 switch (hdsp->io_type) {
3452 case Digiface:
3453 case H9652:
3454 x = status & HDSP_Sync1;
3455 if (status & HDSP_Lock1) {
3456 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3457 } else {
3458 snd_iprintf(buffer, "ADAT2: No Lock\n");
3459 }
3460 x = status & HDSP_Sync2;
3461 if (status & HDSP_Lock2) {
3462 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3463 } else {
3464 snd_iprintf(buffer, "ADAT3: No Lock\n");
3465 }
3466 default:
3467 /* relax */
3468 break;
3469 }
3470
3471 x = status & HDSP_SPDIFSync;
3472 if (status & HDSP_SPDIFErrorFlag) {
3473 snd_iprintf (buffer, "SPDIF: No Lock\n");
3474 } else {
3475 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3476 }
3477
3478 x = status2 & HDSP_wc_sync;
3479 if (status2 & HDSP_wc_lock) {
3480 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3481 } else {
3482 snd_iprintf (buffer, "Word Clock: No Lock\n");
3483 }
3484
3485 x = status & HDSP_TimecodeSync;
3486 if (status & HDSP_TimecodeLock) {
3487 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3488 } else {
3489 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3490 }
3491
3492 snd_iprintf(buffer, "\n");
3493
3494 /* Informations about H9632 specific controls */
3495 if (hdsp->io_type == H9632) {
3496 char *tmp;
3497
3498 switch (hdsp_ad_gain(hdsp)) {
3499 case 0:
3500 tmp = "-10 dBV";
3501 break;
3502 case 1:
3503 tmp = "+4 dBu";
3504 break;
3505 default:
3506 tmp = "Lo Gain";
3507 break;
3508 }
3509 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3510
3511 switch (hdsp_da_gain(hdsp)) {
3512 case 0:
3513 tmp = "Hi Gain";
3514 break;
3515 case 1:
3516 tmp = "+4 dBu";
3517 break;
3518 default:
3519 tmp = "-10 dBV";
3520 break;
3521 }
3522 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3523
3524 switch (hdsp_phone_gain(hdsp)) {
3525 case 0:
3526 tmp = "0 dB";
3527 break;
3528 case 1:
3529 tmp = "-6 dB";
3530 break;
3531 default:
3532 tmp = "-12 dB";
3533 break;
3534 }
3535 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3536
3537 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3538
3539 if (hdsp->control_register & HDSP_AnalogExtensionBoard) {
3540 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3541 } else {
3542 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3543 }
3544 snd_iprintf(buffer, "\n");
3545 }
3546
3547 }
3548
3549 static void __devinit snd_hdsp_proc_init(hdsp_t *hdsp)
3550 {
3551 snd_info_entry_t *entry;
3552
3553 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3554 snd_info_set_text_ops(entry, hdsp, 1024, snd_hdsp_proc_read);
3555 }
3556
3557 static void snd_hdsp_free_buffers(hdsp_t *hdsp)
3558 {
3559 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3560 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3561 }
3562
3563 static int __devinit snd_hdsp_initialize_memory(hdsp_t *hdsp)
3564 {
3565 unsigned long pb_bus, cb_bus;
3566
3567 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3568 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3569 if (hdsp->capture_dma_buf.area)
3570 snd_dma_free_pages(&hdsp->capture_dma_buf);
3571 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3572 return -ENOMEM;
3573 }
3574
3575 /* Align to bus-space 64K boundary */
3576
3577 cb_bus = (hdsp->capture_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3578 pb_bus = (hdsp->playback_dma_buf.addr + 0xFFFF) & ~0xFFFFl;
3579
3580 /* Tell the card where it is */
3581
3582 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3583 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3584
3585 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3586 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3587
3588 return 0;
3589 }
3590
3591 static int snd_hdsp_set_defaults(hdsp_t *hdsp)
3592 {
3593 unsigned int i;
3594
3595 /* ASSUMPTION: hdsp->lock is either held, or
3596 there is no need to hold it (e.g. during module
3597 initalization).
3598 */
3599
3600 /* set defaults:
3601
3602 SPDIF Input via Coax
3603 Master clock mode
3604 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3605 which implies 2 4096 sample, 32Kbyte periods).
3606 Enable line out.
3607 */
3608
3609 hdsp->control_register = HDSP_ClockModeMaster |
3610 HDSP_SPDIFInputCoaxial |
3611 hdsp_encode_latency(7) |
3612 HDSP_LineOut;
3613
3614
3615 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3616
3617 #ifdef SNDRV_BIG_ENDIAN
3618 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3619 #else
3620 hdsp->control2_register = 0;
3621 #endif
3622 if (hdsp->io_type == H9652) {
3623 snd_hdsp_9652_enable_mixer (hdsp);
3624 } else {
3625 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3626 }
3627
3628 hdsp_reset_hw_pointer(hdsp);
3629 hdsp_compute_period_size(hdsp);
3630
3631 /* silence everything */
3632
3633 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) {
3634 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3635 }
3636
3637 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3638 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) {
3639 return -EIO;
3640 }
3641 }
3642
3643 /* H9632 specific defaults */
3644 if (hdsp->io_type == H9632) {
3645 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3646 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3647 }
3648
3649 /* set a default rate so that the channel map is set up.
3650 */
3651
3652 hdsp_set_rate(hdsp, 48000, 1);
3653
3654 return 0;
3655 }
3656
3657 static void hdsp_midi_tasklet(unsigned long arg)
3658 {
3659 hdsp_t *hdsp = (hdsp_t *)arg;
3660
3661 if (hdsp->midi[0].pending) {
3662 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3663 }
3664 if (hdsp->midi[1].pending) {
3665 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3666 }
3667 }
3668
3669 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3670 {
3671 hdsp_t *hdsp = (hdsp_t *) dev_id;
3672 unsigned int status;
3673 int audio;
3674 int midi0;
3675 int midi1;
3676 unsigned int midi0status;
3677 unsigned int midi1status;
3678 int schedule = 0;
3679
3680 status = hdsp_read(hdsp, HDSP_statusRegister);
3681
3682 audio = status & HDSP_audioIRQPending;
3683 midi0 = status & HDSP_midi0IRQPending;
3684 midi1 = status & HDSP_midi1IRQPending;
3685
3686 if (!audio && !midi0 && !midi1) {
3687 return IRQ_NONE;
3688 }
3689
3690 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3691
3692 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3693 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3694
3695 if (audio) {
3696 if (hdsp->capture_substream) {
3697 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3698 }
3699
3700 if (hdsp->playback_substream) {
3701 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3702 }
3703 }
3704
3705 if (midi0 && midi0status) {
3706 if (hdsp->use_midi_tasklet) {
3707 /* we disable interrupts for this input until processing is done */
3708 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3709 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3710 hdsp->midi[0].pending = 1;
3711 schedule = 1;
3712 } else {
3713 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3714 }
3715 }
3716 if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) {
3717 if (hdsp->use_midi_tasklet) {
3718 /* we disable interrupts for this input until processing is done */
3719 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3720 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3721 hdsp->midi[1].pending = 1;
3722 schedule = 1;
3723 } else {
3724 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3725 }
3726 }
3727 if (hdsp->use_midi_tasklet && schedule)
3728 tasklet_hi_schedule(&hdsp->midi_tasklet);
3729 return IRQ_HANDLED;
3730 }
3731
3732 static snd_pcm_uframes_t snd_hdsp_hw_pointer(snd_pcm_substream_t *substream)
3733 {
3734 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3735 return hdsp_hw_pointer(hdsp);
3736 }
3737
3738 static char *hdsp_channel_buffer_location(hdsp_t *hdsp,
3739 int stream,
3740 int channel)
3741
3742 {
3743 int mapped_channel;
3744
3745 snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3746
3747 if ((mapped_channel = hdsp->channel_map[channel]) < 0) {
3748 return NULL;
3749 }
3750
3751 if (stream == SNDRV_PCM_STREAM_CAPTURE) {
3752 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3753 } else {
3754 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3755 }
3756 }
3757
3758 static int snd_hdsp_playback_copy(snd_pcm_substream_t *substream, int channel,
3759 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3760 {
3761 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3762 char *channel_buf;
3763
3764 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3765
3766 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3767 snd_assert(channel_buf != NULL, return -EIO);
3768 if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3769 return -EFAULT;
3770 return count;
3771 }
3772
3773 static int snd_hdsp_capture_copy(snd_pcm_substream_t *substream, int channel,
3774 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3775 {
3776 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3777 char *channel_buf;
3778
3779 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3780
3781 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3782 snd_assert(channel_buf != NULL, return -EIO);
3783 if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3784 return -EFAULT;
3785 return count;
3786 }
3787
3788 static int snd_hdsp_hw_silence(snd_pcm_substream_t *substream, int channel,
3789 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3790 {
3791 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3792 char *channel_buf;
3793
3794 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3795 snd_assert(channel_buf != NULL, return -EIO);
3796 memset(channel_buf + pos * 4, 0, count * 4);
3797 return count;
3798 }
3799
3800 static int snd_hdsp_reset(snd_pcm_substream_t *substream)
3801 {
3802 snd_pcm_runtime_t *runtime = substream->runtime;
3803 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3804 snd_pcm_substream_t *other;
3805 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3806 other = hdsp->capture_substream;
3807 else
3808 other = hdsp->playback_substream;
3809 if (hdsp->running)
3810 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3811 else
3812 runtime->status->hw_ptr = 0;
3813 if (other) {
3814 struct list_head *pos;
3815 snd_pcm_substream_t *s;
3816 snd_pcm_runtime_t *oruntime = other->runtime;
3817 snd_pcm_group_for_each(pos, substream) {
3818 s = snd_pcm_group_substream_entry(pos);
3819 if (s == other) {
3820 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3821 break;
3822 }
3823 }
3824 }
3825 return 0;
3826 }
3827
3828 static int snd_hdsp_hw_params(snd_pcm_substream_t *substream,
3829 snd_pcm_hw_params_t *params)
3830 {
3831 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3832 int err;
3833 pid_t this_pid;
3834 pid_t other_pid;
3835
3836 if (hdsp_check_for_iobox (hdsp)) {
3837 return -EIO;
3838 }
3839
3840 if (hdsp_check_for_firmware(hdsp)) {
3841 if (hdsp->state & HDSP_FirmwareCached) {
3842 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3843 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
3844 }
3845 } else {
3846 snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
3847 }
3848 return -EIO;
3849 }
3850
3851 spin_lock_irq(&hdsp->lock);
3852
3853 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3854 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3855 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3856 this_pid = hdsp->playback_pid;
3857 other_pid = hdsp->capture_pid;
3858 } else {
3859 this_pid = hdsp->capture_pid;
3860 other_pid = hdsp->playback_pid;
3861 }
3862
3863 if ((other_pid > 0) && (this_pid != other_pid)) {
3864
3865 /* The other stream is open, and not by the same
3866 task as this one. Make sure that the parameters
3867 that matter are the same.
3868 */
3869
3870 if (params_rate(params) != hdsp->system_sample_rate) {
3871 spin_unlock_irq(&hdsp->lock);
3872 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3873 return -EBUSY;
3874 }
3875
3876 if (params_period_size(params) != hdsp->period_bytes / 4) {
3877 spin_unlock_irq(&hdsp->lock);
3878 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3879 return -EBUSY;
3880 }
3881
3882 /* We're fine. */
3883
3884 spin_unlock_irq(&hdsp->lock);
3885 return 0;
3886
3887 } else {
3888 spin_unlock_irq(&hdsp->lock);
3889 }
3890
3891 /* how to make sure that the rate matches an externally-set one ?
3892 */
3893
3894 spin_lock_irq(&hdsp->lock);
3895 if (! hdsp->clock_source_locked) {
3896 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3897 spin_unlock_irq(&hdsp->lock);
3898 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3899 return err;
3900 }
3901 }
3902 spin_unlock_irq(&hdsp->lock);
3903
3904 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3905 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3906 return err;
3907 }
3908
3909 return 0;
3910 }
3911
3912 static int snd_hdsp_channel_info(snd_pcm_substream_t *substream,
3913 snd_pcm_channel_info_t *info)
3914 {
3915 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3916 int mapped_channel;
3917
3918 snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3919
3920 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) {
3921 return -EINVAL;
3922 }
3923
3924 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
3925 info->first = 0;
3926 info->step = 32;
3927 return 0;
3928 }
3929
3930 static int snd_hdsp_ioctl(snd_pcm_substream_t *substream,
3931 unsigned int cmd, void *arg)
3932 {
3933 switch (cmd) {
3934 case SNDRV_PCM_IOCTL1_RESET:
3935 {
3936 return snd_hdsp_reset(substream);
3937 }
3938 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3939 {
3940 snd_pcm_channel_info_t *info = arg;
3941 return snd_hdsp_channel_info(substream, info);
3942 }
3943 default:
3944 break;
3945 }
3946
3947 return snd_pcm_lib_ioctl(substream, cmd, arg);
3948 }
3949
3950 static int snd_hdsp_trigger(snd_pcm_substream_t *substream, int cmd)
3951 {
3952 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
3953 snd_pcm_substream_t *other;
3954 int running;
3955
3956 if (hdsp_check_for_iobox (hdsp)) {
3957 return -EIO;
3958 }
3959
3960 if (hdsp_check_for_firmware(hdsp)) {
3961 if (hdsp->state & HDSP_FirmwareCached) {
3962 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3963 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
3964 }
3965 } else {
3966 snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
3967 }
3968 return -EIO;
3969 }
3970
3971 spin_lock(&hdsp->lock);
3972 running = hdsp->running;
3973 switch (cmd) {
3974 case SNDRV_PCM_TRIGGER_START:
3975 running |= 1 << substream->stream;
3976 break;
3977 case SNDRV_PCM_TRIGGER_STOP:
3978 running &= ~(1 << substream->stream);
3979 break;
3980 default:
3981 snd_BUG();
3982 spin_unlock(&hdsp->lock);
3983 return -EINVAL;
3984 }
3985 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3986 other = hdsp->capture_substream;
3987 else
3988 other = hdsp->playback_substream;
3989
3990 if (other) {
3991 struct list_head *pos;
3992 snd_pcm_substream_t *s;
3993 snd_pcm_group_for_each(pos, substream) {
3994 s = snd_pcm_group_substream_entry(pos);
3995 if (s == other) {
3996 snd_pcm_trigger_done(s, substream);
3997 if (cmd == SNDRV_PCM_TRIGGER_START)
3998 running |= 1 << s->stream;
3999 else
4000 running &= ~(1 << s->stream);
4001 goto _ok;
4002 }
4003 }
4004 if (cmd == SNDRV_PCM_TRIGGER_START) {
4005 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4006 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4007 hdsp_silence_playback(hdsp);
4008 } else {
4009 if (running &&
4010 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4011 hdsp_silence_playback(hdsp);
4012 }
4013 } else {
4014 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4015 hdsp_silence_playback(hdsp);
4016 }
4017 _ok:
4018 snd_pcm_trigger_done(substream, substream);
4019 if (!hdsp->running && running)
4020 hdsp_start_audio(hdsp);
4021 else if (hdsp->running && !running)
4022 hdsp_stop_audio(hdsp);
4023 hdsp->running = running;
4024 spin_unlock(&hdsp->lock);
4025
4026 return 0;
4027 }
4028
4029 static int snd_hdsp_prepare(snd_pcm_substream_t *substream)
4030 {
4031 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4032 int result = 0;
4033
4034 if (hdsp_check_for_iobox (hdsp)) {
4035 return -EIO;
4036 }
4037
4038 if (hdsp_check_for_firmware(hdsp)) {
4039 if (hdsp->state & HDSP_FirmwareCached) {
4040 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4041 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
4042 }
4043 } else {
4044 snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
4045 }
4046 return -EIO;
4047 }
4048
4049 spin_lock_irq(&hdsp->lock);
4050 if (!hdsp->running)
4051 hdsp_reset_hw_pointer(hdsp);
4052 spin_unlock_irq(&hdsp->lock);
4053 return result;
4054 }
4055
4056 static snd_pcm_hardware_t snd_hdsp_playback_subinfo =
4057 {
4058 .info = (SNDRV_PCM_INFO_MMAP |
4059 SNDRV_PCM_INFO_MMAP_VALID |
4060 SNDRV_PCM_INFO_NONINTERLEAVED |
4061 SNDRV_PCM_INFO_SYNC_START |
4062 SNDRV_PCM_INFO_DOUBLE),
4063 #ifdef SNDRV_BIG_ENDIAN
4064 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4065 #else
4066 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4067 #endif
4068 .rates = (SNDRV_PCM_RATE_32000 |
4069 SNDRV_PCM_RATE_44100 |
4070 SNDRV_PCM_RATE_48000 |
4071 SNDRV_PCM_RATE_64000 |
4072 SNDRV_PCM_RATE_88200 |
4073 SNDRV_PCM_RATE_96000),
4074 .rate_min = 32000,
4075 .rate_max = 96000,
4076 .channels_min = 14,
4077 .channels_max = HDSP_MAX_CHANNELS,
4078 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4079 .period_bytes_min = (64 * 4) * 10,
4080 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4081 .periods_min = 2,
4082 .periods_max = 2,
4083 .fifo_size = 0
4084 };
4085
4086 static snd_pcm_hardware_t snd_hdsp_capture_subinfo =
4087 {
4088 .info = (SNDRV_PCM_INFO_MMAP |
4089 SNDRV_PCM_INFO_MMAP_VALID |
4090 SNDRV_PCM_INFO_NONINTERLEAVED |
4091 SNDRV_PCM_INFO_SYNC_START),
4092 #ifdef SNDRV_BIG_ENDIAN
4093 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4094 #else
4095 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4096 #endif
4097 .rates = (SNDRV_PCM_RATE_32000 |
4098 SNDRV_PCM_RATE_44100 |
4099 SNDRV_PCM_RATE_48000 |
4100 SNDRV_PCM_RATE_64000 |
4101 SNDRV_PCM_RATE_88200 |
4102 SNDRV_PCM_RATE_96000),
4103 .rate_min = 32000,
4104 .rate_max = 96000,
4105 .channels_min = 14,
4106 .channels_max = HDSP_MAX_CHANNELS,
4107 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4108 .period_bytes_min = (64 * 4) * 10,
4109 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4110 .periods_min = 2,
4111 .periods_max = 2,
4112 .fifo_size = 0
4113 };
4114
4115 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4116
4117 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_period_sizes = {
4118 .count = ARRAY_SIZE(hdsp_period_sizes),
4119 .list = hdsp_period_sizes,
4120 .mask = 0
4121 };
4122
4123 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4124
4125 static snd_pcm_hw_constraint_list_t hdsp_hw_constraints_9632_sample_rates = {
4126 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4127 .list = hdsp_9632_sample_rates,
4128 .mask = 0
4129 };
4130
4131 static int snd_hdsp_hw_rule_in_channels(snd_pcm_hw_params_t *params,
4132 snd_pcm_hw_rule_t *rule)
4133 {
4134 hdsp_t *hdsp = rule->private;
4135 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4136 if (hdsp->io_type == H9632) {
4137 unsigned int list[3];
4138 list[0] = hdsp->qs_in_channels;
4139 list[1] = hdsp->ds_in_channels;
4140 list[2] = hdsp->ss_in_channels;
4141 return snd_interval_list(c, 3, list, 0);
4142 } else {
4143 unsigned int list[2];
4144 list[0] = hdsp->ds_in_channels;
4145 list[1] = hdsp->ss_in_channels;
4146 return snd_interval_list(c, 2, list, 0);
4147 }
4148 }
4149
4150 static int snd_hdsp_hw_rule_out_channels(snd_pcm_hw_params_t *params,
4151 snd_pcm_hw_rule_t *rule)
4152 {
4153 unsigned int list[3];
4154 hdsp_t *hdsp = rule->private;
4155 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4156 if (hdsp->io_type == H9632) {
4157 list[0] = hdsp->qs_out_channels;
4158 list[1] = hdsp->ds_out_channels;
4159 list[2] = hdsp->ss_out_channels;
4160 return snd_interval_list(c, 3, list, 0);
4161 } else {
4162 list[0] = hdsp->ds_out_channels;
4163 list[1] = hdsp->ss_out_channels;
4164 }
4165 return snd_interval_list(c, 2, list, 0);
4166 }
4167
4168 static int snd_hdsp_hw_rule_in_channels_rate(snd_pcm_hw_params_t *params,
4169 snd_pcm_hw_rule_t *rule)
4170 {
4171 hdsp_t *hdsp = rule->private;
4172 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4173 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4174 if (r->min > 96000 && hdsp->io_type == H9632) {
4175 snd_interval_t t = {
4176 .min = hdsp->qs_in_channels,
4177 .max = hdsp->qs_in_channels,
4178 .integer = 1,
4179 };
4180 return snd_interval_refine(c, &t);
4181 } else if (r->min > 48000 && r->max <= 96000) {
4182 snd_interval_t t = {
4183 .min = hdsp->ds_in_channels,
4184 .max = hdsp->ds_in_channels,
4185 .integer = 1,
4186 };
4187 return snd_interval_refine(c, &t);
4188 } else if (r->max < 64000) {
4189 snd_interval_t t = {
4190 .min = hdsp->ss_in_channels,
4191 .max = hdsp->ss_in_channels,
4192 .integer = 1,
4193 };
4194 return snd_interval_refine(c, &t);
4195 }
4196 return 0;
4197 }
4198
4199 static int snd_hdsp_hw_rule_out_channels_rate(snd_pcm_hw_params_t *params,
4200 snd_pcm_hw_rule_t *rule)
4201 {
4202 hdsp_t *hdsp = rule->private;
4203 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4204 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4205 if (r->min > 96000 && hdsp->io_type == H9632) {
4206 snd_interval_t t = {
4207 .min = hdsp->qs_out_channels,
4208 .max = hdsp->qs_out_channels,
4209 .integer = 1,
4210 };
4211 return snd_interval_refine(c, &t);
4212 } else if (r->min > 48000 && r->max <= 96000) {
4213 snd_interval_t t = {
4214 .min = hdsp->ds_out_channels,
4215 .max = hdsp->ds_out_channels,
4216 .integer = 1,
4217 };
4218 return snd_interval_refine(c, &t);
4219 } else if (r->max < 64000) {
4220 snd_interval_t t = {
4221 .min = hdsp->ss_out_channels,
4222 .max = hdsp->ss_out_channels,
4223 .integer = 1,
4224 };
4225 return snd_interval_refine(c, &t);
4226 }
4227 return 0;
4228 }
4229
4230 static int snd_hdsp_hw_rule_rate_out_channels(snd_pcm_hw_params_t *params,
4231 snd_pcm_hw_rule_t *rule)
4232 {
4233 hdsp_t *hdsp = rule->private;
4234 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4235 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4236 if (c->min >= hdsp->ss_out_channels) {
4237 snd_interval_t t = {
4238 .min = 32000,
4239 .max = 48000,
4240 .integer = 1,
4241 };
4242 return snd_interval_refine(r, &t);
4243 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4244 snd_interval_t t = {
4245 .min = 128000,
4246 .max = 192000,
4247 .integer = 1,
4248 };
4249 return snd_interval_refine(r, &t);
4250 } else if (c->max <= hdsp->ds_out_channels) {
4251 snd_interval_t t = {
4252 .min = 64000,
4253 .max = 96000,
4254 .integer = 1,
4255 };
4256 return snd_interval_refine(r, &t);
4257 }
4258 return 0;
4259 }
4260
4261 static int snd_hdsp_hw_rule_rate_in_channels(snd_pcm_hw_params_t *params,
4262 snd_pcm_hw_rule_t *rule)
4263 {
4264 hdsp_t *hdsp = rule->private;
4265 snd_interval_t *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4266 snd_interval_t *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4267 if (c->min >= hdsp->ss_in_channels) {
4268 snd_interval_t t = {
4269 .min = 32000,
4270 .max = 48000,
4271 .integer = 1,
4272 };
4273 return snd_interval_refine(r, &t);
4274 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4275 snd_interval_t t = {
4276 .min = 128000,
4277 .max = 192000,
4278 .integer = 1,
4279 };
4280 return snd_interval_refine(r, &t);
4281 } else if (c->max <= hdsp->ds_in_channels) {
4282 snd_interval_t t = {
4283 .min = 64000,
4284 .max = 96000,
4285 .integer = 1,
4286 };
4287 return snd_interval_refine(r, &t);
4288 }
4289 return 0;
4290 }
4291
4292 static int snd_hdsp_playback_open(snd_pcm_substream_t *substream)
4293 {
4294 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4295 snd_pcm_runtime_t *runtime = substream->runtime;
4296
4297 if (hdsp_check_for_iobox (hdsp)) {
4298 return -EIO;
4299 }
4300
4301 if (hdsp_check_for_firmware(hdsp)) {
4302 if (hdsp->state & HDSP_FirmwareCached) {
4303 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4304 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
4305 }
4306 } else {
4307 snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
4308 }
4309 return -EIO;
4310 }
4311
4312 spin_lock_irq(&hdsp->lock);
4313
4314 snd_pcm_set_sync(substream);
4315
4316 runtime->hw = snd_hdsp_playback_subinfo;
4317 runtime->dma_area = hdsp->playback_buffer;
4318 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4319
4320 hdsp->playback_pid = current->pid;
4321 hdsp->playback_substream = substream;
4322
4323 spin_unlock_irq(&hdsp->lock);
4324
4325 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4326 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4327 if (hdsp->clock_source_locked) {
4328 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4329 } else if (hdsp->io_type == H9632) {
4330 runtime->hw.rate_max = 192000;
4331 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4332 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4333 }
4334 if (hdsp->io_type == H9632) {
4335 runtime->hw.channels_min = hdsp->qs_out_channels;
4336 runtime->hw.channels_max = hdsp->ss_out_channels;
4337 }
4338
4339 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4340 snd_hdsp_hw_rule_out_channels, hdsp,
4341 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4342 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4343 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4344 SNDRV_PCM_HW_PARAM_RATE, -1);
4345 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4346 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4347 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4348
4349 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4350 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4351 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4352 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4353 return 0;
4354 }
4355
4356 static int snd_hdsp_playback_release(snd_pcm_substream_t *substream)
4357 {
4358 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4359
4360 spin_lock_irq(&hdsp->lock);
4361
4362 hdsp->playback_pid = -1;
4363 hdsp->playback_substream = NULL;
4364
4365 spin_unlock_irq(&hdsp->lock);
4366
4367 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4368 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4369 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4370 return 0;
4371 }
4372
4373
4374 static int snd_hdsp_capture_open(snd_pcm_substream_t *substream)
4375 {
4376 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4377 snd_pcm_runtime_t *runtime = substream->runtime;
4378
4379 if (hdsp_check_for_iobox (hdsp)) {
4380 return -EIO;
4381 }
4382
4383 if (hdsp_check_for_firmware(hdsp)) {
4384 if (hdsp->state & HDSP_FirmwareCached) {
4385 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
4386 snd_printk("Hammerfall-DSP: Firmware loading from cache failed, please upload manually.\n");
4387 }
4388 } else {
4389 snd_printk("Hammerfall-DSP: No firmware loaded nor cached, please upload firmware.\n");
4390 }
4391 return -EIO;
4392 }
4393
4394 spin_lock_irq(&hdsp->lock);
4395
4396 snd_pcm_set_sync(substream);
4397
4398 runtime->hw = snd_hdsp_capture_subinfo;
4399 runtime->dma_area = hdsp->capture_buffer;
4400 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4401
4402 hdsp->capture_pid = current->pid;
4403 hdsp->capture_substream = substream;
4404
4405 spin_unlock_irq(&hdsp->lock);
4406
4407 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4408 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4409 if (hdsp->io_type == H9632) {
4410 runtime->hw.channels_min = hdsp->qs_in_channels;
4411 runtime->hw.channels_max = hdsp->ss_in_channels;
4412 runtime->hw.rate_max = 192000;
4413 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4414 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4415 }
4416 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4417 snd_hdsp_hw_rule_in_channels, hdsp,
4418 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4419 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4420 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4421 SNDRV_PCM_HW_PARAM_RATE, -1);
4422 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4423 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4424 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4425 return 0;
4426 }
4427
4428 static int snd_hdsp_capture_release(snd_pcm_substream_t *substream)
4429 {
4430 hdsp_t *hdsp = snd_pcm_substream_chip(substream);
4431
4432 spin_lock_irq(&hdsp->lock);
4433
4434 hdsp->capture_pid = -1;
4435 hdsp->capture_substream = NULL;
4436
4437 spin_unlock_irq(&hdsp->lock);
4438 return 0;
4439 }
4440
4441 static int snd_hdsp_hwdep_dummy_op(snd_hwdep_t *hw, struct file *file)
4442 {
4443 /* we have nothing to initialize but the call is required */
4444 return 0;
4445 }
4446
4447
4448 /* helper functions for copying meter values */
4449 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4450 {
4451 u32 val = readl(src);
4452 return copy_to_user(dest, &val, 4);
4453 }
4454
4455 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4456 {
4457 u32 rms_low, rms_high;
4458 u64 rms;
4459 rms_low = readl(src_low);
4460 rms_high = readl(src_high);
4461 rms = ((u64)rms_high << 32) | rms_low;
4462 return copy_to_user(dest, &rms, 8);
4463 }
4464
4465 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4466 {
4467 u32 rms_low, rms_high;
4468 u64 rms;
4469 rms_low = readl(src_low) & 0xffffff00;
4470 rms_high = readl(src_high) & 0xffffff00;
4471 rms = ((u64)rms_high << 32) | rms_low;
4472 return copy_to_user(dest, &rms, 8);
4473 }
4474
4475 static int hdsp_9652_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4476 {
4477 int doublespeed = 0;
4478 int i, j, channels, ofs;
4479
4480 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4481 doublespeed = 1;
4482 channels = doublespeed ? 14 : 26;
4483 for (i = 0, j = 0; i < 26; ++i) {
4484 if (doublespeed && (i & 4))
4485 continue;
4486 ofs = HDSP_9652_peakBase - j * 4;
4487 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4488 return -EFAULT;
4489 ofs -= channels * 4;
4490 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4491 return -EFAULT;
4492 ofs -= channels * 4;
4493 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4494 return -EFAULT;
4495 ofs = HDSP_9652_rmsBase + j * 8;
4496 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4497 hdsp->iobase + ofs + 4))
4498 return -EFAULT;
4499 ofs += channels * 8;
4500 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4501 hdsp->iobase + ofs + 4))
4502 return -EFAULT;
4503 ofs += channels * 8;
4504 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4505 hdsp->iobase + ofs + 4))
4506 return -EFAULT;
4507 j++;
4508 }
4509 return 0;
4510 }
4511
4512 static int hdsp_9632_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4513 {
4514 int i, j;
4515 hdsp_9632_meters_t __iomem *m;
4516 int doublespeed = 0;
4517
4518 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4519 doublespeed = 1;
4520 m = (hdsp_9632_meters_t __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4521 for (i = 0, j = 0; i < 16; ++i, ++j) {
4522 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4523 return -EFAULT;
4524 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4525 return -EFAULT;
4526 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4527 return -EFAULT;
4528 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4529 &m->input_rms_high[j]))
4530 return -EFAULT;
4531 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4532 &m->playback_rms_high[j]))
4533 return -EFAULT;
4534 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4535 &m->output_rms_high[j]))
4536 return -EFAULT;
4537 if (doublespeed && i == 3) i += 4;
4538 }
4539 return 0;
4540 }
4541
4542 static int hdsp_get_peak(hdsp_t *hdsp, hdsp_peak_rms_t __user *peak_rms)
4543 {
4544 int i;
4545
4546 for (i = 0; i < 26; i++) {
4547 if (copy_u32_le(&peak_rms->playback_peaks[i],
4548 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4549 return -EFAULT;
4550 if (copy_u32_le(&peak_rms->input_peaks[i],
4551 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4552 return -EFAULT;
4553 }
4554 for (i = 0; i < 28; i++) {
4555 if (copy_u32_le(&peak_rms->output_peaks[i],
4556 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4557 return -EFAULT;
4558 }
4559 for (i = 0; i < 26; ++i) {
4560 if (copy_u64_le(&peak_rms->playback_rms[i],
4561 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4562 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4563 return -EFAULT;
4564 if (copy_u64_le(&peak_rms->input_rms[i],
4565 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4566 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4567 return -EFAULT;
4568 }
4569 return 0;
4570 }
4571
4572 static int snd_hdsp_hwdep_ioctl(snd_hwdep_t *hw, struct file *file, unsigned int cmd, unsigned long arg)
4573 {
4574 hdsp_t *hdsp = (hdsp_t *)hw->private_data;
4575 void __user *argp = (void __user *)arg;
4576
4577 switch (cmd) {
4578 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4579 hdsp_peak_rms_t __user *peak_rms = (hdsp_peak_rms_t __user *)arg;
4580
4581 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4582 snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n");
4583 return -EINVAL;
4584 }
4585
4586 switch (hdsp->io_type) {
4587 case H9652:
4588 return hdsp_9652_get_peak(hdsp, peak_rms);
4589 case H9632:
4590 return hdsp_9632_get_peak(hdsp, peak_rms);
4591 default:
4592 return hdsp_get_peak(hdsp, peak_rms);
4593 }
4594 }
4595 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4596 hdsp_config_info_t info;
4597 unsigned long flags;
4598 int i;
4599
4600 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4601 snd_printk("Hammerfall-DSP: Firmware needs to be uploaded to the card.\n");
4602 return -EINVAL;
4603 }
4604 spin_lock_irqsave(&hdsp->lock, flags);
4605 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4606 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4607 if (hdsp->io_type != H9632) {
4608 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4609 }
4610 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4611 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) {
4612 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4613 }
4614 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4615 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4616 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4617 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4618 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4619 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4620 info.system_sample_rate = hdsp->system_sample_rate;
4621 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4622 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4623 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4624 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4625 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4626 if (hdsp->io_type == H9632) {
4627 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4628 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4629 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4630 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4631
4632 }
4633 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
4634 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4635 }
4636 spin_unlock_irqrestore(&hdsp->lock, flags);
4637 if (copy_to_user(argp, &info, sizeof(info)))
4638 return -EFAULT;
4639 break;
4640 }
4641 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4642 hdsp_9632_aeb_t h9632_aeb;
4643
4644 if (hdsp->io_type != H9632) return -EINVAL;
4645 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4646 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4647 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4648 return -EFAULT;
4649 break;
4650 }
4651 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4652 hdsp_version_t hdsp_version;
4653 int err;
4654
4655 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4656 if (hdsp->io_type == Undefined) {
4657 if ((err = hdsp_get_iobox_version(hdsp)) < 0) {
4658 return err;
4659 }
4660 }
4661 hdsp_version.io_type = hdsp->io_type;
4662 hdsp_version.firmware_rev = hdsp->firmware_rev;
4663 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) {
4664 return -EFAULT;
4665 }
4666 break;
4667 }
4668 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4669 hdsp_firmware_t __user *firmware;
4670 u32 __user *firmware_data;
4671 int err;
4672
4673 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4674 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4675 if (hdsp->io_type == Undefined) return -EINVAL;
4676
4677 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4678 return -EBUSY;
4679
4680 snd_printk("Hammerfall-DSP: initializing firmware upload\n");
4681 firmware = (hdsp_firmware_t __user *)argp;
4682
4683 if (get_user(firmware_data, &firmware->firmware_data)) {
4684 return -EFAULT;
4685 }
4686
4687 if (hdsp_check_for_iobox (hdsp)) {
4688 return -EIO;
4689 }
4690
4691 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0) {
4692 return -EFAULT;
4693 }
4694
4695 hdsp->state |= HDSP_FirmwareCached;
4696
4697 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) {
4698 return err;
4699 }
4700
4701 if (!(hdsp->state & HDSP_InitializationComplete)) {
4702 if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
4703 return err;
4704 }
4705
4706 snd_hdsp_initialize_channels(hdsp);
4707 snd_hdsp_initialize_midi_flush(hdsp);
4708
4709 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4710 snd_printk("Hammerfall-DSP: error creating alsa devices\n");
4711 return err;
4712 }
4713 }
4714 break;
4715 }
4716 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4717 hdsp_mixer_t __user *mixer = (hdsp_mixer_t __user *)argp;
4718 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4719 return -EFAULT;
4720 break;
4721 }
4722 default:
4723 return -EINVAL;
4724 }
4725 return 0;
4726 }
4727
4728 static snd_pcm_ops_t snd_hdsp_playback_ops = {
4729 .open = snd_hdsp_playback_open,
4730 .close = snd_hdsp_playback_release,
4731 .ioctl = snd_hdsp_ioctl,
4732 .hw_params = snd_hdsp_hw_params,
4733 .prepare = snd_hdsp_prepare,
4734 .trigger = snd_hdsp_trigger,
4735 .pointer = snd_hdsp_hw_pointer,
4736 .copy = snd_hdsp_playback_copy,
4737 .silence = snd_hdsp_hw_silence,
4738 };
4739
4740 static snd_pcm_ops_t snd_hdsp_capture_ops = {
4741 .open = snd_hdsp_capture_open,
4742 .close = snd_hdsp_capture_release,
4743 .ioctl = snd_hdsp_ioctl,
4744 .hw_params = snd_hdsp_hw_params,
4745 .prepare = snd_hdsp_prepare,
4746 .trigger = snd_hdsp_trigger,
4747 .pointer = snd_hdsp_hw_pointer,
4748 .copy = snd_hdsp_capture_copy,
4749 };
4750
4751 static int __devinit snd_hdsp_create_hwdep(snd_card_t *card,
4752 hdsp_t *hdsp)
4753 {
4754 snd_hwdep_t *hw;
4755 int err;
4756
4757 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4758 return err;
4759
4760 hdsp->hwdep = hw;
4761 hw->private_data = hdsp;
4762 strcpy(hw->name, "HDSP hwdep interface");
4763
4764 hw->ops.open = snd_hdsp_hwdep_dummy_op;
4765 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4766 hw->ops.release = snd_hdsp_hwdep_dummy_op;
4767
4768 return 0;
4769 }
4770
4771 static int snd_hdsp_create_pcm(snd_card_t *card, hdsp_t *hdsp)
4772 {
4773 snd_pcm_t *pcm;
4774 int err;
4775
4776 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4777 return err;
4778
4779 hdsp->pcm = pcm;
4780 pcm->private_data = hdsp;
4781 strcpy(pcm->name, hdsp->card_name);
4782
4783 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4784 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4785
4786 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4787
4788 return 0;
4789 }
4790
4791 static void snd_hdsp_9652_enable_mixer (hdsp_t *hdsp)
4792 {
4793 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4794 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4795 }
4796
4797 static int snd_hdsp_enable_io (hdsp_t *hdsp)
4798 {
4799 int i;
4800
4801 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4802 snd_printk("Hammerfall-DSP: enable_io fifo_wait failed\n");
4803 return -EIO;
4804 }
4805
4806 for (i = 0; i < hdsp->max_channels; ++i) {
4807 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4808 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4809 }
4810
4811 return 0;
4812 }
4813
4814 static void snd_hdsp_initialize_channels(hdsp_t *hdsp)
4815 {
4816 int status, aebi_channels, aebo_channels;
4817
4818 switch (hdsp->io_type) {
4819 case Digiface:
4820 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4821 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4822 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4823 break;
4824
4825 case H9652:
4826 hdsp->card_name = "RME Hammerfall HDSP 9652";
4827 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4828 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4829 break;
4830
4831 case H9632:
4832 status = hdsp_read(hdsp, HDSP_statusRegister);
4833 /* HDSP_AEBx bits are low when AEB are connected */
4834 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4835 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4836 hdsp->card_name = "RME Hammerfall HDSP 9632";
4837 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4838 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4839 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4840 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4841 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4842 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4843 break;
4844
4845 case Multiface:
4846 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4847 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4848 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4849 break;
4850
4851 default:
4852 /* should never get here */
4853 break;
4854 }
4855 }
4856
4857 static void snd_hdsp_initialize_midi_flush (hdsp_t *hdsp)
4858 {
4859 snd_hdsp_flush_midi_input (hdsp, 0);
4860 snd_hdsp_flush_midi_input (hdsp, 1);
4861 }
4862
4863 static int snd_hdsp_create_alsa_devices(snd_card_t *card, hdsp_t *hdsp)
4864 {
4865 int err;
4866
4867 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4868 snd_printk("Hammerfall-DSP: Error creating pcm interface\n");
4869 return err;
4870 }
4871
4872
4873 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4874 snd_printk("Hammerfall-DSP: Error creating first midi interface\n");
4875 return err;
4876 }
4877
4878 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
4879 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4880 snd_printk("Hammerfall-DSP: Error creating second midi interface\n");
4881 return err;
4882 }
4883 }
4884
4885 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4886 snd_printk("Hammerfall-DSP: Error creating ctl interface\n");
4887 return err;
4888 }
4889
4890 snd_hdsp_proc_init(hdsp);
4891
4892 hdsp->system_sample_rate = -1;
4893 hdsp->playback_pid = -1;
4894 hdsp->capture_pid = -1;
4895 hdsp->capture_substream = NULL;
4896 hdsp->playback_substream = NULL;
4897
4898 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4899 snd_printk("Hammerfall-DSP: Error setting default values\n");
4900 return err;
4901 }
4902
4903 if (!(hdsp->state & HDSP_InitializationComplete)) {
4904 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4905 hdsp->port, hdsp->irq);
4906
4907 if ((err = snd_card_register(card)) < 0) {
4908 snd_printk("Hammerfall-DSP: error registering card\n");
4909 return err;
4910 }
4911 hdsp->state |= HDSP_InitializationComplete;
4912 }
4913
4914 return 0;
4915 }
4916
4917 #ifdef HDSP_FW_LOADER
4918 /* load firmware via hotplug fw loader */
4919 static int __devinit hdsp_request_fw_loader(hdsp_t *hdsp)
4920 {
4921 const char *fwfile;
4922 const struct firmware *fw;
4923 int err;
4924
4925 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4926 return 0;
4927 if (hdsp->io_type == Undefined) {
4928 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4929 return err;
4930 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4931 return 0;
4932 }
4933
4934 /* caution: max length of firmware filename is 30! */
4935 switch (hdsp->io_type) {
4936 case Multiface:
4937 if (hdsp->firmware_rev == 0xa)
4938 fwfile = "multiface_firmware.bin";
4939 else
4940 fwfile = "multiface_firmware_rev11.bin";
4941 break;
4942 case Digiface:
4943 if (hdsp->firmware_rev == 0xa)
4944 fwfile = "digiface_firmware.bin";
4945 else
4946 fwfile = "digiface_firmware_rev11.bin";
4947 break;
4948 default:
4949 snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type);
4950 return -EINVAL;
4951 }
4952
4953 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
4954 snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile);
4955 return -ENOENT;
4956 }
4957 if (fw->size < sizeof(hdsp->firmware_cache)) {
4958 snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n",
4959 (int)fw->size, (int)sizeof(hdsp->firmware_cache));
4960 release_firmware(fw);
4961 return -EINVAL;
4962 }
4963
4964 memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache));
4965
4966 release_firmware(fw);
4967
4968 hdsp->state |= HDSP_FirmwareCached;
4969
4970 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4971 return err;
4972
4973 if (!(hdsp->state & HDSP_InitializationComplete)) {
4974 if ((err = snd_hdsp_enable_io(hdsp)) < 0) {
4975 return err;
4976 }
4977
4978 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
4979 snd_printk("Hammerfall-DSP: error creating hwdep device\n");
4980 return err;
4981 }
4982 snd_hdsp_initialize_channels(hdsp);
4983 snd_hdsp_initialize_midi_flush(hdsp);
4984 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4985 snd_printk("Hammerfall-DSP: error creating alsa devices\n");
4986 return err;
4987 }
4988 }
4989 return 0;
4990 }
4991 #endif
4992
4993 static int __devinit snd_hdsp_create(snd_card_t *card,
4994 hdsp_t *hdsp)
4995 {
4996 struct pci_dev *pci = hdsp->pci;
4997 int err;
4998 int is_9652 = 0;
4999 int is_9632 = 0;
5000
5001 hdsp->irq = -1;
5002 hdsp->state = 0;
5003 hdsp->midi[0].rmidi = NULL;
5004 hdsp->midi[1].rmidi = NULL;
5005 hdsp->midi[0].input = NULL;
5006 hdsp->midi[1].input = NULL;
5007 hdsp->midi[0].output = NULL;
5008 hdsp->midi[1].output = NULL;
5009 hdsp->midi[0].pending = 0;
5010 hdsp->midi[1].pending = 0;
5011 spin_lock_init(&hdsp->midi[0].lock);
5012 spin_lock_init(&hdsp->midi[1].lock);
5013 hdsp->iobase = NULL;
5014 hdsp->control_register = 0;
5015 hdsp->control2_register = 0;
5016 hdsp->io_type = Undefined;
5017 hdsp->max_channels = 26;
5018
5019 hdsp->card = card;
5020
5021 spin_lock_init(&hdsp->lock);
5022
5023 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5024
5025 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5026 hdsp->firmware_rev &= 0xff;
5027
5028 /* From Martin Bjoernsen :
5029 "It is important that the card's latency timer register in
5030 the PCI configuration space is set to a value much larger
5031 than 0 by the computer's BIOS or the driver.
5032 The windows driver always sets this 8 bit register [...]
5033 to its maximum 255 to avoid problems with some computers."
5034 */
5035 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5036
5037 strcpy(card->driver, "H-DSP");
5038 strcpy(card->mixername, "Xilinx FPGA");
5039
5040 if (hdsp->firmware_rev < 0xa) {
5041 return -ENODEV;
5042 } else if (hdsp->firmware_rev < 0x64) {
5043 hdsp->card_name = "RME Hammerfall DSP";
5044 } else if (hdsp->firmware_rev < 0x96) {
5045 hdsp->card_name = "RME HDSP 9652";
5046 is_9652 = 1;
5047 } else {
5048 hdsp->card_name = "RME HDSP 9632";
5049 hdsp->max_channels = 16;
5050 is_9632 = 1;
5051 }
5052
5053 if ((err = pci_enable_device(pci)) < 0) {
5054 return err;
5055 }
5056
5057 pci_set_master(hdsp->pci);
5058
5059 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5060 return err;
5061 hdsp->port = pci_resource_start(pci, 0);
5062 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5063 snd_printk("Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5064 return -EBUSY;
5065 }
5066
5067 if (request_irq(pci->irq, snd_hdsp_interrupt, SA_INTERRUPT|SA_SHIRQ, "hdsp", (void *)hdsp)) {
5068 snd_printk("Hammerfall-DSP: unable to use IRQ %d\n", pci->irq);
5069 return -EBUSY;
5070 }
5071
5072 hdsp->irq = pci->irq;
5073 hdsp->precise_ptr = 1;
5074 hdsp->use_midi_tasklet = 1;
5075
5076 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) {
5077 return err;
5078 }
5079
5080 if (!is_9652 && !is_9632) {
5081 /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */
5082 if ((1000 / HZ) < 2000) {
5083 set_current_state(TASK_UNINTERRUPTIBLE);
5084 schedule_timeout((2000 * HZ + 999) / 1000);
5085 } else {
5086 mdelay(2000);
5087 }
5088
5089 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5090 #ifdef HDSP_FW_LOADER
5091 if ((err = hdsp_request_fw_loader(hdsp)) < 0) {
5092 /* we don't fail as this can happen
5093 if userspace is not ready for
5094 firmware upload
5095 */
5096 snd_printk("Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n");
5097 } else {
5098 /* init is complete, we return */
5099 return 0;
5100 }
5101 #endif
5102 /* no iobox connected, we defer initialization */
5103 snd_printk("Hammerfall-DSP: card initialization pending : waiting for firmware\n");
5104 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5105 return err;
5106 }
5107 return 0;
5108 } else {
5109 snd_printk("Hammerfall-DSP: Firmware already present, initializing card.\n");
5110 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) {
5111 hdsp->io_type = Multiface;
5112 } else {
5113 hdsp->io_type = Digiface;
5114 }
5115 }
5116 }
5117
5118 if ((err = snd_hdsp_enable_io(hdsp)) != 0) {
5119 return err;
5120 }
5121
5122 if (is_9652) {
5123 hdsp->io_type = H9652;
5124 }
5125
5126 if (is_9632) {
5127 hdsp->io_type = H9632;
5128 }
5129
5130 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) {
5131 return err;
5132 }
5133
5134 snd_hdsp_initialize_channels(hdsp);
5135 snd_hdsp_initialize_midi_flush(hdsp);
5136
5137 hdsp->state |= HDSP_FirmwareLoaded;
5138
5139 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) {
5140 return err;
5141 }
5142
5143 return 0;
5144 }
5145
5146 static int snd_hdsp_free(hdsp_t *hdsp)
5147 {
5148 if (hdsp->port) {
5149 /* stop the audio, and cancel all interrupts */
5150 tasklet_kill(&hdsp->midi_tasklet);
5151 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5152 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5153 }
5154
5155 if (hdsp->irq >= 0)
5156 free_irq(hdsp->irq, (void *)hdsp);
5157
5158 snd_hdsp_free_buffers(hdsp);
5159
5160 if (hdsp->iobase)
5161 iounmap(hdsp->iobase);
5162
5163 if (hdsp->port)
5164 pci_release_regions(hdsp->pci);
5165
5166 pci_disable_device(hdsp->pci);
5167 return 0;
5168 }
5169
5170 static void snd_hdsp_card_free(snd_card_t *card)
5171 {
5172 hdsp_t *hdsp = (hdsp_t *) card->private_data;
5173
5174 if (hdsp)
5175 snd_hdsp_free(hdsp);
5176 }
5177
5178 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5179 const struct pci_device_id *pci_id)
5180 {
5181 static int dev;
5182 hdsp_t *hdsp;
5183 snd_card_t *card;
5184 int err;
5185
5186 if (dev >= SNDRV_CARDS)
5187 return -ENODEV;
5188 if (!enable[dev]) {
5189 dev++;
5190 return -ENOENT;
5191 }
5192
5193 if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(hdsp_t))))
5194 return -ENOMEM;
5195
5196 hdsp = (hdsp_t *) card->private_data;
5197 card->private_free = snd_hdsp_card_free;
5198 hdsp->dev = dev;
5199 hdsp->pci = pci;
5200 snd_card_set_dev(card, &pci->dev);
5201
5202 if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5203 snd_card_free(card);
5204 return err;
5205 }
5206
5207 strcpy(card->shortname, "Hammerfall DSP");
5208 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5209 hdsp->port, hdsp->irq);
5210
5211 if ((err = snd_card_register(card)) < 0) {
5212 snd_card_free(card);
5213 return err;
5214 }
5215 pci_set_drvdata(pci, card);
5216 dev++;
5217 return 0;
5218 }
5219
5220 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5221 {
5222 snd_card_free(pci_get_drvdata(pci));
5223 pci_set_drvdata(pci, NULL);
5224 }
5225
5226 static struct pci_driver driver = {
5227 .name = "RME Hammerfall DSP",
5228 .id_table = snd_hdsp_ids,
5229 .probe = snd_hdsp_probe,
5230 .remove = __devexit_p(snd_hdsp_remove),
5231 };
5232
5233 static int __init alsa_card_hdsp_init(void)
5234 {
5235 return pci_register_driver(&driver);
5236 }
5237
5238 static void __exit alsa_card_hdsp_exit(void)
5239 {
5240 pci_unregister_driver(&driver);
5241 }
5242
5243 module_init(alsa_card_hdsp_init)
5244 module_exit(alsa_card_hdsp_exit)
Linux kernel - Deliverables
This page took 0.131442 seconds and 6 git commands to generate.