sound/soc/amd/acp.h

   1 #ifndef __ACP_HW_H
   2 #define __ACP_HW_H
   3
   4 #include "include/acp_2_2_d.h"
   5 #include "include/acp_2_2_sh_mask.h"
   6
   7 #define ACP_PAGE_SIZE_4K_ENABLE                 0x02
   8
   9 #define ACP_PLAYBACK_PTE_OFFSET                 10
  10 #define ACP_CAPTURE_PTE_OFFSET                  0
  11
  12 #define ACP_GARLIC_CNTL_DEFAULT                 0x00000FB4
  13 #define ACP_ONION_CNTL_DEFAULT                  0x00000FB4
  14
  15 #define ACP_PHYSICAL_BASE                       0x14000
  16
  17 /* Playback SRAM address (as a destination in dma descriptor) */
  18 #define ACP_SHARED_RAM_BANK_1_ADDRESS           0x4002000
  19
  20 /* Capture SRAM address (as a source in dma descriptor) */
  21 #define ACP_SHARED_RAM_BANK_5_ADDRESS           0x400A000
  22
  23 #define ACP_DMA_RESET_TIME                      10000
  24 #define ACP_CLOCK_EN_TIME_OUT_VALUE             0x000000FF
  25 #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE      0x000000FF
  26 #define ACP_DMA_COMPLETE_TIME_OUT_VALUE         0x000000FF
  27
  28 #define ACP_SRAM_BASE_ADDRESS                   0x4000000
  29 #define ACP_DAGB_GRP_SRAM_BASE_ADDRESS          0x4001000
  30 #define ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET      0x1000
  31 #define ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS  0x00000000
  32 #define ACP_INTERNAL_APERTURE_WINDOW_4_ADDRESS  0x01800000
  33
  34 #define TO_ACP_I2S_1   0x2
  35 #define TO_ACP_I2S_2   0x4
  36 #define FROM_ACP_I2S_1 0xa
  37 #define FROM_ACP_I2S_2 0xb
  38
  39 #define ACP_TILE_ON_MASK                0x03
  40 #define ACP_TILE_OFF_MASK               0x02
  41 #define ACP_TILE_ON_RETAIN_REG_MASK     0x1f
  42 #define ACP_TILE_OFF_RETAIN_REG_MASK    0x20
  43
  44 #define ACP_TILE_P1_MASK                0x3e
  45 #define ACP_TILE_P2_MASK                0x3d
  46 #define ACP_TILE_DSP0_MASK              0x3b
  47 #define ACP_TILE_DSP1_MASK              0x37
  48
  49 #define ACP_TILE_DSP2_MASK              0x2f
  50 /* Playback DMA channels */
  51 #define SYSRAM_TO_ACP_CH_NUM 12
  52 #define ACP_TO_I2S_DMA_CH_NUM 13
  53
  54 /* Capture DMA channels */
  55 #define ACP_TO_SYSRAM_CH_NUM 14
  56 #define I2S_TO_ACP_DMA_CH_NUM 15
  57
  58 #define NUM_DSCRS_PER_CHANNEL 2
  59
  60 #define PLAYBACK_START_DMA_DESCR_CH12 0
  61 #define PLAYBACK_END_DMA_DESCR_CH12 1
  62 #define PLAYBACK_START_DMA_DESCR_CH13 2
  63 #define PLAYBACK_END_DMA_DESCR_CH13 3
  64
  65 #define CAPTURE_START_DMA_DESCR_CH14 4
  66 #define CAPTURE_END_DMA_DESCR_CH14 5
  67 #define CAPTURE_START_DMA_DESCR_CH15 6
  68 #define CAPTURE_END_DMA_DESCR_CH15 7
  69
  70 enum acp_dma_priority_level {
  71         /* 0x0 Specifies the DMA channel is given normal priority */
  72         ACP_DMA_PRIORITY_LEVEL_NORMAL = 0x0,
  73         /* 0x1 Specifies the DMA channel is given high priority */
  74         ACP_DMA_PRIORITY_LEVEL_HIGH = 0x1,
  75         ACP_DMA_PRIORITY_LEVEL_FORCESIZE = 0xFF
  76 };
  77
  78 struct audio_substream_data {
  79         struct page *pg;
  80         unsigned int order;
  81         u16 num_of_pages;
  82         u16 direction;
  83         uint64_t size;
  84         void __iomem *acp_mmio;
  85 };
  86
  87 enum {
  88         ACP_TILE_P1 = 0,
  89         ACP_TILE_P2,
  90         ACP_TILE_DSP0,
  91         ACP_TILE_DSP1,
  92         ACP_TILE_DSP2,
  93 };
  94
  95 enum {
  96         ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION = 0x0,
  97         ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC = 0x1,
  98         ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM = 0x8,
  99         ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM = 0x9,
 100         ACP_DMA_ATTRIBUTES_FORCE_SIZE = 0xF
 101 };
 102
 103 typedef struct acp_dma_dscr_transfer {
 104         /* Specifies the source memory location for the DMA data transfer. */
 105         u32 src;
 106         /* Specifies the destination memory location to where the data will
 107          * be transferred.
 108         */
 109         u32 dest;
 110         /* Specifies the number of bytes need to be transferred
 111         * from source to destination memory.Transfer direction & IOC enable
 112         */
 113         u32 xfer_val;
 114         /* Reserved for future use */
 115         u32 reserved;
 116 } acp_dma_dscr_transfer_t;
 117
 118 #endif /*__ACP_HW_H */