d6b9fd5e6123a6434bd090aa33c7a3d4a03c5f58
[deliverable/linux.git] / sound / soc / at32 / playpaq_wm8510.c
1 /* sound/soc/at32/playpaq_wm8510.c
2 * ASoC machine driver for PlayPaq using WM8510 codec
3 *
4 * Copyright (C) 2008 Long Range Systems
5 * Geoffrey Wossum <gwossum@acm.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This code is largely inspired by sound/soc/at91/eti_b1_wm8731.c
12 *
13 * NOTE: If you don't have the AT32 enhanced portmux configured (which
14 * isn't currently in the mainline or Atmel patched kernel), you will
15 * need to set the MCLK pin (PA30) to peripheral A in your board initialization
16 * code. Something like:
17 * at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
18 *
19 */
20
21 /* #define DEBUG */
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/version.h>
26 #include <linux/kernel.h>
27 #include <linux/errno.h>
28 #include <linux/clk.h>
29 #include <linux/timer.h>
30 #include <linux/interrupt.h>
31 #include <linux/platform_device.h>
32
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/pcm_params.h>
36 #include <sound/soc.h>
37 #include <sound/soc-dapm.h>
38
39 #include <asm/arch/at32ap700x.h>
40 #include <asm/arch/portmux.h>
41
42 #include "../codecs/wm8510.h"
43 #include "at32-pcm.h"
44 #include "at32-ssc.h"
45
46
47 /*-------------------------------------------------------------------------*\
48 * constants
49 \*-------------------------------------------------------------------------*/
50 #define MCLK_PIN GPIO_PIN_PA(30)
51 #define MCLK_PERIPH GPIO_PERIPH_A
52
53
54 /*-------------------------------------------------------------------------*\
55 * data types
56 \*-------------------------------------------------------------------------*/
57 /* SSC clocking data */
58 struct ssc_clock_data {
59 /* CMR div */
60 unsigned int cmr_div;
61
62 /* Frame period (as needed by xCMR.PERIOD) */
63 unsigned int period;
64
65 /* The SSC clock rate these settings where calculated for */
66 unsigned long ssc_rate;
67 };
68
69
70 /*-------------------------------------------------------------------------*\
71 * module data
72 \*-------------------------------------------------------------------------*/
73 static struct clk *_gclk0;
74 static struct clk *_pll0;
75
76 #define CODEC_CLK (_gclk0)
77
78
79 /*-------------------------------------------------------------------------*\
80 * Sound SOC operations
81 \*-------------------------------------------------------------------------*/
82 #if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
83 static struct ssc_clock_data playpaq_wm8510_calc_ssc_clock(
84 struct snd_pcm_hw_params *params,
85 struct snd_soc_cpu_dai *cpu_dai)
86 {
87 struct at32_ssc_info *ssc_p = cpu_dai->private_data;
88 struct ssc_device *ssc = ssc_p->ssc;
89 struct ssc_clock_data cd;
90 unsigned int rate, width_bits, channels;
91 unsigned int bitrate, ssc_div;
92 unsigned actual_rate;
93
94
95 /*
96 * Figure out required bitrate
97 */
98 rate = params_rate(params);
99 channels = params_channels(params);
100 width_bits = snd_pcm_format_physical_width(params_format(params));
101 bitrate = rate * width_bits * channels;
102
103
104 /*
105 * Figure out required SSC divider and period for required bitrate
106 */
107 cd.ssc_rate = clk_get_rate(ssc->clk);
108 ssc_div = cd.ssc_rate / bitrate;
109 cd.cmr_div = ssc_div / 2;
110 if (ssc_div & 1) {
111 /* round cmr_div up */
112 cd.cmr_div++;
113 }
114 cd.period = width_bits - 1;
115
116
117 /*
118 * Find actual rate, compare to requested rate
119 */
120 actual_rate = (cd.ssc_rate / (cd.cmr_div * 2)) / (2 * (cd.period + 1));
121 pr_debug("playpaq_wm8510: Request rate = %d, actual rate = %d\n",
122 rate, actual_rate);
123
124
125 return cd;
126 }
127 #endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
128
129
130
131 static int playpaq_wm8510_hw_params(struct snd_pcm_substream *substream,
132 struct snd_pcm_hw_params *params)
133 {
134 struct snd_soc_pcm_runtime *rtd = substream->private_data;
135 struct snd_soc_codec_dai *codec_dai = rtd->dai->codec_dai;
136 struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
137 struct at32_ssc_info *ssc_p = cpu_dai->private_data;
138 struct ssc_device *ssc = ssc_p->ssc;
139 unsigned int pll_out = 0, bclk = 0, mclk_div = 0;
140 int ret;
141
142
143 /* Due to difficulties with getting the correct clocks from the AT32's
144 * PLL0, we're going to let the CODEC be in charge of all the clocks
145 */
146 #if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
147 const unsigned int fmt = (SND_SOC_DAIFMT_I2S |
148 SND_SOC_DAIFMT_NB_NF |
149 SND_SOC_DAIFMT_CBM_CFM);
150 #else
151 struct ssc_clock_data cd;
152 const unsigned int fmt = (SND_SOC_DAIFMT_I2S |
153 SND_SOC_DAIFMT_NB_NF |
154 SND_SOC_DAIFMT_CBS_CFS);
155 #endif
156
157 if (ssc == NULL) {
158 pr_warning("playpaq_wm8510_hw_params: ssc is NULL!\n");
159 return -EINVAL;
160 }
161
162
163 /*
164 * Figure out PLL and BCLK dividers for WM8510
165 */
166 switch (params_rate(params)) {
167 case 48000:
168 pll_out = 12288000;
169 mclk_div = WM8510_MCLKDIV_1;
170 bclk = WM8510_BCLKDIV_8;
171 break;
172
173 case 44100:
174 pll_out = 11289600;
175 mclk_div = WM8510_MCLKDIV_1;
176 bclk = WM8510_BCLKDIV_8;
177 break;
178
179 case 22050:
180 pll_out = 11289600;
181 mclk_div = WM8510_MCLKDIV_2;
182 bclk = WM8510_BCLKDIV_8;
183 break;
184
185 case 16000:
186 pll_out = 12288000;
187 mclk_div = WM8510_MCLKDIV_3;
188 bclk = WM8510_BCLKDIV_8;
189 break;
190
191 case 11025:
192 pll_out = 11289600;
193 mclk_div = WM8510_MCLKDIV_4;
194 bclk = WM8510_BCLKDIV_8;
195 break;
196
197 case 8000:
198 pll_out = 12288000;
199 mclk_div = WM8510_MCLKDIV_6;
200 bclk = WM8510_BCLKDIV_8;
201 break;
202
203 default:
204 pr_warning("playpaq_wm8510: Unsupported sample rate %d\n",
205 params_rate(params));
206 return -EINVAL;
207 }
208
209
210 /*
211 * set CPU and CODEC DAI configuration
212 */
213 ret = codec_dai->dai_ops.set_fmt(codec_dai, fmt);
214 if (ret < 0) {
215 pr_warning("playpaq_wm8510: "
216 "Failed to set CODEC DAI format (%d)\n",
217 ret);
218 return ret;
219 }
220 ret = cpu_dai->dai_ops.set_fmt(cpu_dai, fmt);
221 if (ret < 0) {
222 pr_warning("playpaq_wm8510: "
223 "Failed to set CPU DAI format (%d)\n",
224 ret);
225 return ret;
226 }
227
228
229 /*
230 * Set CPU clock configuration
231 */
232 #if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
233 cd = playpaq_wm8510_calc_ssc_clock(params, cpu_dai);
234 pr_debug("playpaq_wm8510: cmr_div = %d, period = %d\n",
235 cd.cmr_div, cd.period);
236 ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai,
237 AT32_SSC_CMR_DIV, cd.cmr_div);
238 if (ret < 0) {
239 pr_warning("playpaq_wm8510: Failed to set CPU CMR_DIV (%d)\n",
240 ret);
241 return ret;
242 }
243 ret = cpu_dai->dai_ops.set_clkdiv(cpu_dai, AT32_SSC_TCMR_PERIOD,
244 cd.period);
245 if (ret < 0) {
246 pr_warning("playpaq_wm8510: "
247 "Failed to set CPU transmit period (%d)\n",
248 ret);
249 return ret;
250 }
251 #endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
252
253
254 /*
255 * Set CODEC clock configuration
256 */
257 pr_debug("playpaq_wm8510: "
258 "pll_in = %ld, pll_out = %u, bclk = %x, mclk = %x\n",
259 clk_get_rate(CODEC_CLK), pll_out, bclk, mclk_div);
260
261
262 #if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
263 ret = codec_dai->dai_ops.set_clkdiv(codec_dai, WM8510_BCLKDIV, bclk);
264 if (ret < 0) {
265 pr_warning
266 ("playpaq_wm8510: Failed to set CODEC DAI BCLKDIV (%d)\n",
267 ret);
268 return ret;
269 }
270 #endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
271
272
273 ret = codec_dai->dai_ops.set_pll(codec_dai, 0,
274 clk_get_rate(CODEC_CLK), pll_out);
275 if (ret < 0) {
276 pr_warning("playpaq_wm8510: Failed to set CODEC DAI PLL (%d)\n",
277 ret);
278 return ret;
279 }
280
281
282 ret = codec_dai->dai_ops.set_clkdiv(codec_dai,
283 WM8510_MCLKDIV, mclk_div);
284 if (ret < 0) {
285 pr_warning("playpaq_wm8510: Failed to set CODEC MCLKDIV (%d)\n",
286 ret);
287 return ret;
288 }
289
290
291 return 0;
292 }
293
294
295
296 static struct snd_soc_ops playpaq_wm8510_ops = {
297 .hw_params = playpaq_wm8510_hw_params,
298 };
299
300
301
302 static const struct snd_soc_dapm_widget playpaq_dapm_widgets[] = {
303 SND_SOC_DAPM_MIC("Int Mic", NULL),
304 SND_SOC_DAPM_SPK("Ext Spk", NULL),
305 };
306
307
308
309 static const char *intercon[][3] = {
310 /* speaker connected to SPKOUT */
311 {"Ext Spk", NULL, "SPKOUTP"},
312 {"Ext Spk", NULL, "SPKOUTN"},
313
314 {"Mic Bias", NULL, "Int Mic"},
315 {"MICN", NULL, "Mic Bias"},
316 {"MICP", NULL, "Mic Bias"},
317
318 /* Terminator */
319 {NULL, NULL, NULL},
320 };
321
322
323
324 static int playpaq_wm8510_init(struct snd_soc_codec *codec)
325 {
326 int i;
327
328 /*
329 * Add DAPM widgets
330 */
331 for (i = 0; i < ARRAY_SIZE(playpaq_dapm_widgets); i++)
332 snd_soc_dapm_new_control(codec, &playpaq_dapm_widgets[i]);
333
334
335
336 /*
337 * Setup audio path interconnects
338 */
339 for (i = 0; intercon[i][0] != NULL; i++) {
340 snd_soc_dapm_connect_input(codec,
341 intercon[i][0],
342 intercon[i][1], intercon[i][2]);
343 }
344
345
346 /* always connected endpoints */
347 snd_soc_dapm_set_endpoint(codec, "Int Mic", 1);
348 snd_soc_dapm_set_endpoint(codec, "Ext Spk", 1);
349 snd_soc_dapm_sync_endpoints(codec);
350
351
352
353 /* Make CSB show PLL rate */
354 codec->dai->dai_ops.set_clkdiv(codec->dai, WM8510_OPCLKDIV,
355 WM8510_OPCLKDIV_1 | 4);
356
357 return 0;
358 }
359
360
361
362 static struct snd_soc_dai_link playpaq_wm8510_dai = {
363 .name = "WM8510",
364 .stream_name = "WM8510 PCM",
365 .cpu_dai = &at32_ssc_dai[0],
366 .codec_dai = &wm8510_dai,
367 .init = playpaq_wm8510_init,
368 .ops = &playpaq_wm8510_ops,
369 };
370
371
372
373 static struct snd_soc_machine snd_soc_machine_playpaq = {
374 .name = "LRS_PlayPaq_WM8510",
375 .dai_link = &playpaq_wm8510_dai,
376 .num_links = 1,
377 };
378
379
380
381 static struct wm8510_setup_data playpaq_wm8510_setup = {
382 .i2c_address = 0x1a,
383 };
384
385
386
387 static struct snd_soc_device playpaq_wm8510_snd_devdata = {
388 .machine = &snd_soc_machine_playpaq,
389 .platform = &at32_soc_platform,
390 .codec_dev = &soc_codec_dev_wm8510,
391 .codec_data = &playpaq_wm8510_setup,
392 };
393
394 static struct platform_device *playpaq_snd_device;
395
396
397 static int __init playpaq_asoc_init(void)
398 {
399 int ret = 0;
400 struct at32_ssc_info *ssc_p = playpaq_wm8510_dai.cpu_dai->private_data;
401 struct ssc_device *ssc = NULL;
402
403
404 /*
405 * Request SSC device
406 */
407 ssc = ssc_request(0);
408 if (IS_ERR(ssc)) {
409 ret = PTR_ERR(ssc);
410 ssc = NULL;
411 goto err_ssc;
412 }
413 ssc_p->ssc = ssc;
414
415
416 /*
417 * Configure MCLK for WM8510
418 */
419 _gclk0 = clk_get(NULL, "gclk0");
420 if (IS_ERR(_gclk0)) {
421 _gclk0 = NULL;
422 goto err_gclk0;
423 }
424 _pll0 = clk_get(NULL, "pll0");
425 if (IS_ERR(_pll0)) {
426 _pll0 = NULL;
427 goto err_pll0;
428 }
429 if (clk_set_parent(_gclk0, _pll0)) {
430 pr_warning("snd-soc-playpaq: "
431 "Failed to set PLL0 as parent for DAC clock\n");
432 goto err_set_clk;
433 }
434 clk_set_rate(CODEC_CLK, 12000000);
435 clk_enable(CODEC_CLK);
436
437 #if defined CONFIG_AT32_ENHANCED_PORTMUX
438 at32_select_periph(MCLK_PIN, MCLK_PERIPH, 0);
439 #endif
440
441
442 /*
443 * Create and register platform device
444 */
445 playpaq_snd_device = platform_device_alloc("soc-audio", 0);
446 if (playpaq_snd_device == NULL) {
447 ret = -ENOMEM;
448 goto err_device_alloc;
449 }
450
451 platform_set_drvdata(playpaq_snd_device, &playpaq_wm8510_snd_devdata);
452 playpaq_wm8510_snd_devdata.dev = &playpaq_snd_device->dev;
453
454 ret = platform_device_add(playpaq_snd_device);
455 if (ret) {
456 pr_warning("playpaq_wm8510: platform_device_add failed (%d)\n",
457 ret);
458 goto err_device_add;
459 }
460
461 return 0;
462
463
464 err_device_add:
465 if (playpaq_snd_device != NULL) {
466 platform_device_put(playpaq_snd_device);
467 playpaq_snd_device = NULL;
468 }
469 err_device_alloc:
470 err_set_clk:
471 if (_pll0 != NULL) {
472 clk_put(_pll0);
473 _pll0 = NULL;
474 }
475 err_pll0:
476 if (_gclk0 != NULL) {
477 clk_put(_gclk0);
478 _gclk0 = NULL;
479 }
480 err_gclk0:
481 if (ssc != NULL) {
482 ssc_free(ssc);
483 ssc = NULL;
484 }
485 err_ssc:
486 return ret;
487 }
488
489
490 static void __exit playpaq_asoc_exit(void)
491 {
492 struct at32_ssc_info *ssc_p = playpaq_wm8510_dai.cpu_dai->private_data;
493 struct ssc_device *ssc;
494
495 if (ssc_p != NULL) {
496 ssc = ssc_p->ssc;
497 if (ssc != NULL)
498 ssc_free(ssc);
499 ssc_p->ssc = NULL;
500 }
501
502 if (_gclk0 != NULL) {
503 clk_put(_gclk0);
504 _gclk0 = NULL;
505 }
506 if (_pll0 != NULL) {
507 clk_put(_pll0);
508 _pll0 = NULL;
509 }
510
511 #if defined CONFIG_AT32_ENHANCED_PORTMUX
512 at32_free_pin(MCLK_PIN);
513 #endif
514
515 platform_device_unregister(playpaq_snd_device);
516 playpaq_snd_device = NULL;
517 }
518
519 module_init(playpaq_asoc_init);
520 module_exit(playpaq_asoc_exit);
521
522 MODULE_AUTHOR("Geoffrey Wossum <gwossum@acm.org>");
523 MODULE_DESCRIPTION("ASoC machine driver for LRS PlayPaq");
524 MODULE_LICENSE("GPL");
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