sound/soc/cirrus/ep93xx-ac97.c

   1 /*
   2  * ASoC driver for Cirrus Logic EP93xx AC97 controller.
   3  *
   4  * Copyright (c) 2010 Mika Westerberg
   5  *
   6  * Based on s3c-ac97 ASoC driver by Jaswinder Singh.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/slab.h>
  20
  21 #include <sound/core.h>
  22 #include <sound/ac97_codec.h>
  23 #include <sound/soc.h>
  24
  25 #include <linux/platform_data/dma-ep93xx.h>
  26 #include "ep93xx-pcm.h"
  27
  28 /*
  29  * Per channel (1-4) registers.
  30  */
  31 #define AC97CH(n)               (((n) - 1) * 0x20)
  32
  33 #define AC97DR(n)               (AC97CH(n) + 0x0000)
  34
  35 #define AC97RXCR(n)             (AC97CH(n) + 0x0004)
  36 #define AC97RXCR_REN            BIT(0)
  37 #define AC97RXCR_RX3            BIT(3)
  38 #define AC97RXCR_RX4            BIT(4)
  39 #define AC97RXCR_CM             BIT(15)
  40
  41 #define AC97TXCR(n)             (AC97CH(n) + 0x0008)
  42 #define AC97TXCR_TEN            BIT(0)
  43 #define AC97TXCR_TX3            BIT(3)
  44 #define AC97TXCR_TX4            BIT(4)
  45 #define AC97TXCR_CM             BIT(15)
  46
  47 #define AC97SR(n)               (AC97CH(n) + 0x000c)
  48 #define AC97SR_TXFE             BIT(1)
  49 #define AC97SR_TXUE             BIT(6)
  50
  51 #define AC97RISR(n)             (AC97CH(n) + 0x0010)
  52 #define AC97ISR(n)              (AC97CH(n) + 0x0014)
  53 #define AC97IE(n)               (AC97CH(n) + 0x0018)
  54
  55 /*
  56  * Global AC97 controller registers.
  57  */
  58 #define AC97S1DATA              0x0080
  59 #define AC97S2DATA              0x0084
  60 #define AC97S12DATA             0x0088
  61
  62 #define AC97RGIS                0x008c
  63 #define AC97GIS                 0x0090
  64 #define AC97IM                  0x0094
  65 /*
  66  * Common bits for RGIS, GIS and IM registers.
  67  */
  68 #define AC97_SLOT2RXVALID       BIT(1)
  69 #define AC97_CODECREADY         BIT(5)
  70 #define AC97_SLOT2TXCOMPLETE    BIT(6)
  71
  72 #define AC97EOI                 0x0098
  73 #define AC97EOI_WINT            BIT(0)
  74 #define AC97EOI_CODECREADY      BIT(1)
  75
  76 #define AC97GCR                 0x009c
  77 #define AC97GCR_AC97IFE         BIT(0)
  78
  79 #define AC97RESET               0x00a0
  80 #define AC97RESET_TIMEDRESET    BIT(0)
  81
  82 #define AC97SYNC                0x00a4
  83 #define AC97SYNC_TIMEDSYNC      BIT(0)
  84
  85 #define AC97_TIMEOUT            msecs_to_jiffies(5)
  86
  87 /**
  88  * struct ep93xx_ac97_info - EP93xx AC97 controller info structure
  89  * @lock: mutex serializing access to the bus (slot 1 & 2 ops)
  90  * @dev: pointer to the platform device dev structure
  91  * @regs: mapped AC97 controller registers
  92  * @done: bus ops wait here for an interrupt
  93  */
  94 struct ep93xx_ac97_info {
  95         struct mutex            lock;
  96         struct device           *dev;
  97         void __iomem            *regs;
  98         struct completion       done;
  99 };
 100
 101 /* currently ALSA only supports a single AC97 device */
 102 static struct ep93xx_ac97_info *ep93xx_ac97_info;
 103
 104 static struct ep93xx_pcm_dma_params ep93xx_ac97_pcm_out = {
 105         .name           = "ac97-pcm-out",
 106         .dma_port       = EP93XX_DMA_AAC1,
 107 };
 108
 109 static struct ep93xx_pcm_dma_params ep93xx_ac97_pcm_in = {
 110         .name           = "ac97-pcm-in",
 111         .dma_port       = EP93XX_DMA_AAC1,
 112 };
 113
 114 static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info,
 115                                             unsigned reg)
 116 {
 117         return __raw_readl(info->regs + reg);
 118 }
 119
 120 static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info,
 121                                          unsigned reg, unsigned val)
 122 {
 123         __raw_writel(val, info->regs + reg);
 124 }
 125
 126 static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97,
 127                                        unsigned short reg)
 128 {
 129         struct ep93xx_ac97_info *info = ep93xx_ac97_info;
 130         unsigned short val;
 131
 132         mutex_lock(&info->lock);
 133
 134         ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
 135         ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID);
 136         if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) {
 137                 dev_warn(info->dev, "timeout reading register %x\n", reg);
 138                 mutex_unlock(&info->lock);
 139                 return -ETIMEDOUT;
 140         }
 141         val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA);
 142
 143         mutex_unlock(&info->lock);
 144         return val;
 145 }
 146
 147 static void ep93xx_ac97_write(struct snd_ac97 *ac97,
 148                               unsigned short reg,
 149                               unsigned short val)
 150 {
 151         struct ep93xx_ac97_info *info = ep93xx_ac97_info;
 152
 153         mutex_lock(&info->lock);
 154
 155         /*
 156          * Writes to the codec need to be done so that slot 2 is filled in
 157          * before slot 1.
 158          */
 159         ep93xx_ac97_write_reg(info, AC97S2DATA, val);
 160         ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
 161
 162         ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE);
 163         if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
 164                 dev_warn(info->dev, "timeout writing register %x\n", reg);
 165
 166         mutex_unlock(&info->lock);
 167 }
 168
 169 static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97)
 170 {
 171         struct ep93xx_ac97_info *info = ep93xx_ac97_info;
 172
 173         mutex_lock(&info->lock);
 174
 175         /*
 176          * We are assuming that before this functions gets called, the codec
 177          * BIT_CLK is stopped by forcing the codec into powerdown mode. We can
 178          * control the SYNC signal directly via AC97SYNC register. Using
 179          * TIMEDSYNC the controller will keep the SYNC high > 1us.
 180          */
 181         ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC);
 182         ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
 183         if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
 184                 dev_warn(info->dev, "codec warm reset timeout\n");
 185
 186         mutex_unlock(&info->lock);
 187 }
 188
 189 static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97)
 190 {
 191         struct ep93xx_ac97_info *info = ep93xx_ac97_info;
 192
 193         mutex_lock(&info->lock);
 194
 195         /*
 196          * For doing cold reset, we disable the AC97 controller interface, clear
 197          * WINT and CODECREADY bits, and finally enable the interface again.
 198          */
 199         ep93xx_ac97_write_reg(info, AC97GCR, 0);
 200         ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT);
 201         ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE);
 202
 203         /*
 204          * Now, assert the reset and wait for the codec to become ready.
 205          */
 206         ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET);
 207         ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
 208         if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
 209                 dev_warn(info->dev, "codec cold reset timeout\n");
 210
 211         /*
 212          * Give the codec some time to come fully out from the reset. This way
 213          * we ensure that the subsequent reads/writes will work.
 214          */
 215         usleep_range(15000, 20000);
 216
 217         mutex_unlock(&info->lock);
 218 }
 219
 220 static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id)
 221 {
 222         struct ep93xx_ac97_info *info = dev_id;
 223         unsigned status, mask;
 224
 225         /*
 226          * Just mask out the interrupt and wake up the waiting thread.
 227          * Interrupts are cleared via reading/writing to slot 1 & 2 registers by
 228          * the waiting thread.
 229          */
 230         status = ep93xx_ac97_read_reg(info, AC97GIS);
 231         mask = ep93xx_ac97_read_reg(info, AC97IM);
 232         mask &= ~status;
 233         ep93xx_ac97_write_reg(info, AC97IM, mask);
 234
 235         complete(&info->done);
 236         return IRQ_HANDLED;
 237 }
 238
 239 struct snd_ac97_bus_ops soc_ac97_ops = {
 240         .read           = ep93xx_ac97_read,
 241         .write          = ep93xx_ac97_write,
 242         .reset          = ep93xx_ac97_cold_reset,
 243         .warm_reset     = ep93xx_ac97_warm_reset,
 244 };
 245 EXPORT_SYMBOL_GPL(soc_ac97_ops);
 246
 247 static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream,
 248                                int cmd, struct snd_soc_dai *dai)
 249 {
 250         struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
 251         unsigned v = 0;
 252
 253         switch (cmd) {
 254         case SNDRV_PCM_TRIGGER_START:
 255         case SNDRV_PCM_TRIGGER_RESUME:
 256         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 257                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 258                         /*
 259                          * Enable compact mode, TX slots 3 & 4, and the TX FIFO
 260                          * itself.
 261                          */
 262                         v |= AC97TXCR_CM;
 263                         v |= AC97TXCR_TX3 | AC97TXCR_TX4;
 264                         v |= AC97TXCR_TEN;
 265                         ep93xx_ac97_write_reg(info, AC97TXCR(1), v);
 266                 } else {
 267                         /*
 268                          * Enable compact mode, RX slots 3 & 4, and the RX FIFO
 269                          * itself.
 270                          */
 271                         v |= AC97RXCR_CM;
 272                         v |= AC97RXCR_RX3 | AC97RXCR_RX4;
 273                         v |= AC97RXCR_REN;
 274                         ep93xx_ac97_write_reg(info, AC97RXCR(1), v);
 275                 }
 276                 break;
 277
 278         case SNDRV_PCM_TRIGGER_STOP:
 279         case SNDRV_PCM_TRIGGER_SUSPEND:
 280         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 281                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 282                         /*
 283                          * As per Cirrus EP93xx errata described below:
 284                          *
 285                          * http://www.cirrus.com/en/pubs/errata/ER667E2B.pdf
 286                          *
 287                          * we will wait for the TX FIFO to be empty before
 288                          * clearing the TEN bit.
 289                          */
 290                         unsigned long timeout = jiffies + AC97_TIMEOUT;
 291
 292                         do {
 293                                 v = ep93xx_ac97_read_reg(info, AC97SR(1));
 294                                 if (time_after(jiffies, timeout)) {
 295                                         dev_warn(info->dev, "TX timeout\n");
 296                                         break;
 297                                 }
 298                         } while (!(v & (AC97SR_TXFE | AC97SR_TXUE)));
 299
 300                         /* disable the TX FIFO */
 301                         ep93xx_ac97_write_reg(info, AC97TXCR(1), 0);
 302                 } else {
 303                         /* disable the RX FIFO */
 304                         ep93xx_ac97_write_reg(info, AC97RXCR(1), 0);
 305                 }
 306                 break;
 307
 308         default:
 309                 dev_warn(info->dev, "unknown command %d\n", cmd);
 310                 return -EINVAL;
 311         }
 312
 313         return 0;
 314 }
 315
 316 static int ep93xx_ac97_startup(struct snd_pcm_substream *substream,
 317                                struct snd_soc_dai *dai)
 318 {
 319         struct ep93xx_pcm_dma_params *dma_data;
 320
 321         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 322                 dma_data = &ep93xx_ac97_pcm_out;
 323         else
 324                 dma_data = &ep93xx_ac97_pcm_in;
 325
 326         snd_soc_dai_set_dma_data(dai, substream, dma_data);
 327         return 0;
 328 }
 329
 330 static const struct snd_soc_dai_ops ep93xx_ac97_dai_ops = {
 331         .startup        = ep93xx_ac97_startup,
 332         .trigger        = ep93xx_ac97_trigger,
 333 };
 334
 335 static struct snd_soc_dai_driver ep93xx_ac97_dai = {
 336         .name           = "ep93xx-ac97",
 337         .id             = 0,
 338         .ac97_control   = 1,
 339         .playback       = {
 340                 .stream_name    = "AC97 Playback",
 341                 .channels_min   = 2,
 342                 .channels_max   = 2,
 343                 .rates          = SNDRV_PCM_RATE_8000_48000,
 344                 .formats        = SNDRV_PCM_FMTBIT_S16_LE,
 345         },
 346         .capture        = {
 347                 .stream_name    = "AC97 Capture",
 348                 .channels_min   = 2,
 349                 .channels_max   = 2,
 350                 .rates          = SNDRV_PCM_RATE_8000_48000,
 351                 .formats        = SNDRV_PCM_FMTBIT_S16_LE,
 352         },
 353         .ops                    = &ep93xx_ac97_dai_ops,
 354 };
 355
 356 static int ep93xx_ac97_probe(struct platform_device *pdev)
 357 {
 358         struct ep93xx_ac97_info *info;
 359         struct resource *res;
 360         unsigned int irq;
 361         int ret;
 362
 363         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
 364         if (!info)
 365                 return -ENOMEM;
 366
 367         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 368         if (!res)
 369                 return -ENODEV;
 370
 371         info->regs = devm_ioremap_resource(&pdev->dev, res);
 372         if (IS_ERR(info->regs))
 373                 return PTR_ERR(info->regs);
 374
 375         irq = platform_get_irq(pdev, 0);
 376         if (!irq)
 377                 return -ENODEV;
 378
 379         ret = devm_request_irq(&pdev->dev, irq, ep93xx_ac97_interrupt,
 380                                IRQF_TRIGGER_HIGH, pdev->name, info);
 381         if (ret)
 382                 goto fail;
 383
 384         dev_set_drvdata(&pdev->dev, info);
 385
 386         mutex_init(&info->lock);
 387         init_completion(&info->done);
 388         info->dev = &pdev->dev;
 389
 390         ep93xx_ac97_info = info;
 391         platform_set_drvdata(pdev, info);
 392
 393         ret = snd_soc_register_dai(&pdev->dev, &ep93xx_ac97_dai);
 394         if (ret)
 395                 goto fail;
 396
 397         return 0;
 398
 399 fail:
 400         platform_set_drvdata(pdev, NULL);
 401         ep93xx_ac97_info = NULL;
 402         dev_set_drvdata(&pdev->dev, NULL);
 403         return ret;
 404 }
 405
 406 static int ep93xx_ac97_remove(struct platform_device *pdev)
 407 {
 408         struct ep93xx_ac97_info *info = platform_get_drvdata(pdev);
 409
 410         snd_soc_unregister_dai(&pdev->dev);
 411
 412         /* disable the AC97 controller */
 413         ep93xx_ac97_write_reg(info, AC97GCR, 0);
 414
 415         platform_set_drvdata(pdev, NULL);
 416         ep93xx_ac97_info = NULL;
 417         dev_set_drvdata(&pdev->dev, NULL);
 418
 419         return 0;
 420 }
 421
 422 static struct platform_driver ep93xx_ac97_driver = {
 423         .probe  = ep93xx_ac97_probe,
 424         .remove = ep93xx_ac97_remove,
 425         .driver = {
 426                 .name = "ep93xx-ac97",
 427                 .owner = THIS_MODULE,
 428         },
 429 };
 430
 431 module_platform_driver(ep93xx_ac97_driver);
 432
 433 MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver");
 434 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
 435 MODULE_LICENSE("GPL");
 436 MODULE_ALIAS("platform:ep93xx-ac97");