sound/soc/codecs/ak4642.c

   1 /*
   2  * ak4642.c  --  AK4642/AK4643 ALSA Soc Audio driver
   3  *
   4  * Copyright (C) 2009 Renesas Solutions Corp.
   5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   6  *
   7  * Based on wm8731.c by Richard Purdie
   8  * Based on ak4535.c by Richard Purdie
   9  * Based on wm8753.c by Liam Girdwood
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 /* ** CAUTION **
  17  *
  18  * This is very simple driver.
  19  * It can use headphone output / stereo input only
  20  *
  21  * AK4642 is tested.
  22  * AK4643 is tested.
  23  * AK4648 is tested.
  24  */
  25
  26 #include <linux/delay.h>
  27 #include <linux/i2c.h>
  28 #include <linux/slab.h>
  29 #include <linux/of_device.h>
  30 #include <linux/module.h>
  31 #include <linux/regmap.h>
  32 #include <sound/soc.h>
  33 #include <sound/initval.h>
  34 #include <sound/tlv.h>
  35
  36 #define PW_MGMT1        0x00
  37 #define PW_MGMT2        0x01
  38 #define SG_SL1          0x02
  39 #define SG_SL2          0x03
  40 #define MD_CTL1         0x04
  41 #define MD_CTL2         0x05
  42 #define TIMER           0x06
  43 #define ALC_CTL1        0x07
  44 #define ALC_CTL2        0x08
  45 #define L_IVC           0x09
  46 #define L_DVC           0x0a
  47 #define ALC_CTL3        0x0b
  48 #define R_IVC           0x0c
  49 #define R_DVC           0x0d
  50 #define MD_CTL3         0x0e
  51 #define MD_CTL4         0x0f
  52 #define PW_MGMT3        0x10
  53 #define DF_S            0x11
  54 #define FIL3_0          0x12
  55 #define FIL3_1          0x13
  56 #define FIL3_2          0x14
  57 #define FIL3_3          0x15
  58 #define EQ_0            0x16
  59 #define EQ_1            0x17
  60 #define EQ_2            0x18
  61 #define EQ_3            0x19
  62 #define EQ_4            0x1a
  63 #define EQ_5            0x1b
  64 #define FIL1_0          0x1c
  65 #define FIL1_1          0x1d
  66 #define FIL1_2          0x1e
  67 #define FIL1_3          0x1f    /* The maximum valid register for ak4642 */
  68 #define PW_MGMT4        0x20
  69 #define MD_CTL5         0x21
  70 #define LO_MS           0x22
  71 #define HP_MS           0x23
  72 #define SPK_MS          0x24    /* The maximum valid register for ak4643 */
  73 #define EQ_FBEQAB       0x25
  74 #define EQ_FBEQCD       0x26
  75 #define EQ_FBEQE        0x27    /* The maximum valid register for ak4648 */
  76
  77 /* PW_MGMT1*/
  78 #define PMVCM           (1 << 6) /* VCOM Power Management */
  79 #define PMMIN           (1 << 5) /* MIN Input Power Management */
  80 #define PMDAC           (1 << 2) /* DAC Power Management */
  81 #define PMADL           (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
  82
  83 /* PW_MGMT2 */
  84 #define HPMTN           (1 << 6)
  85 #define PMHPL           (1 << 5)
  86 #define PMHPR           (1 << 4)
  87 #define MS              (1 << 3) /* master/slave select */
  88 #define MCKO            (1 << 1)
  89 #define PMPLL           (1 << 0)
  90
  91 #define PMHP_MASK       (PMHPL | PMHPR)
  92 #define PMHP            PMHP_MASK
  93
  94 /* PW_MGMT3 */
  95 #define PMADR           (1 << 0) /* MIC L / ADC R Power Management */
  96
  97 /* SG_SL1 */
  98 #define MINS            (1 << 6) /* Switch from MIN to Speaker */
  99 #define DACL            (1 << 4) /* Switch from DAC to Stereo or Receiver */
 100 #define PMMP            (1 << 2) /* MPWR pin Power Management */
 101 #define MGAIN0          (1 << 0) /* MIC amp gain*/
 102
 103 /* SG_SL2 */
 104 #define LOPS            (1 << 6) /* Stero Line-out Power Save Mode */
 105
 106 /* TIMER */
 107 #define ZTM(param)      ((param & 0x3) << 4) /* ALC Zero Crossing TimeOut */
 108 #define WTM(param)      (((param & 0x4) << 4) | ((param & 0x3) << 2))
 109
 110 /* ALC_CTL1 */
 111 #define ALC             (1 << 5) /* ALC Enable */
 112 #define LMTH0           (1 << 0) /* ALC Limiter / Recovery Level */
 113
 114 /* MD_CTL1 */
 115 #define PLL3            (1 << 7)
 116 #define PLL2            (1 << 6)
 117 #define PLL1            (1 << 5)
 118 #define PLL0            (1 << 4)
 119 #define PLL_MASK        (PLL3 | PLL2 | PLL1 | PLL0)
 120
 121 #define BCKO_MASK       (1 << 3)
 122 #define BCKO_64         BCKO_MASK
 123
 124 #define DIF_MASK        (3 << 0)
 125 #define DSP             (0 << 0)
 126 #define RIGHT_J         (1 << 0)
 127 #define LEFT_J          (2 << 0)
 128 #define I2S             (3 << 0)
 129
 130 /* MD_CTL2 */
 131 #define FS0             (1 << 0)
 132 #define FS1             (1 << 1)
 133 #define FS2             (1 << 2)
 134 #define FS3             (1 << 5)
 135 #define FS_MASK         (FS0 | FS1 | FS2 | FS3)
 136
 137 /* MD_CTL3 */
 138 #define BST1            (1 << 3)
 139
 140 /* MD_CTL4 */
 141 #define DACH            (1 << 0)
 142
 143 struct ak4642_drvdata {
 144         const struct regmap_config *regmap_config;
 145         int extended_frequencies;
 146 };
 147
 148 struct ak4642_priv {
 149         const struct ak4642_drvdata *drvdata;
 150 };
 151
 152 /*
 153  * Playback Volume (table 39)
 154  *
 155  * max : 0x00 : +12.0 dB
 156  *       ( 0.5 dB step )
 157  * min : 0xFE : -115.0 dB
 158  * mute: 0xFF
 159  */
 160 static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
 161
 162 static const struct snd_kcontrol_new ak4642_snd_controls[] = {
 163
 164         SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
 165                          0, 0xFF, 1, out_tlv),
 166         SOC_SINGLE("ALC Capture Switch", ALC_CTL1, 5, 1, 0),
 167         SOC_SINGLE("ALC Capture ZC Switch", ALC_CTL1, 4, 1, 1),
 168 };
 169
 170 static const struct snd_kcontrol_new ak4642_headphone_control =
 171         SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);
 172
 173 static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
 174         SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
 175 };
 176
 177 /* event handlers */
 178 static int ak4642_lout_event(struct snd_soc_dapm_widget *w,
 179                              struct snd_kcontrol *kcontrol, int event)
 180 {
 181         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 182
 183         switch (event) {
 184         case SND_SOC_DAPM_PRE_PMD:
 185         case SND_SOC_DAPM_PRE_PMU:
 186                 /* Power save mode ON */
 187                 snd_soc_update_bits(codec, SG_SL2, LOPS, LOPS);
 188                 break;
 189         case SND_SOC_DAPM_POST_PMU:
 190         case SND_SOC_DAPM_POST_PMD:
 191                 /* Power save mode OFF */
 192                 mdelay(300);
 193                 snd_soc_update_bits(codec, SG_SL2, LOPS, 0);
 194                 break;
 195         }
 196
 197         return 0;
 198 }
 199
 200 static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
 201
 202         /* Outputs */
 203         SND_SOC_DAPM_OUTPUT("HPOUTL"),
 204         SND_SOC_DAPM_OUTPUT("HPOUTR"),
 205         SND_SOC_DAPM_OUTPUT("LINEOUT"),
 206
 207         SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
 208         SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
 209         SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
 210                             &ak4642_headphone_control),
 211
 212         SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),
 213
 214         SND_SOC_DAPM_MIXER_E("LINEOUT Mixer", PW_MGMT1, 3, 0,
 215                            &ak4642_lout_mixer_controls[0],
 216                            ARRAY_SIZE(ak4642_lout_mixer_controls),
 217                            ak4642_lout_event,
 218                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 219                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
 220
 221         /* DAC */
 222         SND_SOC_DAPM_DAC("DAC", NULL, PW_MGMT1, 2, 0),
 223 };
 224
 225 static const struct snd_soc_dapm_route ak4642_intercon[] = {
 226
 227         /* Outputs */
 228         {"HPOUTL", NULL, "HPL Out"},
 229         {"HPOUTR", NULL, "HPR Out"},
 230         {"LINEOUT", NULL, "LINEOUT Mixer"},
 231
 232         {"HPL Out", NULL, "Headphone Enable"},
 233         {"HPR Out", NULL, "Headphone Enable"},
 234
 235         {"Headphone Enable", "Switch", "DACH"},
 236
 237         {"DACH", NULL, "DAC"},
 238
 239         {"LINEOUT Mixer", "DACL", "DAC"},
 240
 241         { "DAC", NULL, "Playback" },
 242 };
 243
 244 /*
 245  * ak4642 register cache
 246  */
 247 static const struct reg_default ak4643_reg[] = {
 248         {  0, 0x00 }, {  1, 0x00 }, {  2, 0x01 }, {  3, 0x00 },
 249         {  4, 0x02 }, {  5, 0x00 }, {  6, 0x00 }, {  7, 0x00 },
 250         {  8, 0xe1 }, {  9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
 251         { 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0x08 },
 252         { 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
 253         { 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
 254         { 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
 255         { 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
 256         { 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
 257         { 36, 0x00 },
 258 };
 259
 260 /* The default settings for 0x0 ~ 0x1f registers are the same for ak4642
 261    and ak4643. So we reuse the ak4643 reg_default for ak4642.
 262    The valid registers for ak4642 are 0x0 ~ 0x1f which is a subset of ak4643,
 263    so define NUM_AK4642_REG_DEFAULTS for ak4642.
 264 */
 265 #define ak4642_reg ak4643_reg
 266 #define NUM_AK4642_REG_DEFAULTS (FIL1_3 + 1)
 267
 268 static const struct reg_default ak4648_reg[] = {
 269         {  0, 0x00 }, {  1, 0x00 }, {  2, 0x01 }, {  3, 0x00 },
 270         {  4, 0x02 }, {  5, 0x00 }, {  6, 0x00 }, {  7, 0x00 },
 271         {  8, 0xe1 }, {  9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
 272         { 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0xb8 },
 273         { 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
 274         { 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
 275         { 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
 276         { 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
 277         { 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
 278         { 36, 0x00 }, { 37, 0x88 }, { 38, 0x88 }, { 39, 0x08 },
 279 };
 280
 281 static int ak4642_dai_startup(struct snd_pcm_substream *substream,
 282                               struct snd_soc_dai *dai)
 283 {
 284         int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 285         struct snd_soc_codec *codec = dai->codec;
 286
 287         if (is_play) {
 288                 /*
 289                  * start headphone output
 290                  *
 291                  * PLL, Master Mode
 292                  * Audio I/F Format :MSB justified (ADC & DAC)
 293                  * Bass Boost Level : Middle
 294                  *
 295                  * This operation came from example code of
 296                  * "ASAHI KASEI AK4642" (japanese) manual p97.
 297                  */
 298                 snd_soc_write(codec, L_IVC, 0x91); /* volume */
 299                 snd_soc_write(codec, R_IVC, 0x91); /* volume */
 300         } else {
 301                 /*
 302                  * start stereo input
 303                  *
 304                  * PLL Master Mode
 305                  * Audio I/F Format:MSB justified (ADC & DAC)
 306                  * Pre MIC AMP:+20dB
 307                  * MIC Power On
 308                  * ALC setting:Refer to Table 35
 309                  * ALC bit=“1”
 310                  *
 311                  * This operation came from example code of
 312                  * "ASAHI KASEI AK4642" (japanese) manual p94.
 313                  */
 314                 snd_soc_update_bits(codec, SG_SL1, PMMP | MGAIN0, PMMP | MGAIN0);
 315                 snd_soc_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
 316                 snd_soc_write(codec, ALC_CTL1, ALC | LMTH0);
 317                 snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
 318                 snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
 319         }
 320
 321         return 0;
 322 }
 323
 324 static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
 325                                struct snd_soc_dai *dai)
 326 {
 327         int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
 328         struct snd_soc_codec *codec = dai->codec;
 329
 330         if (is_play) {
 331         } else {
 332                 /* stop stereo input */
 333                 snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
 334                 snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
 335                 snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
 336         }
 337 }
 338
 339 static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
 340         int clk_id, unsigned int freq, int dir)
 341 {
 342         struct snd_soc_codec *codec = codec_dai->codec;
 343         struct ak4642_priv *priv = snd_soc_codec_get_drvdata(codec);
 344         u8 pll;
 345         int extended_freq = 0;
 346
 347         switch (freq) {
 348         case 11289600:
 349                 pll = PLL2;
 350                 break;
 351         case 12288000:
 352                 pll = PLL2 | PLL0;
 353                 break;
 354         case 12000000:
 355                 pll = PLL2 | PLL1;
 356                 break;
 357         case 24000000:
 358                 pll = PLL2 | PLL1 | PLL0;
 359                 break;
 360         case 13500000:
 361                 pll = PLL3 | PLL2;
 362                 break;
 363         case 27000000:
 364                 pll = PLL3 | PLL2 | PLL0;
 365                 break;
 366         case 19200000:
 367                 pll = PLL3;
 368                 extended_freq = 1;
 369                 break;
 370         case 13000000:
 371                 pll = PLL3 | PLL2 | PLL1;
 372                 extended_freq = 1;
 373                 break;
 374         case 26000000:
 375                 pll = PLL3 | PLL2 | PLL1 | PLL0;
 376                 extended_freq = 1;
 377                 break;
 378         default:
 379                 return -EINVAL;
 380         }
 381
 382         if (extended_freq && !priv->drvdata->extended_frequencies)
 383                 return -EINVAL;
 384
 385         snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
 386
 387         return 0;
 388 }
 389
 390 static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 391 {
 392         struct snd_soc_codec *codec = dai->codec;
 393         u8 data;
 394         u8 bcko;
 395
 396         data = MCKO | PMPLL; /* use MCKO */
 397         bcko = 0;
 398
 399         /* set master/slave audio interface */
 400         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 401         case SND_SOC_DAIFMT_CBM_CFM:
 402                 data |= MS;
 403                 bcko = BCKO_64;
 404                 break;
 405         case SND_SOC_DAIFMT_CBS_CFS:
 406                 break;
 407         default:
 408                 return -EINVAL;
 409         }
 410         snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data);
 411         snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
 412
 413         /* format type */
 414         data = 0;
 415         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 416         case SND_SOC_DAIFMT_LEFT_J:
 417                 data = LEFT_J;
 418                 break;
 419         case SND_SOC_DAIFMT_I2S:
 420                 data = I2S;
 421                 break;
 422         /* FIXME
 423          * Please add RIGHT_J / DSP support here
 424          */
 425         default:
 426                 return -EINVAL;
 427         }
 428         snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);
 429
 430         return 0;
 431 }
 432
 433 static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
 434                                 struct snd_pcm_hw_params *params,
 435                                 struct snd_soc_dai *dai)
 436 {
 437         struct snd_soc_codec *codec = dai->codec;
 438         u8 rate;
 439
 440         switch (params_rate(params)) {
 441         case 7350:
 442                 rate = FS2;
 443                 break;
 444         case 8000:
 445                 rate = 0;
 446                 break;
 447         case 11025:
 448                 rate = FS2 | FS0;
 449                 break;
 450         case 12000:
 451                 rate = FS0;
 452                 break;
 453         case 14700:
 454                 rate = FS2 | FS1;
 455                 break;
 456         case 16000:
 457                 rate = FS1;
 458                 break;
 459         case 22050:
 460                 rate = FS2 | FS1 | FS0;
 461                 break;
 462         case 24000:
 463                 rate = FS1 | FS0;
 464                 break;
 465         case 29400:
 466                 rate = FS3 | FS2 | FS1;
 467                 break;
 468         case 32000:
 469                 rate = FS3 | FS1;
 470                 break;
 471         case 44100:
 472                 rate = FS3 | FS2 | FS1 | FS0;
 473                 break;
 474         case 48000:
 475                 rate = FS3 | FS1 | FS0;
 476                 break;
 477         default:
 478                 return -EINVAL;
 479         }
 480         snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);
 481
 482         return 0;
 483 }
 484
 485 static int ak4642_set_bias_level(struct snd_soc_codec *codec,
 486                                  enum snd_soc_bias_level level)
 487 {
 488         switch (level) {
 489         case SND_SOC_BIAS_OFF:
 490                 snd_soc_write(codec, PW_MGMT1, 0x00);
 491                 break;
 492         default:
 493                 snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM);
 494                 break;
 495         }
 496
 497         return 0;
 498 }
 499
 500 static const struct snd_soc_dai_ops ak4642_dai_ops = {
 501         .startup        = ak4642_dai_startup,
 502         .shutdown       = ak4642_dai_shutdown,
 503         .set_sysclk     = ak4642_dai_set_sysclk,
 504         .set_fmt        = ak4642_dai_set_fmt,
 505         .hw_params      = ak4642_dai_hw_params,
 506 };
 507
 508 static struct snd_soc_dai_driver ak4642_dai = {
 509         .name = "ak4642-hifi",
 510         .playback = {
 511                 .stream_name = "Playback",
 512                 .channels_min = 2,
 513                 .channels_max = 2,
 514                 .rates = SNDRV_PCM_RATE_8000_48000,
 515                 .formats = SNDRV_PCM_FMTBIT_S16_LE },
 516         .capture = {
 517                 .stream_name = "Capture",
 518                 .channels_min = 2,
 519                 .channels_max = 2,
 520                 .rates = SNDRV_PCM_RATE_8000_48000,
 521                 .formats = SNDRV_PCM_FMTBIT_S16_LE },
 522         .ops = &ak4642_dai_ops,
 523         .symmetric_rates = 1,
 524 };
 525
 526 static int ak4642_resume(struct snd_soc_codec *codec)
 527 {
 528         struct regmap *regmap = dev_get_regmap(codec->dev, NULL);
 529
 530         regcache_mark_dirty(regmap);
 531         regcache_sync(regmap);
 532         return 0;
 533 }
 534
 535 static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
 536         .resume                 = ak4642_resume,
 537         .set_bias_level         = ak4642_set_bias_level,
 538         .controls               = ak4642_snd_controls,
 539         .num_controls           = ARRAY_SIZE(ak4642_snd_controls),
 540         .dapm_widgets           = ak4642_dapm_widgets,
 541         .num_dapm_widgets       = ARRAY_SIZE(ak4642_dapm_widgets),
 542         .dapm_routes            = ak4642_intercon,
 543         .num_dapm_routes        = ARRAY_SIZE(ak4642_intercon),
 544 };
 545
 546 static const struct regmap_config ak4642_regmap = {
 547         .reg_bits               = 8,
 548         .val_bits               = 8,
 549         .max_register           = FIL1_3,
 550         .reg_defaults           = ak4642_reg,
 551         .num_reg_defaults       = NUM_AK4642_REG_DEFAULTS,
 552 };
 553
 554 static const struct regmap_config ak4643_regmap = {
 555         .reg_bits               = 8,
 556         .val_bits               = 8,
 557         .max_register           = SPK_MS,
 558         .reg_defaults           = ak4643_reg,
 559         .num_reg_defaults       = ARRAY_SIZE(ak4643_reg),
 560 };
 561
 562 static const struct regmap_config ak4648_regmap = {
 563         .reg_bits               = 8,
 564         .val_bits               = 8,
 565         .max_register           = EQ_FBEQE,
 566         .reg_defaults           = ak4648_reg,
 567         .num_reg_defaults       = ARRAY_SIZE(ak4648_reg),
 568 };
 569
 570 static const struct ak4642_drvdata ak4642_drvdata = {
 571         .regmap_config = &ak4642_regmap,
 572 };
 573
 574 static const struct ak4642_drvdata ak4643_drvdata = {
 575         .regmap_config = &ak4643_regmap,
 576 };
 577
 578 static const struct ak4642_drvdata ak4648_drvdata = {
 579         .regmap_config = &ak4648_regmap,
 580         .extended_frequencies = 1,
 581 };
 582
 583 static const struct of_device_id ak4642_of_match[];
 584 static int ak4642_i2c_probe(struct i2c_client *i2c,
 585                             const struct i2c_device_id *id)
 586 {
 587         struct device_node *np = i2c->dev.of_node;
 588         const struct ak4642_drvdata *drvdata = NULL;
 589         struct regmap *regmap;
 590         struct ak4642_priv *priv;
 591
 592         if (np) {
 593                 const struct of_device_id *of_id;
 594
 595                 of_id = of_match_device(ak4642_of_match, &i2c->dev);
 596                 if (of_id)
 597                         drvdata = of_id->data;
 598         } else {
 599                 drvdata = (const struct ak4642_drvdata *)id->driver_data;
 600         }
 601
 602         if (!drvdata) {
 603                 dev_err(&i2c->dev, "Unknown device type\n");
 604                 return -EINVAL;
 605         }
 606
 607         priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
 608         if (!priv)
 609                 return -ENOMEM;
 610
 611         priv->drvdata = drvdata;
 612
 613         i2c_set_clientdata(i2c, priv);
 614
 615         regmap = devm_regmap_init_i2c(i2c, drvdata->regmap_config);
 616         if (IS_ERR(regmap))
 617                 return PTR_ERR(regmap);
 618
 619         return snd_soc_register_codec(&i2c->dev,
 620                                       &soc_codec_dev_ak4642, &ak4642_dai, 1);
 621 }
 622
 623 static int ak4642_i2c_remove(struct i2c_client *client)
 624 {
 625         snd_soc_unregister_codec(&client->dev);
 626         return 0;
 627 }
 628
 629 static const struct of_device_id ak4642_of_match[] = {
 630         { .compatible = "asahi-kasei,ak4642",   .data = &ak4642_drvdata},
 631         { .compatible = "asahi-kasei,ak4643",   .data = &ak4643_drvdata},
 632         { .compatible = "asahi-kasei,ak4648",   .data = &ak4648_drvdata},
 633         {},
 634 };
 635 MODULE_DEVICE_TABLE(of, ak4642_of_match);
 636
 637 static const struct i2c_device_id ak4642_i2c_id[] = {
 638         { "ak4642", (kernel_ulong_t)&ak4642_drvdata },
 639         { "ak4643", (kernel_ulong_t)&ak4643_drvdata },
 640         { "ak4648", (kernel_ulong_t)&ak4648_drvdata },
 641         { }
 642 };
 643 MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
 644
 645 static struct i2c_driver ak4642_i2c_driver = {
 646         .driver = {
 647                 .name = "ak4642-codec",
 648                 .of_match_table = ak4642_of_match,
 649         },
 650         .probe          = ak4642_i2c_probe,
 651         .remove         = ak4642_i2c_remove,
 652         .id_table       = ak4642_i2c_id,
 653 };
 654
 655 module_i2c_driver(ak4642_i2c_driver);
 656
 657 MODULE_DESCRIPTION("Soc AK4642 driver");
 658 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
 659 MODULE_LICENSE("GPL");