2 * arizona.c - Wolfson Arizona class device shared support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/gcd.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/tlv.h>
21 #include <linux/mfd/arizona/core.h>
22 #include <linux/mfd/arizona/registers.h>
26 #define ARIZONA_AIF_BCLK_CTRL 0x00
27 #define ARIZONA_AIF_TX_PIN_CTRL 0x01
28 #define ARIZONA_AIF_RX_PIN_CTRL 0x02
29 #define ARIZONA_AIF_RATE_CTRL 0x03
30 #define ARIZONA_AIF_FORMAT 0x04
31 #define ARIZONA_AIF_TX_BCLK_RATE 0x05
32 #define ARIZONA_AIF_RX_BCLK_RATE 0x06
33 #define ARIZONA_AIF_FRAME_CTRL_1 0x07
34 #define ARIZONA_AIF_FRAME_CTRL_2 0x08
35 #define ARIZONA_AIF_FRAME_CTRL_3 0x09
36 #define ARIZONA_AIF_FRAME_CTRL_4 0x0A
37 #define ARIZONA_AIF_FRAME_CTRL_5 0x0B
38 #define ARIZONA_AIF_FRAME_CTRL_6 0x0C
39 #define ARIZONA_AIF_FRAME_CTRL_7 0x0D
40 #define ARIZONA_AIF_FRAME_CTRL_8 0x0E
41 #define ARIZONA_AIF_FRAME_CTRL_9 0x0F
42 #define ARIZONA_AIF_FRAME_CTRL_10 0x10
43 #define ARIZONA_AIF_FRAME_CTRL_11 0x11
44 #define ARIZONA_AIF_FRAME_CTRL_12 0x12
45 #define ARIZONA_AIF_FRAME_CTRL_13 0x13
46 #define ARIZONA_AIF_FRAME_CTRL_14 0x14
47 #define ARIZONA_AIF_FRAME_CTRL_15 0x15
48 #define ARIZONA_AIF_FRAME_CTRL_16 0x16
49 #define ARIZONA_AIF_FRAME_CTRL_17 0x17
50 #define ARIZONA_AIF_FRAME_CTRL_18 0x18
51 #define ARIZONA_AIF_TX_ENABLES 0x19
52 #define ARIZONA_AIF_RX_ENABLES 0x1A
53 #define ARIZONA_AIF_FORCE_WRITE 0x1B
55 #define ARIZONA_FLL_VCO_CORNER 141900000
56 #define ARIZONA_FLL_MAX_FREF 13500000
57 #define ARIZONA_FLL_MIN_FVCO 90000000
58 #define ARIZONA_FLL_MAX_FRATIO 16
59 #define ARIZONA_FLL_MAX_REFDIV 8
60 #define ARIZONA_FLL_MIN_OUTDIV 2
61 #define ARIZONA_FLL_MAX_OUTDIV 7
63 #define ARIZONA_FMT_DSP_MODE_A 0
64 #define ARIZONA_FMT_DSP_MODE_B 1
65 #define ARIZONA_FMT_I2S_MODE 2
66 #define ARIZONA_FMT_LEFT_JUSTIFIED_MODE 3
68 #define arizona_fll_err(_fll, fmt, ...) \
69 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
70 #define arizona_fll_warn(_fll, fmt, ...) \
71 dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
72 #define arizona_fll_dbg(_fll, fmt, ...) \
73 dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
75 #define arizona_aif_err(_dai, fmt, ...) \
76 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
77 #define arizona_aif_warn(_dai, fmt, ...) \
78 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
79 #define arizona_aif_dbg(_dai, fmt, ...) \
80 dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
82 static int arizona_spk_ev(struct snd_soc_dapm_widget
*w
,
83 struct snd_kcontrol
*kcontrol
,
86 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
87 struct arizona
*arizona
= dev_get_drvdata(codec
->dev
->parent
);
88 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
89 bool manual_ena
= false;
92 switch (arizona
->type
) {
94 switch (arizona
->rev
) {
106 case SND_SOC_DAPM_PRE_PMU
:
107 if (!priv
->spk_ena
&& manual_ena
) {
108 regmap_write_async(arizona
->regmap
, 0x4f5, 0x25a);
109 priv
->spk_ena_pending
= true;
112 case SND_SOC_DAPM_POST_PMU
:
113 val
= snd_soc_read(codec
, ARIZONA_INTERRUPT_RAW_STATUS_3
);
114 if (val
& ARIZONA_SPK_OVERHEAT_STS
) {
115 dev_crit(arizona
->dev
,
116 "Speaker not enabled due to temperature\n");
120 regmap_update_bits_async(arizona
->regmap
,
121 ARIZONA_OUTPUT_ENABLES_1
,
122 1 << w
->shift
, 1 << w
->shift
);
124 if (priv
->spk_ena_pending
) {
126 regmap_write_async(arizona
->regmap
, 0x4f5, 0xda);
127 priv
->spk_ena_pending
= false;
131 case SND_SOC_DAPM_PRE_PMD
:
135 regmap_write_async(arizona
->regmap
,
139 regmap_update_bits_async(arizona
->regmap
,
140 ARIZONA_OUTPUT_ENABLES_1
,
143 case SND_SOC_DAPM_POST_PMD
:
146 regmap_write_async(arizona
->regmap
,
155 static irqreturn_t
arizona_thermal_warn(int irq
, void *data
)
157 struct arizona
*arizona
= data
;
161 ret
= regmap_read(arizona
->regmap
, ARIZONA_INTERRUPT_RAW_STATUS_3
,
164 dev_err(arizona
->dev
, "Failed to read thermal status: %d\n",
166 } else if (val
& ARIZONA_SPK_OVERHEAT_WARN_STS
) {
167 dev_crit(arizona
->dev
, "Thermal warning\n");
173 static irqreturn_t
arizona_thermal_shutdown(int irq
, void *data
)
175 struct arizona
*arizona
= data
;
179 ret
= regmap_read(arizona
->regmap
, ARIZONA_INTERRUPT_RAW_STATUS_3
,
182 dev_err(arizona
->dev
, "Failed to read thermal status: %d\n",
184 } else if (val
& ARIZONA_SPK_OVERHEAT_STS
) {
185 dev_crit(arizona
->dev
, "Thermal shutdown\n");
186 ret
= regmap_update_bits(arizona
->regmap
,
187 ARIZONA_OUTPUT_ENABLES_1
,
189 ARIZONA_OUT4R_ENA
, 0);
191 dev_crit(arizona
->dev
,
192 "Failed to disable speaker outputs: %d\n",
199 static const struct snd_soc_dapm_widget arizona_spkl
=
200 SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM
,
201 ARIZONA_OUT4L_ENA_SHIFT
, 0, NULL
, 0, arizona_spk_ev
,
202 SND_SOC_DAPM_PRE_PMD
| SND_SOC_DAPM_POST_PMU
);
204 static const struct snd_soc_dapm_widget arizona_spkr
=
205 SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM
,
206 ARIZONA_OUT4R_ENA_SHIFT
, 0, NULL
, 0, arizona_spk_ev
,
207 SND_SOC_DAPM_PRE_PMD
| SND_SOC_DAPM_POST_PMU
);
209 int arizona_init_spk(struct snd_soc_codec
*codec
)
211 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
212 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
213 struct arizona
*arizona
= priv
->arizona
;
216 ret
= snd_soc_dapm_new_controls(dapm
, &arizona_spkl
, 1);
220 switch (arizona
->type
) {
224 ret
= snd_soc_dapm_new_controls(dapm
, &arizona_spkr
, 1);
230 ret
= arizona_request_irq(arizona
, ARIZONA_IRQ_SPK_OVERHEAT_WARN
,
231 "Thermal warning", arizona_thermal_warn
,
234 dev_err(arizona
->dev
,
235 "Failed to get thermal warning IRQ: %d\n",
238 ret
= arizona_request_irq(arizona
, ARIZONA_IRQ_SPK_OVERHEAT
,
239 "Thermal shutdown", arizona_thermal_shutdown
,
242 dev_err(arizona
->dev
,
243 "Failed to get thermal shutdown IRQ: %d\n",
248 EXPORT_SYMBOL_GPL(arizona_init_spk
);
250 static const struct snd_soc_dapm_route arizona_mono_routes
[] = {
251 { "OUT1R", NULL
, "OUT1L" },
252 { "OUT2R", NULL
, "OUT2L" },
253 { "OUT3R", NULL
, "OUT3L" },
254 { "OUT4R", NULL
, "OUT4L" },
255 { "OUT5R", NULL
, "OUT5L" },
256 { "OUT6R", NULL
, "OUT6L" },
259 int arizona_init_mono(struct snd_soc_codec
*codec
)
261 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
262 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
263 struct arizona
*arizona
= priv
->arizona
;
266 for (i
= 0; i
< ARIZONA_MAX_OUTPUT
; ++i
) {
267 if (arizona
->pdata
.out_mono
[i
])
268 snd_soc_dapm_add_routes(dapm
,
269 &arizona_mono_routes
[i
], 1);
274 EXPORT_SYMBOL_GPL(arizona_init_mono
);
276 int arizona_init_gpio(struct snd_soc_codec
*codec
)
278 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
279 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
280 struct arizona
*arizona
= priv
->arizona
;
283 switch (arizona
->type
) {
286 snd_soc_dapm_disable_pin(dapm
, "DRC2 Signal Activity");
292 snd_soc_dapm_disable_pin(dapm
, "DRC1 Signal Activity");
294 for (i
= 0; i
< ARRAY_SIZE(arizona
->pdata
.gpio_defaults
); i
++) {
295 switch (arizona
->pdata
.gpio_defaults
[i
] & ARIZONA_GPN_FN_MASK
) {
296 case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT
:
297 snd_soc_dapm_enable_pin(dapm
, "DRC1 Signal Activity");
299 case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT
:
300 snd_soc_dapm_enable_pin(dapm
, "DRC2 Signal Activity");
309 EXPORT_SYMBOL_GPL(arizona_init_gpio
);
311 const char *arizona_mixer_texts
[ARIZONA_NUM_MIXER_INPUTS
] = {
416 EXPORT_SYMBOL_GPL(arizona_mixer_texts
);
418 int arizona_mixer_values
[ARIZONA_NUM_MIXER_INPUTS
] = {
424 0x0c, /* Noise mixer */
425 0x0d, /* Comfort noise */
498 0xa0, /* ISRC1INT1 */
502 0xa4, /* ISRC1DEC1 */
506 0xa8, /* ISRC2DEC1 */
510 0xac, /* ISRC2INT1 */
514 0xb0, /* ISRC3DEC1 */
518 0xb4, /* ISRC3INT1 */
523 EXPORT_SYMBOL_GPL(arizona_mixer_values
);
525 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv
, -3200, 100, 0);
526 EXPORT_SYMBOL_GPL(arizona_mixer_tlv
);
528 const char *arizona_rate_text
[ARIZONA_RATE_ENUM_SIZE
] = {
529 "SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate",
531 EXPORT_SYMBOL_GPL(arizona_rate_text
);
533 const int arizona_rate_val
[ARIZONA_RATE_ENUM_SIZE
] = {
536 EXPORT_SYMBOL_GPL(arizona_rate_val
);
539 const struct soc_enum arizona_isrc_fsh
[] = {
540 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_1
,
541 ARIZONA_ISRC1_FSH_SHIFT
, 0xf,
542 ARIZONA_RATE_ENUM_SIZE
,
543 arizona_rate_text
, arizona_rate_val
),
544 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_1
,
545 ARIZONA_ISRC2_FSH_SHIFT
, 0xf,
546 ARIZONA_RATE_ENUM_SIZE
,
547 arizona_rate_text
, arizona_rate_val
),
548 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_1
,
549 ARIZONA_ISRC3_FSH_SHIFT
, 0xf,
550 ARIZONA_RATE_ENUM_SIZE
,
551 arizona_rate_text
, arizona_rate_val
),
553 EXPORT_SYMBOL_GPL(arizona_isrc_fsh
);
555 const struct soc_enum arizona_isrc_fsl
[] = {
556 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2
,
557 ARIZONA_ISRC1_FSL_SHIFT
, 0xf,
558 ARIZONA_RATE_ENUM_SIZE
,
559 arizona_rate_text
, arizona_rate_val
),
560 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2
,
561 ARIZONA_ISRC2_FSL_SHIFT
, 0xf,
562 ARIZONA_RATE_ENUM_SIZE
,
563 arizona_rate_text
, arizona_rate_val
),
564 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2
,
565 ARIZONA_ISRC3_FSL_SHIFT
, 0xf,
566 ARIZONA_RATE_ENUM_SIZE
,
567 arizona_rate_text
, arizona_rate_val
),
569 EXPORT_SYMBOL_GPL(arizona_isrc_fsl
);
571 const struct soc_enum arizona_asrc_rate1
=
572 SOC_VALUE_ENUM_SINGLE(ARIZONA_ASRC_RATE1
,
573 ARIZONA_ASRC_RATE1_SHIFT
, 0xf,
574 ARIZONA_RATE_ENUM_SIZE
- 1,
575 arizona_rate_text
, arizona_rate_val
);
576 EXPORT_SYMBOL_GPL(arizona_asrc_rate1
);
578 static const char *arizona_vol_ramp_text
[] = {
579 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
580 "15ms/6dB", "30ms/6dB",
583 SOC_ENUM_SINGLE_DECL(arizona_in_vd_ramp
,
584 ARIZONA_INPUT_VOLUME_RAMP
,
585 ARIZONA_IN_VD_RAMP_SHIFT
,
586 arizona_vol_ramp_text
);
587 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp
);
589 SOC_ENUM_SINGLE_DECL(arizona_in_vi_ramp
,
590 ARIZONA_INPUT_VOLUME_RAMP
,
591 ARIZONA_IN_VI_RAMP_SHIFT
,
592 arizona_vol_ramp_text
);
593 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp
);
595 SOC_ENUM_SINGLE_DECL(arizona_out_vd_ramp
,
596 ARIZONA_OUTPUT_VOLUME_RAMP
,
597 ARIZONA_OUT_VD_RAMP_SHIFT
,
598 arizona_vol_ramp_text
);
599 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp
);
601 SOC_ENUM_SINGLE_DECL(arizona_out_vi_ramp
,
602 ARIZONA_OUTPUT_VOLUME_RAMP
,
603 ARIZONA_OUT_VI_RAMP_SHIFT
,
604 arizona_vol_ramp_text
);
605 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp
);
607 static const char *arizona_lhpf_mode_text
[] = {
608 "Low-pass", "High-pass"
611 SOC_ENUM_SINGLE_DECL(arizona_lhpf1_mode
,
613 ARIZONA_LHPF1_MODE_SHIFT
,
614 arizona_lhpf_mode_text
);
615 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode
);
617 SOC_ENUM_SINGLE_DECL(arizona_lhpf2_mode
,
619 ARIZONA_LHPF2_MODE_SHIFT
,
620 arizona_lhpf_mode_text
);
621 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode
);
623 SOC_ENUM_SINGLE_DECL(arizona_lhpf3_mode
,
625 ARIZONA_LHPF3_MODE_SHIFT
,
626 arizona_lhpf_mode_text
);
627 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode
);
629 SOC_ENUM_SINGLE_DECL(arizona_lhpf4_mode
,
631 ARIZONA_LHPF4_MODE_SHIFT
,
632 arizona_lhpf_mode_text
);
633 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode
);
635 static const char *arizona_ng_hold_text
[] = {
636 "30ms", "120ms", "250ms", "500ms",
639 SOC_ENUM_SINGLE_DECL(arizona_ng_hold
,
640 ARIZONA_NOISE_GATE_CONTROL
,
641 ARIZONA_NGATE_HOLD_SHIFT
,
642 arizona_ng_hold_text
);
643 EXPORT_SYMBOL_GPL(arizona_ng_hold
);
645 static const char * const arizona_in_hpf_cut_text
[] = {
646 "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz"
649 SOC_ENUM_SINGLE_DECL(arizona_in_hpf_cut_enum
,
651 ARIZONA_IN_HPF_CUT_SHIFT
,
652 arizona_in_hpf_cut_text
);
653 EXPORT_SYMBOL_GPL(arizona_in_hpf_cut_enum
);
655 static const char * const arizona_in_dmic_osr_text
[] = {
656 "1.536MHz", "3.072MHz", "6.144MHz", "768kHz",
659 const struct soc_enum arizona_in_dmic_osr
[] = {
660 SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL
, ARIZONA_IN1_OSR_SHIFT
,
661 ARRAY_SIZE(arizona_in_dmic_osr_text
),
662 arizona_in_dmic_osr_text
),
663 SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL
, ARIZONA_IN2_OSR_SHIFT
,
664 ARRAY_SIZE(arizona_in_dmic_osr_text
),
665 arizona_in_dmic_osr_text
),
666 SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL
, ARIZONA_IN3_OSR_SHIFT
,
667 ARRAY_SIZE(arizona_in_dmic_osr_text
),
668 arizona_in_dmic_osr_text
),
669 SOC_ENUM_SINGLE(ARIZONA_IN4L_CONTROL
, ARIZONA_IN4_OSR_SHIFT
,
670 ARRAY_SIZE(arizona_in_dmic_osr_text
),
671 arizona_in_dmic_osr_text
),
673 EXPORT_SYMBOL_GPL(arizona_in_dmic_osr
);
675 static void arizona_in_set_vu(struct snd_soc_codec
*codec
, int ena
)
677 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
686 for (i
= 0; i
< priv
->num_inputs
; i
++)
687 snd_soc_update_bits(codec
,
688 ARIZONA_ADC_DIGITAL_VOLUME_1L
+ (i
* 4),
692 int arizona_in_ev(struct snd_soc_dapm_widget
*w
, struct snd_kcontrol
*kcontrol
,
695 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
696 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
700 reg
= ARIZONA_ADC_DIGITAL_VOLUME_1L
+ ((w
->shift
/ 2) * 8);
702 reg
= ARIZONA_ADC_DIGITAL_VOLUME_1R
+ ((w
->shift
/ 2) * 8);
705 case SND_SOC_DAPM_PRE_PMU
:
708 case SND_SOC_DAPM_POST_PMU
:
709 snd_soc_update_bits(codec
, reg
, ARIZONA_IN1L_MUTE
, 0);
711 /* If this is the last input pending then allow VU */
713 if (priv
->in_pending
== 0) {
715 arizona_in_set_vu(codec
, 1);
718 case SND_SOC_DAPM_PRE_PMD
:
719 snd_soc_update_bits(codec
, reg
,
720 ARIZONA_IN1L_MUTE
| ARIZONA_IN_VU
,
721 ARIZONA_IN1L_MUTE
| ARIZONA_IN_VU
);
723 case SND_SOC_DAPM_POST_PMD
:
724 /* Disable volume updates if no inputs are enabled */
725 reg
= snd_soc_read(codec
, ARIZONA_INPUT_ENABLES
);
727 arizona_in_set_vu(codec
, 0);
732 EXPORT_SYMBOL_GPL(arizona_in_ev
);
734 int arizona_out_ev(struct snd_soc_dapm_widget
*w
,
735 struct snd_kcontrol
*kcontrol
,
738 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
739 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
742 case SND_SOC_DAPM_PRE_PMU
:
744 case ARIZONA_OUT1L_ENA_SHIFT
:
745 case ARIZONA_OUT1R_ENA_SHIFT
:
746 case ARIZONA_OUT2L_ENA_SHIFT
:
747 case ARIZONA_OUT2R_ENA_SHIFT
:
748 case ARIZONA_OUT3L_ENA_SHIFT
:
749 case ARIZONA_OUT3R_ENA_SHIFT
:
750 priv
->out_up_pending
++;
751 priv
->out_up_delay
+= 17;
757 case SND_SOC_DAPM_POST_PMU
:
759 case ARIZONA_OUT1L_ENA_SHIFT
:
760 case ARIZONA_OUT1R_ENA_SHIFT
:
761 case ARIZONA_OUT2L_ENA_SHIFT
:
762 case ARIZONA_OUT2R_ENA_SHIFT
:
763 case ARIZONA_OUT3L_ENA_SHIFT
:
764 case ARIZONA_OUT3R_ENA_SHIFT
:
765 priv
->out_up_pending
--;
766 if (!priv
->out_up_pending
) {
767 msleep(priv
->out_up_delay
);
768 priv
->out_up_delay
= 0;
776 case SND_SOC_DAPM_PRE_PMD
:
778 case ARIZONA_OUT1L_ENA_SHIFT
:
779 case ARIZONA_OUT1R_ENA_SHIFT
:
780 case ARIZONA_OUT2L_ENA_SHIFT
:
781 case ARIZONA_OUT2R_ENA_SHIFT
:
782 case ARIZONA_OUT3L_ENA_SHIFT
:
783 case ARIZONA_OUT3R_ENA_SHIFT
:
784 priv
->out_down_pending
++;
785 priv
->out_down_delay
++;
791 case SND_SOC_DAPM_POST_PMD
:
793 case ARIZONA_OUT1L_ENA_SHIFT
:
794 case ARIZONA_OUT1R_ENA_SHIFT
:
795 case ARIZONA_OUT2L_ENA_SHIFT
:
796 case ARIZONA_OUT2R_ENA_SHIFT
:
797 case ARIZONA_OUT3L_ENA_SHIFT
:
798 case ARIZONA_OUT3R_ENA_SHIFT
:
799 priv
->out_down_pending
--;
800 if (!priv
->out_down_pending
) {
801 msleep(priv
->out_down_delay
);
802 priv
->out_down_delay
= 0;
813 EXPORT_SYMBOL_GPL(arizona_out_ev
);
815 int arizona_hp_ev(struct snd_soc_dapm_widget
*w
,
816 struct snd_kcontrol
*kcontrol
,
819 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
820 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
821 struct arizona
*arizona
= priv
->arizona
;
822 unsigned int mask
= 1 << w
->shift
;
826 case SND_SOC_DAPM_POST_PMU
:
829 case SND_SOC_DAPM_PRE_PMD
:
832 case SND_SOC_DAPM_PRE_PMU
:
833 case SND_SOC_DAPM_POST_PMD
:
834 return arizona_out_ev(w
, kcontrol
, event
);
839 /* Store the desired state for the HP outputs */
840 priv
->arizona
->hp_ena
&= ~mask
;
841 priv
->arizona
->hp_ena
|= val
;
843 /* Force off if HPDET clamp is active */
844 if (priv
->arizona
->hpdet_clamp
)
847 regmap_update_bits_async(arizona
->regmap
, ARIZONA_OUTPUT_ENABLES_1
,
850 return arizona_out_ev(w
, kcontrol
, event
);
852 EXPORT_SYMBOL_GPL(arizona_hp_ev
);
854 static unsigned int arizona_sysclk_48k_rates
[] = {
864 static unsigned int arizona_sysclk_44k1_rates
[] = {
874 static int arizona_set_opclk(struct snd_soc_codec
*codec
, unsigned int clk
,
877 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
880 int ref
, div
, refclk
;
883 case ARIZONA_CLK_OPCLK
:
884 reg
= ARIZONA_OUTPUT_SYSTEM_CLOCK
;
885 refclk
= priv
->sysclk
;
887 case ARIZONA_CLK_ASYNC_OPCLK
:
888 reg
= ARIZONA_OUTPUT_ASYNC_CLOCK
;
889 refclk
= priv
->asyncclk
;
896 rates
= arizona_sysclk_44k1_rates
;
898 rates
= arizona_sysclk_48k_rates
;
900 for (ref
= 0; ref
< ARRAY_SIZE(arizona_sysclk_48k_rates
) &&
901 rates
[ref
] <= refclk
; ref
++) {
903 while (rates
[ref
] / div
>= freq
&& div
< 32) {
904 if (rates
[ref
] / div
== freq
) {
905 dev_dbg(codec
->dev
, "Configured %dHz OPCLK\n",
907 snd_soc_update_bits(codec
, reg
,
908 ARIZONA_OPCLK_DIV_MASK
|
909 ARIZONA_OPCLK_SEL_MASK
,
911 ARIZONA_OPCLK_DIV_SHIFT
) |
919 dev_err(codec
->dev
, "Unable to generate %dHz OPCLK\n", freq
);
923 int arizona_set_sysclk(struct snd_soc_codec
*codec
, int clk_id
,
924 int source
, unsigned int freq
, int dir
)
926 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
927 struct arizona
*arizona
= priv
->arizona
;
930 unsigned int mask
= ARIZONA_SYSCLK_FREQ_MASK
| ARIZONA_SYSCLK_SRC_MASK
;
931 unsigned int val
= source
<< ARIZONA_SYSCLK_SRC_SHIFT
;
935 case ARIZONA_CLK_SYSCLK
:
937 reg
= ARIZONA_SYSTEM_CLOCK_1
;
939 mask
|= ARIZONA_SYSCLK_FRAC
;
941 case ARIZONA_CLK_ASYNCCLK
:
943 reg
= ARIZONA_ASYNC_CLOCK_1
;
944 clk
= &priv
->asyncclk
;
946 case ARIZONA_CLK_OPCLK
:
947 case ARIZONA_CLK_ASYNC_OPCLK
:
948 return arizona_set_opclk(codec
, clk_id
, freq
);
959 val
|= ARIZONA_CLK_12MHZ
<< ARIZONA_SYSCLK_FREQ_SHIFT
;
963 val
|= ARIZONA_CLK_24MHZ
<< ARIZONA_SYSCLK_FREQ_SHIFT
;
967 val
|= ARIZONA_CLK_49MHZ
<< ARIZONA_SYSCLK_FREQ_SHIFT
;
971 val
|= ARIZONA_CLK_73MHZ
<< ARIZONA_SYSCLK_FREQ_SHIFT
;
975 val
|= ARIZONA_CLK_98MHZ
<< ARIZONA_SYSCLK_FREQ_SHIFT
;
979 val
|= ARIZONA_CLK_147MHZ
<< ARIZONA_SYSCLK_FREQ_SHIFT
;
982 dev_dbg(arizona
->dev
, "%s cleared\n", name
);
992 val
|= ARIZONA_SYSCLK_FRAC
;
994 dev_dbg(arizona
->dev
, "%s set to %uHz", name
, freq
);
996 return regmap_update_bits(arizona
->regmap
, reg
, mask
, val
);
998 EXPORT_SYMBOL_GPL(arizona_set_sysclk
);
1000 static int arizona_set_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
1002 struct snd_soc_codec
*codec
= dai
->codec
;
1003 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1004 struct arizona
*arizona
= priv
->arizona
;
1005 int lrclk
, bclk
, mode
, base
;
1007 base
= dai
->driver
->base
;
1012 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1013 case SND_SOC_DAIFMT_DSP_A
:
1014 mode
= ARIZONA_FMT_DSP_MODE_A
;
1016 case SND_SOC_DAIFMT_DSP_B
:
1017 if ((fmt
& SND_SOC_DAIFMT_MASTER_MASK
)
1018 != SND_SOC_DAIFMT_CBM_CFM
) {
1019 arizona_aif_err(dai
, "DSP_B not valid in slave mode\n");
1022 mode
= ARIZONA_FMT_DSP_MODE_B
;
1024 case SND_SOC_DAIFMT_I2S
:
1025 mode
= ARIZONA_FMT_I2S_MODE
;
1027 case SND_SOC_DAIFMT_LEFT_J
:
1028 if ((fmt
& SND_SOC_DAIFMT_MASTER_MASK
)
1029 != SND_SOC_DAIFMT_CBM_CFM
) {
1030 arizona_aif_err(dai
, "LEFT_J not valid in slave mode\n");
1033 mode
= ARIZONA_FMT_LEFT_JUSTIFIED_MODE
;
1036 arizona_aif_err(dai
, "Unsupported DAI format %d\n",
1037 fmt
& SND_SOC_DAIFMT_FORMAT_MASK
);
1041 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1042 case SND_SOC_DAIFMT_CBS_CFS
:
1044 case SND_SOC_DAIFMT_CBS_CFM
:
1045 lrclk
|= ARIZONA_AIF1TX_LRCLK_MSTR
;
1047 case SND_SOC_DAIFMT_CBM_CFS
:
1048 bclk
|= ARIZONA_AIF1_BCLK_MSTR
;
1050 case SND_SOC_DAIFMT_CBM_CFM
:
1051 bclk
|= ARIZONA_AIF1_BCLK_MSTR
;
1052 lrclk
|= ARIZONA_AIF1TX_LRCLK_MSTR
;
1055 arizona_aif_err(dai
, "Unsupported master mode %d\n",
1056 fmt
& SND_SOC_DAIFMT_MASTER_MASK
);
1060 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1061 case SND_SOC_DAIFMT_NB_NF
:
1063 case SND_SOC_DAIFMT_IB_IF
:
1064 bclk
|= ARIZONA_AIF1_BCLK_INV
;
1065 lrclk
|= ARIZONA_AIF1TX_LRCLK_INV
;
1067 case SND_SOC_DAIFMT_IB_NF
:
1068 bclk
|= ARIZONA_AIF1_BCLK_INV
;
1070 case SND_SOC_DAIFMT_NB_IF
:
1071 lrclk
|= ARIZONA_AIF1TX_LRCLK_INV
;
1077 regmap_update_bits_async(arizona
->regmap
, base
+ ARIZONA_AIF_BCLK_CTRL
,
1078 ARIZONA_AIF1_BCLK_INV
|
1079 ARIZONA_AIF1_BCLK_MSTR
,
1081 regmap_update_bits_async(arizona
->regmap
, base
+ ARIZONA_AIF_TX_PIN_CTRL
,
1082 ARIZONA_AIF1TX_LRCLK_INV
|
1083 ARIZONA_AIF1TX_LRCLK_MSTR
, lrclk
);
1084 regmap_update_bits_async(arizona
->regmap
,
1085 base
+ ARIZONA_AIF_RX_PIN_CTRL
,
1086 ARIZONA_AIF1RX_LRCLK_INV
|
1087 ARIZONA_AIF1RX_LRCLK_MSTR
, lrclk
);
1088 regmap_update_bits(arizona
->regmap
, base
+ ARIZONA_AIF_FORMAT
,
1089 ARIZONA_AIF1_FMT_MASK
, mode
);
1094 static const int arizona_48k_bclk_rates
[] = {
1116 static const unsigned int arizona_48k_rates
[] = {
1134 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint
= {
1135 .count
= ARRAY_SIZE(arizona_48k_rates
),
1136 .list
= arizona_48k_rates
,
1139 static const int arizona_44k1_bclk_rates
[] = {
1161 static const unsigned int arizona_44k1_rates
[] = {
1171 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint
= {
1172 .count
= ARRAY_SIZE(arizona_44k1_rates
),
1173 .list
= arizona_44k1_rates
,
1176 static int arizona_sr_vals
[] = {
1203 static int arizona_startup(struct snd_pcm_substream
*substream
,
1204 struct snd_soc_dai
*dai
)
1206 struct snd_soc_codec
*codec
= dai
->codec
;
1207 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1208 struct arizona_dai_priv
*dai_priv
= &priv
->dai
[dai
->id
- 1];
1209 const struct snd_pcm_hw_constraint_list
*constraint
;
1210 unsigned int base_rate
;
1212 switch (dai_priv
->clk
) {
1213 case ARIZONA_CLK_SYSCLK
:
1214 base_rate
= priv
->sysclk
;
1216 case ARIZONA_CLK_ASYNCCLK
:
1217 base_rate
= priv
->asyncclk
;
1226 if (base_rate
% 8000)
1227 constraint
= &arizona_44k1_constraint
;
1229 constraint
= &arizona_48k_constraint
;
1231 return snd_pcm_hw_constraint_list(substream
->runtime
, 0,
1232 SNDRV_PCM_HW_PARAM_RATE
,
1236 static void arizona_wm5102_set_dac_comp(struct snd_soc_codec
*codec
,
1239 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1240 struct arizona
*arizona
= priv
->arizona
;
1241 struct reg_default dac_comp
[] = {
1243 { ARIZONA_DAC_COMP_1
, 0 },
1244 { ARIZONA_DAC_COMP_2
, 0 },
1248 mutex_lock(&arizona
->dac_comp_lock
);
1250 dac_comp
[1].def
= arizona
->dac_comp_coeff
;
1252 dac_comp
[2].def
= arizona
->dac_comp_enabled
;
1254 mutex_unlock(&arizona
->dac_comp_lock
);
1256 regmap_multi_reg_write(arizona
->regmap
,
1258 ARRAY_SIZE(dac_comp
));
1261 static int arizona_hw_params_rate(struct snd_pcm_substream
*substream
,
1262 struct snd_pcm_hw_params
*params
,
1263 struct snd_soc_dai
*dai
)
1265 struct snd_soc_codec
*codec
= dai
->codec
;
1266 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1267 struct arizona_dai_priv
*dai_priv
= &priv
->dai
[dai
->id
- 1];
1268 int base
= dai
->driver
->base
;
1272 * We will need to be more flexible than this in future,
1273 * currently we use a single sample rate for SYSCLK.
1275 for (i
= 0; i
< ARRAY_SIZE(arizona_sr_vals
); i
++)
1276 if (arizona_sr_vals
[i
] == params_rate(params
))
1278 if (i
== ARRAY_SIZE(arizona_sr_vals
)) {
1279 arizona_aif_err(dai
, "Unsupported sample rate %dHz\n",
1280 params_rate(params
));
1285 switch (dai_priv
->clk
) {
1286 case ARIZONA_CLK_SYSCLK
:
1287 switch (priv
->arizona
->type
) {
1289 arizona_wm5102_set_dac_comp(codec
,
1290 params_rate(params
));
1296 snd_soc_update_bits(codec
, ARIZONA_SAMPLE_RATE_1
,
1297 ARIZONA_SAMPLE_RATE_1_MASK
, sr_val
);
1299 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_RATE_CTRL
,
1300 ARIZONA_AIF1_RATE_MASK
, 0);
1302 case ARIZONA_CLK_ASYNCCLK
:
1303 snd_soc_update_bits(codec
, ARIZONA_ASYNC_SAMPLE_RATE_1
,
1304 ARIZONA_ASYNC_SAMPLE_RATE_1_MASK
, sr_val
);
1306 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_RATE_CTRL
,
1307 ARIZONA_AIF1_RATE_MASK
,
1308 8 << ARIZONA_AIF1_RATE_SHIFT
);
1311 arizona_aif_err(dai
, "Invalid clock %d\n", dai_priv
->clk
);
1318 static bool arizona_aif_cfg_changed(struct snd_soc_codec
*codec
,
1319 int base
, int bclk
, int lrclk
, int frame
)
1323 val
= snd_soc_read(codec
, base
+ ARIZONA_AIF_BCLK_CTRL
);
1324 if (bclk
!= (val
& ARIZONA_AIF1_BCLK_FREQ_MASK
))
1327 val
= snd_soc_read(codec
, base
+ ARIZONA_AIF_TX_BCLK_RATE
);
1328 if (lrclk
!= (val
& ARIZONA_AIF1TX_BCPF_MASK
))
1331 val
= snd_soc_read(codec
, base
+ ARIZONA_AIF_FRAME_CTRL_1
);
1332 if (frame
!= (val
& (ARIZONA_AIF1TX_WL_MASK
|
1333 ARIZONA_AIF1TX_SLOT_LEN_MASK
)))
1339 static int arizona_hw_params(struct snd_pcm_substream
*substream
,
1340 struct snd_pcm_hw_params
*params
,
1341 struct snd_soc_dai
*dai
)
1343 struct snd_soc_codec
*codec
= dai
->codec
;
1344 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1345 struct arizona
*arizona
= priv
->arizona
;
1346 int base
= dai
->driver
->base
;
1349 int channels
= params_channels(params
);
1350 int chan_limit
= arizona
->pdata
.max_channels_clocked
[dai
->id
- 1];
1351 int tdm_width
= arizona
->tdm_width
[dai
->id
- 1];
1352 int tdm_slots
= arizona
->tdm_slots
[dai
->id
- 1];
1353 int bclk
, lrclk
, wl
, frame
, bclk_target
;
1355 unsigned int aif_tx_state
, aif_rx_state
;
1357 if (params_rate(params
) % 8000)
1358 rates
= &arizona_44k1_bclk_rates
[0];
1360 rates
= &arizona_48k_bclk_rates
[0];
1362 wl
= snd_pcm_format_width(params_format(params
));
1365 arizona_aif_dbg(dai
, "Configuring for %d %d bit TDM slots\n",
1366 tdm_slots
, tdm_width
);
1367 bclk_target
= tdm_slots
* tdm_width
* params_rate(params
);
1368 channels
= tdm_slots
;
1370 bclk_target
= snd_soc_params_to_bclk(params
);
1374 if (chan_limit
&& chan_limit
< channels
) {
1375 arizona_aif_dbg(dai
, "Limiting to %d channels\n", chan_limit
);
1376 bclk_target
/= channels
;
1377 bclk_target
*= chan_limit
;
1380 /* Force multiple of 2 channels for I2S mode */
1381 val
= snd_soc_read(codec
, base
+ ARIZONA_AIF_FORMAT
);
1382 val
&= ARIZONA_AIF1_FMT_MASK
;
1383 if ((channels
& 1) && (val
== ARIZONA_FMT_I2S_MODE
)) {
1384 arizona_aif_dbg(dai
, "Forcing stereo mode\n");
1385 bclk_target
/= channels
;
1386 bclk_target
*= channels
+ 1;
1389 for (i
= 0; i
< ARRAY_SIZE(arizona_44k1_bclk_rates
); i
++) {
1390 if (rates
[i
] >= bclk_target
&&
1391 rates
[i
] % params_rate(params
) == 0) {
1396 if (i
== ARRAY_SIZE(arizona_44k1_bclk_rates
)) {
1397 arizona_aif_err(dai
, "Unsupported sample rate %dHz\n",
1398 params_rate(params
));
1402 lrclk
= rates
[bclk
] / params_rate(params
);
1404 arizona_aif_dbg(dai
, "BCLK %dHz LRCLK %dHz\n",
1405 rates
[bclk
], rates
[bclk
] / lrclk
);
1407 frame
= wl
<< ARIZONA_AIF1TX_WL_SHIFT
| tdm_width
;
1409 reconfig
= arizona_aif_cfg_changed(codec
, base
, bclk
, lrclk
, frame
);
1412 /* Save AIF TX/RX state */
1413 aif_tx_state
= snd_soc_read(codec
,
1414 base
+ ARIZONA_AIF_TX_ENABLES
);
1415 aif_rx_state
= snd_soc_read(codec
,
1416 base
+ ARIZONA_AIF_RX_ENABLES
);
1417 /* Disable AIF TX/RX before reconfiguring it */
1418 regmap_update_bits_async(arizona
->regmap
,
1419 base
+ ARIZONA_AIF_TX_ENABLES
, 0xff, 0x0);
1420 regmap_update_bits(arizona
->regmap
,
1421 base
+ ARIZONA_AIF_RX_ENABLES
, 0xff, 0x0);
1424 ret
= arizona_hw_params_rate(substream
, params
, dai
);
1429 regmap_update_bits_async(arizona
->regmap
,
1430 base
+ ARIZONA_AIF_BCLK_CTRL
,
1431 ARIZONA_AIF1_BCLK_FREQ_MASK
, bclk
);
1432 regmap_update_bits_async(arizona
->regmap
,
1433 base
+ ARIZONA_AIF_TX_BCLK_RATE
,
1434 ARIZONA_AIF1TX_BCPF_MASK
, lrclk
);
1435 regmap_update_bits_async(arizona
->regmap
,
1436 base
+ ARIZONA_AIF_RX_BCLK_RATE
,
1437 ARIZONA_AIF1RX_BCPF_MASK
, lrclk
);
1438 regmap_update_bits_async(arizona
->regmap
,
1439 base
+ ARIZONA_AIF_FRAME_CTRL_1
,
1440 ARIZONA_AIF1TX_WL_MASK
|
1441 ARIZONA_AIF1TX_SLOT_LEN_MASK
, frame
);
1442 regmap_update_bits(arizona
->regmap
,
1443 base
+ ARIZONA_AIF_FRAME_CTRL_2
,
1444 ARIZONA_AIF1RX_WL_MASK
|
1445 ARIZONA_AIF1RX_SLOT_LEN_MASK
, frame
);
1450 /* Restore AIF TX/RX state */
1451 regmap_update_bits_async(arizona
->regmap
,
1452 base
+ ARIZONA_AIF_TX_ENABLES
,
1453 0xff, aif_tx_state
);
1454 regmap_update_bits(arizona
->regmap
,
1455 base
+ ARIZONA_AIF_RX_ENABLES
,
1456 0xff, aif_rx_state
);
1461 static const char *arizona_dai_clk_str(int clk_id
)
1464 case ARIZONA_CLK_SYSCLK
:
1466 case ARIZONA_CLK_ASYNCCLK
:
1469 return "Unknown clock";
1473 static int arizona_dai_set_sysclk(struct snd_soc_dai
*dai
,
1474 int clk_id
, unsigned int freq
, int dir
)
1476 struct snd_soc_codec
*codec
= dai
->codec
;
1477 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
1478 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1479 struct arizona_dai_priv
*dai_priv
= &priv
->dai
[dai
->id
- 1];
1480 struct snd_soc_dapm_route routes
[2];
1483 case ARIZONA_CLK_SYSCLK
:
1484 case ARIZONA_CLK_ASYNCCLK
:
1490 if (clk_id
== dai_priv
->clk
)
1494 dev_err(codec
->dev
, "Can't change clock on active DAI %d\n",
1499 dev_dbg(codec
->dev
, "Setting AIF%d to %s\n", dai
->id
+ 1,
1500 arizona_dai_clk_str(clk_id
));
1502 memset(&routes
, 0, sizeof(routes
));
1503 routes
[0].sink
= dai
->driver
->capture
.stream_name
;
1504 routes
[1].sink
= dai
->driver
->playback
.stream_name
;
1506 routes
[0].source
= arizona_dai_clk_str(dai_priv
->clk
);
1507 routes
[1].source
= arizona_dai_clk_str(dai_priv
->clk
);
1508 snd_soc_dapm_del_routes(dapm
, routes
, ARRAY_SIZE(routes
));
1510 routes
[0].source
= arizona_dai_clk_str(clk_id
);
1511 routes
[1].source
= arizona_dai_clk_str(clk_id
);
1512 snd_soc_dapm_add_routes(dapm
, routes
, ARRAY_SIZE(routes
));
1514 dai_priv
->clk
= clk_id
;
1516 return snd_soc_dapm_sync(dapm
);
1519 static int arizona_set_tristate(struct snd_soc_dai
*dai
, int tristate
)
1521 struct snd_soc_codec
*codec
= dai
->codec
;
1522 int base
= dai
->driver
->base
;
1526 reg
= ARIZONA_AIF1_TRI
;
1530 return snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_RATE_CTRL
,
1531 ARIZONA_AIF1_TRI
, reg
);
1534 static void arizona_set_channels_to_mask(struct snd_soc_dai
*dai
,
1536 int channels
, unsigned int mask
)
1538 struct snd_soc_codec
*codec
= dai
->codec
;
1539 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1540 struct arizona
*arizona
= priv
->arizona
;
1543 for (i
= 0; i
< channels
; ++i
) {
1544 slot
= ffs(mask
) - 1;
1548 regmap_write(arizona
->regmap
, base
+ i
, slot
);
1550 mask
&= ~(1 << slot
);
1554 arizona_aif_warn(dai
, "Too many channels in TDM mask\n");
1557 static int arizona_set_tdm_slot(struct snd_soc_dai
*dai
, unsigned int tx_mask
,
1558 unsigned int rx_mask
, int slots
, int slot_width
)
1560 struct snd_soc_codec
*codec
= dai
->codec
;
1561 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1562 struct arizona
*arizona
= priv
->arizona
;
1563 int base
= dai
->driver
->base
;
1564 int rx_max_chan
= dai
->driver
->playback
.channels_max
;
1565 int tx_max_chan
= dai
->driver
->capture
.channels_max
;
1567 /* Only support TDM for the physical AIFs */
1568 if (dai
->id
> ARIZONA_MAX_AIF
)
1572 tx_mask
= (1 << tx_max_chan
) - 1;
1573 rx_mask
= (1 << rx_max_chan
) - 1;
1576 arizona_set_channels_to_mask(dai
, base
+ ARIZONA_AIF_FRAME_CTRL_3
,
1577 tx_max_chan
, tx_mask
);
1578 arizona_set_channels_to_mask(dai
, base
+ ARIZONA_AIF_FRAME_CTRL_11
,
1579 rx_max_chan
, rx_mask
);
1581 arizona
->tdm_width
[dai
->id
- 1] = slot_width
;
1582 arizona
->tdm_slots
[dai
->id
- 1] = slots
;
1587 const struct snd_soc_dai_ops arizona_dai_ops
= {
1588 .startup
= arizona_startup
,
1589 .set_fmt
= arizona_set_fmt
,
1590 .set_tdm_slot
= arizona_set_tdm_slot
,
1591 .hw_params
= arizona_hw_params
,
1592 .set_sysclk
= arizona_dai_set_sysclk
,
1593 .set_tristate
= arizona_set_tristate
,
1595 EXPORT_SYMBOL_GPL(arizona_dai_ops
);
1597 const struct snd_soc_dai_ops arizona_simple_dai_ops
= {
1598 .startup
= arizona_startup
,
1599 .hw_params
= arizona_hw_params_rate
,
1600 .set_sysclk
= arizona_dai_set_sysclk
,
1602 EXPORT_SYMBOL_GPL(arizona_simple_dai_ops
);
1604 int arizona_init_dai(struct arizona_priv
*priv
, int id
)
1606 struct arizona_dai_priv
*dai_priv
= &priv
->dai
[id
];
1608 dai_priv
->clk
= ARIZONA_CLK_SYSCLK
;
1612 EXPORT_SYMBOL_GPL(arizona_init_dai
);
1614 static irqreturn_t
arizona_fll_clock_ok(int irq
, void *data
)
1616 struct arizona_fll
*fll
= data
;
1618 arizona_fll_dbg(fll
, "clock OK\n");
1631 { 0, 64000, 4, 16 },
1632 { 64000, 128000, 3, 8 },
1633 { 128000, 256000, 2, 4 },
1634 { 256000, 1000000, 1, 2 },
1635 { 1000000, 13500000, 0, 1 },
1644 { 256000, 1000000, 2 },
1645 { 1000000, 13500000, 4 },
1648 struct arizona_fll_cfg
{
1658 static int arizona_validate_fll(struct arizona_fll
*fll
,
1662 unsigned int Fvco_min
;
1664 if (fll
->fout
&& Fout
!= fll
->fout
) {
1665 arizona_fll_err(fll
,
1666 "Can't change output on active FLL\n");
1670 if (Fref
/ ARIZONA_FLL_MAX_REFDIV
> ARIZONA_FLL_MAX_FREF
) {
1671 arizona_fll_err(fll
,
1672 "Can't scale %dMHz in to <=13.5MHz\n",
1677 Fvco_min
= ARIZONA_FLL_MIN_FVCO
* fll
->vco_mult
;
1678 if (Fout
* ARIZONA_FLL_MAX_OUTDIV
< Fvco_min
) {
1679 arizona_fll_err(fll
, "No FLL_OUTDIV for Fout=%uHz\n",
1687 static int arizona_find_fratio(unsigned int Fref
, int *fratio
)
1691 /* Find an appropriate FLL_FRATIO */
1692 for (i
= 0; i
< ARRAY_SIZE(fll_fratios
); i
++) {
1693 if (fll_fratios
[i
].min
<= Fref
&& Fref
<= fll_fratios
[i
].max
) {
1695 *fratio
= fll_fratios
[i
].fratio
;
1696 return fll_fratios
[i
].ratio
;
1703 static int arizona_calc_fratio(struct arizona_fll
*fll
,
1704 struct arizona_fll_cfg
*cfg
,
1705 unsigned int target
,
1706 unsigned int Fref
, bool sync
)
1708 int init_ratio
, ratio
;
1711 /* Fref must be <=13.5MHz, find initial refdiv */
1714 while (Fref
> ARIZONA_FLL_MAX_FREF
) {
1719 if (div
> ARIZONA_FLL_MAX_REFDIV
)
1723 /* Find an appropriate FLL_FRATIO */
1724 init_ratio
= arizona_find_fratio(Fref
, &cfg
->fratio
);
1725 if (init_ratio
< 0) {
1726 arizona_fll_err(fll
, "Unable to find FRATIO for Fref=%uHz\n",
1731 switch (fll
->arizona
->type
) {
1734 if (fll
->arizona
->rev
< 3 || sync
)
1741 cfg
->fratio
= init_ratio
- 1;
1743 /* Adjust FRATIO/refdiv to avoid integer mode if possible */
1744 refdiv
= cfg
->refdiv
;
1746 while (div
<= ARIZONA_FLL_MAX_REFDIV
) {
1747 for (ratio
= init_ratio
; ratio
<= ARIZONA_FLL_MAX_FRATIO
;
1749 if ((ARIZONA_FLL_VCO_CORNER
/ 2) /
1750 (fll
->vco_mult
* ratio
) < Fref
)
1753 if (target
% (ratio
* Fref
)) {
1754 cfg
->refdiv
= refdiv
;
1755 cfg
->fratio
= ratio
- 1;
1760 for (ratio
= init_ratio
- 1; ratio
> 0; ratio
--) {
1761 if (target
% (ratio
* Fref
)) {
1762 cfg
->refdiv
= refdiv
;
1763 cfg
->fratio
= ratio
- 1;
1771 init_ratio
= arizona_find_fratio(Fref
, NULL
);
1774 arizona_fll_warn(fll
, "Falling back to integer mode operation\n");
1775 return cfg
->fratio
+ 1;
1778 static int arizona_calc_fll(struct arizona_fll
*fll
,
1779 struct arizona_fll_cfg
*cfg
,
1780 unsigned int Fref
, bool sync
)
1782 unsigned int target
, div
, gcd_fll
;
1785 arizona_fll_dbg(fll
, "Fref=%u Fout=%u\n", Fref
, fll
->fout
);
1787 /* Fvco should be over the targt; don't check the upper bound */
1788 div
= ARIZONA_FLL_MIN_OUTDIV
;
1789 while (fll
->fout
* div
< ARIZONA_FLL_MIN_FVCO
* fll
->vco_mult
) {
1791 if (div
> ARIZONA_FLL_MAX_OUTDIV
)
1794 target
= fll
->fout
* div
/ fll
->vco_mult
;
1797 arizona_fll_dbg(fll
, "Fvco=%dHz\n", target
);
1799 /* Find an appropriate FLL_FRATIO and refdiv */
1800 ratio
= arizona_calc_fratio(fll
, cfg
, target
, Fref
, sync
);
1804 /* Apply the division for our remaining calculations */
1805 Fref
= Fref
/ (1 << cfg
->refdiv
);
1807 cfg
->n
= target
/ (ratio
* Fref
);
1809 if (target
% (ratio
* Fref
)) {
1810 gcd_fll
= gcd(target
, ratio
* Fref
);
1811 arizona_fll_dbg(fll
, "GCD=%u\n", gcd_fll
);
1813 cfg
->theta
= (target
- (cfg
->n
* ratio
* Fref
))
1815 cfg
->lambda
= (ratio
* Fref
) / gcd_fll
;
1821 /* Round down to 16bit range with cost of accuracy lost.
1822 * Denominator must be bigger than numerator so we only
1825 while (cfg
->lambda
>= (1 << 16)) {
1830 for (i
= 0; i
< ARRAY_SIZE(fll_gains
); i
++) {
1831 if (fll_gains
[i
].min
<= Fref
&& Fref
<= fll_gains
[i
].max
) {
1832 cfg
->gain
= fll_gains
[i
].gain
;
1836 if (i
== ARRAY_SIZE(fll_gains
)) {
1837 arizona_fll_err(fll
, "Unable to find gain for Fref=%uHz\n",
1842 arizona_fll_dbg(fll
, "N=%x THETA=%x LAMBDA=%x\n",
1843 cfg
->n
, cfg
->theta
, cfg
->lambda
);
1844 arizona_fll_dbg(fll
, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
1845 cfg
->fratio
, cfg
->fratio
, cfg
->outdiv
, cfg
->refdiv
);
1846 arizona_fll_dbg(fll
, "GAIN=%d\n", cfg
->gain
);
1852 static void arizona_apply_fll(struct arizona
*arizona
, unsigned int base
,
1853 struct arizona_fll_cfg
*cfg
, int source
,
1856 regmap_update_bits_async(arizona
->regmap
, base
+ 3,
1857 ARIZONA_FLL1_THETA_MASK
, cfg
->theta
);
1858 regmap_update_bits_async(arizona
->regmap
, base
+ 4,
1859 ARIZONA_FLL1_LAMBDA_MASK
, cfg
->lambda
);
1860 regmap_update_bits_async(arizona
->regmap
, base
+ 5,
1861 ARIZONA_FLL1_FRATIO_MASK
,
1862 cfg
->fratio
<< ARIZONA_FLL1_FRATIO_SHIFT
);
1863 regmap_update_bits_async(arizona
->regmap
, base
+ 6,
1864 ARIZONA_FLL1_CLK_REF_DIV_MASK
|
1865 ARIZONA_FLL1_CLK_REF_SRC_MASK
,
1866 cfg
->refdiv
<< ARIZONA_FLL1_CLK_REF_DIV_SHIFT
|
1867 source
<< ARIZONA_FLL1_CLK_REF_SRC_SHIFT
);
1870 regmap_update_bits(arizona
->regmap
, base
+ 0x7,
1871 ARIZONA_FLL1_GAIN_MASK
,
1872 cfg
->gain
<< ARIZONA_FLL1_GAIN_SHIFT
);
1874 regmap_update_bits(arizona
->regmap
, base
+ 0x5,
1875 ARIZONA_FLL1_OUTDIV_MASK
,
1876 cfg
->outdiv
<< ARIZONA_FLL1_OUTDIV_SHIFT
);
1877 regmap_update_bits(arizona
->regmap
, base
+ 0x9,
1878 ARIZONA_FLL1_GAIN_MASK
,
1879 cfg
->gain
<< ARIZONA_FLL1_GAIN_SHIFT
);
1882 regmap_update_bits_async(arizona
->regmap
, base
+ 2,
1883 ARIZONA_FLL1_CTRL_UPD
| ARIZONA_FLL1_N_MASK
,
1884 ARIZONA_FLL1_CTRL_UPD
| cfg
->n
);
1887 static int arizona_is_enabled_fll(struct arizona_fll
*fll
)
1889 struct arizona
*arizona
= fll
->arizona
;
1893 ret
= regmap_read(arizona
->regmap
, fll
->base
+ 1, ®
);
1895 arizona_fll_err(fll
, "Failed to read current state: %d\n",
1900 return reg
& ARIZONA_FLL1_ENA
;
1903 static int arizona_enable_fll(struct arizona_fll
*fll
)
1905 struct arizona
*arizona
= fll
->arizona
;
1906 unsigned long time_left
;
1907 bool use_sync
= false;
1908 int already_enabled
= arizona_is_enabled_fll(fll
);
1909 struct arizona_fll_cfg cfg
;
1911 if (already_enabled
< 0)
1912 return already_enabled
;
1914 if (already_enabled
) {
1915 /* Facilitate smooth refclk across the transition */
1916 regmap_update_bits_async(fll
->arizona
->regmap
, fll
->base
+ 0x7,
1917 ARIZONA_FLL1_GAIN_MASK
, 0);
1918 regmap_update_bits_async(fll
->arizona
->regmap
, fll
->base
+ 1,
1919 ARIZONA_FLL1_FREERUN
,
1920 ARIZONA_FLL1_FREERUN
);
1924 * If we have both REFCLK and SYNCCLK then enable both,
1925 * otherwise apply the SYNCCLK settings to REFCLK.
1927 if (fll
->ref_src
>= 0 && fll
->ref_freq
&&
1928 fll
->ref_src
!= fll
->sync_src
) {
1929 arizona_calc_fll(fll
, &cfg
, fll
->ref_freq
, false);
1931 arizona_apply_fll(arizona
, fll
->base
, &cfg
, fll
->ref_src
,
1933 if (fll
->sync_src
>= 0) {
1934 arizona_calc_fll(fll
, &cfg
, fll
->sync_freq
, true);
1936 arizona_apply_fll(arizona
, fll
->base
+ 0x10, &cfg
,
1937 fll
->sync_src
, true);
1940 } else if (fll
->sync_src
>= 0) {
1941 arizona_calc_fll(fll
, &cfg
, fll
->sync_freq
, false);
1943 arizona_apply_fll(arizona
, fll
->base
, &cfg
,
1944 fll
->sync_src
, false);
1946 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 0x11,
1947 ARIZONA_FLL1_SYNC_ENA
, 0);
1949 arizona_fll_err(fll
, "No clocks provided\n");
1954 * Increase the bandwidth if we're not using a low frequency
1957 if (use_sync
&& fll
->sync_freq
> 100000)
1958 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 0x17,
1959 ARIZONA_FLL1_SYNC_BW
, 0);
1961 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 0x17,
1962 ARIZONA_FLL1_SYNC_BW
,
1963 ARIZONA_FLL1_SYNC_BW
);
1965 if (!already_enabled
)
1966 pm_runtime_get(arizona
->dev
);
1968 /* Clear any pending completions */
1969 try_wait_for_completion(&fll
->ok
);
1971 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 1,
1972 ARIZONA_FLL1_ENA
, ARIZONA_FLL1_ENA
);
1974 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 0x11,
1975 ARIZONA_FLL1_SYNC_ENA
,
1976 ARIZONA_FLL1_SYNC_ENA
);
1978 if (already_enabled
)
1979 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 1,
1980 ARIZONA_FLL1_FREERUN
, 0);
1982 time_left
= wait_for_completion_timeout(&fll
->ok
,
1983 msecs_to_jiffies(250));
1985 arizona_fll_warn(fll
, "Timed out waiting for lock\n");
1990 static void arizona_disable_fll(struct arizona_fll
*fll
)
1992 struct arizona
*arizona
= fll
->arizona
;
1995 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 1,
1996 ARIZONA_FLL1_FREERUN
, ARIZONA_FLL1_FREERUN
);
1997 regmap_update_bits_check(arizona
->regmap
, fll
->base
+ 1,
1998 ARIZONA_FLL1_ENA
, 0, &change
);
1999 regmap_update_bits(arizona
->regmap
, fll
->base
+ 0x11,
2000 ARIZONA_FLL1_SYNC_ENA
, 0);
2001 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 1,
2002 ARIZONA_FLL1_FREERUN
, 0);
2005 pm_runtime_put_autosuspend(arizona
->dev
);
2008 int arizona_set_fll_refclk(struct arizona_fll
*fll
, int source
,
2009 unsigned int Fref
, unsigned int Fout
)
2013 if (fll
->ref_src
== source
&& fll
->ref_freq
== Fref
)
2016 if (fll
->fout
&& Fref
> 0) {
2017 ret
= arizona_validate_fll(fll
, Fref
, fll
->fout
);
2022 fll
->ref_src
= source
;
2023 fll
->ref_freq
= Fref
;
2025 if (fll
->fout
&& Fref
> 0) {
2026 ret
= arizona_enable_fll(fll
);
2031 EXPORT_SYMBOL_GPL(arizona_set_fll_refclk
);
2033 int arizona_set_fll(struct arizona_fll
*fll
, int source
,
2034 unsigned int Fref
, unsigned int Fout
)
2038 if (fll
->sync_src
== source
&&
2039 fll
->sync_freq
== Fref
&& fll
->fout
== Fout
)
2043 if (fll
->ref_src
>= 0) {
2044 ret
= arizona_validate_fll(fll
, fll
->ref_freq
, Fout
);
2049 ret
= arizona_validate_fll(fll
, Fref
, Fout
);
2054 fll
->sync_src
= source
;
2055 fll
->sync_freq
= Fref
;
2059 ret
= arizona_enable_fll(fll
);
2061 arizona_disable_fll(fll
);
2065 EXPORT_SYMBOL_GPL(arizona_set_fll
);
2067 int arizona_init_fll(struct arizona
*arizona
, int id
, int base
, int lock_irq
,
2068 int ok_irq
, struct arizona_fll
*fll
)
2073 init_completion(&fll
->ok
);
2077 fll
->arizona
= arizona
;
2078 fll
->sync_src
= ARIZONA_FLL_SRC_NONE
;
2080 /* Configure default refclk to 32kHz if we have one */
2081 regmap_read(arizona
->regmap
, ARIZONA_CLOCK_32K_1
, &val
);
2082 switch (val
& ARIZONA_CLK_32K_SRC_MASK
) {
2083 case ARIZONA_CLK_SRC_MCLK1
:
2084 case ARIZONA_CLK_SRC_MCLK2
:
2085 fll
->ref_src
= val
& ARIZONA_CLK_32K_SRC_MASK
;
2088 fll
->ref_src
= ARIZONA_FLL_SRC_NONE
;
2090 fll
->ref_freq
= 32768;
2092 snprintf(fll
->lock_name
, sizeof(fll
->lock_name
), "FLL%d lock", id
);
2093 snprintf(fll
->clock_ok_name
, sizeof(fll
->clock_ok_name
),
2094 "FLL%d clock OK", id
);
2096 ret
= arizona_request_irq(arizona
, ok_irq
, fll
->clock_ok_name
,
2097 arizona_fll_clock_ok
, fll
);
2099 dev_err(arizona
->dev
, "Failed to get FLL%d clock OK IRQ: %d\n",
2103 regmap_update_bits(arizona
->regmap
, fll
->base
+ 1,
2104 ARIZONA_FLL1_FREERUN
, 0);
2108 EXPORT_SYMBOL_GPL(arizona_init_fll
);
2111 * arizona_set_output_mode - Set the mode of the specified output
2113 * @codec: Device to configure
2114 * @output: Output number
2115 * @diff: True to set the output to differential mode
2117 * Some systems use external analogue switches to connect more
2118 * analogue devices to the CODEC than are supported by the device. In
2119 * some systems this requires changing the switched output from single
2120 * ended to differential mode dynamically at runtime, an operation
2121 * supported using this function.
2123 * Most systems have a single static configuration and should use
2124 * platform data instead.
2126 int arizona_set_output_mode(struct snd_soc_codec
*codec
, int output
, bool diff
)
2128 unsigned int reg
, val
;
2130 if (output
< 1 || output
> 6)
2133 reg
= ARIZONA_OUTPUT_PATH_CONFIG_1L
+ (output
- 1) * 8;
2136 val
= ARIZONA_OUT1_MONO
;
2140 return snd_soc_update_bits(codec
, reg
, ARIZONA_OUT1_MONO
, val
);
2142 EXPORT_SYMBOL_GPL(arizona_set_output_mode
);
2144 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
2145 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2146 MODULE_LICENSE("GPL");