2 * arizona.c - Wolfson Arizona class device shared support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/gcd.h>
14 #include <linux/module.h>
15 #include <linux/pm_runtime.h>
16 #include <sound/pcm.h>
17 #include <sound/pcm_params.h>
18 #include <sound/tlv.h>
20 #include <linux/mfd/arizona/core.h>
21 #include <linux/mfd/arizona/registers.h>
25 #define ARIZONA_AIF_BCLK_CTRL 0x00
26 #define ARIZONA_AIF_TX_PIN_CTRL 0x01
27 #define ARIZONA_AIF_RX_PIN_CTRL 0x02
28 #define ARIZONA_AIF_RATE_CTRL 0x03
29 #define ARIZONA_AIF_FORMAT 0x04
30 #define ARIZONA_AIF_TX_BCLK_RATE 0x05
31 #define ARIZONA_AIF_RX_BCLK_RATE 0x06
32 #define ARIZONA_AIF_FRAME_CTRL_1 0x07
33 #define ARIZONA_AIF_FRAME_CTRL_2 0x08
34 #define ARIZONA_AIF_FRAME_CTRL_3 0x09
35 #define ARIZONA_AIF_FRAME_CTRL_4 0x0A
36 #define ARIZONA_AIF_FRAME_CTRL_5 0x0B
37 #define ARIZONA_AIF_FRAME_CTRL_6 0x0C
38 #define ARIZONA_AIF_FRAME_CTRL_7 0x0D
39 #define ARIZONA_AIF_FRAME_CTRL_8 0x0E
40 #define ARIZONA_AIF_FRAME_CTRL_9 0x0F
41 #define ARIZONA_AIF_FRAME_CTRL_10 0x10
42 #define ARIZONA_AIF_FRAME_CTRL_11 0x11
43 #define ARIZONA_AIF_FRAME_CTRL_12 0x12
44 #define ARIZONA_AIF_FRAME_CTRL_13 0x13
45 #define ARIZONA_AIF_FRAME_CTRL_14 0x14
46 #define ARIZONA_AIF_FRAME_CTRL_15 0x15
47 #define ARIZONA_AIF_FRAME_CTRL_16 0x16
48 #define ARIZONA_AIF_FRAME_CTRL_17 0x17
49 #define ARIZONA_AIF_FRAME_CTRL_18 0x18
50 #define ARIZONA_AIF_TX_ENABLES 0x19
51 #define ARIZONA_AIF_RX_ENABLES 0x1A
52 #define ARIZONA_AIF_FORCE_WRITE 0x1B
54 #define arizona_fll_err(_fll, fmt, ...) \
55 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
56 #define arizona_fll_warn(_fll, fmt, ...) \
57 dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
58 #define arizona_fll_dbg(_fll, fmt, ...) \
59 dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
61 #define arizona_aif_err(_dai, fmt, ...) \
62 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
63 #define arizona_aif_warn(_dai, fmt, ...) \
64 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
65 #define arizona_aif_dbg(_dai, fmt, ...) \
66 dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
68 const char *arizona_mixer_texts
[ARIZONA_NUM_MIXER_INPUTS
] = {
169 EXPORT_SYMBOL_GPL(arizona_mixer_texts
);
171 int arizona_mixer_values
[ARIZONA_NUM_MIXER_INPUTS
] = {
177 0x0c, /* Noise mixer */
178 0x0d, /* Comfort noise */
247 0xa0, /* ISRC1INT1 */
251 0xa4, /* ISRC1DEC1 */
255 0xa8, /* ISRC2DEC1 */
259 0xac, /* ISRC2INT1 */
263 0xb0, /* ISRC3DEC1 */
267 0xb4, /* ISRC3INT1 */
272 EXPORT_SYMBOL_GPL(arizona_mixer_values
);
274 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv
, -3200, 100, 0);
275 EXPORT_SYMBOL_GPL(arizona_mixer_tlv
);
277 static const char *arizona_vol_ramp_text
[] = {
278 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
279 "15ms/6dB", "30ms/6dB",
282 const struct soc_enum arizona_in_vd_ramp
=
283 SOC_ENUM_SINGLE(ARIZONA_INPUT_VOLUME_RAMP
,
284 ARIZONA_IN_VD_RAMP_SHIFT
, 7, arizona_vol_ramp_text
);
285 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp
);
287 const struct soc_enum arizona_in_vi_ramp
=
288 SOC_ENUM_SINGLE(ARIZONA_INPUT_VOLUME_RAMP
,
289 ARIZONA_IN_VI_RAMP_SHIFT
, 7, arizona_vol_ramp_text
);
290 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp
);
292 const struct soc_enum arizona_out_vd_ramp
=
293 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_VOLUME_RAMP
,
294 ARIZONA_OUT_VD_RAMP_SHIFT
, 7, arizona_vol_ramp_text
);
295 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp
);
297 const struct soc_enum arizona_out_vi_ramp
=
298 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_VOLUME_RAMP
,
299 ARIZONA_OUT_VI_RAMP_SHIFT
, 7, arizona_vol_ramp_text
);
300 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp
);
302 static const char *arizona_lhpf_mode_text
[] = {
303 "Low-pass", "High-pass"
306 const struct soc_enum arizona_lhpf1_mode
=
307 SOC_ENUM_SINGLE(ARIZONA_HPLPF1_1
, ARIZONA_LHPF1_MODE_SHIFT
, 2,
308 arizona_lhpf_mode_text
);
309 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode
);
311 const struct soc_enum arizona_lhpf2_mode
=
312 SOC_ENUM_SINGLE(ARIZONA_HPLPF2_1
, ARIZONA_LHPF2_MODE_SHIFT
, 2,
313 arizona_lhpf_mode_text
);
314 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode
);
316 const struct soc_enum arizona_lhpf3_mode
=
317 SOC_ENUM_SINGLE(ARIZONA_HPLPF3_1
, ARIZONA_LHPF3_MODE_SHIFT
, 2,
318 arizona_lhpf_mode_text
);
319 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode
);
321 const struct soc_enum arizona_lhpf4_mode
=
322 SOC_ENUM_SINGLE(ARIZONA_HPLPF4_1
, ARIZONA_LHPF4_MODE_SHIFT
, 2,
323 arizona_lhpf_mode_text
);
324 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode
);
326 static const char *arizona_ng_hold_text
[] = {
327 "30ms", "120ms", "250ms", "500ms",
330 const struct soc_enum arizona_ng_hold
=
331 SOC_ENUM_SINGLE(ARIZONA_NOISE_GATE_CONTROL
, ARIZONA_NGATE_HOLD_SHIFT
,
332 4, arizona_ng_hold_text
);
333 EXPORT_SYMBOL_GPL(arizona_ng_hold
);
335 int arizona_in_ev(struct snd_soc_dapm_widget
*w
, struct snd_kcontrol
*kcontrol
,
341 reg
= ARIZONA_ADC_DIGITAL_VOLUME_1L
+ ((w
->shift
/ 2) * 8);
343 reg
= ARIZONA_ADC_DIGITAL_VOLUME_1R
+ ((w
->shift
/ 2) * 8);
346 case SND_SOC_DAPM_POST_PMU
:
347 snd_soc_update_bits(w
->codec
, reg
, ARIZONA_IN1L_MUTE
, 0);
349 case SND_SOC_DAPM_PRE_PMD
:
350 snd_soc_update_bits(w
->codec
, reg
, ARIZONA_IN1L_MUTE
,
357 EXPORT_SYMBOL_GPL(arizona_in_ev
);
359 int arizona_out_ev(struct snd_soc_dapm_widget
*w
,
360 struct snd_kcontrol
*kcontrol
,
365 EXPORT_SYMBOL_GPL(arizona_out_ev
);
367 static unsigned int arizona_sysclk_48k_rates
[] = {
377 static unsigned int arizona_sysclk_44k1_rates
[] = {
387 static int arizona_set_opclk(struct snd_soc_codec
*codec
, unsigned int clk
,
390 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
393 int ref
, div
, refclk
;
396 case ARIZONA_CLK_OPCLK
:
397 reg
= ARIZONA_OUTPUT_SYSTEM_CLOCK
;
398 refclk
= priv
->sysclk
;
400 case ARIZONA_CLK_ASYNC_OPCLK
:
401 reg
= ARIZONA_OUTPUT_ASYNC_CLOCK
;
402 refclk
= priv
->asyncclk
;
409 rates
= arizona_sysclk_44k1_rates
;
411 rates
= arizona_sysclk_48k_rates
;
413 for (ref
= 0; ref
< ARRAY_SIZE(arizona_sysclk_48k_rates
) &&
414 rates
[ref
] <= refclk
; ref
++) {
416 while (rates
[ref
] / div
>= freq
&& div
< 32) {
417 if (rates
[ref
] / div
== freq
) {
418 dev_dbg(codec
->dev
, "Configured %dHz OPCLK\n",
420 snd_soc_update_bits(codec
, reg
,
421 ARIZONA_OPCLK_DIV_MASK
|
422 ARIZONA_OPCLK_SEL_MASK
,
424 ARIZONA_OPCLK_DIV_SHIFT
) |
432 dev_err(codec
->dev
, "Unable to generate %dHz OPCLK\n", freq
);
436 int arizona_set_sysclk(struct snd_soc_codec
*codec
, int clk_id
,
437 int source
, unsigned int freq
, int dir
)
439 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
440 struct arizona
*arizona
= priv
->arizona
;
443 unsigned int mask
= ARIZONA_SYSCLK_FREQ_MASK
| ARIZONA_SYSCLK_SRC_MASK
;
444 unsigned int val
= source
<< ARIZONA_SYSCLK_SRC_SHIFT
;
448 case ARIZONA_CLK_SYSCLK
:
450 reg
= ARIZONA_SYSTEM_CLOCK_1
;
452 mask
|= ARIZONA_SYSCLK_FRAC
;
454 case ARIZONA_CLK_ASYNCCLK
:
456 reg
= ARIZONA_ASYNC_CLOCK_1
;
457 clk
= &priv
->asyncclk
;
459 case ARIZONA_CLK_OPCLK
:
460 case ARIZONA_CLK_ASYNC_OPCLK
:
461 return arizona_set_opclk(codec
, clk_id
, freq
);
472 val
|= 1 << ARIZONA_SYSCLK_FREQ_SHIFT
;
476 val
|= 2 << ARIZONA_SYSCLK_FREQ_SHIFT
;
480 val
|= 3 << ARIZONA_SYSCLK_FREQ_SHIFT
;
484 val
|= 4 << ARIZONA_SYSCLK_FREQ_SHIFT
;
488 val
|= 5 << ARIZONA_SYSCLK_FREQ_SHIFT
;
492 val
|= 6 << ARIZONA_SYSCLK_FREQ_SHIFT
;
495 dev_dbg(arizona
->dev
, "%s cleared\n", name
);
505 val
|= ARIZONA_SYSCLK_FRAC
;
507 dev_dbg(arizona
->dev
, "%s set to %uHz", name
, freq
);
509 return regmap_update_bits(arizona
->regmap
, reg
, mask
, val
);
511 EXPORT_SYMBOL_GPL(arizona_set_sysclk
);
513 static int arizona_set_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
515 struct snd_soc_codec
*codec
= dai
->codec
;
516 int lrclk
, bclk
, mode
, base
;
518 base
= dai
->driver
->base
;
523 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
524 case SND_SOC_DAIFMT_DSP_A
:
527 case SND_SOC_DAIFMT_I2S
:
531 arizona_aif_err(dai
, "Unsupported DAI format %d\n",
532 fmt
& SND_SOC_DAIFMT_FORMAT_MASK
);
536 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
537 case SND_SOC_DAIFMT_CBS_CFS
:
539 case SND_SOC_DAIFMT_CBS_CFM
:
540 lrclk
|= ARIZONA_AIF1TX_LRCLK_MSTR
;
542 case SND_SOC_DAIFMT_CBM_CFS
:
543 bclk
|= ARIZONA_AIF1_BCLK_MSTR
;
545 case SND_SOC_DAIFMT_CBM_CFM
:
546 bclk
|= ARIZONA_AIF1_BCLK_MSTR
;
547 lrclk
|= ARIZONA_AIF1TX_LRCLK_MSTR
;
550 arizona_aif_err(dai
, "Unsupported master mode %d\n",
551 fmt
& SND_SOC_DAIFMT_MASTER_MASK
);
555 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
556 case SND_SOC_DAIFMT_NB_NF
:
558 case SND_SOC_DAIFMT_IB_IF
:
559 bclk
|= ARIZONA_AIF1_BCLK_INV
;
560 lrclk
|= ARIZONA_AIF1TX_LRCLK_INV
;
562 case SND_SOC_DAIFMT_IB_NF
:
563 bclk
|= ARIZONA_AIF1_BCLK_INV
;
565 case SND_SOC_DAIFMT_NB_IF
:
566 lrclk
|= ARIZONA_AIF1TX_LRCLK_INV
;
572 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_BCLK_CTRL
,
573 ARIZONA_AIF1_BCLK_INV
| ARIZONA_AIF1_BCLK_MSTR
,
575 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_TX_PIN_CTRL
,
576 ARIZONA_AIF1TX_LRCLK_INV
|
577 ARIZONA_AIF1TX_LRCLK_MSTR
, lrclk
);
578 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_RX_PIN_CTRL
,
579 ARIZONA_AIF1RX_LRCLK_INV
|
580 ARIZONA_AIF1RX_LRCLK_MSTR
, lrclk
);
581 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_FORMAT
,
582 ARIZONA_AIF1_FMT_MASK
, mode
);
587 static const int arizona_48k_bclk_rates
[] = {
609 static const unsigned int arizona_48k_rates
[] = {
627 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint
= {
628 .count
= ARRAY_SIZE(arizona_48k_rates
),
629 .list
= arizona_48k_rates
,
632 static const int arizona_44k1_bclk_rates
[] = {
654 static const unsigned int arizona_44k1_rates
[] = {
664 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint
= {
665 .count
= ARRAY_SIZE(arizona_44k1_rates
),
666 .list
= arizona_44k1_rates
,
669 static int arizona_sr_vals
[] = {
696 static int arizona_startup(struct snd_pcm_substream
*substream
,
697 struct snd_soc_dai
*dai
)
699 struct snd_soc_codec
*codec
= dai
->codec
;
700 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
701 struct arizona_dai_priv
*dai_priv
= &priv
->dai
[dai
->id
- 1];
702 const struct snd_pcm_hw_constraint_list
*constraint
;
703 unsigned int base_rate
;
705 switch (dai_priv
->clk
) {
706 case ARIZONA_CLK_SYSCLK
:
707 base_rate
= priv
->sysclk
;
709 case ARIZONA_CLK_ASYNCCLK
:
710 base_rate
= priv
->asyncclk
;
719 if (base_rate
% 8000)
720 constraint
= &arizona_44k1_constraint
;
722 constraint
= &arizona_48k_constraint
;
724 return snd_pcm_hw_constraint_list(substream
->runtime
, 0,
725 SNDRV_PCM_HW_PARAM_RATE
,
729 static int arizona_hw_params_rate(struct snd_pcm_substream
*substream
,
730 struct snd_pcm_hw_params
*params
,
731 struct snd_soc_dai
*dai
)
733 struct snd_soc_codec
*codec
= dai
->codec
;
734 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
735 struct arizona_dai_priv
*dai_priv
= &priv
->dai
[dai
->id
- 1];
736 int base
= dai
->driver
->base
;
740 * We will need to be more flexible than this in future,
741 * currently we use a single sample rate for SYSCLK.
743 for (i
= 0; i
< ARRAY_SIZE(arizona_sr_vals
); i
++)
744 if (arizona_sr_vals
[i
] == params_rate(params
))
746 if (i
== ARRAY_SIZE(arizona_sr_vals
)) {
747 arizona_aif_err(dai
, "Unsupported sample rate %dHz\n",
748 params_rate(params
));
753 switch (dai_priv
->clk
) {
754 case ARIZONA_CLK_SYSCLK
:
755 snd_soc_update_bits(codec
, ARIZONA_SAMPLE_RATE_1
,
756 ARIZONA_SAMPLE_RATE_1_MASK
, sr_val
);
758 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_RATE_CTRL
,
759 ARIZONA_AIF1_RATE_MASK
, 0);
761 case ARIZONA_CLK_ASYNCCLK
:
762 snd_soc_update_bits(codec
, ARIZONA_ASYNC_SAMPLE_RATE_1
,
763 ARIZONA_ASYNC_SAMPLE_RATE_MASK
, sr_val
);
765 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_RATE_CTRL
,
766 ARIZONA_AIF1_RATE_MASK
,
767 8 << ARIZONA_AIF1_RATE_SHIFT
);
770 arizona_aif_err(dai
, "Invalid clock %d\n", dai_priv
->clk
);
777 static int arizona_hw_params(struct snd_pcm_substream
*substream
,
778 struct snd_pcm_hw_params
*params
,
779 struct snd_soc_dai
*dai
)
781 struct snd_soc_codec
*codec
= dai
->codec
;
782 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
783 struct arizona
*arizona
= priv
->arizona
;
784 int base
= dai
->driver
->base
;
787 int chan_limit
= arizona
->pdata
.max_channels_clocked
[dai
->id
- 1];
788 int bclk
, lrclk
, wl
, frame
, bclk_target
;
790 if (params_rate(params
) % 8000)
791 rates
= &arizona_44k1_bclk_rates
[0];
793 rates
= &arizona_48k_bclk_rates
[0];
795 bclk_target
= snd_soc_params_to_bclk(params
);
796 if (chan_limit
&& chan_limit
< params_channels(params
)) {
797 arizona_aif_dbg(dai
, "Limiting to %d channels\n", chan_limit
);
798 bclk_target
/= params_channels(params
);
799 bclk_target
*= chan_limit
;
802 for (i
= 0; i
< ARRAY_SIZE(arizona_44k1_bclk_rates
); i
++) {
803 if (rates
[i
] >= bclk_target
&&
804 rates
[i
] % params_rate(params
) == 0) {
809 if (i
== ARRAY_SIZE(arizona_44k1_bclk_rates
)) {
810 arizona_aif_err(dai
, "Unsupported sample rate %dHz\n",
811 params_rate(params
));
815 lrclk
= rates
[bclk
] / params_rate(params
);
817 arizona_aif_dbg(dai
, "BCLK %dHz LRCLK %dHz\n",
818 rates
[bclk
], rates
[bclk
] / lrclk
);
820 wl
= snd_pcm_format_width(params_format(params
));
821 frame
= wl
<< ARIZONA_AIF1TX_WL_SHIFT
| wl
;
823 ret
= arizona_hw_params_rate(substream
, params
, dai
);
827 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_BCLK_CTRL
,
828 ARIZONA_AIF1_BCLK_FREQ_MASK
, bclk
);
829 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_TX_BCLK_RATE
,
830 ARIZONA_AIF1TX_BCPF_MASK
, lrclk
);
831 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_RX_BCLK_RATE
,
832 ARIZONA_AIF1RX_BCPF_MASK
, lrclk
);
833 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_FRAME_CTRL_1
,
834 ARIZONA_AIF1TX_WL_MASK
|
835 ARIZONA_AIF1TX_SLOT_LEN_MASK
, frame
);
836 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_FRAME_CTRL_2
,
837 ARIZONA_AIF1RX_WL_MASK
|
838 ARIZONA_AIF1RX_SLOT_LEN_MASK
, frame
);
843 static const char *arizona_dai_clk_str(int clk_id
)
846 case ARIZONA_CLK_SYSCLK
:
848 case ARIZONA_CLK_ASYNCCLK
:
851 return "Unknown clock";
855 static int arizona_dai_set_sysclk(struct snd_soc_dai
*dai
,
856 int clk_id
, unsigned int freq
, int dir
)
858 struct snd_soc_codec
*codec
= dai
->codec
;
859 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
860 struct arizona_dai_priv
*dai_priv
= &priv
->dai
[dai
->id
- 1];
861 struct snd_soc_dapm_route routes
[2];
864 case ARIZONA_CLK_SYSCLK
:
865 case ARIZONA_CLK_ASYNCCLK
:
871 if (clk_id
== dai_priv
->clk
)
875 dev_err(codec
->dev
, "Can't change clock on active DAI %d\n",
880 dev_dbg(codec
->dev
, "Setting AIF%d to %s\n", dai
->id
+ 1,
881 arizona_dai_clk_str(clk_id
));
883 memset(&routes
, 0, sizeof(routes
));
884 routes
[0].sink
= dai
->driver
->capture
.stream_name
;
885 routes
[1].sink
= dai
->driver
->playback
.stream_name
;
887 routes
[0].source
= arizona_dai_clk_str(dai_priv
->clk
);
888 routes
[1].source
= arizona_dai_clk_str(dai_priv
->clk
);
889 snd_soc_dapm_del_routes(&codec
->dapm
, routes
, ARRAY_SIZE(routes
));
891 routes
[0].source
= arizona_dai_clk_str(clk_id
);
892 routes
[1].source
= arizona_dai_clk_str(clk_id
);
893 snd_soc_dapm_add_routes(&codec
->dapm
, routes
, ARRAY_SIZE(routes
));
895 dai_priv
->clk
= clk_id
;
897 return snd_soc_dapm_sync(&codec
->dapm
);
900 static int arizona_set_tristate(struct snd_soc_dai
*dai
, int tristate
)
902 struct snd_soc_codec
*codec
= dai
->codec
;
903 int base
= dai
->driver
->base
;
907 reg
= ARIZONA_AIF1_TRI
;
911 return snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_RATE_CTRL
,
912 ARIZONA_AIF1_TRI
, reg
);
915 const struct snd_soc_dai_ops arizona_dai_ops
= {
916 .startup
= arizona_startup
,
917 .set_fmt
= arizona_set_fmt
,
918 .hw_params
= arizona_hw_params
,
919 .set_sysclk
= arizona_dai_set_sysclk
,
920 .set_tristate
= arizona_set_tristate
,
922 EXPORT_SYMBOL_GPL(arizona_dai_ops
);
924 int arizona_init_dai(struct arizona_priv
*priv
, int id
)
926 struct arizona_dai_priv
*dai_priv
= &priv
->dai
[id
];
928 dai_priv
->clk
= ARIZONA_CLK_SYSCLK
;
932 EXPORT_SYMBOL_GPL(arizona_init_dai
);
934 static irqreturn_t
arizona_fll_clock_ok(int irq
, void *data
)
936 struct arizona_fll
*fll
= data
;
938 arizona_fll_dbg(fll
, "clock OK\n");
952 { 64000, 128000, 3, 8 },
953 { 128000, 256000, 2, 4 },
954 { 256000, 1000000, 1, 2 },
955 { 1000000, 13500000, 0, 1 },
958 struct arizona_fll_cfg
{
967 static int arizona_calc_fll(struct arizona_fll
*fll
,
968 struct arizona_fll_cfg
*cfg
,
972 unsigned int target
, div
, gcd_fll
;
975 arizona_fll_dbg(fll
, "Fref=%u Fout=%u\n", Fref
, Fout
);
977 /* Fref must be <=13.5MHz */
980 while ((Fref
/ div
) > 13500000) {
986 "Can't scale %dMHz in to <=13.5MHz\n",
992 /* Apply the division for our remaining calculations */
995 /* Fvco should be over the targt; don't check the upper bound */
997 while (Fout
* div
< 90000000 * fll
->vco_mult
) {
1000 arizona_fll_err(fll
, "No FLL_OUTDIV for Fout=%uHz\n",
1005 target
= Fout
* div
/ fll
->vco_mult
;
1008 arizona_fll_dbg(fll
, "Fvco=%dHz\n", target
);
1010 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1011 for (i
= 0; i
< ARRAY_SIZE(fll_fratios
); i
++) {
1012 if (fll_fratios
[i
].min
<= Fref
&& Fref
<= fll_fratios
[i
].max
) {
1013 cfg
->fratio
= fll_fratios
[i
].fratio
;
1014 ratio
= fll_fratios
[i
].ratio
;
1018 if (i
== ARRAY_SIZE(fll_fratios
)) {
1019 arizona_fll_err(fll
, "Unable to find FRATIO for Fref=%uHz\n",
1024 cfg
->n
= target
/ (ratio
* Fref
);
1026 if (target
% (ratio
* Fref
)) {
1027 gcd_fll
= gcd(target
, ratio
* Fref
);
1028 arizona_fll_dbg(fll
, "GCD=%u\n", gcd_fll
);
1030 cfg
->theta
= (target
- (cfg
->n
* ratio
* Fref
))
1032 cfg
->lambda
= (ratio
* Fref
) / gcd_fll
;
1038 /* Round down to 16bit range with cost of accuracy lost.
1039 * Denominator must be bigger than numerator so we only
1042 while (cfg
->lambda
>= (1 << 16)) {
1047 arizona_fll_dbg(fll
, "N=%x THETA=%x LAMBDA=%x\n",
1048 cfg
->n
, cfg
->theta
, cfg
->lambda
);
1049 arizona_fll_dbg(fll
, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
1050 cfg
->fratio
, cfg
->fratio
, cfg
->outdiv
, cfg
->refdiv
);
1056 static void arizona_apply_fll(struct arizona
*arizona
, unsigned int base
,
1057 struct arizona_fll_cfg
*cfg
, int source
)
1059 regmap_update_bits(arizona
->regmap
, base
+ 3,
1060 ARIZONA_FLL1_THETA_MASK
, cfg
->theta
);
1061 regmap_update_bits(arizona
->regmap
, base
+ 4,
1062 ARIZONA_FLL1_LAMBDA_MASK
, cfg
->lambda
);
1063 regmap_update_bits(arizona
->regmap
, base
+ 5,
1064 ARIZONA_FLL1_FRATIO_MASK
,
1065 cfg
->fratio
<< ARIZONA_FLL1_FRATIO_SHIFT
);
1066 regmap_update_bits(arizona
->regmap
, base
+ 6,
1067 ARIZONA_FLL1_CLK_REF_DIV_MASK
|
1068 ARIZONA_FLL1_CLK_REF_SRC_MASK
,
1069 cfg
->refdiv
<< ARIZONA_FLL1_CLK_REF_DIV_SHIFT
|
1070 source
<< ARIZONA_FLL1_CLK_REF_SRC_SHIFT
);
1072 regmap_update_bits(arizona
->regmap
, base
+ 2,
1073 ARIZONA_FLL1_CTRL_UPD
| ARIZONA_FLL1_N_MASK
,
1074 ARIZONA_FLL1_CTRL_UPD
| cfg
->n
);
1077 int arizona_set_fll(struct arizona_fll
*fll
, int source
,
1078 unsigned int Fref
, unsigned int Fout
)
1080 struct arizona
*arizona
= fll
->arizona
;
1081 struct arizona_fll_cfg cfg
, sync
;
1082 unsigned int reg
, val
;
1087 if (fll
->fref
== Fref
&& fll
->fout
== Fout
)
1090 ret
= regmap_read(arizona
->regmap
, fll
->base
+ 1, ®
);
1092 arizona_fll_err(fll
, "Failed to read current state: %d\n",
1096 ena
= reg
& ARIZONA_FLL1_ENA
;
1099 /* Do we have a 32kHz reference? */
1100 regmap_read(arizona
->regmap
, ARIZONA_CLOCK_32K_1
, &val
);
1101 switch (val
& ARIZONA_CLK_32K_SRC_MASK
) {
1102 case ARIZONA_CLK_SRC_MCLK1
:
1103 case ARIZONA_CLK_SRC_MCLK2
:
1104 syncsrc
= val
& ARIZONA_CLK_32K_SRC_MASK
;
1110 if (source
== syncsrc
)
1114 ret
= arizona_calc_fll(fll
, &sync
, Fref
, Fout
);
1118 ret
= arizona_calc_fll(fll
, &cfg
, 32768, Fout
);
1122 ret
= arizona_calc_fll(fll
, &cfg
, Fref
, Fout
);
1127 regmap_update_bits(arizona
->regmap
, fll
->base
+ 1,
1128 ARIZONA_FLL1_ENA
, 0);
1129 regmap_update_bits(arizona
->regmap
, fll
->base
+ 0x11,
1130 ARIZONA_FLL1_SYNC_ENA
, 0);
1133 pm_runtime_put_autosuspend(arizona
->dev
);
1141 regmap_update_bits(arizona
->regmap
, fll
->base
+ 5,
1142 ARIZONA_FLL1_OUTDIV_MASK
,
1143 cfg
.outdiv
<< ARIZONA_FLL1_OUTDIV_SHIFT
);
1146 arizona_apply_fll(arizona
, fll
->base
, &cfg
, syncsrc
);
1147 arizona_apply_fll(arizona
, fll
->base
+ 0x10, &sync
, source
);
1149 arizona_apply_fll(arizona
, fll
->base
, &cfg
, source
);
1153 pm_runtime_get(arizona
->dev
);
1155 /* Clear any pending completions */
1156 try_wait_for_completion(&fll
->ok
);
1158 regmap_update_bits(arizona
->regmap
, fll
->base
+ 1,
1159 ARIZONA_FLL1_ENA
, ARIZONA_FLL1_ENA
);
1161 regmap_update_bits(arizona
->regmap
, fll
->base
+ 0x11,
1162 ARIZONA_FLL1_SYNC_ENA
,
1163 ARIZONA_FLL1_SYNC_ENA
);
1165 ret
= wait_for_completion_timeout(&fll
->ok
,
1166 msecs_to_jiffies(250));
1168 arizona_fll_warn(fll
, "Timed out waiting for lock\n");
1175 EXPORT_SYMBOL_GPL(arizona_set_fll
);
1177 int arizona_init_fll(struct arizona
*arizona
, int id
, int base
, int lock_irq
,
1178 int ok_irq
, struct arizona_fll
*fll
)
1182 init_completion(&fll
->ok
);
1186 fll
->arizona
= arizona
;
1188 snprintf(fll
->lock_name
, sizeof(fll
->lock_name
), "FLL%d lock", id
);
1189 snprintf(fll
->clock_ok_name
, sizeof(fll
->clock_ok_name
),
1190 "FLL%d clock OK", id
);
1192 ret
= arizona_request_irq(arizona
, ok_irq
, fll
->clock_ok_name
,
1193 arizona_fll_clock_ok
, fll
);
1195 dev_err(arizona
->dev
, "Failed to get FLL%d clock OK IRQ: %d\n",
1199 regmap_update_bits(arizona
->regmap
, fll
->base
+ 1,
1200 ARIZONA_FLL1_FREERUN
, 0);
1204 EXPORT_SYMBOL_GPL(arizona_init_fll
);
1207 * arizona_set_output_mode - Set the mode of the specified output
1209 * @codec: Device to configure
1210 * @output: Output number
1211 * @diff: True to set the output to differential mode
1213 * Some systems use external analogue switches to connect more
1214 * analogue devices to the CODEC than are supported by the device. In
1215 * some systems this requires changing the switched output from single
1216 * ended to differential mode dynamically at runtime, an operation
1217 * supported using this function.
1219 * Most systems have a single static configuration and should use
1220 * platform data instead.
1222 int arizona_set_output_mode(struct snd_soc_codec
*codec
, int output
, bool diff
)
1224 unsigned int reg
, val
;
1226 if (output
< 1 || output
> 6)
1229 reg
= ARIZONA_OUTPUT_PATH_CONFIG_1L
+ (output
- 1) * 8;
1232 val
= ARIZONA_OUT1_MONO
;
1236 return snd_soc_update_bits(codec
, reg
, ARIZONA_OUT1_MONO
, val
);
1238 EXPORT_SYMBOL_GPL(arizona_set_output_mode
);
1240 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
1241 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1242 MODULE_LICENSE("GPL");