2 * arizona.c - Wolfson Arizona class device shared support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/gcd.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/tlv.h>
21 #include <linux/mfd/arizona/core.h>
22 #include <linux/mfd/arizona/registers.h>
26 #define ARIZONA_AIF_BCLK_CTRL 0x00
27 #define ARIZONA_AIF_TX_PIN_CTRL 0x01
28 #define ARIZONA_AIF_RX_PIN_CTRL 0x02
29 #define ARIZONA_AIF_RATE_CTRL 0x03
30 #define ARIZONA_AIF_FORMAT 0x04
31 #define ARIZONA_AIF_TX_BCLK_RATE 0x05
32 #define ARIZONA_AIF_RX_BCLK_RATE 0x06
33 #define ARIZONA_AIF_FRAME_CTRL_1 0x07
34 #define ARIZONA_AIF_FRAME_CTRL_2 0x08
35 #define ARIZONA_AIF_FRAME_CTRL_3 0x09
36 #define ARIZONA_AIF_FRAME_CTRL_4 0x0A
37 #define ARIZONA_AIF_FRAME_CTRL_5 0x0B
38 #define ARIZONA_AIF_FRAME_CTRL_6 0x0C
39 #define ARIZONA_AIF_FRAME_CTRL_7 0x0D
40 #define ARIZONA_AIF_FRAME_CTRL_8 0x0E
41 #define ARIZONA_AIF_FRAME_CTRL_9 0x0F
42 #define ARIZONA_AIF_FRAME_CTRL_10 0x10
43 #define ARIZONA_AIF_FRAME_CTRL_11 0x11
44 #define ARIZONA_AIF_FRAME_CTRL_12 0x12
45 #define ARIZONA_AIF_FRAME_CTRL_13 0x13
46 #define ARIZONA_AIF_FRAME_CTRL_14 0x14
47 #define ARIZONA_AIF_FRAME_CTRL_15 0x15
48 #define ARIZONA_AIF_FRAME_CTRL_16 0x16
49 #define ARIZONA_AIF_FRAME_CTRL_17 0x17
50 #define ARIZONA_AIF_FRAME_CTRL_18 0x18
51 #define ARIZONA_AIF_TX_ENABLES 0x19
52 #define ARIZONA_AIF_RX_ENABLES 0x1A
53 #define ARIZONA_AIF_FORCE_WRITE 0x1B
55 #define ARIZONA_FLL_VCO_CORNER 141900000
56 #define ARIZONA_FLL_MAX_FREF 13500000
57 #define ARIZONA_FLL_MIN_FVCO 90000000
58 #define ARIZONA_FLL_MAX_FRATIO 16
59 #define ARIZONA_FLL_MAX_REFDIV 8
60 #define ARIZONA_FLL_MIN_OUTDIV 2
61 #define ARIZONA_FLL_MAX_OUTDIV 7
63 #define ARIZONA_FMT_DSP_MODE_A 0
64 #define ARIZONA_FMT_DSP_MODE_B 1
65 #define ARIZONA_FMT_I2S_MODE 2
66 #define ARIZONA_FMT_LEFT_JUSTIFIED_MODE 3
68 #define arizona_fll_err(_fll, fmt, ...) \
69 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
70 #define arizona_fll_warn(_fll, fmt, ...) \
71 dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
72 #define arizona_fll_dbg(_fll, fmt, ...) \
73 dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
75 #define arizona_aif_err(_dai, fmt, ...) \
76 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
77 #define arizona_aif_warn(_dai, fmt, ...) \
78 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
79 #define arizona_aif_dbg(_dai, fmt, ...) \
80 dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
82 static int arizona_spk_ev(struct snd_soc_dapm_widget
*w
,
83 struct snd_kcontrol
*kcontrol
,
86 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
87 struct arizona
*arizona
= dev_get_drvdata(codec
->dev
->parent
);
88 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
89 bool manual_ena
= false;
92 switch (arizona
->type
) {
94 switch (arizona
->rev
) {
106 case SND_SOC_DAPM_PRE_PMU
:
107 if (!priv
->spk_ena
&& manual_ena
) {
108 regmap_write_async(arizona
->regmap
, 0x4f5, 0x25a);
109 priv
->spk_ena_pending
= true;
112 case SND_SOC_DAPM_POST_PMU
:
113 val
= snd_soc_read(codec
, ARIZONA_INTERRUPT_RAW_STATUS_3
);
114 if (val
& ARIZONA_SPK_OVERHEAT_STS
) {
115 dev_crit(arizona
->dev
,
116 "Speaker not enabled due to temperature\n");
120 regmap_update_bits_async(arizona
->regmap
,
121 ARIZONA_OUTPUT_ENABLES_1
,
122 1 << w
->shift
, 1 << w
->shift
);
124 if (priv
->spk_ena_pending
) {
126 regmap_write_async(arizona
->regmap
, 0x4f5, 0xda);
127 priv
->spk_ena_pending
= false;
131 case SND_SOC_DAPM_PRE_PMD
:
135 regmap_write_async(arizona
->regmap
,
139 regmap_update_bits_async(arizona
->regmap
,
140 ARIZONA_OUTPUT_ENABLES_1
,
143 case SND_SOC_DAPM_POST_PMD
:
146 regmap_write_async(arizona
->regmap
,
157 static irqreturn_t
arizona_thermal_warn(int irq
, void *data
)
159 struct arizona
*arizona
= data
;
163 ret
= regmap_read(arizona
->regmap
, ARIZONA_INTERRUPT_RAW_STATUS_3
,
166 dev_err(arizona
->dev
, "Failed to read thermal status: %d\n",
168 } else if (val
& ARIZONA_SPK_OVERHEAT_WARN_STS
) {
169 dev_crit(arizona
->dev
, "Thermal warning\n");
175 static irqreturn_t
arizona_thermal_shutdown(int irq
, void *data
)
177 struct arizona
*arizona
= data
;
181 ret
= regmap_read(arizona
->regmap
, ARIZONA_INTERRUPT_RAW_STATUS_3
,
184 dev_err(arizona
->dev
, "Failed to read thermal status: %d\n",
186 } else if (val
& ARIZONA_SPK_OVERHEAT_STS
) {
187 dev_crit(arizona
->dev
, "Thermal shutdown\n");
188 ret
= regmap_update_bits(arizona
->regmap
,
189 ARIZONA_OUTPUT_ENABLES_1
,
191 ARIZONA_OUT4R_ENA
, 0);
193 dev_crit(arizona
->dev
,
194 "Failed to disable speaker outputs: %d\n",
201 static const struct snd_soc_dapm_widget arizona_spkl
=
202 SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM
,
203 ARIZONA_OUT4L_ENA_SHIFT
, 0, NULL
, 0, arizona_spk_ev
,
204 SND_SOC_DAPM_PRE_PMD
| SND_SOC_DAPM_POST_PMU
);
206 static const struct snd_soc_dapm_widget arizona_spkr
=
207 SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM
,
208 ARIZONA_OUT4R_ENA_SHIFT
, 0, NULL
, 0, arizona_spk_ev
,
209 SND_SOC_DAPM_PRE_PMD
| SND_SOC_DAPM_POST_PMU
);
211 int arizona_init_spk(struct snd_soc_codec
*codec
)
213 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
214 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
215 struct arizona
*arizona
= priv
->arizona
;
218 ret
= snd_soc_dapm_new_controls(dapm
, &arizona_spkl
, 1);
222 switch (arizona
->type
) {
226 ret
= snd_soc_dapm_new_controls(dapm
, &arizona_spkr
, 1);
232 ret
= arizona_request_irq(arizona
, ARIZONA_IRQ_SPK_OVERHEAT_WARN
,
233 "Thermal warning", arizona_thermal_warn
,
236 dev_err(arizona
->dev
,
237 "Failed to get thermal warning IRQ: %d\n",
240 ret
= arizona_request_irq(arizona
, ARIZONA_IRQ_SPK_OVERHEAT
,
241 "Thermal shutdown", arizona_thermal_shutdown
,
244 dev_err(arizona
->dev
,
245 "Failed to get thermal shutdown IRQ: %d\n",
250 EXPORT_SYMBOL_GPL(arizona_init_spk
);
252 static const struct snd_soc_dapm_route arizona_mono_routes
[] = {
253 { "OUT1R", NULL
, "OUT1L" },
254 { "OUT2R", NULL
, "OUT2L" },
255 { "OUT3R", NULL
, "OUT3L" },
256 { "OUT4R", NULL
, "OUT4L" },
257 { "OUT5R", NULL
, "OUT5L" },
258 { "OUT6R", NULL
, "OUT6L" },
261 int arizona_init_mono(struct snd_soc_codec
*codec
)
263 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
264 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
265 struct arizona
*arizona
= priv
->arizona
;
268 for (i
= 0; i
< ARIZONA_MAX_OUTPUT
; ++i
) {
269 if (arizona
->pdata
.out_mono
[i
])
270 snd_soc_dapm_add_routes(dapm
,
271 &arizona_mono_routes
[i
], 1);
276 EXPORT_SYMBOL_GPL(arizona_init_mono
);
278 int arizona_init_gpio(struct snd_soc_codec
*codec
)
280 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
281 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
282 struct arizona
*arizona
= priv
->arizona
;
285 switch (arizona
->type
) {
288 snd_soc_dapm_disable_pin(dapm
, "DRC2 Signal Activity");
294 snd_soc_dapm_disable_pin(dapm
, "DRC1 Signal Activity");
296 for (i
= 0; i
< ARRAY_SIZE(arizona
->pdata
.gpio_defaults
); i
++) {
297 switch (arizona
->pdata
.gpio_defaults
[i
] & ARIZONA_GPN_FN_MASK
) {
298 case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT
:
299 snd_soc_dapm_enable_pin(dapm
, "DRC1 Signal Activity");
301 case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT
:
302 snd_soc_dapm_enable_pin(dapm
, "DRC2 Signal Activity");
311 EXPORT_SYMBOL_GPL(arizona_init_gpio
);
313 const char *arizona_mixer_texts
[ARIZONA_NUM_MIXER_INPUTS
] = {
419 EXPORT_SYMBOL_GPL(arizona_mixer_texts
);
421 int arizona_mixer_values
[ARIZONA_NUM_MIXER_INPUTS
] = {
428 0x0c, /* Noise mixer */
429 0x0d, /* Comfort noise */
502 0xa0, /* ISRC1INT1 */
506 0xa4, /* ISRC1DEC1 */
510 0xa8, /* ISRC2DEC1 */
514 0xac, /* ISRC2INT1 */
518 0xb0, /* ISRC3DEC1 */
522 0xb4, /* ISRC3INT1 */
527 EXPORT_SYMBOL_GPL(arizona_mixer_values
);
529 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv
, -3200, 100, 0);
530 EXPORT_SYMBOL_GPL(arizona_mixer_tlv
);
532 const char * const arizona_sample_rate_text
[ARIZONA_SAMPLE_RATE_ENUM_SIZE
] = {
533 "12kHz", "24kHz", "48kHz", "96kHz", "192kHz",
534 "11.025kHz", "22.05kHz", "44.1kHz", "88.2kHz", "176.4kHz",
535 "4kHz", "8kHz", "16kHz", "32kHz",
537 EXPORT_SYMBOL_GPL(arizona_sample_rate_text
);
539 const unsigned int arizona_sample_rate_val
[ARIZONA_SAMPLE_RATE_ENUM_SIZE
] = {
540 0x01, 0x02, 0x03, 0x04, 0x05, 0x09, 0x0A, 0x0B, 0x0C, 0x0D,
541 0x10, 0x11, 0x12, 0x13,
543 EXPORT_SYMBOL_GPL(arizona_sample_rate_val
);
545 const char *arizona_sample_rate_val_to_name(unsigned int rate_val
)
549 for (i
= 0; i
< ARRAY_SIZE(arizona_sample_rate_val
); ++i
) {
550 if (arizona_sample_rate_val
[i
] == rate_val
)
551 return arizona_sample_rate_text
[i
];
556 EXPORT_SYMBOL_GPL(arizona_sample_rate_val_to_name
);
558 const char *arizona_rate_text
[ARIZONA_RATE_ENUM_SIZE
] = {
559 "SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate",
561 EXPORT_SYMBOL_GPL(arizona_rate_text
);
563 const int arizona_rate_val
[ARIZONA_RATE_ENUM_SIZE
] = {
566 EXPORT_SYMBOL_GPL(arizona_rate_val
);
569 const struct soc_enum arizona_isrc_fsh
[] = {
570 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_1
,
571 ARIZONA_ISRC1_FSH_SHIFT
, 0xf,
572 ARIZONA_RATE_ENUM_SIZE
,
573 arizona_rate_text
, arizona_rate_val
),
574 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_1
,
575 ARIZONA_ISRC2_FSH_SHIFT
, 0xf,
576 ARIZONA_RATE_ENUM_SIZE
,
577 arizona_rate_text
, arizona_rate_val
),
578 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_1
,
579 ARIZONA_ISRC3_FSH_SHIFT
, 0xf,
580 ARIZONA_RATE_ENUM_SIZE
,
581 arizona_rate_text
, arizona_rate_val
),
583 EXPORT_SYMBOL_GPL(arizona_isrc_fsh
);
585 const struct soc_enum arizona_isrc_fsl
[] = {
586 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2
,
587 ARIZONA_ISRC1_FSL_SHIFT
, 0xf,
588 ARIZONA_RATE_ENUM_SIZE
,
589 arizona_rate_text
, arizona_rate_val
),
590 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2
,
591 ARIZONA_ISRC2_FSL_SHIFT
, 0xf,
592 ARIZONA_RATE_ENUM_SIZE
,
593 arizona_rate_text
, arizona_rate_val
),
594 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2
,
595 ARIZONA_ISRC3_FSL_SHIFT
, 0xf,
596 ARIZONA_RATE_ENUM_SIZE
,
597 arizona_rate_text
, arizona_rate_val
),
599 EXPORT_SYMBOL_GPL(arizona_isrc_fsl
);
601 const struct soc_enum arizona_asrc_rate1
=
602 SOC_VALUE_ENUM_SINGLE(ARIZONA_ASRC_RATE1
,
603 ARIZONA_ASRC_RATE1_SHIFT
, 0xf,
604 ARIZONA_RATE_ENUM_SIZE
- 1,
605 arizona_rate_text
, arizona_rate_val
);
606 EXPORT_SYMBOL_GPL(arizona_asrc_rate1
);
608 static const char *arizona_vol_ramp_text
[] = {
609 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
610 "15ms/6dB", "30ms/6dB",
613 SOC_ENUM_SINGLE_DECL(arizona_in_vd_ramp
,
614 ARIZONA_INPUT_VOLUME_RAMP
,
615 ARIZONA_IN_VD_RAMP_SHIFT
,
616 arizona_vol_ramp_text
);
617 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp
);
619 SOC_ENUM_SINGLE_DECL(arizona_in_vi_ramp
,
620 ARIZONA_INPUT_VOLUME_RAMP
,
621 ARIZONA_IN_VI_RAMP_SHIFT
,
622 arizona_vol_ramp_text
);
623 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp
);
625 SOC_ENUM_SINGLE_DECL(arizona_out_vd_ramp
,
626 ARIZONA_OUTPUT_VOLUME_RAMP
,
627 ARIZONA_OUT_VD_RAMP_SHIFT
,
628 arizona_vol_ramp_text
);
629 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp
);
631 SOC_ENUM_SINGLE_DECL(arizona_out_vi_ramp
,
632 ARIZONA_OUTPUT_VOLUME_RAMP
,
633 ARIZONA_OUT_VI_RAMP_SHIFT
,
634 arizona_vol_ramp_text
);
635 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp
);
637 static const char *arizona_lhpf_mode_text
[] = {
638 "Low-pass", "High-pass"
641 SOC_ENUM_SINGLE_DECL(arizona_lhpf1_mode
,
643 ARIZONA_LHPF1_MODE_SHIFT
,
644 arizona_lhpf_mode_text
);
645 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode
);
647 SOC_ENUM_SINGLE_DECL(arizona_lhpf2_mode
,
649 ARIZONA_LHPF2_MODE_SHIFT
,
650 arizona_lhpf_mode_text
);
651 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode
);
653 SOC_ENUM_SINGLE_DECL(arizona_lhpf3_mode
,
655 ARIZONA_LHPF3_MODE_SHIFT
,
656 arizona_lhpf_mode_text
);
657 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode
);
659 SOC_ENUM_SINGLE_DECL(arizona_lhpf4_mode
,
661 ARIZONA_LHPF4_MODE_SHIFT
,
662 arizona_lhpf_mode_text
);
663 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode
);
665 static const char *arizona_ng_hold_text
[] = {
666 "30ms", "120ms", "250ms", "500ms",
669 SOC_ENUM_SINGLE_DECL(arizona_ng_hold
,
670 ARIZONA_NOISE_GATE_CONTROL
,
671 ARIZONA_NGATE_HOLD_SHIFT
,
672 arizona_ng_hold_text
);
673 EXPORT_SYMBOL_GPL(arizona_ng_hold
);
675 static const char * const arizona_in_hpf_cut_text
[] = {
676 "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz"
679 SOC_ENUM_SINGLE_DECL(arizona_in_hpf_cut_enum
,
681 ARIZONA_IN_HPF_CUT_SHIFT
,
682 arizona_in_hpf_cut_text
);
683 EXPORT_SYMBOL_GPL(arizona_in_hpf_cut_enum
);
685 static const char * const arizona_in_dmic_osr_text
[] = {
686 "1.536MHz", "3.072MHz", "6.144MHz", "768kHz",
689 const struct soc_enum arizona_in_dmic_osr
[] = {
690 SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL
, ARIZONA_IN1_OSR_SHIFT
,
691 ARRAY_SIZE(arizona_in_dmic_osr_text
),
692 arizona_in_dmic_osr_text
),
693 SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL
, ARIZONA_IN2_OSR_SHIFT
,
694 ARRAY_SIZE(arizona_in_dmic_osr_text
),
695 arizona_in_dmic_osr_text
),
696 SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL
, ARIZONA_IN3_OSR_SHIFT
,
697 ARRAY_SIZE(arizona_in_dmic_osr_text
),
698 arizona_in_dmic_osr_text
),
699 SOC_ENUM_SINGLE(ARIZONA_IN4L_CONTROL
, ARIZONA_IN4_OSR_SHIFT
,
700 ARRAY_SIZE(arizona_in_dmic_osr_text
),
701 arizona_in_dmic_osr_text
),
703 EXPORT_SYMBOL_GPL(arizona_in_dmic_osr
);
705 static void arizona_in_set_vu(struct snd_soc_codec
*codec
, int ena
)
707 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
716 for (i
= 0; i
< priv
->num_inputs
; i
++)
717 snd_soc_update_bits(codec
,
718 ARIZONA_ADC_DIGITAL_VOLUME_1L
+ (i
* 4),
722 bool arizona_input_analog(struct snd_soc_codec
*codec
, int shift
)
724 unsigned int reg
= ARIZONA_IN1L_CONTROL
+ ((shift
/ 2) * 8);
725 unsigned int val
= snd_soc_read(codec
, reg
);
727 return !(val
& ARIZONA_IN1_MODE_MASK
);
729 EXPORT_SYMBOL_GPL(arizona_input_analog
);
731 int arizona_in_ev(struct snd_soc_dapm_widget
*w
, struct snd_kcontrol
*kcontrol
,
734 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
735 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
739 reg
= ARIZONA_ADC_DIGITAL_VOLUME_1L
+ ((w
->shift
/ 2) * 8);
741 reg
= ARIZONA_ADC_DIGITAL_VOLUME_1R
+ ((w
->shift
/ 2) * 8);
744 case SND_SOC_DAPM_PRE_PMU
:
747 case SND_SOC_DAPM_POST_PMU
:
748 snd_soc_update_bits(codec
, reg
, ARIZONA_IN1L_MUTE
, 0);
750 /* If this is the last input pending then allow VU */
752 if (priv
->in_pending
== 0) {
754 arizona_in_set_vu(codec
, 1);
757 case SND_SOC_DAPM_PRE_PMD
:
758 snd_soc_update_bits(codec
, reg
,
759 ARIZONA_IN1L_MUTE
| ARIZONA_IN_VU
,
760 ARIZONA_IN1L_MUTE
| ARIZONA_IN_VU
);
762 case SND_SOC_DAPM_POST_PMD
:
763 /* Disable volume updates if no inputs are enabled */
764 reg
= snd_soc_read(codec
, ARIZONA_INPUT_ENABLES
);
766 arizona_in_set_vu(codec
, 0);
774 EXPORT_SYMBOL_GPL(arizona_in_ev
);
776 int arizona_out_ev(struct snd_soc_dapm_widget
*w
,
777 struct snd_kcontrol
*kcontrol
,
780 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
781 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
784 case SND_SOC_DAPM_PRE_PMU
:
786 case ARIZONA_OUT1L_ENA_SHIFT
:
787 case ARIZONA_OUT1R_ENA_SHIFT
:
788 case ARIZONA_OUT2L_ENA_SHIFT
:
789 case ARIZONA_OUT2R_ENA_SHIFT
:
790 case ARIZONA_OUT3L_ENA_SHIFT
:
791 case ARIZONA_OUT3R_ENA_SHIFT
:
792 priv
->out_up_pending
++;
793 priv
->out_up_delay
+= 17;
799 case SND_SOC_DAPM_POST_PMU
:
801 case ARIZONA_OUT1L_ENA_SHIFT
:
802 case ARIZONA_OUT1R_ENA_SHIFT
:
803 case ARIZONA_OUT2L_ENA_SHIFT
:
804 case ARIZONA_OUT2R_ENA_SHIFT
:
805 case ARIZONA_OUT3L_ENA_SHIFT
:
806 case ARIZONA_OUT3R_ENA_SHIFT
:
807 priv
->out_up_pending
--;
808 if (!priv
->out_up_pending
) {
809 msleep(priv
->out_up_delay
);
810 priv
->out_up_delay
= 0;
818 case SND_SOC_DAPM_PRE_PMD
:
820 case ARIZONA_OUT1L_ENA_SHIFT
:
821 case ARIZONA_OUT1R_ENA_SHIFT
:
822 case ARIZONA_OUT2L_ENA_SHIFT
:
823 case ARIZONA_OUT2R_ENA_SHIFT
:
824 case ARIZONA_OUT3L_ENA_SHIFT
:
825 case ARIZONA_OUT3R_ENA_SHIFT
:
826 priv
->out_down_pending
++;
827 priv
->out_down_delay
++;
833 case SND_SOC_DAPM_POST_PMD
:
835 case ARIZONA_OUT1L_ENA_SHIFT
:
836 case ARIZONA_OUT1R_ENA_SHIFT
:
837 case ARIZONA_OUT2L_ENA_SHIFT
:
838 case ARIZONA_OUT2R_ENA_SHIFT
:
839 case ARIZONA_OUT3L_ENA_SHIFT
:
840 case ARIZONA_OUT3R_ENA_SHIFT
:
841 priv
->out_down_pending
--;
842 if (!priv
->out_down_pending
) {
843 msleep(priv
->out_down_delay
);
844 priv
->out_down_delay
= 0;
857 EXPORT_SYMBOL_GPL(arizona_out_ev
);
859 int arizona_hp_ev(struct snd_soc_dapm_widget
*w
,
860 struct snd_kcontrol
*kcontrol
,
863 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
864 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
865 struct arizona
*arizona
= priv
->arizona
;
866 unsigned int mask
= 1 << w
->shift
;
870 case SND_SOC_DAPM_POST_PMU
:
873 case SND_SOC_DAPM_PRE_PMD
:
876 case SND_SOC_DAPM_PRE_PMU
:
877 case SND_SOC_DAPM_POST_PMD
:
878 return arizona_out_ev(w
, kcontrol
, event
);
883 /* Store the desired state for the HP outputs */
884 priv
->arizona
->hp_ena
&= ~mask
;
885 priv
->arizona
->hp_ena
|= val
;
887 /* Force off if HPDET clamp is active */
888 if (priv
->arizona
->hpdet_clamp
)
891 regmap_update_bits_async(arizona
->regmap
, ARIZONA_OUTPUT_ENABLES_1
,
894 return arizona_out_ev(w
, kcontrol
, event
);
896 EXPORT_SYMBOL_GPL(arizona_hp_ev
);
898 static int arizona_dvfs_enable(struct snd_soc_codec
*codec
)
900 const struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
901 struct arizona
*arizona
= priv
->arizona
;
904 ret
= regulator_set_voltage(arizona
->dcvdd
, 1800000, 1800000);
906 dev_err(codec
->dev
, "Failed to boost DCVDD: %d\n", ret
);
910 ret
= regmap_update_bits(arizona
->regmap
,
911 ARIZONA_DYNAMIC_FREQUENCY_SCALING_1
,
912 ARIZONA_SUBSYS_MAX_FREQ
,
913 ARIZONA_SUBSYS_MAX_FREQ
);
915 dev_err(codec
->dev
, "Failed to enable subsys max: %d\n", ret
);
916 regulator_set_voltage(arizona
->dcvdd
, 1200000, 1800000);
923 static int arizona_dvfs_disable(struct snd_soc_codec
*codec
)
925 const struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
926 struct arizona
*arizona
= priv
->arizona
;
929 ret
= regmap_update_bits(arizona
->regmap
,
930 ARIZONA_DYNAMIC_FREQUENCY_SCALING_1
,
931 ARIZONA_SUBSYS_MAX_FREQ
, 0);
933 dev_err(codec
->dev
, "Failed to disable subsys max: %d\n", ret
);
937 ret
= regulator_set_voltage(arizona
->dcvdd
, 1200000, 1800000);
939 dev_err(codec
->dev
, "Failed to unboost DCVDD: %d\n", ret
);
946 int arizona_dvfs_up(struct snd_soc_codec
*codec
, unsigned int flags
)
948 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
951 mutex_lock(&priv
->dvfs_lock
);
953 if (!priv
->dvfs_cached
&& !priv
->dvfs_reqs
) {
954 ret
= arizona_dvfs_enable(codec
);
959 priv
->dvfs_reqs
|= flags
;
961 mutex_unlock(&priv
->dvfs_lock
);
964 EXPORT_SYMBOL_GPL(arizona_dvfs_up
);
966 int arizona_dvfs_down(struct snd_soc_codec
*codec
, unsigned int flags
)
968 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
969 unsigned int old_reqs
;
972 mutex_lock(&priv
->dvfs_lock
);
974 old_reqs
= priv
->dvfs_reqs
;
975 priv
->dvfs_reqs
&= ~flags
;
977 if (!priv
->dvfs_cached
&& old_reqs
&& !priv
->dvfs_reqs
)
978 ret
= arizona_dvfs_disable(codec
);
980 mutex_unlock(&priv
->dvfs_lock
);
983 EXPORT_SYMBOL_GPL(arizona_dvfs_down
);
985 int arizona_dvfs_sysclk_ev(struct snd_soc_dapm_widget
*w
,
986 struct snd_kcontrol
*kcontrol
, int event
)
988 struct snd_soc_codec
*codec
= snd_soc_dapm_to_codec(w
->dapm
);
989 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
992 mutex_lock(&priv
->dvfs_lock
);
995 case SND_SOC_DAPM_POST_PMU
:
997 ret
= arizona_dvfs_enable(codec
);
999 priv
->dvfs_cached
= false;
1001 case SND_SOC_DAPM_PRE_PMD
:
1002 /* We must ensure DVFS is disabled before the codec goes into
1003 * suspend so that we are never in an illegal state of DVFS
1004 * enabled without enough DCVDD
1006 priv
->dvfs_cached
= true;
1008 if (priv
->dvfs_reqs
)
1009 ret
= arizona_dvfs_disable(codec
);
1015 mutex_unlock(&priv
->dvfs_lock
);
1018 EXPORT_SYMBOL_GPL(arizona_dvfs_sysclk_ev
);
1020 void arizona_init_dvfs(struct arizona_priv
*priv
)
1022 mutex_init(&priv
->dvfs_lock
);
1024 EXPORT_SYMBOL_GPL(arizona_init_dvfs
);
1026 static unsigned int arizona_sysclk_48k_rates
[] = {
1036 static unsigned int arizona_sysclk_44k1_rates
[] = {
1046 static int arizona_set_opclk(struct snd_soc_codec
*codec
, unsigned int clk
,
1049 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1051 unsigned int *rates
;
1052 int ref
, div
, refclk
;
1055 case ARIZONA_CLK_OPCLK
:
1056 reg
= ARIZONA_OUTPUT_SYSTEM_CLOCK
;
1057 refclk
= priv
->sysclk
;
1059 case ARIZONA_CLK_ASYNC_OPCLK
:
1060 reg
= ARIZONA_OUTPUT_ASYNC_CLOCK
;
1061 refclk
= priv
->asyncclk
;
1068 rates
= arizona_sysclk_44k1_rates
;
1070 rates
= arizona_sysclk_48k_rates
;
1072 for (ref
= 0; ref
< ARRAY_SIZE(arizona_sysclk_48k_rates
) &&
1073 rates
[ref
] <= refclk
; ref
++) {
1075 while (rates
[ref
] / div
>= freq
&& div
< 32) {
1076 if (rates
[ref
] / div
== freq
) {
1077 dev_dbg(codec
->dev
, "Configured %dHz OPCLK\n",
1079 snd_soc_update_bits(codec
, reg
,
1080 ARIZONA_OPCLK_DIV_MASK
|
1081 ARIZONA_OPCLK_SEL_MASK
,
1083 ARIZONA_OPCLK_DIV_SHIFT
) |
1091 dev_err(codec
->dev
, "Unable to generate %dHz OPCLK\n", freq
);
1095 int arizona_set_sysclk(struct snd_soc_codec
*codec
, int clk_id
,
1096 int source
, unsigned int freq
, int dir
)
1098 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1099 struct arizona
*arizona
= priv
->arizona
;
1102 unsigned int mask
= ARIZONA_SYSCLK_FREQ_MASK
| ARIZONA_SYSCLK_SRC_MASK
;
1103 unsigned int val
= source
<< ARIZONA_SYSCLK_SRC_SHIFT
;
1107 case ARIZONA_CLK_SYSCLK
:
1109 reg
= ARIZONA_SYSTEM_CLOCK_1
;
1110 clk
= &priv
->sysclk
;
1111 mask
|= ARIZONA_SYSCLK_FRAC
;
1113 case ARIZONA_CLK_ASYNCCLK
:
1115 reg
= ARIZONA_ASYNC_CLOCK_1
;
1116 clk
= &priv
->asyncclk
;
1118 case ARIZONA_CLK_OPCLK
:
1119 case ARIZONA_CLK_ASYNC_OPCLK
:
1120 return arizona_set_opclk(codec
, clk_id
, freq
);
1131 val
|= ARIZONA_CLK_12MHZ
<< ARIZONA_SYSCLK_FREQ_SHIFT
;
1135 val
|= ARIZONA_CLK_24MHZ
<< ARIZONA_SYSCLK_FREQ_SHIFT
;
1139 val
|= ARIZONA_CLK_49MHZ
<< ARIZONA_SYSCLK_FREQ_SHIFT
;
1143 val
|= ARIZONA_CLK_73MHZ
<< ARIZONA_SYSCLK_FREQ_SHIFT
;
1147 val
|= ARIZONA_CLK_98MHZ
<< ARIZONA_SYSCLK_FREQ_SHIFT
;
1151 val
|= ARIZONA_CLK_147MHZ
<< ARIZONA_SYSCLK_FREQ_SHIFT
;
1154 dev_dbg(arizona
->dev
, "%s cleared\n", name
);
1164 val
|= ARIZONA_SYSCLK_FRAC
;
1166 dev_dbg(arizona
->dev
, "%s set to %uHz", name
, freq
);
1168 return regmap_update_bits(arizona
->regmap
, reg
, mask
, val
);
1170 EXPORT_SYMBOL_GPL(arizona_set_sysclk
);
1172 static int arizona_set_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
1174 struct snd_soc_codec
*codec
= dai
->codec
;
1175 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1176 struct arizona
*arizona
= priv
->arizona
;
1177 int lrclk
, bclk
, mode
, base
;
1179 base
= dai
->driver
->base
;
1184 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1185 case SND_SOC_DAIFMT_DSP_A
:
1186 mode
= ARIZONA_FMT_DSP_MODE_A
;
1188 case SND_SOC_DAIFMT_DSP_B
:
1189 if ((fmt
& SND_SOC_DAIFMT_MASTER_MASK
)
1190 != SND_SOC_DAIFMT_CBM_CFM
) {
1191 arizona_aif_err(dai
, "DSP_B not valid in slave mode\n");
1194 mode
= ARIZONA_FMT_DSP_MODE_B
;
1196 case SND_SOC_DAIFMT_I2S
:
1197 mode
= ARIZONA_FMT_I2S_MODE
;
1199 case SND_SOC_DAIFMT_LEFT_J
:
1200 if ((fmt
& SND_SOC_DAIFMT_MASTER_MASK
)
1201 != SND_SOC_DAIFMT_CBM_CFM
) {
1202 arizona_aif_err(dai
, "LEFT_J not valid in slave mode\n");
1205 mode
= ARIZONA_FMT_LEFT_JUSTIFIED_MODE
;
1208 arizona_aif_err(dai
, "Unsupported DAI format %d\n",
1209 fmt
& SND_SOC_DAIFMT_FORMAT_MASK
);
1213 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1214 case SND_SOC_DAIFMT_CBS_CFS
:
1216 case SND_SOC_DAIFMT_CBS_CFM
:
1217 lrclk
|= ARIZONA_AIF1TX_LRCLK_MSTR
;
1219 case SND_SOC_DAIFMT_CBM_CFS
:
1220 bclk
|= ARIZONA_AIF1_BCLK_MSTR
;
1222 case SND_SOC_DAIFMT_CBM_CFM
:
1223 bclk
|= ARIZONA_AIF1_BCLK_MSTR
;
1224 lrclk
|= ARIZONA_AIF1TX_LRCLK_MSTR
;
1227 arizona_aif_err(dai
, "Unsupported master mode %d\n",
1228 fmt
& SND_SOC_DAIFMT_MASTER_MASK
);
1232 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1233 case SND_SOC_DAIFMT_NB_NF
:
1235 case SND_SOC_DAIFMT_IB_IF
:
1236 bclk
|= ARIZONA_AIF1_BCLK_INV
;
1237 lrclk
|= ARIZONA_AIF1TX_LRCLK_INV
;
1239 case SND_SOC_DAIFMT_IB_NF
:
1240 bclk
|= ARIZONA_AIF1_BCLK_INV
;
1242 case SND_SOC_DAIFMT_NB_IF
:
1243 lrclk
|= ARIZONA_AIF1TX_LRCLK_INV
;
1249 regmap_update_bits_async(arizona
->regmap
, base
+ ARIZONA_AIF_BCLK_CTRL
,
1250 ARIZONA_AIF1_BCLK_INV
|
1251 ARIZONA_AIF1_BCLK_MSTR
,
1253 regmap_update_bits_async(arizona
->regmap
, base
+ ARIZONA_AIF_TX_PIN_CTRL
,
1254 ARIZONA_AIF1TX_LRCLK_INV
|
1255 ARIZONA_AIF1TX_LRCLK_MSTR
, lrclk
);
1256 regmap_update_bits_async(arizona
->regmap
,
1257 base
+ ARIZONA_AIF_RX_PIN_CTRL
,
1258 ARIZONA_AIF1RX_LRCLK_INV
|
1259 ARIZONA_AIF1RX_LRCLK_MSTR
, lrclk
);
1260 regmap_update_bits(arizona
->regmap
, base
+ ARIZONA_AIF_FORMAT
,
1261 ARIZONA_AIF1_FMT_MASK
, mode
);
1266 static const int arizona_48k_bclk_rates
[] = {
1288 static const unsigned int arizona_48k_rates
[] = {
1306 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint
= {
1307 .count
= ARRAY_SIZE(arizona_48k_rates
),
1308 .list
= arizona_48k_rates
,
1311 static const int arizona_44k1_bclk_rates
[] = {
1333 static const unsigned int arizona_44k1_rates
[] = {
1343 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint
= {
1344 .count
= ARRAY_SIZE(arizona_44k1_rates
),
1345 .list
= arizona_44k1_rates
,
1348 static int arizona_sr_vals
[] = {
1375 static int arizona_startup(struct snd_pcm_substream
*substream
,
1376 struct snd_soc_dai
*dai
)
1378 struct snd_soc_codec
*codec
= dai
->codec
;
1379 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1380 struct arizona_dai_priv
*dai_priv
= &priv
->dai
[dai
->id
- 1];
1381 const struct snd_pcm_hw_constraint_list
*constraint
;
1382 unsigned int base_rate
;
1384 switch (dai_priv
->clk
) {
1385 case ARIZONA_CLK_SYSCLK
:
1386 base_rate
= priv
->sysclk
;
1388 case ARIZONA_CLK_ASYNCCLK
:
1389 base_rate
= priv
->asyncclk
;
1398 if (base_rate
% 8000)
1399 constraint
= &arizona_44k1_constraint
;
1401 constraint
= &arizona_48k_constraint
;
1403 return snd_pcm_hw_constraint_list(substream
->runtime
, 0,
1404 SNDRV_PCM_HW_PARAM_RATE
,
1408 static void arizona_wm5102_set_dac_comp(struct snd_soc_codec
*codec
,
1411 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1412 struct arizona
*arizona
= priv
->arizona
;
1413 struct reg_sequence dac_comp
[] = {
1415 { ARIZONA_DAC_COMP_1
, 0 },
1416 { ARIZONA_DAC_COMP_2
, 0 },
1420 mutex_lock(&arizona
->dac_comp_lock
);
1422 dac_comp
[1].def
= arizona
->dac_comp_coeff
;
1424 dac_comp
[2].def
= arizona
->dac_comp_enabled
;
1426 mutex_unlock(&arizona
->dac_comp_lock
);
1428 regmap_multi_reg_write(arizona
->regmap
,
1430 ARRAY_SIZE(dac_comp
));
1433 static int arizona_hw_params_rate(struct snd_pcm_substream
*substream
,
1434 struct snd_pcm_hw_params
*params
,
1435 struct snd_soc_dai
*dai
)
1437 struct snd_soc_codec
*codec
= dai
->codec
;
1438 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1439 struct arizona_dai_priv
*dai_priv
= &priv
->dai
[dai
->id
- 1];
1440 int base
= dai
->driver
->base
;
1444 * We will need to be more flexible than this in future,
1445 * currently we use a single sample rate for SYSCLK.
1447 for (i
= 0; i
< ARRAY_SIZE(arizona_sr_vals
); i
++)
1448 if (arizona_sr_vals
[i
] == params_rate(params
))
1450 if (i
== ARRAY_SIZE(arizona_sr_vals
)) {
1451 arizona_aif_err(dai
, "Unsupported sample rate %dHz\n",
1452 params_rate(params
));
1457 switch (priv
->arizona
->type
) {
1460 if (arizona_sr_vals
[sr_val
] >= 88200)
1461 ret
= arizona_dvfs_up(codec
, ARIZONA_DVFS_SR1_RQ
);
1463 ret
= arizona_dvfs_down(codec
, ARIZONA_DVFS_SR1_RQ
);
1466 arizona_aif_err(dai
, "Failed to change DVFS %d\n", ret
);
1474 switch (dai_priv
->clk
) {
1475 case ARIZONA_CLK_SYSCLK
:
1476 switch (priv
->arizona
->type
) {
1478 arizona_wm5102_set_dac_comp(codec
,
1479 params_rate(params
));
1485 snd_soc_update_bits(codec
, ARIZONA_SAMPLE_RATE_1
,
1486 ARIZONA_SAMPLE_RATE_1_MASK
, sr_val
);
1488 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_RATE_CTRL
,
1489 ARIZONA_AIF1_RATE_MASK
, 0);
1491 case ARIZONA_CLK_ASYNCCLK
:
1492 snd_soc_update_bits(codec
, ARIZONA_ASYNC_SAMPLE_RATE_1
,
1493 ARIZONA_ASYNC_SAMPLE_RATE_1_MASK
, sr_val
);
1495 snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_RATE_CTRL
,
1496 ARIZONA_AIF1_RATE_MASK
,
1497 8 << ARIZONA_AIF1_RATE_SHIFT
);
1500 arizona_aif_err(dai
, "Invalid clock %d\n", dai_priv
->clk
);
1507 static bool arizona_aif_cfg_changed(struct snd_soc_codec
*codec
,
1508 int base
, int bclk
, int lrclk
, int frame
)
1512 val
= snd_soc_read(codec
, base
+ ARIZONA_AIF_BCLK_CTRL
);
1513 if (bclk
!= (val
& ARIZONA_AIF1_BCLK_FREQ_MASK
))
1516 val
= snd_soc_read(codec
, base
+ ARIZONA_AIF_TX_BCLK_RATE
);
1517 if (lrclk
!= (val
& ARIZONA_AIF1TX_BCPF_MASK
))
1520 val
= snd_soc_read(codec
, base
+ ARIZONA_AIF_FRAME_CTRL_1
);
1521 if (frame
!= (val
& (ARIZONA_AIF1TX_WL_MASK
|
1522 ARIZONA_AIF1TX_SLOT_LEN_MASK
)))
1528 static int arizona_hw_params(struct snd_pcm_substream
*substream
,
1529 struct snd_pcm_hw_params
*params
,
1530 struct snd_soc_dai
*dai
)
1532 struct snd_soc_codec
*codec
= dai
->codec
;
1533 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1534 struct arizona
*arizona
= priv
->arizona
;
1535 int base
= dai
->driver
->base
;
1538 int channels
= params_channels(params
);
1539 int chan_limit
= arizona
->pdata
.max_channels_clocked
[dai
->id
- 1];
1540 int tdm_width
= arizona
->tdm_width
[dai
->id
- 1];
1541 int tdm_slots
= arizona
->tdm_slots
[dai
->id
- 1];
1542 int bclk
, lrclk
, wl
, frame
, bclk_target
;
1544 unsigned int aif_tx_state
, aif_rx_state
;
1546 if (params_rate(params
) % 8000)
1547 rates
= &arizona_44k1_bclk_rates
[0];
1549 rates
= &arizona_48k_bclk_rates
[0];
1551 wl
= params_width(params
);
1554 arizona_aif_dbg(dai
, "Configuring for %d %d bit TDM slots\n",
1555 tdm_slots
, tdm_width
);
1556 bclk_target
= tdm_slots
* tdm_width
* params_rate(params
);
1557 channels
= tdm_slots
;
1559 bclk_target
= snd_soc_params_to_bclk(params
);
1563 if (chan_limit
&& chan_limit
< channels
) {
1564 arizona_aif_dbg(dai
, "Limiting to %d channels\n", chan_limit
);
1565 bclk_target
/= channels
;
1566 bclk_target
*= chan_limit
;
1569 /* Force multiple of 2 channels for I2S mode */
1570 val
= snd_soc_read(codec
, base
+ ARIZONA_AIF_FORMAT
);
1571 val
&= ARIZONA_AIF1_FMT_MASK
;
1572 if ((channels
& 1) && (val
== ARIZONA_FMT_I2S_MODE
)) {
1573 arizona_aif_dbg(dai
, "Forcing stereo mode\n");
1574 bclk_target
/= channels
;
1575 bclk_target
*= channels
+ 1;
1578 for (i
= 0; i
< ARRAY_SIZE(arizona_44k1_bclk_rates
); i
++) {
1579 if (rates
[i
] >= bclk_target
&&
1580 rates
[i
] % params_rate(params
) == 0) {
1585 if (i
== ARRAY_SIZE(arizona_44k1_bclk_rates
)) {
1586 arizona_aif_err(dai
, "Unsupported sample rate %dHz\n",
1587 params_rate(params
));
1591 lrclk
= rates
[bclk
] / params_rate(params
);
1593 arizona_aif_dbg(dai
, "BCLK %dHz LRCLK %dHz\n",
1594 rates
[bclk
], rates
[bclk
] / lrclk
);
1596 frame
= wl
<< ARIZONA_AIF1TX_WL_SHIFT
| tdm_width
;
1598 reconfig
= arizona_aif_cfg_changed(codec
, base
, bclk
, lrclk
, frame
);
1601 /* Save AIF TX/RX state */
1602 aif_tx_state
= snd_soc_read(codec
,
1603 base
+ ARIZONA_AIF_TX_ENABLES
);
1604 aif_rx_state
= snd_soc_read(codec
,
1605 base
+ ARIZONA_AIF_RX_ENABLES
);
1606 /* Disable AIF TX/RX before reconfiguring it */
1607 regmap_update_bits_async(arizona
->regmap
,
1608 base
+ ARIZONA_AIF_TX_ENABLES
, 0xff, 0x0);
1609 regmap_update_bits(arizona
->regmap
,
1610 base
+ ARIZONA_AIF_RX_ENABLES
, 0xff, 0x0);
1613 ret
= arizona_hw_params_rate(substream
, params
, dai
);
1618 regmap_update_bits_async(arizona
->regmap
,
1619 base
+ ARIZONA_AIF_BCLK_CTRL
,
1620 ARIZONA_AIF1_BCLK_FREQ_MASK
, bclk
);
1621 regmap_update_bits_async(arizona
->regmap
,
1622 base
+ ARIZONA_AIF_TX_BCLK_RATE
,
1623 ARIZONA_AIF1TX_BCPF_MASK
, lrclk
);
1624 regmap_update_bits_async(arizona
->regmap
,
1625 base
+ ARIZONA_AIF_RX_BCLK_RATE
,
1626 ARIZONA_AIF1RX_BCPF_MASK
, lrclk
);
1627 regmap_update_bits_async(arizona
->regmap
,
1628 base
+ ARIZONA_AIF_FRAME_CTRL_1
,
1629 ARIZONA_AIF1TX_WL_MASK
|
1630 ARIZONA_AIF1TX_SLOT_LEN_MASK
, frame
);
1631 regmap_update_bits(arizona
->regmap
,
1632 base
+ ARIZONA_AIF_FRAME_CTRL_2
,
1633 ARIZONA_AIF1RX_WL_MASK
|
1634 ARIZONA_AIF1RX_SLOT_LEN_MASK
, frame
);
1639 /* Restore AIF TX/RX state */
1640 regmap_update_bits_async(arizona
->regmap
,
1641 base
+ ARIZONA_AIF_TX_ENABLES
,
1642 0xff, aif_tx_state
);
1643 regmap_update_bits(arizona
->regmap
,
1644 base
+ ARIZONA_AIF_RX_ENABLES
,
1645 0xff, aif_rx_state
);
1650 static const char *arizona_dai_clk_str(int clk_id
)
1653 case ARIZONA_CLK_SYSCLK
:
1655 case ARIZONA_CLK_ASYNCCLK
:
1658 return "Unknown clock";
1662 static int arizona_dai_set_sysclk(struct snd_soc_dai
*dai
,
1663 int clk_id
, unsigned int freq
, int dir
)
1665 struct snd_soc_codec
*codec
= dai
->codec
;
1666 struct snd_soc_dapm_context
*dapm
= snd_soc_codec_get_dapm(codec
);
1667 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1668 struct arizona_dai_priv
*dai_priv
= &priv
->dai
[dai
->id
- 1];
1669 struct snd_soc_dapm_route routes
[2];
1672 case ARIZONA_CLK_SYSCLK
:
1673 case ARIZONA_CLK_ASYNCCLK
:
1679 if (clk_id
== dai_priv
->clk
)
1683 dev_err(codec
->dev
, "Can't change clock on active DAI %d\n",
1688 dev_dbg(codec
->dev
, "Setting AIF%d to %s\n", dai
->id
+ 1,
1689 arizona_dai_clk_str(clk_id
));
1691 memset(&routes
, 0, sizeof(routes
));
1692 routes
[0].sink
= dai
->driver
->capture
.stream_name
;
1693 routes
[1].sink
= dai
->driver
->playback
.stream_name
;
1695 routes
[0].source
= arizona_dai_clk_str(dai_priv
->clk
);
1696 routes
[1].source
= arizona_dai_clk_str(dai_priv
->clk
);
1697 snd_soc_dapm_del_routes(dapm
, routes
, ARRAY_SIZE(routes
));
1699 routes
[0].source
= arizona_dai_clk_str(clk_id
);
1700 routes
[1].source
= arizona_dai_clk_str(clk_id
);
1701 snd_soc_dapm_add_routes(dapm
, routes
, ARRAY_SIZE(routes
));
1703 dai_priv
->clk
= clk_id
;
1705 return snd_soc_dapm_sync(dapm
);
1708 static int arizona_set_tristate(struct snd_soc_dai
*dai
, int tristate
)
1710 struct snd_soc_codec
*codec
= dai
->codec
;
1711 int base
= dai
->driver
->base
;
1715 reg
= ARIZONA_AIF1_TRI
;
1719 return snd_soc_update_bits(codec
, base
+ ARIZONA_AIF_RATE_CTRL
,
1720 ARIZONA_AIF1_TRI
, reg
);
1723 static void arizona_set_channels_to_mask(struct snd_soc_dai
*dai
,
1725 int channels
, unsigned int mask
)
1727 struct snd_soc_codec
*codec
= dai
->codec
;
1728 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1729 struct arizona
*arizona
= priv
->arizona
;
1732 for (i
= 0; i
< channels
; ++i
) {
1733 slot
= ffs(mask
) - 1;
1737 regmap_write(arizona
->regmap
, base
+ i
, slot
);
1739 mask
&= ~(1 << slot
);
1743 arizona_aif_warn(dai
, "Too many channels in TDM mask\n");
1746 static int arizona_set_tdm_slot(struct snd_soc_dai
*dai
, unsigned int tx_mask
,
1747 unsigned int rx_mask
, int slots
, int slot_width
)
1749 struct snd_soc_codec
*codec
= dai
->codec
;
1750 struct arizona_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
1751 struct arizona
*arizona
= priv
->arizona
;
1752 int base
= dai
->driver
->base
;
1753 int rx_max_chan
= dai
->driver
->playback
.channels_max
;
1754 int tx_max_chan
= dai
->driver
->capture
.channels_max
;
1756 /* Only support TDM for the physical AIFs */
1757 if (dai
->id
> ARIZONA_MAX_AIF
)
1761 tx_mask
= (1 << tx_max_chan
) - 1;
1762 rx_mask
= (1 << rx_max_chan
) - 1;
1765 arizona_set_channels_to_mask(dai
, base
+ ARIZONA_AIF_FRAME_CTRL_3
,
1766 tx_max_chan
, tx_mask
);
1767 arizona_set_channels_to_mask(dai
, base
+ ARIZONA_AIF_FRAME_CTRL_11
,
1768 rx_max_chan
, rx_mask
);
1770 arizona
->tdm_width
[dai
->id
- 1] = slot_width
;
1771 arizona
->tdm_slots
[dai
->id
- 1] = slots
;
1776 const struct snd_soc_dai_ops arizona_dai_ops
= {
1777 .startup
= arizona_startup
,
1778 .set_fmt
= arizona_set_fmt
,
1779 .set_tdm_slot
= arizona_set_tdm_slot
,
1780 .hw_params
= arizona_hw_params
,
1781 .set_sysclk
= arizona_dai_set_sysclk
,
1782 .set_tristate
= arizona_set_tristate
,
1784 EXPORT_SYMBOL_GPL(arizona_dai_ops
);
1786 const struct snd_soc_dai_ops arizona_simple_dai_ops
= {
1787 .startup
= arizona_startup
,
1788 .hw_params
= arizona_hw_params_rate
,
1789 .set_sysclk
= arizona_dai_set_sysclk
,
1791 EXPORT_SYMBOL_GPL(arizona_simple_dai_ops
);
1793 int arizona_init_dai(struct arizona_priv
*priv
, int id
)
1795 struct arizona_dai_priv
*dai_priv
= &priv
->dai
[id
];
1797 dai_priv
->clk
= ARIZONA_CLK_SYSCLK
;
1801 EXPORT_SYMBOL_GPL(arizona_init_dai
);
1809 { 0, 64000, 4, 16 },
1810 { 64000, 128000, 3, 8 },
1811 { 128000, 256000, 2, 4 },
1812 { 256000, 1000000, 1, 2 },
1813 { 1000000, 13500000, 0, 1 },
1822 { 256000, 1000000, 2 },
1823 { 1000000, 13500000, 4 },
1826 struct arizona_fll_cfg
{
1836 static int arizona_validate_fll(struct arizona_fll
*fll
,
1840 unsigned int Fvco_min
;
1842 if (fll
->fout
&& Fout
!= fll
->fout
) {
1843 arizona_fll_err(fll
,
1844 "Can't change output on active FLL\n");
1848 if (Fref
/ ARIZONA_FLL_MAX_REFDIV
> ARIZONA_FLL_MAX_FREF
) {
1849 arizona_fll_err(fll
,
1850 "Can't scale %dMHz in to <=13.5MHz\n",
1855 Fvco_min
= ARIZONA_FLL_MIN_FVCO
* fll
->vco_mult
;
1856 if (Fout
* ARIZONA_FLL_MAX_OUTDIV
< Fvco_min
) {
1857 arizona_fll_err(fll
, "No FLL_OUTDIV for Fout=%uHz\n",
1865 static int arizona_find_fratio(unsigned int Fref
, int *fratio
)
1869 /* Find an appropriate FLL_FRATIO */
1870 for (i
= 0; i
< ARRAY_SIZE(fll_fratios
); i
++) {
1871 if (fll_fratios
[i
].min
<= Fref
&& Fref
<= fll_fratios
[i
].max
) {
1873 *fratio
= fll_fratios
[i
].fratio
;
1874 return fll_fratios
[i
].ratio
;
1881 static int arizona_calc_fratio(struct arizona_fll
*fll
,
1882 struct arizona_fll_cfg
*cfg
,
1883 unsigned int target
,
1884 unsigned int Fref
, bool sync
)
1886 int init_ratio
, ratio
;
1889 /* Fref must be <=13.5MHz, find initial refdiv */
1892 while (Fref
> ARIZONA_FLL_MAX_FREF
) {
1897 if (div
> ARIZONA_FLL_MAX_REFDIV
)
1901 /* Find an appropriate FLL_FRATIO */
1902 init_ratio
= arizona_find_fratio(Fref
, &cfg
->fratio
);
1903 if (init_ratio
< 0) {
1904 arizona_fll_err(fll
, "Unable to find FRATIO for Fref=%uHz\n",
1909 switch (fll
->arizona
->type
) {
1912 if (fll
->arizona
->rev
< 3 || sync
)
1924 cfg
->fratio
= init_ratio
- 1;
1926 /* Adjust FRATIO/refdiv to avoid integer mode if possible */
1927 refdiv
= cfg
->refdiv
;
1929 while (div
<= ARIZONA_FLL_MAX_REFDIV
) {
1930 for (ratio
= init_ratio
; ratio
<= ARIZONA_FLL_MAX_FRATIO
;
1932 if ((ARIZONA_FLL_VCO_CORNER
/ 2) /
1933 (fll
->vco_mult
* ratio
) < Fref
)
1936 if (target
% (ratio
* Fref
)) {
1937 cfg
->refdiv
= refdiv
;
1938 cfg
->fratio
= ratio
- 1;
1943 for (ratio
= init_ratio
- 1; ratio
> 0; ratio
--) {
1944 if (target
% (ratio
* Fref
)) {
1945 cfg
->refdiv
= refdiv
;
1946 cfg
->fratio
= ratio
- 1;
1954 init_ratio
= arizona_find_fratio(Fref
, NULL
);
1957 arizona_fll_warn(fll
, "Falling back to integer mode operation\n");
1958 return cfg
->fratio
+ 1;
1961 static int arizona_calc_fll(struct arizona_fll
*fll
,
1962 struct arizona_fll_cfg
*cfg
,
1963 unsigned int Fref
, bool sync
)
1965 unsigned int target
, div
, gcd_fll
;
1968 arizona_fll_dbg(fll
, "Fref=%u Fout=%u\n", Fref
, fll
->fout
);
1970 /* Fvco should be over the targt; don't check the upper bound */
1971 div
= ARIZONA_FLL_MIN_OUTDIV
;
1972 while (fll
->fout
* div
< ARIZONA_FLL_MIN_FVCO
* fll
->vco_mult
) {
1974 if (div
> ARIZONA_FLL_MAX_OUTDIV
)
1977 target
= fll
->fout
* div
/ fll
->vco_mult
;
1980 arizona_fll_dbg(fll
, "Fvco=%dHz\n", target
);
1982 /* Find an appropriate FLL_FRATIO and refdiv */
1983 ratio
= arizona_calc_fratio(fll
, cfg
, target
, Fref
, sync
);
1987 /* Apply the division for our remaining calculations */
1988 Fref
= Fref
/ (1 << cfg
->refdiv
);
1990 cfg
->n
= target
/ (ratio
* Fref
);
1992 if (target
% (ratio
* Fref
)) {
1993 gcd_fll
= gcd(target
, ratio
* Fref
);
1994 arizona_fll_dbg(fll
, "GCD=%u\n", gcd_fll
);
1996 cfg
->theta
= (target
- (cfg
->n
* ratio
* Fref
))
1998 cfg
->lambda
= (ratio
* Fref
) / gcd_fll
;
2004 /* Round down to 16bit range with cost of accuracy lost.
2005 * Denominator must be bigger than numerator so we only
2008 while (cfg
->lambda
>= (1 << 16)) {
2013 for (i
= 0; i
< ARRAY_SIZE(fll_gains
); i
++) {
2014 if (fll_gains
[i
].min
<= Fref
&& Fref
<= fll_gains
[i
].max
) {
2015 cfg
->gain
= fll_gains
[i
].gain
;
2019 if (i
== ARRAY_SIZE(fll_gains
)) {
2020 arizona_fll_err(fll
, "Unable to find gain for Fref=%uHz\n",
2025 arizona_fll_dbg(fll
, "N=%x THETA=%x LAMBDA=%x\n",
2026 cfg
->n
, cfg
->theta
, cfg
->lambda
);
2027 arizona_fll_dbg(fll
, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
2028 cfg
->fratio
, cfg
->fratio
, cfg
->outdiv
, cfg
->refdiv
);
2029 arizona_fll_dbg(fll
, "GAIN=%d\n", cfg
->gain
);
2035 static void arizona_apply_fll(struct arizona
*arizona
, unsigned int base
,
2036 struct arizona_fll_cfg
*cfg
, int source
,
2039 regmap_update_bits_async(arizona
->regmap
, base
+ 3,
2040 ARIZONA_FLL1_THETA_MASK
, cfg
->theta
);
2041 regmap_update_bits_async(arizona
->regmap
, base
+ 4,
2042 ARIZONA_FLL1_LAMBDA_MASK
, cfg
->lambda
);
2043 regmap_update_bits_async(arizona
->regmap
, base
+ 5,
2044 ARIZONA_FLL1_FRATIO_MASK
,
2045 cfg
->fratio
<< ARIZONA_FLL1_FRATIO_SHIFT
);
2046 regmap_update_bits_async(arizona
->regmap
, base
+ 6,
2047 ARIZONA_FLL1_CLK_REF_DIV_MASK
|
2048 ARIZONA_FLL1_CLK_REF_SRC_MASK
,
2049 cfg
->refdiv
<< ARIZONA_FLL1_CLK_REF_DIV_SHIFT
|
2050 source
<< ARIZONA_FLL1_CLK_REF_SRC_SHIFT
);
2053 regmap_update_bits(arizona
->regmap
, base
+ 0x7,
2054 ARIZONA_FLL1_GAIN_MASK
,
2055 cfg
->gain
<< ARIZONA_FLL1_GAIN_SHIFT
);
2057 regmap_update_bits(arizona
->regmap
, base
+ 0x5,
2058 ARIZONA_FLL1_OUTDIV_MASK
,
2059 cfg
->outdiv
<< ARIZONA_FLL1_OUTDIV_SHIFT
);
2060 regmap_update_bits(arizona
->regmap
, base
+ 0x9,
2061 ARIZONA_FLL1_GAIN_MASK
,
2062 cfg
->gain
<< ARIZONA_FLL1_GAIN_SHIFT
);
2065 regmap_update_bits_async(arizona
->regmap
, base
+ 2,
2066 ARIZONA_FLL1_CTRL_UPD
| ARIZONA_FLL1_N_MASK
,
2067 ARIZONA_FLL1_CTRL_UPD
| cfg
->n
);
2070 static int arizona_is_enabled_fll(struct arizona_fll
*fll
)
2072 struct arizona
*arizona
= fll
->arizona
;
2076 ret
= regmap_read(arizona
->regmap
, fll
->base
+ 1, ®
);
2078 arizona_fll_err(fll
, "Failed to read current state: %d\n",
2083 return reg
& ARIZONA_FLL1_ENA
;
2086 static int arizona_enable_fll(struct arizona_fll
*fll
)
2088 struct arizona
*arizona
= fll
->arizona
;
2089 bool use_sync
= false;
2090 int already_enabled
= arizona_is_enabled_fll(fll
);
2091 struct arizona_fll_cfg cfg
;
2095 if (already_enabled
< 0)
2096 return already_enabled
;
2098 if (already_enabled
) {
2099 /* Facilitate smooth refclk across the transition */
2100 regmap_update_bits_async(fll
->arizona
->regmap
, fll
->base
+ 0x9,
2101 ARIZONA_FLL1_GAIN_MASK
, 0);
2102 regmap_update_bits_async(fll
->arizona
->regmap
, fll
->base
+ 1,
2103 ARIZONA_FLL1_FREERUN
,
2104 ARIZONA_FLL1_FREERUN
);
2108 * If we have both REFCLK and SYNCCLK then enable both,
2109 * otherwise apply the SYNCCLK settings to REFCLK.
2111 if (fll
->ref_src
>= 0 && fll
->ref_freq
&&
2112 fll
->ref_src
!= fll
->sync_src
) {
2113 arizona_calc_fll(fll
, &cfg
, fll
->ref_freq
, false);
2115 arizona_apply_fll(arizona
, fll
->base
, &cfg
, fll
->ref_src
,
2117 if (fll
->sync_src
>= 0) {
2118 arizona_calc_fll(fll
, &cfg
, fll
->sync_freq
, true);
2120 arizona_apply_fll(arizona
, fll
->base
+ 0x10, &cfg
,
2121 fll
->sync_src
, true);
2124 } else if (fll
->sync_src
>= 0) {
2125 arizona_calc_fll(fll
, &cfg
, fll
->sync_freq
, false);
2127 arizona_apply_fll(arizona
, fll
->base
, &cfg
,
2128 fll
->sync_src
, false);
2130 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 0x11,
2131 ARIZONA_FLL1_SYNC_ENA
, 0);
2133 arizona_fll_err(fll
, "No clocks provided\n");
2138 * Increase the bandwidth if we're not using a low frequency
2141 if (use_sync
&& fll
->sync_freq
> 100000)
2142 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 0x17,
2143 ARIZONA_FLL1_SYNC_BW
, 0);
2145 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 0x17,
2146 ARIZONA_FLL1_SYNC_BW
,
2147 ARIZONA_FLL1_SYNC_BW
);
2149 if (!already_enabled
)
2150 pm_runtime_get(arizona
->dev
);
2152 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 1,
2153 ARIZONA_FLL1_ENA
, ARIZONA_FLL1_ENA
);
2155 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 0x11,
2156 ARIZONA_FLL1_SYNC_ENA
,
2157 ARIZONA_FLL1_SYNC_ENA
);
2159 if (already_enabled
)
2160 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 1,
2161 ARIZONA_FLL1_FREERUN
, 0);
2163 arizona_fll_dbg(fll
, "Waiting for FLL lock...\n");
2165 for (i
= 0; i
< 15; i
++) {
2167 usleep_range(200, 400);
2171 regmap_read(arizona
->regmap
,
2172 ARIZONA_INTERRUPT_RAW_STATUS_5
,
2174 if (val
& (ARIZONA_FLL1_CLOCK_OK_STS
<< (fll
->id
- 1)))
2178 arizona_fll_warn(fll
, "Timed out waiting for lock\n");
2180 arizona_fll_dbg(fll
, "FLL locked (%d polls)\n", i
);
2185 static void arizona_disable_fll(struct arizona_fll
*fll
)
2187 struct arizona
*arizona
= fll
->arizona
;
2190 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 1,
2191 ARIZONA_FLL1_FREERUN
, ARIZONA_FLL1_FREERUN
);
2192 regmap_update_bits_check(arizona
->regmap
, fll
->base
+ 1,
2193 ARIZONA_FLL1_ENA
, 0, &change
);
2194 regmap_update_bits(arizona
->regmap
, fll
->base
+ 0x11,
2195 ARIZONA_FLL1_SYNC_ENA
, 0);
2196 regmap_update_bits_async(arizona
->regmap
, fll
->base
+ 1,
2197 ARIZONA_FLL1_FREERUN
, 0);
2200 pm_runtime_put_autosuspend(arizona
->dev
);
2203 int arizona_set_fll_refclk(struct arizona_fll
*fll
, int source
,
2204 unsigned int Fref
, unsigned int Fout
)
2208 if (fll
->ref_src
== source
&& fll
->ref_freq
== Fref
)
2211 if (fll
->fout
&& Fref
> 0) {
2212 ret
= arizona_validate_fll(fll
, Fref
, fll
->fout
);
2217 fll
->ref_src
= source
;
2218 fll
->ref_freq
= Fref
;
2220 if (fll
->fout
&& Fref
> 0) {
2221 ret
= arizona_enable_fll(fll
);
2226 EXPORT_SYMBOL_GPL(arizona_set_fll_refclk
);
2228 int arizona_set_fll(struct arizona_fll
*fll
, int source
,
2229 unsigned int Fref
, unsigned int Fout
)
2233 if (fll
->sync_src
== source
&&
2234 fll
->sync_freq
== Fref
&& fll
->fout
== Fout
)
2238 if (fll
->ref_src
>= 0) {
2239 ret
= arizona_validate_fll(fll
, fll
->ref_freq
, Fout
);
2244 ret
= arizona_validate_fll(fll
, Fref
, Fout
);
2249 fll
->sync_src
= source
;
2250 fll
->sync_freq
= Fref
;
2254 ret
= arizona_enable_fll(fll
);
2256 arizona_disable_fll(fll
);
2260 EXPORT_SYMBOL_GPL(arizona_set_fll
);
2262 int arizona_init_fll(struct arizona
*arizona
, int id
, int base
, int lock_irq
,
2263 int ok_irq
, struct arizona_fll
*fll
)
2269 fll
->arizona
= arizona
;
2270 fll
->sync_src
= ARIZONA_FLL_SRC_NONE
;
2272 /* Configure default refclk to 32kHz if we have one */
2273 regmap_read(arizona
->regmap
, ARIZONA_CLOCK_32K_1
, &val
);
2274 switch (val
& ARIZONA_CLK_32K_SRC_MASK
) {
2275 case ARIZONA_CLK_SRC_MCLK1
:
2276 case ARIZONA_CLK_SRC_MCLK2
:
2277 fll
->ref_src
= val
& ARIZONA_CLK_32K_SRC_MASK
;
2280 fll
->ref_src
= ARIZONA_FLL_SRC_NONE
;
2282 fll
->ref_freq
= 32768;
2284 snprintf(fll
->lock_name
, sizeof(fll
->lock_name
), "FLL%d lock", id
);
2285 snprintf(fll
->clock_ok_name
, sizeof(fll
->clock_ok_name
),
2286 "FLL%d clock OK", id
);
2288 regmap_update_bits(arizona
->regmap
, fll
->base
+ 1,
2289 ARIZONA_FLL1_FREERUN
, 0);
2293 EXPORT_SYMBOL_GPL(arizona_init_fll
);
2296 * arizona_set_output_mode - Set the mode of the specified output
2298 * @codec: Device to configure
2299 * @output: Output number
2300 * @diff: True to set the output to differential mode
2302 * Some systems use external analogue switches to connect more
2303 * analogue devices to the CODEC than are supported by the device. In
2304 * some systems this requires changing the switched output from single
2305 * ended to differential mode dynamically at runtime, an operation
2306 * supported using this function.
2308 * Most systems have a single static configuration and should use
2309 * platform data instead.
2311 int arizona_set_output_mode(struct snd_soc_codec
*codec
, int output
, bool diff
)
2313 unsigned int reg
, val
;
2315 if (output
< 1 || output
> 6)
2318 reg
= ARIZONA_OUTPUT_PATH_CONFIG_1L
+ (output
- 1) * 8;
2321 val
= ARIZONA_OUT1_MONO
;
2325 return snd_soc_update_bits(codec
, reg
, ARIZONA_OUT1_MONO
, val
);
2327 EXPORT_SYMBOL_GPL(arizona_set_output_mode
);
2329 static const struct soc_enum arizona_adsp2_rate_enum
[] = {
2330 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1
,
2331 ARIZONA_DSP1_RATE_SHIFT
, 0xf,
2332 ARIZONA_RATE_ENUM_SIZE
,
2333 arizona_rate_text
, arizona_rate_val
),
2334 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1
,
2335 ARIZONA_DSP1_RATE_SHIFT
, 0xf,
2336 ARIZONA_RATE_ENUM_SIZE
,
2337 arizona_rate_text
, arizona_rate_val
),
2338 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1
,
2339 ARIZONA_DSP1_RATE_SHIFT
, 0xf,
2340 ARIZONA_RATE_ENUM_SIZE
,
2341 arizona_rate_text
, arizona_rate_val
),
2342 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1
,
2343 ARIZONA_DSP1_RATE_SHIFT
, 0xf,
2344 ARIZONA_RATE_ENUM_SIZE
,
2345 arizona_rate_text
, arizona_rate_val
),
2348 const struct snd_kcontrol_new arizona_adsp2_rate_controls
[] = {
2349 SOC_ENUM("DSP1 Rate", arizona_adsp2_rate_enum
[0]),
2350 SOC_ENUM("DSP2 Rate", arizona_adsp2_rate_enum
[1]),
2351 SOC_ENUM("DSP3 Rate", arizona_adsp2_rate_enum
[2]),
2352 SOC_ENUM("DSP4 Rate", arizona_adsp2_rate_enum
[3]),
2354 EXPORT_SYMBOL_GPL(arizona_adsp2_rate_controls
);
2356 static bool arizona_eq_filter_unstable(bool mode
, __be16 _a
, __be16 _b
)
2358 s16 a
= be16_to_cpu(_a
);
2359 s16 b
= be16_to_cpu(_b
);
2362 return abs(a
) >= 4096;
2367 return (abs((a
<< 16) / (4096 - b
)) >= 4096 << 4);
2371 int arizona_eq_coeff_put(struct snd_kcontrol
*kcontrol
,
2372 struct snd_ctl_elem_value
*ucontrol
)
2374 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
2375 struct arizona
*arizona
= dev_get_drvdata(codec
->dev
->parent
);
2376 struct soc_bytes
*params
= (void *)kcontrol
->private_value
;
2382 len
= params
->num_regs
* regmap_get_val_bytes(arizona
->regmap
);
2384 data
= kmemdup(ucontrol
->value
.bytes
.data
, len
, GFP_KERNEL
| GFP_DMA
);
2388 data
[0] &= cpu_to_be16(ARIZONA_EQ1_B1_MODE
);
2390 if (arizona_eq_filter_unstable(!!data
[0], data
[1], data
[2]) ||
2391 arizona_eq_filter_unstable(true, data
[4], data
[5]) ||
2392 arizona_eq_filter_unstable(true, data
[8], data
[9]) ||
2393 arizona_eq_filter_unstable(true, data
[12], data
[13]) ||
2394 arizona_eq_filter_unstable(false, data
[16], data
[17])) {
2395 dev_err(arizona
->dev
, "Rejecting unstable EQ coefficients\n");
2400 ret
= regmap_read(arizona
->regmap
, params
->base
, &val
);
2404 val
&= ~ARIZONA_EQ1_B1_MODE
;
2405 data
[0] |= cpu_to_be16(val
);
2407 ret
= regmap_raw_write(arizona
->regmap
, params
->base
, data
, len
);
2413 EXPORT_SYMBOL_GPL(arizona_eq_coeff_put
);
2415 int arizona_lhpf_coeff_put(struct snd_kcontrol
*kcontrol
,
2416 struct snd_ctl_elem_value
*ucontrol
)
2418 struct snd_soc_codec
*codec
= snd_soc_kcontrol_codec(kcontrol
);
2419 struct arizona
*arizona
= dev_get_drvdata(codec
->dev
->parent
);
2420 __be16
*data
= (__be16
*)ucontrol
->value
.bytes
.data
;
2421 s16 val
= be16_to_cpu(*data
);
2423 if (abs(val
) >= 4096) {
2424 dev_err(arizona
->dev
, "Rejecting unstable LHPF coefficients\n");
2428 return snd_soc_bytes_put(kcontrol
, ucontrol
);
2430 EXPORT_SYMBOL_GPL(arizona_lhpf_coeff_put
);
2432 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
2433 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2434 MODULE_LICENSE("GPL");