2 * CS4271 ASoC codec driver
4 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * This driver support CS4271 codec being master or slave, working
17 * in control port mode, connected either via SPI or I2C.
18 * The data format accepted is I2S or left-justified.
19 * DAPM support not implemented.
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/delay.h>
25 #include <sound/pcm.h>
26 #include <sound/soc.h>
27 #include <sound/tlv.h>
28 #include <linux/gpio.h>
29 #include <linux/i2c.h>
30 #include <linux/spi/spi.h>
31 #include <sound/cs4271.h>
33 #define CS4271_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
34 SNDRV_PCM_FMTBIT_S24_LE | \
35 SNDRV_PCM_FMTBIT_S32_LE)
39 * High byte represents SPI chip address (0x10) + write command (0)
40 * Low byte - codec register address
42 #define CS4271_MODE1 0x2001 /* Mode Control 1 */
43 #define CS4271_DACCTL 0x2002 /* DAC Control */
44 #define CS4271_DACVOL 0x2003 /* DAC Volume & Mixing Control */
45 #define CS4271_VOLA 0x2004 /* DAC Channel A Volume Control */
46 #define CS4271_VOLB 0x2005 /* DAC Channel B Volume Control */
47 #define CS4271_ADCCTL 0x2006 /* ADC Control */
48 #define CS4271_MODE2 0x2007 /* Mode Control 2 */
49 #define CS4271_CHIPID 0x2008 /* Chip ID */
51 #define CS4271_FIRSTREG CS4271_MODE1
52 #define CS4271_LASTREG CS4271_MODE2
53 #define CS4271_NR_REGS ((CS4271_LASTREG & 0xFF) + 1)
55 /* Bit masks for the CS4271 registers */
56 #define CS4271_MODE1_MODE_MASK 0xC0
57 #define CS4271_MODE1_MODE_1X 0x00
58 #define CS4271_MODE1_MODE_2X 0x80
59 #define CS4271_MODE1_MODE_4X 0xC0
61 #define CS4271_MODE1_DIV_MASK 0x30
62 #define CS4271_MODE1_DIV_1 0x00
63 #define CS4271_MODE1_DIV_15 0x10
64 #define CS4271_MODE1_DIV_2 0x20
65 #define CS4271_MODE1_DIV_3 0x30
67 #define CS4271_MODE1_MASTER 0x08
69 #define CS4271_MODE1_DAC_DIF_MASK 0x07
70 #define CS4271_MODE1_DAC_DIF_LJ 0x00
71 #define CS4271_MODE1_DAC_DIF_I2S 0x01
72 #define CS4271_MODE1_DAC_DIF_RJ16 0x02
73 #define CS4271_MODE1_DAC_DIF_RJ24 0x03
74 #define CS4271_MODE1_DAC_DIF_RJ20 0x04
75 #define CS4271_MODE1_DAC_DIF_RJ18 0x05
77 #define CS4271_DACCTL_AMUTE 0x80
78 #define CS4271_DACCTL_IF_SLOW 0x40
80 #define CS4271_DACCTL_DEM_MASK 0x30
81 #define CS4271_DACCTL_DEM_DIS 0x00
82 #define CS4271_DACCTL_DEM_441 0x10
83 #define CS4271_DACCTL_DEM_48 0x20
84 #define CS4271_DACCTL_DEM_32 0x30
86 #define CS4271_DACCTL_SVRU 0x08
87 #define CS4271_DACCTL_SRD 0x04
88 #define CS4271_DACCTL_INVA 0x02
89 #define CS4271_DACCTL_INVB 0x01
91 #define CS4271_DACVOL_BEQUA 0x40
92 #define CS4271_DACVOL_SOFT 0x20
93 #define CS4271_DACVOL_ZEROC 0x10
95 #define CS4271_DACVOL_ATAPI_MASK 0x0F
96 #define CS4271_DACVOL_ATAPI_M_M 0x00
97 #define CS4271_DACVOL_ATAPI_M_BR 0x01
98 #define CS4271_DACVOL_ATAPI_M_BL 0x02
99 #define CS4271_DACVOL_ATAPI_M_BLR2 0x03
100 #define CS4271_DACVOL_ATAPI_AR_M 0x04
101 #define CS4271_DACVOL_ATAPI_AR_BR 0x05
102 #define CS4271_DACVOL_ATAPI_AR_BL 0x06
103 #define CS4271_DACVOL_ATAPI_AR_BLR2 0x07
104 #define CS4271_DACVOL_ATAPI_AL_M 0x08
105 #define CS4271_DACVOL_ATAPI_AL_BR 0x09
106 #define CS4271_DACVOL_ATAPI_AL_BL 0x0A
107 #define CS4271_DACVOL_ATAPI_AL_BLR2 0x0B
108 #define CS4271_DACVOL_ATAPI_ALR2_M 0x0C
109 #define CS4271_DACVOL_ATAPI_ALR2_BR 0x0D
110 #define CS4271_DACVOL_ATAPI_ALR2_BL 0x0E
111 #define CS4271_DACVOL_ATAPI_ALR2_BLR2 0x0F
113 #define CS4271_VOLA_MUTE 0x80
114 #define CS4271_VOLA_VOL_MASK 0x7F
115 #define CS4271_VOLB_MUTE 0x80
116 #define CS4271_VOLB_VOL_MASK 0x7F
118 #define CS4271_ADCCTL_DITHER16 0x20
120 #define CS4271_ADCCTL_ADC_DIF_MASK 0x10
121 #define CS4271_ADCCTL_ADC_DIF_LJ 0x00
122 #define CS4271_ADCCTL_ADC_DIF_I2S 0x10
124 #define CS4271_ADCCTL_MUTEA 0x08
125 #define CS4271_ADCCTL_MUTEB 0x04
126 #define CS4271_ADCCTL_HPFDA 0x02
127 #define CS4271_ADCCTL_HPFDB 0x01
129 #define CS4271_MODE2_LOOP 0x10
130 #define CS4271_MODE2_MUTECAEQUB 0x08
131 #define CS4271_MODE2_FREEZE 0x04
132 #define CS4271_MODE2_CPEN 0x02
133 #define CS4271_MODE2_PDN 0x01
135 #define CS4271_CHIPID_PART_MASK 0xF0
136 #define CS4271_CHIPID_REV_MASK 0x0F
139 * Default CS4271 power-up configuration
140 * Array contains non-existing in hw register at address 0
141 * Array do not include Chip ID, as codec driver does not use
142 * registers read operations at all
144 static const u8 cs4271_dflt_reg
[CS4271_NR_REGS
] = {
148 CS4271_DACVOL_SOFT
| CS4271_DACVOL_ATAPI_AL_BR
,
155 struct cs4271_private
{
156 /* SND_SOC_I2C or SND_SOC_SPI */
157 enum snd_soc_control_type bus_type
;
162 /* Current sample rate for de-emphasis control */
164 /* GPIO driving Reset pin, if any */
166 /* GPIO that disable serial bus, if any */
170 struct cs4271_clk_cfg
{
171 unsigned int ratio
; /* MCLK / sample rate */
172 u8 speed_mode
; /* codec speed mode: 1x, 2x, 4x */
173 u8 mclk_master
; /* ratio bit mask for Master mode */
174 u8 mclk_slave
; /* ratio bit mask for Slave mode */
177 static struct cs4271_clk_cfg cs4271_clk_tab
[] = {
178 {64, CS4271_MODE1_MODE_4X
, CS4271_MODE1_DIV_1
, CS4271_MODE1_DIV_1
},
179 {96, CS4271_MODE1_MODE_4X
, CS4271_MODE1_DIV_15
, CS4271_MODE1_DIV_1
},
180 {128, CS4271_MODE1_MODE_2X
, CS4271_MODE1_DIV_1
, CS4271_MODE1_DIV_1
},
181 {192, CS4271_MODE1_MODE_2X
, CS4271_MODE1_DIV_15
, CS4271_MODE1_DIV_1
},
182 {256, CS4271_MODE1_MODE_1X
, CS4271_MODE1_DIV_1
, CS4271_MODE1_DIV_1
},
183 {384, CS4271_MODE1_MODE_1X
, CS4271_MODE1_DIV_15
, CS4271_MODE1_DIV_1
},
184 {512, CS4271_MODE1_MODE_1X
, CS4271_MODE1_DIV_2
, CS4271_MODE1_DIV_1
},
185 {768, CS4271_MODE1_MODE_1X
, CS4271_MODE1_DIV_3
, CS4271_MODE1_DIV_3
},
186 {1024, CS4271_MODE1_MODE_1X
, CS4271_MODE1_DIV_3
, CS4271_MODE1_DIV_3
}
189 #define CS4171_NR_RATIOS ARRAY_SIZE(cs4271_clk_tab)
192 * @freq is the desired MCLK rate
193 * MCLK rate should (c) be the sample rate, multiplied by one of the
194 * ratios listed in cs4271_mclk_fs_ratios table
196 static int cs4271_set_dai_sysclk(struct snd_soc_dai
*codec_dai
,
197 int clk_id
, unsigned int freq
, int dir
)
199 struct snd_soc_codec
*codec
= codec_dai
->codec
;
200 struct cs4271_private
*cs4271
= snd_soc_codec_get_drvdata(codec
);
206 static int cs4271_set_dai_fmt(struct snd_soc_dai
*codec_dai
,
209 struct snd_soc_codec
*codec
= codec_dai
->codec
;
210 struct cs4271_private
*cs4271
= snd_soc_codec_get_drvdata(codec
);
211 unsigned int val
= 0;
214 switch (format
& SND_SOC_DAIFMT_MASTER_MASK
) {
215 case SND_SOC_DAIFMT_CBS_CFS
:
218 case SND_SOC_DAIFMT_CBM_CFM
:
220 val
|= CS4271_MODE1_MASTER
;
223 dev_err(codec
->dev
, "Invalid DAI format\n");
227 switch (format
& SND_SOC_DAIFMT_FORMAT_MASK
) {
228 case SND_SOC_DAIFMT_LEFT_J
:
229 val
|= CS4271_MODE1_DAC_DIF_LJ
;
230 ret
= snd_soc_update_bits(codec
, CS4271_ADCCTL
,
231 CS4271_ADCCTL_ADC_DIF_MASK
, CS4271_ADCCTL_ADC_DIF_LJ
);
235 case SND_SOC_DAIFMT_I2S
:
236 val
|= CS4271_MODE1_DAC_DIF_I2S
;
237 ret
= snd_soc_update_bits(codec
, CS4271_ADCCTL
,
238 CS4271_ADCCTL_ADC_DIF_MASK
, CS4271_ADCCTL_ADC_DIF_I2S
);
243 dev_err(codec
->dev
, "Invalid DAI format\n");
247 ret
= snd_soc_update_bits(codec
, CS4271_MODE1
,
248 CS4271_MODE1_DAC_DIF_MASK
| CS4271_MODE1_MASTER
, val
);
254 static int cs4271_deemph
[] = {0, 44100, 48000, 32000};
256 static int cs4271_set_deemph(struct snd_soc_codec
*codec
)
258 struct cs4271_private
*cs4271
= snd_soc_codec_get_drvdata(codec
);
260 int val
= CS4271_DACCTL_DEM_DIS
;
262 if (cs4271
->deemph
) {
263 /* Find closest de-emphasis freq */
265 for (i
= 2; i
< ARRAY_SIZE(cs4271_deemph
); i
++)
266 if (abs(cs4271_deemph
[i
] - cs4271
->rate
) <
267 abs(cs4271_deemph
[val
] - cs4271
->rate
))
272 ret
= snd_soc_update_bits(codec
, CS4271_DACCTL
,
273 CS4271_DACCTL_DEM_MASK
, val
);
279 static int cs4271_get_deemph(struct snd_kcontrol
*kcontrol
,
280 struct snd_ctl_elem_value
*ucontrol
)
282 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
283 struct cs4271_private
*cs4271
= snd_soc_codec_get_drvdata(codec
);
285 ucontrol
->value
.enumerated
.item
[0] = cs4271
->deemph
;
289 static int cs4271_put_deemph(struct snd_kcontrol
*kcontrol
,
290 struct snd_ctl_elem_value
*ucontrol
)
292 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
293 struct cs4271_private
*cs4271
= snd_soc_codec_get_drvdata(codec
);
295 cs4271
->deemph
= ucontrol
->value
.enumerated
.item
[0];
296 return cs4271_set_deemph(codec
);
299 static int cs4271_hw_params(struct snd_pcm_substream
*substream
,
300 struct snd_pcm_hw_params
*params
,
301 struct snd_soc_dai
*dai
)
303 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
304 struct snd_soc_codec
*codec
= rtd
->codec
;
305 struct cs4271_private
*cs4271
= snd_soc_codec_get_drvdata(codec
);
307 unsigned int ratio
, val
;
309 cs4271
->rate
= params_rate(params
);
310 ratio
= cs4271
->mclk
/ cs4271
->rate
;
311 for (i
= 0; i
< CS4171_NR_RATIOS
; i
++)
312 if (cs4271_clk_tab
[i
].ratio
== ratio
)
315 if ((i
== CS4171_NR_RATIOS
) || ((ratio
== 1024) && cs4271
->master
)) {
316 dev_err(codec
->dev
, "Invalid sample rate\n");
321 val
= cs4271_clk_tab
[i
].speed_mode
;
324 val
|= cs4271_clk_tab
[i
].mclk_master
;
326 val
|= cs4271_clk_tab
[i
].mclk_slave
;
328 ret
= snd_soc_update_bits(codec
, CS4271_MODE1
,
329 CS4271_MODE1_MODE_MASK
| CS4271_MODE1_DIV_MASK
, val
);
333 return cs4271_set_deemph(codec
);
336 static int cs4271_digital_mute(struct snd_soc_dai
*dai
, int mute
)
338 struct snd_soc_codec
*codec
= dai
->codec
;
344 val_a
= CS4271_VOLA_MUTE
;
345 val_b
= CS4271_VOLB_MUTE
;
348 ret
= snd_soc_update_bits(codec
, CS4271_VOLA
, CS4271_VOLA_MUTE
, val_a
);
351 ret
= snd_soc_update_bits(codec
, CS4271_VOLB
, CS4271_VOLB_MUTE
, val_b
);
358 /* CS4271 controls */
359 static DECLARE_TLV_DB_SCALE(cs4271_dac_tlv
, -12700, 100, 0);
361 static const struct snd_kcontrol_new cs4271_snd_controls
[] = {
362 SOC_DOUBLE_R_TLV("Master Playback Volume", CS4271_VOLA
, CS4271_VOLB
,
363 0, 0x7F, 1, cs4271_dac_tlv
),
364 SOC_SINGLE("Digital Loopback Switch", CS4271_MODE2
, 4, 1, 0),
365 SOC_SINGLE("Soft Ramp Switch", CS4271_DACVOL
, 5, 1, 0),
366 SOC_SINGLE("Zero Cross Switch", CS4271_DACVOL
, 4, 1, 0),
367 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
368 cs4271_get_deemph
, cs4271_put_deemph
),
369 SOC_SINGLE("Auto-Mute Switch", CS4271_DACCTL
, 7, 1, 0),
370 SOC_SINGLE("Slow Roll Off Filter Switch", CS4271_DACCTL
, 6, 1, 0),
371 SOC_SINGLE("Soft Volume Ramp-Up Switch", CS4271_DACCTL
, 3, 1, 0),
372 SOC_SINGLE("Soft Ramp-Down Switch", CS4271_DACCTL
, 2, 1, 0),
373 SOC_SINGLE("Left Channel Inversion Switch", CS4271_DACCTL
, 1, 1, 0),
374 SOC_SINGLE("Right Channel Inversion Switch", CS4271_DACCTL
, 0, 1, 0),
375 SOC_DOUBLE("Master Capture Switch", CS4271_ADCCTL
, 3, 2, 1, 1),
376 SOC_SINGLE("Dither 16-Bit Data Switch", CS4271_ADCCTL
, 5, 1, 0),
377 SOC_DOUBLE("High Pass Filter Switch", CS4271_ADCCTL
, 1, 0, 1, 1),
378 SOC_DOUBLE_R("Master Playback Switch", CS4271_VOLA
, CS4271_VOLB
,
382 static struct snd_soc_dai_ops cs4271_dai_ops
= {
383 .hw_params
= cs4271_hw_params
,
384 .set_sysclk
= cs4271_set_dai_sysclk
,
385 .set_fmt
= cs4271_set_dai_fmt
,
386 .digital_mute
= cs4271_digital_mute
,
389 static struct snd_soc_dai_driver cs4271_dai
= {
390 .name
= "cs4271-hifi",
392 .stream_name
= "Playback",
395 .rates
= SNDRV_PCM_RATE_8000_96000
,
396 .formats
= CS4271_PCM_FORMATS
,
399 .stream_name
= "Capture",
402 .rates
= SNDRV_PCM_RATE_8000_96000
,
403 .formats
= CS4271_PCM_FORMATS
,
405 .ops
= &cs4271_dai_ops
,
406 .symmetric_rates
= 1,
410 static int cs4271_soc_suspend(struct snd_soc_codec
*codec
, pm_message_t mesg
)
413 /* Set power-down bit */
414 ret
= snd_soc_update_bits(codec
, CS4271_MODE2
, 0, CS4271_MODE2_PDN
);
420 static int cs4271_soc_resume(struct snd_soc_codec
*codec
)
423 /* Restore codec state */
424 ret
= snd_soc_cache_sync(codec
);
427 /* then disable the power-down bit */
428 ret
= snd_soc_update_bits(codec
, CS4271_MODE2
, CS4271_MODE2_PDN
, 0);
434 #define cs4271_soc_suspend NULL
435 #define cs4271_soc_resume NULL
436 #endif /* CONFIG_PM */
438 static int cs4271_probe(struct snd_soc_codec
*codec
)
440 struct cs4271_private
*cs4271
= snd_soc_codec_get_drvdata(codec
);
441 struct cs4271_platform_data
*cs4271plat
= codec
->dev
->platform_data
;
443 int gpio_nreset
= -EINVAL
;
444 int gpio_disable
= -EINVAL
;
446 codec
->control_data
= cs4271
->control_data
;
449 if (gpio_is_valid(cs4271plat
->gpio_nreset
))
450 gpio_nreset
= cs4271plat
->gpio_nreset
;
451 if (gpio_is_valid(cs4271plat
->gpio_disable
))
452 gpio_disable
= cs4271plat
->gpio_disable
;
455 if (gpio_disable
>= 0)
456 if (gpio_request(gpio_disable
, "CS4271 Disable"))
457 gpio_disable
= -EINVAL
;
458 if (gpio_disable
>= 0)
459 gpio_direction_output(gpio_disable
, 0);
461 if (gpio_nreset
>= 0)
462 if (gpio_request(gpio_nreset
, "CS4271 Reset"))
463 gpio_nreset
= -EINVAL
;
464 if (gpio_nreset
>= 0) {
466 gpio_direction_output(gpio_nreset
, 0);
468 gpio_set_value(gpio_nreset
, 1);
469 /* Give the codec time to wake up */
473 cs4271
->gpio_nreset
= gpio_nreset
;
474 cs4271
->gpio_disable
= gpio_disable
;
477 * In case of I2C, chip address specified in board data.
478 * So cache IO operations use 8 bit codec register address.
479 * In case of SPI, chip address and register address
480 * passed together as 16 bit value.
481 * Anyway, register address is masked with 0xFF inside
484 if (cs4271
->bus_type
== SND_SOC_SPI
)
485 ret
= snd_soc_codec_set_cache_io(codec
, 16, 8,
488 ret
= snd_soc_codec_set_cache_io(codec
, 8, 8,
491 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
495 ret
= snd_soc_update_bits(codec
, CS4271_MODE2
, 0,
496 CS4271_MODE2_PDN
| CS4271_MODE2_CPEN
);
499 ret
= snd_soc_update_bits(codec
, CS4271_MODE2
, CS4271_MODE2_PDN
, 0);
502 /* Power-up sequence requires 85 uS */
505 return snd_soc_add_controls(codec
, cs4271_snd_controls
,
506 ARRAY_SIZE(cs4271_snd_controls
));
509 static int cs4271_remove(struct snd_soc_codec
*codec
)
511 struct cs4271_private
*cs4271
= snd_soc_codec_get_drvdata(codec
);
512 int gpio_nreset
, gpio_disable
;
514 gpio_nreset
= cs4271
->gpio_nreset
;
515 gpio_disable
= cs4271
->gpio_disable
;
517 if (gpio_is_valid(gpio_nreset
)) {
518 /* Set codec to the reset state */
519 gpio_set_value(gpio_nreset
, 0);
520 gpio_free(gpio_nreset
);
523 if (gpio_is_valid(gpio_disable
))
524 gpio_free(gpio_disable
);
529 static struct snd_soc_codec_driver soc_codec_dev_cs4271
= {
530 .probe
= cs4271_probe
,
531 .remove
= cs4271_remove
,
532 .suspend
= cs4271_soc_suspend
,
533 .resume
= cs4271_soc_resume
,
534 .reg_cache_default
= cs4271_dflt_reg
,
535 .reg_cache_size
= ARRAY_SIZE(cs4271_dflt_reg
),
536 .reg_word_size
= sizeof(cs4271_dflt_reg
[0]),
537 .compress_type
= SND_SOC_FLAT_COMPRESSION
,
540 #if defined(CONFIG_SPI_MASTER)
541 static int __devinit
cs4271_spi_probe(struct spi_device
*spi
)
543 struct cs4271_private
*cs4271
;
545 cs4271
= devm_kzalloc(&spi
->dev
, sizeof(*cs4271
), GFP_KERNEL
);
549 spi_set_drvdata(spi
, cs4271
);
550 cs4271
->control_data
= spi
;
551 cs4271
->bus_type
= SND_SOC_SPI
;
553 return snd_soc_register_codec(&spi
->dev
, &soc_codec_dev_cs4271
,
557 static int __devexit
cs4271_spi_remove(struct spi_device
*spi
)
559 snd_soc_unregister_codec(&spi
->dev
);
563 static struct spi_driver cs4271_spi_driver
= {
566 .owner
= THIS_MODULE
,
568 .probe
= cs4271_spi_probe
,
569 .remove
= __devexit_p(cs4271_spi_remove
),
571 #endif /* defined(CONFIG_SPI_MASTER) */
573 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
574 static struct i2c_device_id cs4271_i2c_id
[] = {
578 MODULE_DEVICE_TABLE(i2c
, cs4271_i2c_id
);
580 static int __devinit
cs4271_i2c_probe(struct i2c_client
*client
,
581 const struct i2c_device_id
*id
)
583 struct cs4271_private
*cs4271
;
585 cs4271
= devm_kzalloc(&client
->dev
, sizeof(*cs4271
), GFP_KERNEL
);
589 i2c_set_clientdata(client
, cs4271
);
590 cs4271
->control_data
= client
;
591 cs4271
->bus_type
= SND_SOC_I2C
;
593 return snd_soc_register_codec(&client
->dev
, &soc_codec_dev_cs4271
,
597 static int __devexit
cs4271_i2c_remove(struct i2c_client
*client
)
599 snd_soc_unregister_codec(&client
->dev
);
603 static struct i2c_driver cs4271_i2c_driver
= {
606 .owner
= THIS_MODULE
,
608 .id_table
= cs4271_i2c_id
,
609 .probe
= cs4271_i2c_probe
,
610 .remove
= __devexit_p(cs4271_i2c_remove
),
612 #endif /* defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) */
615 * We only register our serial bus driver here without
616 * assignment to particular chip. So if any of the below
617 * fails, there is some problem with I2C or SPI subsystem.
618 * In most cases this module will be compiled with support
619 * of only one serial bus.
621 static int __init
cs4271_modinit(void)
625 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
626 ret
= i2c_add_driver(&cs4271_i2c_driver
);
628 pr_err("Failed to register CS4271 I2C driver: %d\n", ret
);
633 #if defined(CONFIG_SPI_MASTER)
634 ret
= spi_register_driver(&cs4271_spi_driver
);
636 pr_err("Failed to register CS4271 SPI driver: %d\n", ret
);
643 module_init(cs4271_modinit
);
645 static void __exit
cs4271_modexit(void)
647 #if defined(CONFIG_SPI_MASTER)
648 spi_unregister_driver(&cs4271_spi_driver
);
651 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
652 i2c_del_driver(&cs4271_i2c_driver
);
655 module_exit(cs4271_modexit
);
657 MODULE_AUTHOR("Alexander Sverdlin <subaparts@yandex.ru>");
658 MODULE_DESCRIPTION("Cirrus Logic CS4271 ALSA SoC Codec Driver");
659 MODULE_LICENSE("GPL");